aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ide/aec62xx.c13
-rw-r--r--drivers/ide/ali14xx.c3
-rw-r--r--drivers/ide/alim15x3.c171
-rw-r--r--drivers/ide/amd74xx.c18
-rw-r--r--drivers/ide/at91_ide.c5
-rw-r--r--drivers/ide/atiixp.c14
-rw-r--r--drivers/ide/au1xxx-ide.c13
-rw-r--r--drivers/ide/cmd640.c5
-rw-r--r--drivers/ide/cmd64x.c114
-rw-r--r--drivers/ide/cs5520.c9
-rw-r--r--drivers/ide/cs5530.c13
-rw-r--r--drivers/ide/cs5535.c14
-rw-r--r--drivers/ide/cs5536.c16
-rw-r--r--drivers/ide/cy82c693.c146
-rw-r--r--drivers/ide/dtc2278.c4
-rw-r--r--drivers/ide/hpt366.c9
-rw-r--r--drivers/ide/ht6560b.c3
-rw-r--r--drivers/ide/icside.c67
-rw-r--r--drivers/ide/ide-cs.c23
-rw-r--r--drivers/ide/ide-devsets.c6
-rw-r--r--drivers/ide/ide-iops.c2
-rw-r--r--drivers/ide/ide-probe.c2
-rw-r--r--drivers/ide/ide-tape.c14
-rw-r--r--drivers/ide/ide-timings.c18
-rw-r--r--drivers/ide/ide-xfer-mode.c18
-rw-r--r--drivers/ide/it8172.c14
-rw-r--r--drivers/ide/it8213.c20
-rw-r--r--drivers/ide/it821x.c14
-rw-r--r--drivers/ide/jmicron.c6
-rw-r--r--drivers/ide/opti621.c77
-rw-r--r--drivers/ide/palm_bk3710.c12
-rw-r--r--drivers/ide/pdc202xx_new.c8
-rw-r--r--drivers/ide/pdc202xx_old.c31
-rw-r--r--drivers/ide/piix.c20
-rw-r--r--drivers/ide/pmac.c13
-rw-r--r--drivers/ide/qd65xx.c10
-rw-r--r--drivers/ide/sc1200.c8
-rw-r--r--drivers/ide/scc_pata.c24
-rw-r--r--drivers/ide/serverworks.c50
-rw-r--r--drivers/ide/sgiioc4.c2
-rw-r--r--drivers/ide/siimage.c14
-rw-r--r--drivers/ide/sis5513.c8
-rw-r--r--drivers/ide/sl82c105.c8
-rw-r--r--drivers/ide/slc90e66.c17
-rw-r--r--drivers/ide/tc86c001.c9
-rw-r--r--drivers/ide/triflex.c10
-rw-r--r--drivers/ide/tx4938ide.c7
-rw-r--r--drivers/ide/tx4939ide.c10
-rw-r--r--drivers/ide/umc8672.c5
-rw-r--r--drivers/ide/via82cxxx.c132
50 files changed, 611 insertions, 638 deletions
diff --git a/drivers/ide/aec62xx.c b/drivers/ide/aec62xx.c
index 878f8ec6dbe1..57d00caefc86 100644
--- a/drivers/ide/aec62xx.c
+++ b/drivers/ide/aec62xx.c
@@ -81,15 +81,15 @@ static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entr
81 return chipset_table->ultra_settings; 81 return chipset_table->ultra_settings;
82} 82}
83 83
84static void aec6210_set_mode(ide_drive_t *drive, const u8 speed) 84static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85{ 85{
86 ide_hwif_t *hwif = drive->hwif;
87 struct pci_dev *dev = to_pci_dev(hwif->dev); 86 struct pci_dev *dev = to_pci_dev(hwif->dev);
88 struct ide_host *host = pci_get_drvdata(dev); 87 struct ide_host *host = pci_get_drvdata(dev);
89 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv; 88 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
90 u16 d_conf = 0; 89 u16 d_conf = 0;
91 u8 ultra = 0, ultra_conf = 0; 90 u8 ultra = 0, ultra_conf = 0;
92 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0; 91 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
92 const u8 speed = drive->dma_mode;
93 unsigned long flags; 93 unsigned long flags;
94 94
95 local_irq_save(flags); 95 local_irq_save(flags);
@@ -109,15 +109,15 @@ static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
109 local_irq_restore(flags); 109 local_irq_restore(flags);
110} 110}
111 111
112static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) 112static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
113{ 113{
114 ide_hwif_t *hwif = drive->hwif;
115 struct pci_dev *dev = to_pci_dev(hwif->dev); 114 struct pci_dev *dev = to_pci_dev(hwif->dev);
116 struct ide_host *host = pci_get_drvdata(dev); 115 struct ide_host *host = pci_get_drvdata(dev);
117 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv; 116 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
118 u8 unit = drive->dn & 1; 117 u8 unit = drive->dn & 1;
119 u8 tmp1 = 0, tmp2 = 0; 118 u8 tmp1 = 0, tmp2 = 0;
120 u8 ultra = 0, drive_conf = 0, ultra_conf = 0; 119 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
120 const u8 speed = drive->dma_mode;
121 unsigned long flags; 121 unsigned long flags;
122 122
123 local_irq_save(flags); 123 local_irq_save(flags);
@@ -134,9 +134,10 @@ static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
134 local_irq_restore(flags); 134 local_irq_restore(flags);
135} 135}
136 136
137static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio) 137static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
138{ 138{
139 drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0); 139 drive->dma_mode = drive->pio_mode;
140 hwif->port_ops->set_dma_mode(hwif, drive);
140} 141}
141 142
142static int init_chipset_aec62xx(struct pci_dev *dev) 143static int init_chipset_aec62xx(struct pci_dev *dev)
diff --git a/drivers/ide/ali14xx.c b/drivers/ide/ali14xx.c
index 90da1f953ed0..25b9fe3a9f8e 100644
--- a/drivers/ide/ali14xx.c
+++ b/drivers/ide/ali14xx.c
@@ -109,13 +109,14 @@ static DEFINE_SPINLOCK(ali14xx_lock);
109 * This function computes timing parameters 109 * This function computes timing parameters
110 * and sets controller registers accordingly. 110 * and sets controller registers accordingly.
111 */ 111 */
112static void ali14xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 112static void ali14xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
113{ 113{
114 int driveNum; 114 int driveNum;
115 int time1, time2; 115 int time1, time2;
116 u8 param1, param2, param3, param4; 116 u8 param1, param2, param3, param4;
117 unsigned long flags; 117 unsigned long flags;
118 int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50; 118 int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
119 const u8 pio = drive->pio_mode - XFER_PIO_0;
119 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
120 121
121 /* calculate timing, according to PIO mode */ 122 /* calculate timing, according to PIO mode */
diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c
index 0abc43f3101e..2c8016ad0e26 100644
--- a/drivers/ide/alim15x3.c
+++ b/drivers/ide/alim15x3.c
@@ -8,7 +8,7 @@
8 * Copyright (C) 2002 Alan Cox 8 * Copyright (C) 2002 Alan Cox
9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw> 9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 11 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
12 * 12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D) 13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 * 14 *
@@ -48,61 +48,84 @@ static u8 m5229_revision;
48static u8 chip_is_1543c_e; 48static u8 chip_is_1543c_e;
49static struct pci_dev *isa_dev; 49static struct pci_dev *isa_dev;
50 50
51static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
52{
53 struct pci_dev *pdev = to_pci_dev(hwif->dev);
54 int pio_fifo = 0x54 + hwif->channel;
55 u8 fifo;
56 int shift = 4 * (drive->dn & 1);
57
58 pci_read_config_byte(pdev, pio_fifo, &fifo);
59 fifo &= ~(0x0F << shift);
60 fifo |= (on << shift);
61 pci_write_config_byte(pdev, pio_fifo, fifo);
62}
63
64static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive,
65 struct ide_timing *t, u8 ultra)
66{
67 struct pci_dev *dev = to_pci_dev(hwif->dev);
68 int port = hwif->channel ? 0x5c : 0x58;
69 int udmat = 0x56 + hwif->channel;
70 u8 unit = drive->dn & 1, udma;
71 int shift = 4 * unit;
72
73 /* Set up the UDMA */
74 pci_read_config_byte(dev, udmat, &udma);
75 udma &= ~(0x0F << shift);
76 udma |= ultra << shift;
77 pci_write_config_byte(dev, udmat, udma);
78
79 if (t == NULL)
80 return;
81
82 t->setup = clamp_val(t->setup, 1, 8) & 7;
83 t->act8b = clamp_val(t->act8b, 1, 8) & 7;
84 t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
85 t->active = clamp_val(t->active, 1, 8) & 7;
86 t->recover = clamp_val(t->recover, 1, 16) & 15;
87
88 pci_write_config_byte(dev, port, t->setup);
89 pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b);
90 pci_write_config_byte(dev, port + unit + 2,
91 (t->active << 4) | t->recover);
92}
93
51/** 94/**
52 * ali_set_pio_mode - set host controller for PIO mode 95 * ali_set_pio_mode - set host controller for PIO mode
96 * @hwif: port
53 * @drive: drive 97 * @drive: drive
54 * @pio: PIO mode number
55 * 98 *
56 * Program the controller for the given PIO mode. 99 * Program the controller for the given PIO mode.
57 */ 100 */
58 101
59static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) 102static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
60{ 103{
61 ide_hwif_t *hwif = drive->hwif; 104 ide_drive_t *pair = ide_get_pair_dev(drive);
62 struct pci_dev *dev = to_pci_dev(hwif->dev);
63 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
64 int s_time = t->setup, a_time = t->active, c_time = t->cycle;
65 u8 s_clc, a_clc, r_clc;
66 unsigned long flags;
67 int bus_speed = ide_pci_clk ? ide_pci_clk : 33; 105 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
68 int port = hwif->channel ? 0x5c : 0x58; 106 unsigned long T = 1000000 / bus_speed; /* PCI clock based */
69 int portFIFO = hwif->channel ? 0x55 : 0x54; 107 struct ide_timing t;
70 u8 cd_dma_fifo = 0, unit = drive->dn & 1; 108
71 109 ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
72 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8) 110 if (pair) {
73 s_clc = 0; 111 struct ide_timing p;
74 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8) 112
75 a_clc = 0; 113 ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
76 114 ide_timing_merge(&p, &t, &t,
77 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) { 115 IDE_TIMING_SETUP | IDE_TIMING_8BIT);
78 r_clc = 1; 116 if (pair->dma_mode) {
79 } else { 117 ide_timing_compute(pair, pair->dma_mode, &p, T, 1);
80 if (r_clc >= 16) 118 ide_timing_merge(&p, &t, &t,
81 r_clc = 0; 119 IDE_TIMING_SETUP | IDE_TIMING_8BIT);
120 }
82 } 121 }
83 local_irq_save(flags); 122
84
85 /* 123 /*
86 * PIO mode => ATA FIFO on, ATAPI FIFO off 124 * PIO mode => ATA FIFO on, ATAPI FIFO off
87 */ 125 */
88 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo); 126 ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00);
89 if (drive->media==ide_disk) { 127
90 if (unit) { 128 ali_program_timings(hwif, drive, &t, 0);
91 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
92 } else {
93 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
94 }
95 } else {
96 if (unit) {
97 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
98 } else {
99 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
100 }
101 }
102
103 pci_write_config_byte(dev, port, s_clc);
104 pci_write_config_byte(dev, port + unit + 2, (a_clc << 4) | r_clc);
105 local_irq_restore(flags);
106} 129}
107 130
108/** 131/**
@@ -132,44 +155,42 @@ static u8 ali_udma_filter(ide_drive_t *drive)
132 155
133/** 156/**
134 * ali_set_dma_mode - set host controller for DMA mode 157 * ali_set_dma_mode - set host controller for DMA mode
158 * @hwif: port
135 * @drive: drive 159 * @drive: drive
136 * @speed: DMA mode
137 * 160 *
138 * Configure the hardware for the desired IDE transfer mode. 161 * Configure the hardware for the desired IDE transfer mode.
139 */ 162 */
140 163
141static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed) 164static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
142{ 165{
143 ide_hwif_t *hwif = drive->hwif; 166 static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
144 struct pci_dev *dev = to_pci_dev(hwif->dev); 167 struct pci_dev *dev = to_pci_dev(hwif->dev);
145 u8 speed1 = speed; 168 ide_drive_t *pair = ide_get_pair_dev(drive);
146 u8 unit = drive->dn & 1; 169 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
170 unsigned long T = 1000000 / bus_speed; /* PCI clock based */
171 const u8 speed = drive->dma_mode;
147 u8 tmpbyte = 0x00; 172 u8 tmpbyte = 0x00;
148 int m5229_udma = (hwif->channel) ? 0x57 : 0x56; 173 struct ide_timing t;
149
150 if (speed == XFER_UDMA_6)
151 speed1 = 0x47;
152 174
153 if (speed < XFER_UDMA_0) { 175 if (speed < XFER_UDMA_0) {
154 u8 ultra_enable = (unit) ? 0x7f : 0xf7; 176 ide_timing_compute(drive, drive->dma_mode, &t, T, 1);
155 /* 177 if (pair) {
156 * clear "ultra enable" bit 178 struct ide_timing p;
157 */ 179
158 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 180 ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
159 tmpbyte &= ultra_enable; 181 ide_timing_merge(&p, &t, &t,
160 pci_write_config_byte(dev, m5229_udma, tmpbyte); 182 IDE_TIMING_SETUP | IDE_TIMING_8BIT);
161 183 if (pair->dma_mode) {
162 /* 184 ide_timing_compute(pair, pair->dma_mode,
163 * FIXME: Oh, my... DMA timings are never set. 185 &p, T, 1);
164 */ 186 ide_timing_merge(&p, &t, &t,
187 IDE_TIMING_SETUP | IDE_TIMING_8BIT);
188 }
189 }
190 ali_program_timings(hwif, drive, &t, 0);
165 } else { 191 } else {
166 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 192 ali_program_timings(hwif, drive, NULL,
167 tmpbyte &= (0x0f << ((1-unit) << 2)); 193 udma_timing[speed - XFER_UDMA_0]);
168 /*
169 * enable ultra dma and set timing
170 */
171 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
172 pci_write_config_byte(dev, m5229_udma, tmpbyte);
173 if (speed >= XFER_UDMA_3) { 194 if (speed >= XFER_UDMA_3) {
174 pci_read_config_byte(dev, 0x4b, &tmpbyte); 195 pci_read_config_byte(dev, 0x4b, &tmpbyte);
175 tmpbyte |= 1; 196 tmpbyte |= 1;
@@ -355,19 +376,13 @@ static int ali_cable_override(struct pci_dev *pdev)
355 * 376 *
356 * This checks if the controller and the cable are capable 377 * This checks if the controller and the cable are capable
357 * of UDMA66 transfers. It doesn't check the drives. 378 * of UDMA66 transfers. It doesn't check the drives.
358 * But see note 2 below!
359 *
360 * FIXME: frobs bits that are not defined on newer ALi devicea
361 */ 379 */
362 380
363static u8 ali_cable_detect(ide_hwif_t *hwif) 381static u8 ali_cable_detect(ide_hwif_t *hwif)
364{ 382{
365 struct pci_dev *dev = to_pci_dev(hwif->dev); 383 struct pci_dev *dev = to_pci_dev(hwif->dev);
366 unsigned long flags;
367 u8 cbl = ATA_CBL_PATA40, tmpbyte; 384 u8 cbl = ATA_CBL_PATA40, tmpbyte;
368 385
369 local_irq_save(flags);
370
371 if (m5229_revision >= 0xC2) { 386 if (m5229_revision >= 0xC2) {
372 /* 387 /*
373 * m5229 80-pin cable detection (from Host View) 388 * m5229 80-pin cable detection (from Host View)
@@ -387,8 +402,6 @@ static u8 ali_cable_detect(ide_hwif_t *hwif)
387 } 402 }
388 } 403 }
389 404
390 local_irq_restore(flags);
391
392 return cbl; 405 return cbl;
393} 406}
394 407
@@ -584,6 +597,6 @@ static void __exit ali15x3_ide_exit(void)
584module_init(ali15x3_ide_init); 597module_init(ali15x3_ide_init);
585module_exit(ali15x3_ide_exit); 598module_exit(ali15x3_ide_exit);
586 599
587MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox"); 600MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz");
588MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE"); 601MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
589MODULE_LICENSE("GPL"); 602MODULE_LICENSE("GPL");
diff --git a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c
index 628cd2e5fed8..3747b2561f09 100644
--- a/drivers/ide/amd74xx.c
+++ b/drivers/ide/amd74xx.c
@@ -3,7 +3,7 @@
3 * IDE driver for Linux. 3 * IDE driver for Linux.
4 * 4 *
5 * Copyright (c) 2000-2002 Vojtech Pavlik 5 * Copyright (c) 2000-2002 Vojtech Pavlik
6 * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz 6 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
7 * 7 *
8 * Based on the work of: 8 * Based on the work of:
9 * Andre Hedrick 9 * Andre Hedrick
@@ -70,7 +70,8 @@ static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
70 default: return; 70 default: return;
71 } 71 }
72 72
73 pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t); 73 if (timing->udma)
74 pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t);
74} 75}
75 76
76/* 77/*
@@ -78,14 +79,14 @@ static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
78 * to a desired transfer mode. It also can be called by upper layers. 79 * to a desired transfer mode. It also can be called by upper layers.
79 */ 80 */
80 81
81static void amd_set_drive(ide_drive_t *drive, const u8 speed) 82static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
82{ 83{
83 ide_hwif_t *hwif = drive->hwif;
84 struct pci_dev *dev = to_pci_dev(hwif->dev); 84 struct pci_dev *dev = to_pci_dev(hwif->dev);
85 ide_drive_t *peer = ide_get_pair_dev(drive); 85 ide_drive_t *peer = ide_get_pair_dev(drive);
86 struct ide_timing t, p; 86 struct ide_timing t, p;
87 int T, UT; 87 int T, UT;
88 u8 udma_mask = hwif->ultra_mask; 88 u8 udma_mask = hwif->ultra_mask;
89 const u8 speed = drive->dma_mode;
89 90
90 T = 1000000000 / amd_clock; 91 T = 1000000000 / amd_clock;
91 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2); 92 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
@@ -93,7 +94,7 @@ static void amd_set_drive(ide_drive_t *drive, const u8 speed)
93 ide_timing_compute(drive, speed, &t, T, UT); 94 ide_timing_compute(drive, speed, &t, T, UT);
94 95
95 if (peer) { 96 if (peer) {
96 ide_timing_compute(peer, peer->current_speed, &p, T, UT); 97 ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
97 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); 98 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
98 } 99 }
99 100
@@ -107,9 +108,10 @@ static void amd_set_drive(ide_drive_t *drive, const u8 speed)
107 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning. 108 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
108 */ 109 */
109 110
110static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio) 111static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
111{ 112{
112 amd_set_drive(drive, XFER_PIO_0 + pio); 113 drive->dma_mode = drive->pio_mode;
114 amd_set_drive(hwif, drive);
113} 115}
114 116
115static void amd7409_cable_detect(struct pci_dev *dev) 117static void amd7409_cable_detect(struct pci_dev *dev)
@@ -340,6 +342,6 @@ static void __exit amd74xx_ide_exit(void)
340module_init(amd74xx_ide_init); 342module_init(amd74xx_ide_init);
341module_exit(amd74xx_ide_exit); 343module_exit(amd74xx_ide_exit);
342 344
343MODULE_AUTHOR("Vojtech Pavlik"); 345MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz");
344MODULE_DESCRIPTION("AMD PCI IDE driver"); 346MODULE_DESCRIPTION("AMD PCI IDE driver");
345MODULE_LICENSE("GPL"); 347MODULE_LICENSE("GPL");
diff --git a/drivers/ide/at91_ide.c b/drivers/ide/at91_ide.c
index 248219a89a68..000a78e5246c 100644
--- a/drivers/ide/at91_ide.c
+++ b/drivers/ide/at91_ide.c
@@ -172,11 +172,12 @@ static void at91_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
172 leave_16bit(chipselect, mode); 172 leave_16bit(chipselect, mode);
173} 173}
174 174
175static void at91_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) 175static void at91_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
176{ 176{
177 struct ide_timing *timing; 177 struct ide_timing *timing;
178 u8 chipselect = drive->hwif->select_data; 178 u8 chipselect = hwif->select_data;
179 int use_iordy = 0; 179 int use_iordy = 0;
180 const u8 pio = drive->pio_mode - XFER_PIO_0;
180 181
181 pdbg("chipselect %u pio %u\n", chipselect, pio); 182 pdbg("chipselect %u pio %u\n", chipselect, pio);
182 183
diff --git a/drivers/ide/atiixp.c b/drivers/ide/atiixp.c
index 837322b10a4c..15f0ead89f5c 100644
--- a/drivers/ide/atiixp.c
+++ b/drivers/ide/atiixp.c
@@ -42,19 +42,20 @@ static DEFINE_SPINLOCK(atiixp_lock);
42 42
43/** 43/**
44 * atiixp_set_pio_mode - set host controller for PIO mode 44 * atiixp_set_pio_mode - set host controller for PIO mode
45 * @hwif: port
45 * @drive: drive 46 * @drive: drive
46 * @pio: PIO mode number
47 * 47 *
48 * Set the interface PIO mode. 48 * Set the interface PIO mode.
49 */ 49 */
50 50
51static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio) 51static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
52{ 52{
53 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 53 struct pci_dev *dev = to_pci_dev(hwif->dev);
54 unsigned long flags; 54 unsigned long flags;
55 int timing_shift = (drive->dn ^ 1) * 8; 55 int timing_shift = (drive->dn ^ 1) * 8;
56 u32 pio_timing_data; 56 u32 pio_timing_data;
57 u16 pio_mode_data; 57 u16 pio_mode_data;
58 const u8 pio = drive->pio_mode - XFER_PIO_0;
58 59
59 spin_lock_irqsave(&atiixp_lock, flags); 60 spin_lock_irqsave(&atiixp_lock, flags);
60 61
@@ -74,21 +75,22 @@ static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
74 75
75/** 76/**
76 * atiixp_set_dma_mode - set host controller for DMA mode 77 * atiixp_set_dma_mode - set host controller for DMA mode
78 * @hwif: port
77 * @drive: drive 79 * @drive: drive
78 * @speed: DMA mode
79 * 80 *
80 * Set a ATIIXP host controller to the desired DMA mode. This involves 81 * Set a ATIIXP host controller to the desired DMA mode. This involves
81 * programming the right timing data into the PCI configuration space. 82 * programming the right timing data into the PCI configuration space.
82 */ 83 */
83 84
84static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed) 85static void atiixp_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85{ 86{
86 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 87 struct pci_dev *dev = to_pci_dev(hwif->dev);
87 unsigned long flags; 88 unsigned long flags;
88 int timing_shift = (drive->dn ^ 1) * 8; 89 int timing_shift = (drive->dn ^ 1) * 8;
89 u32 tmp32; 90 u32 tmp32;
90 u16 tmp16; 91 u16 tmp16;
91 u16 udma_ctl = 0; 92 u16 udma_ctl = 0;
93 const u8 speed = drive->dma_mode;
92 94
93 spin_lock_irqsave(&atiixp_lock, flags); 95 spin_lock_irqsave(&atiixp_lock, flags);
94 96
diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c
index 349a67bf1a36..b26c23416fa7 100644
--- a/drivers/ide/au1xxx-ide.c
+++ b/drivers/ide/au1xxx-ide.c
@@ -99,12 +99,11 @@ static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
99} 99}
100#endif 100#endif
101 101
102static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) 102static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
103{ 103{
104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); 104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105 105
106 /* set pio mode! */ 106 switch (drive->pio_mode - XFER_PIO_0) {
107 switch(pio) {
108 case 0: 107 case 0:
109 mem_sttime = SBC_IDE_TIMING(PIO0); 108 mem_sttime = SBC_IDE_TIMING(PIO0);
110 109
@@ -161,11 +160,11 @@ static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
161 au_writel(mem_stcfg,MEM_STCFG2); 160 au_writel(mem_stcfg,MEM_STCFG2);
162} 161}
163 162
164static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) 163static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
165{ 164{
166 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); 165 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167 166
168 switch(speed) { 167 switch (drive->dma_mode) {
169#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 168#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170 case XFER_MW_DMA_2: 169 case XFER_MW_DMA_2:
171 mem_sttime = SBC_IDE_TIMING(MDMA2); 170 mem_sttime = SBC_IDE_TIMING(MDMA2);
@@ -297,8 +296,8 @@ static int auide_dma_test_irq(ide_drive_t *drive)
297 */ 296 */
298 drive->waiting_for_dma++; 297 drive->waiting_for_dma++;
299 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { 298 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
300 printk(KERN_WARNING "%s: timeout waiting for ddma to \ 299 printk(KERN_WARNING "%s: timeout waiting for ddma to complete\n",
301 complete\n", drive->name); 300 drive->name);
302 return 1; 301 return 1;
303 } 302 }
304 udelay(10); 303 udelay(10);
diff --git a/drivers/ide/cmd640.c b/drivers/ide/cmd640.c
index 1a32d62ed86b..d2b8b272bc27 100644
--- a/drivers/ide/cmd640.c
+++ b/drivers/ide/cmd640.c
@@ -572,9 +572,10 @@ static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
572 program_drive_counts(drive, index); 572 program_drive_counts(drive, index);
573} 573}
574 574
575static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio) 575static void cmd640_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
576{ 576{
577 unsigned int index = 0, cycle_time; 577 unsigned int index = 0, cycle_time;
578 const u8 pio = drive->pio_mode - XFER_PIO_0;
578 u8 b; 579 u8 b;
579 580
580 switch (pio) { 581 switch (pio) {
@@ -605,7 +606,7 @@ static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
605} 606}
606#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ 607#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
607 608
608static void cmd640_init_dev(ide_drive_t *drive) 609static void __init cmd640_init_dev(ide_drive_t *drive)
609{ 610{
610 unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1); 611 unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1);
611 612
diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c
index f2500c8826bb..5f80312e636b 100644
--- a/drivers/ide/cmd64x.c
+++ b/drivers/ide/cmd64x.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 * 8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
10 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com> 11 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
11 */ 12 */
12 13
@@ -50,72 +51,42 @@
50#define UDIDETCR1 0x7B 51#define UDIDETCR1 0x7B
51#define DTPR1 0x7C 52#define DTPR1 0x7C
52 53
53static u8 quantize_timing(int timing, int quant) 54static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
54{
55 return (timing + quant - 1) / quant;
56}
57
58/*
59 * This routine calculates active/recovery counts and then writes them into
60 * the chipset registers.
61 */
62static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
63{ 55{
56 ide_hwif_t *hwif = drive->hwif;
64 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 57 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
65 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33); 58 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
66 u8 cycle_count, active_count, recovery_count, drwtim; 59 const unsigned long T = 1000000 / bus_speed;
67 static const u8 recovery_values[] = 60 static const u8 recovery_values[] =
68 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; 61 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
62 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
63 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
69 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; 64 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
65 struct ide_timing t;
66 u8 arttim = 0;
70 67
71 cycle_count = quantize_timing( cycle_time, clock_time); 68 ide_timing_compute(drive, mode, &t, T, 0);
72 active_count = quantize_timing(active_time, clock_time);
73 recovery_count = cycle_count - active_count;
74 69
75 /* 70 /*
76 * In case we've got too long recovery phase, try to lengthen 71 * In case we've got too long recovery phase, try to lengthen
77 * the active phase 72 * the active phase
78 */ 73 */
79 if (recovery_count > 16) { 74 if (t.recover > 16) {
80 active_count += recovery_count - 16; 75 t.active += t.recover - 16;
81 recovery_count = 16; 76 t.recover = 16;
82 } 77 }
83 if (active_count > 16) /* shouldn't actually happen... */ 78 if (t.active > 16) /* shouldn't actually happen... */
84 active_count = 16; 79 t.active = 16;
85 80
86 /* 81 /*
87 * Convert values to internal chipset representation 82 * Convert values to internal chipset representation
88 */ 83 */
89 recovery_count = recovery_values[recovery_count]; 84 t.recover = recovery_values[t.recover];
90 active_count &= 0x0f; 85 t.active &= 0x0f;
91 86
92 /* Program the active/recovery counts into the DRWTIM register */ 87 /* Program the active/recovery counts into the DRWTIM register */
93 drwtim = (active_count << 4) | recovery_count; 88 pci_write_config_byte(dev, drwtim_regs[drive->dn],
94 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); 89 (t.active << 4) | t.recover);
95}
96
97/*
98 * This routine writes into the chipset registers
99 * PIO setup/active/recovery timings.
100 */
101static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
102{
103 ide_hwif_t *hwif = drive->hwif;
104 struct pci_dev *dev = to_pci_dev(hwif->dev);
105 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
106 unsigned long setup_count;
107 unsigned int cycle_time;
108 u8 arttim = 0;
109
110 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
111 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
112
113 cycle_time = ide_pio_cycle_time(drive, pio);
114
115 program_cycle_times(drive, cycle_time, t->active);
116
117 setup_count = quantize_timing(t->setup,
118 1000 / (ide_pci_clk ? ide_pci_clk : 33));
119 90
120 /* 91 /*
121 * The primary channel has individual address setup timing registers 92 * The primary channel has individual address setup timing registers
@@ -126,15 +97,21 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
126 if (hwif->channel) { 97 if (hwif->channel) {
127 ide_drive_t *pair = ide_get_pair_dev(drive); 98 ide_drive_t *pair = ide_get_pair_dev(drive);
128 99
129 ide_set_drivedata(drive, (void *)setup_count); 100 if (pair) {
101 struct ide_timing tp;
130 102
131 if (pair) 103 ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
132 setup_count = max_t(u8, setup_count, 104 ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
133 (unsigned long)ide_get_drivedata(pair)); 105 if (pair->dma_mode) {
106 ide_timing_compute(pair, pair->dma_mode,
107 &tp, T, 0);
108 ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
109 }
110 }
134 } 111 }
135 112
136 if (setup_count > 5) /* shouldn't actually happen... */ 113 if (t.setup > 5) /* shouldn't actually happen... */
137 setup_count = 5; 114 t.setup = 5;
138 115
139 /* 116 /*
140 * Program the address setup clocks into the ARTTIM registers. 117 * Program the address setup clocks into the ARTTIM registers.
@@ -144,7 +121,7 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
144 if (hwif->channel) 121 if (hwif->channel)
145 arttim &= ~ARTTIM23_INTR_CH1; 122 arttim &= ~ARTTIM23_INTR_CH1;
146 arttim &= ~0xc0; 123 arttim &= ~0xc0;
147 arttim |= setup_values[setup_count]; 124 arttim |= setup_values[t.setup];
148 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); 125 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
149} 126}
150 127
@@ -153,8 +130,10 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
153 * Special cases are 8: prefetch off, 9: prefetch on (both never worked) 130 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
154 */ 131 */
155 132
156static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) 133static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
157{ 134{
135 const u8 pio = drive->pio_mode - XFER_PIO_0;
136
158 /* 137 /*
159 * Filter out the prefetch control values 138 * Filter out the prefetch control values
160 * to prevent PIO5 from being programmed 139 * to prevent PIO5 from being programmed
@@ -162,20 +141,18 @@ static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
162 if (pio == 8 || pio == 9) 141 if (pio == 8 || pio == 9)
163 return; 142 return;
164 143
165 cmd64x_tune_pio(drive, pio); 144 cmd64x_program_timings(drive, XFER_PIO_0 + pio);
166} 145}
167 146
168static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) 147static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
169{ 148{
170 ide_hwif_t *hwif = drive->hwif;
171 struct pci_dev *dev = to_pci_dev(hwif->dev); 149 struct pci_dev *dev = to_pci_dev(hwif->dev);
172 u8 unit = drive->dn & 0x01; 150 u8 unit = drive->dn & 0x01;
173 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; 151 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
152 const u8 speed = drive->dma_mode;
174 153
175 if (speed >= XFER_SW_DMA_0) { 154 pci_read_config_byte(dev, pciU, &regU);
176 (void) pci_read_config_byte(dev, pciU, &regU); 155 regU &= ~(unit ? 0xCA : 0x35);
177 regU &= ~(unit ? 0xCA : 0x35);
178 }
179 156
180 switch(speed) { 157 switch(speed) {
181 case XFER_UDMA_5: 158 case XFER_UDMA_5:
@@ -197,18 +174,13 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
197 regU |= unit ? 0xC2 : 0x31; 174 regU |= unit ? 0xC2 : 0x31;
198 break; 175 break;
199 case XFER_MW_DMA_2: 176 case XFER_MW_DMA_2:
200 program_cycle_times(drive, 120, 70);
201 break;
202 case XFER_MW_DMA_1: 177 case XFER_MW_DMA_1:
203 program_cycle_times(drive, 150, 80);
204 break;
205 case XFER_MW_DMA_0: 178 case XFER_MW_DMA_0:
206 program_cycle_times(drive, 480, 215); 179 cmd64x_program_timings(drive, speed);
207 break; 180 break;
208 } 181 }
209 182
210 if (speed >= XFER_SW_DMA_0) 183 pci_write_config_byte(dev, pciU, regU);
211 (void) pci_write_config_byte(dev, pciU, regU);
212} 184}
213 185
214static void cmd648_clear_irq(ide_drive_t *drive) 186static void cmd648_clear_irq(ide_drive_t *drive)
@@ -471,6 +443,6 @@ static void __exit cmd64x_ide_exit(void)
471module_init(cmd64x_ide_init); 443module_init(cmd64x_ide_init);
472module_exit(cmd64x_ide_exit); 444module_exit(cmd64x_ide_exit);
473 445
474MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); 446MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
475MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); 447MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
476MODULE_LICENSE("GPL"); 448MODULE_LICENSE("GPL");
diff --git a/drivers/ide/cs5520.c b/drivers/ide/cs5520.c
index 09f98ed0731f..2c1e5f7cd261 100644
--- a/drivers/ide/cs5520.c
+++ b/drivers/ide/cs5520.c
@@ -57,11 +57,11 @@ static struct pio_clocks cs5520_pio_clocks[]={
57 {1, 2, 1} 57 {1, 2, 1}
58}; 58};
59 59
60static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio) 60static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
61{ 61{
62 ide_hwif_t *hwif = drive->hwif;
63 struct pci_dev *pdev = to_pci_dev(hwif->dev); 62 struct pci_dev *pdev = to_pci_dev(hwif->dev);
64 int controller = drive->dn > 1 ? 1 : 0; 63 int controller = drive->dn > 1 ? 1 : 0;
64 const u8 pio = drive->pio_mode - XFER_PIO_0;
65 65
66 /* 8bit CAT/CRT - 8bit command timing for channel */ 66 /* 8bit CAT/CRT - 8bit command timing for channel */
67 pci_write_config_byte(pdev, 0x62 + controller, 67 pci_write_config_byte(pdev, 0x62 + controller,
@@ -81,11 +81,12 @@ static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
81 (cs5520_pio_clocks[pio].assert)); 81 (cs5520_pio_clocks[pio].assert));
82} 82}
83 83
84static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed) 84static void cs5520_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85{ 85{
86 printk(KERN_ERR "cs55x0: bad ide timing.\n"); 86 printk(KERN_ERR "cs55x0: bad ide timing.\n");
87 87
88 cs5520_set_pio_mode(drive, 0); 88 drive->pio_mode = XFER_PIO_0 + 0;
89 cs5520_set_pio_mode(hwif, drive);
89} 90}
90 91
91static const struct ide_port_ops cs5520_port_ops = { 92static const struct ide_port_ops cs5520_port_ops = {
diff --git a/drivers/ide/cs5530.c b/drivers/ide/cs5530.c
index 40bf05eddf6e..4dc4eb92b076 100644
--- a/drivers/ide/cs5530.c
+++ b/drivers/ide/cs5530.c
@@ -41,8 +41,8 @@ static unsigned int cs5530_pio_timings[2][5] = {
41 41
42/** 42/**
43 * cs5530_set_pio_mode - set host controller for PIO mode 43 * cs5530_set_pio_mode - set host controller for PIO mode
44 * @hwif: port
44 * @drive: drive 45 * @drive: drive
45 * @pio: PIO mode number
46 * 46 *
47 * Handles setting of PIO mode for the chipset. 47 * Handles setting of PIO mode for the chipset.
48 * 48 *
@@ -50,10 +50,11 @@ static unsigned int cs5530_pio_timings[2][5] = {
50 * will have valid default PIO timings set up before we get here. 50 * will have valid default PIO timings set up before we get here.
51 */ 51 */
52 52
53static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio) 53static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
54{ 54{
55 unsigned long basereg = CS5530_BASEREG(drive->hwif); 55 unsigned long basereg = CS5530_BASEREG(hwif);
56 unsigned int format = (inl(basereg + 4) >> 31) & 1; 56 unsigned int format = (inl(basereg + 4) >> 31) & 1;
57 const u8 pio = drive->pio_mode - XFER_PIO_0;
57 58
58 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3)); 59 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
59} 60}
@@ -99,12 +100,12 @@ out:
99 return mask; 100 return mask;
100} 101}
101 102
102static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode) 103static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
103{ 104{
104 unsigned long basereg; 105 unsigned long basereg;
105 unsigned int reg, timings = 0; 106 unsigned int reg, timings = 0;
106 107
107 switch (mode) { 108 switch (drive->dma_mode) {
108 case XFER_UDMA_0: timings = 0x00921250; break; 109 case XFER_UDMA_0: timings = 0x00921250; break;
109 case XFER_UDMA_1: timings = 0x00911140; break; 110 case XFER_UDMA_1: timings = 0x00911140; break;
110 case XFER_UDMA_2: timings = 0x00911030; break; 111 case XFER_UDMA_2: timings = 0x00911030; break;
@@ -112,7 +113,7 @@ static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
112 case XFER_MW_DMA_1: timings = 0x00012121; break; 113 case XFER_MW_DMA_1: timings = 0x00012121; break;
113 case XFER_MW_DMA_2: timings = 0x00002020; break; 114 case XFER_MW_DMA_2: timings = 0x00002020; break;
114 } 115 }
115 basereg = CS5530_BASEREG(drive->hwif); 116 basereg = CS5530_BASEREG(hwif);
116 reg = inl(basereg + 4); /* get drive0 config register */ 117 reg = inl(basereg + 4); /* get drive0 config register */
117 timings |= reg & 0x80000000; /* preserve PIO format bit */ 118 timings |= reg & 0x80000000; /* preserve PIO format bit */
118 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */ 119 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
diff --git a/drivers/ide/cs5535.c b/drivers/ide/cs5535.c
index b883838adc24..5059fafadf29 100644
--- a/drivers/ide/cs5535.c
+++ b/drivers/ide/cs5535.c
@@ -86,7 +86,7 @@ static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
86 cmd = pioa = speed - XFER_PIO_0; 86 cmd = pioa = speed - XFER_PIO_0;
87 87
88 if (pair) { 88 if (pair) {
89 u8 piob = ide_get_best_pio_mode(pair, 255, 4); 89 u8 piob = pair->pio_mode - XFER_PIO_0;
90 90
91 if (piob < cmd) 91 if (piob < cmd)
92 cmd = piob; 92 cmd = piob;
@@ -129,28 +129,28 @@ static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
129 129
130/** 130/**
131 * cs5535_set_dma_mode - set host controller for DMA mode 131 * cs5535_set_dma_mode - set host controller for DMA mode
132 * @hwif: port
132 * @drive: drive 133 * @drive: drive
133 * @speed: DMA mode
134 * 134 *
135 * Programs the chipset for DMA mode. 135 * Programs the chipset for DMA mode.
136 */ 136 */
137 137
138static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed) 138static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
139{ 139{
140 cs5535_set_speed(drive, speed); 140 cs5535_set_speed(drive, drive->dma_mode);
141} 141}
142 142
143/** 143/**
144 * cs5535_set_pio_mode - set host controller for PIO mode 144 * cs5535_set_pio_mode - set host controller for PIO mode
145 * @hwif: port
145 * @drive: drive 146 * @drive: drive
146 * @pio: PIO mode number
147 * 147 *
148 * A callback from the upper layers for PIO-only tuning. 148 * A callback from the upper layers for PIO-only tuning.
149 */ 149 */
150 150
151static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio) 151static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
152{ 152{
153 cs5535_set_speed(drive, XFER_PIO_0 + pio); 153 cs5535_set_speed(drive, drive->pio_mode);
154} 154}
155 155
156static u8 cs5535_cable_detect(ide_hwif_t *hwif) 156static u8 cs5535_cable_detect(ide_hwif_t *hwif)
diff --git a/drivers/ide/cs5536.c b/drivers/ide/cs5536.c
index 9623b852c616..24214ab60ac0 100644
--- a/drivers/ide/cs5536.c
+++ b/drivers/ide/cs5536.c
@@ -125,11 +125,11 @@ static u8 cs5536_cable_detect(ide_hwif_t *hwif)
125 125
126/** 126/**
127 * cs5536_set_pio_mode - PIO timing setup 127 * cs5536_set_pio_mode - PIO timing setup
128 * @hwif: ATA port
128 * @drive: ATA device 129 * @drive: ATA device
129 * @pio: PIO mode number
130 */ 130 */
131 131
132static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio) 132static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
133{ 133{
134 static const u8 drv_timings[5] = { 134 static const u8 drv_timings[5] = {
135 0x98, 0x55, 0x32, 0x21, 0x20, 135 0x98, 0x55, 0x32, 0x21, 0x20,
@@ -143,15 +143,16 @@ static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio)
143 0x99, 0x92, 0x90, 0x22, 0x20, 143 0x99, 0x92, 0x90, 0x22, 0x20,
144 }; 144 };
145 145
146 struct pci_dev *pdev = to_pci_dev(drive->hwif->dev); 146 struct pci_dev *pdev = to_pci_dev(hwif->dev);
147 ide_drive_t *pair = ide_get_pair_dev(drive); 147 ide_drive_t *pair = ide_get_pair_dev(drive);
148 int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT; 148 int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
149 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 149 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
150 u32 cast; 150 u32 cast;
151 const u8 pio = drive->pio_mode - XFER_PIO_0;
151 u8 cmd_pio = pio; 152 u8 cmd_pio = pio;
152 153
153 if (pair) 154 if (pair)
154 cmd_pio = min(pio, ide_get_best_pio_mode(pair, 255, 4)); 155 cmd_pio = min_t(u8, pio, pair->pio_mode - XFER_PIO_0);
155 156
156 timings &= (IDE_DRV_MASK << 8); 157 timings &= (IDE_DRV_MASK << 8);
157 timings |= drv_timings[pio]; 158 timings |= drv_timings[pio];
@@ -172,11 +173,11 @@ static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio)
172 173
173/** 174/**
174 * cs5536_set_dma_mode - DMA timing setup 175 * cs5536_set_dma_mode - DMA timing setup
176 * @hwif: ATA port
175 * @drive: ATA device 177 * @drive: ATA device
176 * @mode: DMA mode
177 */ 178 */
178 179
179static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode) 180static void cs5536_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
180{ 181{
181 static const u8 udma_timings[6] = { 182 static const u8 udma_timings[6] = {
182 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 183 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
@@ -186,10 +187,11 @@ static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode)
186 0x67, 0x21, 0x20, 187 0x67, 0x21, 0x20,
187 }; 188 };
188 189
189 struct pci_dev *pdev = to_pci_dev(drive->hwif->dev); 190 struct pci_dev *pdev = to_pci_dev(hwif->dev);
190 int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT; 191 int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
191 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 192 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
192 u32 etc; 193 u32 etc;
194 const u8 mode = drive->dma_mode;
193 195
194 cs5536_read(pdev, ETC, &etc); 196 cs5536_read(pdev, ETC, &etc);
195 197
diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c
index d6e2cbbc53a0..9383f67deae1 100644
--- a/drivers/ide/cy82c693.c
+++ b/drivers/ide/cy82c693.c
@@ -1,43 +1,11 @@
1/* 1/*
2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer 2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator 3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
4 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
4 * 5 *
5 * CYPRESS CY82C693 chipset IDE controller 6 * CYPRESS CY82C693 chipset IDE controller
6 * 7 *
7 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards. 8 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
8 * Writing the driver was quite simple, since most of the job is
9 * done by the generic pci-ide support.
10 * The hard part was finding the CY82C693's datasheet on Cypress's
11 * web page :-(. But Altavista solved this problem :-).
12 *
13 *
14 * Notes:
15 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
16 * a large and fast disk - the results look great, so I'd say the
17 * driver is working fine :-)
18 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
19 * - this is my first linux driver, so there's probably a lot of room
20 * for optimizations and bug fixing, so feel free to do it.
21 * - if using PIO mode it's a good idea to set the PIO mode and
22 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
23 * - I had some problems with my IBM DHEA with PIO modes < 2
24 * (lost interrupts) ?????
25 * - first tests with DMA look okay, they seem to work, but there is a
26 * problem with sound - the BusMaster IDE TimeOut should fixed this
27 *
28 * Ancient History:
29 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
30 * ASK@1999-01-23: v0.33 made a few minor code clean ups
31 * removed DMA clock speed setting by default
32 * added boot message
33 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
34 * added support to set DMA Controller Clock Speed
35 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
36 * on some drives.
37 * ASK@1998-10-29: v0.3 added support to set DMA modes
38 * ASK@1998-10-28: v0.2 added support to set PIO modes
39 * ASK@1998-10-27: v0.1 first version - chipset detection
40 *
41 */ 9 */
42 10
43#include <linux/module.h> 11#include <linux/module.h>
@@ -81,87 +49,13 @@
81#define CY82_INDEX_CHANNEL1 0x31 49#define CY82_INDEX_CHANNEL1 0x31
82#define CY82_INDEX_TIMEOUT 0x32 50#define CY82_INDEX_TIMEOUT 0x32
83 51
84/* the min and max PCI bus speed in MHz - from datasheet */
85#define CY82C963_MIN_BUS_SPEED 25
86#define CY82C963_MAX_BUS_SPEED 33
87
88/* the struct for the PIO mode timings */
89typedef struct pio_clocks_s {
90 u8 address_time; /* Address setup (clocks) */
91 u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
92 u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
93 u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
94} pio_clocks_t;
95
96/*
97 * calc clocks using bus_speed
98 * returns (rounded up) time in bus clocks for time in ns
99 */
100static int calc_clk(int time, int bus_speed)
101{
102 int clocks;
103
104 clocks = (time*bus_speed+999)/1000 - 1;
105
106 if (clocks < 0)
107 clocks = 0;
108
109 if (clocks > 0x0F)
110 clocks = 0x0F;
111
112 return clocks;
113}
114
115/*
116 * compute the values for the clock registers for PIO
117 * mode and pci_clk [MHz] speed
118 *
119 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
120 * for mode 3 and 4 drives 8 and 16-bit timings are the same
121 *
122 */
123static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
124{
125 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
126 int clk1, clk2;
127 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
128
129 /* we don't check against CY82C693's min and max speed,
130 * so you can play with the idebus=xx parameter
131 */
132
133 /* let's calc the address setup time clocks */
134 p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
135
136 /* let's calc the active and recovery time clocks */
137 clk1 = calc_clk(t->active, bus_speed);
138
139 /* calc recovery timing */
140 clk2 = t->cycle - t->active - t->setup;
141
142 clk2 = calc_clk(clk2, bus_speed);
143
144 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
145
146 /* note: we use the same values for 16bit IOR and IOW
147 * those are all the same, since I don't have other
148 * timings than those from ide-lib.c
149 */
150
151 p_pclk->time_16r = (u8)clk1;
152 p_pclk->time_16w = (u8)clk1;
153
154 /* what are good values for 8bit ?? */
155 p_pclk->time_8 = (u8)clk1;
156}
157
158/* 52/*
159 * set DMA mode a specific channel for CY82C693 53 * set DMA mode a specific channel for CY82C693
160 */ 54 */
161 55
162static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) 56static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
163{ 57{
164 ide_hwif_t *hwif = drive->hwif; 58 const u8 mode = drive->dma_mode;
165 u8 single = (mode & 0x10) >> 4, index = 0, data = 0; 59 u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
166 60
167 index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; 61 index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
@@ -186,12 +80,14 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
186 outb(data, CY82_DATA_PORT); 80 outb(data, CY82_DATA_PORT);
187} 81}
188 82
189static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) 83static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
190{ 84{
191 ide_hwif_t *hwif = drive->hwif;
192 struct pci_dev *dev = to_pci_dev(hwif->dev); 85 struct pci_dev *dev = to_pci_dev(hwif->dev);
193 pio_clocks_t pclk; 86 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
87 const unsigned long T = 1000000 / bus_speed;
194 unsigned int addrCtrl; 88 unsigned int addrCtrl;
89 struct ide_timing t;
90 u8 time_16, time_8;
195 91
196 /* select primary or secondary channel */ 92 /* select primary or secondary channel */
197 if (hwif->index > 0) { /* drive is on the secondary channel */ 93 if (hwif->index > 0) { /* drive is on the secondary channel */
@@ -204,8 +100,12 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
204 } 100 }
205 } 101 }
206 102
207 /* let's calc the values for this PIO mode */ 103 ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
208 compute_clocks(pio, &pclk); 104
105 time_16 = clamp_val(t.recover - 1, 0, 15) |
106 (clamp_val(t.active - 1, 0, 15) << 4);
107 time_8 = clamp_val(t.act8b - 1, 0, 15) |
108 (clamp_val(t.rec8b - 1, 0, 15) << 4);
209 109
210 /* now let's write the clocks registers */ 110 /* now let's write the clocks registers */
211 if ((drive->dn & 1) == 0) { 111 if ((drive->dn & 1) == 0) {
@@ -217,13 +117,13 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
217 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); 117 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
218 118
219 addrCtrl &= (~0xF); 119 addrCtrl &= (~0xF);
220 addrCtrl |= (unsigned int)pclk.address_time; 120 addrCtrl |= clamp_val(t.setup - 1, 0, 15);
221 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); 121 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
222 122
223 /* now let's set the remaining registers */ 123 /* now let's set the remaining registers */
224 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); 124 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
225 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); 125 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
226 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); 126 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
227 } else { 127 } else {
228 /* 128 /*
229 * set slave drive 129 * set slave drive
@@ -233,13 +133,13 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
233 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); 133 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
234 134
235 addrCtrl &= (~0xF0); 135 addrCtrl &= (~0xF0);
236 addrCtrl |= ((unsigned int)pclk.address_time<<4); 136 addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
237 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); 137 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
238 138
239 /* now let's set the remaining registers */ 139 /* now let's set the remaining registers */
240 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); 140 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
241 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); 141 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
242 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); 142 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
243 } 143 }
244} 144}
245 145
@@ -325,6 +225,6 @@ static void __exit cy82c693_ide_exit(void)
325module_init(cy82c693_ide_init); 225module_init(cy82c693_ide_init);
326module_exit(cy82c693_ide_exit); 226module_exit(cy82c693_ide_exit);
327 227
328MODULE_AUTHOR("Andreas Krebs, Andre Hedrick"); 228MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
329MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE"); 229MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
330MODULE_LICENSE("GPL"); 230MODULE_LICENSE("GPL");
diff --git a/drivers/ide/dtc2278.c b/drivers/ide/dtc2278.c
index c6b138122981..6929f7fce93a 100644
--- a/drivers/ide/dtc2278.c
+++ b/drivers/ide/dtc2278.c
@@ -68,11 +68,11 @@ static void sub22 (char b, char c)
68 68
69static DEFINE_SPINLOCK(dtc2278_lock); 69static DEFINE_SPINLOCK(dtc2278_lock);
70 70
71static void dtc2278_set_pio_mode(ide_drive_t *drive, const u8 pio) 71static void dtc2278_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
72{ 72{
73 unsigned long flags; 73 unsigned long flags;
74 74
75 if (pio >= 3) { 75 if (drive->pio_mode >= XFER_PIO_3) {
76 spin_lock_irqsave(&dtc2278_lock, flags); 76 spin_lock_irqsave(&dtc2278_lock, flags);
77 /* 77 /*
78 * This enables PIO mode4 (3?) on the first interface 78 * This enables PIO mode4 (3?) on the first interface
diff --git a/drivers/ide/hpt366.c b/drivers/ide/hpt366.c
index 4d90ac2dbb1b..b885c1d548f5 100644
--- a/drivers/ide/hpt366.c
+++ b/drivers/ide/hpt366.c
@@ -627,14 +627,14 @@ static u32 get_speed_setting(u8 speed, struct hpt_info *info)
627 return info->timings->clock_table[info->clock][i]; 627 return info->timings->clock_table[info->clock][i];
628} 628}
629 629
630static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) 630static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
631{ 631{
632 ide_hwif_t *hwif = drive->hwif;
633 struct pci_dev *dev = to_pci_dev(hwif->dev); 632 struct pci_dev *dev = to_pci_dev(hwif->dev);
634 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 633 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
635 struct hpt_timings *t = info->timings; 634 struct hpt_timings *t = info->timings;
636 u8 itr_addr = 0x40 + (drive->dn * 4); 635 u8 itr_addr = 0x40 + (drive->dn * 4);
637 u32 old_itr = 0; 636 u32 old_itr = 0;
637 const u8 speed = drive->dma_mode;
638 u32 new_itr = get_speed_setting(speed, info); 638 u32 new_itr = get_speed_setting(speed, info);
639 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : 639 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
640 (speed < XFER_UDMA_0 ? t->dma_mask : 640 (speed < XFER_UDMA_0 ? t->dma_mask :
@@ -651,9 +651,10 @@ static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
651 pci_write_config_dword(dev, itr_addr, new_itr); 651 pci_write_config_dword(dev, itr_addr, new_itr);
652} 652}
653 653
654static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 654static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
655{ 655{
656 hpt3xx_set_mode(drive, XFER_PIO_0 + pio); 656 drive->dma_mode = drive->pio_mode;
657 hpt3xx_set_mode(hwif, drive);
657} 658}
658 659
659static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 660static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
diff --git a/drivers/ide/ht6560b.c b/drivers/ide/ht6560b.c
index aafed8060e17..d81e49680c3f 100644
--- a/drivers/ide/ht6560b.c
+++ b/drivers/ide/ht6560b.c
@@ -279,9 +279,10 @@ static void ht_set_prefetch(ide_drive_t *drive, u8 state)
279#endif 279#endif
280} 280}
281 281
282static void ht6560b_set_pio_mode(ide_drive_t *drive, const u8 pio) 282static void ht6560b_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
283{ 283{
284 unsigned long flags, config; 284 unsigned long flags, config;
285 const u8 pio = drive->pio_mode - XFER_PIO_0;
285 u8 timing; 286 u8 timing;
286 287
287 switch (pio) { 288 switch (pio) {
diff --git a/drivers/ide/icside.c b/drivers/ide/icside.c
index 0f67f1abbbd3..4a697a238e28 100644
--- a/drivers/ide/icside.c
+++ b/drivers/ide/icside.c
@@ -65,6 +65,8 @@ static struct cardinfo icside_cardinfo_v6_2 = {
65}; 65};
66 66
67struct icside_state { 67struct icside_state {
68 unsigned int channel;
69 unsigned int enabled;
68 void __iomem *irq_port; 70 void __iomem *irq_port;
69 void __iomem *ioc_base; 71 void __iomem *ioc_base;
70 unsigned int sel; 72 unsigned int sel;
@@ -114,11 +116,18 @@ static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114 struct icside_state *state = ec->irq_data; 116 struct icside_state *state = ec->irq_data;
115 void __iomem *base = state->irq_port; 117 void __iomem *base = state->irq_port;
116 118
117 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); 119 state->enabled = 1;
118 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
119 120
120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); 121 switch (state->channel) {
121 readb(base + ICS_ARCIN_V6_INTROFFSET_1); 122 case 0:
123 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
124 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
125 break;
126 case 1:
127 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
128 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
129 break;
130 }
122} 131}
123 132
124/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) 133/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
@@ -128,6 +137,8 @@ static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
128{ 137{
129 struct icside_state *state = ec->irq_data; 138 struct icside_state *state = ec->irq_data;
130 139
140 state->enabled = 0;
141
131 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); 142 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
132 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); 143 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
133} 144}
@@ -149,6 +160,44 @@ static const expansioncard_ops_t icside_ops_arcin_v6 = {
149 .irqpending = icside_irqpending_arcin_v6, 160 .irqpending = icside_irqpending_arcin_v6,
150}; 161};
151 162
163/*
164 * Handle routing of interrupts. This is called before
165 * we write the command to the drive.
166 */
167static void icside_maskproc(ide_drive_t *drive, int mask)
168{
169 ide_hwif_t *hwif = drive->hwif;
170 struct expansion_card *ec = ECARD_DEV(hwif->dev);
171 struct icside_state *state = ecard_get_drvdata(ec);
172 unsigned long flags;
173
174 local_irq_save(flags);
175
176 state->channel = hwif->channel;
177
178 if (state->enabled && !mask) {
179 switch (hwif->channel) {
180 case 0:
181 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
182 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
183 break;
184 case 1:
185 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
186 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
187 break;
188 }
189 } else {
190 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
191 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
192 }
193
194 local_irq_restore(flags);
195}
196
197static const struct ide_port_ops icside_v6_no_dma_port_ops = {
198 .maskproc = icside_maskproc,
199};
200
152#ifdef CONFIG_BLK_DEV_IDEDMA_ICS 201#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
153/* 202/*
154 * SG-DMA support. 203 * SG-DMA support.
@@ -185,10 +234,11 @@ static const expansioncard_ops_t icside_ops_arcin_v6 = {
185 * MW1 80 50 50 150 C 234 * MW1 80 50 50 150 C
186 * MW2 70 25 25 120 C 235 * MW2 70 25 25 120 C
187 */ 236 */
188static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode) 237static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
189{ 238{
190 unsigned long cycle_time; 239 unsigned long cycle_time;
191 int use_dma_info = 0; 240 int use_dma_info = 0;
241 const u8 xfer_mode = drive->dma_mode;
192 242
193 switch (xfer_mode) { 243 switch (xfer_mode) {
194 case XFER_MW_DMA_2: 244 case XFER_MW_DMA_2:
@@ -228,6 +278,7 @@ static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
228 278
229static const struct ide_port_ops icside_v6_port_ops = { 279static const struct ide_port_ops icside_v6_port_ops = {
230 .set_dma_mode = icside_set_dma_mode, 280 .set_dma_mode = icside_set_dma_mode,
281 .maskproc = icside_maskproc,
231}; 282};
232 283
233static void icside_dma_host_set(ide_drive_t *drive, int on) 284static void icside_dma_host_set(ide_drive_t *drive, int on)
@@ -272,6 +323,11 @@ static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
272 BUG_ON(dma_channel_active(ec->dma)); 323 BUG_ON(dma_channel_active(ec->dma));
273 324
274 /* 325 /*
326 * Ensure that we have the right interrupt routed.
327 */
328 icside_maskproc(drive, 0);
329
330 /*
275 * Route the DMA signals to the correct interface. 331 * Route the DMA signals to the correct interface.
276 */ 332 */
277 writeb(state->sel | hwif->channel, state->ioc_base); 333 writeb(state->sel | hwif->channel, state->ioc_base);
@@ -399,6 +455,7 @@ err_free:
399 455
400static const struct ide_port_info icside_v6_port_info __initdata = { 456static const struct ide_port_info icside_v6_port_info __initdata = {
401 .init_dma = icside_dma_off_init, 457 .init_dma = icside_dma_off_init,
458 .port_ops = &icside_v6_no_dma_port_ops,
402 .dma_ops = &icside_v6_dma_ops, 459 .dma_ops = &icside_v6_dma_ops,
403 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO, 460 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
404 .mwdma_mask = ATA_MWDMA2, 461 .mwdma_mask = ATA_MWDMA2,
diff --git a/drivers/ide/ide-cs.c b/drivers/ide/ide-cs.c
index dd6396384c25..ab87e4f7cec9 100644
--- a/drivers/ide/ide-cs.c
+++ b/drivers/ide/ide-cs.c
@@ -121,19 +121,11 @@ static int ide_probe(struct pcmcia_device *link)
121static void ide_detach(struct pcmcia_device *link) 121static void ide_detach(struct pcmcia_device *link)
122{ 122{
123 ide_info_t *info = link->priv; 123 ide_info_t *info = link->priv;
124 ide_hwif_t *hwif = info->host->ports[0];
125 unsigned long data_addr, ctl_addr;
126 124
127 dev_dbg(&link->dev, "ide_detach(0x%p)\n", link); 125 dev_dbg(&link->dev, "ide_detach(0x%p)\n", link);
128 126
129 data_addr = hwif->io_ports.data_addr;
130 ctl_addr = hwif->io_ports.ctl_addr;
131
132 ide_release(link); 127 ide_release(link);
133 128
134 release_region(ctl_addr, 1);
135 release_region(data_addr, 8);
136
137 kfree(info); 129 kfree(info);
138} /* ide_detach */ 130} /* ide_detach */
139 131
@@ -354,12 +346,19 @@ static void ide_release(struct pcmcia_device *link)
354 346
355 dev_dbg(&link->dev, "ide_release(0x%p)\n", link); 347 dev_dbg(&link->dev, "ide_release(0x%p)\n", link);
356 348
357 if (info->ndev) 349 if (info->ndev) {
358 /* FIXME: if this fails we need to queue the cleanup somehow 350 ide_hwif_t *hwif = host->ports[0];
359 -- need to investigate the required PCMCIA magic */ 351 unsigned long data_addr, ctl_addr;
352
353 data_addr = hwif->io_ports.data_addr;
354 ctl_addr = hwif->io_ports.ctl_addr;
355
360 ide_host_remove(host); 356 ide_host_remove(host);
357 info->ndev = 0;
361 358
362 info->ndev = 0; 359 release_region(ctl_addr, 1);
360 release_region(data_addr, 8);
361 }
363 362
364 pcmcia_disable_device(link); 363 pcmcia_disable_device(link);
365} /* ide_release */ 364} /* ide_release */
diff --git a/drivers/ide/ide-devsets.c b/drivers/ide/ide-devsets.c
index 1099bf7cf968..c6935c78757c 100644
--- a/drivers/ide/ide-devsets.c
+++ b/drivers/ide/ide-devsets.c
@@ -105,15 +105,17 @@ static int set_pio_mode(ide_drive_t *drive, int arg)
105 return -ENOSYS; 105 return -ENOSYS;
106 106
107 if (set_pio_mode_abuse(drive->hwif, arg)) { 107 if (set_pio_mode_abuse(drive->hwif, arg)) {
108 drive->pio_mode = arg + XFER_PIO_0;
109
108 if (arg == 8 || arg == 9) { 110 if (arg == 8 || arg == 9) {
109 unsigned long flags; 111 unsigned long flags;
110 112
111 /* take lock for IDE_DFLAG_[NO_]UNMASK/[NO_]IO_32BIT */ 113 /* take lock for IDE_DFLAG_[NO_]UNMASK/[NO_]IO_32BIT */
112 spin_lock_irqsave(&hwif->lock, flags); 114 spin_lock_irqsave(&hwif->lock, flags);
113 port_ops->set_pio_mode(drive, arg); 115 port_ops->set_pio_mode(hwif, drive);
114 spin_unlock_irqrestore(&hwif->lock, flags); 116 spin_unlock_irqrestore(&hwif->lock, flags);
115 } else 117 } else
116 port_ops->set_pio_mode(drive, arg); 118 port_ops->set_pio_mode(hwif, drive);
117 } else { 119 } else {
118 int keep_dma = !!(drive->dev_flags & IDE_DFLAG_USING_DMA); 120 int keep_dma = !!(drive->dev_flags & IDE_DFLAG_USING_DMA);
119 121
diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c
index 222c1ef65fb9..376f2dc410c5 100644
--- a/drivers/ide/ide-iops.c
+++ b/drivers/ide/ide-iops.c
@@ -231,7 +231,7 @@ u8 eighty_ninty_three(ide_drive_t *drive)
231 u16 *id = drive->id; 231 u16 *id = drive->id;
232 int ivb = ide_in_drive_list(id, ivb_list); 232 int ivb = ide_in_drive_list(id, ivb_list);
233 233
234 if (hwif->cbl == ATA_CBL_PATA40_SHORT) 234 if (hwif->cbl == ATA_CBL_SATA || hwif->cbl == ATA_CBL_PATA40_SHORT)
235 return 1; 235 return 1;
236 236
237 if (ivb) 237 if (ivb)
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index f8c1ae6ad74c..fbedd35feb44 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -1042,6 +1042,8 @@ static void ide_port_init_devices(ide_hwif_t *hwif)
1042 if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS) 1042 if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS)
1043 drive->dev_flags |= IDE_DFLAG_NO_UNMASK; 1043 drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
1044 1044
1045 drive->pio_mode = XFER_PIO_0;
1046
1045 if (port_ops && port_ops->init_dev) 1047 if (port_ops && port_ops->init_dev)
1046 port_ops->init_dev(drive); 1048 port_ops->init_dev(drive);
1047 } 1049 }
diff --git a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c
index 6a0e62542167..b07232880ec9 100644
--- a/drivers/ide/ide-tape.c
+++ b/drivers/ide/ide-tape.c
@@ -1365,7 +1365,7 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
1365 * supported here, and not in the corresponding block interface. Our own 1365 * supported here, and not in the corresponding block interface. Our own
1366 * ide-tape ioctls are supported on both interfaces. 1366 * ide-tape ioctls are supported on both interfaces.
1367 */ 1367 */
1368static int idetape_chrdev_ioctl(struct inode *inode, struct file *file, 1368static long do_idetape_chrdev_ioctl(struct file *file,
1369 unsigned int cmd, unsigned long arg) 1369 unsigned int cmd, unsigned long arg)
1370{ 1370{
1371 struct ide_tape_obj *tape = file->private_data; 1371 struct ide_tape_obj *tape = file->private_data;
@@ -1420,6 +1420,16 @@ static int idetape_chrdev_ioctl(struct inode *inode, struct file *file,
1420 } 1420 }
1421} 1421}
1422 1422
1423static long idetape_chrdev_ioctl(struct file *file,
1424 unsigned int cmd, unsigned long arg)
1425{
1426 long ret;
1427 lock_kernel();
1428 ret = do_idetape_chrdev_ioctl(file, cmd, arg);
1429 unlock_kernel();
1430 return ret;
1431}
1432
1423/* 1433/*
1424 * Do a mode sense page 0 with block descriptor and if it succeeds set the tape 1434 * Do a mode sense page 0 with block descriptor and if it succeeds set the tape
1425 * block size with the reported value. 1435 * block size with the reported value.
@@ -1888,7 +1898,7 @@ static const struct file_operations idetape_fops = {
1888 .owner = THIS_MODULE, 1898 .owner = THIS_MODULE,
1889 .read = idetape_chrdev_read, 1899 .read = idetape_chrdev_read,
1890 .write = idetape_chrdev_write, 1900 .write = idetape_chrdev_write,
1891 .ioctl = idetape_chrdev_ioctl, 1901 .unlocked_ioctl = idetape_chrdev_ioctl,
1892 .open = idetape_chrdev_open, 1902 .open = idetape_chrdev_open,
1893 .release = idetape_chrdev_release, 1903 .release = idetape_chrdev_release,
1894}; 1904};
diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c
index 001a56365be5..0e05f75934c9 100644
--- a/drivers/ide/ide-timings.c
+++ b/drivers/ide/ide-timings.c
@@ -166,12 +166,13 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
166 if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ 166 if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
167 memset(&p, 0, sizeof(p)); 167 memset(&p, 0, sizeof(p));
168 168
169 if (speed <= XFER_PIO_2) 169 if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
170 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; 170 if (speed <= XFER_PIO_2)
171 else if ((speed <= XFER_PIO_4) || 171 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
172 (speed == XFER_PIO_5 && !ata_id_is_cfa(id))) 172 else if ((speed <= XFER_PIO_4) ||
173 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; 173 (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
174 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 174 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
175 } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
175 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; 176 p.cycle = id[ATA_ID_EIDE_DMA_MIN];
176 177
177 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); 178 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
@@ -185,11 +186,10 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
185 /* 186 /*
186 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, 187 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
187 * S.M.A.R.T and some other commands. We have to ensure that the 188 * S.M.A.R.T and some other commands. We have to ensure that the
188 * DMA cycle timing is slower/equal than the fastest PIO timing. 189 * DMA cycle timing is slower/equal than the current PIO timing.
189 */ 190 */
190 if (speed >= XFER_SW_DMA_0) { 191 if (speed >= XFER_SW_DMA_0) {
191 u8 pio = ide_get_best_pio_mode(drive, 255, 5); 192 ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
192 ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
193 ide_timing_merge(&p, t, t, IDE_TIMING_ALL); 193 ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
194 } 194 }
195 195
diff --git a/drivers/ide/ide-xfer-mode.c b/drivers/ide/ide-xfer-mode.c
index 46d203ce60cc..5fc8d5c17de9 100644
--- a/drivers/ide/ide-xfer-mode.c
+++ b/drivers/ide/ide-xfer-mode.c
@@ -58,7 +58,7 @@ EXPORT_SYMBOL(ide_xfer_verbose);
58 * This is used by most chipset support modules when "auto-tuning". 58 * This is used by most chipset support modules when "auto-tuning".
59 */ 59 */
60 60
61u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode) 61static u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode)
62{ 62{
63 u16 *id = drive->id; 63 u16 *id = drive->id;
64 int pio_mode = -1, overridden = 0; 64 int pio_mode = -1, overridden = 0;
@@ -105,7 +105,6 @@ u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode)
105 105
106 return pio_mode; 106 return pio_mode;
107} 107}
108EXPORT_SYMBOL_GPL(ide_get_best_pio_mode);
109 108
110int ide_pio_need_iordy(ide_drive_t *drive, const u8 pio) 109int ide_pio_need_iordy(ide_drive_t *drive, const u8 pio)
111{ 110{
@@ -135,17 +134,20 @@ int ide_set_pio_mode(ide_drive_t *drive, const u8 mode)
135 * set transfer mode on the device in ->set_pio_mode method... 134 * set transfer mode on the device in ->set_pio_mode method...
136 */ 135 */
137 if (port_ops->set_dma_mode == NULL) { 136 if (port_ops->set_dma_mode == NULL) {
138 port_ops->set_pio_mode(drive, mode - XFER_PIO_0); 137 drive->pio_mode = mode;
138 port_ops->set_pio_mode(hwif, drive);
139 return 0; 139 return 0;
140 } 140 }
141 141
142 if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) { 142 if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) {
143 if (ide_config_drive_speed(drive, mode)) 143 if (ide_config_drive_speed(drive, mode))
144 return -1; 144 return -1;
145 port_ops->set_pio_mode(drive, mode - XFER_PIO_0); 145 drive->pio_mode = mode;
146 port_ops->set_pio_mode(hwif, drive);
146 return 0; 147 return 0;
147 } else { 148 } else {
148 port_ops->set_pio_mode(drive, mode - XFER_PIO_0); 149 drive->pio_mode = mode;
150 port_ops->set_pio_mode(hwif, drive);
149 return ide_config_drive_speed(drive, mode); 151 return ide_config_drive_speed(drive, mode);
150 } 152 }
151} 153}
@@ -164,10 +166,12 @@ int ide_set_dma_mode(ide_drive_t *drive, const u8 mode)
164 if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) { 166 if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) {
165 if (ide_config_drive_speed(drive, mode)) 167 if (ide_config_drive_speed(drive, mode))
166 return -1; 168 return -1;
167 port_ops->set_dma_mode(drive, mode); 169 drive->dma_mode = mode;
170 port_ops->set_dma_mode(hwif, drive);
168 return 0; 171 return 0;
169 } else { 172 } else {
170 port_ops->set_dma_mode(drive, mode); 173 drive->dma_mode = mode;
174 port_ops->set_dma_mode(hwif, drive);
171 return ide_config_drive_speed(drive, mode); 175 return ide_config_drive_speed(drive, mode);
172 } 176 }
173} 177}
diff --git a/drivers/ide/it8172.c b/drivers/ide/it8172.c
index 0d266a5b524d..560e66d07659 100644
--- a/drivers/ide/it8172.c
+++ b/drivers/ide/it8172.c
@@ -37,12 +37,12 @@
37 37
38#define DRV_NAME "IT8172" 38#define DRV_NAME "IT8172"
39 39
40static void it8172_set_pio_mode(ide_drive_t *drive, const u8 pio) 40static void it8172_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
41{ 41{
42 ide_hwif_t *hwif = drive->hwif;
43 struct pci_dev *dev = to_pci_dev(hwif->dev); 42 struct pci_dev *dev = to_pci_dev(hwif->dev);
44 u16 drive_enables; 43 u16 drive_enables;
45 u32 drive_timing; 44 u32 drive_timing;
45 const u8 pio = drive->pio_mode - XFER_PIO_0;
46 46
47 /* 47 /*
48 * The highest value of DIOR/DIOW pulse width and recovery time 48 * The highest value of DIOR/DIOW pulse width and recovery time
@@ -77,14 +77,14 @@ static void it8172_set_pio_mode(ide_drive_t *drive, const u8 pio)
77 pci_write_config_dword(dev, 0x44, drive_timing); 77 pci_write_config_dword(dev, 0x44, drive_timing);
78} 78}
79 79
80static void it8172_set_dma_mode(ide_drive_t *drive, const u8 speed) 80static void it8172_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
81{ 81{
82 ide_hwif_t *hwif = drive->hwif;
83 struct pci_dev *dev = to_pci_dev(hwif->dev); 82 struct pci_dev *dev = to_pci_dev(hwif->dev);
84 int a_speed = 3 << (drive->dn * 4); 83 int a_speed = 3 << (drive->dn * 4);
85 int u_flag = 1 << drive->dn; 84 int u_flag = 1 << drive->dn;
86 int u_speed = 0; 85 int u_speed = 0;
87 u8 reg48, reg4a; 86 u8 reg48, reg4a;
87 const u8 speed = drive->dma_mode;
88 88
89 pci_read_config_byte(dev, 0x48, &reg48); 89 pci_read_config_byte(dev, 0x48, &reg48);
90 pci_read_config_byte(dev, 0x4a, &reg4a); 90 pci_read_config_byte(dev, 0x4a, &reg4a);
@@ -98,14 +98,14 @@ static void it8172_set_dma_mode(ide_drive_t *drive, const u8 speed)
98 pci_write_config_byte(dev, 0x4a, reg4a | u_speed); 98 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
99 } else { 99 } else {
100 const u8 mwdma_to_pio[] = { 0, 3, 4 }; 100 const u8 mwdma_to_pio[] = { 0, 3, 4 };
101 u8 pio;
102 101
103 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); 102 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
104 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed); 103 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
105 104
106 pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; 105 drive->pio_mode =
106 mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
107 107
108 it8172_set_pio_mode(drive, pio); 108 it8172_set_pio_mode(hwif, drive);
109 } 109 }
110} 110}
111 111
diff --git a/drivers/ide/it8213.c b/drivers/ide/it8213.c
index 47976167796a..46816ba26416 100644
--- a/drivers/ide/it8213.c
+++ b/drivers/ide/it8213.c
@@ -17,15 +17,14 @@
17 17
18/** 18/**
19 * it8213_set_pio_mode - set host controller for PIO mode 19 * it8213_set_pio_mode - set host controller for PIO mode
20 * @hwif: port
20 * @drive: drive 21 * @drive: drive
21 * @pio: PIO mode number
22 * 22 *
23 * Set the interface PIO mode. 23 * Set the interface PIO mode.
24 */ 24 */
25 25
26static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio) 26static void it8213_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
27{ 27{
28 ide_hwif_t *hwif = drive->hwif;
29 struct pci_dev *dev = to_pci_dev(hwif->dev); 28 struct pci_dev *dev = to_pci_dev(hwif->dev);
30 int is_slave = drive->dn & 1; 29 int is_slave = drive->dn & 1;
31 int master_port = 0x40; 30 int master_port = 0x40;
@@ -35,6 +34,7 @@ static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio)
35 u8 slave_data; 34 u8 slave_data;
36 static DEFINE_SPINLOCK(tune_lock); 35 static DEFINE_SPINLOCK(tune_lock);
37 int control = 0; 36 int control = 0;
37 const u8 pio = drive->pio_mode - XFER_PIO_0;
38 38
39 static const u8 timings[][2] = { 39 static const u8 timings[][2] = {
40 { 0, 0 }, 40 { 0, 0 },
@@ -74,15 +74,14 @@ static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio)
74 74
75/** 75/**
76 * it8213_set_dma_mode - set host controller for DMA mode 76 * it8213_set_dma_mode - set host controller for DMA mode
77 * @hwif: port
77 * @drive: drive 78 * @drive: drive
78 * @speed: DMA mode
79 * 79 *
80 * Tune the ITE chipset for the DMA mode. 80 * Tune the ITE chipset for the DMA mode.
81 */ 81 */
82 82
83static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed) 83static void it8213_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
84{ 84{
85 ide_hwif_t *hwif = drive->hwif;
86 struct pci_dev *dev = to_pci_dev(hwif->dev); 85 struct pci_dev *dev = to_pci_dev(hwif->dev);
87 u8 maslave = 0x40; 86 u8 maslave = 0x40;
88 int a_speed = 3 << (drive->dn * 4); 87 int a_speed = 3 << (drive->dn * 4);
@@ -92,6 +91,7 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
92 int u_speed = 0; 91 int u_speed = 0;
93 u16 reg4042, reg4a; 92 u16 reg4042, reg4a;
94 u8 reg48, reg54, reg55; 93 u8 reg48, reg54, reg55;
94 const u8 speed = drive->dma_mode;
95 95
96 pci_read_config_word(dev, maslave, &reg4042); 96 pci_read_config_word(dev, maslave, &reg4042);
97 pci_read_config_byte(dev, 0x48, &reg48); 97 pci_read_config_byte(dev, 0x48, &reg48);
@@ -120,7 +120,6 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
120 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); 120 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
121 } else { 121 } else {
122 const u8 mwdma_to_pio[] = { 0, 3, 4 }; 122 const u8 mwdma_to_pio[] = { 0, 3, 4 };
123 u8 pio;
124 123
125 if (reg48 & u_flag) 124 if (reg48 & u_flag)
126 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); 125 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
@@ -132,11 +131,12 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
132 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 131 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
133 132
134 if (speed >= XFER_MW_DMA_0) 133 if (speed >= XFER_MW_DMA_0)
135 pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; 134 drive->pio_mode =
135 mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
136 else 136 else
137 pio = 2; /* only SWDMA2 is allowed */ 137 drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
138 138
139 it8213_set_pio_mode(drive, pio); 139 it8213_set_pio_mode(hwif, drive);
140 } 140 }
141} 141}
142 142
diff --git a/drivers/ide/it821x.c b/drivers/ide/it821x.c
index 51aa745246dc..b2709c733485 100644
--- a/drivers/ide/it821x.c
+++ b/drivers/ide/it821x.c
@@ -228,18 +228,18 @@ static void it821x_clock_strategy(ide_drive_t *drive)
228 228
229/** 229/**
230 * it821x_set_pio_mode - set host controller for PIO mode 230 * it821x_set_pio_mode - set host controller for PIO mode
231 * @hwif: port
231 * @drive: drive 232 * @drive: drive
232 * @pio: PIO mode number
233 * 233 *
234 * Tune the host to the desired PIO mode taking into the consideration 234 * Tune the host to the desired PIO mode taking into the consideration
235 * the maximum PIO mode supported by the other device on the cable. 235 * the maximum PIO mode supported by the other device on the cable.
236 */ 236 */
237 237
238static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio) 238static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
239{ 239{
240 ide_hwif_t *hwif = drive->hwif;
241 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 240 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
242 ide_drive_t *pair = ide_get_pair_dev(drive); 241 ide_drive_t *pair = ide_get_pair_dev(drive);
242 const u8 pio = drive->pio_mode - XFER_PIO_0;
243 u8 unit = drive->dn & 1, set_pio = pio; 243 u8 unit = drive->dn & 1, set_pio = pio;
244 244
245 /* Spec says 89 ref driver uses 88 */ 245 /* Spec says 89 ref driver uses 88 */
@@ -252,7 +252,7 @@ static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
252 * on the cable. 252 * on the cable.
253 */ 253 */
254 if (pair) { 254 if (pair) {
255 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); 255 u8 pair_pio = pair->pio_mode - XFER_PIO_0;
256 /* trim PIO to the slowest of the master/slave */ 256 /* trim PIO to the slowest of the master/slave */
257 if (pair_pio < set_pio) 257 if (pair_pio < set_pio)
258 set_pio = pair_pio; 258 set_pio = pair_pio;
@@ -393,14 +393,16 @@ static int it821x_dma_end(ide_drive_t *drive)
393 393
394/** 394/**
395 * it821x_set_dma_mode - set host controller for DMA mode 395 * it821x_set_dma_mode - set host controller for DMA mode
396 * @hwif: port
396 * @drive: drive 397 * @drive: drive
397 * @speed: DMA mode
398 * 398 *
399 * Tune the ITE chipset for the desired DMA mode. 399 * Tune the ITE chipset for the desired DMA mode.
400 */ 400 */
401 401
402static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed) 402static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
403{ 403{
404 const u8 speed = drive->dma_mode;
405
404 /* 406 /*
405 * MWDMA tuning is really hard because our MWDMA and PIO 407 * MWDMA tuning is really hard because our MWDMA and PIO
406 * timings are kept in the same place. We can switch in the 408 * timings are kept in the same place. We can switch in the
diff --git a/drivers/ide/jmicron.c b/drivers/ide/jmicron.c
index bf2be6431b20..74c2c4a6d909 100644
--- a/drivers/ide/jmicron.c
+++ b/drivers/ide/jmicron.c
@@ -80,19 +80,19 @@ static u8 jmicron_cable_detect(ide_hwif_t *hwif)
80 return ATA_CBL_PATA80; 80 return ATA_CBL_PATA80;
81} 81}
82 82
83static void jmicron_set_pio_mode(ide_drive_t *drive, const u8 pio) 83static void jmicron_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
84{ 84{
85} 85}
86 86
87/** 87/**
88 * jmicron_set_dma_mode - set host controller for DMA mode 88 * jmicron_set_dma_mode - set host controller for DMA mode
89 * @hwif: port
89 * @drive: drive 90 * @drive: drive
90 * @mode: DMA mode
91 * 91 *
92 * As the JMicron snoops for timings we don't need to do anything here. 92 * As the JMicron snoops for timings we don't need to do anything here.
93 */ 93 */
94 94
95static void jmicron_set_dma_mode(ide_drive_t *drive, const u8 mode) 95static void jmicron_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
96{ 96{
97} 97}
98 98
diff --git a/drivers/ide/opti621.c b/drivers/ide/opti621.c
index f1d70d6630fe..1a53a4c375ed 100644
--- a/drivers/ide/opti621.c
+++ b/drivers/ide/opti621.c
@@ -8,77 +8,6 @@
8 * Jan Harkes <jaharkes@cwi.nl>, 8 * Jan Harkes <jaharkes@cwi.nl>,
9 * Mark Lord <mlord@pobox.com> 9 * Mark Lord <mlord@pobox.com>
10 * Some parts of code are from ali14xx.c and from rz1000.c. 10 * Some parts of code are from ali14xx.c and from rz1000.c.
11 *
12 * OPTi is trademark of OPTi, Octek is trademark of Octek.
13 *
14 * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
15 * and disassembled/traced setupvic.exe (DOS program).
16 * It increases kernel code about 2 kB.
17 * I don't have this card no more, but I hope I can get some in case
18 * of needed development.
19 * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
20 * It has a place for a secondary connector in circuit, but nothing
21 * is there. Also BIOS says no address for
22 * secondary controller (see bellow in ide_init_opti621).
23 * I've only tested this on my system, which only has one disk.
24 * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
25 * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
26 * lockups). I tried the OCTEK double speed CD-ROM and
27 * it does not work! But I can't boot DOS also, so it's probably
28 * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
29 * problems) and Seagate 1GB (as slave, WD as master). My experiences
30 * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
31 * it slows to about 100kB/s! I don't know why and I have
32 * not this drive now, so I can't try it again.
33 * I write this driver because I lost the paper ("manual") with
34 * settings of jumpers on the card and I have to boot Linux with
35 * Loadlin except LILO, cause I have to run the setupvic.exe program
36 * already or I get disk errors (my test: rpm -Vf
37 * /usr/X11R6/bin/XF86_SVGA - or any big file).
38 * Some numbers from hdparm -t /dev/hda:
39 * Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
40 * Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
41 * I have 4 Megs/s before, but I don't know why (maybe changes
42 * in hdparm test).
43 * After release of 0.1, I got some successful reports, so it might work.
44 *
45 * The main problem with OPTi is that some timings for master
46 * and slave must be the same. For example, if you have master
47 * PIO 3 and slave PIO 0, driver have to set some timings of
48 * master for PIO 0. Second problem is that opti621_set_pio_mode
49 * got only one drive to set, but have to set both drives.
50 * This is solved in compute_pios. If you don't set
51 * the second drive, compute_pios use ide_get_best_pio_mode
52 * for autoselect mode (you can change it to PIO 0, if you want).
53 * If you then set the second drive to another PIO, the old value
54 * (automatically selected) will be overrided by yours.
55 * There is a 25/33MHz switch in configuration
56 * register, but driver is written for use at any frequency.
57 *
58 * Version 0.1, Nov 8, 1996
59 * by Jaromir Koutek, for 2.1.8.
60 * Initial version of driver.
61 *
62 * Version 0.2
63 * Number 0.2 skipped.
64 *
65 * Version 0.3, Nov 29, 1997
66 * by Mark Lord (probably), for 2.1.68
67 * Updates for use with new IDE block driver.
68 *
69 * Version 0.4, Dec 14, 1997
70 * by Jan Harkes
71 * Fixed some errors and cleaned the code.
72 *
73 * Version 0.5, Jan 2, 1998
74 * by Jaromir Koutek
75 * Updates for use with (again) new IDE block driver.
76 * Update of documentation.
77 *
78 * Version 0.6, Jan 2, 1999
79 * by Jaromir Koutek
80 * Reversed to version 0.3 of the driver, because
81 * 0.5 doesn't work.
82 */ 11 */
83 12
84#include <linux/types.h> 13#include <linux/types.h>
@@ -133,12 +62,12 @@ static u8 read_reg(int reg)
133 return ret; 62 return ret;
134} 63}
135 64
136static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) 65static void opti621_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
137{ 66{
138 ide_hwif_t *hwif = drive->hwif;
139 ide_drive_t *pair = ide_get_pair_dev(drive); 67 ide_drive_t *pair = ide_get_pair_dev(drive);
140 unsigned long flags; 68 unsigned long flags;
141 unsigned long mode = XFER_PIO_0 + pio, pair_mode; 69 unsigned long mode = drive->pio_mode, pair_mode;
70 const u8 pio = mode - XFER_PIO_0;
142 u8 tim, misc, addr_pio = pio, clk; 71 u8 tim, misc, addr_pio = pio, clk;
143 72
144 /* DRDY is default 2 (by OPTi Databook) */ 73 /* DRDY is default 2 (by OPTi Databook) */
diff --git a/drivers/ide/palm_bk3710.c b/drivers/ide/palm_bk3710.c
index f8eddf05ecb8..9e8f4e1b0cc9 100644
--- a/drivers/ide/palm_bk3710.c
+++ b/drivers/ide/palm_bk3710.c
@@ -166,7 +166,7 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
166 writel(val32, base + BK3710_DATRCVR); 166 writel(val32, base + BK3710_DATRCVR);
167 167
168 if (mate) { 168 if (mate) {
169 u8 mode2 = ide_get_best_pio_mode(mate, 255, 4); 169 u8 mode2 = mate->pio_mode - XFER_PIO_0;
170 170
171 if (mode2 < mode) 171 if (mode2 < mode)
172 mode = mode2; 172 mode = mode2;
@@ -188,10 +188,11 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
188 writel(val32, base + BK3710_REGRCVR); 188 writel(val32, base + BK3710_REGRCVR);
189} 189}
190 190
191static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed) 191static void palm_bk3710_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
192{ 192{
193 int is_slave = drive->dn & 1; 193 int is_slave = drive->dn & 1;
194 void __iomem *base = (void *)drive->hwif->dma_base; 194 void __iomem *base = (void *)hwif->dma_base;
195 const u8 xferspeed = drive->dma_mode;
195 196
196 if (xferspeed >= XFER_UDMA_0) { 197 if (xferspeed >= XFER_UDMA_0) {
197 palm_bk3710_setudmamode(base, is_slave, 198 palm_bk3710_setudmamode(base, is_slave,
@@ -203,12 +204,13 @@ static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
203 } 204 }
204} 205}
205 206
206static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio) 207static void palm_bk3710_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
207{ 208{
208 unsigned int cycle_time; 209 unsigned int cycle_time;
209 int is_slave = drive->dn & 1; 210 int is_slave = drive->dn & 1;
210 ide_drive_t *mate; 211 ide_drive_t *mate;
211 void __iomem *base = (void *)drive->hwif->dma_base; 212 void __iomem *base = (void *)hwif->dma_base;
213 const u8 pio = drive->pio_mode - XFER_PIO_0;
212 214
213 /* 215 /*
214 * Obtain the drive PIO data for tuning the Palm Chip registers 216 * Obtain the drive PIO data for tuning the Palm Chip registers
diff --git a/drivers/ide/pdc202xx_new.c b/drivers/ide/pdc202xx_new.c
index 65ba8239e7b5..9546fe2a93f7 100644
--- a/drivers/ide/pdc202xx_new.c
+++ b/drivers/ide/pdc202xx_new.c
@@ -129,11 +129,11 @@ static struct udma_timing {
129 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 129 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
130}; 130};
131 131
132static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed) 132static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
133{ 133{
134 ide_hwif_t *hwif = drive->hwif;
135 struct pci_dev *dev = to_pci_dev(hwif->dev); 134 struct pci_dev *dev = to_pci_dev(hwif->dev);
136 u8 adj = (drive->dn & 1) ? 0x08 : 0x00; 135 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
136 const u8 speed = drive->dma_mode;
137 137
138 /* 138 /*
139 * IDE core issues SETFEATURES_XFER to the drive first (thanks to 139 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
@@ -167,11 +167,11 @@ static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
167 } 167 }
168} 168}
169 169
170static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio) 170static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
171{ 171{
172 ide_hwif_t *hwif = drive->hwif;
173 struct pci_dev *dev = to_pci_dev(hwif->dev); 172 struct pci_dev *dev = to_pci_dev(hwif->dev);
174 u8 adj = (drive->dn & 1) ? 0x08 : 0x00; 173 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
174 const u8 pio = drive->pio_mode - XFER_PIO_0;
175 175
176 if (max_dma_rate(dev) == 4) { 176 if (max_dma_rate(dev) == 4) {
177 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c); 177 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c
index 35161dd840a0..c5f3841af360 100644
--- a/drivers/ide/pdc202xx_old.c
+++ b/drivers/ide/pdc202xx_old.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. 3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 4 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
5 * 5 *
6 * Portions Copyright (C) 1999 Promise Technology, Inc. 6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com) 7 * Author: Frank Tiernan (frankt@promise.com)
@@ -21,23 +21,15 @@
21 21
22#define DRV_NAME "pdc202xx_old" 22#define DRV_NAME "pdc202xx_old"
23 23
24static void pdc_old_disable_66MHz_clock(ide_hwif_t *); 24static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
25
26static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
27{ 25{
28 ide_hwif_t *hwif = drive->hwif;
29 struct pci_dev *dev = to_pci_dev(hwif->dev); 26 struct pci_dev *dev = to_pci_dev(hwif->dev);
30 u8 drive_pci = 0x60 + (drive->dn << 2); 27 u8 drive_pci = 0x60 + (drive->dn << 2);
28 const u8 speed = drive->dma_mode;
31 29
32 u8 AP = 0, BP = 0, CP = 0; 30 u8 AP = 0, BP = 0, CP = 0;
33 u8 TA = 0, TB = 0, TC = 0; 31 u8 TA = 0, TB = 0, TC = 0;
34 32
35 /*
36 * TODO: do this once per channel
37 */
38 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
39 pdc_old_disable_66MHz_clock(hwif);
40
41 pci_read_config_byte(dev, drive_pci, &AP); 33 pci_read_config_byte(dev, drive_pci, &AP);
42 pci_read_config_byte(dev, drive_pci + 1, &BP); 34 pci_read_config_byte(dev, drive_pci + 1, &BP);
43 pci_read_config_byte(dev, drive_pci + 2, &CP); 35 pci_read_config_byte(dev, drive_pci + 2, &CP);
@@ -84,9 +76,10 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
84 } 76 }
85} 77}
86 78
87static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 79static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
88{ 80{
89 pdc202xx_set_mode(drive, XFER_PIO_0 + pio); 81 drive->dma_mode = drive->pio_mode;
82 pdc202xx_set_mode(hwif, drive);
90} 83}
91 84
92static int pdc202xx_test_irq(ide_hwif_t *hwif) 85static int pdc202xx_test_irq(ide_hwif_t *hwif)
@@ -100,13 +93,13 @@ static int pdc202xx_test_irq(ide_hwif_t *hwif)
100 * bit 7: error, bit 6: interrupting, 93 * bit 7: error, bit 6: interrupting,
101 * bit 5: FIFO full, bit 4: FIFO empty 94 * bit 5: FIFO full, bit 4: FIFO empty
102 */ 95 */
103 return ((sc1d & 0x50) == 0x40) ? 1 : 0; 96 return ((sc1d & 0x50) == 0x50) ? 1 : 0;
104 } else { 97 } else {
105 /* 98 /*
106 * bit 3: error, bit 2: interrupting, 99 * bit 3: error, bit 2: interrupting,
107 * bit 1: FIFO full, bit 0: FIFO empty 100 * bit 1: FIFO full, bit 0: FIFO empty
108 */ 101 */
109 return ((sc1d & 0x05) == 0x04) ? 1 : 0; 102 return ((sc1d & 0x05) == 0x05) ? 1 : 0;
110 } 103 }
111} 104}
112 105
@@ -145,6 +138,11 @@ static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
145 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 138 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
146} 139}
147 140
141static void pdc2026x_init_hwif(ide_hwif_t *hwif)
142{
143 pdc_old_disable_66MHz_clock(hwif);
144}
145
148static void pdc202xx_dma_start(ide_drive_t *drive) 146static void pdc202xx_dma_start(ide_drive_t *drive)
149{ 147{
150 if (drive->current_speed > XFER_UDMA_2) 148 if (drive->current_speed > XFER_UDMA_2)
@@ -261,6 +259,7 @@ static const struct ide_dma_ops pdc2026x_dma_ops = {
261 { \ 259 { \
262 .name = DRV_NAME, \ 260 .name = DRV_NAME, \
263 .init_chipset = init_chipset_pdc202xx, \ 261 .init_chipset = init_chipset_pdc202xx, \
262 .init_hwif = pdc2026x_init_hwif, \
264 .port_ops = &pdc2026x_port_ops, \ 263 .port_ops = &pdc2026x_port_ops, \
265 .dma_ops = &pdc2026x_dma_ops, \ 264 .dma_ops = &pdc2026x_dma_ops, \
266 .host_flags = IDE_HFLAGS_PDC202XX, \ 265 .host_flags = IDE_HFLAGS_PDC202XX, \
@@ -356,6 +355,6 @@ static void __exit pdc202xx_ide_exit(void)
356module_init(pdc202xx_ide_init); 355module_init(pdc202xx_ide_init);
357module_exit(pdc202xx_ide_exit); 356module_exit(pdc202xx_ide_exit);
358 357
359MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); 358MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
360MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); 359MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
361MODULE_LICENSE("GPL"); 360MODULE_LICENSE("GPL");
diff --git a/drivers/ide/piix.c b/drivers/ide/piix.c
index bf14f39bd3a7..1bdca49e5a03 100644
--- a/drivers/ide/piix.c
+++ b/drivers/ide/piix.c
@@ -59,15 +59,14 @@ static int no_piix_dma;
59 59
60/** 60/**
61 * piix_set_pio_mode - set host controller for PIO mode 61 * piix_set_pio_mode - set host controller for PIO mode
62 * @port: port
62 * @drive: drive 63 * @drive: drive
63 * @pio: PIO mode number
64 * 64 *
65 * Set the interface PIO mode based upon the settings done by AMI BIOS. 65 * Set the interface PIO mode based upon the settings done by AMI BIOS.
66 */ 66 */
67 67
68static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio) 68static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
69{ 69{
70 ide_hwif_t *hwif = drive->hwif;
71 struct pci_dev *dev = to_pci_dev(hwif->dev); 70 struct pci_dev *dev = to_pci_dev(hwif->dev);
72 int is_slave = drive->dn & 1; 71 int is_slave = drive->dn & 1;
73 int master_port = hwif->channel ? 0x42 : 0x40; 72 int master_port = hwif->channel ? 0x42 : 0x40;
@@ -77,6 +76,7 @@ static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
77 u8 slave_data; 76 u8 slave_data;
78 static DEFINE_SPINLOCK(tune_lock); 77 static DEFINE_SPINLOCK(tune_lock);
79 int control = 0; 78 int control = 0;
79 const u8 pio = drive->pio_mode - XFER_PIO_0;
80 80
81 /* ISP RTC */ 81 /* ISP RTC */
82 static const u8 timings[][2]= { 82 static const u8 timings[][2]= {
@@ -127,16 +127,15 @@ static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
127 127
128/** 128/**
129 * piix_set_dma_mode - set host controller for DMA mode 129 * piix_set_dma_mode - set host controller for DMA mode
130 * @hwif: port
130 * @drive: drive 131 * @drive: drive
131 * @speed: DMA mode
132 * 132 *
133 * Set a PIIX host controller to the desired DMA mode. This involves 133 * Set a PIIX host controller to the desired DMA mode. This involves
134 * programming the right timing data into the PCI configuration space. 134 * programming the right timing data into the PCI configuration space.
135 */ 135 */
136 136
137static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) 137static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
138{ 138{
139 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev); 139 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 u8 maslave = hwif->channel ? 0x42 : 0x40; 140 u8 maslave = hwif->channel ? 0x42 : 0x40;
142 int a_speed = 3 << (drive->dn * 4); 141 int a_speed = 3 << (drive->dn * 4);
@@ -147,6 +146,7 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
147 int sitre; 146 int sitre;
148 u16 reg4042, reg4a; 147 u16 reg4042, reg4a;
149 u8 reg48, reg54, reg55; 148 u8 reg48, reg54, reg55;
149 const u8 speed = drive->dma_mode;
150 150
151 pci_read_config_word(dev, maslave, &reg4042); 151 pci_read_config_word(dev, maslave, &reg4042);
152 sitre = (reg4042 & 0x4000) ? 1 : 0; 152 sitre = (reg4042 & 0x4000) ? 1 : 0;
@@ -176,7 +176,6 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
176 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); 176 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
177 } else { 177 } else {
178 const u8 mwdma_to_pio[] = { 0, 3, 4 }; 178 const u8 mwdma_to_pio[] = { 0, 3, 4 };
179 u8 pio;
180 179
181 if (reg48 & u_flag) 180 if (reg48 & u_flag)
182 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); 181 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
@@ -188,11 +187,12 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
188 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 187 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
189 188
190 if (speed >= XFER_MW_DMA_0) 189 if (speed >= XFER_MW_DMA_0)
191 pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; 190 drive->pio_mode =
191 mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
192 else 192 else
193 pio = 2; /* only SWDMA2 is allowed */ 193 drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
194 194
195 piix_set_pio_mode(drive, pio); 195 piix_set_pio_mode(hwif, drive);
196 } 196 }
197} 197}
198 198
diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c
index 7a4e788cab2f..850ee452e9bb 100644
--- a/drivers/ide/pmac.c
+++ b/drivers/ide/pmac.c
@@ -496,12 +496,11 @@ static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
496/* 496/*
497 * Old tuning functions (called on hdparm -p), sets up drive PIO timings 497 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
498 */ 498 */
499static void 499static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
500pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
501{ 500{
502 ide_hwif_t *hwif = drive->hwif;
503 pmac_ide_hwif_t *pmif = 501 pmac_ide_hwif_t *pmif =
504 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 502 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
503 const u8 pio = drive->pio_mode - XFER_PIO_0;
505 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio); 504 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
506 u32 *timings, t; 505 u32 *timings, t;
507 unsigned accessTicks, recTicks; 506 unsigned accessTicks, recTicks;
@@ -778,14 +777,14 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
778#endif 777#endif
779} 778}
780 779
781static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) 780static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
782{ 781{
783 ide_hwif_t *hwif = drive->hwif;
784 pmac_ide_hwif_t *pmif = 782 pmac_ide_hwif_t *pmif =
785 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 783 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
786 int ret = 0; 784 int ret = 0;
787 u32 *timings, *timings2, tl[2]; 785 u32 *timings, *timings2, tl[2];
788 u8 unit = drive->dn & 1; 786 u8 unit = drive->dn & 1;
787 const u8 speed = drive->dma_mode;
789 788
790 timings = &pmif->timings[unit]; 789 timings = &pmif->timings[unit];
791 timings2 = &pmif->timings[unit+2]; 790 timings2 = &pmif->timings[unit+2];
@@ -1651,8 +1650,8 @@ pmac_ide_dma_test_irq (ide_drive_t *drive)
1651 if ((status & FLUSH) == 0) 1650 if ((status & FLUSH) == 0)
1652 break; 1651 break;
1653 if (++timeout > 100) { 1652 if (++timeout > 100) {
1654 printk(KERN_WARNING "ide%d, ide_dma_test_irq \ 1653 printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
1655 timeout flushing channel\n", hwif->index); 1654 hwif->index);
1656 break; 1655 break;
1657 } 1656 }
1658 } 1657 }
diff --git a/drivers/ide/qd65xx.c b/drivers/ide/qd65xx.c
index 74696edc8d1d..3f0244fd8e62 100644
--- a/drivers/ide/qd65xx.c
+++ b/drivers/ide/qd65xx.c
@@ -189,15 +189,13 @@ static void qd_set_timing (ide_drive_t *drive, u8 timing)
189 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing); 189 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing);
190} 190}
191 191
192static void qd6500_set_pio_mode(ide_drive_t *drive, const u8 pio) 192static void qd6500_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
193{ 193{
194 u16 *id = drive->id; 194 u16 *id = drive->id;
195 int active_time = 175; 195 int active_time = 175;
196 int recovery_time = 415; /* worst case values from the dos driver */ 196 int recovery_time = 415; /* worst case values from the dos driver */
197 197
198 /* 198 /* FIXME: use drive->pio_mode value */
199 * FIXME: use "pio" value
200 */
201 if (!qd_find_disk_type(drive, &active_time, &recovery_time) && 199 if (!qd_find_disk_type(drive, &active_time, &recovery_time) &&
202 (id[ATA_ID_OLD_PIO_MODES] & 0xff) && (id[ATA_ID_FIELD_VALID] & 2) && 200 (id[ATA_ID_OLD_PIO_MODES] & 0xff) && (id[ATA_ID_FIELD_VALID] & 2) &&
203 id[ATA_ID_EIDE_PIO] >= 240) { 201 id[ATA_ID_EIDE_PIO] >= 240) {
@@ -211,9 +209,9 @@ static void qd6500_set_pio_mode(ide_drive_t *drive, const u8 pio)
211 active_time, recovery_time)); 209 active_time, recovery_time));
212} 210}
213 211
214static void qd6580_set_pio_mode(ide_drive_t *drive, const u8 pio) 212static void qd6580_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
215{ 213{
216 ide_hwif_t *hwif = drive->hwif; 214 const u8 pio = drive->pio_mode - XFER_PIO_0;
217 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 215 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
218 unsigned int cycle_time; 216 unsigned int cycle_time;
219 int active_time = 175; 217 int active_time = 175;
diff --git a/drivers/ide/sc1200.c b/drivers/ide/sc1200.c
index d467478d68da..134f1fd13866 100644
--- a/drivers/ide/sc1200.c
+++ b/drivers/ide/sc1200.c
@@ -122,13 +122,13 @@ out:
122 return mask; 122 return mask;
123} 123}
124 124
125static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode) 125static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
126{ 126{
127 ide_hwif_t *hwif = drive->hwif;
128 struct pci_dev *dev = to_pci_dev(hwif->dev); 127 struct pci_dev *dev = to_pci_dev(hwif->dev);
129 unsigned int reg, timings; 128 unsigned int reg, timings;
130 unsigned short pci_clock; 129 unsigned short pci_clock;
131 unsigned int basereg = hwif->channel ? 0x50 : 0x40; 130 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
131 const u8 mode = drive->dma_mode;
132 132
133 static const u32 udma_timing[3][3] = { 133 static const u32 udma_timing[3][3] = {
134 { 0x00921250, 0x00911140, 0x00911030 }, 134 { 0x00921250, 0x00911140, 0x00911030 },
@@ -193,10 +193,10 @@ static int sc1200_dma_end(ide_drive_t *drive)
193 * will have valid default PIO timings set up before we get here. 193 * will have valid default PIO timings set up before we get here.
194 */ 194 */
195 195
196static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio) 196static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
197{ 197{
198 ide_hwif_t *hwif = drive->hwif;
199 int mode = -1; 198 int mode = -1;
199 const u8 pio = drive->pio_mode - XFER_PIO_0;
200 200
201 /* 201 /*
202 * bad abuse of ->set_pio_mode interface 202 * bad abuse of ->set_pio_mode interface
diff --git a/drivers/ide/scc_pata.c b/drivers/ide/scc_pata.c
index 1104bb301eb9..b7f5b0c4310c 100644
--- a/drivers/ide/scc_pata.c
+++ b/drivers/ide/scc_pata.c
@@ -199,16 +199,15 @@ scc_ide_outsl(unsigned long port, void *addr, u32 count)
199 199
200/** 200/**
201 * scc_set_pio_mode - set host controller for PIO mode 201 * scc_set_pio_mode - set host controller for PIO mode
202 * @hwif: port
202 * @drive: drive 203 * @drive: drive
203 * @pio: PIO mode number
204 * 204 *
205 * Load the timing settings for this device mode into the 205 * Load the timing settings for this device mode into the
206 * controller. 206 * controller.
207 */ 207 */
208 208
209static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) 209static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
210{ 210{
211 ide_hwif_t *hwif = drive->hwif;
212 struct scc_ports *ports = ide_get_hwifdata(hwif); 211 struct scc_ports *ports = ide_get_hwifdata(hwif);
213 unsigned long ctl_base = ports->ctl; 212 unsigned long ctl_base = ports->ctl;
214 unsigned long cckctrl_port = ctl_base + 0xff0; 213 unsigned long cckctrl_port = ctl_base + 0xff0;
@@ -216,6 +215,7 @@ static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
216 unsigned long pioct_port = ctl_base + 0x004; 215 unsigned long pioct_port = ctl_base + 0x004;
217 unsigned long reg; 216 unsigned long reg;
218 int offset; 217 int offset;
218 const u8 pio = drive->pio_mode - XFER_PIO_0;
219 219
220 reg = in_be32((void __iomem *)cckctrl_port); 220 reg = in_be32((void __iomem *)cckctrl_port);
221 if (reg & CCKCTRL_ATACLKOEN) { 221 if (reg & CCKCTRL_ATACLKOEN) {
@@ -231,16 +231,15 @@ static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
231 231
232/** 232/**
233 * scc_set_dma_mode - set host controller for DMA mode 233 * scc_set_dma_mode - set host controller for DMA mode
234 * @hwif: port
234 * @drive: drive 235 * @drive: drive
235 * @speed: DMA mode
236 * 236 *
237 * Load the timing settings for this device mode into the 237 * Load the timing settings for this device mode into the
238 * controller. 238 * controller.
239 */ 239 */
240 240
241static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) 241static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
242{ 242{
243 ide_hwif_t *hwif = drive->hwif;
244 struct scc_ports *ports = ide_get_hwifdata(hwif); 243 struct scc_ports *ports = ide_get_hwifdata(hwif);
245 unsigned long ctl_base = ports->ctl; 244 unsigned long ctl_base = ports->ctl;
246 unsigned long cckctrl_port = ctl_base + 0xff0; 245 unsigned long cckctrl_port = ctl_base + 0xff0;
@@ -254,6 +253,7 @@ static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
254 int offset, idx; 253 int offset, idx;
255 unsigned long reg; 254 unsigned long reg;
256 unsigned long jcactsel; 255 unsigned long jcactsel;
256 const u8 speed = drive->dma_mode;
257 257
258 reg = in_be32((void __iomem *)cckctrl_port); 258 reg = in_be32((void __iomem *)cckctrl_port);
259 if (reg & CCKCTRL_ATACLKOEN) { 259 if (reg & CCKCTRL_ATACLKOEN) {
@@ -872,20 +872,18 @@ static struct pci_driver scc_pci_driver = {
872 .remove = __devexit_p(scc_remove), 872 .remove = __devexit_p(scc_remove),
873}; 873};
874 874
875static int scc_ide_init(void) 875static int __init scc_ide_init(void)
876{ 876{
877 return ide_pci_register_driver(&scc_pci_driver); 877 return ide_pci_register_driver(&scc_pci_driver);
878} 878}
879 879
880module_init(scc_ide_init); 880static void __exit scc_ide_exit(void)
881/* -- No exit code?
882static void scc_ide_exit(void)
883{ 881{
884 ide_pci_unregister_driver(&scc_pci_driver); 882 pci_unregister_driver(&scc_pci_driver);
885} 883}
886module_exit(scc_ide_exit);
887 */
888 884
885module_init(scc_ide_init);
886module_exit(scc_ide_exit);
889 887
890MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); 888MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
891MODULE_LICENSE("GPL"); 889MODULE_LICENSE("GPL");
diff --git a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c
index b6554ef92716..35fb8dabb55d 100644
--- a/drivers/ide/serverworks.c
+++ b/drivers/ide/serverworks.c
@@ -2,7 +2,7 @@
2 * Copyright (C) 1998-2000 Michel Aubry 2 * Copyright (C) 1998-2000 Michel Aubry
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 5 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
6 * Portions copyright (c) 2001 Sun Microsystems 6 * Portions copyright (c) 2001 Sun Microsystems
7 * 7 *
8 * 8 *
@@ -52,8 +52,6 @@ static const char *svwks_bad_ata100[] = {
52 NULL 52 NULL
53}; 53};
54 54
55static struct pci_dev *isa_dev;
56
57static int check_in_drive_lists (ide_drive_t *drive, const char **list) 55static int check_in_drive_lists (ide_drive_t *drive, const char **list)
58{ 56{
59 char *m = (char *)&drive->id[ATA_ID_PROD]; 57 char *m = (char *)&drive->id[ATA_ID_PROD];
@@ -67,26 +65,14 @@ static int check_in_drive_lists (ide_drive_t *drive, const char **list)
67static u8 svwks_udma_filter(ide_drive_t *drive) 65static u8 svwks_udma_filter(ide_drive_t *drive)
68{ 66{
69 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 67 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
70 u8 mask = 0;
71 68
72 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) 69 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
73 return 0x1f; 70 return 0x1f;
74 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
75 u32 reg = 0;
76 if (isa_dev)
77 pci_read_config_dword(isa_dev, 0x64, &reg);
78
79 /*
80 * Don't enable UDMA on disk devices for the moment
81 */
82 if(drive->media == ide_disk)
83 return 0;
84 /* Check the OSB4 DMA33 enable bit */
85 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
86 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { 71 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
87 return 0x07; 72 return 0x07;
88 } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { 73 } else {
89 u8 btr = 0, mode; 74 u8 btr = 0, mode, mask;
75
90 pci_read_config_byte(dev, 0x5A, &btr); 76 pci_read_config_byte(dev, 0x5A, &btr);
91 mode = btr & 0x3; 77 mode = btr & 0x3;
92 78
@@ -101,13 +87,9 @@ static u8 svwks_udma_filter(ide_drive_t *drive)
101 case 1: mask = 0x07; break; 87 case 1: mask = 0x07; break;
102 default: mask = 0x00; break; 88 default: mask = 0x00; break;
103 } 89 }
104 }
105 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
106 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
107 (!(PCI_FUNC(dev->devfn) & 1)))
108 mask = 0x1f;
109 90
110 return mask; 91 return mask;
92 }
111} 93}
112 94
113static u8 svwks_csb_check (struct pci_dev *dev) 95static u8 svwks_csb_check (struct pci_dev *dev)
@@ -124,12 +106,13 @@ static u8 svwks_csb_check (struct pci_dev *dev)
124 return 0; 106 return 0;
125} 107}
126 108
127static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) 109static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
128{ 110{
129 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 111 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
130 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; 112 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
131 113
132 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 114 struct pci_dev *dev = to_pci_dev(hwif->dev);
115 const u8 pio = drive->pio_mode - XFER_PIO_0;
133 116
134 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); 117 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
135 118
@@ -145,14 +128,14 @@ static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
145 } 128 }
146} 129}
147 130
148static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) 131static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
149{ 132{
150 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; 133 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
151 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; 134 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
152 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; 135 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
153 136
154 ide_hwif_t *hwif = drive->hwif;
155 struct pci_dev *dev = to_pci_dev(hwif->dev); 137 struct pci_dev *dev = to_pci_dev(hwif->dev);
138 const u8 speed = drive->dma_mode;
156 u8 unit = drive->dn & 1; 139 u8 unit = drive->dn & 1;
157 140
158 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; 141 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
@@ -185,8 +168,9 @@ static int init_chipset_svwks(struct pci_dev *dev)
185 168
186 /* OSB4 : South Bridge and IDE */ 169 /* OSB4 : South Bridge and IDE */
187 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 170 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
188 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 171 struct pci_dev *isa_dev =
189 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 172 pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
173 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
190 if (isa_dev) { 174 if (isa_dev) {
191 pci_read_config_dword(isa_dev, 0x64, &reg); 175 pci_read_config_dword(isa_dev, 0x64, &reg);
192 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 176 reg &= ~0x00002000; /* disable 600ns interrupt mask */
@@ -195,6 +179,7 @@ static int init_chipset_svwks(struct pci_dev *dev)
195 "enabled.\n", pci_name(dev)); 179 "enabled.\n", pci_name(dev));
196 reg |= 0x00004000; /* enable UDMA/33 support */ 180 reg |= 0x00004000; /* enable UDMA/33 support */
197 pci_write_config_dword(isa_dev, 0x64, reg); 181 pci_write_config_dword(isa_dev, 0x64, reg);
182 pci_dev_put(isa_dev);
198 } 183 }
199 } 184 }
200 185
@@ -343,7 +328,6 @@ static u8 svwks_cable_detect(ide_hwif_t *hwif)
343static const struct ide_port_ops osb4_port_ops = { 328static const struct ide_port_ops osb4_port_ops = {
344 .set_pio_mode = svwks_set_pio_mode, 329 .set_pio_mode = svwks_set_pio_mode,
345 .set_dma_mode = svwks_set_dma_mode, 330 .set_dma_mode = svwks_set_dma_mode,
346 .udma_filter = svwks_udma_filter,
347}; 331};
348 332
349static const struct ide_port_ops svwks_port_ops = { 333static const struct ide_port_ops svwks_port_ops = {
@@ -460,6 +444,6 @@ static void __exit svwks_ide_exit(void)
460module_init(svwks_ide_init); 444module_init(svwks_ide_init);
461module_exit(svwks_ide_exit); 445module_exit(svwks_ide_exit);
462 446
463MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); 447MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
464MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); 448MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
465MODULE_LICENSE("GPL"); 449MODULE_LICENSE("GPL");
diff --git a/drivers/ide/sgiioc4.c b/drivers/ide/sgiioc4.c
index b7d61dc64096..e3ea591f66d3 100644
--- a/drivers/ide/sgiioc4.c
+++ b/drivers/ide/sgiioc4.c
@@ -255,7 +255,7 @@ static int sgiioc4_dma_end(ide_drive_t *drive)
255 return dma_stat; 255 return dma_stat;
256} 256}
257 257
258static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed) 258static void sgiioc4_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
259{ 259{
260} 260}
261 261
diff --git a/drivers/ide/siimage.c b/drivers/ide/siimage.c
index d95df528562f..ddeda444a27a 100644
--- a/drivers/ide/siimage.c
+++ b/drivers/ide/siimage.c
@@ -229,19 +229,18 @@ static u8 sil_sata_udma_filter(ide_drive_t *drive)
229 229
230/** 230/**
231 * sil_set_pio_mode - set host controller for PIO mode 231 * sil_set_pio_mode - set host controller for PIO mode
232 * @hwif: port
232 * @drive: drive 233 * @drive: drive
233 * @pio: PIO mode number
234 * 234 *
235 * Load the timing settings for this device mode into the 235 * Load the timing settings for this device mode into the
236 * controller. 236 * controller.
237 */ 237 */
238 238
239static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) 239static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
240{ 240{
241 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; 241 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
242 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 242 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
243 243
244 ide_hwif_t *hwif = drive->hwif;
245 struct pci_dev *dev = to_pci_dev(hwif->dev); 244 struct pci_dev *dev = to_pci_dev(hwif->dev);
246 ide_drive_t *pair = ide_get_pair_dev(drive); 245 ide_drive_t *pair = ide_get_pair_dev(drive);
247 u32 speedt = 0; 246 u32 speedt = 0;
@@ -249,6 +248,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
249 unsigned long addr = siimage_seldev(drive, 0x04); 248 unsigned long addr = siimage_seldev(drive, 0x04);
250 unsigned long tfaddr = siimage_selreg(hwif, 0x02); 249 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
251 unsigned long base = (unsigned long)hwif->hwif_data; 250 unsigned long base = (unsigned long)hwif->hwif_data;
251 const u8 pio = drive->pio_mode - XFER_PIO_0;
252 u8 tf_pio = pio; 252 u8 tf_pio = pio;
253 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 253 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
254 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) 254 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
@@ -258,7 +258,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
258 258
259 /* trim *taskfile* PIO to the slowest of the master/slave */ 259 /* trim *taskfile* PIO to the slowest of the master/slave */
260 if (pair) { 260 if (pair) {
261 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); 261 u8 pair_pio = pair->pio_mode - XFER_PIO_0;
262 262
263 if (pair_pio < tf_pio) 263 if (pair_pio < tf_pio)
264 tf_pio = pair_pio; 264 tf_pio = pair_pio;
@@ -289,19 +289,18 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
289 289
290/** 290/**
291 * sil_set_dma_mode - set host controller for DMA mode 291 * sil_set_dma_mode - set host controller for DMA mode
292 * @hwif: port
292 * @drive: drive 293 * @drive: drive
293 * @speed: DMA mode
294 * 294 *
295 * Tune the SiI chipset for the desired DMA mode. 295 * Tune the SiI chipset for the desired DMA mode.
296 */ 296 */
297 297
298static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) 298static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
299{ 299{
300 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; 300 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
301 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; 301 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
302 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; 302 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
303 303
304 ide_hwif_t *hwif = drive->hwif;
305 struct pci_dev *dev = to_pci_dev(hwif->dev); 304 struct pci_dev *dev = to_pci_dev(hwif->dev);
306 unsigned long base = (unsigned long)hwif->hwif_data; 305 unsigned long base = (unsigned long)hwif->hwif_data;
307 u16 ultra = 0, multi = 0; 306 u16 ultra = 0, multi = 0;
@@ -311,6 +310,7 @@ static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
311 : (mmio ? 0xB4 : 0x80); 310 : (mmio ? 0xB4 : 0x80);
312 unsigned long ma = siimage_seldev(drive, 0x08); 311 unsigned long ma = siimage_seldev(drive, 0x08);
313 unsigned long ua = siimage_seldev(drive, 0x0C); 312 unsigned long ua = siimage_seldev(drive, 0x0C);
313 const u8 speed = drive->dma_mode;
314 314
315 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); 315 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
316 mode = sil_ioread8 (dev, base + addr_mask); 316 mode = sil_ioread8 (dev, base + addr_mask);
diff --git a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c
index 468706082fb5..db7f4e761dbc 100644
--- a/drivers/ide/sis5513.c
+++ b/drivers/ide/sis5513.c
@@ -290,10 +290,10 @@ static void config_drive_art_rwp(ide_drive_t *drive)
290 pci_write_config_byte(dev, 0x4b, rw_prefetch); 290 pci_write_config_byte(dev, 0x4b, rw_prefetch);
291} 291}
292 292
293static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio) 293static void sis_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
294{ 294{
295 config_drive_art_rwp(drive); 295 config_drive_art_rwp(drive);
296 sis_program_timings(drive, XFER_PIO_0 + pio); 296 sis_program_timings(drive, drive->pio_mode);
297} 297}
298 298
299static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode) 299static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
@@ -340,8 +340,10 @@ static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
340 sis_ata33_program_udma_timings(drive, mode); 340 sis_ata33_program_udma_timings(drive, mode);
341} 341}
342 342
343static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) 343static void sis_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
344{ 344{
345 const u8 speed = drive->dma_mode;
346
345 if (speed >= XFER_UDMA_0) 347 if (speed >= XFER_UDMA_0)
346 sis_program_udma_timings(drive, speed); 348 sis_program_udma_timings(drive, speed);
347 else 349 else
diff --git a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c
index 3c2bbf0057ea..f21dc2ad7682 100644
--- a/drivers/ide/sl82c105.c
+++ b/drivers/ide/sl82c105.c
@@ -63,12 +63,13 @@ static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
63/* 63/*
64 * Configure the chipset for PIO mode. 64 * Configure the chipset for PIO mode.
65 */ 65 */
66static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) 66static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
67{ 67{
68 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 68 struct pci_dev *dev = to_pci_dev(hwif->dev);
69 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 69 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
70 int reg = 0x44 + drive->dn * 4; 70 int reg = 0x44 + drive->dn * 4;
71 u16 drv_ctrl; 71 u16 drv_ctrl;
72 const u8 pio = drive->pio_mode - XFER_PIO_0;
72 73
73 drv_ctrl = get_pio_timings(drive, pio); 74 drv_ctrl = get_pio_timings(drive, pio);
74 75
@@ -91,11 +92,12 @@ static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
91/* 92/*
92 * Configure the chipset for DMA mode. 93 * Configure the chipset for DMA mode.
93 */ 94 */
94static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) 95static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
95{ 96{
96 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; 97 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
97 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 98 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
98 u16 drv_ctrl; 99 u16 drv_ctrl;
100 const u8 speed = drive->dma_mode;
99 101
100 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; 102 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
101 103
diff --git a/drivers/ide/slc90e66.c b/drivers/ide/slc90e66.c
index 1ccfb40e7215..864ffe0e26d9 100644
--- a/drivers/ide/slc90e66.c
+++ b/drivers/ide/slc90e66.c
@@ -18,9 +18,8 @@
18 18
19static DEFINE_SPINLOCK(slc90e66_lock); 19static DEFINE_SPINLOCK(slc90e66_lock);
20 20
21static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio) 21static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
22{ 22{
23 ide_hwif_t *hwif = drive->hwif;
24 struct pci_dev *dev = to_pci_dev(hwif->dev); 23 struct pci_dev *dev = to_pci_dev(hwif->dev);
25 int is_slave = drive->dn & 1; 24 int is_slave = drive->dn & 1;
26 int master_port = hwif->channel ? 0x42 : 0x40; 25 int master_port = hwif->channel ? 0x42 : 0x40;
@@ -29,6 +28,8 @@ static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
29 u16 master_data; 28 u16 master_data;
30 u8 slave_data; 29 u8 slave_data;
31 int control = 0; 30 int control = 0;
31 const u8 pio = drive->pio_mode - XFER_PIO_0;
32
32 /* ISP RTC */ 33 /* ISP RTC */
33 static const u8 timings[][2] = { 34 static const u8 timings[][2] = {
34 { 0, 0 }, 35 { 0, 0 },
@@ -71,14 +72,14 @@ static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
71 spin_unlock_irqrestore(&slc90e66_lock, flags); 72 spin_unlock_irqrestore(&slc90e66_lock, flags);
72} 73}
73 74
74static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) 75static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
75{ 76{
76 ide_hwif_t *hwif = drive->hwif;
77 struct pci_dev *dev = to_pci_dev(hwif->dev); 77 struct pci_dev *dev = to_pci_dev(hwif->dev);
78 u8 maslave = hwif->channel ? 0x42 : 0x40; 78 u8 maslave = hwif->channel ? 0x42 : 0x40;
79 int sitre = 0, a_speed = 7 << (drive->dn * 4); 79 int sitre = 0, a_speed = 7 << (drive->dn * 4);
80 int u_speed = 0, u_flag = 1 << drive->dn; 80 int u_speed = 0, u_flag = 1 << drive->dn;
81 u16 reg4042, reg44, reg48, reg4a; 81 u16 reg4042, reg44, reg48, reg4a;
82 const u8 speed = drive->dma_mode;
82 83
83 pci_read_config_word(dev, maslave, &reg4042); 84 pci_read_config_word(dev, maslave, &reg4042);
84 sitre = (reg4042 & 0x4000) ? 1 : 0; 85 sitre = (reg4042 & 0x4000) ? 1 : 0;
@@ -98,7 +99,6 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
98 } 99 }
99 } else { 100 } else {
100 const u8 mwdma_to_pio[] = { 0, 3, 4 }; 101 const u8 mwdma_to_pio[] = { 0, 3, 4 };
101 u8 pio;
102 102
103 if (reg48 & u_flag) 103 if (reg48 & u_flag)
104 pci_write_config_word(dev, 0x48, reg48 & ~u_flag); 104 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
@@ -106,11 +106,12 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
106 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); 106 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
107 107
108 if (speed >= XFER_MW_DMA_0) 108 if (speed >= XFER_MW_DMA_0)
109 pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; 109 drive->pio_mode =
110 mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
110 else 111 else
111 pio = 2; /* only SWDMA2 is allowed */ 112 drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
112 113
113 slc90e66_set_pio_mode(drive, pio); 114 slc90e66_set_pio_mode(hwif, drive);
114 } 115 }
115} 116}
116 117
diff --git a/drivers/ide/tc86c001.c b/drivers/ide/tc86c001.c
index 05a93d6baecc..e444d24934b3 100644
--- a/drivers/ide/tc86c001.c
+++ b/drivers/ide/tc86c001.c
@@ -13,11 +13,11 @@
13 13
14#define DRV_NAME "tc86c001" 14#define DRV_NAME "tc86c001"
15 15
16static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed) 16static void tc86c001_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
17{ 17{
18 ide_hwif_t *hwif = drive->hwif;
19 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00); 18 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
20 u16 mode, scr = inw(scr_port); 19 u16 mode, scr = inw(scr_port);
20 const u8 speed = drive->dma_mode;
21 21
22 switch (speed) { 22 switch (speed) {
23 case XFER_UDMA_4: mode = 0x00c0; break; 23 case XFER_UDMA_4: mode = 0x00c0; break;
@@ -41,9 +41,10 @@ static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed)
41 outw(scr, scr_port); 41 outw(scr, scr_port);
42} 42}
43 43
44static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio) 44static void tc86c001_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
45{ 45{
46 tc86c001_set_mode(drive, XFER_PIO_0 + pio); 46 drive->dma_mode = drive->pio_mode;
47 tc86c001_set_mode(hwif, drive);
47} 48}
48 49
49/* 50/*
diff --git a/drivers/ide/triflex.c b/drivers/ide/triflex.c
index 8773c3ba7462..7953447eae0f 100644
--- a/drivers/ide/triflex.c
+++ b/drivers/ide/triflex.c
@@ -34,9 +34,8 @@
34 34
35#define DRV_NAME "triflex" 35#define DRV_NAME "triflex"
36 36
37static void triflex_set_mode(ide_drive_t *drive, const u8 speed) 37static void triflex_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
38{ 38{
39 ide_hwif_t *hwif = drive->hwif;
40 struct pci_dev *dev = to_pci_dev(hwif->dev); 39 struct pci_dev *dev = to_pci_dev(hwif->dev);
41 u32 triflex_timings = 0; 40 u32 triflex_timings = 0;
42 u16 timing = 0; 41 u16 timing = 0;
@@ -44,7 +43,7 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed)
44 43
45 pci_read_config_dword(dev, channel_offset, &triflex_timings); 44 pci_read_config_dword(dev, channel_offset, &triflex_timings);
46 45
47 switch(speed) { 46 switch (drive->dma_mode) {
48 case XFER_MW_DMA_2: 47 case XFER_MW_DMA_2:
49 timing = 0x0103; 48 timing = 0x0103;
50 break; 49 break;
@@ -82,9 +81,10 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed)
82 pci_write_config_dword(dev, channel_offset, triflex_timings); 81 pci_write_config_dword(dev, channel_offset, triflex_timings);
83} 82}
84 83
85static void triflex_set_pio_mode(ide_drive_t *drive, const u8 pio) 84static void triflex_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
86{ 85{
87 triflex_set_mode(drive, XFER_PIO_0 + pio); 86 drive->dma_mode = drive->pio_mode;
87 triflex_set_mode(hwif, drive);
88} 88}
89 89
90static const struct ide_port_ops triflex_port_ops = { 90static const struct ide_port_ops triflex_port_ops = {
diff --git a/drivers/ide/tx4938ide.c b/drivers/ide/tx4938ide.c
index fd59c0d235b5..1d80f1fdbc97 100644
--- a/drivers/ide/tx4938ide.c
+++ b/drivers/ide/tx4938ide.c
@@ -56,16 +56,15 @@ static void tx4938ide_tune_ebusc(unsigned int ebus_ch,
56 &tx4938_ebuscptr->cr[ebus_ch]); 56 &tx4938_ebuscptr->cr[ebus_ch]);
57} 57}
58 58
59static void tx4938ide_set_pio_mode(ide_drive_t *drive, const u8 pio) 59static void tx4938ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
60{ 60{
61 ide_hwif_t *hwif = drive->hwif;
62 struct tx4938ide_platform_info *pdata = hwif->dev->platform_data; 61 struct tx4938ide_platform_info *pdata = hwif->dev->platform_data;
63 u8 safe = pio; 62 u8 safe = drive->pio_mode - XFER_PIO_0;
64 ide_drive_t *pair; 63 ide_drive_t *pair;
65 64
66 pair = ide_get_pair_dev(drive); 65 pair = ide_get_pair_dev(drive);
67 if (pair) 66 if (pair)
68 safe = min(safe, ide_get_best_pio_mode(pair, 255, 5)); 67 safe = min(safe, pair->pio_mode - XFER_PIO_0);
69 tx4938ide_tune_ebusc(pdata->ebus_ch, pdata->gbus_clock, safe); 68 tx4938ide_tune_ebusc(pdata->ebus_ch, pdata->gbus_clock, safe);
70} 69}
71 70
diff --git a/drivers/ide/tx4939ide.c b/drivers/ide/tx4939ide.c
index 64b58ecc3f0e..3c7367751873 100644
--- a/drivers/ide/tx4939ide.c
+++ b/drivers/ide/tx4939ide.c
@@ -104,17 +104,17 @@ static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
104 104
105#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base) 105#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
106 106
107static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio) 107static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
108{ 108{
109 ide_hwif_t *hwif = drive->hwif;
110 int is_slave = drive->dn; 109 int is_slave = drive->dn;
111 u32 mask, val; 110 u32 mask, val;
111 const u8 pio = drive->pio_mode - XFER_PIO_0;
112 u8 safe = pio; 112 u8 safe = pio;
113 ide_drive_t *pair; 113 ide_drive_t *pair;
114 114
115 pair = ide_get_pair_dev(drive); 115 pair = ide_get_pair_dev(drive);
116 if (pair) 116 if (pair)
117 safe = min(safe, ide_get_best_pio_mode(pair, 255, 4)); 117 safe = min(safe, pair->pio_mode - XFER_PIO_0);
118 /* 118 /*
119 * Update Command Transfer Mode for master/slave and Data 119 * Update Command Transfer Mode for master/slave and Data
120 * Transfer Mode for this drive. 120 * Transfer Mode for this drive.
@@ -125,10 +125,10 @@ static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ 125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
126} 126}
127 127
128static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode) 128static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
129{ 129{
130 ide_hwif_t *hwif = drive->hwif;
131 u32 mask, val; 130 u32 mask, val;
131 const u8 mode = drive->dma_mode;
132 132
133 /* Update Data Transfer Mode for this drive. */ 133 /* Update Data Transfer Mode for this drive. */
134 if (mode >= XFER_UDMA_0) 134 if (mode >= XFER_UDMA_0)
diff --git a/drivers/ide/umc8672.c b/drivers/ide/umc8672.c
index 60f936e2319c..47adcd09cb26 100644
--- a/drivers/ide/umc8672.c
+++ b/drivers/ide/umc8672.c
@@ -104,10 +104,11 @@ static void umc_set_speeds(u8 speeds[])
104 speeds[0], speeds[1], speeds[2], speeds[3]); 104 speeds[0], speeds[1], speeds[2], speeds[3]);
105} 105}
106 106
107static void umc_set_pio_mode(ide_drive_t *drive, const u8 pio) 107static void umc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
108{ 108{
109 ide_hwif_t *hwif = drive->hwif, *mate = hwif->mate; 109 ide_hwif_t *mate = hwif->mate;
110 unsigned long uninitialized_var(flags); 110 unsigned long uninitialized_var(flags);
111 const u8 pio = drive->pio_mode - XFER_PIO_0;
111 112
112 printk("%s: setting umc8672 to PIO mode%d (speed %d)\n", 113 printk("%s: setting umc8672 to PIO mode%d (speed %d)\n",
113 drive->name, pio, pio_to_umc[pio]); 114 drive->name, pio, pio_to_umc[pio]);
diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c
index 028de26a25fe..e65d010b708d 100644
--- a/drivers/ide/via82cxxx.c
+++ b/drivers/ide/via82cxxx.c
@@ -6,7 +6,7 @@
6 * vt8235, vt8237, vt8237a 6 * vt8235, vt8237, vt8237a
7 * 7 *
8 * Copyright (c) 2000-2002 Vojtech Pavlik 8 * Copyright (c) 2000-2002 Vojtech Pavlik
9 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz 9 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
10 * 10 *
11 * Based on the work of: 11 * Based on the work of:
12 * Michel Aubry 12 * Michel Aubry
@@ -54,6 +54,11 @@
54#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ 54#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
55#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ 55#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
56#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ 56#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
57#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
58
59enum {
60 VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
61};
57 62
58/* 63/*
59 * VIA SouthBridge chips. 64 * VIA SouthBridge chips.
@@ -67,11 +72,13 @@ static struct via_isa_bridge {
67 u8 udma_mask; 72 u8 udma_mask;
68 u8 flags; 73 u8 flags;
69} via_isa_bridges[] = { 74} via_isa_bridges[] = {
70 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 75 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
71 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 76 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
72 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 77 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
78 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
73 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 79 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
74 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 80 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
81 { "vt6415", PCI_DEVICE_ID_VIA_6410, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
75 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 82 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
76 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 83 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
77 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 84 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
@@ -92,6 +99,7 @@ static struct via_isa_bridge {
92 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, 99 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
93 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, 100 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
94 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 101 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
102 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
95 { NULL } 103 { NULL }
96}; 104};
97 105
@@ -102,6 +110,7 @@ struct via82cxxx_dev
102{ 110{
103 struct via_isa_bridge *via_config; 111 struct via_isa_bridge *via_config;
104 unsigned int via_80w; 112 unsigned int via_80w;
113 u8 cached_device[2];
105}; 114};
106 115
107/** 116/**
@@ -137,30 +146,45 @@ static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
137 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; 146 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
138 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; 147 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
139 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; 148 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
140 default: return;
141 } 149 }
142 150
143 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); 151 /* Set UDMA unless device is not UDMA capable */
152 if (vdev->via_config->udma_mask) {
153 u8 udma_etc;
154
155 pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);
156
157 /* clear transfer mode bit */
158 udma_etc &= ~0x20;
159
160 if (timing->udma) {
161 /* preserve 80-wire cable detection bit */
162 udma_etc &= 0x10;
163 udma_etc |= t;
164 }
165
166 pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
167 }
144} 168}
145 169
146/** 170/**
147 * via_set_drive - configure transfer mode 171 * via_set_drive - configure transfer mode
172 * @hwif: port
148 * @drive: Drive to set up 173 * @drive: Drive to set up
149 * @speed: desired speed
150 * 174 *
151 * via_set_drive() computes timing values configures the chipset to 175 * via_set_drive() computes timing values configures the chipset to
152 * a desired transfer mode. It also can be called by upper layers. 176 * a desired transfer mode. It also can be called by upper layers.
153 */ 177 */
154 178
155static void via_set_drive(ide_drive_t *drive, const u8 speed) 179static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
156{ 180{
157 ide_hwif_t *hwif = drive->hwif;
158 ide_drive_t *peer = ide_get_pair_dev(drive); 181 ide_drive_t *peer = ide_get_pair_dev(drive);
159 struct pci_dev *dev = to_pci_dev(hwif->dev); 182 struct pci_dev *dev = to_pci_dev(hwif->dev);
160 struct ide_host *host = pci_get_drvdata(dev); 183 struct ide_host *host = pci_get_drvdata(dev);
161 struct via82cxxx_dev *vdev = host->host_priv; 184 struct via82cxxx_dev *vdev = host->host_priv;
162 struct ide_timing t, p; 185 struct ide_timing t, p;
163 unsigned int T, UT; 186 unsigned int T, UT;
187 const u8 speed = drive->dma_mode;
164 188
165 T = 1000000000 / via_clock; 189 T = 1000000000 / via_clock;
166 190
@@ -175,7 +199,7 @@ static void via_set_drive(ide_drive_t *drive, const u8 speed)
175 ide_timing_compute(drive, speed, &t, T, UT); 199 ide_timing_compute(drive, speed, &t, T, UT);
176 200
177 if (peer) { 201 if (peer) {
178 ide_timing_compute(peer, peer->current_speed, &p, T, UT); 202 ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
179 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); 203 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
180 } 204 }
181 205
@@ -184,22 +208,24 @@ static void via_set_drive(ide_drive_t *drive, const u8 speed)
184 208
185/** 209/**
186 * via_set_pio_mode - set host controller for PIO mode 210 * via_set_pio_mode - set host controller for PIO mode
211 * @hwif: port
187 * @drive: drive 212 * @drive: drive
188 * @pio: PIO mode number
189 * 213 *
190 * A callback from the upper layers for PIO-only tuning. 214 * A callback from the upper layers for PIO-only tuning.
191 */ 215 */
192 216
193static void via_set_pio_mode(ide_drive_t *drive, const u8 pio) 217static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
194{ 218{
195 via_set_drive(drive, XFER_PIO_0 + pio); 219 drive->dma_mode = drive->pio_mode;
220 via_set_drive(hwif, drive);
196} 221}
197 222
198static struct via_isa_bridge *via_config_find(struct pci_dev **isa) 223static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
199{ 224{
200 struct via_isa_bridge *via_config; 225 struct via_isa_bridge *via_config;
201 226
202 for (via_config = via_isa_bridges; via_config->id; via_config++) 227 for (via_config = via_isa_bridges;
228 via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
203 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + 229 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
204 !!(via_config->flags & VIA_BAD_ID), 230 !!(via_config->flags & VIA_BAD_ID),
205 via_config->id, NULL))) { 231 via_config->id, NULL))) {
@@ -362,6 +388,9 @@ static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
362 if (via_cable_override(pdev)) 388 if (via_cable_override(pdev))
363 return ATA_CBL_PATA40_SHORT; 389 return ATA_CBL_PATA40_SHORT;
364 390
391 if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
392 return ATA_CBL_SATA;
393
365 if ((vdev->via_80w >> hwif->channel) & 1) 394 if ((vdev->via_80w >> hwif->channel) & 1)
366 return ATA_CBL_PATA80; 395 return ATA_CBL_PATA80;
367 else 396 else
@@ -374,10 +403,66 @@ static const struct ide_port_ops via_port_ops = {
374 .cable_detect = via82cxxx_cable_detect, 403 .cable_detect = via82cxxx_cable_detect,
375}; 404};
376 405
406static void via_write_devctl(ide_hwif_t *hwif, u8 ctl)
407{
408 struct via82cxxx_dev *vdev = hwif->host->host_priv;
409
410 outb(ctl, hwif->io_ports.ctl_addr);
411 outb(vdev->cached_device[hwif->channel], hwif->io_ports.device_addr);
412}
413
414static void __via_dev_select(ide_drive_t *drive, u8 select)
415{
416 ide_hwif_t *hwif = drive->hwif;
417 struct via82cxxx_dev *vdev = hwif->host->host_priv;
418
419 outb(select, hwif->io_ports.device_addr);
420 vdev->cached_device[hwif->channel] = select;
421}
422
423static void via_dev_select(ide_drive_t *drive)
424{
425 __via_dev_select(drive, drive->select | ATA_DEVICE_OBS);
426}
427
428static void via_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
429{
430 ide_hwif_t *hwif = drive->hwif;
431 struct ide_io_ports *io_ports = &hwif->io_ports;
432
433 if (valid & IDE_VALID_FEATURE)
434 outb(tf->feature, io_ports->feature_addr);
435 if (valid & IDE_VALID_NSECT)
436 outb(tf->nsect, io_ports->nsect_addr);
437 if (valid & IDE_VALID_LBAL)
438 outb(tf->lbal, io_ports->lbal_addr);
439 if (valid & IDE_VALID_LBAM)
440 outb(tf->lbam, io_ports->lbam_addr);
441 if (valid & IDE_VALID_LBAH)
442 outb(tf->lbah, io_ports->lbah_addr);
443 if (valid & IDE_VALID_DEVICE)
444 __via_dev_select(drive, tf->device);
445}
446
447const struct ide_tp_ops via_tp_ops = {
448 .exec_command = ide_exec_command,
449 .read_status = ide_read_status,
450 .read_altstatus = ide_read_altstatus,
451 .write_devctl = via_write_devctl,
452
453 .dev_select = via_dev_select,
454 .tf_load = via_tf_load,
455 .tf_read = ide_tf_read,
456
457 .input_data = ide_input_data,
458 .output_data = ide_output_data,
459};
460
377static const struct ide_port_info via82cxxx_chipset __devinitdata = { 461static const struct ide_port_info via82cxxx_chipset __devinitdata = {
378 .name = DRV_NAME, 462 .name = DRV_NAME,
379 .init_chipset = init_chipset_via82cxxx, 463 .init_chipset = init_chipset_via82cxxx,
380 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, 464 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
465 .tp_ops = &via_tp_ops,
381 .port_ops = &via_port_ops, 466 .port_ops = &via_port_ops,
382 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | 467 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
383 IDE_HFLAG_POST_SET_MODE | 468 IDE_HFLAG_POST_SET_MODE |
@@ -402,11 +487,6 @@ static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_i
402 * Find the ISA bridge and check we know what it is. 487 * Find the ISA bridge and check we know what it is.
403 */ 488 */
404 via_config = via_config_find(&isa); 489 via_config = via_config_find(&isa);
405 if (!via_config->id) {
406 printk(KERN_WARNING DRV_NAME " %s: unknown chipset, skipping\n",
407 pci_name(dev));
408 return -ENODEV;
409 }
410 490
411 /* 491 /*
412 * Print the boot message. 492 * Print the boot message.
@@ -436,10 +516,13 @@ static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_i
436 via_clock = 33333; 516 via_clock = 33333;
437 } 517 }
438 518
439 if (idx == 0) 519 if (idx == 1)
440 d.host_flags |= IDE_HFLAG_NO_AUTODMA;
441 else
442 d.enablebits[1].reg = d.enablebits[0].reg = 0; 520 d.enablebits[1].reg = d.enablebits[0].reg = 0;
521 else
522 d.host_flags |= IDE_HFLAG_NO_AUTODMA;
523
524 if (idx == VIA_IDFLAG_SINGLE)
525 d.host_flags |= IDE_HFLAG_SINGLE;
443 526
444 if ((via_config->flags & VIA_NO_UNMASK) == 0) 527 if ((via_config->flags & VIA_NO_UNMASK) == 0)
445 d.host_flags |= IDE_HFLAG_UNMASK_IRQS; 528 d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
@@ -475,8 +558,9 @@ static const struct pci_device_id via_pci_tbl[] = {
475 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, 558 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
476 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, 559 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
477 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, 560 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
478 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), 0 }, 561 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
479 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, 562 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
563 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
480 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, 564 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
481 { 0, }, 565 { 0, },
482}; 566};
@@ -504,6 +588,6 @@ static void __exit via_ide_exit(void)
504module_init(via_ide_init); 588module_init(via_ide_init);
505module_exit(via_ide_exit); 589module_exit(via_ide_exit);
506 590
507MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); 591MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
508MODULE_DESCRIPTION("PCI driver module for VIA IDE"); 592MODULE_DESCRIPTION("PCI driver module for VIA IDE");
509MODULE_LICENSE("GPL"); 593MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 14:53:05 -0500