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-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c4
-rw-r--r--drivers/mfd/twl6040.c92
-rw-r--r--drivers/mfd/wm5110-tables.c139
-rw-r--r--drivers/spi/Kconfig2
4 files changed, 227 insertions, 10 deletions
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 7d2c84265947..8e27aee6887e 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -331,8 +331,8 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
331 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), 331 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
332 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), 332 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
333 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), 333 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
334 ALIAS(HCLK_DMA1, NULL, "dma1"), 334 ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
335 ALIAS(HCLK_DMA0, NULL, "dma0"), 335 ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
336 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"), 336 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
337 ALIAS(HCLK_LCD, "s3c-fb", "lcd"), 337 ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
338 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"), 338 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index 0779d5ab9ab1..51b6df1a7949 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -44,6 +44,54 @@
44#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1) 44#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
45#define TWL6040_NUM_SUPPLIES (2) 45#define TWL6040_NUM_SUPPLIES (2)
46 46
47static struct reg_default twl6040_defaults[] = {
48 { 0x01, 0x4B }, /* REG_ASICID (ro) */
49 { 0x02, 0x00 }, /* REG_ASICREV (ro) */
50 { 0x03, 0x00 }, /* REG_INTID */
51 { 0x04, 0x00 }, /* REG_INTMR */
52 { 0x05, 0x00 }, /* REG_NCPCTRL */
53 { 0x06, 0x00 }, /* REG_LDOCTL */
54 { 0x07, 0x60 }, /* REG_HPPLLCTL */
55 { 0x08, 0x00 }, /* REG_LPPLLCTL */
56 { 0x09, 0x4A }, /* REG_LPPLLDIV */
57 { 0x0A, 0x00 }, /* REG_AMICBCTL */
58 { 0x0B, 0x00 }, /* REG_DMICBCTL */
59 { 0x0C, 0x00 }, /* REG_MICLCTL */
60 { 0x0D, 0x00 }, /* REG_MICRCTL */
61 { 0x0E, 0x00 }, /* REG_MICGAIN */
62 { 0x0F, 0x1B }, /* REG_LINEGAIN */
63 { 0x10, 0x00 }, /* REG_HSLCTL */
64 { 0x11, 0x00 }, /* REG_HSRCTL */
65 { 0x12, 0x00 }, /* REG_HSGAIN */
66 { 0x13, 0x00 }, /* REG_EARCTL */
67 { 0x14, 0x00 }, /* REG_HFLCTL */
68 { 0x15, 0x00 }, /* REG_HFLGAIN */
69 { 0x16, 0x00 }, /* REG_HFRCTL */
70 { 0x17, 0x00 }, /* REG_HFRGAIN */
71 { 0x18, 0x00 }, /* REG_VIBCTLL */
72 { 0x19, 0x00 }, /* REG_VIBDATL */
73 { 0x1A, 0x00 }, /* REG_VIBCTLR */
74 { 0x1B, 0x00 }, /* REG_VIBDATR */
75 { 0x1C, 0x00 }, /* REG_HKCTL1 */
76 { 0x1D, 0x00 }, /* REG_HKCTL2 */
77 { 0x1E, 0x00 }, /* REG_GPOCTL */
78 { 0x1F, 0x00 }, /* REG_ALB */
79 { 0x20, 0x00 }, /* REG_DLB */
80 /* 0x28, REG_TRIM1 */
81 /* 0x29, REG_TRIM2 */
82 /* 0x2A, REG_TRIM3 */
83 /* 0x2B, REG_HSOTRIM */
84 /* 0x2C, REG_HFOTRIM */
85 { 0x2D, 0x08 }, /* REG_ACCCTL */
86 { 0x2E, 0x00 }, /* REG_STATUS (ro) */
87};
88
89struct reg_default twl6040_patch[] = {
90 /* Select I2C bus access to dual access registers */
91 { TWL6040_REG_ACCCTL, 0x09 },
92};
93
94
47static bool twl6040_has_vibra(struct device_node *node) 95static bool twl6040_has_vibra(struct device_node *node)
48{ 96{
49#ifdef CONFIG_OF 97#ifdef CONFIG_OF
@@ -238,6 +286,9 @@ int twl6040_power(struct twl6040 *twl6040, int on)
238 if (twl6040->power_count++) 286 if (twl6040->power_count++)
239 goto out; 287 goto out;
240 288
289 /* Allow writes to the chip */
290 regcache_cache_only(twl6040->regmap, false);
291
241 if (gpio_is_valid(twl6040->audpwron)) { 292 if (gpio_is_valid(twl6040->audpwron)) {
242 /* use automatic power-up sequence */ 293 /* use automatic power-up sequence */
243 ret = twl6040_power_up_automatic(twl6040); 294 ret = twl6040_power_up_automatic(twl6040);
@@ -253,6 +304,10 @@ int twl6040_power(struct twl6040 *twl6040, int on)
253 goto out; 304 goto out;
254 } 305 }
255 } 306 }
307
308 /* Sync with the HW */
309 regcache_sync(twl6040->regmap);
310
256 /* Default PLL configuration after power up */ 311 /* Default PLL configuration after power up */
257 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; 312 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
258 twl6040->sysclk = 19200000; 313 twl6040->sysclk = 19200000;
@@ -279,6 +334,11 @@ int twl6040_power(struct twl6040 *twl6040, int on)
279 /* use manual power-down sequence */ 334 /* use manual power-down sequence */
280 twl6040_power_down_manual(twl6040); 335 twl6040_power_down_manual(twl6040);
281 } 336 }
337
338 /* Set regmap to cache only and mark it as dirty */
339 regcache_cache_only(twl6040->regmap, true);
340 regcache_mark_dirty(twl6040->regmap);
341
282 twl6040->sysclk = 0; 342 twl6040->sysclk = 0;
283 twl6040->mclk = 0; 343 twl6040->mclk = 0;
284 } 344 }
@@ -490,9 +550,24 @@ static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
490static bool twl6040_volatile_reg(struct device *dev, unsigned int reg) 550static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
491{ 551{
492 switch (reg) { 552 switch (reg) {
493 case TWL6040_REG_VIBCTLL: 553 case TWL6040_REG_ASICID:
494 case TWL6040_REG_VIBCTLR: 554 case TWL6040_REG_ASICREV:
495 case TWL6040_REG_INTMR: 555 case TWL6040_REG_INTID:
556 case TWL6040_REG_LPPLLCTL:
557 case TWL6040_REG_HPPLLCTL:
558 case TWL6040_REG_STATUS:
559 return true;
560 default:
561 return false;
562 }
563}
564
565static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
566{
567 switch (reg) {
568 case TWL6040_REG_ASICID:
569 case TWL6040_REG_ASICREV:
570 case TWL6040_REG_STATUS:
496 return false; 571 return false;
497 default: 572 default:
498 return true; 573 return true;
@@ -502,10 +577,15 @@ static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
502static struct regmap_config twl6040_regmap_config = { 577static struct regmap_config twl6040_regmap_config = {
503 .reg_bits = 8, 578 .reg_bits = 8,
504 .val_bits = 8, 579 .val_bits = 8,
580
581 .reg_defaults = twl6040_defaults,
582 .num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
583
505 .max_register = TWL6040_REG_STATUS, /* 0x2e */ 584 .max_register = TWL6040_REG_STATUS, /* 0x2e */
506 585
507 .readable_reg = twl6040_readable_reg, 586 .readable_reg = twl6040_readable_reg,
508 .volatile_reg = twl6040_volatile_reg, 587 .volatile_reg = twl6040_volatile_reg,
588 .writeable_reg = twl6040_writeable_reg,
509 589
510 .cache_type = REGCACHE_RBTREE, 590 .cache_type = REGCACHE_RBTREE,
511}; 591};
@@ -624,6 +704,8 @@ static int twl6040_probe(struct i2c_client *client,
624 704
625 /* dual-access registers controlled by I2C only */ 705 /* dual-access registers controlled by I2C only */
626 twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL); 706 twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL);
707 regmap_register_patch(twl6040->regmap, twl6040_patch,
708 ARRAY_SIZE(twl6040_patch));
627 709
628 /* 710 /*
629 * The main functionality of twl6040 to provide audio on OMAP4+ systems. 711 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
@@ -656,6 +738,10 @@ static int twl6040_probe(struct i2c_client *client,
656 cell->name = "twl6040-gpo"; 738 cell->name = "twl6040-gpo";
657 children++; 739 children++;
658 740
741 /* The chip is powered down so mark regmap to cache only and dirty */
742 regcache_cache_only(twl6040->regmap, true);
743 regcache_mark_dirty(twl6040->regmap);
744
659 ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children, 745 ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
660 NULL, 0, NULL); 746 NULL, 0, NULL);
661 if (ret) 747 if (ret)
diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
index bf8b3b5ad1fe..abd6713de7b0 100644
--- a/drivers/mfd/wm5110-tables.c
+++ b/drivers/mfd/wm5110-tables.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/mfd/arizona/core.h> 15#include <linux/mfd/arizona/core.h>
16#include <linux/mfd/arizona/registers.h> 16#include <linux/mfd/arizona/registers.h>
17#include <linux/device.h>
17 18
18#include "arizona.h" 19#include "arizona.h"
19 20
@@ -524,6 +525,7 @@ static const struct reg_default wm5110_reg_default[] = {
524 { 0x00000300, 0x0000 }, /* R768 - Input Enables */ 525 { 0x00000300, 0x0000 }, /* R768 - Input Enables */
525 { 0x00000308, 0x0000 }, /* R776 - Input Rate */ 526 { 0x00000308, 0x0000 }, /* R776 - Input Rate */
526 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ 527 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
528 { 0x0000030C, 0x0002 }, /* R780 - HPF Control */
527 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */ 529 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */
528 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ 530 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
529 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ 531 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
@@ -545,6 +547,7 @@ static const struct reg_default wm5110_reg_default[] = {
545 { 0x00000328, 0x2000 }, /* R808 - IN4L Control */ 547 { 0x00000328, 0x2000 }, /* R808 - IN4L Control */
546 { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */ 548 { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */
547 { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */ 549 { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */
550 { 0x0000032C, 0x0000 }, /* R812 - IN4R Control */
548 { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */ 551 { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */
549 { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */ 552 { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */
550 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ 553 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
@@ -598,6 +601,7 @@ static const struct reg_default wm5110_reg_default[] = {
598 { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */ 601 { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */
599 { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */ 602 { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */
600 { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */ 603 { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */
604 { 0x00000440, 0x8FFF }, /* R1088 - DRE Enable */
601 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ 605 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
602 { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ 606 { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
603 { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */ 607 { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */
@@ -882,6 +886,38 @@ static const struct reg_default wm5110_reg_default[] = {
882 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ 886 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
883 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ 887 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
884 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ 888 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
889 { 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */
890 { 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */
891 { 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */
892 { 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */
893 { 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */
894 { 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */
895 { 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */
896 { 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */
897 { 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */
898 { 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */
899 { 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */
900 { 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */
901 { 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */
902 { 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */
903 { 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */
904 { 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */
905 { 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */
906 { 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */
907 { 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */
908 { 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */
909 { 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */
910 { 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */
911 { 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */
912 { 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */
913 { 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */
914 { 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */
915 { 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */
916 { 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */
917 { 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */
918 { 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */
919 { 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */
920 { 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */
885 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */ 921 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
886 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */ 922 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
887 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */ 923 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
@@ -1342,6 +1378,64 @@ static const struct reg_default wm5110_reg_default[] = {
1342 { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */ 1378 { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */
1343}; 1379};
1344 1380
1381static bool wm5110_is_rev_b_adsp_memory(unsigned int reg)
1382{
1383 if ((reg >= 0x100000 && reg < 0x103000) ||
1384 (reg >= 0x180000 && reg < 0x181000) ||
1385 (reg >= 0x190000 && reg < 0x192000) ||
1386 (reg >= 0x1a8000 && reg < 0x1a9000) ||
1387 (reg >= 0x200000 && reg < 0x209000) ||
1388 (reg >= 0x280000 && reg < 0x281000) ||
1389 (reg >= 0x290000 && reg < 0x29a000) ||
1390 (reg >= 0x2a8000 && reg < 0x2aa000) ||
1391 (reg >= 0x300000 && reg < 0x30f000) ||
1392 (reg >= 0x380000 && reg < 0x382000) ||
1393 (reg >= 0x390000 && reg < 0x39e000) ||
1394 (reg >= 0x3a8000 && reg < 0x3b6000) ||
1395 (reg >= 0x400000 && reg < 0x403000) ||
1396 (reg >= 0x480000 && reg < 0x481000) ||
1397 (reg >= 0x490000 && reg < 0x492000) ||
1398 (reg >= 0x4a8000 && reg < 0x4a9000))
1399 return true;
1400 else
1401 return false;
1402}
1403
1404static bool wm5110_is_rev_d_adsp_memory(unsigned int reg)
1405{
1406 if ((reg >= 0x100000 && reg < 0x106000) ||
1407 (reg >= 0x180000 && reg < 0x182000) ||
1408 (reg >= 0x190000 && reg < 0x198000) ||
1409 (reg >= 0x1a8000 && reg < 0x1aa000) ||
1410 (reg >= 0x200000 && reg < 0x20f000) ||
1411 (reg >= 0x280000 && reg < 0x282000) ||
1412 (reg >= 0x290000 && reg < 0x29c000) ||
1413 (reg >= 0x2a6000 && reg < 0x2b4000) ||
1414 (reg >= 0x300000 && reg < 0x30f000) ||
1415 (reg >= 0x380000 && reg < 0x382000) ||
1416 (reg >= 0x390000 && reg < 0x3a2000) ||
1417 (reg >= 0x3a6000 && reg < 0x3b4000) ||
1418 (reg >= 0x400000 && reg < 0x406000) ||
1419 (reg >= 0x480000 && reg < 0x482000) ||
1420 (reg >= 0x490000 && reg < 0x498000) ||
1421 (reg >= 0x4a8000 && reg < 0x4aa000))
1422 return true;
1423 else
1424 return false;
1425}
1426
1427static bool wm5110_is_adsp_memory(struct device *dev, unsigned int reg)
1428{
1429 struct arizona *arizona = dev_get_drvdata(dev);
1430
1431 switch (arizona->rev) {
1432 case 0 ... 2:
1433 return wm5110_is_rev_b_adsp_memory(reg);
1434 default:
1435 return wm5110_is_rev_d_adsp_memory(reg);
1436 }
1437}
1438
1345static bool wm5110_readable_register(struct device *dev, unsigned int reg) 1439static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1346{ 1440{
1347 switch (reg) { 1441 switch (reg) {
@@ -1460,6 +1554,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1460 case ARIZONA_INPUT_ENABLES_STATUS: 1554 case ARIZONA_INPUT_ENABLES_STATUS:
1461 case ARIZONA_INPUT_RATE: 1555 case ARIZONA_INPUT_RATE:
1462 case ARIZONA_INPUT_VOLUME_RAMP: 1556 case ARIZONA_INPUT_VOLUME_RAMP:
1557 case ARIZONA_HPF_CONTROL:
1463 case ARIZONA_IN1L_CONTROL: 1558 case ARIZONA_IN1L_CONTROL:
1464 case ARIZONA_ADC_DIGITAL_VOLUME_1L: 1559 case ARIZONA_ADC_DIGITAL_VOLUME_1L:
1465 case ARIZONA_DMIC1L_CONTROL: 1560 case ARIZONA_DMIC1L_CONTROL:
@@ -1481,6 +1576,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1481 case ARIZONA_IN4L_CONTROL: 1576 case ARIZONA_IN4L_CONTROL:
1482 case ARIZONA_ADC_DIGITAL_VOLUME_4L: 1577 case ARIZONA_ADC_DIGITAL_VOLUME_4L:
1483 case ARIZONA_DMIC4L_CONTROL: 1578 case ARIZONA_DMIC4L_CONTROL:
1579 case ARIZONA_IN4R_CONTROL:
1484 case ARIZONA_ADC_DIGITAL_VOLUME_4R: 1580 case ARIZONA_ADC_DIGITAL_VOLUME_4R:
1485 case ARIZONA_DMIC4R_CONTROL: 1581 case ARIZONA_DMIC4R_CONTROL:
1486 case ARIZONA_OUTPUT_ENABLES_1: 1582 case ARIZONA_OUTPUT_ENABLES_1:
@@ -1536,6 +1632,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1536 case ARIZONA_DAC_DIGITAL_VOLUME_6R: 1632 case ARIZONA_DAC_DIGITAL_VOLUME_6R:
1537 case ARIZONA_DAC_VOLUME_LIMIT_6R: 1633 case ARIZONA_DAC_VOLUME_LIMIT_6R:
1538 case ARIZONA_NOISE_GATE_SELECT_6R: 1634 case ARIZONA_NOISE_GATE_SELECT_6R:
1635 case ARIZONA_DRE_ENABLE:
1539 case ARIZONA_DAC_AEC_CONTROL_1: 1636 case ARIZONA_DAC_AEC_CONTROL_1:
1540 case ARIZONA_NOISE_GATE_CONTROL: 1637 case ARIZONA_NOISE_GATE_CONTROL:
1541 case ARIZONA_PDM_SPK1_CTRL_1: 1638 case ARIZONA_PDM_SPK1_CTRL_1:
@@ -1820,6 +1917,38 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1820 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: 1917 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
1821 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: 1918 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
1822 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: 1919 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
1920 case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE:
1921 case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME:
1922 case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE:
1923 case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME:
1924 case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE:
1925 case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME:
1926 case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE:
1927 case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME:
1928 case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE:
1929 case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME:
1930 case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE:
1931 case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME:
1932 case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE:
1933 case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME:
1934 case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE:
1935 case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME:
1936 case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE:
1937 case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME:
1938 case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE:
1939 case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME:
1940 case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE:
1941 case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME:
1942 case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE:
1943 case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME:
1944 case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE:
1945 case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME:
1946 case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE:
1947 case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME:
1948 case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE:
1949 case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME:
1950 case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE:
1951 case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME:
1823 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: 1952 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
1824 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: 1953 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
1825 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: 1954 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
@@ -2331,7 +2460,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
2331 case ARIZONA_DSP4_SCRATCH_3: 2460 case ARIZONA_DSP4_SCRATCH_3:
2332 return true; 2461 return true;
2333 default: 2462 default:
2334 return false; 2463 return wm5110_is_adsp_memory(dev, reg);
2335 } 2464 }
2336} 2465}
2337 2466
@@ -2407,16 +2536,18 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg)
2407 case ARIZONA_DSP4_SCRATCH_3: 2536 case ARIZONA_DSP4_SCRATCH_3:
2408 return true; 2537 return true;
2409 default: 2538 default:
2410 return false; 2539 return wm5110_is_adsp_memory(dev, reg);
2411 } 2540 }
2412} 2541}
2413 2542
2543#define WM5110_MAX_REGISTER 0x4a9fff
2544
2414const struct regmap_config wm5110_spi_regmap = { 2545const struct regmap_config wm5110_spi_regmap = {
2415 .reg_bits = 32, 2546 .reg_bits = 32,
2416 .pad_bits = 16, 2547 .pad_bits = 16,
2417 .val_bits = 16, 2548 .val_bits = 16,
2418 2549
2419 .max_register = ARIZONA_DSP1_STATUS_2, 2550 .max_register = WM5110_MAX_REGISTER,
2420 .readable_reg = wm5110_readable_register, 2551 .readable_reg = wm5110_readable_register,
2421 .volatile_reg = wm5110_volatile_register, 2552 .volatile_reg = wm5110_volatile_register,
2422 2553
@@ -2430,7 +2561,7 @@ const struct regmap_config wm5110_i2c_regmap = {
2430 .reg_bits = 32, 2561 .reg_bits = 32,
2431 .val_bits = 16, 2562 .val_bits = 16,
2432 2563
2433 .max_register = ARIZONA_DSP1_STATUS_2, 2564 .max_register = WM5110_MAX_REGISTER,
2434 .readable_reg = wm5110_readable_register, 2565 .readable_reg = wm5110_readable_register,
2435 .volatile_reg = wm5110_volatile_register, 2566 .volatile_reg = wm5110_volatile_register,
2436 2567
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb1f1ef5fa2e..e2dd2fbec5ee 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -395,7 +395,7 @@ config SPI_S3C24XX_FIQ
395config SPI_S3C64XX 395config SPI_S3C64XX
396 tristate "Samsung S3C64XX series type SPI" 396 tristate "Samsung S3C64XX series type SPI"
397 depends on PLAT_SAMSUNG 397 depends on PLAT_SAMSUNG
398 select S3C64XX_DMA if ARCH_S3C64XX 398 select S3C64XX_PL080 if ARCH_S3C64XX
399 help 399 help
400 SPI driver for Samsung S3C64XX and newer SoCs. 400 SPI driver for Samsung S3C64XX and newer SoCs.
401 401
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 09:25:02 -0400