4 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 636660fca8c2..ae09fe82afbc 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1455,6 +1455,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
 #endif
         WREG32(CP_RB_CNTL, tmp);
         WREG32(CP_SEM_WAIT_TIMER, 0x0);
+        WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
 
         /* Set the write pointer delay */
         WREG32(CP_RB_WPTR_DELAY, 0);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index b502216d42af..74713d42df29 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -108,6 +108,7 @@
 #define CP_RB_WPTR_ADDR_HI                              0xC11C
 #define CP_RB_WPTR_DELAY                                0x8704
 #define CP_SEM_WAIT_TIMER                               0x85BC
+#define CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
 #define CP_DEBUG                                        0xC1FC
 
 
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 321137295400..db09065e68fd 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1219,6 +1219,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
         RREG32(GRBM_SOFT_RESET);
 
         WREG32(CP_SEM_WAIT_TIMER, 0x0);
+        WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
 
         /* Set the write pointer delay */
         WREG32(CP_RB_WPTR_DELAY, 0);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index f9df2a645e79..9a7f3b6e02de 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -222,6 +222,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 #define CP_SEM_WAIT_TIMER                               0x85BC
+#define CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
 #define CP_COHER_CNTL2                                  0x85E8
 #define CP_ME_CNTL                                      0x86D8
 #define         CP_ME_HALT                                      (1 << 28)