diff options
Diffstat (limited to 'drivers/watchdog/jz4740_wdt.c')
| -rw-r--r-- | drivers/watchdog/jz4740_wdt.c | 265 |
1 files changed, 90 insertions, 175 deletions
diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c index 17ef300bccc5..978615ef899d 100644 --- a/drivers/watchdog/jz4740_wdt.c +++ b/drivers/watchdog/jz4740_wdt.c | |||
| @@ -17,18 +17,15 @@ | |||
| 17 | #include <linux/moduleparam.h> | 17 | #include <linux/moduleparam.h> |
| 18 | #include <linux/types.h> | 18 | #include <linux/types.h> |
| 19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/fs.h> | ||
| 21 | #include <linux/miscdevice.h> | 20 | #include <linux/miscdevice.h> |
| 22 | #include <linux/watchdog.h> | 21 | #include <linux/watchdog.h> |
| 23 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 24 | #include <linux/bitops.h> | ||
| 25 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 26 | #include <linux/spinlock.h> | ||
| 27 | #include <linux/uaccess.h> | ||
| 28 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 29 | #include <linux/device.h> | 25 | #include <linux/device.h> |
| 30 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
| 31 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
| 28 | #include <linux/err.h> | ||
| 32 | 29 | ||
| 33 | #include <asm/mach-jz4740/timer.h> | 30 | #include <asm/mach-jz4740/timer.h> |
| 34 | 31 | ||
| @@ -41,9 +38,6 @@ | |||
| 41 | #define JZ_WDT_CLOCK_RTC 0x2 | 38 | #define JZ_WDT_CLOCK_RTC 0x2 |
| 42 | #define JZ_WDT_CLOCK_EXT 0x4 | 39 | #define JZ_WDT_CLOCK_EXT 0x4 |
| 43 | 40 | ||
| 44 | #define WDT_IN_USE 0 | ||
| 45 | #define WDT_OK_TO_CLOSE 1 | ||
| 46 | |||
| 47 | #define JZ_WDT_CLOCK_DIV_SHIFT 3 | 41 | #define JZ_WDT_CLOCK_DIV_SHIFT 3 |
| 48 | 42 | ||
| 49 | #define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT) | 43 | #define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT) |
| @@ -56,32 +50,44 @@ | |||
| 56 | #define DEFAULT_HEARTBEAT 5 | 50 | #define DEFAULT_HEARTBEAT 5 |
| 57 | #define MAX_HEARTBEAT 2048 | 51 | #define MAX_HEARTBEAT 2048 |
| 58 | 52 | ||
| 59 | static struct { | 53 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 60 | void __iomem *base; | 54 | module_param(nowayout, bool, 0); |
| 61 | struct resource *mem; | 55 | MODULE_PARM_DESC(nowayout, |
| 62 | struct clk *rtc_clk; | 56 | "Watchdog cannot be stopped once started (default=" |
| 63 | unsigned long status; | 57 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 64 | } jz4740_wdt; | ||
| 65 | 58 | ||
| 66 | static int heartbeat = DEFAULT_HEARTBEAT; | 59 | static unsigned int heartbeat = DEFAULT_HEARTBEAT; |
| 60 | module_param(heartbeat, uint, 0); | ||
| 61 | MODULE_PARM_DESC(heartbeat, | ||
| 62 | "Watchdog heartbeat period in seconds from 1 to " | ||
| 63 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | ||
| 64 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | ||
| 67 | 65 | ||
| 66 | struct jz4740_wdt_drvdata { | ||
| 67 | struct watchdog_device wdt; | ||
| 68 | void __iomem *base; | ||
| 69 | struct clk *rtc_clk; | ||
| 70 | }; | ||
| 68 | 71 | ||
| 69 | static void jz4740_wdt_service(void) | 72 | static int jz4740_wdt_ping(struct watchdog_device *wdt_dev) |
| 70 | { | 73 | { |
| 71 | writew(0x0, jz4740_wdt.base + JZ_REG_WDT_TIMER_COUNTER); | 74 | struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); |
| 75 | |||
| 76 | writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER); | ||
| 77 | return 0; | ||
| 72 | } | 78 | } |
| 73 | 79 | ||
| 74 | static void jz4740_wdt_set_heartbeat(int new_heartbeat) | 80 | static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev, |
| 81 | unsigned int new_timeout) | ||
| 75 | { | 82 | { |
| 83 | struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); | ||
| 76 | unsigned int rtc_clk_rate; | 84 | unsigned int rtc_clk_rate; |
| 77 | unsigned int timeout_value; | 85 | unsigned int timeout_value; |
| 78 | unsigned short clock_div = JZ_WDT_CLOCK_DIV_1; | 86 | unsigned short clock_div = JZ_WDT_CLOCK_DIV_1; |
| 79 | 87 | ||
| 80 | heartbeat = new_heartbeat; | 88 | rtc_clk_rate = clk_get_rate(drvdata->rtc_clk); |
| 81 | |||
| 82 | rtc_clk_rate = clk_get_rate(jz4740_wdt.rtc_clk); | ||
| 83 | 89 | ||
| 84 | timeout_value = rtc_clk_rate * heartbeat; | 90 | timeout_value = rtc_clk_rate * new_timeout; |
| 85 | while (timeout_value > 0xffff) { | 91 | while (timeout_value > 0xffff) { |
| 86 | if (clock_div == JZ_WDT_CLOCK_DIV_1024) { | 92 | if (clock_div == JZ_WDT_CLOCK_DIV_1024) { |
| 87 | /* Requested timeout too high; | 93 | /* Requested timeout too high; |
| @@ -93,199 +99,115 @@ static void jz4740_wdt_set_heartbeat(int new_heartbeat) | |||
| 93 | clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT); | 99 | clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT); |
| 94 | } | 100 | } |
| 95 | 101 | ||
| 96 | writeb(0x0, jz4740_wdt.base + JZ_REG_WDT_COUNTER_ENABLE); | 102 | writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); |
| 97 | writew(clock_div, jz4740_wdt.base + JZ_REG_WDT_TIMER_CONTROL); | 103 | writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL); |
| 98 | 104 | ||
| 99 | writew((u16)timeout_value, jz4740_wdt.base + JZ_REG_WDT_TIMER_DATA); | 105 | writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA); |
| 100 | writew(0x0, jz4740_wdt.base + JZ_REG_WDT_TIMER_COUNTER); | 106 | writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER); |
| 101 | writew(clock_div | JZ_WDT_CLOCK_RTC, | 107 | writew(clock_div | JZ_WDT_CLOCK_RTC, |
| 102 | jz4740_wdt.base + JZ_REG_WDT_TIMER_CONTROL); | 108 | drvdata->base + JZ_REG_WDT_TIMER_CONTROL); |
| 103 | 109 | ||
| 104 | writeb(0x1, jz4740_wdt.base + JZ_REG_WDT_COUNTER_ENABLE); | 110 | writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); |
| 105 | } | ||
| 106 | 111 | ||
| 107 | static void jz4740_wdt_enable(void) | 112 | wdt_dev->timeout = new_timeout; |
| 108 | { | 113 | return 0; |
| 109 | jz4740_timer_enable_watchdog(); | ||
| 110 | jz4740_wdt_set_heartbeat(heartbeat); | ||
| 111 | } | ||
| 112 | |||
| 113 | static void jz4740_wdt_disable(void) | ||
| 114 | { | ||
| 115 | jz4740_timer_disable_watchdog(); | ||
| 116 | writeb(0x0, jz4740_wdt.base + JZ_REG_WDT_COUNTER_ENABLE); | ||
| 117 | } | 114 | } |
| 118 | 115 | ||
| 119 | static int jz4740_wdt_open(struct inode *inode, struct file *file) | 116 | static int jz4740_wdt_start(struct watchdog_device *wdt_dev) |
| 120 | { | 117 | { |
| 121 | if (test_and_set_bit(WDT_IN_USE, &jz4740_wdt.status)) | 118 | jz4740_timer_enable_watchdog(); |
| 122 | return -EBUSY; | 119 | jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout); |
| 123 | |||
| 124 | jz4740_wdt_enable(); | ||
| 125 | 120 | ||
| 126 | return nonseekable_open(inode, file); | 121 | return 0; |
| 127 | } | 122 | } |
| 128 | 123 | ||
| 129 | static ssize_t jz4740_wdt_write(struct file *file, const char *data, | 124 | static int jz4740_wdt_stop(struct watchdog_device *wdt_dev) |
| 130 | size_t len, loff_t *ppos) | ||
| 131 | { | 125 | { |
| 132 | if (len) { | 126 | struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); |
| 133 | size_t i; | ||
| 134 | |||
| 135 | clear_bit(WDT_OK_TO_CLOSE, &jz4740_wdt.status); | ||
| 136 | for (i = 0; i != len; i++) { | ||
| 137 | char c; | ||
| 138 | 127 | ||
| 139 | if (get_user(c, data + i)) | 128 | jz4740_timer_disable_watchdog(); |
| 140 | return -EFAULT; | 129 | writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); |
| 141 | |||
| 142 | if (c == 'V') | ||
| 143 | set_bit(WDT_OK_TO_CLOSE, &jz4740_wdt.status); | ||
| 144 | } | ||
| 145 | jz4740_wdt_service(); | ||
| 146 | } | ||
| 147 | 130 | ||
| 148 | return len; | 131 | return 0; |
| 149 | } | 132 | } |
| 150 | 133 | ||
| 151 | static const struct watchdog_info ident = { | 134 | static const struct watchdog_info jz4740_wdt_info = { |
| 152 | .options = WDIOF_KEEPALIVEPING, | 135 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, |
| 153 | .identity = "jz4740 Watchdog", | 136 | .identity = "jz4740 Watchdog", |
| 154 | }; | 137 | }; |
| 155 | 138 | ||
| 156 | static long jz4740_wdt_ioctl(struct file *file, | 139 | static const struct watchdog_ops jz4740_wdt_ops = { |
| 157 | unsigned int cmd, unsigned long arg) | ||
| 158 | { | ||
| 159 | int ret = -ENOTTY; | ||
| 160 | int heartbeat_seconds; | ||
| 161 | |||
| 162 | switch (cmd) { | ||
| 163 | case WDIOC_GETSUPPORT: | ||
| 164 | ret = copy_to_user((struct watchdog_info *)arg, &ident, | ||
| 165 | sizeof(ident)) ? -EFAULT : 0; | ||
| 166 | break; | ||
| 167 | |||
| 168 | case WDIOC_GETSTATUS: | ||
| 169 | case WDIOC_GETBOOTSTATUS: | ||
| 170 | ret = put_user(0, (int *)arg); | ||
| 171 | break; | ||
| 172 | |||
| 173 | case WDIOC_KEEPALIVE: | ||
| 174 | jz4740_wdt_service(); | ||
| 175 | return 0; | ||
| 176 | |||
| 177 | case WDIOC_SETTIMEOUT: | ||
| 178 | if (get_user(heartbeat_seconds, (int __user *)arg)) | ||
| 179 | return -EFAULT; | ||
| 180 | |||
| 181 | jz4740_wdt_set_heartbeat(heartbeat_seconds); | ||
| 182 | return 0; | ||
| 183 | |||
| 184 | case WDIOC_GETTIMEOUT: | ||
| 185 | return put_user(heartbeat, (int *)arg); | ||
| 186 | |||
| 187 | default: | ||
| 188 | break; | ||
| 189 | } | ||
| 190 | |||
| 191 | return ret; | ||
| 192 | } | ||
| 193 | |||
| 194 | static int jz4740_wdt_release(struct inode *inode, struct file *file) | ||
| 195 | { | ||
| 196 | jz4740_wdt_service(); | ||
| 197 | |||
| 198 | if (test_and_clear_bit(WDT_OK_TO_CLOSE, &jz4740_wdt.status)) | ||
| 199 | jz4740_wdt_disable(); | ||
| 200 | |||
| 201 | clear_bit(WDT_IN_USE, &jz4740_wdt.status); | ||
| 202 | return 0; | ||
| 203 | } | ||
| 204 | |||
| 205 | static const struct file_operations jz4740_wdt_fops = { | ||
| 206 | .owner = THIS_MODULE, | 140 | .owner = THIS_MODULE, |
| 207 | .llseek = no_llseek, | 141 | .start = jz4740_wdt_start, |
| 208 | .write = jz4740_wdt_write, | 142 | .stop = jz4740_wdt_stop, |
| 209 | .unlocked_ioctl = jz4740_wdt_ioctl, | 143 | .ping = jz4740_wdt_ping, |
| 210 | .open = jz4740_wdt_open, | 144 | .set_timeout = jz4740_wdt_set_timeout, |
| 211 | .release = jz4740_wdt_release, | ||
| 212 | }; | ||
| 213 | |||
| 214 | static struct miscdevice jz4740_wdt_miscdev = { | ||
| 215 | .minor = WATCHDOG_MINOR, | ||
| 216 | .name = "watchdog", | ||
| 217 | .fops = &jz4740_wdt_fops, | ||
| 218 | }; | 145 | }; |
| 219 | 146 | ||
| 220 | static int __devinit jz4740_wdt_probe(struct platform_device *pdev) | 147 | static int __devinit jz4740_wdt_probe(struct platform_device *pdev) |
| 221 | { | 148 | { |
| 222 | int ret = 0, size; | 149 | struct jz4740_wdt_drvdata *drvdata; |
| 223 | struct resource *res; | 150 | struct watchdog_device *jz4740_wdt; |
| 224 | struct device *dev = &pdev->dev; | 151 | struct resource *res; |
| 225 | 152 | int ret; | |
| 226 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 153 | |
| 227 | if (res == NULL) { | 154 | drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata), |
| 228 | dev_err(dev, "failed to get memory region resource\n"); | 155 | GFP_KERNEL); |
| 229 | return -ENXIO; | 156 | if (!drvdata) { |
| 157 | dev_err(&pdev->dev, "Unable to alloacate watchdog device\n"); | ||
| 158 | return -ENOMEM; | ||
| 230 | } | 159 | } |
| 231 | 160 | ||
| 232 | size = resource_size(res); | 161 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) |
| 233 | jz4740_wdt.mem = request_mem_region(res->start, size, pdev->name); | 162 | heartbeat = DEFAULT_HEARTBEAT; |
| 234 | if (jz4740_wdt.mem == NULL) { | ||
| 235 | dev_err(dev, "failed to get memory region\n"); | ||
| 236 | return -EBUSY; | ||
| 237 | } | ||
| 238 | 163 | ||
| 239 | jz4740_wdt.base = ioremap_nocache(res->start, size); | 164 | jz4740_wdt = &drvdata->wdt; |
| 240 | if (jz4740_wdt.base == NULL) { | 165 | jz4740_wdt->info = &jz4740_wdt_info; |
| 241 | dev_err(dev, "failed to map memory region\n"); | 166 | jz4740_wdt->ops = &jz4740_wdt_ops; |
| 167 | jz4740_wdt->timeout = heartbeat; | ||
| 168 | jz4740_wdt->min_timeout = 1; | ||
| 169 | jz4740_wdt->max_timeout = MAX_HEARTBEAT; | ||
| 170 | watchdog_set_nowayout(jz4740_wdt, nowayout); | ||
| 171 | watchdog_set_drvdata(jz4740_wdt, drvdata); | ||
| 172 | |||
| 173 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 174 | drvdata->base = devm_request_and_ioremap(&pdev->dev, res); | ||
| 175 | if (drvdata->base == NULL) { | ||
| 242 | ret = -EBUSY; | 176 | ret = -EBUSY; |
| 243 | goto err_release_region; | 177 | goto err_out; |
| 244 | } | 178 | } |
| 245 | 179 | ||
| 246 | jz4740_wdt.rtc_clk = clk_get(NULL, "rtc"); | 180 | drvdata->rtc_clk = clk_get(NULL, "rtc"); |
| 247 | if (IS_ERR(jz4740_wdt.rtc_clk)) { | 181 | if (IS_ERR(drvdata->rtc_clk)) { |
| 248 | dev_err(dev, "cannot find RTC clock\n"); | 182 | dev_err(&pdev->dev, "cannot find RTC clock\n"); |
| 249 | ret = PTR_ERR(jz4740_wdt.rtc_clk); | 183 | ret = PTR_ERR(drvdata->rtc_clk); |
| 250 | goto err_iounmap; | 184 | goto err_out; |
| 251 | } | 185 | } |
| 252 | 186 | ||
| 253 | ret = misc_register(&jz4740_wdt_miscdev); | 187 | ret = watchdog_register_device(&drvdata->wdt); |
| 254 | if (ret < 0) { | 188 | if (ret < 0) |
| 255 | dev_err(dev, "cannot register misc device\n"); | ||
| 256 | goto err_disable_clk; | 189 | goto err_disable_clk; |
| 257 | } | ||
| 258 | 190 | ||
| 191 | platform_set_drvdata(pdev, drvdata); | ||
| 259 | return 0; | 192 | return 0; |
| 260 | 193 | ||
| 261 | err_disable_clk: | 194 | err_disable_clk: |
| 262 | clk_put(jz4740_wdt.rtc_clk); | 195 | clk_put(drvdata->rtc_clk); |
| 263 | err_iounmap: | 196 | err_out: |
| 264 | iounmap(jz4740_wdt.base); | ||
| 265 | err_release_region: | ||
| 266 | release_mem_region(jz4740_wdt.mem->start, | ||
| 267 | resource_size(jz4740_wdt.mem)); | ||
| 268 | return ret; | 197 | return ret; |
| 269 | } | 198 | } |
| 270 | 199 | ||
| 271 | |||
| 272 | static int __devexit jz4740_wdt_remove(struct platform_device *pdev) | 200 | static int __devexit jz4740_wdt_remove(struct platform_device *pdev) |
| 273 | { | 201 | { |
| 274 | jz4740_wdt_disable(); | 202 | struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev); |
| 275 | misc_deregister(&jz4740_wdt_miscdev); | ||
| 276 | clk_put(jz4740_wdt.rtc_clk); | ||
| 277 | 203 | ||
| 278 | iounmap(jz4740_wdt.base); | 204 | jz4740_wdt_stop(&drvdata->wdt); |
| 279 | jz4740_wdt.base = NULL; | 205 | watchdog_unregister_device(&drvdata->wdt); |
| 280 | 206 | clk_put(drvdata->rtc_clk); | |
| 281 | release_mem_region(jz4740_wdt.mem->start, | ||
| 282 | resource_size(jz4740_wdt.mem)); | ||
| 283 | jz4740_wdt.mem = NULL; | ||
| 284 | 207 | ||
| 285 | return 0; | 208 | return 0; |
| 286 | } | 209 | } |
| 287 | 210 | ||
| 288 | |||
| 289 | static struct platform_driver jz4740_wdt_driver = { | 211 | static struct platform_driver jz4740_wdt_driver = { |
| 290 | .probe = jz4740_wdt_probe, | 212 | .probe = jz4740_wdt_probe, |
| 291 | .remove = __devexit_p(jz4740_wdt_remove), | 213 | .remove = __devexit_p(jz4740_wdt_remove), |
| @@ -299,13 +221,6 @@ module_platform_driver(jz4740_wdt_driver); | |||
| 299 | 221 | ||
| 300 | MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); | 222 | MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); |
| 301 | MODULE_DESCRIPTION("jz4740 Watchdog Driver"); | 223 | MODULE_DESCRIPTION("jz4740 Watchdog Driver"); |
| 302 | |||
| 303 | module_param(heartbeat, int, 0); | ||
| 304 | MODULE_PARM_DESC(heartbeat, | ||
| 305 | "Watchdog heartbeat period in seconds from 1 to " | ||
| 306 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | ||
| 307 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | ||
| 308 | |||
| 309 | MODULE_LICENSE("GPL"); | 224 | MODULE_LICENSE("GPL"); |
| 310 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | 225 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
| 311 | MODULE_ALIAS("platform:jz4740-wdt"); | 226 | MODULE_ALIAS("platform:jz4740-wdt"); |
