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path: root/drivers/vme/bridges/vme_tsi148.c
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Diffstat (limited to 'drivers/vme/bridges/vme_tsi148.c')
-rw-r--r--drivers/vme/bridges/vme_tsi148.c45
1 files changed, 23 insertions, 22 deletions
diff --git a/drivers/vme/bridges/vme_tsi148.c b/drivers/vme/bridges/vme_tsi148.c
index 9c1aa4dc39c9..94c892f27be4 100644
--- a/drivers/vme/bridges/vme_tsi148.c
+++ b/drivers/vme/bridges/vme_tsi148.c
@@ -169,7 +169,7 @@ static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
169 unsigned int error_addr_high, error_addr_low; 169 unsigned int error_addr_high, error_addr_low;
170 unsigned long long error_addr; 170 unsigned long long error_addr;
171 u32 error_attrib; 171 u32 error_attrib;
172 struct vme_bus_error *error; 172 struct vme_bus_error *error = NULL;
173 struct tsi148_driver *bridge; 173 struct tsi148_driver *bridge;
174 174
175 bridge = tsi148_bridge->driver_priv; 175 bridge = tsi148_bridge->driver_priv;
@@ -186,16 +186,22 @@ static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
186 "Occurred\n"); 186 "Occurred\n");
187 } 187 }
188 188
189 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC); 189 if (err_chk) {
190 if (error) { 190 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
191 error->address = error_addr; 191 if (error) {
192 error->attributes = error_attrib; 192 error->address = error_addr;
193 list_add_tail(&error->list, &tsi148_bridge->vme_errors); 193 error->attributes = error_attrib;
194 } else { 194 list_add_tail(&error->list, &tsi148_bridge->vme_errors);
195 dev_err(tsi148_bridge->parent, "Unable to alloc memory for " 195 } else {
196 "VMEbus Error reporting\n"); 196 dev_err(tsi148_bridge->parent,
197 dev_err(tsi148_bridge->parent, "VME Bus Error at address: " 197 "Unable to alloc memory for VMEbus Error reporting\n");
198 "0x%llx, attributes: %08x\n", error_addr, error_attrib); 198 }
199 }
200
201 if (!error) {
202 dev_err(tsi148_bridge->parent,
203 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
204 error_addr, error_attrib);
199 } 205 }
200 206
201 /* Clear Status */ 207 /* Clear Status */
@@ -2294,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2294 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); 2300 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2295 2301
2296 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); 2302 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2297 if (crat & TSI148_LCSR_CRAT_EN) { 2303 if (crat & TSI148_LCSR_CRAT_EN)
2304 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2305 else {
2298 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); 2306 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2299 iowrite32be(crat | TSI148_LCSR_CRAT_EN, 2307 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2300 bridge->base + TSI148_LCSR_CRAT); 2308 bridge->base + TSI148_LCSR_CRAT);
2301 } else 2309 }
2302 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2303 2310
2304 /* If we want flushed, error-checked writes, set up a window 2311 /* If we want flushed, error-checked writes, set up a window
2305 * over the CR/CSR registers. We read from here to safely flush 2312 * over the CR/CSR registers. We read from here to safely flush
@@ -2441,13 +2448,6 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2441 spin_lock_init(&tsi148_device->flush_image->lock); 2448 spin_lock_init(&tsi148_device->flush_image->lock);
2442 tsi148_device->flush_image->locked = 1; 2449 tsi148_device->flush_image->locked = 1;
2443 tsi148_device->flush_image->number = master_num; 2450 tsi148_device->flush_image->number = master_num;
2444 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2445 VME_A32 | VME_A64;
2446 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2447 VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2448 VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2449 VME_USER | VME_PROG | VME_DATA;
2450 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
2451 memset(&tsi148_device->flush_image->bus_resource, 0, 2451 memset(&tsi148_device->flush_image->bus_resource, 0,
2452 sizeof(struct resource)); 2452 sizeof(struct resource));
2453 tsi148_device->flush_image->kern_base = NULL; 2453 tsi148_device->flush_image->kern_base = NULL;
@@ -2582,7 +2582,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2582 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", 2582 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2583 err_chk ? "enabled" : "disabled"); 2583 err_chk ? "enabled" : "disabled");
2584 2584
2585 if (tsi148_crcsr_init(tsi148_bridge, pdev)) { 2585 retval = tsi148_crcsr_init(tsi148_bridge, pdev);
2586 if (retval) {
2586 dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); 2587 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2587 goto err_crcsr; 2588 goto err_crcsr;
2588 } 2589 }