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-rw-r--r--drivers/video/via/Makefile2
-rw-r--r--drivers/video/via/hw.c288
-rw-r--r--drivers/video/via/hw.h6
-rw-r--r--drivers/video/via/via_clock.c280
-rw-r--r--drivers/video/via/via_clock.h73
5 files changed, 368 insertions, 281 deletions
diff --git a/drivers/video/via/Makefile b/drivers/video/via/Makefile
index 96f01ee2a412..5108136e8776 100644
--- a/drivers/video/via/Makefile
+++ b/drivers/video/via/Makefile
@@ -6,4 +6,4 @@ obj-$(CONFIG_FB_VIA) += viafb.o
6 6
7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \ 7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \
8 via_utility.o vt1636.o global.o tblDPASetting.o viamode.o \ 8 via_utility.o vt1636.o global.o tblDPASetting.o viamode.o \
9 via-core.o via-gpio.o via_modesetting.o 9 via-core.o via-gpio.o via_modesetting.o via_clock.o
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 712348df0f84..f1eff0b4831f 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -21,6 +21,7 @@
21 21
22#include <linux/via-core.h> 22#include <linux/via-core.h>
23#include "global.h" 23#include "global.h"
24#include "via_clock.h"
24 25
25static struct pll_limit cle266_pll_limits[] = { 26static struct pll_limit cle266_pll_limits[] = {
26 {19, 19, 4, 0}, 27 {19, 19, 4, 0},
@@ -484,6 +485,9 @@ static struct via_device_mapping device_mapping[] = {
484 {VIA_LVDS2, "LVDS2"} 485 {VIA_LVDS2, "LVDS2"}
485}; 486};
486 487
488/* structure with function pointers to support clock control */
489static struct via_clock clock;
490
487static void load_fix_bit_crtc_reg(void); 491static void load_fix_bit_crtc_reg(void);
488static void __devinit init_gfx_chip_info(int chip_type); 492static void __devinit init_gfx_chip_info(int chip_type);
489static void __devinit init_tmds_chip_info(void); 493static void __devinit init_tmds_chip_info(void);
@@ -1409,230 +1413,10 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1409 1413
1410} 1414}
1411 1415
1412static void set_primary_clock_state(u8 state) 1416static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
1413{
1414 u8 value;
1415
1416 switch (state) {
1417 case VIA_STATE_ON:
1418 value = 0x20;
1419 break;
1420 case VIA_STATE_OFF:
1421 value = 0x00;
1422 break;
1423 default:
1424 return;
1425 }
1426
1427 via_write_reg_mask(VIASR, 0x1B, value, 0x30);
1428}
1429
1430static void set_secondary_clock_state(u8 state)
1431{
1432 u8 value;
1433
1434 switch (state) {
1435 case VIA_STATE_ON:
1436 value = 0x80;
1437 break;
1438 case VIA_STATE_OFF:
1439 value = 0x00;
1440 break;
1441 default:
1442 return;
1443 }
1444
1445 via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
1446}
1447
1448static void set_primary_pll_state(u8 state)
1449{
1450 u8 value;
1451
1452 switch (state) {
1453 case VIA_STATE_ON:
1454 value = 0x20;
1455 break;
1456 case VIA_STATE_OFF:
1457 value = 0x00;
1458 break;
1459 default:
1460 return;
1461 }
1462
1463 via_write_reg_mask(VIASR, 0x2D, value, 0x30);
1464}
1465
1466static void set_secondary_pll_state(u8 state)
1467{
1468 u8 value;
1469
1470 switch (state) {
1471 case VIA_STATE_ON:
1472 value = 0x08;
1473 break;
1474 case VIA_STATE_OFF:
1475 value = 0x00;
1476 break;
1477 default:
1478 return;
1479 }
1480
1481 via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
1482}
1483
1484static u32 cle266_encode_pll(struct pll_config pll)
1485{
1486 return (pll.multiplier << 8)
1487 | (pll.rshift << 6)
1488 | pll.divisor;
1489}
1490
1491static u32 k800_encode_pll(struct pll_config pll)
1492{
1493 return ((pll.divisor - 2) << 16)
1494 | (pll.rshift << 10)
1495 | (pll.multiplier - 2);
1496}
1497
1498static u32 vx855_encode_pll(struct pll_config pll)
1499{
1500 return (pll.divisor << 16)
1501 | (pll.rshift << 10)
1502 | pll.multiplier;
1503}
1504
1505static inline void cle266_set_primary_pll_encoded(u32 data)
1506{
1507 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
1508 via_write_reg(VIASR, 0x46, data & 0xFF);
1509 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
1510 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
1511}
1512
1513static inline void k800_set_primary_pll_encoded(u32 data)
1514{
1515 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
1516 via_write_reg(VIASR, 0x44, data & 0xFF);
1517 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
1518 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
1519 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
1520}
1521
1522static inline void cle266_set_secondary_pll_encoded(u32 data)
1523{
1524 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
1525 via_write_reg(VIASR, 0x44, data & 0xFF);
1526 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
1527 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
1528}
1529
1530static inline void k800_set_secondary_pll_encoded(u32 data)
1531{
1532 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
1533 via_write_reg(VIASR, 0x4A, data & 0xFF);
1534 via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
1535 via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
1536 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
1537}
1538
1539static void cle266_set_primary_pll(struct pll_config config)
1540{
1541 cle266_set_primary_pll_encoded(cle266_encode_pll(config));
1542}
1543
1544static void k800_set_primary_pll(struct pll_config config)
1545{
1546 k800_set_primary_pll_encoded(k800_encode_pll(config));
1547}
1548
1549static void vx855_set_primary_pll(struct pll_config config)
1550{
1551 k800_set_primary_pll_encoded(vx855_encode_pll(config));
1552}
1553
1554static void cle266_set_secondary_pll(struct pll_config config)
1555{
1556 cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
1557}
1558
1559static void k800_set_secondary_pll(struct pll_config config)
1560{
1561 k800_set_secondary_pll_encoded(k800_encode_pll(config));
1562}
1563
1564static void vx855_set_secondary_pll(struct pll_config config)
1565{
1566 k800_set_secondary_pll_encoded(vx855_encode_pll(config));
1567}
1568
1569enum via_clksrc {
1570 VIA_CLKSRC_X1 = 0,
1571 VIA_CLKSRC_TVX1,
1572 VIA_CLKSRC_TVPLL,
1573 VIA_CLKSRC_DVP1TVCLKR,
1574 VIA_CLKSRC_CAP0,
1575 VIA_CLKSRC_CAP1,
1576};
1577
1578static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
1579{
1580 u8 data = 0;
1581
1582 switch (source) {
1583 case VIA_CLKSRC_X1:
1584 data = 0x00;
1585 break;
1586 case VIA_CLKSRC_TVX1:
1587 data = 0x02;
1588 break;
1589 case VIA_CLKSRC_TVPLL:
1590 data = 0x04; /* 0x06 should be the same */
1591 break;
1592 case VIA_CLKSRC_DVP1TVCLKR:
1593 data = 0x0A;
1594 break;
1595 case VIA_CLKSRC_CAP0:
1596 data = 0xC;
1597 break;
1598 case VIA_CLKSRC_CAP1:
1599 data = 0x0E;
1600 break;
1601 }
1602
1603 if (!use_pll)
1604 data |= 1;
1605
1606 return data;
1607}
1608
1609static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
1610{
1611 u8 data = set_clock_source_common(source, use_pll) << 4;
1612 via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
1613}
1614
1615static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
1616{
1617 u8 data = set_clock_source_common(source, use_pll);
1618 via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
1619}
1620
1621static inline u32 get_pll_internal_frequency(u32 ref_freq,
1622 struct pll_config pll)
1623{
1624 return ref_freq / pll.divisor * pll.multiplier;
1625}
1626
1627static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
1628{
1629 return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
1630}
1631
1632static struct pll_config get_pll_config(struct pll_limit *limits, int size,
1633 int clk) 1417 int clk)
1634{ 1418{
1635 struct pll_config cur, up, down, best = {0, 1, 0}; 1419 struct via_pll_config cur, up, down, best = {0, 1, 0};
1636 const u32 f0 = 14318180; /* X1 frequency */ 1420 const u32 f0 = 14318180; /* X1 frequency */
1637 int i, f; 1421 int i, f;
1638 1422
@@ -1662,9 +1446,9 @@ static struct pll_config get_pll_config(struct pll_limit *limits, int size,
1662 return best; 1446 return best;
1663} 1447}
1664 1448
1665static struct pll_config get_best_pll_config(int clk) 1449static struct via_pll_config get_best_pll_config(int clk)
1666{ 1450{
1667 struct pll_config config; 1451 struct via_pll_config config;
1668 1452
1669 switch (viaparinfo->chip_info->gfx_chip_name) { 1453 switch (viaparinfo->chip_info->gfx_chip_name) {
1670 case UNICHROME_CLE266: 1454 case UNICHROME_CLE266:
@@ -1700,57 +1484,12 @@ static struct pll_config get_best_pll_config(int clk)
1700/* Set VCLK*/ 1484/* Set VCLK*/
1701void viafb_set_vclock(u32 clk, int set_iga) 1485void viafb_set_vclock(u32 clk, int set_iga)
1702{ 1486{
1703 struct pll_config config = get_best_pll_config(clk); 1487 struct via_pll_config config = get_best_pll_config(clk);
1704 1488
1705 if (set_iga == IGA1) { 1489 if (set_iga == IGA1)
1706 /* Change D,N FOR VCLK */ 1490 clock.set_primary_pll(config);
1707 switch (viaparinfo->chip_info->gfx_chip_name) { 1491 if (set_iga == IGA2)
1708 case UNICHROME_CLE266: 1492 clock.set_secondary_pll(config);
1709 case UNICHROME_K400:
1710 cle266_set_primary_pll(config);
1711 break;
1712 case UNICHROME_K800:
1713 case UNICHROME_PM800:
1714 case UNICHROME_CN700:
1715 case UNICHROME_CX700:
1716 case UNICHROME_CN750:
1717 case UNICHROME_K8M890:
1718 case UNICHROME_P4M890:
1719 case UNICHROME_P4M900:
1720 case UNICHROME_VX800:
1721 k800_set_primary_pll(config);
1722 break;
1723 case UNICHROME_VX855:
1724 case UNICHROME_VX900:
1725 vx855_set_primary_pll(config);
1726 break;
1727 }
1728 }
1729
1730 if (set_iga == IGA2) {
1731 /* Change D,N FOR LCK */
1732 switch (viaparinfo->chip_info->gfx_chip_name) {
1733 case UNICHROME_CLE266:
1734 case UNICHROME_K400:
1735 cle266_set_secondary_pll(config);
1736 break;
1737 case UNICHROME_K800:
1738 case UNICHROME_PM800:
1739 case UNICHROME_CN700:
1740 case UNICHROME_CX700:
1741 case UNICHROME_CN750:
1742 case UNICHROME_K8M890:
1743 case UNICHROME_P4M890:
1744 case UNICHROME_P4M900:
1745 case UNICHROME_VX800:
1746 k800_set_secondary_pll(config);
1747 break;
1748 case UNICHROME_VX855:
1749 case UNICHROME_VX900:
1750 vx855_set_secondary_pll(config);
1751 break;
1752 }
1753 }
1754 1493
1755 /* Fire! */ 1494 /* Fire! */
1756 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ 1495 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
@@ -2059,6 +1798,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2059 1798
2060void __devinit viafb_init_chip_info(int chip_type) 1799void __devinit viafb_init_chip_info(int chip_type)
2061{ 1800{
1801 via_clock_init(&clock, chip_type);
2062 init_gfx_chip_info(chip_type); 1802 init_gfx_chip_info(chip_type);
2063 init_tmds_chip_info(); 1803 init_tmds_chip_info();
2064 init_lvds_chip_info(); 1804 init_lvds_chip_info();
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 2cdce9b7eb8e..7e9f51a83126 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -732,12 +732,6 @@ struct _lcd_scaling_factor {
732 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor; 732 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
733}; 733};
734 734
735struct pll_config {
736 u16 multiplier;
737 u8 divisor;
738 u8 rshift;
739};
740
741struct pll_limit { 735struct pll_limit {
742 u16 multiplier_min; 736 u16 multiplier_min;
743 u16 multiplier_max; 737 u16 multiplier_max;
diff --git a/drivers/video/via/via_clock.c b/drivers/video/via/via_clock.c
new file mode 100644
index 000000000000..29afe4ce3492
--- /dev/null
+++ b/drivers/video/via/via_clock.c
@@ -0,0 +1,280 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
13 * the implied warranty of MERCHANTABILITY or FITNESS FOR
14 * A PARTICULAR PURPOSE.See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22/*
23 * clock and PLL management functions
24 */
25
26#include <linux/kernel.h>
27#include <linux/via-core.h>
28#include "via_clock.h"
29#include "global.h"
30#include "debug.h"
31
32static inline u32 cle266_encode_pll(struct via_pll_config pll)
33{
34 return (pll.multiplier << 8)
35 | (pll.rshift << 6)
36 | pll.divisor;
37}
38
39static inline u32 k800_encode_pll(struct via_pll_config pll)
40{
41 return ((pll.divisor - 2) << 16)
42 | (pll.rshift << 10)
43 | (pll.multiplier - 2);
44}
45
46static inline u32 vx855_encode_pll(struct via_pll_config pll)
47{
48 return (pll.divisor << 16)
49 | (pll.rshift << 10)
50 | pll.multiplier;
51}
52
53static inline void cle266_set_primary_pll_encoded(u32 data)
54{
55 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
56 via_write_reg(VIASR, 0x46, data & 0xFF);
57 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
58 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
59}
60
61static inline void k800_set_primary_pll_encoded(u32 data)
62{
63 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
64 via_write_reg(VIASR, 0x44, data & 0xFF);
65 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
66 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
67 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
68}
69
70static inline void cle266_set_secondary_pll_encoded(u32 data)
71{
72 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
73 via_write_reg(VIASR, 0x44, data & 0xFF);
74 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
75 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
76}
77
78static inline void k800_set_secondary_pll_encoded(u32 data)
79{
80 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
81 via_write_reg(VIASR, 0x4A, data & 0xFF);
82 via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
83 via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
84 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
85}
86
87static void cle266_set_primary_pll(struct via_pll_config config)
88{
89 cle266_set_primary_pll_encoded(cle266_encode_pll(config));
90}
91
92static void k800_set_primary_pll(struct via_pll_config config)
93{
94 k800_set_primary_pll_encoded(k800_encode_pll(config));
95}
96
97static void vx855_set_primary_pll(struct via_pll_config config)
98{
99 k800_set_primary_pll_encoded(vx855_encode_pll(config));
100}
101
102static void cle266_set_secondary_pll(struct via_pll_config config)
103{
104 cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
105}
106
107static void k800_set_secondary_pll(struct via_pll_config config)
108{
109 k800_set_secondary_pll_encoded(k800_encode_pll(config));
110}
111
112static void vx855_set_secondary_pll(struct via_pll_config config)
113{
114 k800_set_secondary_pll_encoded(vx855_encode_pll(config));
115}
116
117static void set_primary_pll_state(u8 state)
118{
119 u8 value;
120
121 switch (state) {
122 case VIA_STATE_ON:
123 value = 0x20;
124 break;
125 case VIA_STATE_OFF:
126 value = 0x00;
127 break;
128 default:
129 return;
130 }
131
132 via_write_reg_mask(VIASR, 0x2D, value, 0x30);
133}
134
135static void set_secondary_pll_state(u8 state)
136{
137 u8 value;
138
139 switch (state) {
140 case VIA_STATE_ON:
141 value = 0x08;
142 break;
143 case VIA_STATE_OFF:
144 value = 0x00;
145 break;
146 default:
147 return;
148 }
149
150 via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
151}
152
153static void set_primary_clock_state(u8 state)
154{
155 u8 value;
156
157 switch (state) {
158 case VIA_STATE_ON:
159 value = 0x20;
160 break;
161 case VIA_STATE_OFF:
162 value = 0x00;
163 break;
164 default:
165 return;
166 }
167
168 via_write_reg_mask(VIASR, 0x1B, value, 0x30);
169}
170
171static void set_secondary_clock_state(u8 state)
172{
173 u8 value;
174
175 switch (state) {
176 case VIA_STATE_ON:
177 value = 0x80;
178 break;
179 case VIA_STATE_OFF:
180 value = 0x00;
181 break;
182 default:
183 return;
184 }
185
186 via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
187}
188
189static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
190{
191 u8 data = 0;
192
193 switch (source) {
194 case VIA_CLKSRC_X1:
195 data = 0x00;
196 break;
197 case VIA_CLKSRC_TVX1:
198 data = 0x02;
199 break;
200 case VIA_CLKSRC_TVPLL:
201 data = 0x04; /* 0x06 should be the same */
202 break;
203 case VIA_CLKSRC_DVP1TVCLKR:
204 data = 0x0A;
205 break;
206 case VIA_CLKSRC_CAP0:
207 data = 0xC;
208 break;
209 case VIA_CLKSRC_CAP1:
210 data = 0x0E;
211 break;
212 }
213
214 if (!use_pll)
215 data |= 1;
216
217 return data;
218}
219
220static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
221{
222 u8 data = set_clock_source_common(source, use_pll) << 4;
223 via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
224}
225
226static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
227{
228 u8 data = set_clock_source_common(source, use_pll);
229 via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
230}
231
232void via_clock_init(struct via_clock *clock, int gfx_chip)
233{
234 switch (gfx_chip) {
235 case UNICHROME_CLE266:
236 case UNICHROME_K400:
237 clock->set_primary_clock_state = NULL;
238 clock->set_primary_clock_source = NULL;
239 clock->set_primary_pll_state = NULL;
240 clock->set_primary_pll = cle266_set_primary_pll;
241
242 clock->set_secondary_clock_state = NULL;
243 clock->set_secondary_clock_source = NULL;
244 clock->set_secondary_pll_state = NULL;
245 clock->set_secondary_pll = cle266_set_secondary_pll;
246 break;
247 case UNICHROME_K800:
248 case UNICHROME_PM800:
249 case UNICHROME_CN700:
250 case UNICHROME_CX700:
251 case UNICHROME_CN750:
252 case UNICHROME_K8M890:
253 case UNICHROME_P4M890:
254 case UNICHROME_P4M900:
255 case UNICHROME_VX800:
256 clock->set_primary_clock_state = set_primary_clock_state;
257 clock->set_primary_clock_source = set_primary_clock_source;
258 clock->set_primary_pll_state = set_primary_pll_state;
259 clock->set_primary_pll = k800_set_primary_pll;
260
261 clock->set_secondary_clock_state = set_secondary_clock_state;
262 clock->set_secondary_clock_source = set_secondary_clock_source;
263 clock->set_secondary_pll_state = set_secondary_pll_state;
264 clock->set_secondary_pll = k800_set_secondary_pll;
265 break;
266 case UNICHROME_VX855:
267 case UNICHROME_VX900:
268 clock->set_primary_clock_state = set_primary_clock_state;
269 clock->set_primary_clock_source = set_primary_clock_source;
270 clock->set_primary_pll_state = set_primary_pll_state;
271 clock->set_primary_pll = vx855_set_primary_pll;
272
273 clock->set_secondary_clock_state = set_secondary_clock_state;
274 clock->set_secondary_clock_source = set_secondary_clock_source;
275 clock->set_secondary_pll_state = set_secondary_pll_state;
276 clock->set_secondary_pll = vx855_set_secondary_pll;
277 break;
278
279 }
280}
diff --git a/drivers/video/via/via_clock.h b/drivers/video/via/via_clock.h
new file mode 100644
index 000000000000..f213a7a8fc79
--- /dev/null
+++ b/drivers/video/via/via_clock.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
13 * the implied warranty of MERCHANTABILITY or FITNESS FOR
14 * A PARTICULAR PURPOSE.See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22/*
23 * clock and PLL management functions
24 */
25
26#ifndef __VIA_CLOCK_H__
27#define __VIA_CLOCK_H__
28
29#include <linux/types.h>
30
31enum via_clksrc {
32 VIA_CLKSRC_X1 = 0,
33 VIA_CLKSRC_TVX1,
34 VIA_CLKSRC_TVPLL,
35 VIA_CLKSRC_DVP1TVCLKR,
36 VIA_CLKSRC_CAP0,
37 VIA_CLKSRC_CAP1,
38};
39
40struct via_pll_config {
41 u16 multiplier;
42 u8 divisor;
43 u8 rshift;
44};
45
46struct via_clock {
47 void (*set_primary_clock_state)(u8 state);
48 void (*set_primary_clock_source)(enum via_clksrc src, bool use_pll);
49 void (*set_primary_pll_state)(u8 state);
50 void (*set_primary_pll)(struct via_pll_config config);
51
52 void (*set_secondary_clock_state)(u8 state);
53 void (*set_secondary_clock_source)(enum via_clksrc src, bool use_pll);
54 void (*set_secondary_pll_state)(u8 state);
55 void (*set_secondary_pll)(struct via_pll_config config);
56};
57
58
59static inline u32 get_pll_internal_frequency(u32 ref_freq,
60 struct via_pll_config pll)
61{
62 return ref_freq / pll.divisor * pll.multiplier;
63}
64
65static inline u32 get_pll_output_frequency(u32 ref_freq,
66 struct via_pll_config pll)
67{
68 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift;
69}
70
71void via_clock_init(struct via_clock *clock, int gfx_chip);
72
73#endif /* __VIA_CLOCK_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 20:05:33 -0500