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path: root/drivers/video/via/hw.c
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Diffstat (limited to 'drivers/video/via/hw.c')
-rw-r--r--drivers/video/via/hw.c32
1 files changed, 17 insertions, 15 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 063ff65fbea6..c28ae2e85ef6 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1474,7 +1474,7 @@ static struct pll_config get_pll_config(struct pll_limit *limits, int size,
1474 return best; 1474 return best;
1475} 1475}
1476 1476
1477u32 viafb_get_clk_value(int clk) 1477static u32 viafb_get_clk_value(int clk)
1478{ 1478{
1479 u32 value = 0; 1479 u32 value = 0;
1480 1480
@@ -1512,6 +1512,10 @@ u32 viafb_get_clk_value(int clk)
1512/* Set VCLK*/ 1512/* Set VCLK*/
1513void viafb_set_vclock(u32 clk, int set_iga) 1513void viafb_set_vclock(u32 clk, int set_iga)
1514{ 1514{
1515 u32 value = viafb_get_clk_value(clk);
1516
1517 DEBUG_MSG(KERN_INFO "PLL=0x%x", value);
1518
1515 /* H.W. Reset : ON */ 1519 /* H.W. Reset : ON */
1516 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); 1520 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1517 1521
@@ -1520,8 +1524,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
1520 switch (viaparinfo->chip_info->gfx_chip_name) { 1524 switch (viaparinfo->chip_info->gfx_chip_name) {
1521 case UNICHROME_CLE266: 1525 case UNICHROME_CLE266:
1522 case UNICHROME_K400: 1526 case UNICHROME_K400:
1523 via_write_reg(VIASR, SR46, (clk & 0x00FF)); 1527 via_write_reg(VIASR, SR46, (value & 0x00FF));
1524 via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8); 1528 via_write_reg(VIASR, SR47, (value & 0xFF00) >> 8);
1525 break; 1529 break;
1526 1530
1527 case UNICHROME_K800: 1531 case UNICHROME_K800:
@@ -1535,9 +1539,9 @@ void viafb_set_vclock(u32 clk, int set_iga)
1535 case UNICHROME_VX800: 1539 case UNICHROME_VX800:
1536 case UNICHROME_VX855: 1540 case UNICHROME_VX855:
1537 case UNICHROME_VX900: 1541 case UNICHROME_VX900:
1538 via_write_reg(VIASR, SR44, (clk & 0x0000FF)); 1542 via_write_reg(VIASR, SR44, (value & 0x0000FF));
1539 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8); 1543 via_write_reg(VIASR, SR45, (value & 0x00FF00) >> 8);
1540 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16); 1544 via_write_reg(VIASR, SR46, (value & 0xFF0000) >> 16);
1541 break; 1545 break;
1542 } 1546 }
1543 } 1547 }
@@ -1547,8 +1551,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
1547 switch (viaparinfo->chip_info->gfx_chip_name) { 1551 switch (viaparinfo->chip_info->gfx_chip_name) {
1548 case UNICHROME_CLE266: 1552 case UNICHROME_CLE266:
1549 case UNICHROME_K400: 1553 case UNICHROME_K400:
1550 via_write_reg(VIASR, SR44, (clk & 0x00FF)); 1554 via_write_reg(VIASR, SR44, (value & 0x00FF));
1551 via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8); 1555 via_write_reg(VIASR, SR45, (value & 0xFF00) >> 8);
1552 break; 1556 break;
1553 1557
1554 case UNICHROME_K800: 1558 case UNICHROME_K800:
@@ -1562,9 +1566,9 @@ void viafb_set_vclock(u32 clk, int set_iga)
1562 case UNICHROME_VX800: 1566 case UNICHROME_VX800:
1563 case UNICHROME_VX855: 1567 case UNICHROME_VX855:
1564 case UNICHROME_VX900: 1568 case UNICHROME_VX900:
1565 via_write_reg(VIASR, SR4A, (clk & 0x0000FF)); 1569 via_write_reg(VIASR, SR4A, (value & 0x0000FF));
1566 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8); 1570 via_write_reg(VIASR, SR4B, (value & 0x00FF00) >> 8);
1567 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16); 1571 via_write_reg(VIASR, SR4C, (value & 0xFF0000) >> 16);
1568 break; 1572 break;
1569 } 1573 }
1570 } 1574 }
@@ -1827,7 +1831,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1827 int i; 1831 int i;
1828 int index = 0; 1832 int index = 0;
1829 int h_addr, v_addr; 1833 int h_addr, v_addr;
1830 u32 pll_D_N, clock, refresh = viafb_refresh; 1834 u32 clock, refresh = viafb_refresh;
1831 1835
1832 if (viafb_SAMM_ON && set_iga == IGA2) 1836 if (viafb_SAMM_ON && set_iga == IGA2)
1833 refresh = viafb_refresh1; 1837 refresh = viafb_refresh1;
@@ -1884,9 +1888,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1884 1888
1885 clock = crt_reg.hor_total * crt_reg.ver_total 1889 clock = crt_reg.hor_total * crt_reg.ver_total
1886 * crt_table[index].refresh_rate; 1890 * crt_table[index].refresh_rate;
1887 pll_D_N = viafb_get_clk_value(clock); 1891 viafb_set_vclock(clock, set_iga);
1888 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1889 viafb_set_vclock(pll_D_N, set_iga);
1890 1892
1891} 1893}
1892 1894