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path: root/drivers/video/via/hw.c
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Diffstat (limited to 'drivers/video/via/hw.c')
-rw-r--r--drivers/video/via/hw.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index dc4c778877ce..a982718f3998 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1162,6 +1162,8 @@ void via_odev_to_seq(struct seq_file *m, u32 odev)
1162 1162
1163static void load_fix_bit_crtc_reg(void) 1163static void load_fix_bit_crtc_reg(void)
1164{ 1164{
1165 viafb_unlock_crt();
1166
1165 /* always set to 1 */ 1167 /* always set to 1 */
1166 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); 1168 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1167 /* line compare should set all bits = 1 (extend modes) */ 1169 /* line compare should set all bits = 1 (extend modes) */
@@ -1169,8 +1171,6 @@ static void load_fix_bit_crtc_reg(void)
1169 /* line compare should set all bits = 1 (extend modes) */ 1171 /* line compare should set all bits = 1 (extend modes) */
1170 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4); 1172 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1171 /* line compare should set all bits = 1 (extend modes) */ 1173 /* line compare should set all bits = 1 (extend modes) */
1172 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1173 /* line compare should set all bits = 1 (extend modes) */
1174 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); 1174 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1175 /* line compare should set all bits = 1 (extend modes) */ 1175 /* line compare should set all bits = 1 (extend modes) */
1176 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); 1176 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
@@ -1181,6 +1181,10 @@ static void load_fix_bit_crtc_reg(void)
1181 viafb_write_reg(CR08, VIACR, 0x00); 1181 viafb_write_reg(CR08, VIACR, 0x00);
1182 /* extend mode always set to 0h */ 1182 /* extend mode always set to 0h */
1183 viafb_write_reg(CR14, VIACR, 0x00); 1183 viafb_write_reg(CR14, VIACR, 0x00);
1184 viafb_write_reg_mask(CR09, VIACR, 0x40, 0xDF);
1185 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1186
1187 viafb_lock_crt();
1184 1188
1185 /* If K8M800, enable Prefetch Mode. */ 1189 /* If K8M800, enable Prefetch Mode. */
1186 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) 1190 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
@@ -2033,8 +2037,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2033 v_addr = crt_reg.ver_addr; 2037 v_addr = crt_reg.ver_addr;
2034 if (set_iga == IGA1) { 2038 if (set_iga == IGA1) {
2035 viafb_unlock_crt(); 2039 viafb_unlock_crt();
2036 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
2037 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
2038 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); 2040 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
2039 } 2041 }
2040 2042
@@ -2047,7 +2049,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2047 break; 2049 break;
2048 } 2050 }
2049 2051
2050 load_fix_bit_crtc_reg();
2051 viafb_lock_crt(); 2052 viafb_lock_crt();
2052 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); 2053 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
2053 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga); 2054 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
@@ -2432,6 +2433,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2432 } 2433 }
2433 } 2434 }
2434 2435
2436 load_fix_bit_crtc_reg();
2435 via_set_primary_pitch(viafbinfo->fix.line_length); 2437 via_set_primary_pitch(viafbinfo->fix.line_length);
2436 via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length 2438 via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2437 : viafbinfo->fix.line_length); 2439 : viafbinfo->fix.line_length);