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-rw-r--r--drivers/video/nvidia/Makefile12
-rw-r--r--drivers/video/nvidia/nv_accel.c419
-rw-r--r--drivers/video/nvidia/nv_dma.h188
-rw-r--r--drivers/video/nvidia/nv_hw.c1593
-rw-r--r--drivers/video/nvidia/nv_i2c.c215
-rw-r--r--drivers/video/nvidia/nv_local.h107
-rw-r--r--drivers/video/nvidia/nv_of.c59
-rw-r--r--drivers/video/nvidia/nv_proto.h58
-rw-r--r--drivers/video/nvidia/nv_setup.c636
-rw-r--r--drivers/video/nvidia/nv_type.h174
-rw-r--r--drivers/video/nvidia/nvidia.c1729
11 files changed, 5190 insertions, 0 deletions
diff --git a/drivers/video/nvidia/Makefile b/drivers/video/nvidia/Makefile
new file mode 100644
index 000000000000..690d37e8de5b
--- /dev/null
+++ b/drivers/video/nvidia/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for the nVidia framebuffer driver
3#
4
5obj-$(CONFIG_FB_NVIDIA) += nvidiafb.o
6
7nvidiafb-y := nvidia.o nv_hw.o nv_setup.o \
8 nv_accel.o
9nvidiafb-$(CONFIG_FB_NVIDIA_I2C) += nv_i2c.o
10nvidiafb-$(CONFIG_PPC_OF) += nv_of.o
11
12nvidiafb-objs := $(nvidiafb-y) \ No newline at end of file
diff --git a/drivers/video/nvidia/nv_accel.c b/drivers/video/nvidia/nv_accel.c
new file mode 100644
index 000000000000..f377a29ec97a
--- /dev/null
+++ b/drivers/video/nvidia/nv_accel.c
@@ -0,0 +1,419 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#include <linux/fb.h>
51#include "nv_type.h"
52#include "nv_proto.h"
53#include "nv_dma.h"
54#include "nv_local.h"
55
56/* There is a HW race condition with videoram command buffers.
57 You can't jump to the location of your put offset. We write put
58 at the jump offset + SKIPS dwords with noop padding in between
59 to solve this problem */
60#define SKIPS 8
61
62static const int NVCopyROP[16] = {
63 0xCC, /* copy */
64 0x55 /* invert */
65};
66
67static const int NVCopyROP_PM[16] = {
68 0xCA, /* copy */
69 0x5A, /* invert */
70};
71
72static inline void NVFlush(struct nvidia_par *par)
73{
74 int count = 1000000000;
75
76 while (--count && READ_GET(par) != par->dmaPut) ;
77
78 if (!count) {
79 printk("nvidiafb: DMA Flush lockup\n");
80 par->lockup = 1;
81 }
82}
83
84static inline void NVSync(struct nvidia_par *par)
85{
86 int count = 1000000000;
87
88 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
89
90 if (!count) {
91 printk("nvidiafb: DMA Sync lockup\n");
92 par->lockup = 1;
93 }
94}
95
96static void NVDmaKickoff(struct nvidia_par *par)
97{
98 if (par->dmaCurrent != par->dmaPut) {
99 par->dmaPut = par->dmaCurrent;
100 WRITE_PUT(par, par->dmaPut);
101 }
102}
103
104static void NVDmaWait(struct nvidia_par *par, int size)
105{
106 int dmaGet;
107 int count = 1000000000, cnt;
108 size++;
109
110 while (par->dmaFree < size && --count && !par->lockup) {
111 dmaGet = READ_GET(par);
112
113 if (par->dmaPut >= dmaGet) {
114 par->dmaFree = par->dmaMax - par->dmaCurrent;
115 if (par->dmaFree < size) {
116 NVDmaNext(par, 0x20000000);
117 if (dmaGet <= SKIPS) {
118 if (par->dmaPut <= SKIPS)
119 WRITE_PUT(par, SKIPS + 1);
120 cnt = 1000000000;
121 do {
122 dmaGet = READ_GET(par);
123 } while (--cnt && dmaGet <= SKIPS);
124 if (!cnt) {
125 printk("DMA Get lockup\n");
126 par->lockup = 1;
127 }
128 }
129 WRITE_PUT(par, SKIPS);
130 par->dmaCurrent = par->dmaPut = SKIPS;
131 par->dmaFree = dmaGet - (SKIPS + 1);
132 }
133 } else
134 par->dmaFree = dmaGet - par->dmaCurrent - 1;
135 }
136
137 if (!count) {
138 printk("DMA Wait Lockup\n");
139 par->lockup = 1;
140 }
141}
142
143static void NVSetPattern(struct nvidia_par *par, u32 clr0, u32 clr1,
144 u32 pat0, u32 pat1)
145{
146 NVDmaStart(par, PATTERN_COLOR_0, 4);
147 NVDmaNext(par, clr0);
148 NVDmaNext(par, clr1);
149 NVDmaNext(par, pat0);
150 NVDmaNext(par, pat1);
151}
152
153static void NVSetRopSolid(struct nvidia_par *par, u32 rop, u32 planemask)
154{
155 if (planemask != ~0) {
156 NVSetPattern(par, 0, planemask, ~0, ~0);
157 if (par->currentRop != (rop + 32)) {
158 NVDmaStart(par, ROP_SET, 1);
159 NVDmaNext(par, NVCopyROP_PM[rop]);
160 par->currentRop = rop + 32;
161 }
162 } else if (par->currentRop != rop) {
163 if (par->currentRop >= 16)
164 NVSetPattern(par, ~0, ~0, ~0, ~0);
165 NVDmaStart(par, ROP_SET, 1);
166 NVDmaNext(par, NVCopyROP[rop]);
167 par->currentRop = rop;
168 }
169}
170
171static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
172 int x2, int y2)
173{
174 struct nvidia_par *par = info->par;
175 int h = y2 - y1 + 1;
176 int w = x2 - x1 + 1;
177
178 NVDmaStart(par, CLIP_POINT, 2);
179 NVDmaNext(par, (y1 << 16) | x1);
180 NVDmaNext(par, (h << 16) | w);
181}
182
183void NVResetGraphics(struct fb_info *info)
184{
185 struct nvidia_par *par = info->par;
186 u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
187 int pitch, i;
188
189 pitch = info->fix.line_length;
190
191 par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
192
193 for (i = 0; i < SKIPS; i++)
194 NV_WR32(&par->dmaBase[i], 0, 0x00000000);
195
196 NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
197 NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
198 NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
199 NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
200 NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
201 NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
202 NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
203 NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
204 NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
205 NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
206 NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
207 NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
208 NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
209 NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
210 NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
211 NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
212
213 par->dmaPut = 0;
214 par->dmaCurrent = 16 + SKIPS;
215 par->dmaMax = 8191;
216 par->dmaFree = par->dmaMax - par->dmaCurrent;
217
218 switch (info->var.bits_per_pixel) {
219 case 32:
220 case 24:
221 surfaceFormat = SURFACE_FORMAT_DEPTH24;
222 patternFormat = PATTERN_FORMAT_DEPTH24;
223 rectFormat = RECT_FORMAT_DEPTH24;
224 lineFormat = LINE_FORMAT_DEPTH24;
225 break;
226 case 16:
227 surfaceFormat = SURFACE_FORMAT_DEPTH16;
228 patternFormat = PATTERN_FORMAT_DEPTH16;
229 rectFormat = RECT_FORMAT_DEPTH16;
230 lineFormat = LINE_FORMAT_DEPTH16;
231 break;
232 default:
233 surfaceFormat = SURFACE_FORMAT_DEPTH8;
234 patternFormat = PATTERN_FORMAT_DEPTH8;
235 rectFormat = RECT_FORMAT_DEPTH8;
236 lineFormat = LINE_FORMAT_DEPTH8;
237 break;
238 }
239
240 NVDmaStart(par, SURFACE_FORMAT, 4);
241 NVDmaNext(par, surfaceFormat);
242 NVDmaNext(par, pitch | (pitch << 16));
243 NVDmaNext(par, 0);
244 NVDmaNext(par, 0);
245
246 NVDmaStart(par, PATTERN_FORMAT, 1);
247 NVDmaNext(par, patternFormat);
248
249 NVDmaStart(par, RECT_FORMAT, 1);
250 NVDmaNext(par, rectFormat);
251
252 NVDmaStart(par, LINE_FORMAT, 1);
253 NVDmaNext(par, lineFormat);
254
255 par->currentRop = ~0; /* set to something invalid */
256 NVSetRopSolid(par, ROP_COPY, ~0);
257
258 NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
259 info->var.yres_virtual);
260
261 NVDmaKickoff(par);
262}
263
264u8 byte_rev[256] = {
265 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
266 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
267 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
268 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
269 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
270 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
271 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
272 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
273 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
274 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
275 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
276 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
277 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
278 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
279 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
280 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
281 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
282 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
283 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
284 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
285 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
286 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
287 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
288 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
289 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
290 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
291 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
292 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
293 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
294 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
295 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
296 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
297};
298
299int nvidiafb_sync(struct fb_info *info)
300{
301 struct nvidia_par *par = info->par;
302
303 if (!par->lockup)
304 NVFlush(par);
305
306 if (!par->lockup)
307 NVSync(par);
308
309 return 0;
310}
311
312void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
313{
314 struct nvidia_par *par = info->par;
315
316 if (par->lockup)
317 return cfb_copyarea(info, region);
318
319 NVDmaStart(par, BLIT_POINT_SRC, 3);
320 NVDmaNext(par, (region->sy << 16) | region->sx);
321 NVDmaNext(par, (region->dy << 16) | region->dx);
322 NVDmaNext(par, (region->height << 16) | region->width);
323
324 NVDmaKickoff(par);
325}
326
327void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
328{
329 struct nvidia_par *par = info->par;
330 u32 color;
331
332 if (par->lockup)
333 return cfb_fillrect(info, rect);
334
335 if (info->var.bits_per_pixel == 8)
336 color = rect->color;
337 else
338 color = ((u32 *) info->pseudo_palette)[rect->color];
339
340 if (rect->rop != ROP_COPY)
341 NVSetRopSolid(par, rect->rop, ~0);
342
343 NVDmaStart(par, RECT_SOLID_COLOR, 1);
344 NVDmaNext(par, color);
345
346 NVDmaStart(par, RECT_SOLID_RECTS(0), 2);
347 NVDmaNext(par, (rect->dx << 16) | rect->dy);
348 NVDmaNext(par, (rect->width << 16) | rect->height);
349
350 NVDmaKickoff(par);
351
352 if (rect->rop != ROP_COPY)
353 NVSetRopSolid(par, ROP_COPY, ~0);
354}
355
356static void nvidiafb_mono_color_expand(struct fb_info *info,
357 const struct fb_image *image)
358{
359 struct nvidia_par *par = info->par;
360 u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
361 u32 dsize, width, *data = (u32 *) image->data, tmp;
362 int j, k = 0;
363
364 width = (image->width + 31) & ~31;
365 dsize = (width * image->height) >> 5;
366
367 if (info->var.bits_per_pixel == 8) {
368 fg = image->fg_color | mask;
369 bg = image->bg_color | mask;
370 } else {
371 fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
372 bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
373 }
374
375 NVDmaStart(par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
376 NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
377 NVDmaNext(par, ((image->dy + image->height) << 16) |
378 ((image->dx + image->width) & 0xffff));
379 NVDmaNext(par, bg);
380 NVDmaNext(par, fg);
381 NVDmaNext(par, (image->height << 16) | width);
382 NVDmaNext(par, (image->height << 16) | width);
383 NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
384
385 while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
386 NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0),
387 RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
388
389 for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
390 tmp = data[k++];
391 reverse_order(&tmp);
392 NVDmaNext(par, tmp);
393 }
394
395 dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
396 }
397
398 if (dsize) {
399 NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
400
401 for (j = dsize; j--;) {
402 tmp = data[k++];
403 reverse_order(&tmp);
404 NVDmaNext(par, tmp);
405 }
406 }
407
408 NVDmaKickoff(par);
409}
410
411void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
412{
413 struct nvidia_par *par = info->par;
414
415 if (image->depth == 1 && !par->lockup)
416 nvidiafb_mono_color_expand(info, image);
417 else
418 cfb_imageblit(info, image);
419}
diff --git a/drivers/video/nvidia/nv_dma.h b/drivers/video/nvidia/nv_dma.h
new file mode 100644
index 000000000000..a7ed1c0acbbb
--- /dev/null
+++ b/drivers/video/nvidia/nv_dma.h
@@ -0,0 +1,188 @@
1
2 /***************************************************************************\
3|* *|
4|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
5|* *|
6|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
7|* international laws. Users and possessors of this source code are *|
8|* hereby granted a nonexclusive, royalty-free copyright license to *|
9|* use this code in individual and commercial software. *|
10|* *|
11|* Any use of this source code must include, in the user documenta- *|
12|* tion and internal comments to the code, notices to the end user *|
13|* as follows: *|
14|* *|
15|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
16|* *|
17|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
18|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
19|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
21|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
23|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
25|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
26|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
27|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28|* *|
29|* U.S. Government End Users. This source code is a "commercial *|
30|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
31|* consisting of "commercial computer software" and "commercial *|
32|* computer software documentation," as such terms are used in *|
33|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
35|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
36|* all U.S. Government End Users acquire the source code with only *|
37|* those rights set forth herein. *|
38|* *|
39 \***************************************************************************/
40
41/*
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
44 * where the source code is provided "as is" without warranty of any kind.
45 * The only usage restriction is for the copyright notices to be retained
46 * whenever code is used.
47 *
48 * Antonino Daplas <adaplas@pol.net> 2005-03-11
49 */
50
51#define SURFACE_FORMAT 0x00000300
52#define SURFACE_FORMAT_DEPTH8 0x00000001
53#define SURFACE_FORMAT_DEPTH15 0x00000002
54#define SURFACE_FORMAT_DEPTH16 0x00000004
55#define SURFACE_FORMAT_DEPTH24 0x00000006
56#define SURFACE_PITCH 0x00000304
57#define SURFACE_PITCH_SRC 15:0
58#define SURFACE_PITCH_DST 31:16
59#define SURFACE_OFFSET_SRC 0x00000308
60#define SURFACE_OFFSET_DST 0x0000030C
61
62#define ROP_SET 0x00002300
63
64#define PATTERN_FORMAT 0x00004300
65#define PATTERN_FORMAT_DEPTH8 0x00000003
66#define PATTERN_FORMAT_DEPTH16 0x00000001
67#define PATTERN_FORMAT_DEPTH24 0x00000003
68#define PATTERN_COLOR_0 0x00004310
69#define PATTERN_COLOR_1 0x00004314
70#define PATTERN_PATTERN_0 0x00004318
71#define PATTERN_PATTERN_1 0x0000431C
72
73#define CLIP_POINT 0x00006300
74#define CLIP_POINT_X 15:0
75#define CLIP_POINT_Y 31:16
76#define CLIP_SIZE 0x00006304
77#define CLIP_SIZE_WIDTH 15:0
78#define CLIP_SIZE_HEIGHT 31:16
79
80#define LINE_FORMAT 0x00008300
81#define LINE_FORMAT_DEPTH8 0x00000003
82#define LINE_FORMAT_DEPTH16 0x00000001
83#define LINE_FORMAT_DEPTH24 0x00000003
84#define LINE_COLOR 0x00008304
85#define LINE_MAX_LINES 16
86#define LINE_LINES(i) 0x00008400\
87 +(i)*8
88#define LINE_LINES_POINT0_X 15:0
89#define LINE_LINES_POINT0_Y 31:16
90#define LINE_LINES_POINT1_X 47:32
91#define LINE_LINES_POINT1_Y 63:48
92
93#define BLIT_POINT_SRC 0x0000A300
94#define BLIT_POINT_SRC_X 15:0
95#define BLIT_POINT_SRC_Y 31:16
96#define BLIT_POINT_DST 0x0000A304
97#define BLIT_POINT_DST_X 15:0
98#define BLIT_POINT_DST_Y 31:16
99#define BLIT_SIZE 0x0000A308
100#define BLIT_SIZE_WIDTH 15:0
101#define BLIT_SIZE_HEIGHT 31:16
102
103#define RECT_FORMAT 0x0000C300
104#define RECT_FORMAT_DEPTH8 0x00000003
105#define RECT_FORMAT_DEPTH16 0x00000001
106#define RECT_FORMAT_DEPTH24 0x00000003
107#define RECT_SOLID_COLOR 0x0000C3FC
108#define RECT_SOLID_RECTS_MAX_RECTS 32
109#define RECT_SOLID_RECTS(i) 0x0000C400\
110 +(i)*8
111#define RECT_SOLID_RECTS_Y 15:0
112#define RECT_SOLID_RECTS_X 31:16
113#define RECT_SOLID_RECTS_HEIGHT 47:32
114#define RECT_SOLID_RECTS_WIDTH 63:48
115
116#define RECT_EXPAND_ONE_COLOR_CLIP 0x0000C7EC
117#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_X 15:0
118#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y 31:16
119#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_X 47:32
120#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_Y 63:48
121#define RECT_EXPAND_ONE_COLOR_COLOR 0x0000C7F4
122#define RECT_EXPAND_ONE_COLOR_SIZE 0x0000C7F8
123#define RECT_EXPAND_ONE_COLOR_SIZE_WIDTH 15:0
124#define RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT 31:16
125#define RECT_EXPAND_ONE_COLOR_POINT 0x0000C7FC
126#define RECT_EXPAND_ONE_COLOR_POINT_X 15:0
127#define RECT_EXPAND_ONE_COLOR_POINT_Y 31:16
128#define RECT_EXPAND_ONE_COLOR_DATA_MAX_DWORDS 128
129#define RECT_EXPAND_ONE_COLOR_DATA(i) 0x0000C800\
130 +(i)*4
131
132#define RECT_EXPAND_TWO_COLOR_CLIP 0x0000CBE4
133#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_X 15:0
134#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_Y 31:16
135#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_X 47:32
136#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_Y 63:48
137#define RECT_EXPAND_TWO_COLOR_COLOR_0 0x0000CBEC
138#define RECT_EXPAND_TWO_COLOR_COLOR_1 0x0000CBF0
139#define RECT_EXPAND_TWO_COLOR_SIZE_IN 0x0000CBF4
140#define RECT_EXPAND_TWO_COLOR_SIZE_IN_WIDTH 15:0
141#define RECT_EXPAND_TWO_COLOR_SIZE_IN_HEIGHT 31:16
142#define RECT_EXPAND_TWO_COLOR_SIZE_OUT 0x0000CBF8
143#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_WIDTH 15:0
144#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_HEIGHT 31:16
145#define RECT_EXPAND_TWO_COLOR_POINT 0x0000CBFC
146#define RECT_EXPAND_TWO_COLOR_POINT_X 15:0
147#define RECT_EXPAND_TWO_COLOR_POINT_Y 31:16
148#define RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS 128
149#define RECT_EXPAND_TWO_COLOR_DATA(i) 0x0000CC00\
150 +(i)*4
151
152#define STRETCH_BLIT_FORMAT 0x0000E300
153#define STRETCH_BLIT_FORMAT_DEPTH8 0x00000004
154#define STRETCH_BLIT_FORMAT_DEPTH16 0x00000007
155#define STRETCH_BLIT_FORMAT_DEPTH24 0x00000004
156#define STRETCH_BLIT_FORMAT_X8R8G8B8 0x00000004
157#define STRETCH_BLIT_FORMAT_YUYV 0x00000005
158#define STRETCH_BLIT_FORMAT_UYVY 0x00000006
159#define STRETCH_BLIT_CLIP_POINT 0x0000E308
160#define STRETCH_BLIT_CLIP_POINT_X 15:0
161#define STRETCH_BLIT_CLIP_POINT_Y 31:16
162#define STRETCH_BLIT_CLIP_POINT 0x0000E308
163#define STRETCH_BLIT_CLIP_SIZE 0x0000E30C
164#define STRETCH_BLIT_CLIP_SIZE_WIDTH 15:0
165#define STRETCH_BLIT_CLIP_SIZE_HEIGHT 31:16
166#define STRETCH_BLIT_DST_POINT 0x0000E310
167#define STRETCH_BLIT_DST_POINT_X 15:0
168#define STRETCH_BLIT_DST_POINT_Y 31:16
169#define STRETCH_BLIT_DST_SIZE 0x0000E314
170#define STRETCH_BLIT_DST_SIZE_WIDTH 15:0
171#define STRETCH_BLIT_DST_SIZE_HEIGHT 31:16
172#define STRETCH_BLIT_DU_DX 0x0000E318
173#define STRETCH_BLIT_DV_DY 0x0000E31C
174#define STRETCH_BLIT_SRC_SIZE 0x0000E400
175#define STRETCH_BLIT_SRC_SIZE_WIDTH 15:0
176#define STRETCH_BLIT_SRC_SIZE_HEIGHT 31:16
177#define STRETCH_BLIT_SRC_FORMAT 0x0000E404
178#define STRETCH_BLIT_SRC_FORMAT_PITCH 15:0
179#define STRETCH_BLIT_SRC_FORMAT_ORIGIN 23:16
180#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CENTER 0x00000001
181#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CORNER 0x00000002
182#define STRETCH_BLIT_SRC_FORMAT_FILTER 31:24
183#define STRETCH_BLIT_SRC_FORMAT_FILTER_POINT_SAMPLE 0x00000000
184#define STRETCH_BLIT_SRC_FORMAT_FILTER_BILINEAR 0x00000001
185#define STRETCH_BLIT_SRC_OFFSET 0x0000E408
186#define STRETCH_BLIT_SRC_POINT 0x0000E40C
187#define STRETCH_BLIT_SRC_POINT_U 15:0
188#define STRETCH_BLIT_SRC_POINT_V 31:16
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c
new file mode 100644
index 000000000000..b989358437b3
--- /dev/null
+++ b/drivers/video/nvidia/nv_hw.c
@@ -0,0 +1,1593 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
51
52#include <linux/pci.h>
53#include "nv_type.h"
54#include "nv_local.h"
55
56void NVLockUnlock(struct nvidia_par *par, int Lock)
57{
58 u8 cr11;
59
60 VGA_WR08(par->PCIO, 0x3D4, 0x1F);
61 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
62
63 VGA_WR08(par->PCIO, 0x3D4, 0x11);
64 cr11 = VGA_RD08(par->PCIO, 0x3D5);
65 if (Lock)
66 cr11 |= 0x80;
67 else
68 cr11 &= ~0x80;
69 VGA_WR08(par->PCIO, 0x3D5, cr11);
70}
71
72int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
73{
74 int cur = par->CurrentState->cursor1;
75
76 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
77 (ShowHide & 0x01);
78 VGA_WR08(par->PCIO, 0x3D4, 0x31);
79 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
80
81 if (par->Architecture == NV_ARCH_40)
82 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
83
84 return (cur & 0x01);
85}
86
87/****************************************************************************\
88* *
89* The video arbitration routines calculate some "magic" numbers. Fixes *
90* the snow seen when accessing the framebuffer without it. *
91* It just works (I hope). *
92* *
93\****************************************************************************/
94
95typedef struct {
96 int graphics_lwm;
97 int video_lwm;
98 int graphics_burst_size;
99 int video_burst_size;
100 int valid;
101} nv4_fifo_info;
102
103typedef struct {
104 int pclk_khz;
105 int mclk_khz;
106 int nvclk_khz;
107 char mem_page_miss;
108 char mem_latency;
109 int memory_width;
110 char enable_video;
111 char gr_during_vid;
112 char pix_bpp;
113 char mem_aligned;
114 char enable_mp;
115} nv4_sim_state;
116
117typedef struct {
118 int graphics_lwm;
119 int video_lwm;
120 int graphics_burst_size;
121 int video_burst_size;
122 int valid;
123} nv10_fifo_info;
124
125typedef struct {
126 int pclk_khz;
127 int mclk_khz;
128 int nvclk_khz;
129 char mem_page_miss;
130 char mem_latency;
131 int memory_type;
132 int memory_width;
133 char enable_video;
134 char gr_during_vid;
135 char pix_bpp;
136 char mem_aligned;
137 char enable_mp;
138} nv10_sim_state;
139
140static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
141 unsigned int *NVClk)
142{
143 unsigned int pll, N, M, MB, NB, P;
144
145 if (par->Architecture >= NV_ARCH_40) {
146 pll = NV_RD32(par->PMC, 0x4020);
147 P = (pll >> 16) & 0x03;
148 pll = NV_RD32(par->PMC, 0x4024);
149 M = pll & 0xFF;
150 N = (pll >> 8) & 0xFF;
151 MB = (pll >> 16) & 0xFF;
152 NB = (pll >> 24) & 0xFF;
153 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
154
155 pll = NV_RD32(par->PMC, 0x4000);
156 P = (pll >> 16) & 0x03;
157 pll = NV_RD32(par->PMC, 0x4004);
158 M = pll & 0xFF;
159 N = (pll >> 8) & 0xFF;
160 MB = (pll >> 16) & 0xFF;
161 NB = (pll >> 24) & 0xFF;
162
163 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
164 } else if (par->twoStagePLL) {
165 pll = NV_RD32(par->PRAMDAC0, 0x0504);
166 M = pll & 0xFF;
167 N = (pll >> 8) & 0xFF;
168 P = (pll >> 16) & 0x0F;
169 pll = NV_RD32(par->PRAMDAC0, 0x0574);
170 if (pll & 0x80000000) {
171 MB = pll & 0xFF;
172 NB = (pll >> 8) & 0xFF;
173 } else {
174 MB = 1;
175 NB = 1;
176 }
177 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
178
179 pll = NV_RD32(par->PRAMDAC0, 0x0500);
180 M = pll & 0xFF;
181 N = (pll >> 8) & 0xFF;
182 P = (pll >> 16) & 0x0F;
183 pll = NV_RD32(par->PRAMDAC0, 0x0570);
184 if (pll & 0x80000000) {
185 MB = pll & 0xFF;
186 NB = (pll >> 8) & 0xFF;
187 } else {
188 MB = 1;
189 NB = 1;
190 }
191 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
192 } else
193 if (((par->Chipset & 0x0ff0) == 0x0300) ||
194 ((par->Chipset & 0x0ff0) == 0x0330)) {
195 pll = NV_RD32(par->PRAMDAC0, 0x0504);
196 M = pll & 0x0F;
197 N = (pll >> 8) & 0xFF;
198 P = (pll >> 16) & 0x07;
199 if (pll & 0x00000080) {
200 MB = (pll >> 4) & 0x07;
201 NB = (pll >> 19) & 0x1f;
202 } else {
203 MB = 1;
204 NB = 1;
205 }
206 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
207
208 pll = NV_RD32(par->PRAMDAC0, 0x0500);
209 M = pll & 0x0F;
210 N = (pll >> 8) & 0xFF;
211 P = (pll >> 16) & 0x07;
212 if (pll & 0x00000080) {
213 MB = (pll >> 4) & 0x07;
214 NB = (pll >> 19) & 0x1f;
215 } else {
216 MB = 1;
217 NB = 1;
218 }
219 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
220 } else {
221 pll = NV_RD32(par->PRAMDAC0, 0x0504);
222 M = pll & 0xFF;
223 N = (pll >> 8) & 0xFF;
224 P = (pll >> 16) & 0x0F;
225 *MClk = (N * par->CrystalFreqKHz / M) >> P;
226
227 pll = NV_RD32(par->PRAMDAC0, 0x0500);
228 M = pll & 0xFF;
229 N = (pll >> 8) & 0xFF;
230 P = (pll >> 16) & 0x0F;
231 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
232 }
233}
234
235static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
236{
237 int data, pagemiss, cas, width, video_enable, bpp;
238 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
239 int found, mclk_extra, mclk_loop, cbs, m1, p1;
240 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
241 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
242 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
243
244 fifo->valid = 1;
245 pclk_freq = arb->pclk_khz;
246 mclk_freq = arb->mclk_khz;
247 nvclk_freq = arb->nvclk_khz;
248 pagemiss = arb->mem_page_miss;
249 cas = arb->mem_latency;
250 width = arb->memory_width >> 6;
251 video_enable = arb->enable_video;
252 bpp = arb->pix_bpp;
253 mp_enable = arb->enable_mp;
254 clwm = 0;
255 vlwm = 0;
256 cbs = 128;
257 pclks = 2;
258 nvclks = 2;
259 nvclks += 2;
260 nvclks += 1;
261 mclks = 5;
262 mclks += 3;
263 mclks += 1;
264 mclks += cas;
265 mclks += 1;
266 mclks += 1;
267 mclks += 1;
268 mclks += 1;
269 mclk_extra = 3;
270 nvclks += 2;
271 nvclks += 1;
272 nvclks += 1;
273 nvclks += 1;
274 if (mp_enable)
275 mclks += 4;
276 nvclks += 0;
277 pclks += 0;
278 found = 0;
279 vbs = 0;
280 while (found != 1) {
281 fifo->valid = 1;
282 found = 1;
283 mclk_loop = mclks + mclk_extra;
284 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
285 us_n = nvclks * 1000 * 1000 / nvclk_freq;
286 us_p = nvclks * 1000 * 1000 / pclk_freq;
287 if (video_enable) {
288 video_drain_rate = pclk_freq * 2;
289 crtc_drain_rate = pclk_freq * bpp / 8;
290 vpagemiss = 2;
291 vpagemiss += 1;
292 crtpagemiss = 2;
293 vpm_us =
294 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
295 if (nvclk_freq * 2 > mclk_freq * width)
296 video_fill_us =
297 cbs * 1000 * 1000 / 16 / nvclk_freq;
298 else
299 video_fill_us =
300 cbs * 1000 * 1000 / (8 * width) /
301 mclk_freq;
302 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
303 vlwm = us_video * video_drain_rate / (1000 * 1000);
304 vlwm++;
305 vbs = 128;
306 if (vlwm > 128)
307 vbs = 64;
308 if (vlwm > (256 - 64))
309 vbs = 32;
310 if (nvclk_freq * 2 > mclk_freq * width)
311 video_fill_us =
312 vbs * 1000 * 1000 / 16 / nvclk_freq;
313 else
314 video_fill_us =
315 vbs * 1000 * 1000 / (8 * width) /
316 mclk_freq;
317 cpm_us =
318 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
319 us_crt =
320 us_video + video_fill_us + cpm_us + us_m + us_n +
321 us_p;
322 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
323 clwm++;
324 } else {
325 crtc_drain_rate = pclk_freq * bpp / 8;
326 crtpagemiss = 2;
327 crtpagemiss += 1;
328 cpm_us =
329 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
330 us_crt = cpm_us + us_m + us_n + us_p;
331 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
332 clwm++;
333 }
334 m1 = clwm + cbs - 512;
335 p1 = m1 * pclk_freq / mclk_freq;
336 p1 = p1 * bpp / 8;
337 if ((p1 < m1) && (m1 > 0)) {
338 fifo->valid = 0;
339 found = 0;
340 if (mclk_extra == 0)
341 found = 1;
342 mclk_extra--;
343 } else if (video_enable) {
344 if ((clwm > 511) || (vlwm > 255)) {
345 fifo->valid = 0;
346 found = 0;
347 if (mclk_extra == 0)
348 found = 1;
349 mclk_extra--;
350 }
351 } else {
352 if (clwm > 519) {
353 fifo->valid = 0;
354 found = 0;
355 if (mclk_extra == 0)
356 found = 1;
357 mclk_extra--;
358 }
359 }
360 if (clwm < 384)
361 clwm = 384;
362 if (vlwm < 128)
363 vlwm = 128;
364 data = (int)(clwm);
365 fifo->graphics_lwm = data;
366 fifo->graphics_burst_size = 128;
367 data = (int)((vlwm + 15));
368 fifo->video_lwm = data;
369 fifo->video_burst_size = vbs;
370 }
371}
372
373static void nv4UpdateArbitrationSettings(unsigned VClk,
374 unsigned pixelDepth,
375 unsigned *burst,
376 unsigned *lwm, struct nvidia_par *par)
377{
378 nv4_fifo_info fifo_data;
379 nv4_sim_state sim_data;
380 unsigned int MClk, NVClk, cfg1;
381
382 nvGetClocks(par, &MClk, &NVClk);
383
384 cfg1 = NV_RD32(par->PFB, 0x00000204);
385 sim_data.pix_bpp = (char)pixelDepth;
386 sim_data.enable_video = 0;
387 sim_data.enable_mp = 0;
388 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
389 128 : 64;
390 sim_data.mem_latency = (char)cfg1 & 0x0F;
391 sim_data.mem_aligned = 1;
392 sim_data.mem_page_miss =
393 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
394 sim_data.gr_during_vid = 0;
395 sim_data.pclk_khz = VClk;
396 sim_data.mclk_khz = MClk;
397 sim_data.nvclk_khz = NVClk;
398 nv4CalcArbitration(&fifo_data, &sim_data);
399 if (fifo_data.valid) {
400 int b = fifo_data.graphics_burst_size >> 4;
401 *burst = 0;
402 while (b >>= 1)
403 (*burst)++;
404 *lwm = fifo_data.graphics_lwm >> 3;
405 }
406}
407
408static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
409{
410 int data, pagemiss, width, video_enable, bpp;
411 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
412 int nvclk_fill;
413 int found, mclk_extra, mclk_loop, cbs, m1;
414 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
415 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
416 int vus_m;
417 int vpm_us, us_video, cpm_us, us_crt, clwm;
418 int clwm_rnd_down;
419 int m2us, us_pipe_min, p1clk, p2;
420 int min_mclk_extra;
421 int us_min_mclk_extra;
422
423 fifo->valid = 1;
424 pclk_freq = arb->pclk_khz; /* freq in KHz */
425 mclk_freq = arb->mclk_khz;
426 nvclk_freq = arb->nvclk_khz;
427 pagemiss = arb->mem_page_miss;
428 width = arb->memory_width / 64;
429 video_enable = arb->enable_video;
430 bpp = arb->pix_bpp;
431 mp_enable = arb->enable_mp;
432 clwm = 0;
433
434 cbs = 512;
435
436 pclks = 4; /* lwm detect. */
437
438 nvclks = 3; /* lwm -> sync. */
439 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
440 /* 2 edge sync. may be very close to edge so just put one. */
441 mclks = 1;
442 mclks += 1; /* arb_hp_req */
443 mclks += 5; /* ap_hp_req tiling pipeline */
444
445 mclks += 2; /* tc_req latency fifo */
446 mclks += 2; /* fb_cas_n_ memory request to fbio block */
447 mclks += 7; /* sm_d_rdv data returned from fbio block */
448
449 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
450 if (arb->memory_type == 0)
451 if (arb->memory_width == 64) /* 64 bit bus */
452 mclks += 4;
453 else
454 mclks += 2;
455 else if (arb->memory_width == 64) /* 64 bit bus */
456 mclks += 2;
457 else
458 mclks += 1;
459
460 if ((!video_enable) && (arb->memory_width == 128)) {
461 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
462 min_mclk_extra = 17;
463 } else {
464 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
465 /* mclk_extra = 4; *//* Margin of error */
466 min_mclk_extra = 18;
467 }
468
469 /* 2 edge sync. may be very close to edge so just put one. */
470 nvclks += 1;
471 nvclks += 1; /* fbi_d_rdv_n */
472 nvclks += 1; /* Fbi_d_rdata */
473 nvclks += 1; /* crtfifo load */
474
475 if (mp_enable)
476 mclks += 4; /* Mp can get in with a burst of 8. */
477 /* Extra clocks determined by heuristics */
478
479 nvclks += 0;
480 pclks += 0;
481 found = 0;
482 while (found != 1) {
483 fifo->valid = 1;
484 found = 1;
485 mclk_loop = mclks + mclk_extra;
486 /* Mclk latency in us */
487 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
488 /* Minimum Mclk latency in us */
489 us_m_min = mclks * 1000 * 1000 / mclk_freq;
490 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
491 /* nvclk latency in us */
492 us_n = nvclks * 1000 * 1000 / nvclk_freq;
493 /* nvclk latency in us */
494 us_p = pclks * 1000 * 1000 / pclk_freq;
495 us_pipe_min = us_m_min + us_n + us_p;
496
497 /* Mclk latency in us */
498 vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
499
500 if (video_enable) {
501 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
502
503 vpagemiss = 1; /* self generating page miss */
504 vpagemiss += 1; /* One higher priority before */
505
506 crtpagemiss = 2; /* self generating page miss */
507 if (mp_enable)
508 crtpagemiss += 1; /* if MA0 conflict */
509
510 vpm_us =
511 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
512
513 /* Video has separate read return path */
514 us_video = vpm_us + vus_m;
515
516 cpm_us =
517 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
518 /* Wait for video */
519 us_crt = us_video
520 + cpm_us /* CRT Page miss */
521 + us_m + us_n + us_p /* other latency */
522 ;
523
524 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
525 /* fixed point <= float_point - 1. Fixes that */
526 clwm++;
527 } else {
528 /* bpp * pclk/8 */
529 crtc_drain_rate = pclk_freq * bpp / 8;
530
531 crtpagemiss = 1; /* self generating page miss */
532 crtpagemiss += 1; /* MA0 page miss */
533 if (mp_enable)
534 crtpagemiss += 1; /* if MA0 conflict */
535 cpm_us =
536 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
537 us_crt = cpm_us + us_m + us_n + us_p;
538 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
539 /* fixed point <= float_point - 1. Fixes that */
540 clwm++;
541
542 /* Finally, a heuristic check when width == 64 bits */
543 if (width == 1) {
544 nvclk_fill = nvclk_freq * 8;
545 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
546 /*Large number to fail */
547 clwm = 0xfff;
548
549 else if (crtc_drain_rate * 100 >=
550 nvclk_fill * 98) {
551 clwm = 1024;
552 cbs = 512;
553 }
554 }
555 }
556
557 /*
558 Overfill check:
559 */
560
561 clwm_rnd_down = ((int)clwm / 8) * 8;
562 if (clwm_rnd_down < clwm)
563 clwm += 8;
564
565 m1 = clwm + cbs - 1024; /* Amount of overfill */
566 m2us = us_pipe_min + us_min_mclk_extra;
567
568 /* pclk cycles to drain */
569 p1clk = m2us * pclk_freq / (1000 * 1000);
570 p2 = p1clk * bpp / 8; /* bytes drained. */
571
572 if ((p2 < m1) && (m1 > 0)) {
573 fifo->valid = 0;
574 found = 0;
575 if (min_mclk_extra == 0) {
576 if (cbs <= 32) {
577 /* Can't adjust anymore! */
578 found = 1;
579 } else {
580 /* reduce the burst size */
581 cbs = cbs / 2;
582 }
583 } else {
584 min_mclk_extra--;
585 }
586 } else {
587 if (clwm > 1023) { /* Have some margin */
588 fifo->valid = 0;
589 found = 0;
590 if (min_mclk_extra == 0)
591 /* Can't adjust anymore! */
592 found = 1;
593 else
594 min_mclk_extra--;
595 }
596 }
597
598 if (clwm < (1024 - cbs + 8))
599 clwm = 1024 - cbs + 8;
600 data = (int)(clwm);
601 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
602 clwm, data ); */
603 fifo->graphics_lwm = data;
604 fifo->graphics_burst_size = cbs;
605
606 fifo->video_lwm = 1024;
607 fifo->video_burst_size = 512;
608 }
609}
610
611static void nv10UpdateArbitrationSettings(unsigned VClk,
612 unsigned pixelDepth,
613 unsigned *burst,
614 unsigned *lwm,
615 struct nvidia_par *par)
616{
617 nv10_fifo_info fifo_data;
618 nv10_sim_state sim_data;
619 unsigned int MClk, NVClk, cfg1;
620
621 nvGetClocks(par, &MClk, &NVClk);
622
623 cfg1 = NV_RD32(par->PFB, 0x0204);
624 sim_data.pix_bpp = (char)pixelDepth;
625 sim_data.enable_video = 1;
626 sim_data.enable_mp = 0;
627 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
628 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
629 128 : 64;
630 sim_data.mem_latency = (char)cfg1 & 0x0F;
631 sim_data.mem_aligned = 1;
632 sim_data.mem_page_miss =
633 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
634 sim_data.gr_during_vid = 0;
635 sim_data.pclk_khz = VClk;
636 sim_data.mclk_khz = MClk;
637 sim_data.nvclk_khz = NVClk;
638 nv10CalcArbitration(&fifo_data, &sim_data);
639 if (fifo_data.valid) {
640 int b = fifo_data.graphics_burst_size >> 4;
641 *burst = 0;
642 while (b >>= 1)
643 (*burst)++;
644 *lwm = fifo_data.graphics_lwm >> 3;
645 }
646}
647
648static void nv30UpdateArbitrationSettings (
649 struct nvidia_par *par,
650 unsigned int *burst,
651 unsigned int *lwm
652)
653{
654 unsigned int MClk, NVClk;
655 unsigned int fifo_size, burst_size, graphics_lwm;
656
657 fifo_size = 2048;
658 burst_size = 512;
659 graphics_lwm = fifo_size - burst_size;
660
661 nvGetClocks(par, &MClk, &NVClk);
662
663 *burst = 0;
664 burst_size >>= 5;
665 while(burst_size >>= 1) (*burst)++;
666 *lwm = graphics_lwm >> 3;
667}
668
669static void nForceUpdateArbitrationSettings(unsigned VClk,
670 unsigned pixelDepth,
671 unsigned *burst,
672 unsigned *lwm,
673 struct nvidia_par *par)
674{
675 nv10_fifo_info fifo_data;
676 nv10_sim_state sim_data;
677 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
678 struct pci_dev *dev;
679
680 if ((par->Chipset & 0x0FF0) == 0x01A0) {
681 unsigned int uMClkPostDiv;
682 dev = pci_find_slot(0, 3);
683 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
684 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
685
686 if (!uMClkPostDiv)
687 uMClkPostDiv = 4;
688 MClk = 400000 / uMClkPostDiv;
689 } else {
690 dev = pci_find_slot(0, 5);
691 pci_read_config_dword(dev, 0x4c, &MClk);
692 MClk /= 1000;
693 }
694
695 pll = NV_RD32(par->PRAMDAC0, 0x0500);
696 M = (pll >> 0) & 0xFF;
697 N = (pll >> 8) & 0xFF;
698 P = (pll >> 16) & 0x0F;
699 NVClk = (N * par->CrystalFreqKHz / M) >> P;
700 sim_data.pix_bpp = (char)pixelDepth;
701 sim_data.enable_video = 0;
702 sim_data.enable_mp = 0;
703 pci_find_slot(0, 1);
704 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
705 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
706 sim_data.memory_width = 64;
707
708 dev = pci_find_slot(0, 3);
709 pci_read_config_dword(dev, 0, &memctrl);
710 memctrl >>= 16;
711
712 if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
713 int dimm[3];
714
715 pci_find_slot(0, 2);
716 pci_read_config_dword(dev, 0x40, &dimm[0]);
717 dimm[0] = (dimm[0] >> 8) & 0x4f;
718 pci_read_config_dword(dev, 0x44, &dimm[1]);
719 dimm[1] = (dimm[1] >> 8) & 0x4f;
720 pci_read_config_dword(dev, 0x48, &dimm[2]);
721 dimm[2] = (dimm[2] >> 8) & 0x4f;
722
723 if ((dimm[0] + dimm[1]) != dimm[2]) {
724 printk("nvidiafb: your nForce DIMMs are not arranged "
725 "in optimal banks!\n");
726 }
727 }
728
729 sim_data.mem_latency = 3;
730 sim_data.mem_aligned = 1;
731 sim_data.mem_page_miss = 10;
732 sim_data.gr_during_vid = 0;
733 sim_data.pclk_khz = VClk;
734 sim_data.mclk_khz = MClk;
735 sim_data.nvclk_khz = NVClk;
736 nv10CalcArbitration(&fifo_data, &sim_data);
737 if (fifo_data.valid) {
738 int b = fifo_data.graphics_burst_size >> 4;
739 *burst = 0;
740 while (b >>= 1)
741 (*burst)++;
742 *lwm = fifo_data.graphics_lwm >> 3;
743 }
744}
745
746/****************************************************************************\
747* *
748* RIVA Mode State Routines *
749* *
750\****************************************************************************/
751
752/*
753 * Calculate the Video Clock parameters for the PLL.
754 */
755static void CalcVClock(int clockIn,
756 int *clockOut, u32 * pllOut, struct nvidia_par *par)
757{
758 unsigned lowM, highM;
759 unsigned DeltaNew, DeltaOld;
760 unsigned VClk, Freq;
761 unsigned M, N, P;
762
763 DeltaOld = 0xFFFFFFFF;
764
765 VClk = (unsigned)clockIn;
766
767 if (par->CrystalFreqKHz == 13500) {
768 lowM = 7;
769 highM = 13;
770 } else {
771 lowM = 8;
772 highM = 14;
773 }
774
775 for (P = 0; P <= 4; P++) {
776 Freq = VClk << P;
777 if ((Freq >= 128000) && (Freq <= 350000)) {
778 for (M = lowM; M <= highM; M++) {
779 N = ((VClk << P) * M) / par->CrystalFreqKHz;
780 if (N <= 255) {
781 Freq =
782 ((par->CrystalFreqKHz * N) /
783 M) >> P;
784 if (Freq > VClk)
785 DeltaNew = Freq - VClk;
786 else
787 DeltaNew = VClk - Freq;
788 if (DeltaNew < DeltaOld) {
789 *pllOut =
790 (P << 16) | (N << 8) | M;
791 *clockOut = Freq;
792 DeltaOld = DeltaNew;
793 }
794 }
795 }
796 }
797 }
798}
799
800static void CalcVClock2Stage(int clockIn,
801 int *clockOut,
802 u32 * pllOut,
803 u32 * pllBOut, struct nvidia_par *par)
804{
805 unsigned DeltaNew, DeltaOld;
806 unsigned VClk, Freq;
807 unsigned M, N, P;
808
809 DeltaOld = 0xFFFFFFFF;
810
811 *pllBOut = 0x80000401; /* fixed at x4 for now */
812
813 VClk = (unsigned)clockIn;
814
815 for (P = 0; P <= 6; P++) {
816 Freq = VClk << P;
817 if ((Freq >= 400000) && (Freq <= 1000000)) {
818 for (M = 1; M <= 13; M++) {
819 N = ((VClk << P) * M) /
820 (par->CrystalFreqKHz << 2);
821 if ((N >= 5) && (N <= 255)) {
822 Freq =
823 (((par->CrystalFreqKHz << 2) * N) /
824 M) >> P;
825 if (Freq > VClk)
826 DeltaNew = Freq - VClk;
827 else
828 DeltaNew = VClk - Freq;
829 if (DeltaNew < DeltaOld) {
830 *pllOut =
831 (P << 16) | (N << 8) | M;
832 *clockOut = Freq;
833 DeltaOld = DeltaNew;
834 }
835 }
836 }
837 }
838 }
839}
840
841/*
842 * Calculate extended mode parameters (SVGA) and save in a
843 * mode state structure.
844 */
845void NVCalcStateExt(struct nvidia_par *par,
846 RIVA_HW_STATE * state,
847 int bpp,
848 int width,
849 int hDisplaySize, int height, int dotClock, int flags)
850{
851 int pixelDepth, VClk;
852 /*
853 * Save mode parameters.
854 */
855 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
856 state->width = width;
857 state->height = height;
858 /*
859 * Extended RIVA registers.
860 */
861 pixelDepth = (bpp + 1) / 8;
862 if (par->twoStagePLL)
863 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
864 par);
865 else
866 CalcVClock(dotClock, &VClk, &state->pll, par);
867
868 switch (par->Architecture) {
869 case NV_ARCH_04:
870 nv4UpdateArbitrationSettings(VClk,
871 pixelDepth * 8,
872 &(state->arbitration0),
873 &(state->arbitration1), par);
874 state->cursor0 = 0x00;
875 state->cursor1 = 0xbC;
876 if (flags & FB_VMODE_DOUBLE)
877 state->cursor1 |= 2;
878 state->cursor2 = 0x00000000;
879 state->pllsel = 0x10000700;
880 state->config = 0x00001114;
881 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
882 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
883 break;
884 case NV_ARCH_10:
885 case NV_ARCH_20:
886 case NV_ARCH_30:
887 default:
888 if (((par->Chipset & 0xffff) == 0x01A0) ||
889 ((par->Chipset & 0xffff) == 0x01f0)) {
890 nForceUpdateArbitrationSettings(VClk,
891 pixelDepth * 8,
892 &(state->arbitration0),
893 &(state->arbitration1),
894 par);
895 } else if (par->Architecture < NV_ARCH_30) {
896 nv10UpdateArbitrationSettings(VClk,
897 pixelDepth * 8,
898 &(state->arbitration0),
899 &(state->arbitration1),
900 par);
901 } else {
902 nv30UpdateArbitrationSettings(par,
903 &(state->arbitration0),
904 &(state->arbitration1));
905 }
906
907 state->cursor0 = 0x80 | (par->CursorStart >> 17);
908 state->cursor1 = (par->CursorStart >> 11) << 2;
909 state->cursor2 = par->CursorStart >> 24;
910 if (flags & FB_VMODE_DOUBLE)
911 state->cursor1 |= 2;
912 state->pllsel = 0x10000700;
913 state->config = NV_RD32(par->PFB, 0x00000200);
914 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
915 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
916 break;
917 }
918
919 if (bpp != 8) /* DirectColor */
920 state->general |= 0x00000030;
921
922 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
923 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
924}
925
926void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
927{
928 int i;
929
930 NV_WR32(par->PMC, 0x0140, 0x00000000);
931 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
932 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
933
934 NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
935 NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
936 NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
937 NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
938
939 if (par->Architecture == NV_ARCH_04) {
940 NV_WR32(par->PFB, 0x0200, state->config);
941 } else if ((par->Chipset & 0xfff0) == 0x0090) {
942 for (i = 0; i < 15; i++) {
943 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
944 NV_WR32(par->PFB, 0x0604 + (i * 0x10), par->FbMapSize - 1);
945 }
946 } else {
947 for (i = 0; i < 8; i++) {
948 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
949 NV_WR32(par->PFB, 0x0244 + (i * 0x10), par->FbMapSize - 1);
950 }
951 }
952
953 if (par->Architecture >= NV_ARCH_40) {
954 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
955 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
956 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
957 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
958 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
959 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
960 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
961 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
962 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
963 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
964 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
965 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
966 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
967 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
968 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
969 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
970 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
971 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
972 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
973 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
974 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
975 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
976 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
977 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
978 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
979 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
980 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
981 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
982 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
983 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
984 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
985 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
986 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
987 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
988 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
989 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
990 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
991 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
992 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
993 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
994 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
995 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
996 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
997 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
998 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
999 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1000 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1001 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1002 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1003 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1004 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1005 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1006 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1007 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1008 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1009 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1010 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1011 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1012 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1013 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1014 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1015 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1016 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1017 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1018 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1019 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1020 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1021 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1022 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1023 NV_WR32(par->PRAMIN, 0x084E * 4,
1024 par->FbUsableSize | 0x00000002);
1025
1026#ifdef __BIG_ENDIAN
1027 NV_WR32(par->PRAMIN, 0x080A * 4,
1028 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1029 NV_WR32(par->PRAMIN, 0x0812 * 4,
1030 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1031 NV_WR32(par->PRAMIN, 0x081A * 4,
1032 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1033 NV_WR32(par->PRAMIN, 0x0822 * 4,
1034 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1035 NV_WR32(par->PRAMIN, 0x082A * 4,
1036 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1037 NV_WR32(par->PRAMIN, 0x0832 * 4,
1038 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1039 NV_WR32(par->PRAMIN, 0x083A * 4,
1040 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1041 NV_WR32(par->PRAMIN, 0x0842 * 4,
1042 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1043 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1044 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1045#endif
1046 } else {
1047 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1048 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1049 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1050 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1051 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1052 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1053 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1054 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1055 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1056 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1057 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1058 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1059 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1060 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1061 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1062 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1063 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1064 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1065 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1066 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1067 if (par->Architecture >= NV_ARCH_10)
1068 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1069 else
1070 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1071 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1072 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1073 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1074 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1075 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1076 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1077 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1078 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1079 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1080 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1081 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1082 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1083 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1084 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1085 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1086 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1087 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1088 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1089 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1090 if (par->WaitVSyncPossible)
1091 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1092 else
1093 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1094 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1095 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1096 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1097 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1098 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1099 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1100 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1101 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1102 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1103 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1104 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1105 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1106 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1107 NV_WR32(par->PRAMIN, 0x0826 * 4,
1108 par->FbUsableSize | 0x00000002);
1109 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1110#ifdef __BIG_ENDIAN
1111 NV_WR32(par->PRAMIN, 0x0804 * 4,
1112 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1113 NV_WR32(par->PRAMIN, 0x0808 * 4,
1114 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1115 NV_WR32(par->PRAMIN, 0x080C * 4,
1116 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1117 NV_WR32(par->PRAMIN, 0x0810 * 4,
1118 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1119 NV_WR32(par->PRAMIN, 0x0814 * 4,
1120 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1121 NV_WR32(par->PRAMIN, 0x0818 * 4,
1122 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1123 NV_WR32(par->PRAMIN, 0x081C * 4,
1124 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1125 NV_WR32(par->PRAMIN, 0x0820 * 4,
1126 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1127 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1128 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1129#endif
1130 }
1131 if (par->Architecture < NV_ARCH_10) {
1132 if ((par->Chipset & 0x0fff) == 0x0020) {
1133 NV_WR32(par->PRAMIN, 0x0824 * 4,
1134 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1135 NV_WR32(par->PRAMIN, 0x0826 * 4,
1136 NV_RD32(par->PRAMIN,
1137 0x0826 * 4) + par->FbAddress);
1138 }
1139 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1140 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1141 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1142 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1143 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1144 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1145 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1146 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1147 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1148 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1149 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1150 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1151 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1152 } else {
1153 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1154 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1155
1156 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1157 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1158 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1159 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1160 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1161 NV_WR32(par->PGRAPH, 0x0710,
1162 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1163 NV_WR32(par->PGRAPH, 0x0710,
1164 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1165
1166 if (par->Architecture == NV_ARCH_10) {
1167 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1168 NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1169 NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1170
1171 for (i = 0; i < 32; i++)
1172 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1173 NV_RD32(&par->PFB[(0x0240 / 4) + i],
1174 0));
1175
1176 NV_WR32(par->PGRAPH, 0x640, 0);
1177 NV_WR32(par->PGRAPH, 0x644, 0);
1178 NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1179 NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1180
1181 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1182 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1183 } else {
1184 if (par->Architecture >= NV_ARCH_40) {
1185 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1186 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1187 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1188 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1189
1190 if ((par->Chipset & 0xfff0) == 0x0040) {
1191 NV_WR32(par->PGRAPH, 0x09b0,
1192 0x83280fff);
1193 NV_WR32(par->PGRAPH, 0x09b4,
1194 0x000000a0);
1195 } else {
1196 NV_WR32(par->PGRAPH, 0x0820,
1197 0x83280eff);
1198 NV_WR32(par->PGRAPH, 0x0824,
1199 0x000000a0);
1200 }
1201
1202 switch (par->Chipset & 0xfff0) {
1203 case 0x0040:
1204 case 0x0210:
1205 NV_WR32(par->PGRAPH, 0x09b8,
1206 0x0078e366);
1207 NV_WR32(par->PGRAPH, 0x09bc,
1208 0x0000014c);
1209 NV_WR32(par->PFB, 0x033C,
1210 NV_RD32(par->PFB, 0x33C) &
1211 0xffff7fff);
1212 break;
1213 case 0x00C0:
1214 NV_WR32(par->PGRAPH, 0x0828,
1215 0x007596ff);
1216 NV_WR32(par->PGRAPH, 0x082C,
1217 0x00000108);
1218 break;
1219 case 0x0160:
1220 case 0x01D0:
1221 NV_WR32(par->PMC, 0x1700,
1222 NV_RD32(par->PFB, 0x020C));
1223 NV_WR32(par->PMC, 0x1704, 0);
1224 NV_WR32(par->PMC, 0x1708, 0);
1225 NV_WR32(par->PMC, 0x170C,
1226 NV_RD32(par->PFB, 0x020C));
1227 NV_WR32(par->PGRAPH, 0x0860, 0);
1228 NV_WR32(par->PGRAPH, 0x0864, 0);
1229 NV_WR32(par->PRAMDAC, 0x0608,
1230 NV_RD32(par->PRAMDAC,
1231 0x0608) | 0x00100000);
1232 break;
1233 case 0x0140:
1234 NV_WR32(par->PGRAPH, 0x0828,
1235 0x0072cb77);
1236 NV_WR32(par->PGRAPH, 0x082C,
1237 0x00000108);
1238 break;
1239 case 0x0220:
1240 case 0x0230:
1241 NV_WR32(par->PGRAPH, 0x0860, 0);
1242 NV_WR32(par->PGRAPH, 0x0864, 0);
1243 NV_WR32(par->PRAMDAC, 0x0608,
1244 NV_RD32(par->PRAMDAC, 0x0608) |
1245 0x00100000);
1246 break;
1247 case 0x0090:
1248 NV_WR32(par->PRAMDAC, 0x0608,
1249 NV_RD32(par->PRAMDAC, 0x0608) |
1250 0x00100000);
1251 NV_WR32(par->PGRAPH, 0x0828,
1252 0x07830610);
1253 NV_WR32(par->PGRAPH, 0x082C,
1254 0x0000016A);
1255 break;
1256 default:
1257 break;
1258 };
1259
1260 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1261 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1262 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1263 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1264 } else if (par->Architecture == NV_ARCH_30) {
1265 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1266 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1267 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1268 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1269 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1270 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1271 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1272 } else {
1273 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1274 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1275 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1276 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1277
1278 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1279 NV_WR32(par->PGRAPH, 0x0890,
1280 0x00080000);
1281 NV_WR32(par->PGRAPH, 0x0610,
1282 0x304B1FB6);
1283 NV_WR32(par->PGRAPH, 0x0B80,
1284 0x18B82880);
1285 NV_WR32(par->PGRAPH, 0x0B84,
1286 0x44000000);
1287 NV_WR32(par->PGRAPH, 0x0098,
1288 0x40000080);
1289 NV_WR32(par->PGRAPH, 0x0B88,
1290 0x000000ff);
1291 } else {
1292 NV_WR32(par->PGRAPH, 0x0880,
1293 0x00080000);
1294 NV_WR32(par->PGRAPH, 0x0094,
1295 0x00000005);
1296 NV_WR32(par->PGRAPH, 0x0B80,
1297 0x45CAA208);
1298 NV_WR32(par->PGRAPH, 0x0B84,
1299 0x24000000);
1300 NV_WR32(par->PGRAPH, 0x0098,
1301 0x00000040);
1302 NV_WR32(par->PGRAPH, 0x0750,
1303 0x00E00038);
1304 NV_WR32(par->PGRAPH, 0x0754,
1305 0x00000030);
1306 NV_WR32(par->PGRAPH, 0x0750,
1307 0x00E10038);
1308 NV_WR32(par->PGRAPH, 0x0754,
1309 0x00000030);
1310 }
1311 }
1312
1313 if ((par->Chipset & 0xfff0) == 0x0090) {
1314 for (i = 0; i < 60; i++)
1315 NV_WR32(par->PGRAPH, 0x0D00 + i,
1316 NV_RD32(par->PFB, 0x0600 + i));
1317 } else {
1318 for (i = 0; i < 32; i++)
1319 NV_WR32(par->PGRAPH, 0x0900 + i,
1320 NV_RD32(par->PFB, 0x0240 + i));
1321 }
1322
1323 if (par->Architecture >= NV_ARCH_40) {
1324 if ((par->Chipset & 0xfff0) == 0x0040) {
1325 NV_WR32(par->PGRAPH, 0x09A4,
1326 NV_RD32(par->PFB, 0x0200));
1327 NV_WR32(par->PGRAPH, 0x09A8,
1328 NV_RD32(par->PFB, 0x0204));
1329 NV_WR32(par->PGRAPH, 0x69A4,
1330 NV_RD32(par->PFB, 0x0200));
1331 NV_WR32(par->PGRAPH, 0x69A8,
1332 NV_RD32(par->PFB, 0x0204));
1333
1334 NV_WR32(par->PGRAPH, 0x0820, 0);
1335 NV_WR32(par->PGRAPH, 0x0824, 0);
1336 NV_WR32(par->PGRAPH, 0x0864,
1337 par->FbMapSize - 1);
1338 NV_WR32(par->PGRAPH, 0x0868,
1339 par->FbMapSize - 1);
1340 } else {
1341 if((par->Chipset & 0xfff0) == 0x0090) {
1342 NV_WR32(par->PGRAPH, 0x0DF0,
1343 NV_RD32(par->PFB, 0x0200));
1344 NV_WR32(par->PGRAPH, 0x0DF4,
1345 NV_RD32(par->PFB, 0x0204));
1346 } else {
1347 NV_WR32(par->PGRAPH, 0x09F0,
1348 NV_RD32(par->PFB, 0x0200));
1349 NV_WR32(par->PGRAPH, 0x09F4,
1350 NV_RD32(par->PFB, 0x0204));
1351 }
1352 NV_WR32(par->PGRAPH, 0x69F0,
1353 NV_RD32(par->PFB, 0x0200));
1354 NV_WR32(par->PGRAPH, 0x69F4,
1355 NV_RD32(par->PFB, 0x0204));
1356
1357 NV_WR32(par->PGRAPH, 0x0840, 0);
1358 NV_WR32(par->PGRAPH, 0x0844, 0);
1359 NV_WR32(par->PGRAPH, 0x08a0,
1360 par->FbMapSize - 1);
1361 NV_WR32(par->PGRAPH, 0x08a4,
1362 par->FbMapSize - 1);
1363 }
1364 } else {
1365 NV_WR32(par->PGRAPH, 0x09A4,
1366 NV_RD32(par->PFB, 0x0200));
1367 NV_WR32(par->PGRAPH, 0x09A8,
1368 NV_RD32(par->PFB, 0x0204));
1369 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1370 NV_WR32(par->PGRAPH, 0x0754,
1371 NV_RD32(par->PFB, 0x0200));
1372 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1373 NV_WR32(par->PGRAPH, 0x0754,
1374 NV_RD32(par->PFB, 0x0204));
1375
1376 NV_WR32(par->PGRAPH, 0x0820, 0);
1377 NV_WR32(par->PGRAPH, 0x0824, 0);
1378 NV_WR32(par->PGRAPH, 0x0864,
1379 par->FbMapSize - 1);
1380 NV_WR32(par->PGRAPH, 0x0868,
1381 par->FbMapSize - 1);
1382 }
1383 NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1384 NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1385 }
1386 }
1387 NV_WR32(par->PGRAPH, 0x053C, 0);
1388 NV_WR32(par->PGRAPH, 0x0540, 0);
1389 NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1390 NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1391
1392 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1393 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1394 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1395 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1396 if (par->Architecture >= NV_ARCH_40)
1397 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1398 else
1399 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1400 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1401 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1402 if (par->Architecture >= NV_ARCH_40)
1403 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1404 else
1405 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1406 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1407 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1408 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1409 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1410 NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1411 NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1412 NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1413 NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1414 NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1415 NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1416 NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1417 NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1418#ifdef __BIG_ENDIAN
1419 NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1420#else
1421 NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1422#endif
1423 NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1424 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1425 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1426 NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1427 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1428 if (par->Architecture >= NV_ARCH_10) {
1429 if (par->twoHeads) {
1430 NV_WR32(par->PCRTC0, 0x0860, state->head);
1431 NV_WR32(par->PCRTC0, 0x2860, state->head2);
1432 }
1433 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1434 (1 << 25));
1435
1436 NV_WR32(par->PMC, 0x8704, 1);
1437 NV_WR32(par->PMC, 0x8140, 0);
1438 NV_WR32(par->PMC, 0x8920, 0);
1439 NV_WR32(par->PMC, 0x8924, 0);
1440 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1441 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1442 NV_WR32(par->PMC, 0x1588, 0);
1443
1444 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1445 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1446 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1447
1448 if (par->FlatPanel) {
1449 if ((par->Chipset & 0x0ff0) == 0x0110) {
1450 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1451 } else if (par->twoHeads) {
1452 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1453 }
1454
1455 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1456 VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1457 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1458 VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1459 VGA_WR08(par->PCIO, 0x03D4, 0x21);
1460 VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1461 }
1462
1463 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1464 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1465 }
1466
1467 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1468 VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1469 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1470 VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1471 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1472 VGA_WR08(par->PCIO, 0x03D5, state->screen);
1473 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1474 VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1475 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1476 VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1477 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1478 VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1479 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1480 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1481 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1482 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1483
1484 if(par->Architecture >= NV_ARCH_30) {
1485 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1486 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1487 }
1488
1489 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1490 VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1491 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1492 VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1493 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1494 VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1495 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1496 VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1497
1498 if (!par->FlatPanel) {
1499 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1500 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1501 if (par->twoHeads)
1502 NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1503 if (par->twoStagePLL) {
1504 NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1505 NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1506 }
1507 } else {
1508 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1509 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1510 par->PanelTweak);
1511 }
1512
1513 NV_WR32(par->PRAMDAC, 0x0600, state->general);
1514
1515 NV_WR32(par->PCRTC, 0x0140, 0);
1516 NV_WR32(par->PCRTC, 0x0100, 1);
1517
1518 par->CurrentState = state;
1519}
1520
1521void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1522 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1523 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1524 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1525 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1526 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1527 state->screen = VGA_RD08(par->PCIO, 0x03D5);
1528 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1529 state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1530 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1531 state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1532 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1533 state->fifo = VGA_RD08(par->PCIO, 0x03D5);
1534 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1535 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1536 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1537 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1538
1539 if(par->Architecture >= NV_ARCH_30) {
1540 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1541 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1542 }
1543
1544 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1545 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1546 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1547 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1548 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1549 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1550 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1551 state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1552 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1553 if (par->twoHeads)
1554 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1555 if (par->twoStagePLL) {
1556 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1557 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1558 }
1559 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1560 state->general = NV_RD32(par->PRAMDAC, 0x0600);
1561 state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1562 state->config = NV_RD32(par->PFB, 0x0200);
1563
1564 if (par->Architecture >= NV_ARCH_10) {
1565 if (par->twoHeads) {
1566 state->head = NV_RD32(par->PCRTC0, 0x0860);
1567 state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1568 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1569 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1570 }
1571 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1572 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1573 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1574
1575 if ((par->Chipset & 0x0ff0) == 0x0110) {
1576 state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1577 } else if (par->twoHeads) {
1578 state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1579 }
1580
1581 if (par->FlatPanel) {
1582 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1583 state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1584 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1585 state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1586 }
1587 }
1588}
1589
1590void NVSetStartAddress(struct nvidia_par *par, u32 start)
1591{
1592 NV_WR32(par->PCRTC, 0x800, start);
1593}
diff --git a/drivers/video/nvidia/nv_i2c.c b/drivers/video/nvidia/nv_i2c.c
new file mode 100644
index 000000000000..3757c1407c19
--- /dev/null
+++ b/drivers/video/nvidia/nv_i2c.c
@@ -0,0 +1,215 @@
1/*
2 * linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c
3 *
4 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
5 *
6 * Based on rivafb-i2c.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19#include <linux/fb.h>
20
21#include <asm/io.h>
22
23#include "nv_type.h"
24#include "nv_local.h"
25#include "nv_proto.h"
26
27#include "../edid.h"
28
29static void nvidia_gpio_setscl(void *data, int state)
30{
31 struct nvidia_i2c_chan *chan = data;
32 struct nvidia_par *par = chan->par;
33 u32 val;
34
35 VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
36 val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
37
38 if (state)
39 val |= 0x20;
40 else
41 val &= ~0x20;
42
43 VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
44 VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
45}
46
47static void nvidia_gpio_setsda(void *data, int state)
48{
49 struct nvidia_i2c_chan *chan = (struct nvidia_i2c_chan *)data;
50 struct nvidia_par *par = chan->par;
51 u32 val;
52
53 VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
54 val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
55
56 if (state)
57 val |= 0x10;
58 else
59 val &= ~0x10;
60
61 VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
62 VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
63}
64
65static int nvidia_gpio_getscl(void *data)
66{
67 struct nvidia_i2c_chan *chan = (struct nvidia_i2c_chan *)data;
68 struct nvidia_par *par = chan->par;
69 u32 val = 0;
70
71 VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
72 if (VGA_RD08(par->PCIO, 0x3d5) & 0x04)
73 val = 1;
74
75 val = VGA_RD08(par->PCIO, 0x3d5);
76
77 return val;
78}
79
80static int nvidia_gpio_getsda(void *data)
81{
82 struct nvidia_i2c_chan *chan = (struct nvidia_i2c_chan *)data;
83 struct nvidia_par *par = chan->par;
84 u32 val = 0;
85
86 VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
87 if (VGA_RD08(par->PCIO, 0x3d5) & 0x08)
88 val = 1;
89
90 return val;
91}
92
93#define I2C_ALGO_NVIDIA 0x0e0000
94static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name)
95{
96 int rc;
97
98 strcpy(chan->adapter.name, name);
99 chan->adapter.owner = THIS_MODULE;
100 chan->adapter.id = I2C_ALGO_NVIDIA;
101 chan->adapter.algo_data = &chan->algo;
102 chan->adapter.dev.parent = &chan->par->pci_dev->dev;
103 chan->algo.setsda = nvidia_gpio_setsda;
104 chan->algo.setscl = nvidia_gpio_setscl;
105 chan->algo.getsda = nvidia_gpio_getsda;
106 chan->algo.getscl = nvidia_gpio_getscl;
107 chan->algo.udelay = 40;
108 chan->algo.timeout = msecs_to_jiffies(2);
109 chan->algo.data = chan;
110
111 i2c_set_adapdata(&chan->adapter, chan);
112
113 /* Raise SCL and SDA */
114 nvidia_gpio_setsda(chan, 1);
115 nvidia_gpio_setscl(chan, 1);
116 udelay(20);
117
118 rc = i2c_bit_add_bus(&chan->adapter);
119 if (rc == 0)
120 dev_dbg(&chan->par->pci_dev->dev,
121 "I2C bus %s registered.\n", name);
122 else {
123 dev_warn(&chan->par->pci_dev->dev,
124 "Failed to register I2C bus %s.\n", name);
125 chan->par = NULL;
126 }
127
128 return rc;
129}
130
131void nvidia_create_i2c_busses(struct nvidia_par *par)
132{
133 par->bus = 3;
134
135 par->chan[0].par = par;
136 par->chan[1].par = par;
137 par->chan[2].par = par;
138
139 par->chan[0].ddc_base = 0x3e;
140 nvidia_setup_i2c_bus(&par->chan[0], "BUS1");
141
142 par->chan[1].ddc_base = 0x36;
143 nvidia_setup_i2c_bus(&par->chan[1], "BUS2");
144
145 par->chan[2].ddc_base = 0x50;
146 nvidia_setup_i2c_bus(&par->chan[2], "BUS3");
147}
148
149void nvidia_delete_i2c_busses(struct nvidia_par *par)
150{
151 if (par->chan[0].par)
152 i2c_bit_del_bus(&par->chan[0].adapter);
153 par->chan[0].par = NULL;
154
155 if (par->chan[1].par)
156 i2c_bit_del_bus(&par->chan[1].adapter);
157 par->chan[1].par = NULL;
158
159 if (par->chan[2].par)
160 i2c_bit_del_bus(&par->chan[2].adapter);
161 par->chan[2].par = NULL;
162
163}
164
165static u8 *nvidia_do_probe_i2c_edid(struct nvidia_i2c_chan *chan)
166{
167 u8 start = 0x0;
168 struct i2c_msg msgs[] = {
169 {
170 .addr = 0x50,
171 .len = 1,
172 .buf = &start,
173 }, {
174 .addr = 0x50,
175 .flags = I2C_M_RD,
176 .len = EDID_LENGTH,
177 },
178 };
179 u8 *buf;
180
181 if (!chan->par)
182 return NULL;
183
184 buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
185 if (!buf) {
186 dev_warn(&chan->par->pci_dev->dev, "Out of memory!\n");
187 return NULL;
188 }
189 msgs[1].buf = buf;
190
191 if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
192 return buf;
193 dev_dbg(&chan->par->pci_dev->dev, "Unable to read EDID block.\n");
194 kfree(buf);
195 return NULL;
196}
197
198int nvidia_probe_i2c_connector(struct nvidia_par *par, int conn, u8 **out_edid)
199{
200 u8 *edid = NULL;
201 int i;
202
203 for (i = 0; i < 3; i++) {
204 /* Do the real work */
205 edid = nvidia_do_probe_i2c_edid(&par->chan[conn - 1]);
206 if (edid)
207 break;
208 }
209 if (out_edid)
210 *out_edid = edid;
211 if (!edid)
212 return 1;
213
214 return 0;
215}
diff --git a/drivers/video/nvidia/nv_local.h b/drivers/video/nvidia/nv_local.h
new file mode 100644
index 000000000000..9da320986f4c
--- /dev/null
+++ b/drivers/video/nvidia/nv_local.h
@@ -0,0 +1,107 @@
1/***************************************************************************\
2|* *|
3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#ifndef __NV_LOCAL_H__
51#define __NV_LOCAL_H__
52
53/*
54 * This file includes any environment or machine specific values to access the
55 * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
56 * can stay generic in nature.
57 */
58
59/*
60 * HW access macros. These assume memory-mapped I/O, and not normal I/O space.
61 */
62#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
63#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
64#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
65#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
66#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
67#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
68
69/* VGA I/O is now always done through MMIO */
70#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
71#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
72
73#define NVDmaNext(par, data) \
74 NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data))
75
76#define NVDmaStart(par, tag, size) { \
77 if((par)->dmaFree <= (size)) \
78 NVDmaWait(par, size); \
79 NVDmaNext(par, ((size) << 18) | (tag)); \
80 (par)->dmaFree -= ((size) + 1); \
81}
82
83#if defined(__i386__)
84#define _NV_FENCE() outb(0, 0x3D0);
85#else
86#define _NV_FENCE() mb();
87#endif
88
89#define WRITE_PUT(par, data) { \
90 _NV_FENCE() \
91 NV_RD08((par)->FbStart, 0); \
92 NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
93 mb(); \
94}
95
96#define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
97
98#define reverse_order(l) \
99do { \
100 u8 *a = (u8 *)(l); \
101 *a = byte_rev[*a], a++; \
102 *a = byte_rev[*a], a++; \
103 *a = byte_rev[*a], a++; \
104 *a = byte_rev[*a]; \
105} while(0)
106
107#endif /* __NV_LOCAL_H__ */
diff --git a/drivers/video/nvidia/nv_of.c b/drivers/video/nvidia/nv_of.c
new file mode 100644
index 000000000000..7d12eb85310d
--- /dev/null
+++ b/drivers/video/nvidia/nv_of.c
@@ -0,0 +1,59 @@
1/*
2 * linux/drivers/video/nvidia/nv_of.c
3 *
4 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
5 *
6 * Based on rivafb-i2c.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19#include <linux/fb.h>
20
21#include <asm/io.h>
22
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25
26#include "nv_type.h"
27#include "nv_local.h"
28#include "nv_proto.h"
29
30void nvidia_create_i2c_busses(struct nvidia_par *par) {}
31void nvidia_delete_i2c_busses(struct nvidia_par *par) {}
32
33int nvidia_probe_i2c_connector(struct nvidia_par *par, int conn, u8 **out_edid)
34{
35 struct device_node *dp;
36 unsigned char *pedid = NULL;
37 unsigned char *disptype = NULL;
38 static char *propnames[] = {
39 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
40 int i;
41
42 dp = pci_device_to_OF_node(par->pci_dev);
43 for (; dp != NULL; dp = dp->child) {
44 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
45 if (disptype == NULL)
46 continue;
47 if (strncmp(disptype, "LCD", 3) != 0)
48 continue;
49 for (i = 0; propnames[i] != NULL; ++i) {
50 pedid = (unsigned char *)
51 get_property(dp, propnames[i], NULL);
52 if (pedid != NULL) {
53 *out_edid = pedid;
54 return 0;
55 }
56 }
57 }
58 return 1;
59}
diff --git a/drivers/video/nvidia/nv_proto.h b/drivers/video/nvidia/nv_proto.h
new file mode 100644
index 000000000000..42847ce1b8dd
--- /dev/null
+++ b/drivers/video/nvidia/nv_proto.h
@@ -0,0 +1,58 @@
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h,v 1.10 2003/07/31 20:24:29 mvojkovi Exp $ */
2
3#ifndef __NV_PROTO_H__
4#define __NV_PROTO_H__
5
6/* in nv_setup.c */
7void NVCommonSetup(struct fb_info *info);
8void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value);
9u8 NVReadCrtc(struct nvidia_par *par, u8 index);
10void NVWriteGr(struct nvidia_par *par, u8 index, u8 value);
11u8 NVReadGr(struct nvidia_par *par, u8 index);
12void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value);
13u8 NVReadSeq(struct nvidia_par *par, u8 index);
14void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value);
15u8 NVReadAttr(struct nvidia_par *par, u8 index);
16void NVWriteMiscOut(struct nvidia_par *par, u8 value);
17u8 NVReadMiscOut(struct nvidia_par *par);
18void NVWriteDacMask(struct nvidia_par *par, u8 value);
19void NVWriteDacReadAddr(struct nvidia_par *par, u8 value);
20void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value);
21void NVWriteDacData(struct nvidia_par *par, u8 value);
22u8 NVReadDacData(struct nvidia_par *par);
23
24/* in nv_hw.c */
25void NVCalcStateExt(struct nvidia_par *par, struct _riva_hw_state *,
26 int, int, int, int, int, int);
27void NVLoadStateExt(struct nvidia_par *par, struct _riva_hw_state *);
28void NVUnloadStateExt(struct nvidia_par *par, struct _riva_hw_state *);
29void NVSetStartAddress(struct nvidia_par *par, u32);
30int NVShowHideCursor(struct nvidia_par *par, int);
31void NVLockUnlock(struct nvidia_par *par, int);
32
33/* in nvidia-i2c.c */
34#if defined(CONFIG_FB_NVIDIA_I2C) || defined (CONFIG_PPC_OF)
35void nvidia_create_i2c_busses(struct nvidia_par *par);
36void nvidia_delete_i2c_busses(struct nvidia_par *par);
37int nvidia_probe_i2c_connector(struct nvidia_par *par, int conn,
38 u8 ** out_edid);
39#else
40#define nvidia_create_i2c_busses(...)
41#define nvidia_delete_i2c_busses(...)
42#define nvidia_probe_i2c_connector(p, c, edid) \
43do { \
44 *(edid) = NULL; \
45} while(0)
46#endif
47
48/* in nv_accel.c */
49extern void NVResetGraphics(struct fb_info *info);
50extern void nvidiafb_copyarea(struct fb_info *info,
51 const struct fb_copyarea *region);
52extern void nvidiafb_fillrect(struct fb_info *info,
53 const struct fb_fillrect *rect);
54extern void nvidiafb_imageblit(struct fb_info *info,
55 const struct fb_image *image);
56extern int nvidiafb_sync(struct fb_info *info);
57extern u8 byte_rev[256];
58#endif /* __NV_PROTO_H__ */
diff --git a/drivers/video/nvidia/nv_setup.c b/drivers/video/nvidia/nv_setup.c
new file mode 100644
index 000000000000..0bbdca2e0f91
--- /dev/null
+++ b/drivers/video/nvidia/nv_setup.c
@@ -0,0 +1,636 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#include <video/vga.h>
51#include <linux/delay.h>
52#include <linux/pci.h>
53#include "nv_type.h"
54#include "nv_local.h"
55#include "nv_proto.h"
56/*
57 * Override VGA I/O routines.
58 */
59void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
60{
61 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
62 VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
63}
64u8 NVReadCrtc(struct nvidia_par *par, u8 index)
65{
66 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
67 return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
68}
69void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
70{
71 VGA_WR08(par->PVIO, VGA_GFX_I, index);
72 VGA_WR08(par->PVIO, VGA_GFX_D, value);
73}
74u8 NVReadGr(struct nvidia_par *par, u8 index)
75{
76 VGA_WR08(par->PVIO, VGA_GFX_I, index);
77 return (VGA_RD08(par->PVIO, VGA_GFX_D));
78}
79void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
80{
81 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
82 VGA_WR08(par->PVIO, VGA_SEQ_D, value);
83}
84u8 NVReadSeq(struct nvidia_par *par, u8 index)
85{
86 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
87 return (VGA_RD08(par->PVIO, VGA_SEQ_D));
88}
89void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
90{
91 volatile u8 tmp;
92
93 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
94 if (par->paletteEnabled)
95 index &= ~0x20;
96 else
97 index |= 0x20;
98 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
99 VGA_WR08(par->PCIO, VGA_ATT_W, value);
100}
101u8 NVReadAttr(struct nvidia_par *par, u8 index)
102{
103 volatile u8 tmp;
104
105 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
106 if (par->paletteEnabled)
107 index &= ~0x20;
108 else
109 index |= 0x20;
110 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
111 return (VGA_RD08(par->PCIO, VGA_ATT_R));
112}
113void NVWriteMiscOut(struct nvidia_par *par, u8 value)
114{
115 VGA_WR08(par->PVIO, VGA_MIS_W, value);
116}
117u8 NVReadMiscOut(struct nvidia_par *par)
118{
119 return (VGA_RD08(par->PVIO, VGA_MIS_R));
120}
121#if 0
122void NVEnablePalette(struct nvidia_par *par)
123{
124 volatile u8 tmp;
125
126 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
127 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
128 par->paletteEnabled = 1;
129}
130void NVDisablePalette(struct nvidia_par *par)
131{
132 volatile u8 tmp;
133
134 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
135 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
136 par->paletteEnabled = 0;
137}
138#endif /* 0 */
139void NVWriteDacMask(struct nvidia_par *par, u8 value)
140{
141 VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
142}
143#if 0
144u8 NVReadDacMask(struct nvidia_par *par)
145{
146 return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
147}
148#endif /* 0 */
149void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
150{
151 VGA_WR08(par->PDIO, VGA_PEL_IR, value);
152}
153void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
154{
155 VGA_WR08(par->PDIO, VGA_PEL_IW, value);
156}
157void NVWriteDacData(struct nvidia_par *par, u8 value)
158{
159 VGA_WR08(par->PDIO, VGA_PEL_D, value);
160}
161u8 NVReadDacData(struct nvidia_par *par)
162{
163 return (VGA_RD08(par->PDIO, VGA_PEL_D));
164}
165
166static int NVIsConnected(struct nvidia_par *par, int output)
167{
168 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
169 u32 reg52C, reg608;
170 int present;
171
172 if (output)
173 PRAMDAC += 0x800;
174
175 reg52C = NV_RD32(PRAMDAC, 0x052C);
176 reg608 = NV_RD32(PRAMDAC, 0x0608);
177
178 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
179
180 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
181 msleep(1);
182 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
183
184 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
185 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
186 0x00001000);
187
188 msleep(1);
189
190 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
191
192 if (present)
193 printk("nvidiafb: CRTC%i found\n", output);
194 else
195 printk("nvidiafb: CRTC%i not found\n", output);
196
197 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
198 0x0000EFFF);
199
200 NV_WR32(PRAMDAC, 0x052C, reg52C);
201 NV_WR32(PRAMDAC, 0x0608, reg608);
202
203 return present;
204}
205
206static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
207{
208 if (head) {
209 par->PCIO = par->PCIO0 + 0x2000;
210 par->PCRTC = par->PCRTC0 + 0x800;
211 par->PRAMDAC = par->PRAMDAC0 + 0x800;
212 par->PDIO = par->PDIO0 + 0x2000;
213 } else {
214 par->PCIO = par->PCIO0;
215 par->PCRTC = par->PCRTC0;
216 par->PRAMDAC = par->PRAMDAC0;
217 par->PDIO = par->PDIO0;
218 }
219}
220
221static void nv4GetConfig(struct nvidia_par *par)
222{
223 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
224 par->RamAmountKBytes =
225 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
226 1024 * 2;
227 } else {
228 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
229 case 0:
230 par->RamAmountKBytes = 1024 * 32;
231 break;
232 case 1:
233 par->RamAmountKBytes = 1024 * 4;
234 break;
235 case 2:
236 par->RamAmountKBytes = 1024 * 8;
237 break;
238 case 3:
239 default:
240 par->RamAmountKBytes = 1024 * 16;
241 break;
242 }
243 }
244 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
245 14318 : 13500;
246 par->CURSOR = &par->PRAMIN[0x1E00];
247 par->MinVClockFreqKHz = 12000;
248 par->MaxVClockFreqKHz = 350000;
249}
250
251static void nv10GetConfig(struct nvidia_par *par)
252{
253 struct pci_dev *dev;
254 u32 implementation = par->Chipset & 0x0ff0;
255
256#ifdef __BIG_ENDIAN
257 /* turn on big endian register access */
258 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
259 NV_WR32(par->PMC, 0x0004, 0x01000001);
260 mb();
261 }
262#endif
263
264 dev = pci_find_slot(0, 1);
265 if ((par->Chipset && 0xffff) == 0x01a0) {
266 int amt = 0;
267
268 pci_read_config_dword(dev, 0x7c, &amt);
269 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
270 } else if ((par->Chipset & 0xffff) == 0x01f0) {
271 int amt = 0;
272
273 pci_read_config_dword(dev, 0x84, &amt);
274 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
275 } else {
276 par->RamAmountKBytes =
277 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
278 }
279
280 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
281 14318 : 13500;
282
283 if (par->twoHeads && (implementation != 0x0110)) {
284 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
285 par->CrystalFreqKHz = 27000;
286 }
287
288 par->CursorStart = (par->RamAmountKBytes - 96) * 1024;
289 par->CURSOR = NULL; /* can't set this here */
290 par->MinVClockFreqKHz = 12000;
291 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
292}
293
294void NVCommonSetup(struct fb_info *info)
295{
296 struct nvidia_par *par = info->par;
297 struct fb_var_screeninfo var;
298 u16 implementation = par->Chipset & 0x0ff0;
299 u8 *edidA = NULL, *edidB = NULL;
300 struct fb_monspecs monitorA, monitorB;
301 struct fb_monspecs *monA = NULL, *monB = NULL;
302 int mobile = 0;
303 int tvA = 0;
304 int tvB = 0;
305 int FlatPanel = -1; /* really means the CRTC is slaved */
306 int Television = 0;
307
308 par->PRAMIN = par->REGS + (0x00710000 / 4);
309 par->PCRTC0 = par->REGS + (0x00600000 / 4);
310 par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
311 par->PFB = par->REGS + (0x00100000 / 4);
312 par->PFIFO = par->REGS + (0x00002000 / 4);
313 par->PGRAPH = par->REGS + (0x00400000 / 4);
314 par->PEXTDEV = par->REGS + (0x00101000 / 4);
315 par->PTIMER = par->REGS + (0x00009000 / 4);
316 par->PMC = par->REGS + (0x00000000 / 4);
317 par->FIFO = par->REGS + (0x00800000 / 4);
318
319 /* 8 bit registers */
320 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
321 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
322 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
323
324 par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
325 (implementation != 0x0100) &&
326 (implementation != 0x0150) &&
327 (implementation != 0x01A0) && (implementation != 0x0200);
328
329 par->fpScaler = (par->FpScale && par->twoHeads &&
330 (implementation != 0x0110));
331
332 par->twoStagePLL = (implementation == 0x0310) ||
333 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
334
335 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
336 (implementation != 0x0100);
337
338 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
339
340 /* look for known laptop chips */
341 switch (par->Chipset & 0xffff) {
342 case 0x0112:
343 case 0x0174:
344 case 0x0175:
345 case 0x0176:
346 case 0x0177:
347 case 0x0179:
348 case 0x017C:
349 case 0x017D:
350 case 0x0186:
351 case 0x0187:
352 case 0x018D:
353 case 0x0286:
354 case 0x028C:
355 case 0x0316:
356 case 0x0317:
357 case 0x031A:
358 case 0x031B:
359 case 0x031C:
360 case 0x031D:
361 case 0x031E:
362 case 0x031F:
363 case 0x0324:
364 case 0x0325:
365 case 0x0328:
366 case 0x0329:
367 case 0x032C:
368 case 0x032D:
369 case 0x0347:
370 case 0x0348:
371 case 0x0349:
372 case 0x034B:
373 case 0x034C:
374 case 0x0160:
375 case 0x0166:
376 case 0x00C8:
377 case 0x00CC:
378 case 0x0144:
379 case 0x0146:
380 case 0x0147:
381 case 0x0148:
382 mobile = 1;
383 break;
384 default:
385 break;
386 }
387
388 if (par->Architecture == NV_ARCH_04)
389 nv4GetConfig(par);
390 else
391 nv10GetConfig(par);
392
393 NVSelectHeadRegisters(par, 0);
394
395 NVLockUnlock(par, 0);
396
397 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
398
399 par->Television = 0;
400
401 nvidia_create_i2c_busses(par);
402 if (!par->twoHeads) {
403 par->CRTCnumber = 0;
404 nvidia_probe_i2c_connector(par, 1, &edidA);
405 if (edidA && !fb_parse_edid(edidA, &var)) {
406 printk("nvidiafb: EDID found from BUS1\n");
407 monA = &monitorA;
408 fb_edid_to_monspecs(edidA, monA);
409 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
410
411 /* NV4 doesn't support FlatPanels */
412 if ((par->Chipset & 0x0fff) <= 0x0020)
413 FlatPanel = 0;
414 } else {
415 VGA_WR08(par->PCIO, 0x03D4, 0x28);
416 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
417 VGA_WR08(par->PCIO, 0x03D4, 0x33);
418 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
419 Television = 1;
420 FlatPanel = 1;
421 } else {
422 FlatPanel = 0;
423 }
424 printk("nvidiafb: HW is currently programmed for %s\n",
425 FlatPanel ? (Television ? "TV" : "DFP") :
426 "CRT");
427 }
428
429 if (par->FlatPanel == -1) {
430 par->FlatPanel = FlatPanel;
431 par->Television = Television;
432 } else {
433 printk("nvidiafb: Forcing display type to %s as "
434 "specified\n", par->FlatPanel ? "DFP" : "CRT");
435 }
436 } else {
437 u8 outputAfromCRTC, outputBfromCRTC;
438 int CRTCnumber = -1;
439 u8 slaved_on_A, slaved_on_B;
440 int analog_on_A, analog_on_B;
441 u32 oldhead;
442 u8 cr44;
443
444 if (implementation != 0x0110) {
445 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
446 outputAfromCRTC = 1;
447 else
448 outputAfromCRTC = 0;
449 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
450 outputBfromCRTC = 1;
451 else
452 outputBfromCRTC = 0;
453 analog_on_A = NVIsConnected(par, 0);
454 analog_on_B = NVIsConnected(par, 1);
455 } else {
456 outputAfromCRTC = 0;
457 outputBfromCRTC = 1;
458 analog_on_A = 0;
459 analog_on_B = 0;
460 }
461
462 VGA_WR08(par->PCIO, 0x03D4, 0x44);
463 cr44 = VGA_RD08(par->PCIO, 0x03D5);
464
465 VGA_WR08(par->PCIO, 0x03D5, 3);
466 NVSelectHeadRegisters(par, 1);
467 NVLockUnlock(par, 0);
468
469 VGA_WR08(par->PCIO, 0x03D4, 0x28);
470 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
471 if (slaved_on_B) {
472 VGA_WR08(par->PCIO, 0x03D4, 0x33);
473 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
474 }
475
476 VGA_WR08(par->PCIO, 0x03D4, 0x44);
477 VGA_WR08(par->PCIO, 0x03D5, 0);
478 NVSelectHeadRegisters(par, 0);
479 NVLockUnlock(par, 0);
480
481 VGA_WR08(par->PCIO, 0x03D4, 0x28);
482 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
483 if (slaved_on_A) {
484 VGA_WR08(par->PCIO, 0x03D4, 0x33);
485 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
486 }
487
488 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
489 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
490
491 nvidia_probe_i2c_connector(par, 1, &edidA);
492 if (edidA && !fb_parse_edid(edidA, &var)) {
493 printk("nvidiafb: EDID found from BUS1\n");
494 monA = &monitorA;
495 fb_edid_to_monspecs(edidA, monA);
496 }
497
498 nvidia_probe_i2c_connector(par, 2, &edidB);
499 if (edidB && !fb_parse_edid(edidB, &var)) {
500 printk("nvidiafb: EDID found from BUS2\n");
501 monB = &monitorB;
502 fb_edid_to_monspecs(edidB, monB);
503 }
504
505 if (slaved_on_A && !tvA) {
506 CRTCnumber = 0;
507 FlatPanel = 1;
508 printk("nvidiafb: CRTC 0 is currently programmed for "
509 "DFP\n");
510 } else if (slaved_on_B && !tvB) {
511 CRTCnumber = 1;
512 FlatPanel = 1;
513 printk("nvidiafb: CRTC 1 is currently programmed "
514 "for DFP\n");
515 } else if (analog_on_A) {
516 CRTCnumber = outputAfromCRTC;
517 FlatPanel = 0;
518 printk("nvidiafb: CRTC %i appears to have a "
519 "CRT attached\n", CRTCnumber);
520 } else if (analog_on_B) {
521 CRTCnumber = outputBfromCRTC;
522 FlatPanel = 0;
523 printk("nvidiafb: CRTC %i"
524 "appears to have a "
525 "CRT attached\n", CRTCnumber);
526 } else if (slaved_on_A) {
527 CRTCnumber = 0;
528 FlatPanel = 1;
529 Television = 1;
530 printk("nvidiafb: CRTC 0 is currently programmed "
531 "for TV\n");
532 } else if (slaved_on_B) {
533 CRTCnumber = 1;
534 FlatPanel = 1;
535 Television = 1;
536 printk("nvidiafb: CRTC 1 is currently programmed for "
537 "TV\n");
538 } else if (monA) {
539 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
540 } else if (monB) {
541 FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
542 }
543
544 if (par->FlatPanel == -1) {
545 if (FlatPanel != -1) {
546 par->FlatPanel = FlatPanel;
547 par->Television = Television;
548 } else {
549 printk("nvidiafb: Unable to detect display "
550 "type...\n");
551 if (mobile) {
552 printk("...On a laptop, assuming "
553 "DFP\n");
554 par->FlatPanel = 1;
555 } else {
556 printk("...Using default of CRT\n");
557 par->FlatPanel = 0;
558 }
559 }
560 } else {
561 printk("nvidiafb: Forcing display type to %s as "
562 "specified\n", par->FlatPanel ? "DFP" : "CRT");
563 }
564
565 if (par->CRTCnumber == -1) {
566 if (CRTCnumber != -1)
567 par->CRTCnumber = CRTCnumber;
568 else {
569 printk("nvidiafb: Unable to detect which "
570 "CRTCNumber...\n");
571 if (par->FlatPanel)
572 par->CRTCnumber = 1;
573 else
574 par->CRTCnumber = 0;
575 printk("...Defaulting to CRTCNumber %i\n",
576 par->CRTCnumber);
577 }
578 } else {
579 printk("nvidiafb: Forcing CRTCNumber %i as "
580 "specified\n", par->CRTCnumber);
581 }
582
583 if (monA) {
584 if (((monA->input & FB_DISP_DDI) &&
585 par->FlatPanel) ||
586 ((!(monA->input & FB_DISP_DDI)) &&
587 !par->FlatPanel)) {
588 if (monB) {
589 fb_destroy_modedb(monB->modedb);
590 monB = NULL;
591 }
592 } else {
593 fb_destroy_modedb(monA->modedb);
594 monA = NULL;
595 }
596 }
597
598 if (monB) {
599 if (((monB->input & FB_DISP_DDI) &&
600 !par->FlatPanel) ||
601 ((!(monB->input & FB_DISP_DDI)) &&
602 par->FlatPanel)) {
603 fb_destroy_modedb(monB->modedb);
604 monB = NULL;
605 } else
606 monA = monB;
607 }
608
609 if (implementation == 0x0110)
610 cr44 = par->CRTCnumber * 0x3;
611
612 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
613
614 VGA_WR08(par->PCIO, 0x03D4, 0x44);
615 VGA_WR08(par->PCIO, 0x03D5, cr44);
616 NVSelectHeadRegisters(par, par->CRTCnumber);
617 }
618
619 printk("nvidiafb: Using %s on CRTC %i\n",
620 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
621 par->CRTCnumber);
622
623 if (par->FlatPanel && !par->Television) {
624 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
625 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
626 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
627
628 printk("Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
629 }
630
631 if (monA)
632 info->monspecs = *monA;
633
634 kfree(edidA);
635 kfree(edidB);
636}
diff --git a/drivers/video/nvidia/nv_type.h b/drivers/video/nvidia/nv_type.h
new file mode 100644
index 000000000000..e4a5b1da71c4
--- /dev/null
+++ b/drivers/video/nvidia/nv_type.h
@@ -0,0 +1,174 @@
1#ifndef __NV_TYPE_H__
2#define __NV_TYPE_H__
3
4#include <linux/fb.h>
5#include <linux/types.h>
6#include <linux/i2c.h>
7#include <linux/i2c-id.h>
8#include <linux/i2c-algo-bit.h>
9
10#define NV_ARCH_04 0x04
11#define NV_ARCH_10 0x10
12#define NV_ARCH_20 0x20
13#define NV_ARCH_30 0x30
14#define NV_ARCH_40 0x40
15
16#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
17#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
18#define SetBF(mask,value) ((value) << (0?mask))
19#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
20#define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
21#define SetBit(n) (1<<(n))
22#define Set8Bits(value) ((value)&0xff)
23
24#define V_DBLSCAN 1
25
26typedef struct {
27 int bitsPerPixel;
28 int depth;
29 int displayWidth;
30 int weight;
31} NVFBLayout;
32
33#define NUM_SEQ_REGS 0x05
34#define NUM_CRT_REGS 0x41
35#define NUM_GRC_REGS 0x09
36#define NUM_ATC_REGS 0x15
37
38struct nvidia_par;
39
40struct nvidia_i2c_chan {
41 struct nvidia_par *par;
42 unsigned long ddc_base;
43 struct i2c_adapter adapter;
44 struct i2c_algo_bit_data algo;
45};
46
47typedef struct _riva_hw_state {
48 u8 attr[NUM_ATC_REGS];
49 u8 crtc[NUM_CRT_REGS];
50 u8 gra[NUM_GRC_REGS];
51 u8 seq[NUM_SEQ_REGS];
52 u8 misc_output;
53 u32 bpp;
54 u32 width;
55 u32 height;
56 u32 interlace;
57 u32 repaint0;
58 u32 repaint1;
59 u32 screen;
60 u32 scale;
61 u32 dither;
62 u32 extra;
63 u32 fifo;
64 u32 pixel;
65 u32 horiz;
66 u32 arbitration0;
67 u32 arbitration1;
68 u32 pll;
69 u32 pllB;
70 u32 vpll;
71 u32 vpll2;
72 u32 vpllB;
73 u32 vpll2B;
74 u32 pllsel;
75 u32 general;
76 u32 crtcOwner;
77 u32 head;
78 u32 head2;
79 u32 config;
80 u32 cursorConfig;
81 u32 cursor0;
82 u32 cursor1;
83 u32 cursor2;
84 u32 timingH;
85 u32 timingV;
86 u32 displayV;
87 u32 crtcSync;
88} RIVA_HW_STATE;
89
90struct riva_regs {
91 RIVA_HW_STATE ext;
92};
93
94struct nvidia_par {
95 RIVA_HW_STATE SavedReg;
96 RIVA_HW_STATE ModeReg;
97 RIVA_HW_STATE *CurrentState;
98 u32 pseudo_palette[16];
99 struct pci_dev *pci_dev;
100 u32 Architecture;
101 u32 CursorStart;
102 int Chipset;
103 int bus;
104 unsigned long FbAddress;
105 u8 __iomem *FbStart;
106 u32 FbMapSize;
107 u32 FbUsableSize;
108 u32 ScratchBufferSize;
109 u32 ScratchBufferStart;
110 int FpScale;
111 u32 MinVClockFreqKHz;
112 u32 MaxVClockFreqKHz;
113 u32 CrystalFreqKHz;
114 u32 RamAmountKBytes;
115 u32 IOBase;
116 NVFBLayout CurrentLayout;
117 int cursor_reset;
118 int lockup;
119 int videoKey;
120 int FlatPanel;
121 int FPDither;
122 int Television;
123 int CRTCnumber;
124 int alphaCursor;
125 int twoHeads;
126 int twoStagePLL;
127 int fpScaler;
128 int fpWidth;
129 int fpHeight;
130 int PanelTweak;
131 int paneltweak;
132 u32 crtcSync_read;
133 u32 fpSyncs;
134 u32 dmaPut;
135 u32 dmaCurrent;
136 u32 dmaFree;
137 u32 dmaMax;
138 u32 __iomem *dmaBase;
139 u32 currentRop;
140 int WaitVSyncPossible;
141 int BlendingPossible;
142 u32 paletteEnabled;
143 u32 forceCRTC;
144 u8 DDCBase;
145#ifdef CONFIG_MTRR
146 struct {
147 int vram;
148 int vram_valid;
149 } mtrr;
150#endif
151 struct nvidia_i2c_chan chan[3];
152
153 volatile u32 __iomem *REGS;
154 volatile u32 __iomem *PCRTC0;
155 volatile u32 __iomem *PCRTC;
156 volatile u32 __iomem *PRAMDAC0;
157 volatile u32 __iomem *PFB;
158 volatile u32 __iomem *PFIFO;
159 volatile u32 __iomem *PGRAPH;
160 volatile u32 __iomem *PEXTDEV;
161 volatile u32 __iomem *PTIMER;
162 volatile u32 __iomem *PMC;
163 volatile u32 __iomem *PRAMIN;
164 volatile u32 __iomem *FIFO;
165 volatile u32 __iomem *CURSOR;
166 volatile u8 __iomem *PCIO0;
167 volatile u8 __iomem *PCIO;
168 volatile u8 __iomem *PVIO;
169 volatile u8 __iomem *PDIO0;
170 volatile u8 __iomem *PDIO;
171 volatile u32 __iomem *PRAMDAC;
172};
173
174#endif /* __NV_TYPE_H__ */
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c
new file mode 100644
index 000000000000..3a6555a8aaa2
--- /dev/null
+++ b/drivers/video/nvidia/nvidia.c
@@ -0,0 +1,1729 @@
1/*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12#include <linux/config.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/mm.h>
18#include <linux/tty.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/fb.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#ifdef CONFIG_MTRR
25#include <asm/mtrr.h>
26#endif
27#ifdef CONFIG_PPC_OF
28#include <asm/prom.h>
29#include <asm/pci-bridge.h>
30#endif
31#ifdef CONFIG_PMAC_BACKLIGHT
32#include <asm/backlight.h>
33#endif
34
35#include "nv_local.h"
36#include "nv_type.h"
37#include "nv_proto.h"
38#include "nv_dma.h"
39
40#ifndef CONFIG_PCI /* sanity check */
41#error This driver requires PCI support.
42#endif
43
44#undef CONFIG_FB_NVIDIA_DEBUG
45#ifdef CONFIG_FB_NVIDIA_DEBUG
46#define NVTRACE printk
47#else
48#define NVTRACE if (0) printk
49#endif
50
51#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
53
54#ifdef CONFIG_FB_NVIDIA_DEBUG
55#define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
59 BUG(); \
60 }
61#else
62#define assert(expr)
63#endif
64
65#define PFX "nvidiafb: "
66
67/* HW cursor parameters */
68#define MAX_CURS 32
69
70static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, 0x0252,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, 0x0313,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, 0x0316,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, 0x0317,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, 0x031D,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, 0x031E,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x031F,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0329,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x032F,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0345,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x0349,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x034B,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x034F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, 0x0142,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, 0x0143,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, 0x0144,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, 0x0145,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x0146,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, 0x0147,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0148,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0149,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x014b,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x14c,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x014d,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0160,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0162,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x0163,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x0165,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0169,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, 0x016b,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x016c,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, 0x016d,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, 0x016e,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, 0x0210,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, 0x021d,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, 0x021e,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, 0x0220,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, 0x0221,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, 0x0222,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, 0x0228,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {0,} /* terminate list */
400};
401
402MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
403
404/* command line data, set in nvidiafb_setup() */
405static int flatpanel __devinitdata = -1; /* Autodetect later */
406static int forceCRTC __devinitdata = -1;
407static int hwcur __devinitdata = 0;
408static int noaccel __devinitdata = 0;
409static int noscale __devinitdata = 0;
410static int paneltweak __devinitdata = 0;
411#ifdef CONFIG_MTRR
412static int nomtrr __devinitdata = 0;
413#endif
414
415static char *mode_option __devinitdata = NULL;
416
417static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
418 .type = FB_TYPE_PACKED_PIXELS,
419 .xpanstep = 8,
420 .ypanstep = 1,
421};
422
423static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
424 .xres = 640,
425 .yres = 480,
426 .xres_virtual = 640,
427 .yres_virtual = 480,
428 .bits_per_pixel = 8,
429 .red = {0, 8, 0},
430 .green = {0, 8, 0},
431 .blue = {0, 8, 0},
432 .transp = {0, 0, 0},
433 .activate = FB_ACTIVATE_NOW,
434 .height = -1,
435 .width = -1,
436 .pixclock = 39721,
437 .left_margin = 40,
438 .right_margin = 24,
439 .upper_margin = 32,
440 .lower_margin = 11,
441 .hsync_len = 96,
442 .vsync_len = 2,
443 .vmode = FB_VMODE_NONINTERLACED
444};
445
446/*
447 * Backlight control
448 */
449#ifdef CONFIG_PMAC_BACKLIGHT
450
451static int nvidia_backlight_levels[] = {
452 0x158,
453 0x192,
454 0x1c6,
455 0x200,
456 0x234,
457 0x268,
458 0x2a2,
459 0x2d6,
460 0x310,
461 0x344,
462 0x378,
463 0x3b2,
464 0x3e6,
465 0x41a,
466 0x454,
467 0x534,
468};
469
470/* ------------------------------------------------------------------------- *
471 *
472 * Backlight operations
473 *
474 * ------------------------------------------------------------------------- */
475
476static int nvidia_set_backlight_enable(int on, int level, void *data)
477{
478 struct nvidia_par *par = (struct nvidia_par *)data;
479 u32 tmp_pcrt, tmp_pmc, fpcontrol;
480
481 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
482 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
483 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
484
485 if (on && (level > BACKLIGHT_OFF)) {
486 tmp_pcrt |= 0x1;
487 tmp_pmc |= (1 << 31); // backlight bit
488 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
489 }
490
491 if (on)
492 fpcontrol |= par->fpSyncs;
493 else
494 fpcontrol |= 0x20000022;
495
496 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
497 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
498 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
499
500 return 0;
501}
502
503static int nvidia_set_backlight_level(int level, void *data)
504{
505 return nvidia_set_backlight_enable(1, level, data);
506}
507
508static struct backlight_controller nvidia_backlight_controller = {
509 nvidia_set_backlight_enable,
510 nvidia_set_backlight_level
511};
512
513#endif /* CONFIG_PMAC_BACKLIGHT */
514
515static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
516 u16 bg, u16 fg, u32 w, u32 h)
517{
518 int i, j, k = 0;
519 u32 b, tmp;
520 u32 *data = (u32 *) data8;
521
522 w = (w + 1) & ~1;
523
524 for (i = 0; i < h; i++) {
525 b = *data++;
526 reverse_order(&b);
527
528 for (j = 0; j < w / 2; j++) {
529 tmp = 0;
530#if defined (__BIG_ENDIAN)
531 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
532 b <<= 1;
533 tmp |= (b & (1 << 31)) ? fg : bg;
534 b <<= 1;
535#else
536 tmp = (b & 1) ? fg : bg;
537 b >>= 1;
538 tmp |= (b & 1) ? fg << 16 : bg << 16;
539 b >>= 1;
540#endif
541 NV_WR32(&par->CURSOR[k++], 0, tmp);
542 }
543 k += (MAX_CURS - w) / 2;
544 }
545}
546
547static void nvidia_write_clut(struct nvidia_par *par,
548 u8 regnum, u8 red, u8 green, u8 blue)
549{
550 NVWriteDacMask(par, 0xff);
551 NVWriteDacWriteAddr(par, regnum);
552 NVWriteDacData(par, red);
553 NVWriteDacData(par, green);
554 NVWriteDacData(par, blue);
555}
556
557static void nvidia_read_clut(struct nvidia_par *par,
558 u8 regnum, u8 * red, u8 * green, u8 * blue)
559{
560 NVWriteDacMask(par, 0xff);
561 NVWriteDacReadAddr(par, regnum);
562 *red = NVReadDacData(par);
563 *green = NVReadDacData(par);
564 *blue = NVReadDacData(par);
565}
566
567static int nvidia_panel_tweak(struct nvidia_par *par,
568 struct _riva_hw_state *state)
569{
570 int tweak = 0;
571
572 if (par->paneltweak) {
573 tweak = par->paneltweak;
574 } else {
575 /* begin flat panel hacks */
576 /* This is unfortunate, but some chips need this register
577 tweaked or else you get artifacts where adjacent pixels are
578 swapped. There are no hard rules for what to set here so all
579 we can do is experiment and apply hacks. */
580
581 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
582 /* At least one NV34 laptop needs this workaround. */
583 tweak = -1;
584 }
585
586 if((par->Chipset & 0xfff0) == 0x0310) {
587 tweak = 1;
588 }
589 /* end flat panel hacks */
590 }
591
592 return tweak;
593}
594
595static void nvidia_save_vga(struct nvidia_par *par,
596 struct _riva_hw_state *state)
597{
598 int i;
599
600 NVTRACE_ENTER();
601 NVLockUnlock(par, 0);
602
603 NVUnloadStateExt(par, state);
604
605 state->misc_output = NVReadMiscOut(par);
606
607 for (i = 0; i < NUM_CRT_REGS; i++)
608 state->crtc[i] = NVReadCrtc(par, i);
609
610 for (i = 0; i < NUM_ATC_REGS; i++)
611 state->attr[i] = NVReadAttr(par, i);
612
613 for (i = 0; i < NUM_GRC_REGS; i++)
614 state->gra[i] = NVReadGr(par, i);
615
616 for (i = 0; i < NUM_SEQ_REGS; i++)
617 state->seq[i] = NVReadSeq(par, i);
618 NVTRACE_LEAVE();
619}
620
621static void nvidia_write_regs(struct nvidia_par *par)
622{
623 struct _riva_hw_state *state = &par->ModeReg;
624 int i;
625
626 NVTRACE_ENTER();
627 NVWriteCrtc(par, 0x11, 0x00);
628
629 NVLockUnlock(par, 0);
630
631 NVLoadStateExt(par, state);
632
633 NVWriteMiscOut(par, state->misc_output);
634
635 for (i = 0; i < NUM_CRT_REGS; i++) {
636 switch (i) {
637 case 0x19:
638 case 0x20 ... 0x40:
639 break;
640 default:
641 NVWriteCrtc(par, i, state->crtc[i]);
642 }
643 }
644
645 for (i = 0; i < NUM_ATC_REGS; i++)
646 NVWriteAttr(par, i, state->attr[i]);
647
648 for (i = 0; i < NUM_GRC_REGS; i++)
649 NVWriteGr(par, i, state->gra[i]);
650
651 for (i = 0; i < NUM_SEQ_REGS; i++)
652 NVWriteSeq(par, i, state->seq[i]);
653 NVTRACE_LEAVE();
654}
655
656static int nvidia_calc_regs(struct fb_info *info)
657{
658 struct nvidia_par *par = info->par;
659 struct _riva_hw_state *state = &par->ModeReg;
660 int i, depth = fb_get_color_depth(&info->var);
661 int h_display = info->var.xres / 8 - 1;
662 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
663 int h_end = (info->var.xres + info->var.right_margin +
664 info->var.hsync_len) / 8 - 1;
665 int h_total = (info->var.xres + info->var.right_margin +
666 info->var.hsync_len + info->var.left_margin) / 8 - 5;
667 int h_blank_s = h_display;
668 int h_blank_e = h_total + 4;
669 int v_display = info->var.yres - 1;
670 int v_start = info->var.yres + info->var.lower_margin - 1;
671 int v_end = (info->var.yres + info->var.lower_margin +
672 info->var.vsync_len) - 1;
673 int v_total = (info->var.yres + info->var.lower_margin +
674 info->var.vsync_len + info->var.upper_margin) - 2;
675 int v_blank_s = v_display;
676 int v_blank_e = v_total + 1;
677
678 /*
679 * Set all CRTC values.
680 */
681
682 if (info->var.vmode & FB_VMODE_INTERLACED)
683 v_total |= 1;
684
685 if (par->FlatPanel == 1) {
686 v_start = v_total - 3;
687 v_end = v_total - 2;
688 v_blank_s = v_start;
689 h_start = h_total - 5;
690 h_end = h_total - 2;
691 h_blank_e = h_total + 4;
692 }
693
694 state->crtc[0x0] = Set8Bits(h_total);
695 state->crtc[0x1] = Set8Bits(h_display);
696 state->crtc[0x2] = Set8Bits(h_blank_s);
697 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
698 | SetBit(7);
699 state->crtc[0x4] = Set8Bits(h_start);
700 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
701 | SetBitField(h_end, 4: 0, 4:0);
702 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
703 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
704 | SetBitField(v_display, 8: 8, 1:1)
705 | SetBitField(v_start, 8: 8, 2:2)
706 | SetBitField(v_blank_s, 8: 8, 3:3)
707 | SetBit(4)
708 | SetBitField(v_total, 9: 9, 5:5)
709 | SetBitField(v_display, 9: 9, 6:6)
710 | SetBitField(v_start, 9: 9, 7:7);
711 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
712 | SetBit(6)
713 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
714 state->crtc[0x10] = Set8Bits(v_start);
715 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
716 state->crtc[0x12] = Set8Bits(v_display);
717 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
718 (info->var.bits_per_pixel / 8));
719 state->crtc[0x15] = Set8Bits(v_blank_s);
720 state->crtc[0x16] = Set8Bits(v_blank_e);
721
722 state->attr[0x10] = 0x01;
723
724 if (par->Television)
725 state->attr[0x11] = 0x00;
726
727 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
728 | SetBitField(v_blank_s, 10: 10, 3:3)
729 | SetBitField(v_start, 10: 10, 2:2)
730 | SetBitField(v_display, 10: 10, 1:1)
731 | SetBitField(v_total, 10: 10, 0:0);
732
733 state->horiz = SetBitField(h_total, 8: 8, 0:0)
734 | SetBitField(h_display, 8: 8, 1:1)
735 | SetBitField(h_blank_s, 8: 8, 2:2)
736 | SetBitField(h_start, 8: 8, 3:3);
737
738 state->extra = SetBitField(v_total, 11: 11, 0:0)
739 | SetBitField(v_display, 11: 11, 2:2)
740 | SetBitField(v_start, 11: 11, 4:4)
741 | SetBitField(v_blank_s, 11: 11, 6:6);
742
743 if (info->var.vmode & FB_VMODE_INTERLACED) {
744 h_total = (h_total >> 1) & ~1;
745 state->interlace = Set8Bits(h_total);
746 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
747 } else {
748 state->interlace = 0xff; /* interlace off */
749 }
750
751 /*
752 * Calculate the extended registers.
753 */
754
755 if (depth < 24)
756 i = depth;
757 else
758 i = 32;
759
760 if (par->Architecture >= NV_ARCH_10)
761 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
762 par->CursorStart);
763
764 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
765 state->misc_output &= ~0x40;
766 else
767 state->misc_output |= 0x40;
768 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
769 state->misc_output &= ~0x80;
770 else
771 state->misc_output |= 0x80;
772
773 NVCalcStateExt(par, state, i, info->var.xres_virtual,
774 info->var.xres, info->var.yres_virtual,
775 1000000000 / info->var.pixclock, info->var.vmode);
776
777 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
778 if (par->FlatPanel == 1) {
779 state->pixel |= (1 << 7);
780
781 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
782 || (par->fpHeight <= info->var.yres)) {
783 state->scale |= (1 << 8);
784 }
785
786 if (!par->crtcSync_read) {
787 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
788 par->crtcSync_read = 1;
789 }
790
791 par->PanelTweak = nvidia_panel_tweak(par, state);
792 }
793
794 state->vpll = state->pll;
795 state->vpll2 = state->pll;
796 state->vpllB = state->pllB;
797 state->vpll2B = state->pllB;
798
799 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
800 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
801
802 if (par->CRTCnumber) {
803 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
804 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
805 state->crtcOwner = 3;
806 state->pllsel |= 0x20000800;
807 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
808 if (par->twoStagePLL)
809 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
810 } else if (par->twoHeads) {
811 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
812 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
813 state->crtcOwner = 0;
814 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
815 if (par->twoStagePLL)
816 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
817 }
818
819 state->cursorConfig = 0x00000100;
820
821 if (info->var.vmode & FB_VMODE_DOUBLE)
822 state->cursorConfig |= (1 << 4);
823
824 if (par->alphaCursor) {
825 if ((par->Chipset & 0x0ff0) != 0x0110)
826 state->cursorConfig |= 0x04011000;
827 else
828 state->cursorConfig |= 0x14011000;
829 state->general |= (1 << 29);
830 } else
831 state->cursorConfig |= 0x02000000;
832
833 if (par->twoHeads) {
834 if ((par->Chipset & 0x0ff0) == 0x0110) {
835 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
836 ~0x00010000;
837 if (par->FPDither)
838 state->dither |= 0x00010000;
839 } else {
840 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
841 if (par->FPDither)
842 state->dither |= 1;
843 }
844 }
845
846 state->timingH = 0;
847 state->timingV = 0;
848 state->displayV = info->var.xres;
849
850 return 0;
851}
852
853static void nvidia_init_vga(struct fb_info *info)
854{
855 struct nvidia_par *par = info->par;
856 struct _riva_hw_state *state = &par->ModeReg;
857 int i;
858
859 for (i = 0; i < 0x10; i++)
860 state->attr[i] = i;
861 state->attr[0x10] = 0x41;
862 state->attr[0x11] = 0x01;
863 state->attr[0x12] = 0x0f;
864 state->attr[0x13] = 0x00;
865 state->attr[0x14] = 0x00;
866
867 memset(state->crtc, 0x00, NUM_CRT_REGS);
868 state->crtc[0x0a] = 0x20;
869 state->crtc[0x17] = 0xe3;
870 state->crtc[0x18] = 0xff;
871 state->crtc[0x28] = 0x40;
872
873 memset(state->gra, 0x00, NUM_GRC_REGS);
874 state->gra[0x05] = 0x40;
875 state->gra[0x06] = 0x05;
876 state->gra[0x07] = 0x0f;
877 state->gra[0x08] = 0xff;
878
879 state->seq[0x00] = 0x03;
880 state->seq[0x01] = 0x01;
881 state->seq[0x02] = 0x0f;
882 state->seq[0x03] = 0x00;
883 state->seq[0x04] = 0x0e;
884
885 state->misc_output = 0xeb;
886}
887
888static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
889{
890 struct nvidia_par *par = info->par;
891 u8 data[MAX_CURS * MAX_CURS / 8];
892 u16 fg, bg;
893 int i, set = cursor->set;
894
895 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
896 return soft_cursor(info, cursor);
897
898 NVShowHideCursor(par, 0);
899
900 if (par->cursor_reset) {
901 set = FB_CUR_SETALL;
902 par->cursor_reset = 0;
903 }
904
905 if (set & FB_CUR_SETSIZE)
906 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
907
908 if (set & FB_CUR_SETPOS) {
909 u32 xx, yy, temp;
910
911 yy = cursor->image.dy - info->var.yoffset;
912 xx = cursor->image.dx - info->var.xoffset;
913 temp = xx & 0xFFFF;
914 temp |= yy << 16;
915
916 NV_WR32(par->PRAMDAC, 0x0000300, temp);
917 }
918
919 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
920 u32 bg_idx = cursor->image.bg_color;
921 u32 fg_idx = cursor->image.fg_color;
922 u32 s_pitch = (cursor->image.width + 7) >> 3;
923 u32 d_pitch = MAX_CURS / 8;
924 u8 *dat = (u8 *) cursor->image.data;
925 u8 *msk = (u8 *) cursor->mask;
926 u8 *src;
927
928 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
929
930 if (src) {
931 switch (cursor->rop) {
932 case ROP_XOR:
933 for (i = 0; i < s_pitch * cursor->image.height;
934 i++)
935 src[i] = dat[i] ^ msk[i];
936 break;
937 case ROP_COPY:
938 default:
939 for (i = 0; i < s_pitch * cursor->image.height;
940 i++)
941 src[i] = dat[i] & msk[i];
942 break;
943 }
944
945 fb_sysmove_buf_aligned(info, &info->pixmap, data,
946 d_pitch, src, s_pitch,
947 cursor->image.height);
948
949 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
950 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
951 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
952
953 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
954 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
955 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
956
957 NVLockUnlock(par, 0);
958
959 nvidiafb_load_cursor_image(par, data, bg, fg,
960 cursor->image.width,
961 cursor->image.height);
962 kfree(src);
963 }
964 }
965
966 if (cursor->enable)
967 NVShowHideCursor(par, 1);
968
969 return 0;
970}
971
972static int nvidiafb_set_par(struct fb_info *info)
973{
974 struct nvidia_par *par = info->par;
975
976 NVTRACE_ENTER();
977
978 NVLockUnlock(par, 1);
979 if (!par->FlatPanel || (info->var.bits_per_pixel != 24) ||
980 !par->twoHeads)
981 par->FPDither = 0;
982
983 nvidia_init_vga(info);
984 nvidia_calc_regs(info);
985 nvidia_write_regs(par);
986
987 NVLockUnlock(par, 0);
988 if (par->twoHeads) {
989 VGA_WR08(par->PCIO, 0x03D4, 0x44);
990 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
991 NVLockUnlock(par, 0);
992 }
993
994 NVWriteCrtc(par, 0x11, 0x00);
995 info->fix.line_length = (info->var.xres_virtual *
996 info->var.bits_per_pixel) >> 3;
997 info->fix.visual = (info->var.bits_per_pixel == 8) ?
998 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
999
1000 if (info->var.accel_flags) {
1001 info->fbops->fb_imageblit = nvidiafb_imageblit;
1002 info->fbops->fb_fillrect = nvidiafb_fillrect;
1003 info->fbops->fb_copyarea = nvidiafb_copyarea;
1004 info->fbops->fb_sync = nvidiafb_sync;
1005 info->pixmap.scan_align = 4;
1006 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1007 NVResetGraphics(info);
1008 } else {
1009 info->fbops->fb_imageblit = cfb_imageblit;
1010 info->fbops->fb_fillrect = cfb_fillrect;
1011 info->fbops->fb_copyarea = cfb_copyarea;
1012 info->fbops->fb_sync = NULL;
1013 info->pixmap.scan_align = 1;
1014 info->flags |= FBINFO_HWACCEL_DISABLED;
1015 }
1016
1017 par->cursor_reset = 1;
1018
1019 NVWriteCrtc(par, 0x11, 0xff);
1020
1021 NVTRACE_LEAVE();
1022 return 0;
1023}
1024
1025static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1026 unsigned blue, unsigned transp,
1027 struct fb_info *info)
1028{
1029 struct nvidia_par *par = info->par;
1030 int i;
1031
1032 NVTRACE_ENTER();
1033 if (regno >= (1 << info->var.green.length))
1034 return -EINVAL;
1035
1036 if (info->var.grayscale) {
1037 /* gray = 0.30*R + 0.59*G + 0.11*B */
1038 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1039 }
1040
1041 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1042 ((u32 *) info->pseudo_palette)[regno] =
1043 (regno << info->var.red.offset) |
1044 (regno << info->var.green.offset) |
1045 (regno << info->var.blue.offset);
1046 }
1047
1048 switch (info->var.bits_per_pixel) {
1049 case 8:
1050 /* "transparent" stuff is completely ignored. */
1051 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1052 break;
1053 case 16:
1054 if (info->var.green.length == 5) {
1055 for (i = 0; i < 8; i++) {
1056 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1057 green >> 8, blue >> 8);
1058 }
1059 } else {
1060 u8 r, g, b;
1061
1062 if (regno < 32) {
1063 for (i = 0; i < 8; i++) {
1064 nvidia_write_clut(par, regno * 8 + i,
1065 red >> 8, green >> 8,
1066 blue >> 8);
1067 }
1068 }
1069
1070 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1071
1072 for (i = 0; i < 4; i++)
1073 nvidia_write_clut(par, regno * 4 + i, r,
1074 green >> 8, b);
1075 }
1076 break;
1077 case 32:
1078 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1079 break;
1080 default:
1081 /* do nothing */
1082 break;
1083 }
1084
1085 NVTRACE_LEAVE();
1086 return 0;
1087}
1088
1089static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1090 struct fb_info *info)
1091{
1092 struct nvidia_par *par = info->par;
1093 int memlen, vramlen, mode_valid = 0;
1094 int pitch, err = 0;
1095
1096 NVTRACE_ENTER();
1097
1098 var->transp.offset = 0;
1099 var->transp.length = 0;
1100
1101 var->xres &= ~7;
1102
1103 if (var->bits_per_pixel <= 8)
1104 var->bits_per_pixel = 8;
1105 else if (var->bits_per_pixel <= 16)
1106 var->bits_per_pixel = 16;
1107 else
1108 var->bits_per_pixel = 32;
1109
1110 switch (var->bits_per_pixel) {
1111 case 8:
1112 var->red.offset = 0;
1113 var->red.length = 8;
1114 var->green.offset = 0;
1115 var->green.length = 8;
1116 var->blue.offset = 0;
1117 var->blue.length = 8;
1118 var->transp.offset = 0;
1119 var->transp.length = 0;
1120 break;
1121 case 16:
1122 var->green.length = (var->green.length < 6) ? 5 : 6;
1123 var->red.length = 5;
1124 var->blue.length = 5;
1125 var->transp.length = 6 - var->green.length;
1126 var->blue.offset = 0;
1127 var->green.offset = 5;
1128 var->red.offset = 5 + var->green.length;
1129 var->transp.offset = (5 + var->red.offset) & 15;
1130 break;
1131 case 32: /* RGBA 8888 */
1132 var->red.offset = 16;
1133 var->red.length = 8;
1134 var->green.offset = 8;
1135 var->green.length = 8;
1136 var->blue.offset = 0;
1137 var->blue.length = 8;
1138 var->transp.length = 8;
1139 var->transp.offset = 24;
1140 break;
1141 }
1142
1143 var->red.msb_right = 0;
1144 var->green.msb_right = 0;
1145 var->blue.msb_right = 0;
1146 var->transp.msb_right = 0;
1147
1148 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1149 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1150 mode_valid = 1;
1151
1152 /* calculate modeline if supported by monitor */
1153 if (!mode_valid && info->monspecs.gtf) {
1154 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1155 mode_valid = 1;
1156 }
1157
1158 if (!mode_valid) {
1159 struct fb_videomode *mode;
1160
1161 mode = fb_find_best_mode(var, &info->modelist);
1162 if (mode) {
1163 fb_videomode_to_var(var, mode);
1164 mode_valid = 1;
1165 }
1166 }
1167
1168 if (!mode_valid && info->monspecs.modedb_len)
1169 return -EINVAL;
1170
1171 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1172 par->fpHeight < var->yres))
1173 return -EINVAL;
1174
1175 if (var->yres_virtual < var->yres)
1176 var->yres_virtual = var->yres;
1177
1178 if (var->xres_virtual < var->xres)
1179 var->xres_virtual = var->xres;
1180
1181 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1182
1183 vramlen = info->fix.smem_len;
1184 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1185 memlen = pitch * var->yres_virtual;
1186
1187 if (memlen > vramlen) {
1188 var->yres_virtual = vramlen / pitch;
1189
1190 if (var->yres_virtual < var->yres) {
1191 var->yres_virtual = var->yres;
1192 var->xres_virtual = vramlen / var->yres_virtual;
1193 var->xres_virtual /= var->bits_per_pixel / 8;
1194 var->xres_virtual &= ~63;
1195 pitch = (var->xres_virtual *
1196 var->bits_per_pixel + 7) / 8;
1197 memlen = pitch * var->yres;
1198
1199 if (var->xres_virtual < var->xres) {
1200 printk("nvidiafb: required video memory, "
1201 "%d bytes, for %dx%d-%d (virtual) "
1202 "is out of range\n",
1203 memlen, var->xres_virtual,
1204 var->yres_virtual, var->bits_per_pixel);
1205 err = -ENOMEM;
1206 }
1207 }
1208 }
1209
1210 if (var->accel_flags) {
1211 if (var->yres_virtual > 0x7fff)
1212 var->yres_virtual = 0x7fff;
1213 if (var->xres_virtual > 0x7fff)
1214 var->xres_virtual = 0x7fff;
1215 }
1216
1217 var->xres_virtual &= ~63;
1218
1219 NVTRACE_LEAVE();
1220
1221 return err;
1222}
1223
1224static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1225 struct fb_info *info)
1226{
1227 struct nvidia_par *par = info->par;
1228 u32 total;
1229
1230 total = info->var.yoffset * info->fix.line_length + info->var.xoffset;
1231
1232 NVSetStartAddress(par, total);
1233
1234 return 0;
1235}
1236
1237static int nvidiafb_blank(int blank, struct fb_info *info)
1238{
1239 struct nvidia_par *par = info->par;
1240 unsigned char tmp, vesa;
1241
1242 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1243 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1244
1245 NVTRACE_ENTER();
1246
1247 if (blank)
1248 tmp |= 0x20;
1249
1250 switch (blank) {
1251 case FB_BLANK_UNBLANK:
1252 case FB_BLANK_NORMAL:
1253 break;
1254 case FB_BLANK_VSYNC_SUSPEND:
1255 vesa |= 0x80;
1256 break;
1257 case FB_BLANK_HSYNC_SUSPEND:
1258 vesa |= 0x40;
1259 break;
1260 case FB_BLANK_POWERDOWN:
1261 vesa |= 0xc0;
1262 break;
1263 }
1264
1265 NVWriteSeq(par, 0x01, tmp);
1266 NVWriteCrtc(par, 0x1a, vesa);
1267
1268#ifdef CONFIG_PMAC_BACKLIGHT
1269 if (par->FlatPanel && _machine == _MACH_Pmac) {
1270 set_backlight_enable(!blank);
1271 }
1272#endif
1273
1274 NVTRACE_LEAVE();
1275
1276 return 0;
1277}
1278
1279static struct fb_ops nvidia_fb_ops = {
1280 .owner = THIS_MODULE,
1281 .fb_check_var = nvidiafb_check_var,
1282 .fb_set_par = nvidiafb_set_par,
1283 .fb_setcolreg = nvidiafb_setcolreg,
1284 .fb_pan_display = nvidiafb_pan_display,
1285 .fb_blank = nvidiafb_blank,
1286 .fb_fillrect = nvidiafb_fillrect,
1287 .fb_copyarea = nvidiafb_copyarea,
1288 .fb_imageblit = nvidiafb_imageblit,
1289 .fb_cursor = nvidiafb_cursor,
1290 .fb_sync = nvidiafb_sync,
1291};
1292
1293static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1294{
1295 struct fb_monspecs *specs = &info->monspecs;
1296 struct fb_videomode modedb;
1297 struct nvidia_par *par = info->par;
1298 int lpitch;
1299
1300 NVTRACE_ENTER();
1301 info->flags = FBINFO_DEFAULT
1302 | FBINFO_HWACCEL_IMAGEBLIT
1303 | FBINFO_HWACCEL_FILLRECT
1304 | FBINFO_HWACCEL_COPYAREA
1305 | FBINFO_HWACCEL_YPAN;
1306
1307 fb_videomode_to_modelist(info->monspecs.modedb,
1308 info->monspecs.modedb_len, &info->modelist);
1309 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1310
1311 if (specs->modedb != NULL) {
1312 /* get preferred timing */
1313 if (specs->misc & FB_MISC_1ST_DETAIL) {
1314 int i;
1315
1316 for (i = 0; i < specs->modedb_len; i++) {
1317 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1318 modedb = specs->modedb[i];
1319 break;
1320 }
1321 }
1322 } else {
1323 /* otherwise, get first mode in database */
1324 modedb = specs->modedb[0];
1325 }
1326
1327 fb_videomode_to_var(&nvidiafb_default_var, &modedb);
1328 nvidiafb_default_var.bits_per_pixel = 8;
1329 }
1330
1331 if (mode_option)
1332 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1333 specs->modedb, specs->modedb_len, &modedb, 8);
1334
1335 info->var = nvidiafb_default_var;
1336 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1337 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1338 info->pseudo_palette = par->pseudo_palette;
1339 fb_alloc_cmap(&info->cmap, 256, 0);
1340 fb_destroy_modedb(info->monspecs.modedb);
1341 info->monspecs.modedb = NULL;
1342
1343 /* maximize virtual vertical length */
1344 lpitch = info->var.xres_virtual *
1345 ((info->var.bits_per_pixel + 7) >> 3);
1346 info->var.yres_virtual = info->fix.smem_len / lpitch;
1347
1348 info->pixmap.scan_align = 4;
1349 info->pixmap.buf_align = 4;
1350 info->pixmap.size = 8 * 1024;
1351 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1352
1353 if (!hwcur)
1354 info->fbops->fb_cursor = soft_cursor;
1355 info->var.accel_flags = (!noaccel);
1356
1357 switch (par->Architecture) {
1358 case NV_ARCH_04:
1359 info->fix.accel = FB_ACCEL_NV4;
1360 break;
1361 case NV_ARCH_10:
1362 info->fix.accel = FB_ACCEL_NV_10;
1363 break;
1364 case NV_ARCH_20:
1365 info->fix.accel = FB_ACCEL_NV_20;
1366 break;
1367 case NV_ARCH_30:
1368 info->fix.accel = FB_ACCEL_NV_30;
1369 break;
1370 case NV_ARCH_40:
1371 info->fix.accel = FB_ACCEL_NV_40;
1372 break;
1373 }
1374
1375 NVTRACE_LEAVE();
1376
1377 return nvidiafb_check_var(&info->var, info);
1378}
1379
1380static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
1381{
1382 u32 arch = 0;
1383
1384 switch (pd->device & 0x0ff0) {
1385 case 0x0100: /* GeForce 256 */
1386 case 0x0110: /* GeForce2 MX */
1387 case 0x0150: /* GeForce2 */
1388 case 0x0170: /* GeForce4 MX */
1389 case 0x0180: /* GeForce4 MX (8x AGP) */
1390 case 0x01A0: /* nForce */
1391 case 0x01F0: /* nForce2 */
1392 arch = NV_ARCH_10;
1393 break;
1394 case 0x0200: /* GeForce3 */
1395 case 0x0250: /* GeForce4 Ti */
1396 case 0x0280: /* GeForce4 Ti (8x AGP) */
1397 arch = NV_ARCH_20;
1398 break;
1399 case 0x0300: /* GeForceFX 5800 */
1400 case 0x0310: /* GeForceFX 5600 */
1401 case 0x0320: /* GeForceFX 5200 */
1402 case 0x0330: /* GeForceFX 5900 */
1403 case 0x0340: /* GeForceFX 5700 */
1404 arch = NV_ARCH_30;
1405 break;
1406 case 0x0040:
1407 case 0x00C0:
1408 case 0x0120:
1409 case 0x0130:
1410 case 0x0140:
1411 case 0x0160:
1412 case 0x01D0:
1413 case 0x0090:
1414 case 0x0210:
1415 case 0x0220:
1416 case 0x0230:
1417 arch = NV_ARCH_40;
1418 break;
1419 case 0x0020: /* TNT, TNT2 */
1420 arch = NV_ARCH_04;
1421 break;
1422 default: /* unknown architecture */
1423 break;
1424 }
1425
1426 return arch;
1427}
1428
1429static int __devinit nvidiafb_probe(struct pci_dev *pd,
1430 const struct pci_device_id *ent)
1431{
1432 struct nvidia_par *par;
1433 struct fb_info *info;
1434 unsigned short cmd;
1435
1436
1437 NVTRACE_ENTER();
1438 assert(pd != NULL);
1439
1440 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1441
1442 if (!info)
1443 goto err_out;
1444
1445 par = (struct nvidia_par *)info->par;
1446 par->pci_dev = pd;
1447
1448 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1449
1450 if (info->pixmap.addr == NULL)
1451 goto err_out_kfree;
1452
1453 memset(info->pixmap.addr, 0, 8 * 1024);
1454
1455 if (pci_enable_device(pd)) {
1456 printk(KERN_ERR PFX "cannot enable PCI device\n");
1457 goto err_out_enable;
1458 }
1459
1460 if (pci_request_regions(pd, "nvidiafb")) {
1461 printk(KERN_ERR PFX "cannot request PCI regions\n");
1462 goto err_out_request;
1463 }
1464
1465 par->Architecture = nvidia_get_arch(pd);
1466
1467 par->Chipset = (pd->vendor << 16) | pd->device;
1468 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1469
1470#ifdef CONFIG_PCI_NAMES
1471 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1472#endif
1473
1474 if (par->Architecture == 0) {
1475 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1476 goto err_out_free_base0;
1477 }
1478
1479 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1480
1481 par->FlatPanel = flatpanel;
1482
1483 if (flatpanel == 1)
1484 printk(KERN_INFO PFX "flatpanel support enabled\n");
1485
1486 par->CRTCnumber = forceCRTC;
1487 par->FpScale = (!noscale);
1488 par->paneltweak = paneltweak;
1489
1490 /* enable IO and mem if not already done */
1491 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1492 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1493 pci_write_config_word(pd, PCI_COMMAND, cmd);
1494
1495 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1496 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1497 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1498
1499 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1500
1501 if (!par->REGS) {
1502 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1503 goto err_out_free_base0;
1504 }
1505
1506 NVCommonSetup(info);
1507
1508 par->FbAddress = nvidiafb_fix.smem_start;
1509 par->FbMapSize = par->RamAmountKBytes * 1024;
1510 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1511 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1512 16 * 1024;
1513 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1514 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1515 nvidiafb_fix.smem_len = par->FbUsableSize;
1516
1517 if (!info->screen_base) {
1518 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1519 goto err_out_free_base1;
1520 }
1521
1522 par->FbStart = info->screen_base;
1523
1524#ifdef CONFIG_MTRR
1525 if (!nomtrr) {
1526 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1527 par->FbMapSize, MTRR_TYPE_WRCOMB, 1);
1528 if (par->mtrr.vram < 0) {
1529 printk(KERN_ERR PFX "unable to setup MTRR\n");
1530 } else {
1531 par->mtrr.vram_valid = 1;
1532 /* let there be speed */
1533 printk(KERN_INFO PFX "MTRR set to ON\n");
1534 }
1535 }
1536#endif /* CONFIG_MTRR */
1537
1538 info->fbops = &nvidia_fb_ops;
1539 info->fix = nvidiafb_fix;
1540
1541 if (nvidia_set_fbinfo(info) < 0) {
1542 printk(KERN_ERR PFX "error setting initial video mode\n");
1543 goto err_out_iounmap_fb;
1544 }
1545
1546 nvidia_save_vga(par, &par->SavedReg);
1547
1548 if (register_framebuffer(info) < 0) {
1549 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1550 goto err_out_iounmap_fb;
1551 }
1552
1553 pci_set_drvdata(pd, info);
1554
1555 printk(KERN_INFO PFX
1556 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1557 info->fix.id,
1558 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1559#ifdef CONFIG_PMAC_BACKLIGHT
1560 if (par->FlatPanel && _machine == _MACH_Pmac)
1561 register_backlight_controller(&nvidia_backlight_controller,
1562 par, "mnca");
1563#endif
1564 NVTRACE_LEAVE();
1565 return 0;
1566
1567 err_out_iounmap_fb:
1568 iounmap(info->screen_base);
1569 fb_destroy_modedb(info->monspecs.modedb);
1570 nvidia_delete_i2c_busses(par);
1571 err_out_free_base1:
1572 iounmap(par->REGS);
1573 err_out_free_base0:
1574 pci_release_regions(pd);
1575 err_out_request:
1576 pci_disable_device(pd);
1577 err_out_enable:
1578 kfree(info->pixmap.addr);
1579 err_out_kfree:
1580 framebuffer_release(info);
1581 err_out:
1582 return -ENODEV;
1583}
1584
1585static void __exit nvidiafb_remove(struct pci_dev *pd)
1586{
1587 struct fb_info *info = pci_get_drvdata(pd);
1588 struct nvidia_par *par = info->par;
1589
1590 NVTRACE_ENTER();
1591 if (!info)
1592 return;
1593
1594 unregister_framebuffer(info);
1595#ifdef CONFIG_MTRR
1596 if (par->mtrr.vram_valid)
1597 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1598 info->fix.smem_len);
1599#endif /* CONFIG_MTRR */
1600
1601 iounmap(info->screen_base);
1602 fb_destroy_modedb(info->monspecs.modedb);
1603 nvidia_delete_i2c_busses(par);
1604 iounmap(par->REGS);
1605 pci_release_regions(pd);
1606 pci_disable_device(pd);
1607 kfree(info->pixmap.addr);
1608 framebuffer_release(info);
1609 pci_set_drvdata(pd, NULL);
1610 NVTRACE_LEAVE();
1611}
1612
1613/* ------------------------------------------------------------------------- *
1614 *
1615 * initialization
1616 *
1617 * ------------------------------------------------------------------------- */
1618
1619#ifndef MODULE
1620static int __devinit nvidiafb_setup(char *options)
1621{
1622 char *this_opt;
1623
1624 NVTRACE_ENTER();
1625 if (!options || !*options)
1626 return 0;
1627
1628 while ((this_opt = strsep(&options, ",")) != NULL) {
1629 if (!strncmp(this_opt, "forceCRTC", 9)) {
1630 char *p;
1631
1632 p = this_opt + 9;
1633 if (!*p || !*(++p))
1634 continue;
1635 forceCRTC = *p - '0';
1636 if (forceCRTC < 0 || forceCRTC > 1)
1637 forceCRTC = -1;
1638 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1639 flatpanel = 1;
1640 } else if (!strncmp(this_opt, "hwcur", 5)) {
1641 hwcur = 1;
1642 } else if (!strncmp(this_opt, "noaccel", 6)) {
1643 noaccel = 1;
1644 } else if (!strncmp(this_opt, "noscale", 7)) {
1645 noscale = 1;
1646 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1647 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1648#ifdef CONFIG_MTRR
1649 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1650 nomtrr = 1;
1651#endif
1652 } else
1653 mode_option = this_opt;
1654 }
1655 NVTRACE_LEAVE();
1656 return 0;
1657}
1658#endif /* !MODULE */
1659
1660static struct pci_driver nvidiafb_driver = {
1661 .name = "nvidiafb",
1662 .id_table = nvidiafb_pci_tbl,
1663 .probe = nvidiafb_probe,
1664 .remove = __exit_p(nvidiafb_remove),
1665};
1666
1667/* ------------------------------------------------------------------------- *
1668 *
1669 * modularization
1670 *
1671 * ------------------------------------------------------------------------- */
1672
1673static int __devinit nvidiafb_init(void)
1674{
1675#ifndef MODULE
1676 char *option = NULL;
1677
1678 if (fb_get_options("nvidiafb", &option))
1679 return -ENODEV;
1680 nvidiafb_setup(option);
1681#endif
1682 return pci_register_driver(&nvidiafb_driver);
1683}
1684
1685module_init(nvidiafb_init);
1686
1687#ifdef MODULE
1688static void __exit nvidiafb_exit(void)
1689{
1690 pci_unregister_driver(&nvidiafb_driver);
1691}
1692
1693module_exit(nvidiafb_exit);
1694
1695module_param(flatpanel, int, 0);
1696MODULE_PARM_DESC(flatpanel,
1697 "Enables experimental flat panel support for some chipsets. "
1698 "(0 or 1=enabled) (default=0)");
1699module_param(hwcur, int, 0);
1700MODULE_PARM_DESC(hwcur,
1701 "Enables hardware cursor implementation. (0 or 1=enabled) "
1702 "(default=0)");
1703module_param(noaccel, int, 0);
1704MODULE_PARM_DESC(noaccel,
1705 "Disables hardware acceleration. (0 or 1=disable) "
1706 "(default=0)");
1707module_param(noscale, int, 0);
1708MODULE_PARM_DESC(noscale,
1709 "Disables screen scaleing. (0 or 1=disable) "
1710 "(default=0, do scaling)");
1711module_param(paneltweak, int, 0);
1712MODULE_PARM_DESC(paneltweak,
1713 "Tweak display settings for flatpanels. "
1714 "(default=0, no tweaks)");
1715module_param(forceCRTC, int, 0);
1716MODULE_PARM_DESC(forceCRTC,
1717 "Forces usage of a particular CRTC in case autodetection "
1718 "fails. (0 or 1) (default=autodetect)");
1719#ifdef CONFIG_MTRR
1720module_param(nomtrr, bool, 0);
1721MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1722 "(default=0)");
1723#endif
1724
1725MODULE_AUTHOR("Antonino Daplas");
1726MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1727MODULE_LICENSE("GPL");
1728#endif /* MODULE */
1729
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 10:07:18 -0500