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path: root/drivers/video/mbx/reg_bits.h
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-rw-r--r--drivers/video/mbx/reg_bits.h418
1 files changed, 418 insertions, 0 deletions
diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h
new file mode 100644
index 000000000000..c226a8e45312
--- /dev/null
+++ b/drivers/video/mbx/reg_bits.h
@@ -0,0 +1,418 @@
1#ifndef __REG_BITS_2700G_
2#define __REG_BITS_2700G_
3
4/* use defines from asm-arm/arch-pxa/bitfields.h for bit fields access */
5#define UData(Data) ((unsigned long) (Data))
6#define Fld(Size, Shft) (((Size) << 16) + (Shft))
7#define FSize(Field) ((Field) >> 16)
8#define FShft(Field) ((Field) & 0x0000FFFF)
9#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
10#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
11#define F1stBit(Field) (UData (1) << FShft (Field))
12
13#define SYSRST_RST (1 << 0)
14
15/* SYSCLKSRC - SYSCLK Source Control Register */
16#define SYSCLKSRC_SEL Fld(2,0)
17#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
18#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
19#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
20
21/* PIXCLKSRC - PIXCLK Source Control Register */
22#define PIXCLKSRC_SEL Fld(2,0)
23#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
24#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
25#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
26
27/* Clock Disable Register */
28#define CLKSLEEP_SLP (1 << 0)
29
30/* Core PLL Control Register */
31#define CORE_PLL_M Fld(6,7)
32#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
33#define CORE_PLL_N Fld(3,4)
34#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
35#define CORE_PLL_P Fld(3,1)
36#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
37#define CORE_PLL_EN (1 << 0)
38
39/* Display PLL Control Register */
40#define DISP_PLL_M Fld(6,7)
41#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
42#define DISP_PLL_N Fld(3,4)
43#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
44#define DISP_PLL_P Fld(3,1)
45#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
46#define DISP_PLL_EN (1 << 0)
47
48/* PLL status register */
49#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
50#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
51#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
52#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
53
54/* Video and scale clock control register */
55#define VOVRCLK_EN (1 << 0)
56
57/* Pixel clock control register */
58#define PIXCLK_EN (1 << 0)
59
60/* Memory clock control register */
61#define MEMCLK_EN (1 << 0)
62
63/* MBX clock control register */
64#define MBXCLK_DIV Fld(2,2)
65#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
66#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
67#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
68#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
69#define MBXCLK_EN Fld(2,0)
70#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
71#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
72#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
73
74/* M24 clock control register */
75#define M24CLK_DIV Fld(2,1)
76#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
77#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
78#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
79#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
80#define M24CLK_EN (1 << 0)
81
82/* SDRAM clock control register */
83#define SDCLK_EN (1 << 0)
84
85/* PixClk Divisor Register */
86#define PIXCLKDIV_PD Fld(9,0)
87#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
88
89/* LCD Config control register */
90#define LCDCFG_IN_FMT Fld(3,28)
91#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
92#define LCDCFG_LCD1DEN_POL (1 << 27)
93#define LCDCFG_LCD1FCLK_POL (1 << 26)
94#define LCDCFG_LCD1LCLK_POL (1 << 25)
95#define LCDCFG_LCD1D_POL (1 << 24)
96#define LCDCFG_LCD2DEN_POL (1 << 23)
97#define LCDCFG_LCD2FCLK_POL (1 << 22)
98#define LCDCFG_LCD2LCLK_POL (1 << 21)
99#define LCDCFG_LCD2D_POL (1 << 20)
100#define LCDCFG_LCD1_TS (1 << 19)
101#define LCDCFG_LCD1D_DS (1 << 18)
102#define LCDCFG_LCD1C_DS (1 << 17)
103#define LCDCFG_LCD1_IS_IN (1 << 16)
104#define LCDCFG_LCD2_TS (1 << 3)
105#define LCDCFG_LCD2D_DS (1 << 2)
106#define LCDCFG_LCD2C_DS (1 << 1)
107#define LCDCFG_LCD2_IS_IN (1 << 0)
108
109/* On-Die Frame Buffer Power Control Register */
110#define ODFBPWR_SLOW (1 << 2)
111#define ODFBPWR_MODE Fld(2,0)
112#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
113#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
114#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
115#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
116
117/* On-Die Frame Buffer Power State Status Register */
118#define ODFBSTAT_ACT (1 << 2)
119#define ODFBSTAT_SLP (1 << 1)
120#define ODFBSTAT_SDN (1 << 0)
121
122/* LMRST - Local Memory (SDRAM) Reset */
123#define LMRST_MC_RST (1 << 0)
124
125/* LMCFG - Local Memory (SDRAM) Configuration Register */
126#define LMCFG_LMC_DS (1 << 5)
127#define LMCFG_LMD_DS (1 << 4)
128#define LMCFG_LMA_DS (1 << 3)
129#define LMCFG_LMC_TS (1 << 2)
130#define LMCFG_LMD_TS (1 << 1)
131#define LMCFG_LMA_TS (1 << 0)
132
133/* LMPWR - Local Memory (SDRAM) Power Control Register */
134#define LMPWR_MC_PWR_CNT Fld(2,0)
135#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
136#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
137#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
138
139/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
140#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
141#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
142#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
143#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
144
145/* LMTYPE - Local Memory (SDRAM) Type Register */
146#define LMTYPE_CASLAT Fld(3,10)
147#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
148#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
149#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
150#define LMTYPE_BKSZ Fld(2,8)
151#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
152#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
153#define LMTYPE_ROWSZ Fld(4,4)
154#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
155#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
156#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
157#define LMTYPE_COLSZ Fld(4,0)
158#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
159#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
160#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
161#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
162#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
163#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
164
165/* LMTIM - Local Memory (SDRAM) Timing Register */
166#define LMTIM_TRAS Fld(4,16)
167#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
168#define LMTIM_TRP Fld(4,12)
169#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
170#define LMTIM_TRCD Fld(4,8)
171#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
172#define LMTIM_TRC Fld(4,4)
173#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
174#define LMTIM_TDPL Fld(4,0)
175#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
176
177/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
178#define LMREFRESH_TREF Fld(2,0)
179#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
180
181/* GSCTRL - Graphics surface control register */
182#define GSCTRL_LUT_EN (1 << 31)
183#define GSCTRL_GPIXFMT Fld(4,27)
184#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
185#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
186#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
187#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
188#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
189#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
190#define GSCTRL_GAMMA_EN (1 << 26)
191
192#define GSCTRL_GSWIDTH Fld(11,11)
193#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
194 (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
195
196#define GSCTRL_GSHEIGHT Fld(11,0)
197#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
198 (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
199
200/* GBBASE fileds */
201#define GBBASE_GLALPHA Fld(8,24)
202#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
203
204#define GBBASE_COLKEY Fld(24,0)
205#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
206
207/* GDRCTRL fields */
208#define GDRCTRL_PIXDBL (1 << 31)
209#define GDRCTRL_PIXHLV (1 << 30)
210#define GDRCTRL_LNDBL (1 << 29)
211#define GDRCTRL_LNHLV (1 << 28)
212#define GDRCTRL_COLKEYM Fld(24,0)
213#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
214
215/* GSCADR graphics stream control address register fields */
216#define GSCADR_STR_EN (1 << 31)
217#define GSCADR_COLKEY_EN (1 << 30)
218#define GSCADR_COLKEYSCR (1 << 29)
219#define GSCADR_BLEND_M Fld(2,27)
220#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
221#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
222#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
223#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
224#define GSCADR_BLEND_POS Fld(2,24)
225#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
226#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
227#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
228#define GSCADR_GBASE_ADR Fld(23,0)
229#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
230
231/* GSADR graphics stride address register fields */
232#define GSADR_SRCSTRIDE Fld(10,22)
233#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
234#define GSADR_XSTART Fld(11,11)
235#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
236#define GSADR_YSTART Fld(11,0)
237#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
238
239/* GPLUT graphics palette register fields */
240#define GPLUT_LUTADR Fld(8,24)
241#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
242#define GPLUT_LUTDATA Fld(24,0)
243#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
244
245/* HCCTRL - Hardware Cursor Register fields */
246#define HCCTRL_CUR_EN (1 << 31)
247#define HCCTRL_COLKEY_EN (1 << 29)
248#define HCCTRL_COLKEYSRC (1 << 28)
249#define HCCTRL_BLEND_M Fld(2,26)
250#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
251#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
252#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
253#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
254#define HCCTRL_CPIXFMT Fld(3,23)
255#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
256#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
257#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
258#define HCCTRL_CBASE_ADR Fld(23,0)
259#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
260
261/* HCSIZE Hardware Cursor Size Register fields */
262#define HCSIZE_BLEND_POS Fld(2,29)
263#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
264#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
265#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
266#define HCSIZE_CWIDTH Fld(3,16)
267#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
268#define HCSIZE_CHEIGHT Fld(3,0)
269#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
270
271/* HCPOS Hardware Cursor Position Register fields */
272#define HCPOS_SWITCHSRC (1 << 30)
273#define HCPOS_CURBLINK Fld(6,24)
274#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
275#define HCPOS_XSTART Fld(12,12)
276#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
277#define HCPOS_YSTART Fld(12,0)
278#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
279
280/* HCBADR Hardware Cursor Blend Address Register */
281#define HCBADR_GLALPHA Fld(8,24)
282#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
283#define HCBADR_COLKEY Fld(24,0)
284#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
285
286/* HCCKMSK - Hardware Cursor Color Key Mask Register */
287#define HCCKMSK_COLKEY_M Fld(24,0)
288#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
289
290/* DSCTRL - Display sync control register */
291#define DSCTRL_SYNCGEN_EN (1 << 31)
292#define DSCTRL_DPL_RST (1 << 29)
293#define DSCTRL_PWRDN_M (1 << 28)
294#define DSCTRL_UPDSYNCCNT (1 << 26)
295#define DSCTRL_UPDINTCNT (1 << 25)
296#define DSCTRL_UPDCNT (1 << 24)
297#define DSCTRL_UPDWAIT Fld(4,16)
298#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
299#define DSCTRL_CLKPOL (1 << 11)
300#define DSCTRL_CSYNC_EN (1 << 10)
301#define DSCTRL_VS_SLAVE (1 << 7)
302#define DSCTRL_HS_SLAVE (1 << 6)
303#define DSCTRL_BLNK_POL (1 << 5)
304#define DSCTRL_BLNK_DIS (1 << 4)
305#define DSCTRL_VS_POL (1 << 3)
306#define DSCTRL_VS_DIS (1 << 2)
307#define DSCTRL_HS_POL (1 << 1)
308#define DSCTRL_HS_DIS (1 << 0)
309
310/* DHT01 - Display horizontal timing register 01 */
311#define DHT01_HBPS Fld(12,16)
312#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
313#define DHT01_HT Fld(12,0)
314#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
315
316/* DHT02 - Display horizontal timing register 02 */
317#define DHT02_HAS Fld(12,16)
318#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
319#define DHT02_HLBS Fld(12,0)
320#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
321
322/* DHT03 - Display horizontal timing register 03 */
323#define DHT03_HFPS Fld(12,16)
324#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
325#define DHT03_HRBS Fld(12,0)
326#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
327
328/* DVT01 - Display vertical timing register 01 */
329#define DVT01_VBPS Fld(12,16)
330#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
331#define DVT01_VT Fld(12,0)
332#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
333
334/* DVT02 - Display vertical timing register 02 */
335#define DVT02_VAS Fld(12,16)
336#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
337#define DVT02_VTBS Fld(12,0)
338#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
339
340/* DVT03 - Display vertical timing register 03 */
341#define DVT03_VFPS Fld(12,16)
342#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
343#define DVT03_VBBS Fld(12,0)
344#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
345
346/* DVECTRL - display vertical event control register */
347#define DVECTRL_VEVENT Fld(12,16)
348#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
349#define DVECTRL_VFETCH Fld(12,0)
350#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
351
352/* DHDET - display horizontal DE timing register */
353#define DHDET_HDES Fld(12,16)
354#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
355#define DHDET_HDEF Fld(12,0)
356#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
357
358/* DVDET - display vertical DE timing register */
359#define DVDET_VDES Fld(12,16)
360#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
361#define DVDET_VDEF Fld(12,0)
362#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
363
364/* DODMSK - display output data mask register */
365#define DODMSK_MASK_LVL (1 << 31)
366#define DODMSK_BLNK_LVL (1 << 30)
367#define DODMSK_MASK_B Fld(8,16)
368#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
369#define DODMSK_MASK_G Fld(8,8)
370#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
371#define DODMSK_MASK_R Fld(8,0)
372#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
373
374/* DBCOL - display border color control register */
375#define DBCOL_BORDCOL Fld(24,0)
376#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
377
378/* DVLNUM - display vertical line number register */
379#define DVLNUM_VLINE Fld(12,0)
380#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
381
382/* DMCTRL - Display Memory Control Register */
383#define DMCTRL_MEM_REF Fld(2,30)
384#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
385#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
386#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
387#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
388#define DMCTRL_UV_THRHLD Fld(6,24)
389#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
390#define DMCTRL_V_THRHLD Fld(7,16)
391#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
392#define DMCTRL_D_THRHLD Fld(7,8)
393#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
394#define DMCTRL_BURSTLEN Fld(6,0)
395#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
396
397
398/* DLSTS - display load status register */
399#define DLSTS_RLD_ADONE (1 << 23)
400/* #define DLSTS_RLD_ADOUT Fld(23,0) */
401
402/* DLLCTRL - display list load control register */
403#define DLLCTRL_RLD_ADRLN Fld(8,24)
404#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
405
406/* SPOCTRL - Scale Pitch/Order Control Register */
407#define SPOCTRL_H_SC_BP (1 << 31)
408#define SPOCTRL_V_SC_BP (1 << 30)
409#define SPOCTRL_HV_SC_OR (1 << 29)
410#define SPOCTRL_VS_UR_C (1 << 27)
411#define SPOCTRL_VORDER Fld(2,16)
412#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
413#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
414#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
415#define SPOCTRL_VPITCH Fld(16,0)
416#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
417
418#endif /* __REG_BITS_2700G_ */