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-rw-r--r--drivers/video/fbdev/geode/Kconfig54
-rw-r--r--drivers/video/fbdev/geode/Makefile9
-rw-r--r--drivers/video/fbdev/geode/display_gx.c184
-rw-r--r--drivers/video/fbdev/geode/display_gx1.c214
-rw-r--r--drivers/video/fbdev/geode/display_gx1.h154
-rw-r--r--drivers/video/fbdev/geode/geodefb.h38
-rw-r--r--drivers/video/fbdev/geode/gx1fb_core.c476
-rw-r--r--drivers/video/fbdev/geode/gxfb.h358
-rw-r--r--drivers/video/fbdev/geode/gxfb_core.c547
-rw-r--r--drivers/video/fbdev/geode/lxfb.h452
-rw-r--r--drivers/video/fbdev/geode/lxfb_core.c683
-rw-r--r--drivers/video/fbdev/geode/lxfb_ops.c845
-rw-r--r--drivers/video/fbdev/geode/suspend_gx.c267
-rw-r--r--drivers/video/fbdev/geode/video_cs5530.c193
-rw-r--r--drivers/video/fbdev/geode/video_cs5530.h75
-rw-r--r--drivers/video/fbdev/geode/video_gx.c349
16 files changed, 4898 insertions, 0 deletions
diff --git a/drivers/video/fbdev/geode/Kconfig b/drivers/video/fbdev/geode/Kconfig
new file mode 100644
index 000000000000..1e8555284786
--- /dev/null
+++ b/drivers/video/fbdev/geode/Kconfig
@@ -0,0 +1,54 @@
1#
2# Geode family framebuffer configuration
3#
4config FB_GEODE
5 bool "AMD Geode family framebuffer support"
6 depends on FB && PCI && (X86_32 || (X86 && COMPILE_TEST))
7 ---help---
8 Say 'Y' here to allow you to select framebuffer drivers for
9 the AMD Geode family of processors.
10
11config FB_GEODE_LX
12 tristate "AMD Geode LX framebuffer support"
13 depends on FB && FB_GEODE
14 select FB_CFB_FILLRECT
15 select FB_CFB_COPYAREA
16 select FB_CFB_IMAGEBLIT
17 ---help---
18 Framebuffer driver for the display controller integrated into the
19 AMD Geode LX processors.
20
21 To compile this driver as a module, choose M here: the module will
22 be called lxfb.
23
24 If unsure, say N.
25
26config FB_GEODE_GX
27 tristate "AMD Geode GX framebuffer support"
28 depends on FB && FB_GEODE
29 select FB_CFB_FILLRECT
30 select FB_CFB_COPYAREA
31 select FB_CFB_IMAGEBLIT
32 ---help---
33 Framebuffer driver for the display controller integrated into the
34 AMD Geode GX processors.
35
36 To compile this driver as a module, choose M here: the module will be
37 called gxfb.
38
39 If unsure, say N.
40
41config FB_GEODE_GX1
42 tristate "AMD Geode GX1 framebuffer support"
43 depends on FB && FB_GEODE
44 select FB_CFB_FILLRECT
45 select FB_CFB_COPYAREA
46 select FB_CFB_IMAGEBLIT
47 ---help---
48 Framebuffer driver for the display controller integrated into the
49 AMD Geode GX1 processor.
50
51 To compile this driver as a module, choose M here: the module will be
52 called gx1fb.
53
54 If unsure, say N.
diff --git a/drivers/video/fbdev/geode/Makefile b/drivers/video/fbdev/geode/Makefile
new file mode 100644
index 000000000000..5c98da126883
--- /dev/null
+++ b/drivers/video/fbdev/geode/Makefile
@@ -0,0 +1,9 @@
1# Makefile for the Geode family framebuffer drivers
2
3obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
4obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
5obj-$(CONFIG_FB_GEODE_LX) += lxfb.o
6
7gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
8gxfb-objs := gxfb_core.o display_gx.o video_gx.o suspend_gx.o
9lxfb-objs := lxfb_core.o lxfb_ops.o
diff --git a/drivers/video/fbdev/geode/display_gx.c b/drivers/video/fbdev/geode/display_gx.c
new file mode 100644
index 000000000000..f0af911a096d
--- /dev/null
+++ b/drivers/video/fbdev/geode/display_gx.c
@@ -0,0 +1,184 @@
1/*
2 * Geode GX display controller.
3 *
4 * Copyright (C) 2005 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by * the
11 * Free Software Foundation; either version 2 of the License, or * (at your
12 * option) any later version.
13 */
14#include <linux/spinlock.h>
15#include <linux/fb.h>
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/div64.h>
19#include <asm/delay.h>
20#include <linux/cs5535.h>
21
22#include "gxfb.h"
23
24unsigned int gx_frame_buffer_size(void)
25{
26 unsigned int val;
27
28 if (!cs5535_has_vsa2()) {
29 uint32_t hi, lo;
30
31 /* The number of pages is (PMAX - PMIN)+1 */
32 rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
33
34 /* PMAX */
35 val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
36 /* PMIN */
37 val -= (lo & 0x000fffff);
38 val += 1;
39
40 /* The page size is 4k */
41 return (val << 12);
42 }
43
44 /* FB size can be obtained from the VSA II */
45 /* Virtual register class = 0x02 */
46 /* VG_MEM_SIZE(512Kb units) = 0x00 */
47
48 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
49 outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
50
51 val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl;
52 return (val << 19);
53}
54
55int gx_line_delta(int xres, int bpp)
56{
57 /* Must be a multiple of 8 bytes. */
58 return (xres * (bpp >> 3) + 7) & ~0x7;
59}
60
61void gx_set_mode(struct fb_info *info)
62{
63 struct gxfb_par *par = info->par;
64 u32 gcfg, dcfg;
65 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
66 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
67
68 /* Unlock the display controller registers. */
69 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
70
71 gcfg = read_dc(par, DC_GENERAL_CFG);
72 dcfg = read_dc(par, DC_DISPLAY_CFG);
73
74 /* Disable the timing generator. */
75 dcfg &= ~DC_DISPLAY_CFG_TGEN;
76 write_dc(par, DC_DISPLAY_CFG, dcfg);
77
78 /* Wait for pending memory requests before disabling the FIFO load. */
79 udelay(100);
80
81 /* Disable FIFO load and compression. */
82 gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
83 DC_GENERAL_CFG_DECE);
84 write_dc(par, DC_GENERAL_CFG, gcfg);
85
86 /* Setup DCLK and its divisor. */
87 gx_set_dclk_frequency(info);
88
89 /*
90 * Setup new mode.
91 */
92
93 /* Clear all unused feature bits. */
94 gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
95 dcfg = 0;
96
97 /* Set FIFO priority (default 6/5) and enable. */
98 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
99 gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
100 (5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
101
102 /* Framebuffer start offset. */
103 write_dc(par, DC_FB_ST_OFFSET, 0);
104
105 /* Line delta and line buffer length. */
106 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
107 write_dc(par, DC_LINE_SIZE,
108 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
109
110
111 /* Enable graphics and video data and unmask address lines. */
112 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
113 DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
114
115 /* Set pixel format. */
116 switch (info->var.bits_per_pixel) {
117 case 8:
118 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
119 break;
120 case 16:
121 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
122 break;
123 case 32:
124 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
125 dcfg |= DC_DISPLAY_CFG_PALB;
126 break;
127 }
128
129 /* Enable timing generator. */
130 dcfg |= DC_DISPLAY_CFG_TGEN;
131
132 /* Horizontal and vertical timings. */
133 hactive = info->var.xres;
134 hblankstart = hactive;
135 hsyncstart = hblankstart + info->var.right_margin;
136 hsyncend = hsyncstart + info->var.hsync_len;
137 hblankend = hsyncend + info->var.left_margin;
138 htotal = hblankend;
139
140 vactive = info->var.yres;
141 vblankstart = vactive;
142 vsyncstart = vblankstart + info->var.lower_margin;
143 vsyncend = vsyncstart + info->var.vsync_len;
144 vblankend = vsyncend + info->var.upper_margin;
145 vtotal = vblankend;
146
147 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
148 ((htotal - 1) << 16));
149 write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
150 ((hblankend - 1) << 16));
151 write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
152 ((hsyncend - 1) << 16));
153
154 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
155 ((vtotal - 1) << 16));
156 write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
157 ((vblankend - 1) << 16));
158 write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
159 ((vsyncend - 1) << 16));
160
161 /* Write final register values. */
162 write_dc(par, DC_DISPLAY_CFG, dcfg);
163 write_dc(par, DC_GENERAL_CFG, gcfg);
164
165 gx_configure_display(info);
166
167 /* Relock display controller registers */
168 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
169}
170
171void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
172 unsigned red, unsigned green, unsigned blue)
173{
174 struct gxfb_par *par = info->par;
175 int val;
176
177 /* Hardware palette is in RGB 8-8-8 format. */
178 val = (red << 8) & 0xff0000;
179 val |= (green) & 0x00ff00;
180 val |= (blue >> 8) & 0x0000ff;
181
182 write_dc(par, DC_PAL_ADDRESS, regno);
183 write_dc(par, DC_PAL_DATA, val);
184}
diff --git a/drivers/video/fbdev/geode/display_gx1.c b/drivers/video/fbdev/geode/display_gx1.c
new file mode 100644
index 000000000000..926d53eeb549
--- /dev/null
+++ b/drivers/video/fbdev/geode/display_gx1.c
@@ -0,0 +1,214 @@
1/*
2 * drivers/video/geode/display_gx1.c
3 * -- Geode GX1 display controller
4 *
5 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 *
7 * Based on AMD's original 2.4 driver:
8 * Copyright (C) 2004 Advanced Micro Devices, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15#include <linux/spinlock.h>
16#include <linux/fb.h>
17#include <linux/delay.h>
18#include <asm/io.h>
19#include <asm/div64.h>
20#include <asm/delay.h>
21
22#include "geodefb.h"
23#include "display_gx1.h"
24
25static DEFINE_SPINLOCK(gx1_conf_reg_lock);
26
27static u8 gx1_read_conf_reg(u8 reg)
28{
29 u8 val, ccr3;
30 unsigned long flags;
31
32 spin_lock_irqsave(&gx1_conf_reg_lock, flags);
33
34 outb(CONFIG_CCR3, 0x22);
35 ccr3 = inb(0x23);
36 outb(CONFIG_CCR3, 0x22);
37 outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23);
38 outb(reg, 0x22);
39 val = inb(0x23);
40 outb(CONFIG_CCR3, 0x22);
41 outb(ccr3, 0x23);
42
43 spin_unlock_irqrestore(&gx1_conf_reg_lock, flags);
44
45 return val;
46}
47
48unsigned gx1_gx_base(void)
49{
50 return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30;
51}
52
53int gx1_frame_buffer_size(void)
54{
55 void __iomem *mc_regs;
56 u32 bank_cfg;
57 int d;
58 unsigned dram_size = 0, fb_base;
59
60 mc_regs = ioremap(gx1_gx_base() + 0x8400, 0x100);
61 if (!mc_regs)
62 return -ENOMEM;
63
64
65 /* Calculate the total size of both DIMM0 and DIMM1. */
66 bank_cfg = readl(mc_regs + MC_BANK_CFG);
67
68 for (d = 0; d < 2; d++) {
69 if ((bank_cfg & MC_BCFG_DIMM0_PG_SZ_MASK) != MC_BCFG_DIMM0_PG_SZ_NO_DIMM)
70 dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8);
71 bank_cfg >>= 16; /* look at DIMM1 next */
72 }
73
74 fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
75
76 iounmap(mc_regs);
77
78 return dram_size - fb_base;
79}
80
81static void gx1_set_mode(struct fb_info *info)
82{
83 struct geodefb_par *par = info->par;
84 u32 gcfg, tcfg, ocfg, dclk_div, val;
85 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
86 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
87
88 /* Unlock the display controller registers. */
89 readl(par->dc_regs + DC_UNLOCK);
90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
91
92 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
93 tcfg = readl(par->dc_regs + DC_TIMING_CFG);
94
95 /* Blank the display and disable the timing generator. */
96 tcfg &= ~(DC_TCFG_BLKE | DC_TCFG_TGEN);
97 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
98
99 /* Wait for pending memory requests before disabling the FIFO load. */
100 udelay(100);
101
102 /* Disable FIFO load and compression. */
103 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
105
106 /* Setup DCLK and its divisor. */
107 gcfg &= ~DC_GCFG_DCLK_MASK;
108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
109
110 par->vid_ops->set_dclk(info);
111
112 dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */
113 gcfg |= dclk_div;
114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
115
116 /* Wait for the clock generatation to settle. This is needed since
117 * some of the register writes that follow require that clock to be
118 * present. */
119 udelay(1000); /* FIXME: seems a little long */
120
121 /*
122 * Setup new mode.
123 */
124
125 /* Clear all unused feature bits. */
126 gcfg = DC_GCFG_VRDY | dclk_div;
127
128 /* Set FIFO priority (default 6/5) and enable. */
129 /* FIXME: increase fifo priority for 1280x1024 modes? */
130 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
131
132 /* FIXME: Set pixel and line double bits if necessary. */
133
134 /* Framebuffer start offset. */
135 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
136
137 /* Line delta and line buffer length. */
138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
140 par->dc_regs + DC_BUF_SIZE);
141
142 /* Output configuration. Enable panel data, set pixel format. */
143 ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH;
144 if (info->var.bits_per_pixel == 8) ocfg |= DC_OCFG_8BPP;
145
146 /* Enable timing generator, sync and FP data. */
147 tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE
148 | DC_TCFG_TGEN;
149
150 /* Horizontal and vertical timings. */
151 hactive = info->var.xres;
152 hblankstart = hactive;
153 hsyncstart = hblankstart + info->var.right_margin;
154 hsyncend = hsyncstart + info->var.hsync_len;
155 hblankend = hsyncend + info->var.left_margin;
156 htotal = hblankend;
157
158 vactive = info->var.yres;
159 vblankstart = vactive;
160 vsyncstart = vblankstart + info->var.lower_margin;
161 vsyncend = vsyncstart + info->var.vsync_len;
162 vblankend = vsyncend + info->var.upper_margin;
163 vtotal = vblankend;
164
165 val = (hactive - 1) | ((htotal - 1) << 16);
166 writel(val, par->dc_regs + DC_H_TIMING_1);
167 val = (hblankstart - 1) | ((hblankend - 1) << 16);
168 writel(val, par->dc_regs + DC_H_TIMING_2);
169 val = (hsyncstart - 1) | ((hsyncend - 1) << 16);
170 writel(val, par->dc_regs + DC_H_TIMING_3);
171 writel(val, par->dc_regs + DC_FP_H_TIMING);
172 val = (vactive - 1) | ((vtotal - 1) << 16);
173 writel(val, par->dc_regs + DC_V_TIMING_1);
174 val = (vblankstart - 1) | ((vblankend - 1) << 16);
175 writel(val, par->dc_regs + DC_V_TIMING_2);
176 val = (vsyncstart - 1) | ((vsyncend - 1) << 16);
177 writel(val, par->dc_regs + DC_V_TIMING_3);
178 val = (vsyncstart - 2) | ((vsyncend - 2) << 16);
179 writel(val, par->dc_regs + DC_FP_V_TIMING);
180
181 /* Write final register values. */
182 writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
183 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
184 udelay(1000); /* delay after TIMING_CFG. FIXME: perhaps a little long */
185 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
186
187 par->vid_ops->configure_display(info);
188
189 /* Relock display controller registers */
190 writel(0, par->dc_regs + DC_UNLOCK);
191
192 /* FIXME: write line_length and bpp to Graphics Pipeline GP_BLT_STATUS
193 * register. */
194}
195
196static void gx1_set_hw_palette_reg(struct fb_info *info, unsigned regno,
197 unsigned red, unsigned green, unsigned blue)
198{
199 struct geodefb_par *par = info->par;
200 int val;
201
202 /* Hardware palette is in RGB 6-6-6 format. */
203 val = (red << 2) & 0x3f000;
204 val |= (green >> 4) & 0x00fc0;
205 val |= (blue >> 10) & 0x0003f;
206
207 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
208 writel(val, par->dc_regs + DC_PAL_DATA);
209}
210
211struct geode_dc_ops gx1_dc_ops = {
212 .set_mode = gx1_set_mode,
213 .set_palette_reg = gx1_set_hw_palette_reg,
214};
diff --git a/drivers/video/fbdev/geode/display_gx1.h b/drivers/video/fbdev/geode/display_gx1.h
new file mode 100644
index 000000000000..671c05558c79
--- /dev/null
+++ b/drivers/video/fbdev/geode/display_gx1.h
@@ -0,0 +1,154 @@
1/*
2 * drivers/video/geode/display_gx1.h
3 * -- Geode GX1 display controller
4 *
5 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 *
7 * Based on AMD's original 2.4 driver:
8 * Copyright (C) 2004 Advanced Micro Devices, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15#ifndef __DISPLAY_GX1_H__
16#define __DISPLAY_GX1_H__
17
18unsigned gx1_gx_base(void);
19int gx1_frame_buffer_size(void);
20
21extern struct geode_dc_ops gx1_dc_ops;
22
23/* GX1 configuration I/O registers */
24
25#define CONFIG_CCR3 0xc3
26# define CONFIG_CCR3_MAPEN 0x10
27#define CONFIG_GCR 0xb8
28
29/* Memory controller registers */
30
31#define MC_BANK_CFG 0x08
32# define MC_BCFG_DIMM0_SZ_MASK 0x00000700
33# define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
34# define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
35
36#define MC_GBASE_ADD 0x14
37# define MC_GADD_GBADD_MASK 0x000003ff
38
39/* Display controller registers */
40
41#define DC_PAL_ADDRESS 0x70
42#define DC_PAL_DATA 0x74
43
44#define DC_UNLOCK 0x00
45# define DC_UNLOCK_CODE 0x00004758
46
47#define DC_GENERAL_CFG 0x04
48# define DC_GCFG_DFLE 0x00000001
49# define DC_GCFG_CURE 0x00000002
50# define DC_GCFG_VCLK_DIV 0x00000004
51# define DC_GCFG_PLNO 0x00000004
52# define DC_GCFG_PPC 0x00000008
53# define DC_GCFG_CMPE 0x00000010
54# define DC_GCFG_DECE 0x00000020
55# define DC_GCFG_DCLK_MASK 0x000000C0
56# define DC_GCFG_DCLK_DIV_1 0x00000080
57# define DC_GCFG_DFHPSL_MASK 0x00000F00
58# define DC_GCFG_DFHPSL_POS 8
59# define DC_GCFG_DFHPEL_MASK 0x0000F000
60# define DC_GCFG_DFHPEL_POS 12
61# define DC_GCFG_CIM_MASK 0x00030000
62# define DC_GCFG_CIM_POS 16
63# define DC_GCFG_FDTY 0x00040000
64# define DC_GCFG_RTPM 0x00080000
65# define DC_GCFG_DAC_RS_MASK 0x00700000
66# define DC_GCFG_DAC_RS_POS 20
67# define DC_GCFG_CKWR 0x00800000
68# define DC_GCFG_LDBL 0x01000000
69# define DC_GCFG_DIAG 0x02000000
70# define DC_GCFG_CH4S 0x04000000
71# define DC_GCFG_SSLC 0x08000000
72# define DC_GCFG_VIDE 0x10000000
73# define DC_GCFG_VRDY 0x20000000
74# define DC_GCFG_DPCK 0x40000000
75# define DC_GCFG_DDCK 0x80000000
76
77#define DC_TIMING_CFG 0x08
78# define DC_TCFG_FPPE 0x00000001
79# define DC_TCFG_HSYE 0x00000002
80# define DC_TCFG_VSYE 0x00000004
81# define DC_TCFG_BLKE 0x00000008
82# define DC_TCFG_DDCK 0x00000010
83# define DC_TCFG_TGEN 0x00000020
84# define DC_TCFG_VIEN 0x00000040
85# define DC_TCFG_BLNK 0x00000080
86# define DC_TCFG_CHSP 0x00000100
87# define DC_TCFG_CVSP 0x00000200
88# define DC_TCFG_FHSP 0x00000400
89# define DC_TCFG_FVSP 0x00000800
90# define DC_TCFG_FCEN 0x00001000
91# define DC_TCFG_CDCE 0x00002000
92# define DC_TCFG_PLNR 0x00002000
93# define DC_TCFG_INTL 0x00004000
94# define DC_TCFG_PXDB 0x00008000
95# define DC_TCFG_BKRT 0x00010000
96# define DC_TCFG_PSD_MASK 0x000E0000
97# define DC_TCFG_PSD_POS 17
98# define DC_TCFG_DDCI 0x08000000
99# define DC_TCFG_SENS 0x10000000
100# define DC_TCFG_DNA 0x20000000
101# define DC_TCFG_VNA 0x40000000
102# define DC_TCFG_VINT 0x80000000
103
104#define DC_OUTPUT_CFG 0x0C
105# define DC_OCFG_8BPP 0x00000001
106# define DC_OCFG_555 0x00000002
107# define DC_OCFG_PCKE 0x00000004
108# define DC_OCFG_FRME 0x00000008
109# define DC_OCFG_DITE 0x00000010
110# define DC_OCFG_2PXE 0x00000020
111# define DC_OCFG_2XCK 0x00000040
112# define DC_OCFG_2IND 0x00000080
113# define DC_OCFG_34ADD 0x00000100
114# define DC_OCFG_FRMS 0x00000200
115# define DC_OCFG_CKSL 0x00000400
116# define DC_OCFG_PRMP 0x00000800
117# define DC_OCFG_PDEL 0x00001000
118# define DC_OCFG_PDEH 0x00002000
119# define DC_OCFG_CFRW 0x00004000
120# define DC_OCFG_DIAG 0x00008000
121
122#define DC_FB_ST_OFFSET 0x10
123#define DC_CB_ST_OFFSET 0x14
124#define DC_CURS_ST_OFFSET 0x18
125#define DC_ICON_ST_OFFSET 0x1C
126#define DC_VID_ST_OFFSET 0x20
127#define DC_LINE_DELTA 0x24
128#define DC_BUF_SIZE 0x28
129
130#define DC_H_TIMING_1 0x30
131#define DC_H_TIMING_2 0x34
132#define DC_H_TIMING_3 0x38
133#define DC_FP_H_TIMING 0x3C
134
135#define DC_V_TIMING_1 0x40
136#define DC_V_TIMING_2 0x44
137#define DC_V_TIMING_3 0x48
138#define DC_FP_V_TIMING 0x4C
139
140#define DC_CURSOR_X 0x50
141#define DC_ICON_X 0x54
142#define DC_V_LINE_CNT 0x54
143#define DC_CURSOR_Y 0x58
144#define DC_ICON_Y 0x5C
145#define DC_SS_LINE_CMP 0x5C
146#define DC_CURSOR_COLOR 0x60
147#define DC_ICON_COLOR 0x64
148#define DC_BORDER_COLOR 0x68
149#define DC_PAL_ADDRESS 0x70
150#define DC_PAL_DATA 0x74
151#define DC_DFIFO_DIAG 0x78
152#define DC_CFIFO_DIAG 0x7C
153
154#endif /* !__DISPLAY_GX1_H__ */
diff --git a/drivers/video/fbdev/geode/geodefb.h b/drivers/video/fbdev/geode/geodefb.h
new file mode 100644
index 000000000000..ae04820e0c57
--- /dev/null
+++ b/drivers/video/fbdev/geode/geodefb.h
@@ -0,0 +1,38 @@
1/*
2 * drivers/video/geode/geodefb.h
3 * -- Geode framebuffer driver
4 *
5 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#ifndef __GEODEFB_H__
13#define __GEODEFB_H__
14
15struct geodefb_info;
16
17struct geode_dc_ops {
18 void (*set_mode)(struct fb_info *);
19 void (*set_palette_reg)(struct fb_info *, unsigned, unsigned, unsigned, unsigned);
20};
21
22struct geode_vid_ops {
23 void (*set_dclk)(struct fb_info *);
24 void (*configure_display)(struct fb_info *);
25 int (*blank_display)(struct fb_info *, int blank_mode);
26};
27
28struct geodefb_par {
29 int enable_crt;
30 int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */
31 int panel_y;
32 void __iomem *dc_regs;
33 void __iomem *vid_regs;
34 struct geode_dc_ops *dc_ops;
35 struct geode_vid_ops *vid_ops;
36};
37
38#endif /* !__GEODEFB_H__ */
diff --git a/drivers/video/fbdev/geode/gx1fb_core.c b/drivers/video/fbdev/geode/gx1fb_core.c
new file mode 100644
index 000000000000..2794ba11f332
--- /dev/null
+++ b/drivers/video/fbdev/geode/gx1fb_core.c
@@ -0,0 +1,476 @@
1/*
2 * drivers/video/geode/gx1fb_core.c
3 * -- Geode GX1 framebuffer driver
4 *
5 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/mm.h>
18#include <linux/delay.h>
19#include <linux/fb.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22
23#include "geodefb.h"
24#include "display_gx1.h"
25#include "video_cs5530.h"
26
27static char mode_option[32] = "640x480-16@60";
28static int crt_option = 1;
29static char panel_option[32] = "";
30
31/* Modes relevant to the GX1 (taken from modedb.c) */
32static const struct fb_videomode gx1_modedb[] = {
33 /* 640x480-60 VESA */
34 { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
35 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
36 /* 640x480-75 VESA */
37 { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
38 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
39 /* 640x480-85 VESA */
40 { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
41 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
42 /* 800x600-60 VESA */
43 { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
44 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
45 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
46 /* 800x600-75 VESA */
47 { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
48 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
49 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
50 /* 800x600-85 VESA */
51 { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
52 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
53 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
54 /* 1024x768-60 VESA */
55 { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
56 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
57 /* 1024x768-75 VESA */
58 { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
59 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
60 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
61 /* 1024x768-85 VESA */
62 { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
63 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
64 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
65 /* 1280x960-60 VESA */
66 { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
67 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
68 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
69 /* 1280x960-85 VESA */
70 { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
71 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
72 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
73 /* 1280x1024-60 VESA */
74 { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
75 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
76 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
77 /* 1280x1024-75 VESA */
78 { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
79 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
80 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
81 /* 1280x1024-85 VESA */
82 { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
83 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
84 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
85};
86
87static int gx1_line_delta(int xres, int bpp)
88{
89 int line_delta = xres * (bpp >> 3);
90
91 if (line_delta > 2048)
92 line_delta = 4096;
93 else if (line_delta > 1024)
94 line_delta = 2048;
95 else
96 line_delta = 1024;
97 return line_delta;
98}
99
100static int gx1fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
101{
102 struct geodefb_par *par = info->par;
103
104 /* Maximum resolution is 1280x1024. */
105 if (var->xres > 1280 || var->yres > 1024)
106 return -EINVAL;
107
108 if (par->panel_x && (var->xres > par->panel_x || var->yres > par->panel_y))
109 return -EINVAL;
110
111 /* Only 16 bpp and 8 bpp is supported by the hardware. */
112 if (var->bits_per_pixel == 16) {
113 var->red.offset = 11; var->red.length = 5;
114 var->green.offset = 5; var->green.length = 6;
115 var->blue.offset = 0; var->blue.length = 5;
116 var->transp.offset = 0; var->transp.length = 0;
117 } else if (var->bits_per_pixel == 8) {
118 var->red.offset = 0; var->red.length = 8;
119 var->green.offset = 0; var->green.length = 8;
120 var->blue.offset = 0; var->blue.length = 8;
121 var->transp.offset = 0; var->transp.length = 0;
122 } else
123 return -EINVAL;
124
125 /* Enough video memory? */
126 if (gx1_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
127 return -EINVAL;
128
129 /* FIXME: Check timing parameters here? */
130
131 return 0;
132}
133
134static int gx1fb_set_par(struct fb_info *info)
135{
136 struct geodefb_par *par = info->par;
137
138 if (info->var.bits_per_pixel == 16)
139 info->fix.visual = FB_VISUAL_TRUECOLOR;
140 else
141 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
142
143 info->fix.line_length = gx1_line_delta(info->var.xres, info->var.bits_per_pixel);
144
145 par->dc_ops->set_mode(info);
146
147 return 0;
148}
149
150static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
151{
152 chan &= 0xffff;
153 chan >>= 16 - bf->length;
154 return chan << bf->offset;
155}
156
157static int gx1fb_setcolreg(unsigned regno, unsigned red, unsigned green,
158 unsigned blue, unsigned transp,
159 struct fb_info *info)
160{
161 struct geodefb_par *par = info->par;
162
163 if (info->var.grayscale) {
164 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
165 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
166 }
167
168 /* Truecolor has hardware independent palette */
169 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
170 u32 *pal = info->pseudo_palette;
171 u32 v;
172
173 if (regno >= 16)
174 return -EINVAL;
175
176 v = chan_to_field(red, &info->var.red);
177 v |= chan_to_field(green, &info->var.green);
178 v |= chan_to_field(blue, &info->var.blue);
179
180 pal[regno] = v;
181 } else {
182 if (regno >= 256)
183 return -EINVAL;
184
185 par->dc_ops->set_palette_reg(info, regno, red, green, blue);
186 }
187
188 return 0;
189}
190
191static int gx1fb_blank(int blank_mode, struct fb_info *info)
192{
193 struct geodefb_par *par = info->par;
194
195 return par->vid_ops->blank_display(info, blank_mode);
196}
197
198static int gx1fb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
199{
200 struct geodefb_par *par = info->par;
201 unsigned gx_base;
202 int fb_len;
203 int ret;
204
205 gx_base = gx1_gx_base();
206 if (!gx_base)
207 return -ENODEV;
208
209 ret = pci_enable_device(dev);
210 if (ret < 0)
211 return ret;
212
213 ret = pci_request_region(dev, 0, "gx1fb (video)");
214 if (ret < 0)
215 return ret;
216 par->vid_regs = pci_ioremap_bar(dev, 0);
217 if (!par->vid_regs)
218 return -ENOMEM;
219
220 if (!request_mem_region(gx_base + 0x8300, 0x100, "gx1fb (display controller)"))
221 return -EBUSY;
222 par->dc_regs = ioremap(gx_base + 0x8300, 0x100);
223 if (!par->dc_regs)
224 return -ENOMEM;
225
226 if ((fb_len = gx1_frame_buffer_size()) < 0)
227 return -ENOMEM;
228 info->fix.smem_start = gx_base + 0x800000;
229 info->fix.smem_len = fb_len;
230 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
231 if (!info->screen_base)
232 return -ENOMEM;
233
234 dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
235 info->fix.smem_len / 1024, info->fix.smem_start);
236
237 return 0;
238}
239
240static int parse_panel_option(struct fb_info *info)
241{
242 struct geodefb_par *par = info->par;
243
244 if (strcmp(panel_option, "") != 0) {
245 int x, y;
246 char *s;
247 x = simple_strtol(panel_option, &s, 10);
248 if (!x)
249 return -EINVAL;
250 y = simple_strtol(s + 1, NULL, 10);
251 if (!y)
252 return -EINVAL;
253 par->panel_x = x;
254 par->panel_y = y;
255 }
256 return 0;
257}
258
259static struct fb_ops gx1fb_ops = {
260 .owner = THIS_MODULE,
261 .fb_check_var = gx1fb_check_var,
262 .fb_set_par = gx1fb_set_par,
263 .fb_setcolreg = gx1fb_setcolreg,
264 .fb_blank = gx1fb_blank,
265 /* No HW acceleration for now. */
266 .fb_fillrect = cfb_fillrect,
267 .fb_copyarea = cfb_copyarea,
268 .fb_imageblit = cfb_imageblit,
269};
270
271static struct fb_info *gx1fb_init_fbinfo(struct device *dev)
272{
273 struct geodefb_par *par;
274 struct fb_info *info;
275
276 /* Alloc enough space for the pseudo palette. */
277 info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
278 if (!info)
279 return NULL;
280
281 par = info->par;
282
283 strcpy(info->fix.id, "GX1");
284
285 info->fix.type = FB_TYPE_PACKED_PIXELS;
286 info->fix.type_aux = 0;
287 info->fix.xpanstep = 0;
288 info->fix.ypanstep = 0;
289 info->fix.ywrapstep = 0;
290 info->fix.accel = FB_ACCEL_NONE;
291
292 info->var.nonstd = 0;
293 info->var.activate = FB_ACTIVATE_NOW;
294 info->var.height = -1;
295 info->var.width = -1;
296 info->var.accel_flags = 0;
297 info->var.vmode = FB_VMODE_NONINTERLACED;
298
299 info->fbops = &gx1fb_ops;
300 info->flags = FBINFO_DEFAULT;
301 info->node = -1;
302
303 info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
304
305 info->var.grayscale = 0;
306
307 /* CRT and panel options */
308 par->enable_crt = crt_option;
309 if (parse_panel_option(info) < 0)
310 printk(KERN_WARNING "gx1fb: invalid 'panel' option -- disabling flat panel\n");
311 if (!par->panel_x)
312 par->enable_crt = 1; /* fall back to CRT if no panel is specified */
313
314 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
315 framebuffer_release(info);
316 return NULL;
317 }
318 return info;
319}
320
321static int gx1fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
322{
323 struct geodefb_par *par;
324 struct fb_info *info;
325 int ret;
326
327 info = gx1fb_init_fbinfo(&pdev->dev);
328 if (!info)
329 return -ENOMEM;
330 par = info->par;
331
332 /* GX1 display controller and CS5530 video device */
333 par->dc_ops = &gx1_dc_ops;
334 par->vid_ops = &cs5530_vid_ops;
335
336 if ((ret = gx1fb_map_video_memory(info, pdev)) < 0) {
337 dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
338 goto err;
339 }
340
341 ret = fb_find_mode(&info->var, info, mode_option,
342 gx1_modedb, ARRAY_SIZE(gx1_modedb), NULL, 16);
343 if (ret == 0 || ret == 4) {
344 dev_err(&pdev->dev, "could not find valid video mode\n");
345 ret = -EINVAL;
346 goto err;
347 }
348
349 /* Clear the frame buffer of garbage. */
350 memset_io(info->screen_base, 0, info->fix.smem_len);
351
352 gx1fb_check_var(&info->var, info);
353 gx1fb_set_par(info);
354
355 if (register_framebuffer(info) < 0) {
356 ret = -EINVAL;
357 goto err;
358 }
359 pci_set_drvdata(pdev, info);
360 fb_info(info, "%s frame buffer device\n", info->fix.id);
361 return 0;
362
363 err:
364 if (info->screen_base) {
365 iounmap(info->screen_base);
366 pci_release_region(pdev, 0);
367 }
368 if (par->vid_regs) {
369 iounmap(par->vid_regs);
370 pci_release_region(pdev, 1);
371 }
372 if (par->dc_regs) {
373 iounmap(par->dc_regs);
374 release_mem_region(gx1_gx_base() + 0x8300, 0x100);
375 }
376
377 if (info) {
378 fb_dealloc_cmap(&info->cmap);
379 framebuffer_release(info);
380 }
381
382 return ret;
383}
384
385static void gx1fb_remove(struct pci_dev *pdev)
386{
387 struct fb_info *info = pci_get_drvdata(pdev);
388 struct geodefb_par *par = info->par;
389
390 unregister_framebuffer(info);
391
392 iounmap((void __iomem *)info->screen_base);
393 pci_release_region(pdev, 0);
394
395 iounmap(par->vid_regs);
396 pci_release_region(pdev, 1);
397
398 iounmap(par->dc_regs);
399 release_mem_region(gx1_gx_base() + 0x8300, 0x100);
400
401 fb_dealloc_cmap(&info->cmap);
402
403 framebuffer_release(info);
404}
405
406#ifndef MODULE
407static void __init gx1fb_setup(char *options)
408{
409 char *this_opt;
410
411 if (!options || !*options)
412 return;
413
414 while ((this_opt = strsep(&options, ","))) {
415 if (!*this_opt)
416 continue;
417
418 if (!strncmp(this_opt, "mode:", 5))
419 strlcpy(mode_option, this_opt + 5, sizeof(mode_option));
420 else if (!strncmp(this_opt, "crt:", 4))
421 crt_option = !!simple_strtoul(this_opt + 4, NULL, 0);
422 else if (!strncmp(this_opt, "panel:", 6))
423 strlcpy(panel_option, this_opt + 6, sizeof(panel_option));
424 else
425 strlcpy(mode_option, this_opt, sizeof(mode_option));
426 }
427}
428#endif
429
430static struct pci_device_id gx1fb_id_table[] = {
431 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_VIDEO,
432 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
433 0xff0000, 0 },
434 { 0, }
435};
436
437MODULE_DEVICE_TABLE(pci, gx1fb_id_table);
438
439static struct pci_driver gx1fb_driver = {
440 .name = "gx1fb",
441 .id_table = gx1fb_id_table,
442 .probe = gx1fb_probe,
443 .remove = gx1fb_remove,
444};
445
446static int __init gx1fb_init(void)
447{
448#ifndef MODULE
449 char *option = NULL;
450
451 if (fb_get_options("gx1fb", &option))
452 return -ENODEV;
453 gx1fb_setup(option);
454#endif
455 return pci_register_driver(&gx1fb_driver);
456}
457
458static void gx1fb_cleanup(void)
459{
460 pci_unregister_driver(&gx1fb_driver);
461}
462
463module_init(gx1fb_init);
464module_exit(gx1fb_cleanup);
465
466module_param_string(mode, mode_option, sizeof(mode_option), 0444);
467MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
468
469module_param_named(crt, crt_option, int, 0444);
470MODULE_PARM_DESC(crt, "enable CRT output. 0 = off, 1 = on (default)");
471
472module_param_string(panel, panel_option, sizeof(panel_option), 0444);
473MODULE_PARM_DESC(panel, "size of attached flat panel (<x>x<y>)");
474
475MODULE_DESCRIPTION("framebuffer driver for the AMD Geode GX1");
476MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/geode/gxfb.h b/drivers/video/fbdev/geode/gxfb.h
new file mode 100644
index 000000000000..d19e9378b0c0
--- /dev/null
+++ b/drivers/video/fbdev/geode/gxfb.h
@@ -0,0 +1,358 @@
1/*
2 * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
3 *
4 * Geode GX2 header information
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef _GXFB_H_
12#define _GXFB_H_
13
14#include <linux/io.h>
15
16#define GP_REG_COUNT (0x50 / 4)
17#define DC_REG_COUNT (0x90 / 4)
18#define VP_REG_COUNT (0x138 / 8)
19#define FP_REG_COUNT (0x68 / 8)
20
21#define DC_PAL_COUNT 0x104
22
23struct gxfb_par {
24 int enable_crt;
25 void __iomem *dc_regs;
26 void __iomem *vid_regs;
27 void __iomem *gp_regs;
28#ifdef CONFIG_PM
29 int powered_down;
30
31 /* register state, for power management functionality */
32 struct {
33 uint64_t padsel;
34 uint64_t dotpll;
35 } msr;
36
37 uint32_t gp[GP_REG_COUNT];
38 uint32_t dc[DC_REG_COUNT];
39 uint64_t vp[VP_REG_COUNT];
40 uint64_t fp[FP_REG_COUNT];
41
42 uint32_t pal[DC_PAL_COUNT];
43#endif
44};
45
46unsigned int gx_frame_buffer_size(void);
47int gx_line_delta(int xres, int bpp);
48void gx_set_mode(struct fb_info *info);
49void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
50 unsigned red, unsigned green, unsigned blue);
51
52void gx_set_dclk_frequency(struct fb_info *info);
53void gx_configure_display(struct fb_info *info);
54int gx_blank_display(struct fb_info *info, int blank_mode);
55
56#ifdef CONFIG_PM
57int gx_powerdown(struct fb_info *info);
58int gx_powerup(struct fb_info *info);
59#endif
60
61
62/* Graphics Processor registers (table 6-23 from the data book) */
63enum gp_registers {
64 GP_DST_OFFSET = 0,
65 GP_SRC_OFFSET,
66 GP_STRIDE,
67 GP_WID_HEIGHT,
68
69 GP_SRC_COLOR_FG,
70 GP_SRC_COLOR_BG,
71 GP_PAT_COLOR_0,
72 GP_PAT_COLOR_1,
73
74 GP_PAT_COLOR_2,
75 GP_PAT_COLOR_3,
76 GP_PAT_COLOR_4,
77 GP_PAT_COLOR_5,
78
79 GP_PAT_DATA_0,
80 GP_PAT_DATA_1,
81 GP_RASTER_MODE,
82 GP_VECTOR_MODE,
83
84 GP_BLT_MODE,
85 GP_BLT_STATUS,
86 GP_HST_SRC,
87 GP_BASE_OFFSET, /* 0x4c */
88};
89
90#define GP_BLT_STATUS_BLT_PENDING (1 << 2)
91#define GP_BLT_STATUS_BLT_BUSY (1 << 0)
92
93
94/* Display Controller registers (table 6-38 from the data book) */
95enum dc_registers {
96 DC_UNLOCK = 0,
97 DC_GENERAL_CFG,
98 DC_DISPLAY_CFG,
99 DC_RSVD_0,
100
101 DC_FB_ST_OFFSET,
102 DC_CB_ST_OFFSET,
103 DC_CURS_ST_OFFSET,
104 DC_ICON_ST_OFFSET,
105
106 DC_VID_Y_ST_OFFSET,
107 DC_VID_U_ST_OFFSET,
108 DC_VID_V_ST_OFFSET,
109 DC_RSVD_1,
110
111 DC_LINE_SIZE,
112 DC_GFX_PITCH,
113 DC_VID_YUV_PITCH,
114 DC_RSVD_2,
115
116 DC_H_ACTIVE_TIMING,
117 DC_H_BLANK_TIMING,
118 DC_H_SYNC_TIMING,
119 DC_RSVD_3,
120
121 DC_V_ACTIVE_TIMING,
122 DC_V_BLANK_TIMING,
123 DC_V_SYNC_TIMING,
124 DC_RSVD_4,
125
126 DC_CURSOR_X,
127 DC_CURSOR_Y,
128 DC_ICON_X,
129 DC_LINE_CNT,
130
131 DC_PAL_ADDRESS,
132 DC_PAL_DATA,
133 DC_DFIFO_DIAG,
134 DC_CFIFO_DIAG,
135
136 DC_VID_DS_DELTA,
137 DC_GLIU0_MEM_OFFSET,
138 DC_RSVD_5,
139 DC_DV_ACC, /* 0x8c */
140};
141
142#define DC_UNLOCK_LOCK 0x00000000
143#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
144
145#define DC_GENERAL_CFG_YUVM (1 << 20)
146#define DC_GENERAL_CFG_VDSE (1 << 19)
147#define DC_GENERAL_CFG_DFHPEL_SHIFT 12
148#define DC_GENERAL_CFG_DFHPSL_SHIFT 8
149#define DC_GENERAL_CFG_DECE (1 << 6)
150#define DC_GENERAL_CFG_CMPE (1 << 5)
151#define DC_GENERAL_CFG_VIDE (1 << 3)
152#define DC_GENERAL_CFG_ICNE (1 << 2)
153#define DC_GENERAL_CFG_CURE (1 << 1)
154#define DC_GENERAL_CFG_DFLE (1 << 0)
155
156#define DC_DISPLAY_CFG_A20M (1 << 31)
157#define DC_DISPLAY_CFG_A18M (1 << 30)
158#define DC_DISPLAY_CFG_PALB (1 << 25)
159#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
160#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
161#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
162#define DC_DISPLAY_CFG_VDEN (1 << 4)
163#define DC_DISPLAY_CFG_GDEN (1 << 3)
164#define DC_DISPLAY_CFG_TGEN (1 << 0)
165
166
167/*
168 * Video Processor registers (table 6-54).
169 * There is space for 64 bit values, but we never use more than the
170 * lower 32 bits. The actual register save/restore code only bothers
171 * to restore those 32 bits.
172 */
173enum vp_registers {
174 VP_VCFG = 0,
175 VP_DCFG,
176
177 VP_VX,
178 VP_VY,
179
180 VP_VS,
181 VP_VCK,
182
183 VP_VCM,
184 VP_GAR,
185
186 VP_GDR,
187 VP_RSVD_0,
188
189 VP_MISC,
190 VP_CCS,
191
192 VP_RSVD_1,
193 VP_RSVD_2,
194
195 VP_RSVD_3,
196 VP_VDC,
197
198 VP_VCO,
199 VP_CRC,
200
201 VP_CRC32,
202 VP_VDE,
203
204 VP_CCK,
205 VP_CCM,
206
207 VP_CC1,
208 VP_CC2,
209
210 VP_A1X,
211 VP_A1Y,
212
213 VP_A1C,
214 VP_A1T,
215
216 VP_A2X,
217 VP_A2Y,
218
219 VP_A2C,
220 VP_A2T,
221
222 VP_A3X,
223 VP_A3Y,
224
225 VP_A3C,
226 VP_A3T,
227
228 VP_VRR,
229 VP_AWT,
230
231 VP_VTM, /* 0x130 */
232};
233
234#define VP_VCFG_VID_EN (1 << 0)
235
236#define VP_DCFG_DAC_VREF (1 << 26)
237#define VP_DCFG_GV_GAM (1 << 21)
238#define VP_DCFG_VG_CK (1 << 20)
239#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
240#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
241#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
242#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
243#define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */
244#define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */
245#define VP_DCFG_DAC_BL_EN (1 << 3)
246#define VP_DCFG_VSYNC_EN (1 << 2)
247#define VP_DCFG_HSYNC_EN (1 << 1)
248#define VP_DCFG_CRT_EN (1 << 0)
249
250#define VP_MISC_GAM_EN (1 << 0)
251#define VP_MISC_DACPWRDN (1 << 10)
252#define VP_MISC_APWRDN (1 << 11)
253
254
255/*
256 * Flat Panel registers (table 6-55).
257 * Also 64 bit registers; see above note about 32-bit handling.
258 */
259
260/* we're actually in the VP register space, starting at address 0x400 */
261#define VP_FP_START 0x400
262
263enum fp_registers {
264 FP_PT1 = 0,
265 FP_PT2,
266
267 FP_PM,
268 FP_DFC,
269
270 FP_BLFSR,
271 FP_RLFSR,
272
273 FP_FMI,
274 FP_FMD,
275
276 FP_RSVD_0,
277 FP_DCA,
278
279 FP_DMD,
280 FP_CRC,
281
282 FP_FBB, /* 0x460 */
283};
284
285#define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */
286#define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */
287
288#define FP_PT2_HSP (1 << 22)
289#define FP_PT2_VSP (1 << 23)
290
291#define FP_PM_P (1 << 24) /* panel power on */
292#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
293#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
294#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
295#define FP_PM_PANEL_ON (1 << 0) /* r/o */
296
297#define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6))
298
299
300/* register access functions */
301
302static inline uint32_t read_gp(struct gxfb_par *par, int reg)
303{
304 return readl(par->gp_regs + 4*reg);
305}
306
307static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val)
308{
309 writel(val, par->gp_regs + 4*reg);
310}
311
312static inline uint32_t read_dc(struct gxfb_par *par, int reg)
313{
314 return readl(par->dc_regs + 4*reg);
315}
316
317static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val)
318{
319 writel(val, par->dc_regs + 4*reg);
320}
321
322static inline uint32_t read_vp(struct gxfb_par *par, int reg)
323{
324 return readl(par->vid_regs + 8*reg);
325}
326
327static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val)
328{
329 writel(val, par->vid_regs + 8*reg);
330}
331
332static inline uint32_t read_fp(struct gxfb_par *par, int reg)
333{
334 return readl(par->vid_regs + 8*reg + VP_FP_START);
335}
336
337static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val)
338{
339 writel(val, par->vid_regs + 8*reg + VP_FP_START);
340}
341
342
343/* MSRs are defined in linux/cs5535.h; their bitfields are here */
344
345#define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3)
346#define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2)
347#define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (1 << 1)
348
349#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
350#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
351#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
352
353#define MSR_GX_MSR_PADSEL_MASK 0x3FFFFFFF /* undocumented? */
354#define MSR_GX_MSR_PADSEL_TFT 0x1FFFFFFF /* undocumented? */
355
356#define MSR_GX_GLD_MSR_CONFIG_FP (1 << 3)
357
358#endif
diff --git a/drivers/video/fbdev/geode/gxfb_core.c b/drivers/video/fbdev/geode/gxfb_core.c
new file mode 100644
index 000000000000..1790f14bab15
--- /dev/null
+++ b/drivers/video/fbdev/geode/gxfb_core.c
@@ -0,0 +1,547 @@
1/*
2 * Geode GX framebuffer driver.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 *
12 * This driver assumes that the BIOS has created a virtual PCI device header
13 * for the video device. The PCI header is assumed to contain the following
14 * BARs:
15 *
16 * BAR0 - framebuffer memory
17 * BAR1 - graphics processor registers
18 * BAR2 - display controller registers
19 * BAR3 - video processor and flat panel control registers.
20 *
21 * 16 MiB of framebuffer memory is assumed to be available.
22 */
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/errno.h>
26#include <linux/string.h>
27#include <linux/mm.h>
28#include <linux/delay.h>
29#include <linux/fb.h>
30#include <linux/console.h>
31#include <linux/suspend.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/cs5535.h>
35
36#include "gxfb.h"
37
38static char *mode_option;
39static int vram;
40static int vt_switch;
41
42/* Modes relevant to the GX (taken from modedb.c) */
43static struct fb_videomode gx_modedb[] = {
44 /* 640x480-60 VESA */
45 { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
46 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
47 /* 640x480-75 VESA */
48 { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
49 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
50 /* 640x480-85 VESA */
51 { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
52 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
53 /* 800x600-60 VESA */
54 { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
55 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
56 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
57 /* 800x600-75 VESA */
58 { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
59 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
60 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
61 /* 800x600-85 VESA */
62 { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
63 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
64 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
65 /* 1024x768-60 VESA */
66 { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
67 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
68 /* 1024x768-75 VESA */
69 { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
70 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
71 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
72 /* 1024x768-85 VESA */
73 { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
74 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
75 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
76 /* 1280x960-60 VESA */
77 { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
78 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
79 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
80 /* 1280x960-85 VESA */
81 { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
82 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
83 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
84 /* 1280x1024-60 VESA */
85 { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
86 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
87 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
88 /* 1280x1024-75 VESA */
89 { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
90 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
91 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
92 /* 1280x1024-85 VESA */
93 { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
94 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
95 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
96 /* 1600x1200-60 VESA */
97 { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
98 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
99 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
100 /* 1600x1200-75 VESA */
101 { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
102 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
103 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
104 /* 1600x1200-85 VESA */
105 { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
106 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
107 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
108};
109
110#ifdef CONFIG_OLPC
111#include <asm/olpc.h>
112
113static struct fb_videomode gx_dcon_modedb[] = {
114 /* The only mode the DCON has is 1200x900 */
115 { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
116 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
117 FB_VMODE_NONINTERLACED, 0 }
118};
119
120static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
121{
122 if (olpc_has_dcon()) {
123 *modedb = (struct fb_videomode *) gx_dcon_modedb;
124 *size = ARRAY_SIZE(gx_dcon_modedb);
125 } else {
126 *modedb = (struct fb_videomode *) gx_modedb;
127 *size = ARRAY_SIZE(gx_modedb);
128 }
129}
130
131#else
132static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
133{
134 *modedb = (struct fb_videomode *) gx_modedb;
135 *size = ARRAY_SIZE(gx_modedb);
136}
137#endif
138
139static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
140{
141 if (var->xres > 1600 || var->yres > 1200)
142 return -EINVAL;
143 if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
144 return -EINVAL;
145
146 if (var->bits_per_pixel == 32) {
147 var->red.offset = 16; var->red.length = 8;
148 var->green.offset = 8; var->green.length = 8;
149 var->blue.offset = 0; var->blue.length = 8;
150 } else if (var->bits_per_pixel == 16) {
151 var->red.offset = 11; var->red.length = 5;
152 var->green.offset = 5; var->green.length = 6;
153 var->blue.offset = 0; var->blue.length = 5;
154 } else if (var->bits_per_pixel == 8) {
155 var->red.offset = 0; var->red.length = 8;
156 var->green.offset = 0; var->green.length = 8;
157 var->blue.offset = 0; var->blue.length = 8;
158 } else
159 return -EINVAL;
160 var->transp.offset = 0; var->transp.length = 0;
161
162 /* Enough video memory? */
163 if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
164 return -EINVAL;
165
166 /* FIXME: Check timing parameters here? */
167
168 return 0;
169}
170
171static int gxfb_set_par(struct fb_info *info)
172{
173 if (info->var.bits_per_pixel > 8)
174 info->fix.visual = FB_VISUAL_TRUECOLOR;
175 else
176 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
177
178 info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
179
180 gx_set_mode(info);
181
182 return 0;
183}
184
185static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
186{
187 chan &= 0xffff;
188 chan >>= 16 - bf->length;
189 return chan << bf->offset;
190}
191
192static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
193 unsigned blue, unsigned transp,
194 struct fb_info *info)
195{
196 if (info->var.grayscale) {
197 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
198 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
199 }
200
201 /* Truecolor has hardware independent palette */
202 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
203 u32 *pal = info->pseudo_palette;
204 u32 v;
205
206 if (regno >= 16)
207 return -EINVAL;
208
209 v = chan_to_field(red, &info->var.red);
210 v |= chan_to_field(green, &info->var.green);
211 v |= chan_to_field(blue, &info->var.blue);
212
213 pal[regno] = v;
214 } else {
215 if (regno >= 256)
216 return -EINVAL;
217
218 gx_set_hw_palette_reg(info, regno, red, green, blue);
219 }
220
221 return 0;
222}
223
224static int gxfb_blank(int blank_mode, struct fb_info *info)
225{
226 return gx_blank_display(info, blank_mode);
227}
228
229static int gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
230{
231 struct gxfb_par *par = info->par;
232 int ret;
233
234 ret = pci_enable_device(dev);
235 if (ret < 0)
236 return ret;
237
238 ret = pci_request_region(dev, 3, "gxfb (video processor)");
239 if (ret < 0)
240 return ret;
241 par->vid_regs = pci_ioremap_bar(dev, 3);
242 if (!par->vid_regs)
243 return -ENOMEM;
244
245 ret = pci_request_region(dev, 2, "gxfb (display controller)");
246 if (ret < 0)
247 return ret;
248 par->dc_regs = pci_ioremap_bar(dev, 2);
249 if (!par->dc_regs)
250 return -ENOMEM;
251
252 ret = pci_request_region(dev, 1, "gxfb (graphics processor)");
253 if (ret < 0)
254 return ret;
255 par->gp_regs = pci_ioremap_bar(dev, 1);
256
257 if (!par->gp_regs)
258 return -ENOMEM;
259
260 ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
261 if (ret < 0)
262 return ret;
263
264 info->fix.smem_start = pci_resource_start(dev, 0);
265 info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
266 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
267 if (!info->screen_base)
268 return -ENOMEM;
269
270 /* Set the 16MiB aligned base address of the graphics memory region
271 * in the display controller */
272
273 write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
274
275 dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
276 info->fix.smem_len / 1024, info->fix.smem_start);
277
278 return 0;
279}
280
281static struct fb_ops gxfb_ops = {
282 .owner = THIS_MODULE,
283 .fb_check_var = gxfb_check_var,
284 .fb_set_par = gxfb_set_par,
285 .fb_setcolreg = gxfb_setcolreg,
286 .fb_blank = gxfb_blank,
287 /* No HW acceleration for now. */
288 .fb_fillrect = cfb_fillrect,
289 .fb_copyarea = cfb_copyarea,
290 .fb_imageblit = cfb_imageblit,
291};
292
293static struct fb_info *gxfb_init_fbinfo(struct device *dev)
294{
295 struct gxfb_par *par;
296 struct fb_info *info;
297
298 /* Alloc enough space for the pseudo palette. */
299 info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
300 dev);
301 if (!info)
302 return NULL;
303
304 par = info->par;
305
306 strcpy(info->fix.id, "Geode GX");
307
308 info->fix.type = FB_TYPE_PACKED_PIXELS;
309 info->fix.type_aux = 0;
310 info->fix.xpanstep = 0;
311 info->fix.ypanstep = 0;
312 info->fix.ywrapstep = 0;
313 info->fix.accel = FB_ACCEL_NONE;
314
315 info->var.nonstd = 0;
316 info->var.activate = FB_ACTIVATE_NOW;
317 info->var.height = -1;
318 info->var.width = -1;
319 info->var.accel_flags = 0;
320 info->var.vmode = FB_VMODE_NONINTERLACED;
321
322 info->fbops = &gxfb_ops;
323 info->flags = FBINFO_DEFAULT;
324 info->node = -1;
325
326 info->pseudo_palette = (void *)par + sizeof(struct gxfb_par);
327
328 info->var.grayscale = 0;
329
330 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
331 framebuffer_release(info);
332 return NULL;
333 }
334
335 return info;
336}
337
338#ifdef CONFIG_PM
339static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state)
340{
341 struct fb_info *info = pci_get_drvdata(pdev);
342
343 if (state.event == PM_EVENT_SUSPEND) {
344 console_lock();
345 gx_powerdown(info);
346 fb_set_suspend(info, 1);
347 console_unlock();
348 }
349
350 /* there's no point in setting PCI states; we emulate PCI, so
351 * we don't end up getting power savings anyways */
352
353 return 0;
354}
355
356static int gxfb_resume(struct pci_dev *pdev)
357{
358 struct fb_info *info = pci_get_drvdata(pdev);
359 int ret;
360
361 console_lock();
362 ret = gx_powerup(info);
363 if (ret) {
364 printk(KERN_ERR "gxfb: power up failed!\n");
365 return ret;
366 }
367
368 fb_set_suspend(info, 0);
369 console_unlock();
370 return 0;
371}
372#endif
373
374static int gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
375{
376 struct gxfb_par *par;
377 struct fb_info *info;
378 int ret;
379 unsigned long val;
380
381 struct fb_videomode *modedb_ptr;
382 unsigned int modedb_size;
383
384 info = gxfb_init_fbinfo(&pdev->dev);
385 if (!info)
386 return -ENOMEM;
387 par = info->par;
388
389 if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
390 dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
391 goto err;
392 }
393
394 /* Figure out if this is a TFT or CRT part */
395
396 rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);
397
398 if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
399 par->enable_crt = 0;
400 else
401 par->enable_crt = 1;
402
403 get_modedb(&modedb_ptr, &modedb_size);
404 ret = fb_find_mode(&info->var, info, mode_option,
405 modedb_ptr, modedb_size, NULL, 16);
406 if (ret == 0 || ret == 4) {
407 dev_err(&pdev->dev, "could not find valid video mode\n");
408 ret = -EINVAL;
409 goto err;
410 }
411
412
413 /* Clear the frame buffer of garbage. */
414 memset_io(info->screen_base, 0, info->fix.smem_len);
415
416 gxfb_check_var(&info->var, info);
417 gxfb_set_par(info);
418
419 pm_set_vt_switch(vt_switch);
420
421 if (register_framebuffer(info) < 0) {
422 ret = -EINVAL;
423 goto err;
424 }
425 pci_set_drvdata(pdev, info);
426 fb_info(info, "%s frame buffer device\n", info->fix.id);
427 return 0;
428
429 err:
430 if (info->screen_base) {
431 iounmap(info->screen_base);
432 pci_release_region(pdev, 0);
433 }
434 if (par->vid_regs) {
435 iounmap(par->vid_regs);
436 pci_release_region(pdev, 3);
437 }
438 if (par->dc_regs) {
439 iounmap(par->dc_regs);
440 pci_release_region(pdev, 2);
441 }
442 if (par->gp_regs) {
443 iounmap(par->gp_regs);
444 pci_release_region(pdev, 1);
445 }
446
447 if (info) {
448 fb_dealloc_cmap(&info->cmap);
449 framebuffer_release(info);
450 }
451 return ret;
452}
453
454static void gxfb_remove(struct pci_dev *pdev)
455{
456 struct fb_info *info = pci_get_drvdata(pdev);
457 struct gxfb_par *par = info->par;
458
459 unregister_framebuffer(info);
460
461 iounmap((void __iomem *)info->screen_base);
462 pci_release_region(pdev, 0);
463
464 iounmap(par->vid_regs);
465 pci_release_region(pdev, 3);
466
467 iounmap(par->dc_regs);
468 pci_release_region(pdev, 2);
469
470 iounmap(par->gp_regs);
471 pci_release_region(pdev, 1);
472
473 fb_dealloc_cmap(&info->cmap);
474
475 framebuffer_release(info);
476}
477
478static struct pci_device_id gxfb_id_table[] = {
479 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
480 { 0, }
481};
482
483MODULE_DEVICE_TABLE(pci, gxfb_id_table);
484
485static struct pci_driver gxfb_driver = {
486 .name = "gxfb",
487 .id_table = gxfb_id_table,
488 .probe = gxfb_probe,
489 .remove = gxfb_remove,
490#ifdef CONFIG_PM
491 .suspend = gxfb_suspend,
492 .resume = gxfb_resume,
493#endif
494};
495
496#ifndef MODULE
497static int __init gxfb_setup(char *options)
498{
499
500 char *opt;
501
502 if (!options || !*options)
503 return 0;
504
505 while ((opt = strsep(&options, ",")) != NULL) {
506 if (!*opt)
507 continue;
508
509 mode_option = opt;
510 }
511
512 return 0;
513}
514#endif
515
516static int __init gxfb_init(void)
517{
518#ifndef MODULE
519 char *option = NULL;
520
521 if (fb_get_options("gxfb", &option))
522 return -ENODEV;
523
524 gxfb_setup(option);
525#endif
526 return pci_register_driver(&gxfb_driver);
527}
528
529static void __exit gxfb_cleanup(void)
530{
531 pci_unregister_driver(&gxfb_driver);
532}
533
534module_init(gxfb_init);
535module_exit(gxfb_cleanup);
536
537module_param(mode_option, charp, 0);
538MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
539
540module_param(vram, int, 0);
541MODULE_PARM_DESC(vram, "video memory size");
542
543module_param(vt_switch, int, 0);
544MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
545
546MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
547MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/geode/lxfb.h b/drivers/video/fbdev/geode/lxfb.h
new file mode 100644
index 000000000000..cfcd8090f313
--- /dev/null
+++ b/drivers/video/fbdev/geode/lxfb.h
@@ -0,0 +1,452 @@
1/* Geode LX framebuffer driver
2 *
3 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
4 * Copyright (c) 2008 Andres Salomon <dilinger@debian.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef _LXFB_H_
12#define _LXFB_H_
13
14#include <linux/fb.h>
15
16#define GP_REG_COUNT (0x7c / 4)
17#define DC_REG_COUNT (0xf0 / 4)
18#define VP_REG_COUNT (0x158 / 8)
19#define FP_REG_COUNT (0x60 / 8)
20
21#define DC_PAL_COUNT 0x104
22#define DC_HFILT_COUNT 0x100
23#define DC_VFILT_COUNT 0x100
24#define VP_COEFF_SIZE 0x1000
25#define VP_PAL_COUNT 0x100
26
27#define OUTPUT_CRT 0x01
28#define OUTPUT_PANEL 0x02
29
30struct lxfb_par {
31 int output;
32
33 void __iomem *gp_regs;
34 void __iomem *dc_regs;
35 void __iomem *vp_regs;
36#ifdef CONFIG_PM
37 int powered_down;
38
39 /* register state, for power mgmt functionality */
40 struct {
41 uint64_t padsel;
42 uint64_t dotpll;
43 uint64_t dfglcfg;
44 uint64_t dcspare;
45 } msr;
46
47 uint32_t gp[GP_REG_COUNT];
48 uint32_t dc[DC_REG_COUNT];
49 uint64_t vp[VP_REG_COUNT];
50 uint64_t fp[FP_REG_COUNT];
51
52 uint32_t dc_pal[DC_PAL_COUNT];
53 uint32_t vp_pal[VP_PAL_COUNT];
54 uint32_t hcoeff[DC_HFILT_COUNT * 2];
55 uint32_t vcoeff[DC_VFILT_COUNT];
56 uint32_t vp_coeff[VP_COEFF_SIZE / 4];
57#endif
58};
59
60static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
61{
62 return (((xres * (bpp >> 3)) + 7) & ~7);
63}
64
65void lx_set_mode(struct fb_info *);
66unsigned int lx_framebuffer_size(void);
67int lx_blank_display(struct fb_info *, int);
68void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
69 unsigned int, unsigned int);
70
71#ifdef CONFIG_PM
72int lx_powerdown(struct fb_info *info);
73int lx_powerup(struct fb_info *info);
74#endif
75
76
77/* Graphics Processor registers (table 6-29 from the data book) */
78enum gp_registers {
79 GP_DST_OFFSET = 0,
80 GP_SRC_OFFSET,
81 GP_STRIDE,
82 GP_WID_HEIGHT,
83
84 GP_SRC_COLOR_FG,
85 GP_SRC_COLOR_BG,
86 GP_PAT_COLOR_0,
87 GP_PAT_COLOR_1,
88
89 GP_PAT_COLOR_2,
90 GP_PAT_COLOR_3,
91 GP_PAT_COLOR_4,
92 GP_PAT_COLOR_5,
93
94 GP_PAT_DATA_0,
95 GP_PAT_DATA_1,
96 GP_RASTER_MODE,
97 GP_VECTOR_MODE,
98
99 GP_BLT_MODE,
100 GP_BLT_STATUS,
101 GP_HST_SRC,
102 GP_BASE_OFFSET,
103
104 GP_CMD_TOP,
105 GP_CMD_BOT,
106 GP_CMD_READ,
107 GP_CMD_WRITE,
108
109 GP_CH3_OFFSET,
110 GP_CH3_MODE_STR,
111 GP_CH3_WIDHI,
112 GP_CH3_HSRC,
113
114 GP_LUT_INDEX,
115 GP_LUT_DATA,
116 GP_INT_CNTRL, /* 0x78 */
117};
118
119#define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
120#define GP_BLT_STATUS_PB (1 << 0) /* primitive busy */
121
122
123/* Display Controller registers (table 6-47 from the data book) */
124enum dc_registers {
125 DC_UNLOCK = 0,
126 DC_GENERAL_CFG,
127 DC_DISPLAY_CFG,
128 DC_ARB_CFG,
129
130 DC_FB_ST_OFFSET,
131 DC_CB_ST_OFFSET,
132 DC_CURS_ST_OFFSET,
133 DC_RSVD_0,
134
135 DC_VID_Y_ST_OFFSET,
136 DC_VID_U_ST_OFFSET,
137 DC_VID_V_ST_OFFSET,
138 DC_DV_TOP,
139
140 DC_LINE_SIZE,
141 DC_GFX_PITCH,
142 DC_VID_YUV_PITCH,
143 DC_RSVD_1,
144
145 DC_H_ACTIVE_TIMING,
146 DC_H_BLANK_TIMING,
147 DC_H_SYNC_TIMING,
148 DC_RSVD_2,
149
150 DC_V_ACTIVE_TIMING,
151 DC_V_BLANK_TIMING,
152 DC_V_SYNC_TIMING,
153 DC_FB_ACTIVE,
154
155 DC_CURSOR_X,
156 DC_CURSOR_Y,
157 DC_RSVD_3,
158 DC_LINE_CNT,
159
160 DC_PAL_ADDRESS,
161 DC_PAL_DATA,
162 DC_DFIFO_DIAG,
163 DC_CFIFO_DIAG,
164
165 DC_VID_DS_DELTA,
166 DC_GLIU0_MEM_OFFSET,
167 DC_DV_CTL,
168 DC_DV_ACCESS,
169
170 DC_GFX_SCALE,
171 DC_IRQ_FILT_CTL,
172 DC_FILT_COEFF1,
173 DC_FILT_COEFF2,
174
175 DC_VBI_EVEN_CTL,
176 DC_VBI_ODD_CTL,
177 DC_VBI_HOR,
178 DC_VBI_LN_ODD,
179
180 DC_VBI_LN_EVEN,
181 DC_VBI_PITCH,
182 DC_CLR_KEY,
183 DC_CLR_KEY_MASK,
184
185 DC_CLR_KEY_X,
186 DC_CLR_KEY_Y,
187 DC_IRQ,
188 DC_RSVD_4,
189
190 DC_RSVD_5,
191 DC_GENLK_CTL,
192 DC_VID_EVEN_Y_ST_OFFSET,
193 DC_VID_EVEN_U_ST_OFFSET,
194
195 DC_VID_EVEN_V_ST_OFFSET,
196 DC_V_ACTIVE_EVEN_TIMING,
197 DC_V_BLANK_EVEN_TIMING,
198 DC_V_SYNC_EVEN_TIMING, /* 0xec */
199};
200
201#define DC_UNLOCK_LOCK 0x00000000
202#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
203
204#define DC_GENERAL_CFG_FDTY (1 << 17)
205#define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
206#define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
207#define DC_GENERAL_CFG_VGAE (1 << 7)
208#define DC_GENERAL_CFG_DECE (1 << 6)
209#define DC_GENERAL_CFG_CMPE (1 << 5)
210#define DC_GENERAL_CFG_VIDE (1 << 3)
211#define DC_GENERAL_CFG_DFLE (1 << 0)
212
213#define DC_DISPLAY_CFG_VISL (1 << 27)
214#define DC_DISPLAY_CFG_PALB (1 << 25)
215#define DC_DISPLAY_CFG_DCEN (1 << 24)
216#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
217#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
218#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
219#define DC_DISPLAY_CFG_TRUP (1 << 6)
220#define DC_DISPLAY_CFG_VDEN (1 << 4)
221#define DC_DISPLAY_CFG_GDEN (1 << 3)
222#define DC_DISPLAY_CFG_TGEN (1 << 0)
223
224#define DC_DV_TOP_DV_TOP_EN (1 << 0)
225
226#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11))
227#define DC_DV_CTL_DV_LINE_SIZE_1K (0)
228#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
229#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
230#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
231#define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
232
233#define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
234
235#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
236
237#define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
238#define DC_IRQ_STATUS (1 << 20) /* undocumented? */
239#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
240#define DC_IRQ_MASK (1 << 0)
241
242#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
243#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
244#define DC_GENLK_CTL_FLICK_EN (1 << 24)
245#define DC_GENLK_CTL_GENLK_EN (1 << 18)
246
247
248/*
249 * Video Processor registers (table 6-71).
250 * There is space for 64 bit values, but we never use more than the
251 * lower 32 bits. The actual register save/restore code only bothers
252 * to restore those 32 bits.
253 */
254enum vp_registers {
255 VP_VCFG = 0,
256 VP_DCFG,
257
258 VP_VX,
259 VP_VY,
260
261 VP_SCL,
262 VP_VCK,
263
264 VP_VCM,
265 VP_PAR,
266
267 VP_PDR,
268 VP_SLR,
269
270 VP_MISC,
271 VP_CCS,
272
273 VP_VYS,
274 VP_VXS,
275
276 VP_RSVD_0,
277 VP_VDC,
278
279 VP_RSVD_1,
280 VP_CRC,
281
282 VP_CRC32,
283 VP_VDE,
284
285 VP_CCK,
286 VP_CCM,
287
288 VP_CC1,
289 VP_CC2,
290
291 VP_A1X,
292 VP_A1Y,
293
294 VP_A1C,
295 VP_A1T,
296
297 VP_A2X,
298 VP_A2Y,
299
300 VP_A2C,
301 VP_A2T,
302
303 VP_A3X,
304 VP_A3Y,
305
306 VP_A3C,
307 VP_A3T,
308
309 VP_VRR,
310 VP_AWT,
311
312 VP_VTM,
313 VP_VYE,
314
315 VP_A1YE,
316 VP_A2YE,
317
318 VP_A3YE, /* 0x150 */
319
320 VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
321};
322
323#define VP_VCFG_VID_EN (1 << 0)
324
325#define VP_DCFG_GV_GAM (1 << 21)
326#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19))
327#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
328#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
329#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
330#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
331#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
332#define VP_DCFG_DAC_BL_EN (1 << 3)
333#define VP_DCFG_VSYNC_EN (1 << 2)
334#define VP_DCFG_HSYNC_EN (1 << 1)
335#define VP_DCFG_CRT_EN (1 << 0)
336
337#define VP_MISC_APWRDN (1 << 11)
338#define VP_MISC_DACPWRDN (1 << 10)
339#define VP_MISC_BYP_BOTH (1 << 0)
340
341
342/*
343 * Flat Panel registers (table 6-71).
344 * Also 64 bit registers; see above note about 32-bit handling.
345 */
346
347/* we're actually in the VP register space, starting at address 0x400 */
348#define VP_FP_START 0x400
349
350enum fp_registers {
351 FP_PT1 = 0,
352 FP_PT2,
353
354 FP_PM,
355 FP_DFC,
356
357 FP_RSVD_0,
358 FP_RSVD_1,
359
360 FP_RSVD_2,
361 FP_RSVD_3,
362
363 FP_RSVD_4,
364 FP_DCA,
365
366 FP_DMD,
367 FP_CRC, /* 0x458 */
368};
369
370#define FP_PT2_HSP (1 << 22)
371#define FP_PT2_VSP (1 << 23)
372#define FP_PT2_SCRC (1 << 27) /* shfclk free */
373
374#define FP_PM_P (1 << 24) /* panel power ctl */
375#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
376#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
377#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
378#define FP_PM_PANEL_ON (1 << 0) /* r/o */
379
380#define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
381
382
383/* register access functions */
384
385static inline uint32_t read_gp(struct lxfb_par *par, int reg)
386{
387 return readl(par->gp_regs + 4*reg);
388}
389
390static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
391{
392 writel(val, par->gp_regs + 4*reg);
393}
394
395static inline uint32_t read_dc(struct lxfb_par *par, int reg)
396{
397 return readl(par->dc_regs + 4*reg);
398}
399
400static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
401{
402 writel(val, par->dc_regs + 4*reg);
403}
404
405static inline uint32_t read_vp(struct lxfb_par *par, int reg)
406{
407 return readl(par->vp_regs + 8*reg);
408}
409
410static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
411{
412 writel(val, par->vp_regs + 8*reg);
413}
414
415static inline uint32_t read_fp(struct lxfb_par *par, int reg)
416{
417 return readl(par->vp_regs + 8*reg + VP_FP_START);
418}
419
420static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
421{
422 writel(val, par->vp_regs + 8*reg + VP_FP_START);
423}
424
425
426/* MSRs are defined in linux/cs5535.h; their bitfields are here */
427
428#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
429#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
430#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
431#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
432
433/* note: this is actually the VP's GLD_MSR_CONFIG */
434#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
435#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
436#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
437#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
438
439#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
440#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
441
442#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
443#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
444#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
445#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
446#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
447#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
448#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
449#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
450#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
451
452#endif
diff --git a/drivers/video/fbdev/geode/lxfb_core.c b/drivers/video/fbdev/geode/lxfb_core.c
new file mode 100644
index 000000000000..9e1d19d673a1
--- /dev/null
+++ b/drivers/video/fbdev/geode/lxfb_core.c
@@ -0,0 +1,683 @@
1/*
2 * Geode LX framebuffer driver.
3 *
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 * Built from gxfb (which is Copyright (C) 2006 Arcom Control Systems Ltd.)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/console.h>
18#include <linux/mm.h>
19#include <linux/suspend.h>
20#include <linux/delay.h>
21#include <linux/fb.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/uaccess.h>
25
26#include "lxfb.h"
27
28static char *mode_option;
29static int noclear, nopanel, nocrt;
30static int vram;
31static int vt_switch;
32
33/* Most of these modes are sorted in ascending order, but
34 * since the first entry in this table is the "default" mode,
35 * we try to make it something sane - 640x480-60 is sane
36 */
37
38static struct fb_videomode geode_modedb[] = {
39 /* 640x480-60 */
40 { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2,
41 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
42 FB_VMODE_NONINTERLACED, 0 },
43 /* 640x400-70 */
44 { NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2,
45 FB_SYNC_HOR_HIGH_ACT,
46 FB_VMODE_NONINTERLACED, 0 },
47 /* 640x480-70 */
48 { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3,
49 0, FB_VMODE_NONINTERLACED, 0 },
50 /* 640x480-72 */
51 { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3,
52 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
53 FB_VMODE_NONINTERLACED, 0 },
54 /* 640x480-75 */
55 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
56 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
57 FB_VMODE_NONINTERLACED, 0 },
58 /* 640x480-85 */
59 { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3,
60 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
61 FB_VMODE_NONINTERLACED, 0 },
62 /* 640x480-90 */
63 { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3,
64 0, FB_VMODE_NONINTERLACED, 0 },
65 /* 640x480-100 */
66 { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3,
67 0, FB_VMODE_NONINTERLACED, 0 },
68 /* 640x480-60 */
69 { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2,
70 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
71 FB_VMODE_NONINTERLACED, 0 },
72 /* 800x600-56 */
73 { NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2,
74 0, FB_VMODE_NONINTERLACED, 0 },
75 /* 800x600-60 */
76 { NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4,
77 0, FB_VMODE_NONINTERLACED, 0 },
78 /* 800x600-70 */
79 { NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3,
80 0, FB_VMODE_NONINTERLACED, 0 },
81 /* 800x600-72 */
82 { NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6,
83 0, FB_VMODE_NONINTERLACED, 0 },
84 /* 800x600-75 */
85 { NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3,
86 0, FB_VMODE_NONINTERLACED, 0 },
87 /* 800x600-85 */
88 { NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3,
89 0, FB_VMODE_NONINTERLACED, 0 },
90 /* 800x600-90 */
91 { NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3,
92 0, FB_VMODE_NONINTERLACED, 0 },
93 /* 800x600-100 */
94 { NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3,
95 0, FB_VMODE_NONINTERLACED, 0 },
96 /* 800x600-60 */
97 { NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4,
98 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
99 FB_VMODE_NONINTERLACED, 0 },
100 /* 1024x768-60 */
101 { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
102 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
103 FB_VMODE_NONINTERLACED, 0 },
104 /* 1024x768-70 */
105 { NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6,
106 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
107 FB_VMODE_NONINTERLACED, 0 },
108 /* 1024x768-72 */
109 { NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3,
110 0, FB_VMODE_NONINTERLACED, 0 },
111 /* 1024x768-75 */
112 { NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3,
113 0, FB_VMODE_NONINTERLACED, 0 },
114 /* 1024x768-85 */
115 { NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3,
116 0, FB_VMODE_NONINTERLACED, 0 },
117 /* 1024x768-90 */
118 { NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3,
119 0, FB_VMODE_NONINTERLACED, 0 },
120 /* 1024x768-100 */
121 { NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3,
122 0, FB_VMODE_NONINTERLACED, 0 },
123 /* 1024x768-60 */
124 { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
125 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
126 FB_VMODE_NONINTERLACED, 0 },
127 /* 1152x864-60 */
128 { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
129 0, FB_VMODE_NONINTERLACED, 0 },
130 /* 1152x864-70 */
131 { NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3,
132 0, FB_VMODE_NONINTERLACED, 0 },
133 /* 1152x864-72 */
134 { NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3,
135 0, FB_VMODE_NONINTERLACED, 0 },
136 /* 1152x864-75 */
137 { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
138 0, FB_VMODE_NONINTERLACED, 0 },
139 /* 1152x864-85 */
140 { NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3,
141 0, FB_VMODE_NONINTERLACED, 0 },
142 /* 1152x864-90 */
143 { NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3,
144 0, FB_VMODE_NONINTERLACED, 0 },
145 /* 1152x864-100 */
146 { NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3,
147 0, FB_VMODE_NONINTERLACED, 0 },
148 /* 1152x864-60 */
149 { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
150 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
151 FB_VMODE_NONINTERLACED, 0 },
152 /* 1280x1024-60 */
153 { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
154 0, FB_VMODE_NONINTERLACED, 0 },
155 /* 1280x1024-70 */
156 { NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3,
157 0, FB_VMODE_NONINTERLACED, 0 },
158 /* 1280x1024-72 */
159 { NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3,
160 0, FB_VMODE_NONINTERLACED, 0 },
161 /* 1280x1024-75 */
162 { NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3,
163 0, FB_VMODE_NONINTERLACED, 0 },
164 /* 1280x1024-85 */
165 { NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3,
166 0, FB_VMODE_NONINTERLACED, 0 },
167 /* 1280x1024-90 */
168 { NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3,
169 0, FB_VMODE_NONINTERLACED, 0 },
170 /* 1280x1024-100 */
171 { NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3,
172 0, FB_VMODE_NONINTERLACED, 0 },
173 /* 1280x1024-60 */
174 { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
175 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
176 FB_VMODE_NONINTERLACED, 0 },
177 /* 1600x1200-60 */
178 { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
179 0, FB_VMODE_NONINTERLACED, 0 },
180 /* 1600x1200-70 */
181 { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
182 0, FB_VMODE_NONINTERLACED, 0 },
183 /* 1600x1200-72 */
184 { NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3,
185 0, FB_VMODE_NONINTERLACED, 0 },
186 /* 1600x1200-75 */
187 { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
188 0, FB_VMODE_NONINTERLACED, 0 },
189 /* 1600x1200-85 */
190 { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
191 0, FB_VMODE_NONINTERLACED, 0 },
192 /* 1600x1200-90 */
193 { NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3,
194 0, FB_VMODE_NONINTERLACED, 0 },
195 /* 1600x1200-100 */
196 { NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3,
197 0, FB_VMODE_NONINTERLACED, 0 },
198 /* 1600x1200-60 */
199 { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
200 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
201 FB_VMODE_NONINTERLACED, 0 },
202 /* 1920x1440-60 */
203 { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3,
204 0, FB_VMODE_NONINTERLACED, 0 },
205 /* 1920x1440-70 */
206 { NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3,
207 0, FB_VMODE_NONINTERLACED, 0 },
208 /* 1920x1440-72 */
209 { NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3,
210 0, FB_VMODE_NONINTERLACED, 0 },
211 /* 1920x1440-75 */
212 { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
213 0, FB_VMODE_NONINTERLACED, 0 },
214 /* 1920x1440-85 */
215 { NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3,
216 0, FB_VMODE_NONINTERLACED, 0 },
217};
218
219#ifdef CONFIG_OLPC
220#include <asm/olpc.h>
221
222static struct fb_videomode olpc_dcon_modedb[] = {
223 /* The only mode the DCON has is 1200x900 */
224 { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
225 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
226 FB_VMODE_NONINTERLACED, 0 }
227};
228
229static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
230{
231 if (olpc_has_dcon()) {
232 *modedb = (struct fb_videomode *) olpc_dcon_modedb;
233 *size = ARRAY_SIZE(olpc_dcon_modedb);
234 } else {
235 *modedb = (struct fb_videomode *) geode_modedb;
236 *size = ARRAY_SIZE(geode_modedb);
237 }
238}
239
240#else
241static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
242{
243 *modedb = (struct fb_videomode *) geode_modedb;
244 *size = ARRAY_SIZE(geode_modedb);
245}
246#endif
247
248static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
249{
250 if (var->xres > 1920 || var->yres > 1440)
251 return -EINVAL;
252
253 if (var->bits_per_pixel == 32) {
254 var->red.offset = 16; var->red.length = 8;
255 var->green.offset = 8; var->green.length = 8;
256 var->blue.offset = 0; var->blue.length = 8;
257 } else if (var->bits_per_pixel == 16) {
258 var->red.offset = 11; var->red.length = 5;
259 var->green.offset = 5; var->green.length = 6;
260 var->blue.offset = 0; var->blue.length = 5;
261 } else if (var->bits_per_pixel == 8) {
262 var->red.offset = 0; var->red.length = 8;
263 var->green.offset = 0; var->green.length = 8;
264 var->blue.offset = 0; var->blue.length = 8;
265 } else
266 return -EINVAL;
267
268 var->transp.offset = 0; var->transp.length = 0;
269
270 /* Enough video memory? */
271 if ((lx_get_pitch(var->xres, var->bits_per_pixel) * var->yres)
272 > info->fix.smem_len)
273 return -EINVAL;
274
275 return 0;
276}
277
278static int lxfb_set_par(struct fb_info *info)
279{
280 if (info->var.bits_per_pixel > 8)
281 info->fix.visual = FB_VISUAL_TRUECOLOR;
282 else
283 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
284
285 info->fix.line_length = lx_get_pitch(info->var.xres,
286 info->var.bits_per_pixel);
287
288 lx_set_mode(info);
289 return 0;
290}
291
292static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
293{
294 chan &= 0xffff;
295 chan >>= 16 - bf->length;
296 return chan << bf->offset;
297}
298
299static int lxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
300 unsigned blue, unsigned transp,
301 struct fb_info *info)
302{
303 if (info->var.grayscale) {
304 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
305 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
306 }
307
308 /* Truecolor has hardware independent palette */
309 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
310 u32 *pal = info->pseudo_palette;
311 u32 v;
312
313 if (regno >= 16)
314 return -EINVAL;
315
316 v = chan_to_field(red, &info->var.red);
317 v |= chan_to_field(green, &info->var.green);
318 v |= chan_to_field(blue, &info->var.blue);
319
320 pal[regno] = v;
321 } else {
322 if (regno >= 256)
323 return -EINVAL;
324
325 lx_set_palette_reg(info, regno, red, green, blue);
326 }
327
328 return 0;
329}
330
331static int lxfb_blank(int blank_mode, struct fb_info *info)
332{
333 return lx_blank_display(info, blank_mode);
334}
335
336
337static int lxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
338{
339 struct lxfb_par *par = info->par;
340 int ret;
341
342 ret = pci_enable_device(dev);
343
344 if (ret)
345 return ret;
346
347 ret = pci_request_region(dev, 0, "lxfb-framebuffer");
348
349 if (ret)
350 return ret;
351
352 ret = pci_request_region(dev, 1, "lxfb-gp");
353
354 if (ret)
355 return ret;
356
357 ret = pci_request_region(dev, 2, "lxfb-vg");
358
359 if (ret)
360 return ret;
361
362 ret = pci_request_region(dev, 3, "lxfb-vp");
363
364 if (ret)
365 return ret;
366
367 info->fix.smem_start = pci_resource_start(dev, 0);
368 info->fix.smem_len = vram ? vram : lx_framebuffer_size();
369
370 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
371
372 ret = -ENOMEM;
373
374 if (info->screen_base == NULL)
375 return ret;
376
377 par->gp_regs = pci_ioremap_bar(dev, 1);
378
379 if (par->gp_regs == NULL)
380 return ret;
381
382 par->dc_regs = pci_ioremap_bar(dev, 2);
383
384 if (par->dc_regs == NULL)
385 return ret;
386
387 par->vp_regs = pci_ioremap_bar(dev, 3);
388
389 if (par->vp_regs == NULL)
390 return ret;
391
392 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
393 write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
394 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
395
396 dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n",
397 info->fix.smem_len / 1024, info->fix.smem_start);
398
399 return 0;
400}
401
402static struct fb_ops lxfb_ops = {
403 .owner = THIS_MODULE,
404 .fb_check_var = lxfb_check_var,
405 .fb_set_par = lxfb_set_par,
406 .fb_setcolreg = lxfb_setcolreg,
407 .fb_blank = lxfb_blank,
408 /* No HW acceleration for now. */
409 .fb_fillrect = cfb_fillrect,
410 .fb_copyarea = cfb_copyarea,
411 .fb_imageblit = cfb_imageblit,
412};
413
414static struct fb_info *lxfb_init_fbinfo(struct device *dev)
415{
416 struct lxfb_par *par;
417 struct fb_info *info;
418
419 /* Alloc enough space for the pseudo palette. */
420 info = framebuffer_alloc(sizeof(struct lxfb_par) + sizeof(u32) * 16,
421 dev);
422 if (!info)
423 return NULL;
424
425 par = info->par;
426
427 strcpy(info->fix.id, "Geode LX");
428
429 info->fix.type = FB_TYPE_PACKED_PIXELS;
430 info->fix.type_aux = 0;
431 info->fix.xpanstep = 0;
432 info->fix.ypanstep = 0;
433 info->fix.ywrapstep = 0;
434 info->fix.accel = FB_ACCEL_NONE;
435
436 info->var.nonstd = 0;
437 info->var.activate = FB_ACTIVATE_NOW;
438 info->var.height = -1;
439 info->var.width = -1;
440 info->var.accel_flags = 0;
441 info->var.vmode = FB_VMODE_NONINTERLACED;
442
443 info->fbops = &lxfb_ops;
444 info->flags = FBINFO_DEFAULT;
445 info->node = -1;
446
447 info->pseudo_palette = (void *)par + sizeof(struct lxfb_par);
448
449 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
450 framebuffer_release(info);
451 return NULL;
452 }
453
454 info->var.grayscale = 0;
455
456 return info;
457}
458
459#ifdef CONFIG_PM
460static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state)
461{
462 struct fb_info *info = pci_get_drvdata(pdev);
463
464 if (state.event == PM_EVENT_SUSPEND) {
465 console_lock();
466 lx_powerdown(info);
467 fb_set_suspend(info, 1);
468 console_unlock();
469 }
470
471 /* there's no point in setting PCI states; we emulate PCI, so
472 * we don't end up getting power savings anyways */
473
474 return 0;
475}
476
477static int lxfb_resume(struct pci_dev *pdev)
478{
479 struct fb_info *info = pci_get_drvdata(pdev);
480 int ret;
481
482 console_lock();
483 ret = lx_powerup(info);
484 if (ret) {
485 printk(KERN_ERR "lxfb: power up failed!\n");
486 return ret;
487 }
488
489 fb_set_suspend(info, 0);
490 console_unlock();
491 return 0;
492}
493#else
494#define lxfb_suspend NULL
495#define lxfb_resume NULL
496#endif
497
498static int lxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
499{
500 struct lxfb_par *par;
501 struct fb_info *info;
502 int ret;
503
504 struct fb_videomode *modedb_ptr;
505 unsigned int modedb_size;
506
507 info = lxfb_init_fbinfo(&pdev->dev);
508
509 if (info == NULL)
510 return -ENOMEM;
511
512 par = info->par;
513
514 ret = lxfb_map_video_memory(info, pdev);
515
516 if (ret < 0) {
517 dev_err(&pdev->dev,
518 "failed to map frame buffer or controller registers\n");
519 goto err;
520 }
521
522 /* Set up the desired outputs */
523
524 par->output = 0;
525 par->output |= (nopanel) ? 0 : OUTPUT_PANEL;
526 par->output |= (nocrt) ? 0 : OUTPUT_CRT;
527
528 /* Set up the mode database */
529
530 get_modedb(&modedb_ptr, &modedb_size);
531 ret = fb_find_mode(&info->var, info, mode_option,
532 modedb_ptr, modedb_size, NULL, 16);
533
534 if (ret == 0 || ret == 4) {
535 dev_err(&pdev->dev, "could not find valid video mode\n");
536 ret = -EINVAL;
537 goto err;
538 }
539
540 /* Clear the screen of garbage, unless noclear was specified,
541 * in which case we assume the user knows what he is doing */
542
543 if (!noclear)
544 memset_io(info->screen_base, 0, info->fix.smem_len);
545
546 /* Set the mode */
547
548 lxfb_check_var(&info->var, info);
549 lxfb_set_par(info);
550
551 pm_set_vt_switch(vt_switch);
552
553 if (register_framebuffer(info) < 0) {
554 ret = -EINVAL;
555 goto err;
556 }
557 pci_set_drvdata(pdev, info);
558 fb_info(info, "%s frame buffer device\n", info->fix.id);
559
560 return 0;
561
562err:
563 if (info->screen_base) {
564 iounmap(info->screen_base);
565 pci_release_region(pdev, 0);
566 }
567 if (par->gp_regs) {
568 iounmap(par->gp_regs);
569 pci_release_region(pdev, 1);
570 }
571 if (par->dc_regs) {
572 iounmap(par->dc_regs);
573 pci_release_region(pdev, 2);
574 }
575 if (par->vp_regs) {
576 iounmap(par->vp_regs);
577 pci_release_region(pdev, 3);
578 }
579
580 if (info) {
581 fb_dealloc_cmap(&info->cmap);
582 framebuffer_release(info);
583 }
584
585 return ret;
586}
587
588static void lxfb_remove(struct pci_dev *pdev)
589{
590 struct fb_info *info = pci_get_drvdata(pdev);
591 struct lxfb_par *par = info->par;
592
593 unregister_framebuffer(info);
594
595 iounmap(info->screen_base);
596 pci_release_region(pdev, 0);
597
598 iounmap(par->gp_regs);
599 pci_release_region(pdev, 1);
600
601 iounmap(par->dc_regs);
602 pci_release_region(pdev, 2);
603
604 iounmap(par->vp_regs);
605 pci_release_region(pdev, 3);
606
607 fb_dealloc_cmap(&info->cmap);
608 framebuffer_release(info);
609}
610
611static struct pci_device_id lxfb_id_table[] = {
612 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_VIDEO) },
613 { 0, }
614};
615
616MODULE_DEVICE_TABLE(pci, lxfb_id_table);
617
618static struct pci_driver lxfb_driver = {
619 .name = "lxfb",
620 .id_table = lxfb_id_table,
621 .probe = lxfb_probe,
622 .remove = lxfb_remove,
623 .suspend = lxfb_suspend,
624 .resume = lxfb_resume,
625};
626
627#ifndef MODULE
628static int __init lxfb_setup(char *options)
629{
630 char *opt;
631
632 if (!options || !*options)
633 return 0;
634
635 while ((opt = strsep(&options, ",")) != NULL) {
636 if (!*opt)
637 continue;
638
639 if (!strcmp(opt, "noclear"))
640 noclear = 1;
641 else if (!strcmp(opt, "nopanel"))
642 nopanel = 1;
643 else if (!strcmp(opt, "nocrt"))
644 nocrt = 1;
645 else
646 mode_option = opt;
647 }
648
649 return 0;
650}
651#endif
652
653static int __init lxfb_init(void)
654{
655#ifndef MODULE
656 char *option = NULL;
657
658 if (fb_get_options("lxfb", &option))
659 return -ENODEV;
660
661 lxfb_setup(option);
662#endif
663 return pci_register_driver(&lxfb_driver);
664}
665static void __exit lxfb_cleanup(void)
666{
667 pci_unregister_driver(&lxfb_driver);
668}
669
670module_init(lxfb_init);
671module_exit(lxfb_cleanup);
672
673module_param(mode_option, charp, 0);
674MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
675
676module_param(vram, int, 0);
677MODULE_PARM_DESC(vram, "video memory size");
678
679module_param(vt_switch, int, 0);
680MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
681
682MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode LX");
683MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/geode/lxfb_ops.c b/drivers/video/fbdev/geode/lxfb_ops.c
new file mode 100644
index 000000000000..79e9abc72b83
--- /dev/null
+++ b/drivers/video/fbdev/geode/lxfb_ops.c
@@ -0,0 +1,845 @@
1/* Geode LX framebuffer driver
2 *
3 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/fb.h>
14#include <linux/uaccess.h>
15#include <linux/delay.h>
16#include <linux/cs5535.h>
17
18#include "lxfb.h"
19
20/* TODO
21 * Support panel scaling
22 * Add acceleration
23 * Add support for interlacing (TV out)
24 * Support compression
25 */
26
27/* This is the complete list of PLL frequencies that we can set -
28 * we will choose the closest match to the incoming clock.
29 * freq is the frequency of the dotclock * 1000 (for example,
30 * 24823 = 24.983 Mhz).
31 * pllval is the corresponding PLL value
32*/
33
34static const struct {
35 unsigned int pllval;
36 unsigned int freq;
37} pll_table[] = {
38 { 0x000131AC, 6231 },
39 { 0x0001215D, 6294 },
40 { 0x00011087, 6750 },
41 { 0x0001216C, 7081 },
42 { 0x0001218D, 7140 },
43 { 0x000110C9, 7800 },
44 { 0x00013147, 7875 },
45 { 0x000110A7, 8258 },
46 { 0x00012159, 8778 },
47 { 0x00014249, 8875 },
48 { 0x00010057, 9000 },
49 { 0x0001219A, 9472 },
50 { 0x00012158, 9792 },
51 { 0x00010045, 10000 },
52 { 0x00010089, 10791 },
53 { 0x000110E7, 11225 },
54 { 0x00012136, 11430 },
55 { 0x00013207, 12375 },
56 { 0x00012187, 12500 },
57 { 0x00014286, 14063 },
58 { 0x000110E5, 15016 },
59 { 0x00014214, 16250 },
60 { 0x00011105, 17045 },
61 { 0x000131E4, 18563 },
62 { 0x00013183, 18750 },
63 { 0x00014284, 19688 },
64 { 0x00011104, 20400 },
65 { 0x00016363, 23625 },
66 { 0x000031AC, 24923 },
67 { 0x0000215D, 25175 },
68 { 0x00001087, 27000 },
69 { 0x0000216C, 28322 },
70 { 0x0000218D, 28560 },
71 { 0x000010C9, 31200 },
72 { 0x00003147, 31500 },
73 { 0x000010A7, 33032 },
74 { 0x00002159, 35112 },
75 { 0x00004249, 35500 },
76 { 0x00000057, 36000 },
77 { 0x0000219A, 37889 },
78 { 0x00002158, 39168 },
79 { 0x00000045, 40000 },
80 { 0x00000089, 43163 },
81 { 0x000010E7, 44900 },
82 { 0x00002136, 45720 },
83 { 0x00003207, 49500 },
84 { 0x00002187, 50000 },
85 { 0x00004286, 56250 },
86 { 0x000010E5, 60065 },
87 { 0x00004214, 65000 },
88 { 0x00001105, 68179 },
89 { 0x000031E4, 74250 },
90 { 0x00003183, 75000 },
91 { 0x00004284, 78750 },
92 { 0x00001104, 81600 },
93 { 0x00006363, 94500 },
94 { 0x00005303, 97520 },
95 { 0x00002183, 100187 },
96 { 0x00002122, 101420 },
97 { 0x00001081, 108000 },
98 { 0x00006201, 113310 },
99 { 0x00000041, 119650 },
100 { 0x000041A1, 129600 },
101 { 0x00002182, 133500 },
102 { 0x000041B1, 135000 },
103 { 0x00000051, 144000 },
104 { 0x000041E1, 148500 },
105 { 0x000062D1, 157500 },
106 { 0x000031A1, 162000 },
107 { 0x00000061, 169203 },
108 { 0x00004231, 172800 },
109 { 0x00002151, 175500 },
110 { 0x000052E1, 189000 },
111 { 0x00000071, 192000 },
112 { 0x00003201, 198000 },
113 { 0x00004291, 202500 },
114 { 0x00001101, 204750 },
115 { 0x00007481, 218250 },
116 { 0x00004170, 229500 },
117 { 0x00006210, 234000 },
118 { 0x00003140, 251182 },
119 { 0x00006250, 261000 },
120 { 0x000041C0, 278400 },
121 { 0x00005220, 280640 },
122 { 0x00000050, 288000 },
123 { 0x000041E0, 297000 },
124 { 0x00002130, 320207 }
125};
126
127
128static void lx_set_dotpll(u32 pllval)
129{
130 u32 dotpll_lo, dotpll_hi;
131 int i;
132
133 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
134
135 if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
136 return;
137
138 dotpll_hi = pllval;
139 dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
140 dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
141
142 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
143
144 /* Wait 100us for the PLL to lock */
145
146 udelay(100);
147
148 /* Now, loop for the lock bit */
149
150 for (i = 0; i < 1000; i++) {
151 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
152 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
153 break;
154 }
155
156 /* Clear the reset bit */
157
158 dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
159 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
160}
161
162/* Set the clock based on the frequency specified by the current mode */
163
164static void lx_set_clock(struct fb_info *info)
165{
166 unsigned int diff, min, best = 0;
167 unsigned int freq, i;
168
169 freq = (unsigned int) (1000000000 / info->var.pixclock);
170
171 min = abs(pll_table[0].freq - freq);
172
173 for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
174 diff = abs(pll_table[i].freq - freq);
175 if (diff < min) {
176 min = diff;
177 best = i;
178 }
179 }
180
181 lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
182}
183
184static void lx_graphics_disable(struct fb_info *info)
185{
186 struct lxfb_par *par = info->par;
187 unsigned int val, gcfg;
188
189 /* Note: This assumes that the video is in a quitet state */
190
191 write_vp(par, VP_A1T, 0);
192 write_vp(par, VP_A2T, 0);
193 write_vp(par, VP_A3T, 0);
194
195 /* Turn off the VGA and video enable */
196 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
197 DC_GENERAL_CFG_VIDE);
198
199 write_dc(par, DC_GENERAL_CFG, val);
200
201 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
202 write_vp(par, VP_VCFG, val);
203
204 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
205 DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
206
207 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
208 write_dc(par, DC_GENLK_CTL, val);
209
210 val = read_dc(par, DC_CLR_KEY);
211 write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
212
213 /* turn off the panel */
214 write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P);
215
216 val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
217 write_vp(par, VP_MISC, val);
218
219 /* Turn off the display */
220
221 val = read_vp(par, VP_DCFG);
222 write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
223 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
224
225 gcfg = read_dc(par, DC_GENERAL_CFG);
226 gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
227 write_dc(par, DC_GENERAL_CFG, gcfg);
228
229 /* Turn off the TGEN */
230 val = read_dc(par, DC_DISPLAY_CFG);
231 val &= ~DC_DISPLAY_CFG_TGEN;
232 write_dc(par, DC_DISPLAY_CFG, val);
233
234 /* Wait 1000 usecs to ensure that the TGEN is clear */
235 udelay(1000);
236
237 /* Turn off the FIFO loader */
238
239 gcfg &= ~DC_GENERAL_CFG_DFLE;
240 write_dc(par, DC_GENERAL_CFG, gcfg);
241
242 /* Lastly, wait for the GP to go idle */
243
244 do {
245 val = read_gp(par, GP_BLT_STATUS);
246 } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
247}
248
249static void lx_graphics_enable(struct fb_info *info)
250{
251 struct lxfb_par *par = info->par;
252 u32 temp, config;
253
254 /* Set the video request register */
255 write_vp(par, VP_VRR, 0);
256
257 /* Set up the polarities */
258
259 config = read_vp(par, VP_DCFG);
260
261 config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
262 VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
263
264 config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
265 | VP_DCFG_GV_GAM);
266
267 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
268 config |= VP_DCFG_CRT_HSYNC_POL;
269
270 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
271 config |= VP_DCFG_CRT_VSYNC_POL;
272
273 if (par->output & OUTPUT_PANEL) {
274 u32 msrlo, msrhi;
275
276 write_fp(par, FP_PT1, 0);
277 temp = FP_PT2_SCRC;
278
279 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
280 temp |= FP_PT2_HSP;
281
282 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
283 temp |= FP_PT2_VSP;
284
285 write_fp(par, FP_PT2, temp);
286 write_fp(par, FP_DFC, FP_DFC_BC);
287
288 msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
289 msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
290
291 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
292 }
293
294 if (par->output & OUTPUT_CRT) {
295 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
296 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
297 }
298
299 write_vp(par, VP_DCFG, config);
300
301 /* Turn the CRT dacs back on */
302
303 if (par->output & OUTPUT_CRT) {
304 temp = read_vp(par, VP_MISC);
305 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
306 write_vp(par, VP_MISC, temp);
307 }
308
309 /* Turn the panel on (if it isn't already) */
310 if (par->output & OUTPUT_PANEL)
311 write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P);
312}
313
314unsigned int lx_framebuffer_size(void)
315{
316 unsigned int val;
317
318 if (!cs5535_has_vsa2()) {
319 uint32_t hi, lo;
320
321 /* The number of pages is (PMAX - PMIN)+1 */
322 rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
323
324 /* PMAX */
325 val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
326 /* PMIN */
327 val -= (lo & 0x000fffff);
328 val += 1;
329
330 /* The page size is 4k */
331 return (val << 12);
332 }
333
334 /* The frame buffer size is reported by a VSM in VSA II */
335 /* Virtual Register Class = 0x02 */
336 /* VG_MEM_SIZE (1MB units) = 0x00 */
337
338 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
339 outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
340
341 val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE;
342 return (val << 20);
343}
344
345void lx_set_mode(struct fb_info *info)
346{
347 struct lxfb_par *par = info->par;
348 u64 msrval;
349
350 unsigned int max, dv, val, size;
351
352 unsigned int gcfg, dcfg;
353 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
354 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
355
356 /* Unlock the DC registers */
357 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
358
359 lx_graphics_disable(info);
360
361 lx_set_clock(info);
362
363 /* Set output mode */
364
365 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
366 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
367
368 if (par->output & OUTPUT_PANEL) {
369 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
370
371 if (par->output & OUTPUT_CRT)
372 msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
373 else
374 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
375 } else
376 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
377
378 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
379
380 /* Clear the various buffers */
381 /* FIXME: Adjust for panning here */
382
383 write_dc(par, DC_FB_ST_OFFSET, 0);
384 write_dc(par, DC_CB_ST_OFFSET, 0);
385 write_dc(par, DC_CURS_ST_OFFSET, 0);
386
387 /* FIXME: Add support for interlacing */
388 /* FIXME: Add support for scaling */
389
390 val = read_dc(par, DC_GENLK_CTL);
391 val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
392 DC_GENLK_CTL_FLICK_SEL_MASK);
393
394 /* Default scaling params */
395
396 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
397 write_dc(par, DC_IRQ_FILT_CTL, 0);
398 write_dc(par, DC_GENLK_CTL, val);
399
400 /* FIXME: Support compression */
401
402 if (info->fix.line_length > 4096)
403 dv = DC_DV_CTL_DV_LINE_SIZE_8K;
404 else if (info->fix.line_length > 2048)
405 dv = DC_DV_CTL_DV_LINE_SIZE_4K;
406 else if (info->fix.line_length > 1024)
407 dv = DC_DV_CTL_DV_LINE_SIZE_2K;
408 else
409 dv = DC_DV_CTL_DV_LINE_SIZE_1K;
410
411 max = info->fix.line_length * info->var.yres;
412 max = (max + 0x3FF) & 0xFFFFFC00;
413
414 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
415
416 val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
417 write_dc(par, DC_DV_CTL, val | dv);
418
419 size = info->var.xres * (info->var.bits_per_pixel >> 3);
420
421 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
422 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
423
424 /* Set default watermark values */
425
426 rdmsrl(MSR_LX_SPARE_MSR, msrval);
427
428 msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
429 | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
430 | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
431 | MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
432 msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
433 MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
434 wrmsrl(MSR_LX_SPARE_MSR, msrval);
435
436 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */
437 gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
438 (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
439 gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */
440
441 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */
442 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */
443 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */
444 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */
445 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */
446 dcfg |= DC_DISPLAY_CFG_VISL;
447 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */
448
449 /* Set the current BPP mode */
450
451 switch (info->var.bits_per_pixel) {
452 case 8:
453 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
454 break;
455
456 case 16:
457 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
458 break;
459
460 case 32:
461 case 24:
462 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
463 break;
464 }
465
466 /* Now - set up the timings */
467
468 hactive = info->var.xres;
469 hblankstart = hactive;
470 hsyncstart = hblankstart + info->var.right_margin;
471 hsyncend = hsyncstart + info->var.hsync_len;
472 hblankend = hsyncend + info->var.left_margin;
473 htotal = hblankend;
474
475 vactive = info->var.yres;
476 vblankstart = vactive;
477 vsyncstart = vblankstart + info->var.lower_margin;
478 vsyncend = vsyncstart + info->var.vsync_len;
479 vblankend = vsyncend + info->var.upper_margin;
480 vtotal = vblankend;
481
482 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
483 write_dc(par, DC_H_BLANK_TIMING,
484 (hblankstart - 1) | ((hblankend - 1) << 16));
485 write_dc(par, DC_H_SYNC_TIMING,
486 (hsyncstart - 1) | ((hsyncend - 1) << 16));
487
488 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
489 write_dc(par, DC_V_BLANK_TIMING,
490 (vblankstart - 1) | ((vblankend - 1) << 16));
491 write_dc(par, DC_V_SYNC_TIMING,
492 (vsyncstart - 1) | ((vsyncend - 1) << 16));
493
494 write_dc(par, DC_FB_ACTIVE,
495 (info->var.xres - 1) << 16 | (info->var.yres - 1));
496
497 /* And re-enable the graphics output */
498 lx_graphics_enable(info);
499
500 /* Write the two main configuration registers */
501 write_dc(par, DC_DISPLAY_CFG, dcfg);
502 write_dc(par, DC_ARB_CFG, 0);
503 write_dc(par, DC_GENERAL_CFG, gcfg);
504
505 /* Lock the DC registers */
506 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
507}
508
509void lx_set_palette_reg(struct fb_info *info, unsigned regno,
510 unsigned red, unsigned green, unsigned blue)
511{
512 struct lxfb_par *par = info->par;
513 int val;
514
515 /* Hardware palette is in RGB 8-8-8 format. */
516
517 val = (red << 8) & 0xff0000;
518 val |= (green) & 0x00ff00;
519 val |= (blue >> 8) & 0x0000ff;
520
521 write_dc(par, DC_PAL_ADDRESS, regno);
522 write_dc(par, DC_PAL_DATA, val);
523}
524
525int lx_blank_display(struct fb_info *info, int blank_mode)
526{
527 struct lxfb_par *par = info->par;
528 u32 dcfg, misc, fp_pm;
529 int blank, hsync, vsync;
530
531 /* CRT power saving modes. */
532 switch (blank_mode) {
533 case FB_BLANK_UNBLANK:
534 blank = 0; hsync = 1; vsync = 1;
535 break;
536 case FB_BLANK_NORMAL:
537 blank = 1; hsync = 1; vsync = 1;
538 break;
539 case FB_BLANK_VSYNC_SUSPEND:
540 blank = 1; hsync = 1; vsync = 0;
541 break;
542 case FB_BLANK_HSYNC_SUSPEND:
543 blank = 1; hsync = 0; vsync = 1;
544 break;
545 case FB_BLANK_POWERDOWN:
546 blank = 1; hsync = 0; vsync = 0;
547 break;
548 default:
549 return -EINVAL;
550 }
551
552 dcfg = read_vp(par, VP_DCFG);
553 dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
554 VP_DCFG_CRT_EN);
555 if (!blank)
556 dcfg |= VP_DCFG_DAC_BL_EN | VP_DCFG_CRT_EN;
557 if (hsync)
558 dcfg |= VP_DCFG_HSYNC_EN;
559 if (vsync)
560 dcfg |= VP_DCFG_VSYNC_EN;
561
562 write_vp(par, VP_DCFG, dcfg);
563
564 misc = read_vp(par, VP_MISC);
565
566 if (vsync && hsync)
567 misc &= ~VP_MISC_DACPWRDN;
568 else
569 misc |= VP_MISC_DACPWRDN;
570
571 write_vp(par, VP_MISC, misc);
572
573 /* Power on/off flat panel */
574
575 if (par->output & OUTPUT_PANEL) {
576 fp_pm = read_fp(par, FP_PM);
577 if (blank_mode == FB_BLANK_POWERDOWN)
578 fp_pm &= ~FP_PM_P;
579 else
580 fp_pm |= FP_PM_P;
581 write_fp(par, FP_PM, fp_pm);
582 }
583
584 return 0;
585}
586
587#ifdef CONFIG_PM
588
589static void lx_save_regs(struct lxfb_par *par)
590{
591 uint32_t filt;
592 int i;
593
594 /* wait for the BLT engine to stop being busy */
595 do {
596 i = read_gp(par, GP_BLT_STATUS);
597 } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
598
599 /* save MSRs */
600 rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
601 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
602 rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
603 rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
604
605 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
606
607 /* save registers */
608 memcpy(par->gp, par->gp_regs, sizeof(par->gp));
609 memcpy(par->dc, par->dc_regs, sizeof(par->dc));
610 memcpy(par->vp, par->vp_regs, sizeof(par->vp));
611 memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp));
612
613 /* save the display controller palette */
614 write_dc(par, DC_PAL_ADDRESS, 0);
615 for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++)
616 par->dc_pal[i] = read_dc(par, DC_PAL_DATA);
617
618 /* save the video processor palette */
619 write_vp(par, VP_PAR, 0);
620 for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++)
621 par->vp_pal[i] = read_vp(par, VP_PDR);
622
623 /* save the horizontal filter coefficients */
624 filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
625 for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
626 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
627 par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1);
628 par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2);
629 }
630
631 /* save the vertical filter coefficients */
632 filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
633 for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
634 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
635 par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1);
636 }
637
638 /* save video coeff ram */
639 memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff));
640}
641
642static void lx_restore_gfx_proc(struct lxfb_par *par)
643{
644 int i;
645
646 /* a bunch of registers require GP_RASTER_MODE to be set first */
647 write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]);
648
649 for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
650 switch (i) {
651 case GP_RASTER_MODE:
652 case GP_VECTOR_MODE:
653 case GP_BLT_MODE:
654 case GP_BLT_STATUS:
655 case GP_HST_SRC:
656 /* FIXME: restore LUT data */
657 case GP_LUT_INDEX:
658 case GP_LUT_DATA:
659 /* don't restore these registers */
660 break;
661
662 default:
663 write_gp(par, i, par->gp[i]);
664 }
665 }
666}
667
668static void lx_restore_display_ctlr(struct lxfb_par *par)
669{
670 uint32_t filt;
671 int i;
672
673 wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
674
675 for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
676 switch (i) {
677 case DC_UNLOCK:
678 /* unlock the DC; runs first */
679 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
680 break;
681
682 case DC_GENERAL_CFG:
683 case DC_DISPLAY_CFG:
684 /* disable all while restoring */
685 write_dc(par, i, 0);
686 break;
687
688 case DC_DV_CTL:
689 /* set all ram to dirty */
690 write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
691
692 case DC_RSVD_1:
693 case DC_RSVD_2:
694 case DC_RSVD_3:
695 case DC_LINE_CNT:
696 case DC_PAL_ADDRESS:
697 case DC_PAL_DATA:
698 case DC_DFIFO_DIAG:
699 case DC_CFIFO_DIAG:
700 case DC_FILT_COEFF1:
701 case DC_FILT_COEFF2:
702 case DC_RSVD_4:
703 case DC_RSVD_5:
704 /* don't restore these registers */
705 break;
706
707 default:
708 write_dc(par, i, par->dc[i]);
709 }
710 }
711
712 /* restore the palette */
713 write_dc(par, DC_PAL_ADDRESS, 0);
714 for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++)
715 write_dc(par, DC_PAL_DATA, par->dc_pal[i]);
716
717 /* restore the horizontal filter coefficients */
718 filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
719 for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
720 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
721 write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
722 write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
723 }
724
725 /* restore the vertical filter coefficients */
726 filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
727 for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
728 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
729 write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
730 }
731}
732
733static void lx_restore_video_proc(struct lxfb_par *par)
734{
735 int i;
736
737 wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
738 wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
739
740 for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
741 switch (i) {
742 case VP_VCFG:
743 case VP_DCFG:
744 case VP_PAR:
745 case VP_PDR:
746 case VP_CCS:
747 case VP_RSVD_0:
748 /* case VP_VDC: */ /* why should this not be restored? */
749 case VP_RSVD_1:
750 case VP_CRC32:
751 /* don't restore these registers */
752 break;
753
754 default:
755 write_vp(par, i, par->vp[i]);
756 }
757 }
758
759 /* restore video processor palette */
760 write_vp(par, VP_PAR, 0);
761 for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++)
762 write_vp(par, VP_PDR, par->vp_pal[i]);
763
764 /* restore video coeff ram */
765 memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff));
766}
767
768static void lx_restore_regs(struct lxfb_par *par)
769{
770 int i;
771
772 lx_set_dotpll((u32) (par->msr.dotpll >> 32));
773 lx_restore_gfx_proc(par);
774 lx_restore_display_ctlr(par);
775 lx_restore_video_proc(par);
776
777 /* Flat Panel */
778 for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
779 switch (i) {
780 case FP_PM:
781 case FP_RSVD_0:
782 case FP_RSVD_1:
783 case FP_RSVD_2:
784 case FP_RSVD_3:
785 case FP_RSVD_4:
786 /* don't restore these registers */
787 break;
788
789 default:
790 write_fp(par, i, par->fp[i]);
791 }
792 }
793
794 /* control the panel */
795 if (par->fp[FP_PM] & FP_PM_P) {
796 /* power on the panel if not already power{ed,ing} on */
797 if (!(read_fp(par, FP_PM) &
798 (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
799 write_fp(par, FP_PM, par->fp[FP_PM]);
800 } else {
801 /* power down the panel if not already power{ed,ing} down */
802 if (!(read_fp(par, FP_PM) &
803 (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
804 write_fp(par, FP_PM, par->fp[FP_PM]);
805 }
806
807 /* turn everything on */
808 write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
809 write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
810 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
811 /* do this last; it will enable the FIFO load */
812 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
813
814 /* lock the door behind us */
815 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
816}
817
818int lx_powerdown(struct fb_info *info)
819{
820 struct lxfb_par *par = info->par;
821
822 if (par->powered_down)
823 return 0;
824
825 lx_save_regs(par);
826 lx_graphics_disable(info);
827
828 par->powered_down = 1;
829 return 0;
830}
831
832int lx_powerup(struct fb_info *info)
833{
834 struct lxfb_par *par = info->par;
835
836 if (!par->powered_down)
837 return 0;
838
839 lx_restore_regs(par);
840
841 par->powered_down = 0;
842 return 0;
843}
844
845#endif
diff --git a/drivers/video/fbdev/geode/suspend_gx.c b/drivers/video/fbdev/geode/suspend_gx.c
new file mode 100644
index 000000000000..1bb043d70c64
--- /dev/null
+++ b/drivers/video/fbdev/geode/suspend_gx.c
@@ -0,0 +1,267 @@
1/*
2 * Copyright (C) 2007 Advanced Micro Devices, Inc.
3 * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/fb.h>
11#include <asm/io.h>
12#include <asm/msr.h>
13#include <linux/cs5535.h>
14#include <asm/delay.h>
15
16#include "gxfb.h"
17
18#ifdef CONFIG_PM
19
20static void gx_save_regs(struct gxfb_par *par)
21{
22 int i;
23
24 /* wait for the BLT engine to stop being busy */
25 do {
26 i = read_gp(par, GP_BLT_STATUS);
27 } while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY));
28
29 /* save MSRs */
30 rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
31 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
32
33 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
34
35 /* save registers */
36 memcpy(par->gp, par->gp_regs, sizeof(par->gp));
37 memcpy(par->dc, par->dc_regs, sizeof(par->dc));
38 memcpy(par->vp, par->vid_regs, sizeof(par->vp));
39 memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp));
40
41 /* save the palette */
42 write_dc(par, DC_PAL_ADDRESS, 0);
43 for (i = 0; i < ARRAY_SIZE(par->pal); i++)
44 par->pal[i] = read_dc(par, DC_PAL_DATA);
45}
46
47static void gx_set_dotpll(uint32_t dotpll_hi)
48{
49 uint32_t dotpll_lo;
50 int i;
51
52 rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
53 dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
54 dotpll_lo &= ~MSR_GLCP_DOTPLL_BYPASS;
55 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
56
57 /* wait for the PLL to lock */
58 for (i = 0; i < 200; i++) {
59 rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
60 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
61 break;
62 udelay(1);
63 }
64
65 /* PLL set, unlock */
66 dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
67 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
68}
69
70static void gx_restore_gfx_proc(struct gxfb_par *par)
71{
72 int i;
73
74 for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
75 switch (i) {
76 case GP_VECTOR_MODE:
77 case GP_BLT_MODE:
78 case GP_BLT_STATUS:
79 case GP_HST_SRC:
80 /* don't restore these registers */
81 break;
82 default:
83 write_gp(par, i, par->gp[i]);
84 }
85 }
86}
87
88static void gx_restore_display_ctlr(struct gxfb_par *par)
89{
90 int i;
91
92 for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
93 switch (i) {
94 case DC_UNLOCK:
95 /* unlock the DC; runs first */
96 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
97 break;
98
99 case DC_GENERAL_CFG:
100 /* write without the enables */
101 write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |
102 DC_GENERAL_CFG_ICNE |
103 DC_GENERAL_CFG_CURE |
104 DC_GENERAL_CFG_DFLE));
105 break;
106
107 case DC_DISPLAY_CFG:
108 /* write without the enables */
109 write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
110 DC_DISPLAY_CFG_GDEN |
111 DC_DISPLAY_CFG_TGEN));
112 break;
113
114 case DC_RSVD_0:
115 case DC_RSVD_1:
116 case DC_RSVD_2:
117 case DC_RSVD_3:
118 case DC_RSVD_4:
119 case DC_LINE_CNT:
120 case DC_PAL_ADDRESS:
121 case DC_PAL_DATA:
122 case DC_DFIFO_DIAG:
123 case DC_CFIFO_DIAG:
124 case DC_RSVD_5:
125 /* don't restore these registers */
126 break;
127 default:
128 write_dc(par, i, par->dc[i]);
129 }
130 }
131
132 /* restore the palette */
133 write_dc(par, DC_PAL_ADDRESS, 0);
134 for (i = 0; i < ARRAY_SIZE(par->pal); i++)
135 write_dc(par, DC_PAL_DATA, par->pal[i]);
136}
137
138static void gx_restore_video_proc(struct gxfb_par *par)
139{
140 int i;
141
142 wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
143
144 for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
145 switch (i) {
146 case VP_VCFG:
147 /* don't enable video yet */
148 write_vp(par, i, par->vp[i] & ~VP_VCFG_VID_EN);
149 break;
150
151 case VP_DCFG:
152 /* don't enable CRT yet */
153 write_vp(par, i, par->vp[i] &
154 ~(VP_DCFG_DAC_BL_EN | VP_DCFG_VSYNC_EN |
155 VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
156 break;
157
158 case VP_GAR:
159 case VP_GDR:
160 case VP_RSVD_0:
161 case VP_RSVD_1:
162 case VP_RSVD_2:
163 case VP_RSVD_3:
164 case VP_CRC32:
165 case VP_AWT:
166 case VP_VTM:
167 /* don't restore these registers */
168 break;
169 default:
170 write_vp(par, i, par->vp[i]);
171 }
172 }
173}
174
175static void gx_restore_regs(struct gxfb_par *par)
176{
177 int i;
178
179 gx_set_dotpll((uint32_t) (par->msr.dotpll >> 32));
180 gx_restore_gfx_proc(par);
181 gx_restore_display_ctlr(par);
182 gx_restore_video_proc(par);
183
184 /* Flat Panel */
185 for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
186 if (i != FP_PM && i != FP_RSVD_0)
187 write_fp(par, i, par->fp[i]);
188 }
189}
190
191static void gx_disable_graphics(struct gxfb_par *par)
192{
193 /* shut down the engine */
194 write_vp(par, VP_VCFG, par->vp[VP_VCFG] & ~VP_VCFG_VID_EN);
195 write_vp(par, VP_DCFG, par->vp[VP_DCFG] & ~(VP_DCFG_DAC_BL_EN |
196 VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
197
198 /* turn off the flat panel */
199 write_fp(par, FP_PM, par->fp[FP_PM] & ~FP_PM_P);
200
201
202 /* turn off display */
203 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
204 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
205 ~(DC_GENERAL_CFG_VIDE | DC_GENERAL_CFG_ICNE |
206 DC_GENERAL_CFG_CURE | DC_GENERAL_CFG_DFLE));
207 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
208 ~(DC_DISPLAY_CFG_VDEN | DC_DISPLAY_CFG_GDEN |
209 DC_DISPLAY_CFG_TGEN));
210 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
211}
212
213static void gx_enable_graphics(struct gxfb_par *par)
214{
215 uint32_t fp;
216
217 fp = read_fp(par, FP_PM);
218 if (par->fp[FP_PM] & FP_PM_P) {
219 /* power on the panel if not already power{ed,ing} on */
220 if (!(fp & (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
221 write_fp(par, FP_PM, par->fp[FP_PM]);
222 } else {
223 /* power down the panel if not already power{ed,ing} down */
224 if (!(fp & (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
225 write_fp(par, FP_PM, par->fp[FP_PM]);
226 }
227
228 /* turn everything on */
229 write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
230 write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
231 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
232 /* do this last; it will enable the FIFO load */
233 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
234
235 /* lock the door behind us */
236 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
237}
238
239int gx_powerdown(struct fb_info *info)
240{
241 struct gxfb_par *par = info->par;
242
243 if (par->powered_down)
244 return 0;
245
246 gx_save_regs(par);
247 gx_disable_graphics(par);
248
249 par->powered_down = 1;
250 return 0;
251}
252
253int gx_powerup(struct fb_info *info)
254{
255 struct gxfb_par *par = info->par;
256
257 if (!par->powered_down)
258 return 0;
259
260 gx_restore_regs(par);
261 gx_enable_graphics(par);
262
263 par->powered_down = 0;
264 return 0;
265}
266
267#endif
diff --git a/drivers/video/fbdev/geode/video_cs5530.c b/drivers/video/fbdev/geode/video_cs5530.c
new file mode 100644
index 000000000000..649c3943d431
--- /dev/null
+++ b/drivers/video/fbdev/geode/video_cs5530.c
@@ -0,0 +1,193 @@
1/*
2 * drivers/video/geode/video_cs5530.c
3 * -- CS5530 video device
4 *
5 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 *
7 * Based on AMD's original 2.4 driver:
8 * Copyright (C) 2004 Advanced Micro Devices, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15#include <linux/fb.h>
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/delay.h>
19
20#include "geodefb.h"
21#include "video_cs5530.h"
22
23/*
24 * CS5530 PLL table. This maps pixclocks to the appropriate PLL register
25 * value.
26 */
27struct cs5530_pll_entry {
28 long pixclock; /* ps */
29 u32 pll_value;
30};
31
32static const struct cs5530_pll_entry cs5530_pll_table[] = {
33 { 39721, 0x31C45801, }, /* 25.1750 MHz */
34 { 35308, 0x20E36802, }, /* 28.3220 */
35 { 31746, 0x33915801, }, /* 31.5000 */
36 { 27777, 0x31EC4801, }, /* 36.0000 */
37 { 26666, 0x21E22801, }, /* 37.5000 */
38 { 25000, 0x33088801, }, /* 40.0000 */
39 { 22271, 0x33E22801, }, /* 44.9000 */
40 { 20202, 0x336C4801, }, /* 49.5000 */
41 { 20000, 0x23088801, }, /* 50.0000 */
42 { 19860, 0x23088801, }, /* 50.3500 */
43 { 18518, 0x3708A801, }, /* 54.0000 */
44 { 17777, 0x23E36802, }, /* 56.2500 */
45 { 17733, 0x23E36802, }, /* 56.3916 */
46 { 17653, 0x23E36802, }, /* 56.6444 */
47 { 16949, 0x37C45801, }, /* 59.0000 */
48 { 15873, 0x23EC4801, }, /* 63.0000 */
49 { 15384, 0x37911801, }, /* 65.0000 */
50 { 14814, 0x37963803, }, /* 67.5000 */
51 { 14124, 0x37058803, }, /* 70.8000 */
52 { 13888, 0x3710C805, }, /* 72.0000 */
53 { 13333, 0x37E22801, }, /* 75.0000 */
54 { 12698, 0x27915801, }, /* 78.7500 */
55 { 12500, 0x37D8D802, }, /* 80.0000 */
56 { 11135, 0x27588802, }, /* 89.8000 */
57 { 10582, 0x27EC4802, }, /* 94.5000 */
58 { 10101, 0x27AC6803, }, /* 99.0000 */
59 { 10000, 0x27088801, }, /* 100.0000 */
60 { 9259, 0x2710C805, }, /* 108.0000 */
61 { 8888, 0x27E36802, }, /* 112.5000 */
62 { 7692, 0x27C58803, }, /* 130.0000 */
63 { 7407, 0x27316803, }, /* 135.0000 */
64 { 6349, 0x2F915801, }, /* 157.5000 */
65 { 6172, 0x2F08A801, }, /* 162.0000 */
66 { 5714, 0x2FB11802, }, /* 175.0000 */
67 { 5291, 0x2FEC4802, }, /* 189.0000 */
68 { 4950, 0x2F963803, }, /* 202.0000 */
69 { 4310, 0x2FB1B802, }, /* 232.0000 */
70};
71
72static void cs5530_set_dclk_frequency(struct fb_info *info)
73{
74 struct geodefb_par *par = info->par;
75 int i;
76 u32 value;
77 long min, diff;
78
79 /* Search the table for the closest pixclock. */
80 value = cs5530_pll_table[0].pll_value;
81 min = cs5530_pll_table[0].pixclock - info->var.pixclock;
82 if (min < 0) min = -min;
83 for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) {
84 diff = cs5530_pll_table[i].pixclock - info->var.pixclock;
85 if (diff < 0L) diff = -diff;
86 if (diff < min) {
87 min = diff;
88 value = cs5530_pll_table[i].pll_value;
89 }
90 }
91
92 writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG);
93 writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */
94 udelay(500); /* wait for PLL to settle */
95 writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */
96 writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */
97}
98
99static void cs5530_configure_display(struct fb_info *info)
100{
101 struct geodefb_par *par = info->par;
102 u32 dcfg;
103
104 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
105
106 /* Clear bits from existing mode. */
107 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK
108 | CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL
109 | CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN
110 | CS5530_DCFG_DAC_PWR_EN | CS5530_DCFG_VSYNC_EN
111 | CS5530_DCFG_HSYNC_EN);
112
113 /* Set default sync skew and power sequence delays. */
114 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT
115 | CS5530_DCFG_GV_PAL_BYP);
116
117 /* Enable DACs, hsync and vsync for CRTs */
118 if (par->enable_crt) {
119 dcfg |= CS5530_DCFG_DAC_PWR_EN;
120 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN;
121 }
122 /* Enable panel power and data if using a flat panel. */
123 if (par->panel_x > 0) {
124 dcfg |= CS5530_DCFG_FP_PWR_EN;
125 dcfg |= CS5530_DCFG_FP_DATA_EN;
126 }
127
128 /* Sync polarities. */
129 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
130 dcfg |= CS5530_DCFG_CRT_HSYNC_POL;
131 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
132 dcfg |= CS5530_DCFG_CRT_VSYNC_POL;
133
134 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
135}
136
137static int cs5530_blank_display(struct fb_info *info, int blank_mode)
138{
139 struct geodefb_par *par = info->par;
140 u32 dcfg;
141 int blank, hsync, vsync;
142
143 switch (blank_mode) {
144 case FB_BLANK_UNBLANK:
145 blank = 0; hsync = 1; vsync = 1;
146 break;
147 case FB_BLANK_NORMAL:
148 blank = 1; hsync = 1; vsync = 1;
149 break;
150 case FB_BLANK_VSYNC_SUSPEND:
151 blank = 1; hsync = 1; vsync = 0;
152 break;
153 case FB_BLANK_HSYNC_SUSPEND:
154 blank = 1; hsync = 0; vsync = 1;
155 break;
156 case FB_BLANK_POWERDOWN:
157 blank = 1; hsync = 0; vsync = 0;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
164
165 dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN
166 | CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN
167 | CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN);
168
169 if (par->enable_crt) {
170 if (!blank)
171 dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN;
172 if (hsync)
173 dcfg |= CS5530_DCFG_HSYNC_EN;
174 if (vsync)
175 dcfg |= CS5530_DCFG_VSYNC_EN;
176 }
177 if (par->panel_x > 0) {
178 if (!blank)
179 dcfg |= CS5530_DCFG_FP_DATA_EN;
180 if (hsync && vsync)
181 dcfg |= CS5530_DCFG_FP_PWR_EN;
182 }
183
184 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
185
186 return 0;
187}
188
189struct geode_vid_ops cs5530_vid_ops = {
190 .set_dclk = cs5530_set_dclk_frequency,
191 .configure_display = cs5530_configure_display,
192 .blank_display = cs5530_blank_display,
193};
diff --git a/drivers/video/fbdev/geode/video_cs5530.h b/drivers/video/fbdev/geode/video_cs5530.h
new file mode 100644
index 000000000000..56cecca7f1ce
--- /dev/null
+++ b/drivers/video/fbdev/geode/video_cs5530.h
@@ -0,0 +1,75 @@
1/*
2 * drivers/video/geode/video_cs5530.h
3 * -- CS5530 video device
4 *
5 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 *
7 * Based on AMD's original 2.4 driver:
8 * Copyright (C) 2004 Advanced Micro Devices, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15#ifndef __VIDEO_CS5530_H__
16#define __VIDEO_CS5530_H__
17
18extern struct geode_vid_ops cs5530_vid_ops;
19
20/* CS5530 Video device registers */
21
22#define CS5530_VIDEO_CONFIG 0x0000
23# define CS5530_VCFG_VID_EN 0x00000001
24# define CS5530_VCFG_VID_REG_UPDATE 0x00000002
25# define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
26# define CS5530_VCFG_8_BIT_4_2_0 0x00000004
27# define CS5530_VCFG_16_BIT_4_2_0 0x00000008
28# define CS5530_VCFG_GV_SEL 0x00000010
29# define CS5530_VCFG_CSC_BYPASS 0x00000020
30# define CS5530_VCFG_X_FILTER_EN 0x00000040
31# define CS5530_VCFG_Y_FILTER_EN 0x00000080
32# define CS5530_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00
33# define CS5530_VCFG_INIT_READ_MASK 0x01FF0000
34# define CS5530_VCFG_EARLY_VID_RDY 0x02000000
35# define CS5530_VCFG_LINE_SIZE_UPPER 0x08000000
36# define CS5530_VCFG_4_2_0_MODE 0x10000000
37# define CS5530_VCFG_16_BIT_EN 0x20000000
38# define CS5530_VCFG_HIGH_SPD_INT 0x40000000
39
40#define CS5530_DISPLAY_CONFIG 0x0004
41# define CS5530_DCFG_DIS_EN 0x00000001
42# define CS5530_DCFG_HSYNC_EN 0x00000002
43# define CS5530_DCFG_VSYNC_EN 0x00000004
44# define CS5530_DCFG_DAC_BL_EN 0x00000008
45# define CS5530_DCFG_DAC_PWR_EN 0x00000020
46# define CS5530_DCFG_FP_PWR_EN 0x00000040
47# define CS5530_DCFG_FP_DATA_EN 0x00000080
48# define CS5530_DCFG_CRT_HSYNC_POL 0x00000100
49# define CS5530_DCFG_CRT_VSYNC_POL 0x00000200
50# define CS5530_DCFG_FP_HSYNC_POL 0x00000400
51# define CS5530_DCFG_FP_VSYNC_POL 0x00000800
52# define CS5530_DCFG_XGA_FP 0x00001000
53# define CS5530_DCFG_FP_DITH_EN 0x00002000
54# define CS5530_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
55# define CS5530_DCFG_CRT_SYNC_SKW_INIT 0x00010000
56# define CS5530_DCFG_PWR_SEQ_DLY_MASK 0x000E0000
57# define CS5530_DCFG_PWR_SEQ_DLY_INIT 0x00080000
58# define CS5530_DCFG_VG_CK 0x00100000
59# define CS5530_DCFG_GV_PAL_BYP 0x00200000
60# define CS5530_DCFG_DDC_SCL 0x00400000
61# define CS5530_DCFG_DDC_SDA 0x00800000
62# define CS5530_DCFG_DDC_OE 0x01000000
63# define CS5530_DCFG_16_BIT_EN 0x02000000
64
65#define CS5530_VIDEO_X_POS 0x0008
66#define CS5530_VIDEO_Y_POS 0x000C
67#define CS5530_VIDEO_SCALE 0x0010
68#define CS5530_VIDEO_COLOR_KEY 0x0014
69#define CS5530_VIDEO_COLOR_MASK 0x0018
70#define CS5530_PALETTE_ADDRESS 0x001C
71#define CS5530_PALETTE_DATA 0x0020
72#define CS5530_DOT_CLK_CONFIG 0x0024
73#define CS5530_CRCSIG_TFT_TV 0x0028
74
75#endif /* !__VIDEO_CS5530_H__ */
diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
new file mode 100644
index 000000000000..6082f653c68a
--- /dev/null
+++ b/drivers/video/fbdev/geode/video_gx.c
@@ -0,0 +1,349 @@
1/*
2 * Geode GX video processor device.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/fb.h>
15#include <linux/delay.h>
16#include <asm/io.h>
17#include <asm/delay.h>
18#include <asm/msr.h>
19#include <linux/cs5535.h>
20
21#include "gxfb.h"
22
23
24/*
25 * Tables of register settings for various DOTCLKs.
26 */
27struct gx_pll_entry {
28 long pixclock; /* ps */
29 u32 sys_rstpll_bits;
30 u32 dotpll_value;
31};
32
33#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
34#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
35#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
36
37static const struct gx_pll_entry gx_pll_table_48MHz[] = {
38 { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
39 { 39721, 0, 0x00000037 }, /* 25.1750 */
40 { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
41 { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
42 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
43 { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
44 { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
45 { 22271, 0, 0x00000063 }, /* 44.9000 */
46 { 20202, 0, 0x0000054B }, /* 49.5000 */
47 { 20000, 0, 0x0000026E }, /* 50.0000 */
48 { 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
49 { 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
50 { 17777, 0, 0x00000577 }, /* 56.2500 */
51 { 17733, 0, 0x000007F7 }, /* 56.3916 */
52 { 17653, 0, 0x0000057B }, /* 56.6444 */
53 { 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
54 { 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
55 { 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
56 { 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
57 { 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
58 { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
59 { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
60 { 13333, 0, 0x00000052 }, /* 75.0000 */
61 { 12698, 0, 0x00000056 }, /* 78.7500 */
62 { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
63 { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
64 { 10582, 0, 0x000002D2 }, /* 94.5000 */
65 { 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
66 { 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
67 { 9259, 0, 0x000007E2 }, /* 108.0000 */
68 { 8888, 0, 0x000007F6 }, /* 112.5000 */
69 { 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
70 { 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
71 { 6349, 0, 0x00000055 }, /* 157.5000 */
72 { 6172, 0, 0x000009C1 }, /* 162.0000 */
73 { 5787, PREMULT2, 0x0000002D }, /* 172.798 */
74 { 5698, 0, 0x000002C1 }, /* 175.5000 */
75 { 5291, 0, 0x000002D1 }, /* 189.0000 */
76 { 4938, 0, 0x00000551 }, /* 202.5000 */
77 { 4357, 0, 0x0000057D }, /* 229.5000 */
78};
79
80static const struct gx_pll_entry gx_pll_table_14MHz[] = {
81 { 39721, 0, 0x00000037 }, /* 25.1750 */
82 { 35308, 0, 0x00000B7B }, /* 28.3220 */
83 { 31746, 0, 0x000004D3 }, /* 31.5000 */
84 { 27777, 0, 0x00000BE3 }, /* 36.0000 */
85 { 26666, 0, 0x0000074F }, /* 37.5000 */
86 { 25000, 0, 0x0000050B }, /* 40.0000 */
87 { 22271, 0, 0x00000063 }, /* 44.9000 */
88 { 20202, 0, 0x0000054B }, /* 49.5000 */
89 { 20000, 0, 0x0000026E }, /* 50.0000 */
90 { 19860, 0, 0x000007C3 }, /* 50.3500 */
91 { 18518, 0, 0x000007E3 }, /* 54.0000 */
92 { 17777, 0, 0x00000577 }, /* 56.2500 */
93 { 17733, 0, 0x000002FB }, /* 56.3916 */
94 { 17653, 0, 0x0000057B }, /* 56.6444 */
95 { 16949, 0, 0x0000058B }, /* 59.0000 */
96 { 15873, 0, 0x0000095E }, /* 63.0000 */
97 { 15384, 0, 0x0000096A }, /* 65.0000 */
98 { 14814, 0, 0x00000BC2 }, /* 67.5000 */
99 { 14124, 0, 0x0000098A }, /* 70.8000 */
100 { 13888, 0, 0x00000BE2 }, /* 72.0000 */
101 { 13333, 0, 0x00000052 }, /* 75.0000 */
102 { 12698, 0, 0x00000056 }, /* 78.7500 */
103 { 12500, 0, 0x0000050A }, /* 80.0000 */
104 { 11135, 0, 0x0000078E }, /* 89.8000 */
105 { 10582, 0, 0x000002D2 }, /* 94.5000 */
106 { 10101, 0, 0x000011F6 }, /* 99.0000 */
107 { 10000, 0, 0x0000054E }, /* 100.0000 */
108 { 9259, 0, 0x000007E2 }, /* 108.0000 */
109 { 8888, 0, 0x000002FA }, /* 112.5000 */
110 { 7692, 0, 0x00000BB1 }, /* 130.0000 */
111 { 7407, 0, 0x00000975 }, /* 135.0000 */
112 { 6349, 0, 0x00000055 }, /* 157.5000 */
113 { 6172, 0, 0x000009C1 }, /* 162.0000 */
114 { 5698, 0, 0x000002C1 }, /* 175.5000 */
115 { 5291, 0, 0x00000539 }, /* 189.0000 */
116 { 4938, 0, 0x00000551 }, /* 202.5000 */
117 { 4357, 0, 0x0000057D }, /* 229.5000 */
118};
119
120void gx_set_dclk_frequency(struct fb_info *info)
121{
122 const struct gx_pll_entry *pll_table;
123 int pll_table_len;
124 int i, best_i;
125 long min, diff;
126 u64 dotpll, sys_rstpll;
127 int timeout = 1000;
128
129 /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
130 if (cpu_data(0).x86_mask == 1) {
131 pll_table = gx_pll_table_14MHz;
132 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
133 } else {
134 pll_table = gx_pll_table_48MHz;
135 pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
136 }
137
138 /* Search the table for the closest pixclock. */
139 best_i = 0;
140 min = abs(pll_table[0].pixclock - info->var.pixclock);
141 for (i = 1; i < pll_table_len; i++) {
142 diff = abs(pll_table[i].pixclock - info->var.pixclock);
143 if (diff < min) {
144 min = diff;
145 best_i = i;
146 }
147 }
148
149 rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
150 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
151
152 /* Program new M, N and P. */
153 dotpll &= 0x00000000ffffffffull;
154 dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
155 dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
156 dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
157
158 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
159
160 /* Program dividers. */
161 sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
162 | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
163 | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
164 sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
165
166 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
167
168 /* Clear reset bit to start PLL. */
169 dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
170 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
171
172 /* Wait for LOCK bit. */
173 do {
174 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
175 } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
176}
177
178static void
179gx_configure_tft(struct fb_info *info)
180{
181 struct gxfb_par *par = info->par;
182 unsigned long val;
183 unsigned long fp;
184
185 /* Set up the DF pad select MSR */
186
187 rdmsrl(MSR_GX_MSR_PADSEL, val);
188 val &= ~MSR_GX_MSR_PADSEL_MASK;
189 val |= MSR_GX_MSR_PADSEL_TFT;
190 wrmsrl(MSR_GX_MSR_PADSEL, val);
191
192 /* Turn off the panel */
193
194 fp = read_fp(par, FP_PM);
195 fp &= ~FP_PM_P;
196 write_fp(par, FP_PM, fp);
197
198 /* Set timing 1 */
199
200 fp = read_fp(par, FP_PT1);
201 fp &= FP_PT1_VSIZE_MASK;
202 fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
203 write_fp(par, FP_PT1, fp);
204
205 /* Timing 2 */
206 /* Set bits that are always on for TFT */
207
208 fp = 0x0F100000;
209
210 /* Configure sync polarity */
211
212 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
213 fp |= FP_PT2_VSP;
214
215 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
216 fp |= FP_PT2_HSP;
217
218 write_fp(par, FP_PT2, fp);
219
220 /* Set the dither control */
221 write_fp(par, FP_DFC, FP_DFC_NFI);
222
223 /* Enable the FP data and power (in case the BIOS didn't) */
224
225 fp = read_vp(par, VP_DCFG);
226 fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
227 write_vp(par, VP_DCFG, fp);
228
229 /* Unblank the panel */
230
231 fp = read_fp(par, FP_PM);
232 fp |= FP_PM_P;
233 write_fp(par, FP_PM, fp);
234}
235
236void gx_configure_display(struct fb_info *info)
237{
238 struct gxfb_par *par = info->par;
239 u32 dcfg, misc;
240
241 /* Write the display configuration */
242 dcfg = read_vp(par, VP_DCFG);
243
244 /* Disable hsync and vsync */
245 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
246 write_vp(par, VP_DCFG, dcfg);
247
248 /* Clear bits from existing mode. */
249 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
250 | VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
251 | VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
252
253 /* Set default sync skew. */
254 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
255
256 /* Enable hsync and vsync. */
257 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
258
259 misc = read_vp(par, VP_MISC);
260
261 /* Disable gamma correction */
262 misc |= VP_MISC_GAM_EN;
263
264 if (par->enable_crt) {
265
266 /* Power up the CRT DACs */
267 misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
268 write_vp(par, VP_MISC, misc);
269
270 /* Only change the sync polarities if we are running
271 * in CRT mode. The FP polarities will be handled in
272 * gxfb_configure_tft */
273 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
274 dcfg |= VP_DCFG_CRT_HSYNC_POL;
275 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
276 dcfg |= VP_DCFG_CRT_VSYNC_POL;
277 } else {
278 /* Power down the CRT DACs if in FP mode */
279 misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
280 write_vp(par, VP_MISC, misc);
281 }
282
283 /* Enable the display logic */
284 /* Set up the DACS to blank normally */
285
286 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
287
288 /* Enable the external DAC VREF? */
289
290 write_vp(par, VP_DCFG, dcfg);
291
292 /* Set up the flat panel (if it is enabled) */
293
294 if (par->enable_crt == 0)
295 gx_configure_tft(info);
296}
297
298int gx_blank_display(struct fb_info *info, int blank_mode)
299{
300 struct gxfb_par *par = info->par;
301 u32 dcfg, fp_pm;
302 int blank, hsync, vsync, crt;
303
304 /* CRT power saving modes. */
305 switch (blank_mode) {
306 case FB_BLANK_UNBLANK:
307 blank = 0; hsync = 1; vsync = 1; crt = 1;
308 break;
309 case FB_BLANK_NORMAL:
310 blank = 1; hsync = 1; vsync = 1; crt = 1;
311 break;
312 case FB_BLANK_VSYNC_SUSPEND:
313 blank = 1; hsync = 1; vsync = 0; crt = 1;
314 break;
315 case FB_BLANK_HSYNC_SUSPEND:
316 blank = 1; hsync = 0; vsync = 1; crt = 1;
317 break;
318 case FB_BLANK_POWERDOWN:
319 blank = 1; hsync = 0; vsync = 0; crt = 0;
320 break;
321 default:
322 return -EINVAL;
323 }
324 dcfg = read_vp(par, VP_DCFG);
325 dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
326 VP_DCFG_CRT_EN);
327 if (!blank)
328 dcfg |= VP_DCFG_DAC_BL_EN;
329 if (hsync)
330 dcfg |= VP_DCFG_HSYNC_EN;
331 if (vsync)
332 dcfg |= VP_DCFG_VSYNC_EN;
333 if (crt)
334 dcfg |= VP_DCFG_CRT_EN;
335 write_vp(par, VP_DCFG, dcfg);
336
337 /* Power on/off flat panel. */
338
339 if (par->enable_crt == 0) {
340 fp_pm = read_fp(par, FP_PM);
341 if (blank_mode == FB_BLANK_POWERDOWN)
342 fp_pm &= ~FP_PM_P;
343 else
344 fp_pm |= FP_PM_P;
345 write_fp(par, FP_PM, fp_pm);
346 }
347
348 return 0;
349}
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-10 06:43:37 -0400