diff options
Diffstat (limited to 'drivers/video/aty/radeon_base.c')
-rw-r--r-- | drivers/video/aty/radeon_base.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c index 9a5821c65ebf..d0f1a7fc2c9d 100644 --- a/drivers/video/aty/radeon_base.c +++ b/drivers/video/aty/radeon_base.c | |||
@@ -852,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var, | |||
852 | if (rinfo->asleep) | 852 | if (rinfo->asleep) |
853 | return 0; | 853 | return 0; |
854 | 854 | ||
855 | radeon_fifo_wait(2); | ||
855 | OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) | 856 | OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) |
856 | * var->bits_per_pixel / 8) & ~7); | 857 | * var->bits_per_pixel / 8) & ~7); |
857 | return 0; | 858 | return 0; |
@@ -881,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, | |||
881 | if (rc) | 882 | if (rc) |
882 | return rc; | 883 | return rc; |
883 | 884 | ||
885 | radeon_fifo_wait(2); | ||
884 | if (value & 0x01) { | 886 | if (value & 0x01) { |
885 | tmp = INREG(LVDS_GEN_CNTL); | 887 | tmp = INREG(LVDS_GEN_CNTL); |
886 | 888 | ||
@@ -938,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) | |||
938 | if (rinfo->lock_blank) | 940 | if (rinfo->lock_blank) |
939 | return 0; | 941 | return 0; |
940 | 942 | ||
941 | radeon_engine_idle(rinfo); | 943 | radeon_engine_idle(); |
942 | 944 | ||
943 | val = INREG(CRTC_EXT_CNTL); | 945 | val = INREG(CRTC_EXT_CNTL); |
944 | val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | | 946 | val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | |
@@ -1046,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info) | |||
1046 | 1048 | ||
1047 | if (rinfo->asleep) | 1049 | if (rinfo->asleep) |
1048 | return 0; | 1050 | return 0; |
1049 | 1051 | ||
1050 | return radeon_screen_blank(rinfo, blank, 0); | 1052 | return radeon_screen_blank(rinfo, blank, 0); |
1051 | } | 1053 | } |
1052 | 1054 | ||
@@ -1072,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, | |||
1072 | pindex = regno; | 1074 | pindex = regno; |
1073 | 1075 | ||
1074 | if (!rinfo->asleep) { | 1076 | if (!rinfo->asleep) { |
1077 | radeon_fifo_wait(9); | ||
1078 | |||
1075 | if (rinfo->bpp == 16) { | 1079 | if (rinfo->bpp == 16) { |
1076 | pindex = regno * 8; | 1080 | pindex = regno * 8; |
1077 | 1081 | ||
@@ -1240,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg | |||
1240 | { | 1244 | { |
1241 | int i; | 1245 | int i; |
1242 | 1246 | ||
1247 | radeon_fifo_wait(20); | ||
1248 | |||
1243 | /* Workaround from XFree */ | 1249 | /* Workaround from XFree */ |
1244 | if (rinfo->is_mobility) { | 1250 | if (rinfo->is_mobility) { |
1245 | /* A temporal workaround for the occational blanking on certain laptop | 1251 | /* A temporal workaround for the occational blanking on certain laptop |
@@ -1335,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data) | |||
1335 | { | 1341 | { |
1336 | struct radeonfb_info *rinfo = (struct radeonfb_info *)data; | 1342 | struct radeonfb_info *rinfo = (struct radeonfb_info *)data; |
1337 | 1343 | ||
1338 | radeon_engine_idle(rinfo); | 1344 | radeon_engine_idle(); |
1339 | 1345 | ||
1340 | OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); | 1346 | OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); |
1341 | } | 1347 | } |
@@ -1353,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, | |||
1353 | if (nomodeset) | 1359 | if (nomodeset) |
1354 | return; | 1360 | return; |
1355 | 1361 | ||
1356 | radeon_engine_idle(rinfo); | ||
1357 | |||
1358 | if (!regs_only) | 1362 | if (!regs_only) |
1359 | radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); | 1363 | radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); |
1360 | 1364 | ||
1365 | radeon_fifo_wait(31); | ||
1361 | for (i=0; i<10; i++) | 1366 | for (i=0; i<10; i++) |
1362 | OUTREG(common_regs[i].reg, common_regs[i].val); | 1367 | OUTREG(common_regs[i].reg, common_regs[i].val); |
1363 | 1368 | ||
@@ -1385,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, | |||
1385 | radeon_write_pll_regs(rinfo, mode); | 1390 | radeon_write_pll_regs(rinfo, mode); |
1386 | 1391 | ||
1387 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | 1392 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { |
1393 | radeon_fifo_wait(10); | ||
1388 | OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); | 1394 | OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); |
1389 | OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); | 1395 | OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); |
1390 | OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); | 1396 | OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); |
@@ -1399,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, | |||
1399 | if (!regs_only) | 1405 | if (!regs_only) |
1400 | radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); | 1406 | radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); |
1401 | 1407 | ||
1408 | radeon_fifo_wait(2); | ||
1402 | OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); | 1409 | OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); |
1403 | 1410 | ||
1404 | return; | 1411 | return; |
@@ -1549,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info) | |||
1549 | /* We always want engine to be idle on a mode switch, even | 1556 | /* We always want engine to be idle on a mode switch, even |
1550 | * if we won't actually change the mode | 1557 | * if we won't actually change the mode |
1551 | */ | 1558 | */ |
1552 | radeon_engine_idle(rinfo); | 1559 | radeon_engine_idle(); |
1553 | 1560 | ||
1554 | hSyncStart = mode->xres + mode->right_margin; | 1561 | hSyncStart = mode->xres + mode->right_margin; |
1555 | hSyncEnd = hSyncStart + mode->hsync_len; | 1562 | hSyncEnd = hSyncStart + mode->hsync_len; |
@@ -1844,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info) | |||
1844 | return 0; | 1851 | return 0; |
1845 | } | 1852 | } |
1846 | 1853 | ||
1854 | |||
1847 | static struct fb_ops radeonfb_ops = { | 1855 | static struct fb_ops radeonfb_ops = { |
1848 | .owner = THIS_MODULE, | 1856 | .owner = THIS_MODULE, |
1849 | .fb_check_var = radeonfb_check_var, | 1857 | .fb_check_var = radeonfb_check_var, |
@@ -1867,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo) | |||
1867 | info->par = rinfo; | 1875 | info->par = rinfo; |
1868 | info->pseudo_palette = rinfo->pseudo_palette; | 1876 | info->pseudo_palette = rinfo->pseudo_palette; |
1869 | info->flags = FBINFO_DEFAULT | 1877 | info->flags = FBINFO_DEFAULT |
1870 | | FBINFO_HWACCEL_IMAGEBLIT | ||
1871 | | FBINFO_HWACCEL_COPYAREA | 1878 | | FBINFO_HWACCEL_COPYAREA |
1872 | | FBINFO_HWACCEL_FILLRECT | 1879 | | FBINFO_HWACCEL_FILLRECT |
1873 | | FBINFO_HWACCEL_XPAN | 1880 | | FBINFO_HWACCEL_XPAN |
@@ -1999,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) | |||
1999 | u32 tom = INREG(NB_TOM); | 2006 | u32 tom = INREG(NB_TOM); |
2000 | tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); | 2007 | tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); |
2001 | 2008 | ||
2009 | radeon_fifo_wait(6); | ||
2002 | OUTREG(MC_FB_LOCATION, tom); | 2010 | OUTREG(MC_FB_LOCATION, tom); |
2003 | OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); | 2011 | OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); |
2004 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); | 2012 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); |