16 files changed, 1164 insertions, 149 deletions

diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index cfd38edfcf9e..341a37a469bd 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -45,6 +45,9 @@ config USB_MUSB_SOC
 comment "DaVinci 35x and 644x USB support"
         depends on USB_MUSB_HDRC && ARCH_DAVINCI_DMx
 
+comment "DA8xx/OMAP-L1x USB support"
+        depends on USB_MUSB_HDRC && ARCH_DAVINCI_DA8XX
+
 comment "OMAP 243x high speed USB support"
         depends on USB_MUSB_HDRC && ARCH_OMAP2430
 
@@ -57,6 +60,17 @@ comment "OMAP 44xx high speed USB support"
 comment "Blackfin high speed USB Support"
         depends on USB_MUSB_HDRC && ((BF54x && !BF544) || (BF52x && !BF522 && !BF523))
 
+config USB_MUSB_AM35X
+        bool
+        depends on USB_MUSB_HDRC && !ARCH_OMAP2430 && !ARCH_OMAP4
+        select NOP_USB_XCEIV
+        default MACH_OMAP3517EVM
+        help
+          Select this option if your platform is based on AM35x. As
+          AM35x has an updated MUSB with CPPI4.1 DMA so this config
+          is introduced to differentiate musb ip between OMAP3x and
+          AM35x platforms.
+
 config USB_TUSB6010
         boolean "TUSB 6010 support"
         depends on USB_MUSB_HDRC && !USB_MUSB_SOC
@@ -144,7 +158,7 @@ config USB_MUSB_HDRC_HCD
 config MUSB_PIO_ONLY
         bool 'Disable DMA (always use PIO)'
         depends on USB_MUSB_HDRC
-        default y if USB_TUSB6010
+        default USB_TUSB6010 || ARCH_DAVINCI_DA8XX || USB_MUSB_AM35X
         help
           All data is copied between memory and FIFO by the CPU.
           DMA controllers are ignored.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 9705f716386e..ce164e8998d8 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -2,49 +2,27 @@
 # for USB OTG silicon based on Mentor Graphics INVENTRA designs
 #
 
-musb_hdrc-objs := musb_core.o
+ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG
 
-obj-$(CONFIG_USB_MUSB_HDRC)     += musb_hdrc.o
+obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
 
-ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
-        musb_hdrc-objs  += davinci.o
-endif
-
-ifeq ($(CONFIG_USB_TUSB6010),y)
-        musb_hdrc-objs  += tusb6010.o
-endif
-
-ifeq ($(CONFIG_ARCH_OMAP2430),y)
-        musb_hdrc-objs  += omap2430.o
-endif
-
-ifeq ($(CONFIG_ARCH_OMAP3430),y)
-        musb_hdrc-objs  += omap2430.o
-endif
-
-ifeq ($(CONFIG_ARCH_OMAP4),y)
-        musb_hdrc-objs  += omap2430.o
-endif
-
-ifeq ($(CONFIG_BF54x),y)
-        musb_hdrc-objs  += blackfin.o
-endif
+musb_hdrc-y := musb_core.o
 
-ifeq ($(CONFIG_BF52x),y)
-        musb_hdrc-objs  += blackfin.o
-endif
-
-ifeq ($(CONFIG_USB_GADGET_MUSB_HDRC),y)
-        musb_hdrc-objs          += musb_gadget_ep0.o musb_gadget.o
-endif
-
-ifeq ($(CONFIG_USB_MUSB_HDRC_HCD),y)
-        musb_hdrc-objs          += musb_virthub.o musb_host.o
-endif
-
-ifeq ($(CONFIG_DEBUG_FS),y)
-        musb_hdrc-objs          += musb_debugfs.o
+musb_hdrc-$(CONFIG_ARCH_DAVINCI_DMx)            += davinci.o
+musb_hdrc-$(CONFIG_ARCH_DAVINCI_DA8XX)          += da8xx.o
+musb_hdrc-$(CONFIG_USB_TUSB6010)                += tusb6010.o
+musb_hdrc-$(CONFIG_ARCH_OMAP2430)               += omap2430.o
+ifeq ($(CONFIG_USB_MUSB_AM35X),y)
+        musb_hdrc-$(CONFIG_ARCH_OMAP3430)       += am35x.o
+else
+        musb_hdrc-$(CONFIG_ARCH_OMAP3430)       += omap2430.o
 endif
+musb_hdrc-$(CONFIG_ARCH_OMAP4)                  += omap2430.o
+musb_hdrc-$(CONFIG_BF54x)                       += blackfin.o
+musb_hdrc-$(CONFIG_BF52x)                       += blackfin.o
+musb_hdrc-$(CONFIG_USB_GADGET_MUSB_HDRC)        += musb_gadget_ep0.o musb_gadget.o
+musb_hdrc-$(CONFIG_USB_MUSB_HDRC_HCD)           += musb_virthub.o musb_host.o
+musb_hdrc-$(CONFIG_DEBUG_FS)                    += musb_debugfs.o
 
 # the kconfig must guarantee that only one of the
 # possible I/O schemes will be enabled at a time ...
@@ -54,26 +32,17 @@ endif
 ifneq ($(CONFIG_MUSB_PIO_ONLY),y)
 
   ifeq ($(CONFIG_USB_INVENTRA_DMA),y)
-    musb_hdrc-objs              += musbhsdma.o
+    musb_hdrc-y                 += musbhsdma.o
 
   else
     ifeq ($(CONFIG_USB_TI_CPPI_DMA),y)
-      musb_hdrc-objs            += cppi_dma.o
+      musb_hdrc-y               += cppi_dma.o
 
     else
       ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
-        musb_hdrc-objs          += tusb6010_omap.o
+        musb_hdrc-y             += tusb6010_omap.o
 
       endif
     endif
   endif
 endif
-
-
-################################################################################
-
-# Debugging
-
-ifeq ($(CONFIG_USB_MUSB_DEBUG),y)
-        EXTRA_CFLAGS += -DDEBUG
-endif
diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
new file mode 100644
index 000000000000..b0aabf3a606f
--- /dev/null
+++ b/drivers/usb/musb/am35x.c
@@ -0,0 +1,524 @@
+/*
+ * Texas Instruments AM35x "glue layer"
+ *
+ * Copyright (c) 2010, by Texas Instruments
+ *
+ * Based on the DA8xx "glue layer" code.
+ * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ *
+ * The Inventra Controller Driver for Linux is free software; you
+ * can redistribute it and/or modify it under the terms of the GNU
+ * General Public License version 2 as published by the Free Software
+ * Foundation.
+ *
+ * The Inventra Controller Driver for Linux is distributed in
+ * the hope that it will be useful, but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with The Inventra Controller Driver for Linux ; if not,
+ * write to the Free Software Foundation, Inc., 59 Temple Place,
+ * Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/control.h>
+#include <plat/usb.h>
+
+#include "musb_core.h"
+
+/*
+ * AM35x specific definitions
+ */
+/* USB 2.0 OTG module registers */
+#define USB_REVISION_REG        0x00
+#define USB_CTRL_REG            0x04
+#define USB_STAT_REG            0x08
+#define USB_EMULATION_REG       0x0c
+/* 0x10 Reserved */
+#define USB_AUTOREQ_REG         0x14
+#define USB_SRP_FIX_TIME_REG    0x18
+#define USB_TEARDOWN_REG        0x1c
+#define EP_INTR_SRC_REG         0x20
+#define EP_INTR_SRC_SET_REG     0x24
+#define EP_INTR_SRC_CLEAR_REG   0x28
+#define EP_INTR_MASK_REG        0x2c
+#define EP_INTR_MASK_SET_REG    0x30
+#define EP_INTR_MASK_CLEAR_REG  0x34
+#define EP_INTR_SRC_MASKED_REG  0x38
+#define CORE_INTR_SRC_REG       0x40
+#define CORE_INTR_SRC_SET_REG   0x44
+#define CORE_INTR_SRC_CLEAR_REG 0x48
+#define CORE_INTR_MASK_REG      0x4c
+#define CORE_INTR_MASK_SET_REG  0x50
+#define CORE_INTR_MASK_CLEAR_REG 0x54
+#define CORE_INTR_SRC_MASKED_REG 0x58
+/* 0x5c Reserved */
+#define USB_END_OF_INTR_REG     0x60
+
+/* Control register bits */
+#define AM35X_SOFT_RESET_MASK   1
+
+/* USB interrupt register bits */
+#define AM35X_INTR_USB_SHIFT    16
+#define AM35X_INTR_USB_MASK     (0x1ff << AM35X_INTR_USB_SHIFT)
+#define AM35X_INTR_DRVVBUS      0x100
+#define AM35X_INTR_RX_SHIFT     16
+#define AM35X_INTR_TX_SHIFT     0
+#define AM35X_TX_EP_MASK        0xffff          /* EP0 + 15 Tx EPs */
+#define AM35X_RX_EP_MASK        0xfffe          /* 15 Rx EPs */
+#define AM35X_TX_INTR_MASK      (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
+#define AM35X_RX_INTR_MASK      (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
+
+#define USB_MENTOR_CORE_OFFSET  0x400
+
+static inline void phy_on(void)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(100);
+        u32 devconf2;
+
+        /*
+         * Start the on-chip PHY and its PLL.
+         */
+        devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+        devconf2 |= CONF2_PHY_PLLON;
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+
+        DBG(1, "Waiting for PHY clock good...\n");
+        while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
+                        & CONF2_PHYCLKGD)) {
+                cpu_relax();
+
+                if (time_after(jiffies, timeout)) {
+                        DBG(1, "musb PHY clock good timed out\n");
+                        break;
+                }
+        }
+}
+
+static inline void phy_off(void)
+{
+        u32 devconf2;
+
+        /*
+         * Power down the on-chip PHY.
+         */
+        devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        devconf2 &= ~CONF2_PHY_PLLON;
+        devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+}
+
+/*
+ * musb_platform_enable - enable interrupts
+ */
+void musb_platform_enable(struct musb *musb)
+{
+        void __iomem *reg_base = musb->ctrl_base;
+        u32 epmask;
+
+        /* Workaround: setup IRQs through both register sets. */
+        epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
+               ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
+
+        musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
+        musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
+
+        /* Force the DRVVBUS IRQ so we can start polling for ID change. */
+        if (is_otg_enabled(musb))
+                musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
+                            AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
+}
+
+/*
+ * musb_platform_disable - disable HDRC and flush interrupts
+ */
+void musb_platform_disable(struct musb *musb)
+{
+        void __iomem *reg_base = musb->ctrl_base;
+
+        musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
+        musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
+                         AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
+        musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
+        musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
+}
+
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
+#define portstate(stmt)         stmt
+#else
+#define portstate(stmt)
+#endif
+
+static void am35x_set_vbus(struct musb *musb, int is_on)
+{
+        WARN_ON(is_on && is_peripheral_active(musb));
+}
+
+#define POLL_SECONDS    2
+
+static struct timer_list otg_workaround;
+
+static void otg_timer(unsigned long _musb)
+{
+        struct musb             *musb = (void *)_musb;
+        void __iomem            *mregs = musb->mregs;
+        u8                      devctl;
+        unsigned long           flags;
+
+        /*
+         * We poll because AM35x's won't expose several OTG-critical
+         * status change events (from the transceiver) otherwise.
+         */
+        devctl = musb_readb(mregs, MUSB_DEVCTL);
+        DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+
+        spin_lock_irqsave(&musb->lock, flags);
+        switch (musb->xceiv->state) {
+        case OTG_STATE_A_WAIT_BCON:
+                devctl &= ~MUSB_DEVCTL_SESSION;
+                musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+                devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+                if (devctl & MUSB_DEVCTL_BDEVICE) {
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
+                        MUSB_DEV_MODE(musb);
+                } else {
+                        musb->xceiv->state = OTG_STATE_A_IDLE;
+                        MUSB_HST_MODE(musb);
+                }
+                break;
+        case OTG_STATE_A_WAIT_VFALL:
+                musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+                musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
+                            MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
+                break;
+        case OTG_STATE_B_IDLE:
+                if (!is_peripheral_enabled(musb))
+                        break;
+
+                devctl = musb_readb(mregs, MUSB_DEVCTL);
+                if (devctl & MUSB_DEVCTL_BDEVICE)
+                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+                else
+                        musb->xceiv->state = OTG_STATE_A_IDLE;
+                break;
+        default:
+                break;
+        }
+        spin_unlock_irqrestore(&musb->lock, flags);
+}
+
+void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
+{
+        static unsigned long last_timer;
+
+        if (!is_otg_enabled(musb))
+                return;
+
+        if (timeout == 0)
+                timeout = jiffies + msecs_to_jiffies(3);
+
+        /* Never idle if active, or when VBUS timeout is not set as host */
+        if (musb->is_active || (musb->a_wait_bcon == 0 &&
+                                musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
+                DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+                del_timer(&otg_workaround);
+                last_timer = jiffies;
+                return;
+        }
+
+        if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
+                DBG(4, "Longer idle timer already pending, ignoring...\n");
+                return;
+        }
+        last_timer = timeout;
+
+        DBG(4, "%s inactive, starting idle timer for %u ms\n",
+            otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
+        mod_timer(&otg_workaround, timeout);
+}
+
+static irqreturn_t am35x_interrupt(int irq, void *hci)
+{
+        struct musb  *musb = hci;
+        void __iomem *reg_base = musb->ctrl_base;
+        unsigned long flags;
+        irqreturn_t ret = IRQ_NONE;
+        u32 epintr, usbintr, lvl_intr;
+
+        spin_lock_irqsave(&musb->lock, flags);
+
+        /* Get endpoint interrupts */
+        epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
+
+        if (epintr) {
+                musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
+
+                musb->int_rx =
+                        (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
+                musb->int_tx =
+                        (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
+        }
+
+        /* Get usb core interrupts */
+        usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
+        if (!usbintr && !epintr)
+                goto eoi;
+
+        if (usbintr) {
+                musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
+
+                musb->int_usb =
+                        (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
+        }
+        /*
+         * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
+         * AM35x's missing ID change IRQ.  We need an ID change IRQ to
+         * switch appropriately between halves of the OTG state machine.
+         * Managing DEVCTL.SESSION per Mentor docs requires that we know its
+         * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
+         * Also, DRVVBUS pulses for SRP (but not at 5V) ...
+         */
+        if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
+                int drvvbus = musb_readl(reg_base, USB_STAT_REG);
+                void __iomem *mregs = musb->mregs;
+                u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
+                int err;
+
+                err = is_host_enabled(musb) && (musb->int_usb &
+                                                MUSB_INTR_VBUSERROR);
+                if (err) {
+                        /*
+                         * The Mentor core doesn't debounce VBUS as needed
+                         * to cope with device connect current spikes. This
+                         * means it's not uncommon for bus-powered devices
+                         * to get VBUS errors during enumeration.
+                         *
+                         * This is a workaround, but newer RTL from Mentor
+                         * seems to allow a better one: "re"-starting sessions
+                         * without waiting for VBUS to stop registering in
+                         * devctl.
+                         */
+                        musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+                        WARNING("VBUS error workaround (delay coming)\n");
+                } else if (is_host_enabled(musb) && drvvbus) {
+                        MUSB_HST_MODE(musb);
+                        musb->xceiv->default_a = 1;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+                        portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+                        del_timer(&otg_workaround);
+                } else {
+                        musb->is_active = 0;
+                        MUSB_DEV_MODE(musb);
+                        musb->xceiv->default_a = 0;
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
+                        portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+                }
+
+                /* NOTE: this must complete power-on within 100 ms. */
+                DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+                                drvvbus ? "on" : "off",
+                                otg_state_string(musb),
+                                err ? " ERROR" : "",
+                                devctl);
+                ret = IRQ_HANDLED;
+        }
+
+        if (musb->int_tx || musb->int_rx || musb->int_usb)
+                ret |= musb_interrupt(musb);
+
+eoi:
+        /* EOI needs to be written for the IRQ to be re-asserted. */
+        if (ret == IRQ_HANDLED || epintr || usbintr) {
+                /* clear level interrupt */
+                lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+                lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
+                omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
+                /* write EOI */
+                musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
+        }
+
+        /* Poll for ID change */
+        if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+                mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+
+        spin_unlock_irqrestore(&musb->lock, flags);
+
+        return ret;
+}
+
+int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+{
+        u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        devconf2 &= ~CONF2_OTGMODE;
+        switch (musb_mode) {
+#ifdef  CONFIG_USB_MUSB_HDRC_HCD
+        case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
+                devconf2 |= CONF2_FORCE_HOST;
+                break;
+#endif
+#ifdef  CONFIG_USB_GADGET_MUSB_HDRC
+        case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
+                devconf2 |= CONF2_FORCE_DEVICE;
+                break;
+#endif
+#ifdef  CONFIG_USB_MUSB_OTG
+        case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
+                devconf2 |= CONF2_NO_OVERRIDE;
+                break;
+#endif
+        default:
+                DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
+        }
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+        return 0;
+}
+
+int __init musb_platform_init(struct musb *musb, void *board_data)
+{
+        void __iomem *reg_base = musb->ctrl_base;
+        u32 rev, lvl_intr, sw_reset;
+        int status;
+
+        musb->mregs += USB_MENTOR_CORE_OFFSET;
+
+        clk_enable(musb->clock);
+        DBG(2, "musb->clock=%lud\n", clk_get_rate(musb->clock));
+
+        musb->phy_clock = clk_get(musb->controller, "fck");
+        if (IS_ERR(musb->phy_clock)) {
+                status = PTR_ERR(musb->phy_clock);
+                goto exit0;
+        }
+        clk_enable(musb->phy_clock);
+        DBG(2, "musb->phy_clock=%lud\n", clk_get_rate(musb->phy_clock));
+
+        /* Returns zero if e.g. not clocked */
+        rev = musb_readl(reg_base, USB_REVISION_REG);
+        if (!rev) {
+                status = -ENODEV;
+                goto exit1;
+        }
+
+        usb_nop_xceiv_register();
+        musb->xceiv = otg_get_transceiver();
+        if (!musb->xceiv) {
+                status = -ENODEV;
+                goto exit1;
+        }
+
+        if (is_host_enabled(musb))
+                setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
+
+        musb->board_set_vbus = am35x_set_vbus;
+
+        /* Global reset */
+        sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+
+        sw_reset |= AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
+
+        sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
+
+        /* Reset the controller */
+        musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
+
+        /* Start the on-chip PHY and its PLL. */
+        phy_on();
+
+        msleep(5);
+
+        musb->isr = am35x_interrupt;
+
+        /* clear level interrupt */
+        lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
+        omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        return 0;
+exit1:
+        clk_disable(musb->phy_clock);
+        clk_put(musb->phy_clock);
+exit0:
+        clk_disable(musb->clock);
+        return status;
+}
+
+int musb_platform_exit(struct musb *musb)
+{
+        if (is_host_enabled(musb))
+                del_timer_sync(&otg_workaround);
+
+        phy_off();
+
+        otg_put_transceiver(musb->xceiv);
+        usb_nop_xceiv_unregister();
+
+        clk_disable(musb->clock);
+
+        clk_disable(musb->phy_clock);
+        clk_put(musb->phy_clock);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+void musb_platform_save_context(struct musb *musb,
+        struct musb_context_registers *musb_context)
+{
+        phy_off();
+}
+
+void musb_platform_restore_context(struct musb *musb,
+        struct musb_context_registers *musb_context)
+{
+        phy_on();
+}
+#endif
+
+/* AM35x supports only 32bit read operation */
+void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+{
+        void __iomem *fifo = hw_ep->fifo;
+        u32             val;
+        int             i;
+
+        /* Read for 32bit-aligned destination address */
+        if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
+                readsl(fifo, dst, len >> 2);
+                dst += len & ~0x03;
+                len &= 0x03;
+        }
+        /*
+         * Now read the remaining 1 to 3 byte or complete length if
+         * unaligned address.
+         */
+        if (len > 4) {
+                for (i = 0; i < (len >> 2); i++) {
+                        *(u32 *) dst = musb_readl(fifo, 0);
+                        dst += 4;
+                }
+                len &= 0x03;
+        }
+        if (len > 0) {
+                val = musb_readl(fifo, 0);
+                memcpy(dst, &val, len);
+        }
+}
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index b611420a8050..611a9d274363 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -342,8 +342,10 @@ int __init musb_platform_init(struct musb *musb, void *board_data)
 
         usb_nop_xceiv_register();
         musb->xceiv = otg_get_transceiver();
-        if (!musb->xceiv)
+        if (!musb->xceiv) {
+                gpio_free(musb->config->gpio_vrsel);
                 return -ENODEV;
+        }
 
         if (ANOMALY_05000346) {
                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
@@ -394,8 +396,9 @@ int __init musb_platform_init(struct musb *musb, void *board_data)
 
 int musb_platform_exit(struct musb *musb)
 {
-
         gpio_free(musb->config->gpio_vrsel);
 
+        otg_put_transceiver(musb->xceiv);
+        usb_nop_xceiv_unregister();
         return 0;
 }
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index 5ab5bb89bae3..f5a65ff0ac2b 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -1156,7 +1156,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
         struct musb_hw_ep       *hw_ep = NULL;
         u32                     rx, tx;
         int                     i, index;
-        unsigned long           flags;
+        unsigned long           uninitialized_var(flags);
 
         cppi = container_of(musb->dma_controller, struct cppi, controller);
         if (cppi->irq)
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
new file mode 100644
index 000000000000..84427bebbf62
--- /dev/null
+++ b/drivers/usb/musb/da8xx.c
@@ -0,0 +1,469 @@
+/*
+ * Texas Instruments DA8xx/OMAP-L1x "glue layer"
+ *
+ * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * Based on the DaVinci "glue layer" code.
+ * Copyright (C) 2005-2006 by Texas Instruments
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ *
+ * The Inventra Controller Driver for Linux is free software; you
+ * can redistribute it and/or modify it under the terms of the GNU
+ * General Public License version 2 as published by the Free Software
+ * Foundation.
+ *
+ * The Inventra Controller Driver for Linux is distributed in
+ * the hope that it will be useful, but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with The Inventra Controller Driver for Linux ; if not,
+ * write to the Free Software Foundation, Inc., 59 Temple Place,
+ * Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/da8xx.h>
+#include <mach/usb.h>
+
+#include "musb_core.h"
+
+/*
+ * DA8XX specific definitions
+ */
+
+/* USB 2.0 OTG module registers */
+#define DA8XX_USB_REVISION_REG  0x00
+#define DA8XX_USB_CTRL_REG      0x04
+#define DA8XX_USB_STAT_REG      0x08
+#define DA8XX_USB_EMULATION_REG 0x0c
+#define DA8XX_USB_MODE_REG      0x10    /* Transparent, CDC, [Generic] RNDIS */
+#define DA8XX_USB_AUTOREQ_REG   0x14
+#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
+#define DA8XX_USB_TEARDOWN_REG  0x1c
+#define DA8XX_USB_INTR_SRC_REG  0x20
+#define DA8XX_USB_INTR_SRC_SET_REG 0x24
+#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
+#define DA8XX_USB_INTR_MASK_REG 0x2c
+#define DA8XX_USB_INTR_MASK_SET_REG 0x30
+#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
+#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
+#define DA8XX_USB_END_OF_INTR_REG 0x3c
+#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
+
+/* Control register bits */
+#define DA8XX_SOFT_RESET_MASK   1
+
+#define DA8XX_USB_TX_EP_MASK    0x1f            /* EP0 + 4 Tx EPs */
+#define DA8XX_USB_RX_EP_MASK    0x1e            /* 4 Rx EPs */
+
+/* USB interrupt register bits */
+#define DA8XX_INTR_USB_SHIFT    16
+#define DA8XX_INTR_USB_MASK     (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
+                                        /* interrupts and DRVVBUS interrupt */
+#define DA8XX_INTR_DRVVBUS      0x100
+#define DA8XX_INTR_RX_SHIFT     8
+#define DA8XX_INTR_RX_MASK      (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
+#define DA8XX_INTR_TX_SHIFT     0
+#define DA8XX_INTR_TX_MASK      (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
+
+#define DA8XX_MENTOR_CORE_OFFSET 0x400
+
+#define CFGCHIP2        IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
+
+/*
+ * REVISIT (PM): we should be able to keep the PHY in low power mode most
+ * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
+ * and, when in host mode, autosuspending idle root ports... PHY_PLLON
+ * (overriding SUSPENDM?) then likely needs to stay off.
+ */
+
+static inline void phy_on(void)
+{
+        u32 cfgchip2 = __raw_readl(CFGCHIP2);
+
+        /*
+         * Start the on-chip PHY and its PLL.
+         */
+        cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
+        cfgchip2 |= CFGCHIP2_PHY_PLLON;
+        __raw_writel(cfgchip2, CFGCHIP2);
+
+        pr_info("Waiting for USB PHY clock good...\n");
+        while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
+                cpu_relax();
+}
+
+static inline void phy_off(void)
+{
+        u32 cfgchip2 = __raw_readl(CFGCHIP2);
+
+        /*
+         * Ensure that USB 1.1 reference clock is not being sourced from
+         * USB 2.0 PHY.  Otherwise do not power down the PHY.
+         */
+        if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
+             (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
+                pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
+                           "can't power it down\n");
+                return;
+        }
+
+        /*
+         * Power down the on-chip PHY.
+         */
+        cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
+        __raw_writel(cfgchip2, CFGCHIP2);
+}
+
+/*
+ * Because we don't set CTRL.UINT, it's "important" to:
+ *      - not read/write INTRUSB/INTRUSBE (except during
+ *        initial setup, as a workaround);
+ *      - use INTSET/INTCLR instead.
+ */
+
+/**
+ * musb_platform_enable - enable interrupts
+ */
+void musb_platform_enable(struct musb *musb)
+{
+        void __iomem *reg_base = musb->ctrl_base;
+        u32 mask;
+
+        /* Workaround: setup IRQs through both register sets. */
+        mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
+               ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
+               DA8XX_INTR_USB_MASK;
+        musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
+
+        /* Force the DRVVBUS IRQ so we can start polling for ID change. */
+        if (is_otg_enabled(musb))
+                musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
+                            DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
+}
+
+/**
+ * musb_platform_disable - disable HDRC and flush interrupts
+ */
+void musb_platform_disable(struct musb *musb)
+{
+        void __iomem *reg_base = musb->ctrl_base;
+
+        musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
+                    DA8XX_INTR_USB_MASK |
+                    DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
+        musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
+        musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+}
+
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
+#define portstate(stmt)         stmt
+#else
+#define portstate(stmt)
+#endif
+
+static void da8xx_set_vbus(struct musb *musb, int is_on)
+{
+        WARN_ON(is_on && is_peripheral_active(musb));
+}
+
+#define POLL_SECONDS    2
+
+static struct timer_list otg_workaround;
+
+static void otg_timer(unsigned long _musb)
+{
+        struct musb             *musb = (void *)_musb;
+        void __iomem            *mregs = musb->mregs;
+        u8                      devctl;
+        unsigned long           flags;
+
+        /*
+         * We poll because DaVinci's won't expose several OTG-critical
+         * status change events (from the transceiver) otherwise.
+         */
+        devctl = musb_readb(mregs, MUSB_DEVCTL);
+        DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+
+        spin_lock_irqsave(&musb->lock, flags);
+        switch (musb->xceiv->state) {
+        case OTG_STATE_A_WAIT_BCON:
+                devctl &= ~MUSB_DEVCTL_SESSION;
+                musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+                devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+                if (devctl & MUSB_DEVCTL_BDEVICE) {
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
+                        MUSB_DEV_MODE(musb);
+                } else {
+                        musb->xceiv->state = OTG_STATE_A_IDLE;
+                        MUSB_HST_MODE(musb);
+                }
+                break;
+        case OTG_STATE_A_WAIT_VFALL:
+                /*
+                 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
+                 * RTL seems to mis-handle session "start" otherwise (or in
+                 * our case "recover"), in routine "VBUS was valid by the time
+                 * VBUSERR got reported during enumeration" cases.
+                 */
+                if (devctl & MUSB_DEVCTL_VBUS) {
+                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+                        break;
+                }
+                musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+                musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
+                            MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
+                break;
+        case OTG_STATE_B_IDLE:
+                if (!is_peripheral_enabled(musb))
+                        break;
+
+                /*
+                 * There's no ID-changed IRQ, so we have no good way to tell
+                 * when to switch to the A-Default state machine (by setting
+                 * the DEVCTL.Session bit).
+                 *
+                 * Workaround:  whenever we're in B_IDLE, try setting the
+                 * session flag every few seconds.  If it works, ID was
+                 * grounded and we're now in the A-Default state machine.
+                 *
+                 * NOTE: setting the session flag is _supposed_ to trigger
+                 * SRP but clearly it doesn't.
+                 */
+                musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
+                devctl = musb_readb(mregs, MUSB_DEVCTL);
+                if (devctl & MUSB_DEVCTL_BDEVICE)
+                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+                else
+                        musb->xceiv->state = OTG_STATE_A_IDLE;
+                break;
+        default:
+                break;
+        }
+        spin_unlock_irqrestore(&musb->lock, flags);
+}
+
+void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
+{
+        static unsigned long last_timer;
+
+        if (!is_otg_enabled(musb))
+                return;
+
+        if (timeout == 0)
+                timeout = jiffies + msecs_to_jiffies(3);
+
+        /* Never idle if active, or when VBUS timeout is not set as host */
+        if (musb->is_active || (musb->a_wait_bcon == 0 &&
+                                musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
+                DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+                del_timer(&otg_workaround);
+                last_timer = jiffies;
+                return;
+        }
+
+        if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
+                DBG(4, "Longer idle timer already pending, ignoring...\n");
+                return;
+        }
+        last_timer = timeout;
+
+        DBG(4, "%s inactive, starting idle timer for %u ms\n",
+            otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
+        mod_timer(&otg_workaround, timeout);
+}
+
+static irqreturn_t da8xx_interrupt(int irq, void *hci)
+{
+        struct musb             *musb = hci;
+        void __iomem            *reg_base = musb->ctrl_base;
+        unsigned long           flags;
+        irqreturn_t             ret = IRQ_NONE;
+        u32                     status;
+
+        spin_lock_irqsave(&musb->lock, flags);
+
+        /*
+         * NOTE: DA8XX shadows the Mentor IRQs.  Don't manage them through
+         * the Mentor registers (except for setup), use the TI ones and EOI.
+         */
+
+        /* Acknowledge and handle non-CPPI interrupts */
+        status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
+        if (!status)
+                goto eoi;
+
+        musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
+        DBG(4, "USB IRQ %08x\n", status);
+
+        musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
+        musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
+        musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
+
+        /*
+         * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
+         * DA8xx's missing ID change IRQ.  We need an ID change IRQ to
+         * switch appropriately between halves of the OTG state machine.
+         * Managing DEVCTL.Session per Mentor docs requires that we know its
+         * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
+         * Also, DRVVBUS pulses for SRP (but not at 5 V)...
+         */
+        if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
+                int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
+                void __iomem *mregs = musb->mregs;
+                u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
+                int err;
+
+                err = is_host_enabled(musb) && (musb->int_usb &
+                                                MUSB_INTR_VBUSERROR);
+                if (err) {
+                        /*
+                         * The Mentor core doesn't debounce VBUS as needed
+                         * to cope with device connect current spikes. This
+                         * means it's not uncommon for bus-powered devices
+                         * to get VBUS errors during enumeration.
+                         *
+                         * This is a workaround, but newer RTL from Mentor
+                         * seems to allow a better one: "re"-starting sessions
+                         * without waiting for VBUS to stop registering in
+                         * devctl.
+                         */
+                        musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+                        WARNING("VBUS error workaround (delay coming)\n");
+                } else if (is_host_enabled(musb) && drvvbus) {
+                        MUSB_HST_MODE(musb);
+                        musb->xceiv->default_a = 1;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+                        portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+                        del_timer(&otg_workaround);
+                } else {
+                        musb->is_active = 0;
+                        MUSB_DEV_MODE(musb);
+                        musb->xceiv->default_a = 0;
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
+                        portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+                }
+
+                DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+                                drvvbus ? "on" : "off",
+                                otg_state_string(musb),
+                                err ? " ERROR" : "",
+                                devctl);
+                ret = IRQ_HANDLED;
+        }
+
+        if (musb->int_tx || musb->int_rx || musb->int_usb)
+                ret |= musb_interrupt(musb);
+
+ eoi:
+        /* EOI needs to be written for the IRQ to be re-asserted. */
+        if (ret == IRQ_HANDLED || status)
+                musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+
+        /* Poll for ID change */
+        if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+                mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+
+        spin_unlock_irqrestore(&musb->lock, flags);
+
+        return ret;
+}
+
+int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+{
+        u32 cfgchip2 = __raw_readl(CFGCHIP2);
+
+        cfgchip2 &= ~CFGCHIP2_OTGMODE;
+        switch (musb_mode) {
+#ifdef  CONFIG_USB_MUSB_HDRC_HCD
+        case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
+                cfgchip2 |= CFGCHIP2_FORCE_HOST;
+                break;
+#endif
+#ifdef  CONFIG_USB_GADGET_MUSB_HDRC
+        case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
+                cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
+                break;
+#endif
+#ifdef  CONFIG_USB_MUSB_OTG
+        case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
+                cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
+                break;
+#endif
+        default:
+                DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
+        }
+
+        __raw_writel(cfgchip2, CFGCHIP2);
+        return 0;
+}
+
+int __init musb_platform_init(struct musb *musb, void *board_data)
+{
+        void __iomem *reg_base = musb->ctrl_base;
+        u32 rev;
+
+        musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
+
+        clk_enable(musb->clock);
+
+        /* Returns zero if e.g. not clocked */
+        rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
+        if (!rev)
+                goto fail;
+
+        usb_nop_xceiv_register();
+        musb->xceiv = otg_get_transceiver();
+        if (!musb->xceiv)
+                goto fail;
+
+        if (is_host_enabled(musb))
+                setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
+
+        musb->board_set_vbus = da8xx_set_vbus;
+
+        /* Reset the controller */
+        musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
+
+        /* Start the on-chip PHY and its PLL. */
+        phy_on();
+
+        msleep(5);
+
+        /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
+        pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
+                 rev, __raw_readl(CFGCHIP2),
+                 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
+
+        musb->isr = da8xx_interrupt;
+        return 0;
+fail:
+        clk_disable(musb->clock);
+        return -ENODEV;
+}
+
+int musb_platform_exit(struct musb *musb)
+{
+        if (is_host_enabled(musb))
+                del_timer_sync(&otg_workaround);
+
+        phy_off();
+
+        otg_put_transceiver(musb->xceiv);
+        usb_nop_xceiv_unregister();
+
+        clk_disable(musb->clock);
+
+        return 0;
+}
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 57624361c1de..6e67629f50cc 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -446,6 +446,7 @@ int __init musb_platform_init(struct musb *musb, void *board_data)
 fail:
         clk_disable(musb->clock);
 
+        otg_put_transceiver(musb->xceiv);
         usb_nop_xceiv_unregister();
         return -ENODEV;
 }
@@ -496,6 +497,7 @@ int musb_platform_exit(struct musb *musb)
 
         clk_disable(musb->clock);
 
+        otg_put_transceiver(musb->xceiv);
         usb_nop_xceiv_unregister();
 
         return 0;
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 540c766c4f86..c9f9024c5515 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -272,6 +272,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
         }
 }
 
+#if !defined(CONFIG_USB_MUSB_AM35X)
 /*
  * Unload an endpoint's FIFO
  */
@@ -309,6 +310,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
                 readsb(fifo, dst, len);
         }
 }
+#endif
 
 #endif  /* normal PIO */
 
@@ -550,6 +552,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
         if (int_usb & MUSB_INTR_SESSREQ) {
                 void __iomem *mbase = musb->mregs;
 
+                if (devctl & MUSB_DEVCTL_BDEVICE) {
+                        DBG(3, "SessReq while on B state\n");
+                        return IRQ_HANDLED;
+                }
+
                 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
 
                 /* IRQ arrives from ID pin sense or (later, if VBUS power
@@ -1921,10 +1928,6 @@ static void musb_free(struct musb *musb)
                 dma_controller_destroy(c);
         }
 
-#ifdef CONFIG_USB_MUSB_OTG
-        put_device(musb->xceiv->dev);
-#endif
-
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
         usb_put_hcd(musb_to_hcd(musb));
 #else
@@ -2266,6 +2269,7 @@ void musb_save_context(struct musb *musb)
 {
         int i;
         void __iomem *musb_base = musb->mregs;
+        void __iomem *epio;
 
         if (is_host_enabled(musb)) {
                 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
@@ -2279,16 +2283,16 @@ void musb_save_context(struct musb *musb)
         musb_context.index = musb_readb(musb_base, MUSB_INDEX);
         musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
 
-        for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
-                musb_writeb(musb_base, MUSB_INDEX, i);
+        for (i = 0; i < musb->config->num_eps; ++i) {
+                epio = musb->endpoints[i].regs;
                 musb_context.index_regs[i].txmaxp =
-                        musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
+                        musb_readw(epio, MUSB_TXMAXP);
                 musb_context.index_regs[i].txcsr =
-                        musb_readw(musb_base, 0x10 + MUSB_TXCSR);
+                        musb_readw(epio, MUSB_TXCSR);
                 musb_context.index_regs[i].rxmaxp =
-                        musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
+                        musb_readw(epio, MUSB_RXMAXP);
                 musb_context.index_regs[i].rxcsr =
-                        musb_readw(musb_base, 0x10 + MUSB_RXCSR);
+                        musb_readw(epio, MUSB_RXCSR);
 
                 if (musb->dyn_fifo) {
                         musb_context.index_regs[i].txfifoadd =
@@ -2302,13 +2306,13 @@ void musb_save_context(struct musb *musb)
                 }
                 if (is_host_enabled(musb)) {
                         musb_context.index_regs[i].txtype =
-                                musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
+                                musb_readb(epio, MUSB_TXTYPE);
                         musb_context.index_regs[i].txinterval =
-                                musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
+                                musb_readb(epio, MUSB_TXINTERVAL);
                         musb_context.index_regs[i].rxtype =
-                                musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
+                                musb_readb(epio, MUSB_RXTYPE);
                         musb_context.index_regs[i].rxinterval =
-                                musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
+                                musb_readb(epio, MUSB_RXINTERVAL);
 
                         musb_context.index_regs[i].txfunaddr =
                                 musb_read_txfunaddr(musb_base, i);
@@ -2326,8 +2330,6 @@ void musb_save_context(struct musb *musb)
                 }
         }
 
-        musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
-
         musb_platform_save_context(musb, &musb_context);
 }
 
@@ -2336,6 +2338,7 @@ void musb_restore_context(struct musb *musb)
         int i;
         void __iomem *musb_base = musb->mregs;
         void __iomem *ep_target_regs;
+        void __iomem *epio;
 
         musb_platform_restore_context(musb, &musb_context);
 
@@ -2350,15 +2353,15 @@ void musb_restore_context(struct musb *musb)
         musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
         musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
 
-        for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
-                musb_writeb(musb_base, MUSB_INDEX, i);
-                musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
+        for (i = 0; i < musb->config->num_eps; ++i) {
+                epio = musb->endpoints[i].regs;
+                musb_writew(epio, MUSB_TXMAXP,
                         musb_context.index_regs[i].txmaxp);
-                musb_writew(musb_base, 0x10 + MUSB_TXCSR,
+                musb_writew(epio, MUSB_TXCSR,
                         musb_context.index_regs[i].txcsr);
-                musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
+                musb_writew(epio, MUSB_RXMAXP,
                         musb_context.index_regs[i].rxmaxp);
-                musb_writew(musb_base, 0x10 + MUSB_RXCSR,
+                musb_writew(epio, MUSB_RXCSR,
                         musb_context.index_regs[i].rxcsr);
 
                 if (musb->dyn_fifo) {
@@ -2373,13 +2376,13 @@ void musb_restore_context(struct musb *musb)
                 }
 
                 if (is_host_enabled(musb)) {
-                        musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
+                        musb_writeb(epio, MUSB_TXTYPE,
                                 musb_context.index_regs[i].txtype);
-                        musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
+                        musb_writeb(epio, MUSB_TXINTERVAL,
                                 musb_context.index_regs[i].txinterval);
-                        musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
+                        musb_writeb(epio, MUSB_RXTYPE,
                                 musb_context.index_regs[i].rxtype);
-                        musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
+                        musb_writeb(epio, MUSB_RXINTERVAL,
 
                         musb_context.index_regs[i].rxinterval);
                         musb_write_txfunaddr(musb_base, i,
@@ -2400,8 +2403,6 @@ void musb_restore_context(struct musb *musb)
                                 musb_context.index_regs[i].rxhubport);
                 }
         }
-
-        musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
 }
 
 static int musb_suspend(struct device *dev)
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 91d67794e350..69797e5b46a7 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -330,6 +330,7 @@ struct musb {
         /* device lock */
         spinlock_t              lock;
         struct clk              *clock;
+        struct clk              *phy_clock;
         irqreturn_t             (*isr)(int, void *);
         struct work_struct      irq_work;
         u16                     hwvers;
@@ -599,6 +600,7 @@ extern void musb_hnp_stop(struct musb *musb);
 extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
 
 #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
+        defined(CONFIG_ARCH_DAVINCI_DA8XX) || \
         defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
         defined(CONFIG_ARCH_OMAP4)
 extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
index d73afdbde3ee..94f6973cf8f7 100644
--- a/drivers/usb/musb/musb_debug.h
+++ b/drivers/usb/musb/musb_debug.h
@@ -42,11 +42,10 @@
 #define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
 #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
 
-#define xprintk(level, facility, format, args...) do { \
-        if (_dbg_level(level)) { \
-                printk(facility "%s %d: " format , \
-                                __func__, __LINE__ , ## args); \
-        } } while (0)
+#define DBG(level, format, args...) do { \
+        if (_dbg_level(level)) \
+                pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
+        } while (0)
 
 extern unsigned musb_debug;
 
@@ -55,8 +54,6 @@ static inline int _dbg_level(unsigned l)
         return musb_debug >= l;
 }
 
-#define DBG(level, fmt, args...) xprintk(level, KERN_DEBUG, fmt, ## args)
-
 extern const char *otg_state_string(struct musb *);
 
 #ifdef CONFIG_DEBUG_FS
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index d065e23f123e..5d815049cbaa 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -337,13 +337,15 @@ static void txstate(struct musb *musb, struct musb_request *req)
                                         csr |= (MUSB_TXCSR_DMAENAB |
                                                         MUSB_TXCSR_MODE);
                                         /* against programming guide */
-                                } else
-                                        csr |= (MUSB_TXCSR_AUTOSET
-                                                        | MUSB_TXCSR_DMAENAB
+                                } else {
+                                        csr |= (MUSB_TXCSR_DMAENAB
                                                         | MUSB_TXCSR_DMAMODE
                                                         | MUSB_TXCSR_MODE);
-
+                                        if (!musb_ep->hb_mult)
+                                                csr |= MUSB_TXCSR_AUTOSET;
+                                }
                                 csr &= ~MUSB_TXCSR_P_UNDERRUN;
+
                                 musb_writew(epio, MUSB_TXCSR, csr);
                         }
                 }
@@ -475,40 +477,39 @@ void musb_g_tx(struct musb *musb, u8 epnum)
                                 epnum, csr, musb_ep->dma->actual_len, request);
                 }
 
-                if (is_dma || request->actual == request->length) {
-                        /*
-                         * First, maybe a terminating short packet. Some DMA
-                         * engines might handle this by themselves.
-                         */
-                        if ((request->zero && request->length
-                                && request->length % musb_ep->packet_sz == 0)
+                /*
+                 * First, maybe a terminating short packet. Some DMA
+                 * engines might handle this by themselves.
+                 */
+                if ((request->zero && request->length
+                        && (request->length % musb_ep->packet_sz == 0)
+                        && (request->actual == request->length))
 #ifdef CONFIG_USB_INVENTRA_DMA
-                                || (is_dma && (!dma->desired_mode ||
-                                        (request->actual &
-                                                (musb_ep->packet_sz - 1))))
+                        || (is_dma && (!dma->desired_mode ||
+                                (request->actual &
+                                        (musb_ep->packet_sz - 1))))
 #endif
-                        ) {
-                                /*
-                                 * On DMA completion, FIFO may not be
-                                 * available yet...
-                                 */
-                                if (csr & MUSB_TXCSR_TXPKTRDY)
-                                        return;
+                ) {
+                        /*
+                         * On DMA completion, FIFO may not be
+                         * available yet...
+                         */
+                        if (csr & MUSB_TXCSR_TXPKTRDY)
+                                return;
 
-                                DBG(4, "sending zero pkt\n");
-                                musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
-                                                | MUSB_TXCSR_TXPKTRDY);
-                                request->zero = 0;
-                        }
+                        DBG(4, "sending zero pkt\n");
+                        musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
+                                        | MUSB_TXCSR_TXPKTRDY);
+                        request->zero = 0;
+                }
 
-                        if (request->actual == request->length) {
-                                musb_g_giveback(musb_ep, request, 0);
-                                request = musb_ep->desc ? next_request(musb_ep) : NULL;
-                                if (!request) {
-                                        DBG(4, "%s idle now\n",
-                                                musb_ep->end_point.name);
-                                        return;
-                                }
+                if (request->actual == request->length) {
+                        musb_g_giveback(musb_ep, request, 0);
+                        request = musb_ep->desc ? next_request(musb_ep) : NULL;
+                        if (!request) {
+                                DBG(4, "%s idle now\n",
+                                        musb_ep->end_point.name);
+                                return;
                         }
                 }
 
@@ -643,7 +644,9 @@ static void rxstate(struct musb *musb, struct musb_request *req)
          */
 
                                 csr |= MUSB_RXCSR_DMAENAB;
-                                csr |= MUSB_RXCSR_AUTOCLEAR;
+                                if (!musb_ep->hb_mult &&
+                                        musb_ep->hw_ep->rx_double_buffered)
+                                        csr |= MUSB_RXCSR_AUTOCLEAR;
 #ifdef USE_MODE1
                                 /* csr |= MUSB_RXCSR_DMAMODE; */
 
@@ -772,7 +775,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
                 musb_writew(epio, MUSB_RXCSR, csr);
 
                 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
-                if (request && request->status == -EINPROGRESS)
+                if (request->status == -EINPROGRESS)
                         request->status = -EOVERFLOW;
         }
         if (csr & MUSB_RXCSR_INCOMPRX) {
@@ -825,14 +828,8 @@ void musb_g_rx(struct musb *musb, u8 epnum)
                         return;
         }
 
-        /* analyze request if the ep is hot */
-        if (request)
-                rxstate(musb, to_musb_request(request));
-        else
-                DBG(3, "packet waiting for %s%s request\n",
-                                musb_ep->desc ? "" : "inactive ",
-                                musb_ep->end_point.name);
-        return;
+        /* Analyze request */
+        rxstate(musb, to_musb_request(request));
 }
 
 /* ------------------------------------------------------------ */
@@ -875,9 +872,25 @@ static int musb_gadget_enable(struct usb_ep *ep,
 
         /* REVISIT this rules out high bandwidth periodic transfers */
         tmp = le16_to_cpu(desc->wMaxPacketSize);
-        if (tmp & ~0x07ff)
-                goto fail;
-        musb_ep->packet_sz = tmp;
+        if (tmp & ~0x07ff) {
+                int ok;
+
+                if (usb_endpoint_dir_in(desc))
+                        ok = musb->hb_iso_tx;
+                else
+                        ok = musb->hb_iso_rx;
+
+                if (!ok) {
+                        DBG(4, "%s: not support ISO high bandwidth\n", __func__);
+                        goto fail;
+                }
+                musb_ep->hb_mult = (tmp >> 11) & 3;
+        } else {
+                musb_ep->hb_mult = 0;
+        }
+
+        musb_ep->packet_sz = tmp & 0x7ff;
+        tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
 
         /* enable the interrupts for the endpoint, set the endpoint
          * packet size (or fail), set the mode, clear the fifo
@@ -890,8 +903,11 @@ static int musb_gadget_enable(struct usb_ep *ep,
                         musb_ep->is_in = 1;
                 if (!musb_ep->is_in)
                         goto fail;
-                if (tmp > hw_ep->max_packet_sz_tx)
+
+                if (tmp > hw_ep->max_packet_sz_tx) {
+                        DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
                         goto fail;
+                }
 
                 int_txe |= (1 << epnum);
                 musb_writew(mbase, MUSB_INTRTXE, int_txe);
@@ -906,7 +922,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
                 if (musb->hwvers < MUSB_HWVERS_2000)
                         musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
                 else
-                        musb_writew(regs, MUSB_TXMAXP, tmp);
+                        musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11));
 
                 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
                 if (musb_readw(regs, MUSB_TXCSR)
@@ -927,8 +943,11 @@ static int musb_gadget_enable(struct usb_ep *ep,
                         musb_ep->is_in = 0;
                 if (musb_ep->is_in)
                         goto fail;
-                if (tmp > hw_ep->max_packet_sz_rx)
+
+                if (tmp > hw_ep->max_packet_sz_rx) {
+                        DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
                         goto fail;
+                }
 
                 int_rxe |= (1 << epnum);
                 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
@@ -942,7 +961,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
                 if (musb->hwvers < MUSB_HWVERS_2000)
                         musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_rx);
                 else
-                        musb_writew(regs, MUSB_RXMAXP, tmp);
+                        musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11));
 
                 /* force shared fifo to OUT-only mode */
                 if (hw_ep->is_shared_fifo) {
@@ -1699,9 +1718,11 @@ void musb_gadget_cleanup(struct musb *musb)
  * -ENOMEM no memeory to perform the operation
  *
  * @param driver the gadget driver
+ * @param bind the driver's bind function
  * @return <0 if error, 0 if everything is fine
  */
-int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
+                int (*bind)(struct usb_gadget *))
 {
         int retval;
         unsigned long flags;
@@ -1709,8 +1730,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 
         if (!driver
                         || driver->speed != USB_SPEED_HIGH
-                        || !driver->bind
-                        || !driver->setup)
+                        || !bind || !driver->setup)
                 return -EINVAL;
 
         /* driver must be initialized to support peripheral mode */
@@ -1738,7 +1758,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
         spin_unlock_irqrestore(&musb->lock, flags);
 
         if (retval == 0) {
-                retval = driver->bind(&musb->g);
+                retval = bind(&musb->g);
                 if (retval != 0) {
                         DBG(3, "bind to driver %s failed --> %d\n",
                                         driver->driver.name, retval);
@@ -1786,7 +1806,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 
         return retval;
 }
-EXPORT_SYMBOL(usb_gadget_register_driver);
+EXPORT_SYMBOL(usb_gadget_probe_driver);
 
 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
 {
diff --git a/drivers/usb/musb/musb_gadget.h b/drivers/usb/musb/musb_gadget.h
index 572b1da7f2dc..dec8dc008191 100644
--- a/drivers/usb/musb/musb_gadget.h
+++ b/drivers/usb/musb/musb_gadget.h
@@ -79,6 +79,8 @@ struct musb_ep {
 
         /* true if lock must be dropped but req_list may not be advanced */
         u8                              busy;
+
+        u8                              hb_mult;
 };
 
 static inline struct musb_ep *to_musb_ep(struct usb_ep *ep)
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 9e65c47cc98b..4d5bcb4e14d2 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -41,6 +41,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/dma-mapping.h>
 
 #include "musb_core.h"
 #include "musb_host.h"
@@ -1119,6 +1120,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
         u32                     status = 0;
         void __iomem            *mbase = musb->mregs;
         struct dma_channel      *dma;
+        bool                    transfer_pending = false;
 
         musb_ep_select(mbase, epnum);
         tx_csr = musb_readw(epio, MUSB_TXCSR);
@@ -1279,7 +1281,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                                 offset = d->offset;
                                 length = d->length;
                         }
-                } else if (dma) {
+                } else if (dma && urb->transfer_buffer_length == qh->offset) {
                         done = true;
                 } else {
                         /* see if we need to send more data, or ZLP */
@@ -1292,6 +1294,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                         if (!done) {
                                 offset = qh->offset;
                                 length = urb->transfer_buffer_length - offset;
+                                transfer_pending = true;
                         }
                 }
         }
@@ -1311,7 +1314,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                 urb->actual_length = qh->offset;
                 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
                 return;
-        } else  if (usb_pipeisoc(pipe) && dma) {
+        } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
                 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
                                 offset, length)) {
                         if (is_cppi_enabled() || tusb_dma_omap())
@@ -1332,6 +1335,8 @@ void musb_host_tx(struct musb *musb, u8 epnum)
          */
         if (length > qh->maxpacket)
                 length = qh->maxpacket;
+        /* Unmap the buffer so that CPU can use it */
+        unmap_urb_for_dma(musb_to_hcd(musb), urb);
         musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
         qh->segsize = length;
 
@@ -1752,6 +1757,8 @@ void musb_host_rx(struct musb *musb, u8 epnum)
 #endif  /* Mentor DMA */
 
                 if (!dma) {
+                        /* Unmap the buffer so that CPU can use it */
+                        unmap_urb_for_dma(musb_to_hcd(musb), urb);
                         done = musb_host_packet_rx(musb, urb,
                                         epnum, iso_err);
                         DBG(6, "read %spacket\n", done ? "last " : "");
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 6dc107f25245..6f771af5cbdb 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -91,7 +91,7 @@ static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
                         channel = &(musb_channel->channel);
                         channel->private_data = musb_channel;
                         channel->status = MUSB_DMA_STATUS_FREE;
-                        channel->max_len = 0x10000;
+                        channel->max_len = 0x100000;
                         /* Tx => mode 1; Rx => mode 0 */
                         channel->desired_mode = transmit;
                         channel->actual_len = 0;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 2111a241dd03..ed618bde1eec 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -320,5 +320,6 @@ int musb_platform_exit(struct musb *musb)
 
         musb_platform_suspend(musb);
 
+        otg_put_transceiver(musb->xceiv);
         return 0;
 }
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 3c48e77a0aa2..bde40efc7046 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -1152,6 +1152,8 @@ done:
         if (ret < 0) {
                 if (sync)
                         iounmap(sync);
+
+                otg_put_transceiver(musb->xceiv);
                 usb_nop_xceiv_unregister();
         }
         return ret;
@@ -1166,6 +1168,8 @@ int musb_platform_exit(struct musb *musb)
                 musb->board_set_power(0);
 
         iounmap(musb->sync_va);
+
+        otg_put_transceiver(musb->xceiv);
         usb_nop_xceiv_unregister();
         return 0;
 }