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path: root/drivers/usb/musb/tusb6010.c
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Diffstat (limited to 'drivers/usb/musb/tusb6010.c')
-rw-r--r--drivers/usb/musb/tusb6010.c62
1 files changed, 33 insertions, 29 deletions
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index c47aac4a1f98..b410357cf016 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -106,7 +106,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
@@ -115,7 +115,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0; 121 phy_otg_ctrl = 0;
@@ -172,13 +172,14 @@ static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
172 172
173void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 173void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
174{ 174{
175 struct musb *musb = hw_ep->musb;
175 void __iomem *ep_conf = hw_ep->conf; 176 void __iomem *ep_conf = hw_ep->conf;
176 void __iomem *fifo = hw_ep->fifo; 177 void __iomem *fifo = hw_ep->fifo;
177 u8 epnum = hw_ep->epnum; 178 u8 epnum = hw_ep->epnum;
178 179
179 prefetch(buf); 180 prefetch(buf);
180 181
181 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 182 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
182 'T', epnum, fifo, len, buf); 183 'T', epnum, fifo, len, buf);
183 184
184 if (epnum) 185 if (epnum)
@@ -221,11 +222,12 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
221 222
222void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 223void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
223{ 224{
225 struct musb *musb = hw_ep->musb;
224 void __iomem *ep_conf = hw_ep->conf; 226 void __iomem *ep_conf = hw_ep->conf;
225 void __iomem *fifo = hw_ep->fifo; 227 void __iomem *fifo = hw_ep->fifo;
226 u8 epnum = hw_ep->epnum; 228 u8 epnum = hw_ep->epnum;
227 229
228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 230 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'R', epnum, fifo, len, buf); 231 'R', epnum, fifo, len, buf);
230 232
231 if (epnum) 233 if (epnum)
@@ -304,7 +306,7 @@ static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
304 } 306 }
305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 307 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
306 308
307 DBG(2, "draw max %d mA VBUS\n", mA); 309 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
308 return 0; 310 return 0;
309} 311}
310 312
@@ -374,7 +376,7 @@ static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 376 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 377 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376 378
377 DBG(6, "idle, wake on %02x\n", wakeup_enables); 379 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378} 380}
379 381
380/* 382/*
@@ -421,8 +423,8 @@ static void musb_do_idle(unsigned long _musb)
421 if ((musb->a_wait_bcon != 0) 423 if ((musb->a_wait_bcon != 0)
422 && (musb->idle_timeout == 0 424 && (musb->idle_timeout == 0
423 || time_after(jiffies, musb->idle_timeout))) { 425 || time_after(jiffies, musb->idle_timeout))) {
424 DBG(4, "Nothing connected %s, turning off VBUS\n", 426 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425 otg_state_string(musb)); 427 otg_state_string(musb->xceiv->state));
426 } 428 }
427 /* FALLTHROUGH */ 429 /* FALLTHROUGH */
428 case OTG_STATE_A_IDLE: 430 case OTG_STATE_A_IDLE:
@@ -481,7 +483,8 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
481 /* Never idle if active, or when VBUS timeout is not set as host */ 483 /* Never idle if active, or when VBUS timeout is not set as host */
482 if (musb->is_active || ((musb->a_wait_bcon == 0) 484 if (musb->is_active || ((musb->a_wait_bcon == 0)
483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 485 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
484 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 486 dev_dbg(musb->controller, "%s active, deleting timer\n",
487 otg_state_string(musb->xceiv->state));
485 del_timer(&musb_idle_timer); 488 del_timer(&musb_idle_timer);
486 last_timer = jiffies; 489 last_timer = jiffies;
487 return; 490 return;
@@ -491,14 +494,14 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
491 if (!timer_pending(&musb_idle_timer)) 494 if (!timer_pending(&musb_idle_timer))
492 last_timer = timeout; 495 last_timer = timeout;
493 else { 496 else {
494 DBG(4, "Longer idle timer already pending, ignoring\n"); 497 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
495 return; 498 return;
496 } 499 }
497 } 500 }
498 last_timer = timeout; 501 last_timer = timeout;
499 502
500 DBG(4, "%s inactive, for idle timer for %lu ms\n", 503 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
501 otg_state_string(musb), 504 otg_state_string(musb->xceiv->state),
502 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 505 (unsigned long)jiffies_to_msecs(timeout - jiffies));
503 mod_timer(&musb_idle_timer, timeout); 506 mod_timer(&musb_idle_timer, timeout);
504} 507}
@@ -572,8 +575,8 @@ static void tusb_musb_set_vbus(struct musb *musb, int is_on)
572 musb_writel(tbase, TUSB_DEV_CONF, conf); 575 musb_writel(tbase, TUSB_DEV_CONF, conf);
573 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 576 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
574 577
575 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 578 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
576 otg_state_string(musb), 579 otg_state_string(musb->xceiv->state),
577 musb_readb(musb->mregs, MUSB_DEVCTL), 580 musb_readb(musb->mregs, MUSB_DEVCTL),
578 musb_readl(tbase, TUSB_DEV_OTG_STAT), 581 musb_readl(tbase, TUSB_DEV_OTG_STAT),
579 conf, prcm); 582 conf, prcm);
@@ -633,7 +636,7 @@ static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
633#endif 636#endif
634 637
635 default: 638 default:
636 DBG(2, "Trying to set mode %i\n", musb_mode); 639 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
637 return -EINVAL; 640 return -EINVAL;
638 } 641 }
639 642
@@ -666,7 +669,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
666 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 669 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
667 else 670 else
668 default_a = is_host_enabled(musb); 671 default_a = is_host_enabled(musb);
669 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 672 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
670 musb->xceiv->default_a = default_a; 673 musb->xceiv->default_a = default_a;
671 tusb_musb_set_vbus(musb, default_a); 674 tusb_musb_set_vbus(musb, default_a);
672 675
@@ -693,7 +696,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
693#endif 696#endif
694 697
695 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 698 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
696 DBG(1, "Forcing disconnect (no interrupt)\n"); 699 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
697 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 700 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
698 /* INTR_DISCONNECT can hide... */ 701 /* INTR_DISCONNECT can hide... */
699 musb->xceiv->state = OTG_STATE_B_IDLE; 702 musb->xceiv->state = OTG_STATE_B_IDLE;
@@ -701,18 +704,18 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
701 } 704 }
702 musb->is_active = 0; 705 musb->is_active = 0;
703 } 706 }
704 DBG(2, "vbus change, %s, otg %03x\n", 707 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
705 otg_state_string(musb), otg_stat); 708 otg_state_string(musb->xceiv->state), otg_stat);
706 idle_timeout = jiffies + (1 * HZ); 709 idle_timeout = jiffies + (1 * HZ);
707 schedule_work(&musb->irq_work); 710 schedule_work(&musb->irq_work);
708 711
709 } else /* A-dev state machine */ { 712 } else /* A-dev state machine */ {
710 DBG(2, "vbus change, %s, otg %03x\n", 713 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
711 otg_state_string(musb), otg_stat); 714 otg_state_string(musb->xceiv->state), otg_stat);
712 715
713 switch (musb->xceiv->state) { 716 switch (musb->xceiv->state) {
714 case OTG_STATE_A_IDLE: 717 case OTG_STATE_A_IDLE:
715 DBG(2, "Got SRP, turning on VBUS\n"); 718 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
716 musb_platform_set_vbus(musb, 1); 719 musb_platform_set_vbus(musb, 1);
717 720
718 /* CONNECT can wake if a_wait_bcon is set */ 721 /* CONNECT can wake if a_wait_bcon is set */
@@ -756,7 +759,8 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
756 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 759 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
757 u8 devctl; 760 u8 devctl;
758 761
759 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 762 dev_dbg(musb->controller, "%s timer, %03x\n",
763 otg_state_string(musb->xceiv->state), otg_stat);
760 764
761 switch (musb->xceiv->state) { 765 switch (musb->xceiv->state) {
762 case OTG_STATE_A_WAIT_VRISE: 766 case OTG_STATE_A_WAIT_VRISE:
@@ -767,7 +771,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
767 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 771 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
768 if ((devctl & MUSB_DEVCTL_VBUS) 772 if ((devctl & MUSB_DEVCTL_VBUS)
769 != MUSB_DEVCTL_VBUS) { 773 != MUSB_DEVCTL_VBUS) {
770 DBG(2, "devctl %02x\n", devctl); 774 dev_dbg(musb->controller, "devctl %02x\n", devctl);
771 break; 775 break;
772 } 776 }
773 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 777 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
@@ -812,7 +816,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
812 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 816 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
813 817
814 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 818 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
815 DBG(3, "TUSB IRQ %08x\n", int_src); 819 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
816 820
817 musb->int_usb = (u8) int_src; 821 musb->int_usb = (u8) int_src;
818 822
@@ -833,7 +837,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
833 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 837 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
834 if (reg == i) 838 if (reg == i)
835 break; 839 break;
836 DBG(6, "TUSB NOR not ready\n"); 840 dev_dbg(musb->controller, "TUSB NOR not ready\n");
837 } 841 }
838 842
839 /* work around issue 13 (2nd half) */ 843 /* work around issue 13 (2nd half) */
@@ -845,7 +849,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
845 musb->is_active = 1; 849 musb->is_active = 1;
846 schedule_work(&musb->irq_work); 850 schedule_work(&musb->irq_work);
847 } 851 }
848 DBG(3, "wake %sactive %02x\n", 852 dev_dbg(musb->controller, "wake %sactive %02x\n",
849 musb->is_active ? "" : "in", reg); 853 musb->is_active ? "" : "in", reg);
850 854
851 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 855 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
@@ -867,7 +871,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
867 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 871 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
868 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 872 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
869 873
870 DBG(3, "DMA IRQ %08x\n", dma_src); 874 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
871 real_dma_src = ~real_dma_src & dma_src; 875 real_dma_src = ~real_dma_src & dma_src;
872 if (tusb_dma_omap() && real_dma_src) { 876 if (tusb_dma_omap() && real_dma_src) {
873 int tx_source = (real_dma_src & 0xffff); 877 int tx_source = (real_dma_src & 0xffff);
@@ -875,7 +879,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
875 879
876 for (i = 1; i <= 15; i++) { 880 for (i = 1; i <= 15; i++) {
877 if (tx_source & (1 << i)) { 881 if (tx_source & (1 << i)) {
878 DBG(3, "completing ep%i %s\n", i, "tx"); 882 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
879 musb_dma_completion(musb, i, 1); 883 musb_dma_completion(musb, i, 1);
880 } 884 }
881 } 885 }