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Diffstat (limited to 'drivers/usb/musb/omap2430.c')
-rw-r--r--drivers/usb/musb/omap2430.c324
1 files changed, 324 insertions, 0 deletions
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
new file mode 100644
index 000000000000..298b22e6ad0d
--- /dev/null
+++ b/drivers/usb/musb/omap2430.c
@@ -0,0 +1,324 @@
1/*
2 * Copyright (C) 2005-2007 by Texas Instruments
3 * Some code has been taken from tusb6010.c
4 * Copyrights for that are attributable to:
5 * Copyright (C) 2006 Nokia Corporation
6 * Jarkko Nikula <jarkko.nikula@nokia.com>
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/init.h>
33#include <linux/list.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36
37#include <asm/mach-types.h>
38#include <asm/arch/hardware.h>
39#include <asm/arch/mux.h>
40
41#include "musb_core.h"
42#include "omap2430.h"
43
44#ifdef CONFIG_ARCH_OMAP3430
45#define get_cpu_rev() 2
46#endif
47
48#define MUSB_TIMEOUT_A_WAIT_BCON 1100
49
50static struct timer_list musb_idle_timer;
51
52static void musb_do_idle(unsigned long _musb)
53{
54 struct musb *musb = (void *)_musb;
55 unsigned long flags;
56 u8 power;
57 u8 devctl;
58
59 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
60
61 spin_lock_irqsave(&musb->lock, flags);
62
63 switch (musb->xceiv.state) {
64 case OTG_STATE_A_WAIT_BCON:
65 devctl &= ~MUSB_DEVCTL_SESSION;
66 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
67
68 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
69 if (devctl & MUSB_DEVCTL_BDEVICE) {
70 musb->xceiv.state = OTG_STATE_B_IDLE;
71 MUSB_DEV_MODE(musb);
72 } else {
73 musb->xceiv.state = OTG_STATE_A_IDLE;
74 MUSB_HST_MODE(musb);
75 }
76 break;
77#ifdef CONFIG_USB_MUSB_HDRC_HCD
78 case OTG_STATE_A_SUSPEND:
79 /* finish RESUME signaling? */
80 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
81 power = musb_readb(musb->mregs, MUSB_POWER);
82 power &= ~MUSB_POWER_RESUME;
83 DBG(1, "root port resume stopped, power %02x\n", power);
84 musb_writeb(musb->mregs, MUSB_POWER, power);
85 musb->is_active = 1;
86 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
87 | MUSB_PORT_STAT_RESUME);
88 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
89 usb_hcd_poll_rh_status(musb_to_hcd(musb));
90 /* NOTE: it might really be A_WAIT_BCON ... */
91 musb->xceiv.state = OTG_STATE_A_HOST;
92 }
93 break;
94#endif
95#ifdef CONFIG_USB_MUSB_HDRC_HCD
96 case OTG_STATE_A_HOST:
97 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
98 if (devctl & MUSB_DEVCTL_BDEVICE)
99 musb->xceiv.state = OTG_STATE_B_IDLE;
100 else
101 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
102#endif
103 default:
104 break;
105 }
106 spin_unlock_irqrestore(&musb->lock, flags);
107}
108
109
110void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
111{
112 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
113 static unsigned long last_timer;
114
115 if (timeout == 0)
116 timeout = default_timeout;
117
118 /* Never idle if active, or when VBUS timeout is not set as host */
119 if (musb->is_active || ((musb->a_wait_bcon == 0)
120 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
121 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
122 del_timer(&musb_idle_timer);
123 last_timer = jiffies;
124 return;
125 }
126
127 if (time_after(last_timer, timeout)) {
128 if (!timer_pending(&musb_idle_timer))
129 last_timer = timeout;
130 else {
131 DBG(4, "Longer idle timer already pending, ignoring\n");
132 return;
133 }
134 }
135 last_timer = timeout;
136
137 DBG(4, "%s inactive, for idle timer for %lu ms\n",
138 otg_state_string(musb),
139 (unsigned long)jiffies_to_msecs(timeout - jiffies));
140 mod_timer(&musb_idle_timer, timeout);
141}
142
143void musb_platform_enable(struct musb *musb)
144{
145}
146void musb_platform_disable(struct musb *musb)
147{
148}
149static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
150{
151}
152
153static void omap_set_vbus(struct musb *musb, int is_on)
154{
155 u8 devctl;
156 /* HDRC controls CPEN, but beware current surges during device
157 * connect. They can trigger transient overcurrent conditions
158 * that must be ignored.
159 */
160
161 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
162
163 if (is_on) {
164 musb->is_active = 1;
165 musb->xceiv.default_a = 1;
166 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
167 devctl |= MUSB_DEVCTL_SESSION;
168
169 MUSB_HST_MODE(musb);
170 } else {
171 musb->is_active = 0;
172
173 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
174 * jumping right to B_IDLE...
175 */
176
177 musb->xceiv.default_a = 0;
178 musb->xceiv.state = OTG_STATE_B_IDLE;
179 devctl &= ~MUSB_DEVCTL_SESSION;
180
181 MUSB_DEV_MODE(musb);
182 }
183 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
184
185 DBG(1, "VBUS %s, devctl %02x "
186 /* otg %3x conf %08x prcm %08x */ "\n",
187 otg_state_string(musb),
188 musb_readb(musb->mregs, MUSB_DEVCTL));
189}
190static int omap_set_power(struct otg_transceiver *x, unsigned mA)
191{
192 return 0;
193}
194
195static int musb_platform_resume(struct musb *musb);
196
197void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
198{
199 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
200
201 devctl |= MUSB_DEVCTL_SESSION;
202 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
203
204 switch (musb_mode) {
205 case MUSB_HOST:
206 otg_set_host(&musb->xceiv, musb->xceiv.host);
207 break;
208 case MUSB_PERIPHERAL:
209 otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
210 break;
211 case MUSB_OTG:
212 break;
213 }
214}
215
216int __init musb_platform_init(struct musb *musb)
217{
218 u32 l;
219
220#if defined(CONFIG_ARCH_OMAP2430)
221 omap_cfg_reg(AE5_2430_USB0HS_STP);
222#endif
223
224 musb_platform_resume(musb);
225
226 l = omap_readl(OTG_SYSCONFIG);
227 l &= ~ENABLEWAKEUP; /* disable wakeup */
228 l &= ~NOSTDBY; /* remove possible nostdby */
229 l |= SMARTSTDBY; /* enable smart standby */
230 l &= ~AUTOIDLE; /* disable auto idle */
231 l &= ~NOIDLE; /* remove possible noidle */
232 l |= SMARTIDLE; /* enable smart idle */
233 l |= AUTOIDLE; /* enable auto idle */
234 omap_writel(l, OTG_SYSCONFIG);
235
236 l = omap_readl(OTG_INTERFSEL);
237 l |= ULPI_12PIN;
238 omap_writel(l, OTG_INTERFSEL);
239
240 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
241 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
242 omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
243 omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
244 omap_readl(OTG_SIMENABLE));
245
246 omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
247
248 if (is_host_enabled(musb))
249 musb->board_set_vbus = omap_set_vbus;
250 if (is_peripheral_enabled(musb))
251 musb->xceiv.set_power = omap_set_power;
252 musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
253
254 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
255
256 return 0;
257}
258
259int musb_platform_suspend(struct musb *musb)
260{
261 u32 l;
262
263 if (!musb->clock)
264 return 0;
265
266 /* in any role */
267 l = omap_readl(OTG_FORCESTDBY);
268 l |= ENABLEFORCE; /* enable MSTANDBY */
269 omap_writel(l, OTG_FORCESTDBY);
270
271 l = omap_readl(OTG_SYSCONFIG);
272 l |= ENABLEWAKEUP; /* enable wakeup */
273 omap_writel(l, OTG_SYSCONFIG);
274
275 if (musb->xceiv.set_suspend)
276 musb->xceiv.set_suspend(&musb->xceiv, 1);
277
278 if (musb->set_clock)
279 musb->set_clock(musb->clock, 0);
280 else
281 clk_disable(musb->clock);
282
283 return 0;
284}
285
286static int musb_platform_resume(struct musb *musb)
287{
288 u32 l;
289
290 if (!musb->clock)
291 return 0;
292
293 if (musb->xceiv.set_suspend)
294 musb->xceiv.set_suspend(&musb->xceiv, 0);
295
296 if (musb->set_clock)
297 musb->set_clock(musb->clock, 1);
298 else
299 clk_enable(musb->clock);
300
301 l = omap_readl(OTG_SYSCONFIG);
302 l &= ~ENABLEWAKEUP; /* disable wakeup */
303 omap_writel(l, OTG_SYSCONFIG);
304
305 l = omap_readl(OTG_FORCESTDBY);
306 l &= ~ENABLEFORCE; /* disable MSTANDBY */
307 omap_writel(l, OTG_FORCESTDBY);
308
309 return 0;
310}
311
312
313int musb_platform_exit(struct musb *musb)
314{
315
316 omap_vbus_power(musb, 0 /*off*/, 1);
317
318 musb_platform_suspend(musb);
319
320 clk_put(musb->clock);
321 musb->clock = 0;
322
323 return 0;
324}