diff options
Diffstat (limited to 'drivers/usb/host')
94 files changed, 11808 insertions, 4790 deletions
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2d926cec0725..ab085f12d570 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig | |||
@@ -91,14 +91,28 @@ config USB_EHCI_TT_NEWSCHED | |||
91 | 91 | ||
92 | If unsure, say Y. | 92 | If unsure, say Y. |
93 | 93 | ||
94 | config USB_EHCI_HCD_PMC_MSP | ||
95 | tristate "EHCI support for on-chip PMC MSP71xx USB controller" | ||
96 | depends on USB_EHCI_HCD && MSP_HAS_USB | ||
97 | default n | ||
98 | select USB_EHCI_BIG_ENDIAN_DESC | ||
99 | select USB_EHCI_BIG_ENDIAN_MMIO | ||
100 | ---help--- | ||
101 | Enables support for the onchip USB controller on the PMC_MSP7100 Family SoC's. | ||
102 | If unsure, say N. | ||
103 | |||
94 | config USB_EHCI_BIG_ENDIAN_MMIO | 104 | config USB_EHCI_BIG_ENDIAN_MMIO |
95 | bool | 105 | bool |
96 | depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX) | 106 | depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ |
107 | ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ | ||
108 | PPC_MPC512x || CPU_CAVIUM_OCTEON || \ | ||
109 | PMC_MSP || SPARC_LEON) | ||
97 | default y | 110 | default y |
98 | 111 | ||
99 | config USB_EHCI_BIG_ENDIAN_DESC | 112 | config USB_EHCI_BIG_ENDIAN_DESC |
100 | bool | 113 | bool |
101 | depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX) | 114 | depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ |
115 | PPC_MPC512x || PMC_MSP || SPARC_LEON) | ||
102 | default y | 116 | default y |
103 | 117 | ||
104 | config XPS_USB_HCD_XILINX | 118 | config XPS_USB_HCD_XILINX |
@@ -112,10 +126,14 @@ config XPS_USB_HCD_XILINX | |||
112 | support both high speed and full speed devices, or high speed | 126 | support both high speed and full speed devices, or high speed |
113 | devices only. | 127 | devices only. |
114 | 128 | ||
129 | config USB_FSL_MPH_DR_OF | ||
130 | tristate | ||
131 | |||
115 | config USB_EHCI_FSL | 132 | config USB_EHCI_FSL |
116 | bool "Support for Freescale on-chip EHCI USB controller" | 133 | bool "Support for Freescale on-chip EHCI USB controller" |
117 | depends on USB_EHCI_HCD && FSL_SOC | 134 | depends on USB_EHCI_HCD && FSL_SOC |
118 | select USB_EHCI_ROOT_HUB_TT | 135 | select USB_EHCI_ROOT_HUB_TT |
136 | select USB_FSL_MPH_DR_OF if OF | ||
119 | ---help--- | 137 | ---help--- |
120 | Variation of ARC USB block used in some Freescale chips. | 138 | Variation of ARC USB block used in some Freescale chips. |
121 | 139 | ||
@@ -126,6 +144,35 @@ config USB_EHCI_MXC | |||
126 | ---help--- | 144 | ---help--- |
127 | Variation of ARC USB block used in some Freescale chips. | 145 | Variation of ARC USB block used in some Freescale chips. |
128 | 146 | ||
147 | config USB_EHCI_HCD_OMAP | ||
148 | bool "EHCI support for OMAP3 and later chips" | ||
149 | depends on USB_EHCI_HCD && ARCH_OMAP | ||
150 | default y | ||
151 | --- help --- | ||
152 | Enables support for the on-chip EHCI controller on | ||
153 | OMAP3 and later chips. | ||
154 | |||
155 | config USB_EHCI_MSM | ||
156 | bool "Support for MSM on-chip EHCI USB controller" | ||
157 | depends on USB_EHCI_HCD && ARCH_MSM | ||
158 | select USB_EHCI_ROOT_HUB_TT | ||
159 | select USB_MSM_OTG | ||
160 | ---help--- | ||
161 | Enables support for the USB Host controller present on the | ||
162 | Qualcomm chipsets. Root Hub has inbuilt TT. | ||
163 | This driver depends on OTG driver for PHY initialization, | ||
164 | clock management, powering up VBUS, and power management. | ||
165 | This driver is not supported on boards like trout which | ||
166 | has an external PHY. | ||
167 | |||
168 | config USB_EHCI_TEGRA | ||
169 | boolean "NVIDIA Tegra HCD support" | ||
170 | depends on USB_EHCI_HCD && ARCH_TEGRA | ||
171 | select USB_EHCI_ROOT_HUB_TT | ||
172 | help | ||
173 | This driver enables support for the internal USB Host Controllers | ||
174 | found in NVIDIA Tegra SoCs. The controllers are EHCI compliant. | ||
175 | |||
129 | config USB_EHCI_HCD_PPC_OF | 176 | config USB_EHCI_HCD_PPC_OF |
130 | bool "EHCI support for PPC USB controller on OF platform bus" | 177 | bool "EHCI support for PPC USB controller on OF platform bus" |
131 | depends on USB_EHCI_HCD && PPC_OF | 178 | depends on USB_EHCI_HCD && PPC_OF |
@@ -134,12 +181,42 @@ config USB_EHCI_HCD_PPC_OF | |||
134 | Enables support for the USB controller present on the PowerPC | 181 | Enables support for the USB controller present on the PowerPC |
135 | OpenFirmware platform bus. | 182 | OpenFirmware platform bus. |
136 | 183 | ||
184 | config USB_EHCI_SH | ||
185 | bool "EHCI support for SuperH USB controller" | ||
186 | depends on USB_EHCI_HCD && SUPERH | ||
187 | ---help--- | ||
188 | Enables support for the on-chip EHCI controller on the SuperH. | ||
189 | If you use the PCI EHCI controller, this option is not necessary. | ||
190 | |||
191 | config USB_EHCI_S5P | ||
192 | boolean "S5P EHCI support" | ||
193 | depends on USB_EHCI_HCD && PLAT_S5P | ||
194 | help | ||
195 | Enable support for the S5P SOC's on-chip EHCI controller. | ||
196 | |||
137 | config USB_W90X900_EHCI | 197 | config USB_W90X900_EHCI |
138 | bool "W90X900(W90P910) EHCI support" | 198 | bool "W90X900(W90P910) EHCI support" |
139 | depends on USB_EHCI_HCD && ARCH_W90X900 | 199 | depends on USB_EHCI_HCD && ARCH_W90X900 |
140 | ---help--- | 200 | ---help--- |
141 | Enables support for the W90X900 USB controller | 201 | Enables support for the W90X900 USB controller |
142 | 202 | ||
203 | config USB_CNS3XXX_EHCI | ||
204 | bool "Cavium CNS3XXX EHCI Module" | ||
205 | depends on USB_EHCI_HCD && ARCH_CNS3XXX | ||
206 | ---help--- | ||
207 | Enable support for the CNS3XXX SOC's on-chip EHCI controller. | ||
208 | It is needed for high-speed (480Mbit/sec) USB 2.0 device | ||
209 | support. | ||
210 | |||
211 | config USB_EHCI_ATH79 | ||
212 | bool "EHCI support for AR7XXX/AR9XXX SoCs" | ||
213 | depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X) | ||
214 | select USB_EHCI_ROOT_HUB_TT | ||
215 | default y | ||
216 | ---help--- | ||
217 | Enables support for the built-in EHCI controller present | ||
218 | on the Atheros AR7XXX/AR9XXX SoCs. | ||
219 | |||
143 | config USB_OXU210HP_HCD | 220 | config USB_OXU210HP_HCD |
144 | tristate "OXU210HP HCD support" | 221 | tristate "OXU210HP HCD support" |
145 | depends on USB | 222 | depends on USB |
@@ -225,6 +302,14 @@ config USB_OHCI_HCD_OMAP3 | |||
225 | Enables support for the on-chip OHCI controller on | 302 | Enables support for the on-chip OHCI controller on |
226 | OMAP3 and later chips. | 303 | OMAP3 and later chips. |
227 | 304 | ||
305 | config USB_OHCI_ATH79 | ||
306 | bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" | ||
307 | depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) | ||
308 | default y | ||
309 | help | ||
310 | Enables support for the built-in OHCI controller present on the | ||
311 | Atheros AR71XX/AR7240 SoCs. | ||
312 | |||
228 | config USB_OHCI_HCD_PPC_SOC | 313 | config USB_OHCI_HCD_PPC_SOC |
229 | bool "OHCI support for on-chip PPC USB controller" | 314 | bool "OHCI support for on-chip PPC USB controller" |
230 | depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) | 315 | depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) |
@@ -279,6 +364,20 @@ config USB_OHCI_HCD_SSB | |||
279 | 364 | ||
280 | If unsure, say N. | 365 | If unsure, say N. |
281 | 366 | ||
367 | config USB_OHCI_SH | ||
368 | bool "OHCI support for SuperH USB controller" | ||
369 | depends on USB_OHCI_HCD && SUPERH | ||
370 | ---help--- | ||
371 | Enables support for the on-chip OHCI controller on the SuperH. | ||
372 | If you use the PCI OHCI controller, this option is not necessary. | ||
373 | |||
374 | config USB_CNS3XXX_OHCI | ||
375 | bool "Cavium CNS3XXX OHCI Module" | ||
376 | depends on USB_OHCI_HCD && ARCH_CNS3XXX | ||
377 | ---help--- | ||
378 | Enable support for the CNS3XXX SOC's on-chip OHCI controller. | ||
379 | It is needed for low-speed USB 1.0 device support. | ||
380 | |||
282 | config USB_OHCI_BIG_ENDIAN_DESC | 381 | config USB_OHCI_BIG_ENDIAN_DESC |
283 | bool | 382 | bool |
284 | depends on USB_OHCI_HCD | 383 | depends on USB_OHCI_HCD |
@@ -297,7 +396,7 @@ config USB_OHCI_LITTLE_ENDIAN | |||
297 | 396 | ||
298 | config USB_UHCI_HCD | 397 | config USB_UHCI_HCD |
299 | tristate "UHCI HCD (most Intel and VIA) support" | 398 | tristate "UHCI HCD (most Intel and VIA) support" |
300 | depends on USB && PCI | 399 | depends on USB && (PCI || SPARC_LEON) |
301 | ---help--- | 400 | ---help--- |
302 | The Universal Host Controller Interface is a standard by Intel for | 401 | The Universal Host Controller Interface is a standard by Intel for |
303 | accessing the USB hardware in the PC (which is also called the USB | 402 | accessing the USB hardware in the PC (which is also called the USB |
@@ -306,11 +405,27 @@ config USB_UHCI_HCD | |||
306 | with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, | 405 | with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, |
307 | i810, i820) conform to this standard. Also all VIA PCI chipsets | 406 | i810, i820) conform to this standard. Also all VIA PCI chipsets |
308 | (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro | 407 | (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro |
309 | 133). If unsure, say Y. | 408 | 133) and LEON/GRLIB SoCs with the GRUSBHC controller. |
409 | If unsure, say Y. | ||
310 | 410 | ||
311 | To compile this driver as a module, choose M here: the | 411 | To compile this driver as a module, choose M here: the |
312 | module will be called uhci-hcd. | 412 | module will be called uhci-hcd. |
313 | 413 | ||
414 | config USB_UHCI_SUPPORT_NON_PCI_HC | ||
415 | bool | ||
416 | depends on USB_UHCI_HCD | ||
417 | default y if SPARC_LEON | ||
418 | |||
419 | config USB_UHCI_BIG_ENDIAN_MMIO | ||
420 | bool | ||
421 | depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON | ||
422 | default y | ||
423 | |||
424 | config USB_UHCI_BIG_ENDIAN_DESC | ||
425 | bool | ||
426 | depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON | ||
427 | default y | ||
428 | |||
314 | config USB_FHCI_HCD | 429 | config USB_FHCI_HCD |
315 | tristate "Freescale QE USB Host Controller support" | 430 | tristate "Freescale QE USB Host Controller support" |
316 | depends on USB && OF_GPIO && QE_GPIO && QUICC_ENGINE | 431 | depends on USB && OF_GPIO && QE_GPIO && QUICC_ENGINE |
@@ -326,7 +441,7 @@ config FHCI_DEBUG | |||
326 | depends on USB_FHCI_HCD && DEBUG_FS | 441 | depends on USB_FHCI_HCD && DEBUG_FS |
327 | help | 442 | help |
328 | Say "y" to see some FHCI debug information and statistics | 443 | Say "y" to see some FHCI debug information and statistics |
329 | throught debugfs. | 444 | through debugfs. |
330 | 445 | ||
331 | config USB_U132_HCD | 446 | config USB_U132_HCD |
332 | tristate "Elan U132 Adapter Host Controller" | 447 | tristate "Elan U132 Adapter Host Controller" |
@@ -368,6 +483,16 @@ config USB_SL811_HCD | |||
368 | To compile this driver as a module, choose M here: the | 483 | To compile this driver as a module, choose M here: the |
369 | module will be called sl811-hcd. | 484 | module will be called sl811-hcd. |
370 | 485 | ||
486 | config USB_SL811_HCD_ISO | ||
487 | bool "partial ISO support" | ||
488 | depends on USB_SL811_HCD | ||
489 | help | ||
490 | The driver doesn't support iso_frame_desc (yet), but for some simple | ||
491 | devices that just queue one ISO frame per URB, then ISO transfers | ||
492 | "should" work using the normal urb status fields. | ||
493 | |||
494 | If unsure, say N. | ||
495 | |||
371 | config USB_SL811_CS | 496 | config USB_SL811_CS |
372 | tristate "CF/PCMCIA support for SL811HS HCD" | 497 | tristate "CF/PCMCIA support for SL811HS HCD" |
373 | depends on USB_SL811_HCD && PCMCIA | 498 | depends on USB_SL811_HCD && PCMCIA |
@@ -428,3 +553,28 @@ config USB_IMX21_HCD | |||
428 | To compile this driver as a module, choose M here: the | 553 | To compile this driver as a module, choose M here: the |
429 | module will be called "imx21-hcd". | 554 | module will be called "imx21-hcd". |
430 | 555 | ||
556 | config USB_OCTEON_EHCI | ||
557 | bool "Octeon on-chip EHCI support" | ||
558 | depends on USB && USB_EHCI_HCD && CPU_CAVIUM_OCTEON | ||
559 | default n | ||
560 | select USB_EHCI_BIG_ENDIAN_MMIO | ||
561 | help | ||
562 | Enable support for the Octeon II SOC's on-chip EHCI | ||
563 | controller. It is needed for high-speed (480Mbit/sec) | ||
564 | USB 2.0 device support. All CN6XXX based chips with USB are | ||
565 | supported. | ||
566 | |||
567 | config USB_OCTEON_OHCI | ||
568 | bool "Octeon on-chip OHCI support" | ||
569 | depends on USB && USB_OHCI_HCD && CPU_CAVIUM_OCTEON | ||
570 | default USB_OCTEON_EHCI | ||
571 | select USB_OHCI_BIG_ENDIAN_MMIO | ||
572 | select USB_OHCI_LITTLE_ENDIAN | ||
573 | help | ||
574 | Enable support for the Octeon II SOC's on-chip OHCI | ||
575 | controller. It is needed for low-speed USB 1.0 device | ||
576 | support. All CN6XXX based chips with USB are supported. | ||
577 | |||
578 | config USB_OCTEON2_COMMON | ||
579 | bool | ||
580 | default y if USB_OCTEON_EHCI || USB_OCTEON_OHCI | ||
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index b6315aa47f7a..624a362f2fee 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile | |||
@@ -2,17 +2,17 @@ | |||
2 | # Makefile for USB Host Controller Drivers | 2 | # Makefile for USB Host Controller Drivers |
3 | # | 3 | # |
4 | 4 | ||
5 | ifeq ($(CONFIG_USB_DEBUG),y) | 5 | ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG |
6 | EXTRA_CFLAGS += -DDEBUG | 6 | |
7 | endif | 7 | isp1760-y := isp1760-hcd.o isp1760-if.o |
8 | 8 | ||
9 | isp1760-objs := isp1760-hcd.o isp1760-if.o | 9 | fhci-y := fhci-hcd.o fhci-hub.o fhci-q.o |
10 | fhci-objs := fhci-hcd.o fhci-hub.o fhci-q.o fhci-mem.o \ | 10 | fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o |
11 | fhci-tds.o fhci-sched.o | 11 | |
12 | ifeq ($(CONFIG_FHCI_DEBUG),y) | 12 | fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o |
13 | fhci-objs += fhci-dbg.o | 13 | |
14 | endif | 14 | xhci-hcd-y := xhci.o xhci-mem.o xhci-pci.o |
15 | xhci-hcd-objs := xhci.o xhci-mem.o xhci-pci.o xhci-ring.o xhci-hub.o xhci-dbg.o | 15 | xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o |
16 | 16 | ||
17 | obj-$(CONFIG_USB_WHCI_HCD) += whci/ | 17 | obj-$(CONFIG_USB_WHCI_HCD) += whci/ |
18 | 18 | ||
@@ -33,4 +33,5 @@ obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o | |||
33 | obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o | 33 | obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o |
34 | obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o | 34 | obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o |
35 | obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o | 35 | obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o |
36 | 36 | obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o | |
37 | obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o | ||
diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c new file mode 100644 index 000000000000..aa248c2f2c60 --- /dev/null +++ b/drivers/usb/host/ehci-ath79.c | |||
@@ -0,0 +1,204 @@ | |||
1 | /* | ||
2 | * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. | ||
3 | * | ||
4 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> | ||
5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | ||
6 | * | ||
7 | * Parts of this file are based on Atheros' 2.6.15 BSP | ||
8 | * Copyright (C) 2007 Atheros Communications, Inc. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License version 2 as published | ||
12 | * by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/platform_device.h> | ||
16 | |||
17 | enum { | ||
18 | EHCI_ATH79_IP_V1 = 0, | ||
19 | EHCI_ATH79_IP_V2, | ||
20 | }; | ||
21 | |||
22 | static const struct platform_device_id ehci_ath79_id_table[] = { | ||
23 | { | ||
24 | .name = "ar71xx-ehci", | ||
25 | .driver_data = EHCI_ATH79_IP_V1, | ||
26 | }, | ||
27 | { | ||
28 | .name = "ar724x-ehci", | ||
29 | .driver_data = EHCI_ATH79_IP_V2, | ||
30 | }, | ||
31 | { | ||
32 | .name = "ar913x-ehci", | ||
33 | .driver_data = EHCI_ATH79_IP_V2, | ||
34 | }, | ||
35 | { | ||
36 | /* terminating entry */ | ||
37 | }, | ||
38 | }; | ||
39 | |||
40 | MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); | ||
41 | |||
42 | static int ehci_ath79_init(struct usb_hcd *hcd) | ||
43 | { | ||
44 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
45 | struct platform_device *pdev = to_platform_device(hcd->self.controller); | ||
46 | const struct platform_device_id *id; | ||
47 | int ret; | ||
48 | |||
49 | id = platform_get_device_id(pdev); | ||
50 | if (!id) { | ||
51 | dev_err(hcd->self.controller, "missing device id\n"); | ||
52 | return -EINVAL; | ||
53 | } | ||
54 | |||
55 | switch (id->driver_data) { | ||
56 | case EHCI_ATH79_IP_V1: | ||
57 | ehci->has_synopsys_hc_bug = 1; | ||
58 | |||
59 | ehci->caps = hcd->regs; | ||
60 | ehci->regs = hcd->regs + | ||
61 | HC_LENGTH(ehci, | ||
62 | ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
63 | break; | ||
64 | |||
65 | case EHCI_ATH79_IP_V2: | ||
66 | hcd->has_tt = 1; | ||
67 | |||
68 | ehci->caps = hcd->regs + 0x100; | ||
69 | ehci->regs = hcd->regs + 0x100 + | ||
70 | HC_LENGTH(ehci, | ||
71 | ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
72 | break; | ||
73 | |||
74 | default: | ||
75 | BUG(); | ||
76 | } | ||
77 | |||
78 | dbg_hcs_params(ehci, "reset"); | ||
79 | dbg_hcc_params(ehci, "reset"); | ||
80 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
81 | ehci->sbrn = 0x20; | ||
82 | |||
83 | ehci_reset(ehci); | ||
84 | |||
85 | ret = ehci_init(hcd); | ||
86 | if (ret) | ||
87 | return ret; | ||
88 | |||
89 | ehci_port_power(ehci, 0); | ||
90 | |||
91 | return 0; | ||
92 | } | ||
93 | |||
94 | static const struct hc_driver ehci_ath79_hc_driver = { | ||
95 | .description = hcd_name, | ||
96 | .product_desc = "Atheros built-in EHCI controller", | ||
97 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
98 | .irq = ehci_irq, | ||
99 | .flags = HCD_MEMORY | HCD_USB2, | ||
100 | |||
101 | .reset = ehci_ath79_init, | ||
102 | .start = ehci_run, | ||
103 | .stop = ehci_stop, | ||
104 | .shutdown = ehci_shutdown, | ||
105 | |||
106 | .urb_enqueue = ehci_urb_enqueue, | ||
107 | .urb_dequeue = ehci_urb_dequeue, | ||
108 | .endpoint_disable = ehci_endpoint_disable, | ||
109 | .endpoint_reset = ehci_endpoint_reset, | ||
110 | |||
111 | .get_frame_number = ehci_get_frame, | ||
112 | |||
113 | .hub_status_data = ehci_hub_status_data, | ||
114 | .hub_control = ehci_hub_control, | ||
115 | |||
116 | .relinquish_port = ehci_relinquish_port, | ||
117 | .port_handed_over = ehci_port_handed_over, | ||
118 | |||
119 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
120 | }; | ||
121 | |||
122 | static int ehci_ath79_probe(struct platform_device *pdev) | ||
123 | { | ||
124 | struct usb_hcd *hcd; | ||
125 | struct resource *res; | ||
126 | int irq; | ||
127 | int ret; | ||
128 | |||
129 | if (usb_disabled()) | ||
130 | return -ENODEV; | ||
131 | |||
132 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
133 | if (!res) { | ||
134 | dev_dbg(&pdev->dev, "no IRQ specified\n"); | ||
135 | return -ENODEV; | ||
136 | } | ||
137 | irq = res->start; | ||
138 | |||
139 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
140 | if (!res) { | ||
141 | dev_dbg(&pdev->dev, "no base address specified\n"); | ||
142 | return -ENODEV; | ||
143 | } | ||
144 | |||
145 | hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, | ||
146 | dev_name(&pdev->dev)); | ||
147 | if (!hcd) | ||
148 | return -ENOMEM; | ||
149 | |||
150 | hcd->rsrc_start = res->start; | ||
151 | hcd->rsrc_len = res->end - res->start + 1; | ||
152 | |||
153 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
154 | dev_dbg(&pdev->dev, "controller already in use\n"); | ||
155 | ret = -EBUSY; | ||
156 | goto err_put_hcd; | ||
157 | } | ||
158 | |||
159 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
160 | if (!hcd->regs) { | ||
161 | dev_dbg(&pdev->dev, "error mapping memory\n"); | ||
162 | ret = -EFAULT; | ||
163 | goto err_release_region; | ||
164 | } | ||
165 | |||
166 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | ||
167 | if (ret) | ||
168 | goto err_iounmap; | ||
169 | |||
170 | return 0; | ||
171 | |||
172 | err_iounmap: | ||
173 | iounmap(hcd->regs); | ||
174 | |||
175 | err_release_region: | ||
176 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
177 | err_put_hcd: | ||
178 | usb_put_hcd(hcd); | ||
179 | return ret; | ||
180 | } | ||
181 | |||
182 | static int ehci_ath79_remove(struct platform_device *pdev) | ||
183 | { | ||
184 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
185 | |||
186 | usb_remove_hcd(hcd); | ||
187 | iounmap(hcd->regs); | ||
188 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
189 | usb_put_hcd(hcd); | ||
190 | |||
191 | return 0; | ||
192 | } | ||
193 | |||
194 | static struct platform_driver ehci_ath79_driver = { | ||
195 | .probe = ehci_ath79_probe, | ||
196 | .remove = ehci_ath79_remove, | ||
197 | .id_table = ehci_ath79_id_table, | ||
198 | .driver = { | ||
199 | .owner = THIS_MODULE, | ||
200 | .name = "ath79-ehci", | ||
201 | } | ||
202 | }; | ||
203 | |||
204 | MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); | ||
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 51bd0edf544f..a5a3ef1f0096 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c | |||
@@ -56,7 +56,7 @@ static int ehci_atmel_setup(struct usb_hcd *hcd) | |||
56 | /* registers start at offset 0x0 */ | 56 | /* registers start at offset 0x0 */ |
57 | ehci->caps = hcd->regs; | 57 | ehci->caps = hcd->regs; |
58 | ehci->regs = hcd->regs + | 58 | ehci->regs = hcd->regs + |
59 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 59 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
60 | dbg_hcs_params(ehci, "reset"); | 60 | dbg_hcs_params(ehci, "reset"); |
61 | dbg_hcc_params(ehci, "reset"); | 61 | dbg_hcc_params(ehci, "reset"); |
62 | 62 | ||
@@ -99,6 +99,7 @@ static const struct hc_driver ehci_atmel_hc_driver = { | |||
99 | .urb_enqueue = ehci_urb_enqueue, | 99 | .urb_enqueue = ehci_urb_enqueue, |
100 | .urb_dequeue = ehci_urb_dequeue, | 100 | .urb_dequeue = ehci_urb_dequeue, |
101 | .endpoint_disable = ehci_endpoint_disable, | 101 | .endpoint_disable = ehci_endpoint_disable, |
102 | .endpoint_reset = ehci_endpoint_reset, | ||
102 | 103 | ||
103 | /* scheduling support */ | 104 | /* scheduling support */ |
104 | .get_frame_number = ehci_get_frame, | 105 | .get_frame_number = ehci_get_frame, |
@@ -110,9 +111,11 @@ static const struct hc_driver ehci_atmel_hc_driver = { | |||
110 | .bus_resume = ehci_bus_resume, | 111 | .bus_resume = ehci_bus_resume, |
111 | .relinquish_port = ehci_relinquish_port, | 112 | .relinquish_port = ehci_relinquish_port, |
112 | .port_handed_over = ehci_port_handed_over, | 113 | .port_handed_over = ehci_port_handed_over, |
114 | |||
115 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
113 | }; | 116 | }; |
114 | 117 | ||
115 | static int __init ehci_atmel_drv_probe(struct platform_device *pdev) | 118 | static int __devinit ehci_atmel_drv_probe(struct platform_device *pdev) |
116 | { | 119 | { |
117 | struct usb_hcd *hcd; | 120 | struct usb_hcd *hcd; |
118 | const struct hc_driver *driver = &ehci_atmel_hc_driver; | 121 | const struct hc_driver *driver = &ehci_atmel_hc_driver; |
@@ -204,7 +207,7 @@ fail_create_hcd: | |||
204 | return retval; | 207 | return retval; |
205 | } | 208 | } |
206 | 209 | ||
207 | static int __exit ehci_atmel_drv_remove(struct platform_device *pdev) | 210 | static int __devexit ehci_atmel_drv_remove(struct platform_device *pdev) |
208 | { | 211 | { |
209 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | 212 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
210 | 213 | ||
@@ -224,7 +227,7 @@ static int __exit ehci_atmel_drv_remove(struct platform_device *pdev) | |||
224 | 227 | ||
225 | static struct platform_driver ehci_atmel_driver = { | 228 | static struct platform_driver ehci_atmel_driver = { |
226 | .probe = ehci_atmel_drv_probe, | 229 | .probe = ehci_atmel_drv_probe, |
227 | .remove = __exit_p(ehci_atmel_drv_remove), | 230 | .remove = __devexit_p(ehci_atmel_drv_remove), |
228 | .shutdown = usb_hcd_platform_shutdown, | 231 | .shutdown = usb_hcd_platform_shutdown, |
229 | .driver.name = "atmel-ehci", | 232 | .driver.name = "atmel-ehci", |
230 | }; | 233 | }; |
diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c index 2baf8a849086..42ae57409908 100644 --- a/drivers/usb/host/ehci-au1xxx.c +++ b/drivers/usb/host/ehci-au1xxx.c | |||
@@ -175,7 +175,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) | |||
175 | 175 | ||
176 | ehci = hcd_to_ehci(hcd); | 176 | ehci = hcd_to_ehci(hcd); |
177 | ehci->caps = hcd->regs; | 177 | ehci->caps = hcd->regs; |
178 | ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); | 178 | ehci->regs = hcd->regs + |
179 | HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); | ||
179 | /* cache this readonly data; minimize chip reads */ | 180 | /* cache this readonly data; minimize chip reads */ |
180 | ehci->hcs_params = readl(&ehci->caps->hcs_params); | 181 | ehci->hcs_params = readl(&ehci->caps->hcs_params); |
181 | 182 | ||
@@ -215,10 +216,7 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev) | |||
215 | struct usb_hcd *hcd = dev_get_drvdata(dev); | 216 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
216 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 217 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
217 | unsigned long flags; | 218 | unsigned long flags; |
218 | int rc; | 219 | int rc = 0; |
219 | |||
220 | return 0; | ||
221 | rc = 0; | ||
222 | 220 | ||
223 | if (time_before(jiffies, ehci->next_statechange)) | 221 | if (time_before(jiffies, ehci->next_statechange)) |
224 | msleep(10); | 222 | msleep(10); |
@@ -227,19 +225,19 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev) | |||
227 | * mark HW unaccessible. The PM and USB cores make sure that | 225 | * mark HW unaccessible. The PM and USB cores make sure that |
228 | * the root hub is either suspended or stopped. | 226 | * the root hub is either suspended or stopped. |
229 | */ | 227 | */ |
230 | spin_lock_irqsave(&ehci->lock, flags); | ||
231 | ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); | 228 | ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); |
229 | spin_lock_irqsave(&ehci->lock, flags); | ||
232 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | 230 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
233 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); | 231 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); |
234 | 232 | ||
235 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | 233 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
236 | |||
237 | au1xxx_stop_ehc(); | ||
238 | spin_unlock_irqrestore(&ehci->lock, flags); | 234 | spin_unlock_irqrestore(&ehci->lock, flags); |
239 | 235 | ||
240 | // could save FLADJ in case of Vaux power loss | 236 | // could save FLADJ in case of Vaux power loss |
241 | // ... we'd only use it to handle clock skew | 237 | // ... we'd only use it to handle clock skew |
242 | 238 | ||
239 | au1xxx_stop_ehc(); | ||
240 | |||
243 | return rc; | 241 | return rc; |
244 | } | 242 | } |
245 | 243 | ||
diff --git a/drivers/usb/host/ehci-cns3xxx.c b/drivers/usb/host/ehci-cns3xxx.c new file mode 100644 index 000000000000..d41745c6f0c4 --- /dev/null +++ b/drivers/usb/host/ehci-cns3xxx.c | |||
@@ -0,0 +1,171 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Cavium Networks | ||
3 | * | ||
4 | * This file is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License, Version 2, as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #include <linux/platform_device.h> | ||
10 | #include <linux/atomic.h> | ||
11 | #include <mach/cns3xxx.h> | ||
12 | #include <mach/pm.h> | ||
13 | |||
14 | static int cns3xxx_ehci_init(struct usb_hcd *hcd) | ||
15 | { | ||
16 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
17 | int retval; | ||
18 | |||
19 | /* | ||
20 | * EHCI and OHCI share the same clock and power, | ||
21 | * resetting twice would cause the 1st controller been reset. | ||
22 | * Therefore only do power up at the first up device, and | ||
23 | * power down at the last down device. | ||
24 | * | ||
25 | * Set USB AHB INCR length to 16 | ||
26 | */ | ||
27 | if (atomic_inc_return(&usb_pwr_ref) == 1) { | ||
28 | cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); | ||
29 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); | ||
30 | cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); | ||
31 | __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), | ||
32 | MISC_CHIP_CONFIG_REG); | ||
33 | } | ||
34 | |||
35 | ehci->caps = hcd->regs; | ||
36 | ehci->regs = hcd->regs | ||
37 | + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
38 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
39 | |||
40 | hcd->has_tt = 0; | ||
41 | ehci_reset(ehci); | ||
42 | |||
43 | retval = ehci_init(hcd); | ||
44 | if (retval) | ||
45 | return retval; | ||
46 | |||
47 | ehci_port_power(ehci, 0); | ||
48 | |||
49 | return retval; | ||
50 | } | ||
51 | |||
52 | static const struct hc_driver cns3xxx_ehci_hc_driver = { | ||
53 | .description = hcd_name, | ||
54 | .product_desc = "CNS3XXX EHCI Host Controller", | ||
55 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
56 | .irq = ehci_irq, | ||
57 | .flags = HCD_MEMORY | HCD_USB2, | ||
58 | .reset = cns3xxx_ehci_init, | ||
59 | .start = ehci_run, | ||
60 | .stop = ehci_stop, | ||
61 | .shutdown = ehci_shutdown, | ||
62 | .urb_enqueue = ehci_urb_enqueue, | ||
63 | .urb_dequeue = ehci_urb_dequeue, | ||
64 | .endpoint_disable = ehci_endpoint_disable, | ||
65 | .endpoint_reset = ehci_endpoint_reset, | ||
66 | .get_frame_number = ehci_get_frame, | ||
67 | .hub_status_data = ehci_hub_status_data, | ||
68 | .hub_control = ehci_hub_control, | ||
69 | #ifdef CONFIG_PM | ||
70 | .bus_suspend = ehci_bus_suspend, | ||
71 | .bus_resume = ehci_bus_resume, | ||
72 | #endif | ||
73 | .relinquish_port = ehci_relinquish_port, | ||
74 | .port_handed_over = ehci_port_handed_over, | ||
75 | |||
76 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
77 | }; | ||
78 | |||
79 | static int cns3xxx_ehci_probe(struct platform_device *pdev) | ||
80 | { | ||
81 | struct device *dev = &pdev->dev; | ||
82 | struct usb_hcd *hcd; | ||
83 | const struct hc_driver *driver = &cns3xxx_ehci_hc_driver; | ||
84 | struct resource *res; | ||
85 | int irq; | ||
86 | int retval; | ||
87 | |||
88 | if (usb_disabled()) | ||
89 | return -ENODEV; | ||
90 | |||
91 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
92 | if (!res) { | ||
93 | dev_err(dev, "Found HC with no IRQ.\n"); | ||
94 | return -ENODEV; | ||
95 | } | ||
96 | irq = res->start; | ||
97 | |||
98 | hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); | ||
99 | if (!hcd) | ||
100 | return -ENOMEM; | ||
101 | |||
102 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
103 | if (!res) { | ||
104 | dev_err(dev, "Found HC with no register addr.\n"); | ||
105 | retval = -ENODEV; | ||
106 | goto err1; | ||
107 | } | ||
108 | |||
109 | hcd->rsrc_start = res->start; | ||
110 | hcd->rsrc_len = res->end - res->start + 1; | ||
111 | |||
112 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, | ||
113 | driver->description)) { | ||
114 | dev_dbg(dev, "controller already in use\n"); | ||
115 | retval = -EBUSY; | ||
116 | goto err1; | ||
117 | } | ||
118 | |||
119 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
120 | if (hcd->regs == NULL) { | ||
121 | dev_dbg(dev, "error mapping memory\n"); | ||
122 | retval = -EFAULT; | ||
123 | goto err2; | ||
124 | } | ||
125 | |||
126 | retval = usb_add_hcd(hcd, irq, IRQF_SHARED); | ||
127 | if (retval == 0) | ||
128 | return retval; | ||
129 | |||
130 | iounmap(hcd->regs); | ||
131 | err2: | ||
132 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
133 | err1: | ||
134 | usb_put_hcd(hcd); | ||
135 | |||
136 | return retval; | ||
137 | } | ||
138 | |||
139 | static int cns3xxx_ehci_remove(struct platform_device *pdev) | ||
140 | { | ||
141 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
142 | |||
143 | usb_remove_hcd(hcd); | ||
144 | iounmap(hcd->regs); | ||
145 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
146 | |||
147 | /* | ||
148 | * EHCI and OHCI share the same clock and power, | ||
149 | * resetting twice would cause the 1st controller been reset. | ||
150 | * Therefore only do power up at the first up device, and | ||
151 | * power down at the last down device. | ||
152 | */ | ||
153 | if (atomic_dec_return(&usb_pwr_ref) == 0) | ||
154 | cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); | ||
155 | |||
156 | usb_put_hcd(hcd); | ||
157 | |||
158 | platform_set_drvdata(pdev, NULL); | ||
159 | |||
160 | return 0; | ||
161 | } | ||
162 | |||
163 | MODULE_ALIAS("platform:cns3xxx-ehci"); | ||
164 | |||
165 | static struct platform_driver cns3xxx_ehci_driver = { | ||
166 | .probe = cns3xxx_ehci_probe, | ||
167 | .remove = cns3xxx_ehci_remove, | ||
168 | .driver = { | ||
169 | .name = "cns3xxx-ehci", | ||
170 | }, | ||
171 | }; | ||
diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c index 76b7fd2d838a..40a844c1dbb4 100644 --- a/drivers/usb/host/ehci-dbg.c +++ b/drivers/usb/host/ehci-dbg.c | |||
@@ -28,11 +28,9 @@ | |||
28 | dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args ) | 28 | dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args ) |
29 | 29 | ||
30 | #ifdef VERBOSE_DEBUG | 30 | #ifdef VERBOSE_DEBUG |
31 | # define vdbg dbg | ||
32 | # define ehci_vdbg ehci_dbg | 31 | # define ehci_vdbg ehci_dbg |
33 | #else | 32 | #else |
34 | # define vdbg(fmt,args...) do { } while (0) | 33 | static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {} |
35 | # define ehci_vdbg(ehci, fmt, args...) do { } while (0) | ||
36 | #endif | 34 | #endif |
37 | 35 | ||
38 | #ifdef DEBUG | 36 | #ifdef DEBUG |
@@ -369,18 +367,21 @@ static const struct file_operations debug_async_fops = { | |||
369 | .open = debug_async_open, | 367 | .open = debug_async_open, |
370 | .read = debug_output, | 368 | .read = debug_output, |
371 | .release = debug_close, | 369 | .release = debug_close, |
370 | .llseek = default_llseek, | ||
372 | }; | 371 | }; |
373 | static const struct file_operations debug_periodic_fops = { | 372 | static const struct file_operations debug_periodic_fops = { |
374 | .owner = THIS_MODULE, | 373 | .owner = THIS_MODULE, |
375 | .open = debug_periodic_open, | 374 | .open = debug_periodic_open, |
376 | .read = debug_output, | 375 | .read = debug_output, |
377 | .release = debug_close, | 376 | .release = debug_close, |
377 | .llseek = default_llseek, | ||
378 | }; | 378 | }; |
379 | static const struct file_operations debug_registers_fops = { | 379 | static const struct file_operations debug_registers_fops = { |
380 | .owner = THIS_MODULE, | 380 | .owner = THIS_MODULE, |
381 | .open = debug_registers_open, | 381 | .open = debug_registers_open, |
382 | .read = debug_output, | 382 | .read = debug_output, |
383 | .release = debug_close, | 383 | .release = debug_close, |
384 | .llseek = default_llseek, | ||
384 | }; | 385 | }; |
385 | static const struct file_operations debug_lpm_fops = { | 386 | static const struct file_operations debug_lpm_fops = { |
386 | .owner = THIS_MODULE, | 387 | .owner = THIS_MODULE, |
@@ -388,6 +389,7 @@ static const struct file_operations debug_lpm_fops = { | |||
388 | .read = debug_lpm_read, | 389 | .read = debug_lpm_read, |
389 | .write = debug_lpm_write, | 390 | .write = debug_lpm_write, |
390 | .release = debug_lpm_close, | 391 | .release = debug_lpm_close, |
392 | .llseek = noop_llseek, | ||
391 | }; | 393 | }; |
392 | 394 | ||
393 | static struct dentry *ehci_debug_root; | 395 | static struct dentry *ehci_debug_root; |
@@ -724,7 +726,7 @@ static ssize_t fill_registers_buffer(struct debug_buffer *buf) | |||
724 | } | 726 | } |
725 | 727 | ||
726 | /* Capability Registers */ | 728 | /* Capability Registers */ |
727 | i = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 729 | i = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
728 | temp = scnprintf (next, size, | 730 | temp = scnprintf (next, size, |
729 | "bus %s, device %s\n" | 731 | "bus %s, device %s\n" |
730 | "%s\n" | 732 | "%s\n" |
@@ -875,7 +877,7 @@ static int fill_buffer(struct debug_buffer *buf) | |||
875 | int ret = 0; | 877 | int ret = 0; |
876 | 878 | ||
877 | if (!buf->output_buf) | 879 | if (!buf->output_buf) |
878 | buf->output_buf = (char *)vmalloc(buf->alloc_size); | 880 | buf->output_buf = vmalloc(buf->alloc_size); |
879 | 881 | ||
880 | if (!buf->output_buf) { | 882 | if (!buf->output_buf) { |
881 | ret = -ENOMEM; | 883 | ret = -ENOMEM; |
@@ -1063,7 +1065,7 @@ static inline void create_debug_files (struct ehci_hcd *ehci) | |||
1063 | &debug_registers_fops)) | 1065 | &debug_registers_fops)) |
1064 | goto file_error; | 1066 | goto file_error; |
1065 | 1067 | ||
1066 | if (!debugfs_create_file("lpm", S_IRUGO|S_IWUGO, ehci->debug_dir, bus, | 1068 | if (!debugfs_create_file("lpm", S_IRUGO|S_IWUSR, ehci->debug_dir, bus, |
1067 | &debug_lpm_fops)) | 1069 | &debug_lpm_fops)) |
1068 | goto file_error; | 1070 | goto file_error; |
1069 | 1071 | ||
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index a416421abfa2..f380bf97e5af 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c | |||
@@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver, | |||
52 | struct resource *res; | 52 | struct resource *res; |
53 | int irq; | 53 | int irq; |
54 | int retval; | 54 | int retval; |
55 | unsigned int temp; | ||
56 | 55 | ||
57 | pr_debug("initializing FSL-SOC USB Controller\n"); | 56 | pr_debug("initializing FSL-SOC USB Controller\n"); |
58 | 57 | ||
@@ -116,17 +115,52 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver, | |||
116 | goto err3; | 115 | goto err3; |
117 | } | 116 | } |
118 | 117 | ||
119 | /* Enable USB controller */ | 118 | pdata->regs = hcd->regs; |
120 | temp = in_be32(hcd->regs + 0x500); | ||
121 | out_be32(hcd->regs + 0x500, temp | 0x4); | ||
122 | 119 | ||
123 | /* Set to Host mode */ | 120 | if (pdata->power_budget) |
124 | temp = in_le32(hcd->regs + 0x1a8); | 121 | hcd->power_budget = pdata->power_budget; |
125 | out_le32(hcd->regs + 0x1a8, temp | 0x3); | 122 | |
123 | /* | ||
124 | * do platform specific init: check the clock, grab/config pins, etc. | ||
125 | */ | ||
126 | if (pdata->init && pdata->init(pdev)) { | ||
127 | retval = -ENODEV; | ||
128 | goto err3; | ||
129 | } | ||
130 | |||
131 | /* Enable USB controller, 83xx or 8536 */ | ||
132 | if (pdata->have_sysif_regs) | ||
133 | setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4); | ||
134 | |||
135 | /* Don't need to set host mode here. It will be done by tdi_reset() */ | ||
126 | 136 | ||
127 | retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | 137 | retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); |
128 | if (retval != 0) | 138 | if (retval != 0) |
129 | goto err4; | 139 | goto err4; |
140 | |||
141 | #ifdef CONFIG_USB_OTG | ||
142 | if (pdata->operating_mode == FSL_USB2_DR_OTG) { | ||
143 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
144 | |||
145 | ehci->transceiver = otg_get_transceiver(); | ||
146 | dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, transceiver=0x%p\n", | ||
147 | hcd, ehci, ehci->transceiver); | ||
148 | |||
149 | if (ehci->transceiver) { | ||
150 | retval = otg_set_host(ehci->transceiver, | ||
151 | &ehci_to_hcd(ehci)->self); | ||
152 | if (retval) { | ||
153 | if (ehci->transceiver) | ||
154 | put_device(ehci->transceiver->dev); | ||
155 | goto err4; | ||
156 | } | ||
157 | } else { | ||
158 | dev_err(&pdev->dev, "can't find transceiver\n"); | ||
159 | retval = -ENODEV; | ||
160 | goto err4; | ||
161 | } | ||
162 | } | ||
163 | #endif | ||
130 | return retval; | 164 | return retval; |
131 | 165 | ||
132 | err4: | 166 | err4: |
@@ -137,6 +171,8 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver, | |||
137 | usb_put_hcd(hcd); | 171 | usb_put_hcd(hcd); |
138 | err1: | 172 | err1: |
139 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); | 173 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); |
174 | if (pdata->exit) | ||
175 | pdata->exit(pdev); | ||
140 | return retval; | 176 | return retval; |
141 | } | 177 | } |
142 | 178 | ||
@@ -154,17 +190,36 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver, | |||
154 | static void usb_hcd_fsl_remove(struct usb_hcd *hcd, | 190 | static void usb_hcd_fsl_remove(struct usb_hcd *hcd, |
155 | struct platform_device *pdev) | 191 | struct platform_device *pdev) |
156 | { | 192 | { |
193 | struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; | ||
194 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
195 | |||
196 | if (ehci->transceiver) { | ||
197 | otg_set_host(ehci->transceiver, NULL); | ||
198 | put_device(ehci->transceiver->dev); | ||
199 | } | ||
200 | |||
157 | usb_remove_hcd(hcd); | 201 | usb_remove_hcd(hcd); |
202 | |||
203 | /* | ||
204 | * do platform specific un-initialization: | ||
205 | * release iomux pins, disable clock, etc. | ||
206 | */ | ||
207 | if (pdata->exit) | ||
208 | pdata->exit(pdev); | ||
158 | iounmap(hcd->regs); | 209 | iounmap(hcd->regs); |
159 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | 210 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); |
160 | usb_put_hcd(hcd); | 211 | usb_put_hcd(hcd); |
161 | } | 212 | } |
162 | 213 | ||
163 | static void mpc83xx_setup_phy(struct ehci_hcd *ehci, | 214 | static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, |
164 | enum fsl_usb2_phy_modes phy_mode, | 215 | enum fsl_usb2_phy_modes phy_mode, |
165 | unsigned int port_offset) | 216 | unsigned int port_offset) |
166 | { | 217 | { |
167 | u32 portsc = 0; | 218 | u32 portsc; |
219 | |||
220 | portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); | ||
221 | portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); | ||
222 | |||
168 | switch (phy_mode) { | 223 | switch (phy_mode) { |
169 | case FSL_USB2_PHY_ULPI: | 224 | case FSL_USB2_PHY_ULPI: |
170 | portsc |= PORT_PTS_ULPI; | 225 | portsc |= PORT_PTS_ULPI; |
@@ -184,20 +239,21 @@ static void mpc83xx_setup_phy(struct ehci_hcd *ehci, | |||
184 | ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); | 239 | ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); |
185 | } | 240 | } |
186 | 241 | ||
187 | static void mpc83xx_usb_setup(struct usb_hcd *hcd) | 242 | static void ehci_fsl_usb_setup(struct ehci_hcd *ehci) |
188 | { | 243 | { |
189 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 244 | struct usb_hcd *hcd = ehci_to_hcd(ehci); |
190 | struct fsl_usb2_platform_data *pdata; | 245 | struct fsl_usb2_platform_data *pdata; |
191 | void __iomem *non_ehci = hcd->regs; | 246 | void __iomem *non_ehci = hcd->regs; |
192 | u32 temp; | 247 | u32 temp; |
193 | 248 | ||
194 | pdata = | 249 | pdata = hcd->self.controller->platform_data; |
195 | (struct fsl_usb2_platform_data *)hcd->self.controller-> | 250 | |
196 | platform_data; | ||
197 | /* Enable PHY interface in the control reg. */ | 251 | /* Enable PHY interface in the control reg. */ |
198 | temp = in_be32(non_ehci + FSL_SOC_USB_CTRL); | 252 | if (pdata->have_sysif_regs) { |
199 | out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004); | 253 | temp = in_be32(non_ehci + FSL_SOC_USB_CTRL); |
200 | out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b); | 254 | out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004); |
255 | out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b); | ||
256 | } | ||
201 | 257 | ||
202 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | 258 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
203 | /* | 259 | /* |
@@ -214,7 +270,7 @@ static void mpc83xx_usb_setup(struct usb_hcd *hcd) | |||
214 | 270 | ||
215 | if ((pdata->operating_mode == FSL_USB2_DR_HOST) || | 271 | if ((pdata->operating_mode == FSL_USB2_DR_HOST) || |
216 | (pdata->operating_mode == FSL_USB2_DR_OTG)) | 272 | (pdata->operating_mode == FSL_USB2_DR_OTG)) |
217 | mpc83xx_setup_phy(ehci, pdata->phy_mode, 0); | 273 | ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); |
218 | 274 | ||
219 | if (pdata->operating_mode == FSL_USB2_MPH_HOST) { | 275 | if (pdata->operating_mode == FSL_USB2_MPH_HOST) { |
220 | unsigned int chip, rev, svr; | 276 | unsigned int chip, rev, svr; |
@@ -228,27 +284,27 @@ static void mpc83xx_usb_setup(struct usb_hcd *hcd) | |||
228 | ehci->has_fsl_port_bug = 1; | 284 | ehci->has_fsl_port_bug = 1; |
229 | 285 | ||
230 | if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) | 286 | if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) |
231 | mpc83xx_setup_phy(ehci, pdata->phy_mode, 0); | 287 | ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); |
232 | if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) | 288 | if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) |
233 | mpc83xx_setup_phy(ehci, pdata->phy_mode, 1); | 289 | ehci_fsl_setup_phy(ehci, pdata->phy_mode, 1); |
234 | } | 290 | } |
235 | 291 | ||
236 | /* put controller in host mode. */ | 292 | if (pdata->have_sysif_regs) { |
237 | ehci_writel(ehci, 0x00000003, non_ehci + FSL_SOC_USB_USBMODE); | ||
238 | #ifdef CONFIG_PPC_85xx | 293 | #ifdef CONFIG_PPC_85xx |
239 | out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008); | 294 | out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008); |
240 | out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080); | 295 | out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080); |
241 | #else | 296 | #else |
242 | out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c); | 297 | out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c); |
243 | out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040); | 298 | out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040); |
244 | #endif | 299 | #endif |
245 | out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); | 300 | out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); |
301 | } | ||
246 | } | 302 | } |
247 | 303 | ||
248 | /* called after powerup, by probe or system-pm "wakeup" */ | 304 | /* called after powerup, by probe or system-pm "wakeup" */ |
249 | static int ehci_fsl_reinit(struct ehci_hcd *ehci) | 305 | static int ehci_fsl_reinit(struct ehci_hcd *ehci) |
250 | { | 306 | { |
251 | mpc83xx_usb_setup(ehci_to_hcd(ehci)); | 307 | ehci_fsl_usb_setup(ehci); |
252 | ehci_port_power(ehci, 0); | 308 | ehci_port_power(ehci, 0); |
253 | 309 | ||
254 | return 0; | 310 | return 0; |
@@ -259,17 +315,24 @@ static int ehci_fsl_setup(struct usb_hcd *hcd) | |||
259 | { | 315 | { |
260 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 316 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
261 | int retval; | 317 | int retval; |
318 | struct fsl_usb2_platform_data *pdata; | ||
319 | |||
320 | pdata = hcd->self.controller->platform_data; | ||
321 | ehci->big_endian_desc = pdata->big_endian_desc; | ||
322 | ehci->big_endian_mmio = pdata->big_endian_mmio; | ||
262 | 323 | ||
263 | /* EHCI registers start at offset 0x100 */ | 324 | /* EHCI registers start at offset 0x100 */ |
264 | ehci->caps = hcd->regs + 0x100; | 325 | ehci->caps = hcd->regs + 0x100; |
265 | ehci->regs = hcd->regs + 0x100 + | 326 | ehci->regs = hcd->regs + 0x100 + |
266 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 327 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
267 | dbg_hcs_params(ehci, "reset"); | 328 | dbg_hcs_params(ehci, "reset"); |
268 | dbg_hcc_params(ehci, "reset"); | 329 | dbg_hcc_params(ehci, "reset"); |
269 | 330 | ||
270 | /* cache this readonly data; minimize chip reads */ | 331 | /* cache this readonly data; minimize chip reads */ |
271 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | 332 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
272 | 333 | ||
334 | hcd->has_tt = 1; | ||
335 | |||
273 | retval = ehci_halt(ehci); | 336 | retval = ehci_halt(ehci); |
274 | if (retval) | 337 | if (retval) |
275 | return retval; | 338 | return retval; |
@@ -279,8 +342,6 @@ static int ehci_fsl_setup(struct usb_hcd *hcd) | |||
279 | if (retval) | 342 | if (retval) |
280 | return retval; | 343 | return retval; |
281 | 344 | ||
282 | hcd->has_tt = 1; | ||
283 | |||
284 | ehci->sbrn = 0x20; | 345 | ehci->sbrn = 0x20; |
285 | 346 | ||
286 | ehci_reset(ehci); | 347 | ehci_reset(ehci); |
@@ -300,6 +361,149 @@ struct ehci_fsl { | |||
300 | 361 | ||
301 | #ifdef CONFIG_PM | 362 | #ifdef CONFIG_PM |
302 | 363 | ||
364 | #ifdef CONFIG_PPC_MPC512x | ||
365 | static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) | ||
366 | { | ||
367 | struct usb_hcd *hcd = dev_get_drvdata(dev); | ||
368 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
369 | struct fsl_usb2_platform_data *pdata = dev->platform_data; | ||
370 | u32 tmp; | ||
371 | |||
372 | #ifdef DEBUG | ||
373 | u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); | ||
374 | mode &= USBMODE_CM_MASK; | ||
375 | tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ | ||
376 | |||
377 | dev_dbg(dev, "suspend=%d already_suspended=%d " | ||
378 | "mode=%d usbcmd %08x\n", pdata->suspended, | ||
379 | pdata->already_suspended, mode, tmp); | ||
380 | #endif | ||
381 | |||
382 | /* | ||
383 | * If the controller is already suspended, then this must be a | ||
384 | * PM suspend. Remember this fact, so that we will leave the | ||
385 | * controller suspended at PM resume time. | ||
386 | */ | ||
387 | if (pdata->suspended) { | ||
388 | dev_dbg(dev, "already suspended, leaving early\n"); | ||
389 | pdata->already_suspended = 1; | ||
390 | return 0; | ||
391 | } | ||
392 | |||
393 | dev_dbg(dev, "suspending...\n"); | ||
394 | |||
395 | hcd->state = HC_STATE_SUSPENDED; | ||
396 | dev->power.power_state = PMSG_SUSPEND; | ||
397 | |||
398 | /* ignore non-host interrupts */ | ||
399 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
400 | |||
401 | /* stop the controller */ | ||
402 | tmp = ehci_readl(ehci, &ehci->regs->command); | ||
403 | tmp &= ~CMD_RUN; | ||
404 | ehci_writel(ehci, tmp, &ehci->regs->command); | ||
405 | |||
406 | /* save EHCI registers */ | ||
407 | pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); | ||
408 | pdata->pm_command &= ~CMD_RUN; | ||
409 | pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); | ||
410 | pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); | ||
411 | pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); | ||
412 | pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); | ||
413 | pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); | ||
414 | pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); | ||
415 | pdata->pm_configured_flag = | ||
416 | ehci_readl(ehci, &ehci->regs->configured_flag); | ||
417 | pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); | ||
418 | pdata->pm_usbgenctrl = ehci_readl(ehci, | ||
419 | hcd->regs + FSL_SOC_USB_USBGENCTRL); | ||
420 | |||
421 | /* clear the W1C bits */ | ||
422 | pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); | ||
423 | |||
424 | pdata->suspended = 1; | ||
425 | |||
426 | /* clear PP to cut power to the port */ | ||
427 | tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); | ||
428 | tmp &= ~PORT_POWER; | ||
429 | ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); | ||
430 | |||
431 | return 0; | ||
432 | } | ||
433 | |||
434 | static int ehci_fsl_mpc512x_drv_resume(struct device *dev) | ||
435 | { | ||
436 | struct usb_hcd *hcd = dev_get_drvdata(dev); | ||
437 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
438 | struct fsl_usb2_platform_data *pdata = dev->platform_data; | ||
439 | u32 tmp; | ||
440 | |||
441 | dev_dbg(dev, "suspend=%d already_suspended=%d\n", | ||
442 | pdata->suspended, pdata->already_suspended); | ||
443 | |||
444 | /* | ||
445 | * If the controller was already suspended at suspend time, | ||
446 | * then don't resume it now. | ||
447 | */ | ||
448 | if (pdata->already_suspended) { | ||
449 | dev_dbg(dev, "already suspended, leaving early\n"); | ||
450 | pdata->already_suspended = 0; | ||
451 | return 0; | ||
452 | } | ||
453 | |||
454 | if (!pdata->suspended) { | ||
455 | dev_dbg(dev, "not suspended, leaving early\n"); | ||
456 | return 0; | ||
457 | } | ||
458 | |||
459 | pdata->suspended = 0; | ||
460 | |||
461 | dev_dbg(dev, "resuming...\n"); | ||
462 | |||
463 | /* set host mode */ | ||
464 | tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); | ||
465 | ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); | ||
466 | |||
467 | ehci_writel(ehci, pdata->pm_usbgenctrl, | ||
468 | hcd->regs + FSL_SOC_USB_USBGENCTRL); | ||
469 | ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, | ||
470 | hcd->regs + FSL_SOC_USB_ISIPHYCTRL); | ||
471 | |||
472 | /* restore EHCI registers */ | ||
473 | ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); | ||
474 | ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); | ||
475 | ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); | ||
476 | ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); | ||
477 | ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); | ||
478 | ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); | ||
479 | ehci_writel(ehci, pdata->pm_configured_flag, | ||
480 | &ehci->regs->configured_flag); | ||
481 | ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); | ||
482 | |||
483 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
484 | hcd->state = HC_STATE_RUNNING; | ||
485 | dev->power.power_state = PMSG_ON; | ||
486 | |||
487 | tmp = ehci_readl(ehci, &ehci->regs->command); | ||
488 | tmp |= CMD_RUN; | ||
489 | ehci_writel(ehci, tmp, &ehci->regs->command); | ||
490 | |||
491 | usb_hcd_resume_root_hub(hcd); | ||
492 | |||
493 | return 0; | ||
494 | } | ||
495 | #else | ||
496 | static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) | ||
497 | { | ||
498 | return 0; | ||
499 | } | ||
500 | |||
501 | static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) | ||
502 | { | ||
503 | return 0; | ||
504 | } | ||
505 | #endif /* CONFIG_PPC_MPC512x */ | ||
506 | |||
303 | static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) | 507 | static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) |
304 | { | 508 | { |
305 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 509 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
@@ -313,6 +517,11 @@ static int ehci_fsl_drv_suspend(struct device *dev) | |||
313 | struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); | 517 | struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); |
314 | void __iomem *non_ehci = hcd->regs; | 518 | void __iomem *non_ehci = hcd->regs; |
315 | 519 | ||
520 | if (of_device_is_compatible(dev->parent->of_node, | ||
521 | "fsl,mpc5121-usb2-dr")) { | ||
522 | return ehci_fsl_mpc512x_drv_suspend(dev); | ||
523 | } | ||
524 | |||
316 | ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), | 525 | ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), |
317 | device_may_wakeup(dev)); | 526 | device_may_wakeup(dev)); |
318 | if (!fsl_deep_sleep()) | 527 | if (!fsl_deep_sleep()) |
@@ -329,6 +538,11 @@ static int ehci_fsl_drv_resume(struct device *dev) | |||
329 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 538 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
330 | void __iomem *non_ehci = hcd->regs; | 539 | void __iomem *non_ehci = hcd->regs; |
331 | 540 | ||
541 | if (of_device_is_compatible(dev->parent->of_node, | ||
542 | "fsl,mpc5121-usb2-dr")) { | ||
543 | return ehci_fsl_mpc512x_drv_resume(dev); | ||
544 | } | ||
545 | |||
332 | ehci_prepare_ports_for_controller_resume(ehci); | 546 | ehci_prepare_ports_for_controller_resume(ehci); |
333 | if (!fsl_deep_sleep()) | 547 | if (!fsl_deep_sleep()) |
334 | return 0; | 548 | return 0; |
@@ -363,6 +577,38 @@ static struct dev_pm_ops ehci_fsl_pm_ops = { | |||
363 | #define EHCI_FSL_PM_OPS NULL | 577 | #define EHCI_FSL_PM_OPS NULL |
364 | #endif /* CONFIG_PM */ | 578 | #endif /* CONFIG_PM */ |
365 | 579 | ||
580 | #ifdef CONFIG_USB_OTG | ||
581 | static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) | ||
582 | { | ||
583 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
584 | u32 status; | ||
585 | |||
586 | if (!port) | ||
587 | return -EINVAL; | ||
588 | |||
589 | port--; | ||
590 | |||
591 | /* start port reset before HNP protocol time out */ | ||
592 | status = readl(&ehci->regs->port_status[port]); | ||
593 | if (!(status & PORT_CONNECT)) | ||
594 | return -ENODEV; | ||
595 | |||
596 | /* khubd will finish the reset later */ | ||
597 | if (ehci_is_TDI(ehci)) { | ||
598 | writel(PORT_RESET | | ||
599 | (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), | ||
600 | &ehci->regs->port_status[port]); | ||
601 | } else { | ||
602 | writel(PORT_RESET, &ehci->regs->port_status[port]); | ||
603 | } | ||
604 | |||
605 | return 0; | ||
606 | } | ||
607 | #else | ||
608 | #define ehci_start_port_reset NULL | ||
609 | #endif /* CONFIG_USB_OTG */ | ||
610 | |||
611 | |||
366 | static const struct hc_driver ehci_fsl_hc_driver = { | 612 | static const struct hc_driver ehci_fsl_hc_driver = { |
367 | .description = hcd_name, | 613 | .description = hcd_name, |
368 | .product_desc = "Freescale On-Chip EHCI Host Controller", | 614 | .product_desc = "Freescale On-Chip EHCI Host Controller", |
@@ -372,7 +618,7 @@ static const struct hc_driver ehci_fsl_hc_driver = { | |||
372 | * generic hardware linkage | 618 | * generic hardware linkage |
373 | */ | 619 | */ |
374 | .irq = ehci_irq, | 620 | .irq = ehci_irq, |
375 | .flags = HCD_USB2, | 621 | .flags = HCD_USB2 | HCD_MEMORY, |
376 | 622 | ||
377 | /* | 623 | /* |
378 | * basic lifecycle operations | 624 | * basic lifecycle operations |
@@ -402,6 +648,7 @@ static const struct hc_driver ehci_fsl_hc_driver = { | |||
402 | .hub_control = ehci_hub_control, | 648 | .hub_control = ehci_hub_control, |
403 | .bus_suspend = ehci_bus_suspend, | 649 | .bus_suspend = ehci_bus_suspend, |
404 | .bus_resume = ehci_bus_resume, | 650 | .bus_resume = ehci_bus_resume, |
651 | .start_port_reset = ehci_start_port_reset, | ||
405 | .relinquish_port = ehci_relinquish_port, | 652 | .relinquish_port = ehci_relinquish_port, |
406 | .port_handed_over = ehci_port_handed_over, | 653 | .port_handed_over = ehci_port_handed_over, |
407 | 654 | ||
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h index b5e59db53347..491806221165 100644 --- a/drivers/usb/host/ehci-fsl.h +++ b/drivers/usb/host/ehci-fsl.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2005 freescale semiconductor | 1 | /* Copyright (C) 2005-2010 Freescale Semiconductor, Inc. |
2 | * Copyright (c) 2005 MontaVista Software | 2 | * Copyright (c) 2005 MontaVista Software |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
@@ -28,6 +28,17 @@ | |||
28 | #define PORT_PTS_PTW (1<<28) | 28 | #define PORT_PTS_PTW (1<<28) |
29 | #define FSL_SOC_USB_PORTSC2 0x188 | 29 | #define FSL_SOC_USB_PORTSC2 0x188 |
30 | #define FSL_SOC_USB_USBMODE 0x1a8 | 30 | #define FSL_SOC_USB_USBMODE 0x1a8 |
31 | #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ | ||
32 | #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ | ||
33 | #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ | ||
34 | |||
35 | #define FSL_SOC_USB_USBGENCTRL 0x200 | ||
36 | #define USBGENCTRL_PPP (1 << 3) | ||
37 | #define USBGENCTRL_PFP (1 << 2) | ||
38 | #define FSL_SOC_USB_ISIPHYCTRL 0x204 | ||
39 | #define ISIPHYCTRL_PXE (1) | ||
40 | #define ISIPHYCTRL_PHYE (1 << 4) | ||
41 | |||
31 | #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ | 42 | #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ |
32 | #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ | 43 | #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ |
33 | #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ | 44 | #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ |
diff --git a/drivers/usb/host/ehci-grlib.c b/drivers/usb/host/ehci-grlib.c new file mode 100644 index 000000000000..93b230dc51a2 --- /dev/null +++ b/drivers/usb/host/ehci-grlib.c | |||
@@ -0,0 +1,242 @@ | |||
1 | /* | ||
2 | * Driver for Aeroflex Gaisler GRLIB GRUSBHC EHCI host controller | ||
3 | * | ||
4 | * GRUSBHC is typically found on LEON/GRLIB SoCs | ||
5 | * | ||
6 | * (c) Jan Andersson <jan@gaisler.com> | ||
7 | * | ||
8 | * Based on ehci-ppc-of.c which is: | ||
9 | * (c) Valentine Barshak <vbarshak@ru.mvista.com> | ||
10 | * and in turn based on "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de> | ||
11 | * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com> | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify it | ||
14 | * under the terms of the GNU General Public License as published by the | ||
15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
16 | * option) any later version. | ||
17 | * | ||
18 | * This program is distributed in the hope that it will be useful, but | ||
19 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
20 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
21 | * for more details. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License | ||
24 | * along with this program; if not, write to the Free Software Foundation, | ||
25 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
26 | */ | ||
27 | |||
28 | |||
29 | #include <linux/signal.h> | ||
30 | |||
31 | #include <linux/of_irq.h> | ||
32 | #include <linux/of_address.h> | ||
33 | #include <linux/of_platform.h> | ||
34 | |||
35 | #define GRUSBHC_HCIVERSION 0x0100 /* Known value of cap. reg. HCIVERSION */ | ||
36 | |||
37 | /* called during probe() after chip reset completes */ | ||
38 | static int ehci_grlib_setup(struct usb_hcd *hcd) | ||
39 | { | ||
40 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
41 | int retval; | ||
42 | |||
43 | retval = ehci_halt(ehci); | ||
44 | if (retval) | ||
45 | return retval; | ||
46 | |||
47 | retval = ehci_init(hcd); | ||
48 | if (retval) | ||
49 | return retval; | ||
50 | |||
51 | ehci->sbrn = 0x20; | ||
52 | ehci_port_power(ehci, 1); | ||
53 | |||
54 | return ehci_reset(ehci); | ||
55 | } | ||
56 | |||
57 | |||
58 | static const struct hc_driver ehci_grlib_hc_driver = { | ||
59 | .description = hcd_name, | ||
60 | .product_desc = "GRLIB GRUSBHC EHCI", | ||
61 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
62 | |||
63 | /* | ||
64 | * generic hardware linkage | ||
65 | */ | ||
66 | .irq = ehci_irq, | ||
67 | .flags = HCD_MEMORY | HCD_USB2, | ||
68 | |||
69 | /* | ||
70 | * basic lifecycle operations | ||
71 | */ | ||
72 | .reset = ehci_grlib_setup, | ||
73 | .start = ehci_run, | ||
74 | .stop = ehci_stop, | ||
75 | .shutdown = ehci_shutdown, | ||
76 | |||
77 | /* | ||
78 | * managing i/o requests and associated device resources | ||
79 | */ | ||
80 | .urb_enqueue = ehci_urb_enqueue, | ||
81 | .urb_dequeue = ehci_urb_dequeue, | ||
82 | .endpoint_disable = ehci_endpoint_disable, | ||
83 | .endpoint_reset = ehci_endpoint_reset, | ||
84 | |||
85 | /* | ||
86 | * scheduling support | ||
87 | */ | ||
88 | .get_frame_number = ehci_get_frame, | ||
89 | |||
90 | /* | ||
91 | * root hub support | ||
92 | */ | ||
93 | .hub_status_data = ehci_hub_status_data, | ||
94 | .hub_control = ehci_hub_control, | ||
95 | #ifdef CONFIG_PM | ||
96 | .bus_suspend = ehci_bus_suspend, | ||
97 | .bus_resume = ehci_bus_resume, | ||
98 | #endif | ||
99 | .relinquish_port = ehci_relinquish_port, | ||
100 | .port_handed_over = ehci_port_handed_over, | ||
101 | |||
102 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
103 | }; | ||
104 | |||
105 | |||
106 | static int __devinit ehci_hcd_grlib_probe(struct platform_device *op) | ||
107 | { | ||
108 | struct device_node *dn = op->dev.of_node; | ||
109 | struct usb_hcd *hcd; | ||
110 | struct ehci_hcd *ehci = NULL; | ||
111 | struct resource res; | ||
112 | u32 hc_capbase; | ||
113 | int irq; | ||
114 | int rv; | ||
115 | |||
116 | if (usb_disabled()) | ||
117 | return -ENODEV; | ||
118 | |||
119 | dev_dbg(&op->dev, "initializing GRUSBHC EHCI USB Controller\n"); | ||
120 | |||
121 | rv = of_address_to_resource(dn, 0, &res); | ||
122 | if (rv) | ||
123 | return rv; | ||
124 | |||
125 | /* usb_create_hcd requires dma_mask != NULL */ | ||
126 | op->dev.dma_mask = &op->dev.coherent_dma_mask; | ||
127 | hcd = usb_create_hcd(&ehci_grlib_hc_driver, &op->dev, | ||
128 | "GRUSBHC EHCI USB"); | ||
129 | if (!hcd) | ||
130 | return -ENOMEM; | ||
131 | |||
132 | hcd->rsrc_start = res.start; | ||
133 | hcd->rsrc_len = res.end - res.start + 1; | ||
134 | |||
135 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
136 | printk(KERN_ERR "%s: request_mem_region failed\n", __FILE__); | ||
137 | rv = -EBUSY; | ||
138 | goto err_rmr; | ||
139 | } | ||
140 | |||
141 | irq = irq_of_parse_and_map(dn, 0); | ||
142 | if (irq == NO_IRQ) { | ||
143 | printk(KERN_ERR "%s: irq_of_parse_and_map failed\n", __FILE__); | ||
144 | rv = -EBUSY; | ||
145 | goto err_irq; | ||
146 | } | ||
147 | |||
148 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
149 | if (!hcd->regs) { | ||
150 | printk(KERN_ERR "%s: ioremap failed\n", __FILE__); | ||
151 | rv = -ENOMEM; | ||
152 | goto err_ioremap; | ||
153 | } | ||
154 | |||
155 | ehci = hcd_to_ehci(hcd); | ||
156 | |||
157 | ehci->caps = hcd->regs; | ||
158 | |||
159 | /* determine endianness of this implementation */ | ||
160 | hc_capbase = ehci_readl(ehci, &ehci->caps->hc_capbase); | ||
161 | if (HC_VERSION(ehci, hc_capbase) != GRUSBHC_HCIVERSION) { | ||
162 | ehci->big_endian_mmio = 1; | ||
163 | ehci->big_endian_desc = 1; | ||
164 | ehci->big_endian_capbase = 1; | ||
165 | } | ||
166 | |||
167 | ehci->regs = hcd->regs + | ||
168 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
169 | |||
170 | /* cache this readonly data; minimize chip reads */ | ||
171 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
172 | |||
173 | rv = usb_add_hcd(hcd, irq, 0); | ||
174 | if (rv) | ||
175 | goto err_ehci; | ||
176 | |||
177 | return 0; | ||
178 | |||
179 | err_ehci: | ||
180 | iounmap(hcd->regs); | ||
181 | err_ioremap: | ||
182 | irq_dispose_mapping(irq); | ||
183 | err_irq: | ||
184 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
185 | err_rmr: | ||
186 | usb_put_hcd(hcd); | ||
187 | |||
188 | return rv; | ||
189 | } | ||
190 | |||
191 | |||
192 | static int ehci_hcd_grlib_remove(struct platform_device *op) | ||
193 | { | ||
194 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); | ||
195 | |||
196 | dev_set_drvdata(&op->dev, NULL); | ||
197 | |||
198 | dev_dbg(&op->dev, "stopping GRLIB GRUSBHC EHCI USB Controller\n"); | ||
199 | |||
200 | usb_remove_hcd(hcd); | ||
201 | |||
202 | iounmap(hcd->regs); | ||
203 | irq_dispose_mapping(hcd->irq); | ||
204 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
205 | |||
206 | usb_put_hcd(hcd); | ||
207 | |||
208 | return 0; | ||
209 | } | ||
210 | |||
211 | |||
212 | static void ehci_hcd_grlib_shutdown(struct platform_device *op) | ||
213 | { | ||
214 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); | ||
215 | |||
216 | if (hcd->driver->shutdown) | ||
217 | hcd->driver->shutdown(hcd); | ||
218 | } | ||
219 | |||
220 | |||
221 | static const struct of_device_id ehci_hcd_grlib_of_match[] = { | ||
222 | { | ||
223 | .name = "GAISLER_EHCI", | ||
224 | }, | ||
225 | { | ||
226 | .name = "01_026", | ||
227 | }, | ||
228 | {}, | ||
229 | }; | ||
230 | MODULE_DEVICE_TABLE(of, ehci_hcd_grlib_of_match); | ||
231 | |||
232 | |||
233 | static struct platform_driver ehci_grlib_driver = { | ||
234 | .probe = ehci_hcd_grlib_probe, | ||
235 | .remove = ehci_hcd_grlib_remove, | ||
236 | .shutdown = ehci_hcd_grlib_shutdown, | ||
237 | .driver = { | ||
238 | .name = "grlib-ehci", | ||
239 | .owner = THIS_MODULE, | ||
240 | .of_match_table = ehci_hcd_grlib_of_match, | ||
241 | }, | ||
242 | }; | ||
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 34a928d3b7d2..f8030ee928e8 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c | |||
@@ -1,4 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * Enhanced Host Controller Interface (EHCI) driver for USB. | ||
3 | * | ||
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | ||
5 | * | ||
2 | * Copyright (c) 2000-2004 by David Brownell | 6 | * Copyright (c) 2000-2004 by David Brownell |
3 | * | 7 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
@@ -118,6 +122,7 @@ MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); | |||
118 | 122 | ||
119 | #include "ehci.h" | 123 | #include "ehci.h" |
120 | #include "ehci-dbg.c" | 124 | #include "ehci-dbg.c" |
125 | #include "pci-quirks.h" | ||
121 | 126 | ||
122 | /*-------------------------------------------------------------------------*/ | 127 | /*-------------------------------------------------------------------------*/ |
123 | 128 | ||
@@ -194,6 +199,17 @@ static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, | |||
194 | return -ETIMEDOUT; | 199 | return -ETIMEDOUT; |
195 | } | 200 | } |
196 | 201 | ||
202 | /* check TDI/ARC silicon is in host mode */ | ||
203 | static int tdi_in_host_mode (struct ehci_hcd *ehci) | ||
204 | { | ||
205 | u32 __iomem *reg_ptr; | ||
206 | u32 tmp; | ||
207 | |||
208 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); | ||
209 | tmp = ehci_readl(ehci, reg_ptr); | ||
210 | return (tmp & 3) == USBMODE_CM_HC; | ||
211 | } | ||
212 | |||
197 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ | 213 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
198 | static int ehci_halt (struct ehci_hcd *ehci) | 214 | static int ehci_halt (struct ehci_hcd *ehci) |
199 | { | 215 | { |
@@ -202,6 +218,10 @@ static int ehci_halt (struct ehci_hcd *ehci) | |||
202 | /* disable any irqs left enabled by previous code */ | 218 | /* disable any irqs left enabled by previous code */ |
203 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | 219 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
204 | 220 | ||
221 | if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { | ||
222 | return 0; | ||
223 | } | ||
224 | |||
205 | if ((temp & STS_HALT) != 0) | 225 | if ((temp & STS_HALT) != 0) |
206 | return 0; | 226 | return 0; |
207 | 227 | ||
@@ -514,6 +534,9 @@ static void ehci_stop (struct usb_hcd *hcd) | |||
514 | spin_unlock_irq (&ehci->lock); | 534 | spin_unlock_irq (&ehci->lock); |
515 | ehci_mem_cleanup (ehci); | 535 | ehci_mem_cleanup (ehci); |
516 | 536 | ||
537 | if (ehci->amd_pll_fix == 1) | ||
538 | usb_amd_dev_put(); | ||
539 | |||
517 | #ifdef EHCI_STATS | 540 | #ifdef EHCI_STATS |
518 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | 541 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", |
519 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | 542 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, |
@@ -549,6 +572,8 @@ static int ehci_init(struct usb_hcd *hcd) | |||
549 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | 572 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; |
550 | ehci->iaa_watchdog.data = (unsigned long) ehci; | 573 | ehci->iaa_watchdog.data = (unsigned long) ehci; |
551 | 574 | ||
575 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); | ||
576 | |||
552 | /* | 577 | /* |
553 | * hw default: 1K periodic list heads, one per frame. | 578 | * hw default: 1K periodic list heads, one per frame. |
554 | * periodic_size can shrink by USBCMD update if hcc_params allows. | 579 | * periodic_size can shrink by USBCMD update if hcc_params allows. |
@@ -556,11 +581,20 @@ static int ehci_init(struct usb_hcd *hcd) | |||
556 | ehci->periodic_size = DEFAULT_I_TDPS; | 581 | ehci->periodic_size = DEFAULT_I_TDPS; |
557 | INIT_LIST_HEAD(&ehci->cached_itd_list); | 582 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
558 | INIT_LIST_HEAD(&ehci->cached_sitd_list); | 583 | INIT_LIST_HEAD(&ehci->cached_sitd_list); |
584 | |||
585 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { | ||
586 | /* periodic schedule size can be smaller than default */ | ||
587 | switch (EHCI_TUNE_FLS) { | ||
588 | case 0: ehci->periodic_size = 1024; break; | ||
589 | case 1: ehci->periodic_size = 512; break; | ||
590 | case 2: ehci->periodic_size = 256; break; | ||
591 | default: BUG(); | ||
592 | } | ||
593 | } | ||
559 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) | 594 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
560 | return retval; | 595 | return retval; |
561 | 596 | ||
562 | /* controllers may cache some of the periodic schedule ... */ | 597 | /* controllers may cache some of the periodic schedule ... */ |
563 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); | ||
564 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache | 598 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
565 | ehci->i_thresh = 2 + 8; | 599 | ehci->i_thresh = 2 + 8; |
566 | else // N microframes cached | 600 | else // N microframes cached |
@@ -614,12 +648,6 @@ static int ehci_init(struct usb_hcd *hcd) | |||
614 | /* periodic schedule size can be smaller than default */ | 648 | /* periodic schedule size can be smaller than default */ |
615 | temp &= ~(3 << 2); | 649 | temp &= ~(3 << 2); |
616 | temp |= (EHCI_TUNE_FLS << 2); | 650 | temp |= (EHCI_TUNE_FLS << 2); |
617 | switch (EHCI_TUNE_FLS) { | ||
618 | case 0: ehci->periodic_size = 1024; break; | ||
619 | case 1: ehci->periodic_size = 512; break; | ||
620 | case 2: ehci->periodic_size = 256; break; | ||
621 | default: BUG(); | ||
622 | } | ||
623 | } | 651 | } |
624 | if (HCC_LPM(hcc_params)) { | 652 | if (HCC_LPM(hcc_params)) { |
625 | /* support link power management EHCI 1.1 addendum */ | 653 | /* support link power management EHCI 1.1 addendum */ |
@@ -651,7 +679,12 @@ static int ehci_run (struct usb_hcd *hcd) | |||
651 | hcd->uses_new_polling = 1; | 679 | hcd->uses_new_polling = 1; |
652 | 680 | ||
653 | /* EHCI spec section 4.1 */ | 681 | /* EHCI spec section 4.1 */ |
654 | if ((retval = ehci_reset(ehci)) != 0) { | 682 | /* |
683 | * TDI driver does the ehci_reset in their reset callback. | ||
684 | * Don't reset here, because configuration settings will | ||
685 | * vanish. | ||
686 | */ | ||
687 | if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) { | ||
655 | ehci_mem_cleanup(ehci); | 688 | ehci_mem_cleanup(ehci); |
656 | return retval; | 689 | return retval; |
657 | } | 690 | } |
@@ -710,7 +743,7 @@ static int ehci_run (struct usb_hcd *hcd) | |||
710 | up_write(&ehci_cf_port_reset_rwsem); | 743 | up_write(&ehci_cf_port_reset_rwsem); |
711 | ehci->last_periodic_enable = ktime_get_real(); | 744 | ehci->last_periodic_enable = ktime_get_real(); |
712 | 745 | ||
713 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 746 | temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
714 | ehci_info (ehci, | 747 | ehci_info (ehci, |
715 | "USB %x.%x started, EHCI %x.%02x%s\n", | 748 | "USB %x.%x started, EHCI %x.%02x%s\n", |
716 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), | 749 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
@@ -748,8 +781,9 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) | |||
748 | goto dead; | 781 | goto dead; |
749 | } | 782 | } |
750 | 783 | ||
784 | /* Shared IRQ? */ | ||
751 | masked_status = status & INTR_MASK; | 785 | masked_status = status & INTR_MASK; |
752 | if (!masked_status) { /* irq sharing? */ | 786 | if (!masked_status || unlikely(hcd->state == HC_STATE_HALT)) { |
753 | spin_unlock(&ehci->lock); | 787 | spin_unlock(&ehci->lock); |
754 | return IRQ_NONE; | 788 | return IRQ_NONE; |
755 | } | 789 | } |
@@ -844,6 +878,7 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) | |||
844 | dead: | 878 | dead: |
845 | ehci_reset(ehci); | 879 | ehci_reset(ehci); |
846 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); | 880 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
881 | usb_hc_died(hcd); | ||
847 | /* generic layer kills/unlinks all urbs, then | 882 | /* generic layer kills/unlinks all urbs, then |
848 | * uses ehci_stop to clean up the rest | 883 | * uses ehci_stop to clean up the rest |
849 | */ | 884 | */ |
@@ -1048,10 +1083,11 @@ rescan: | |||
1048 | tmp && tmp != qh; | 1083 | tmp && tmp != qh; |
1049 | tmp = tmp->qh_next.qh) | 1084 | tmp = tmp->qh_next.qh) |
1050 | continue; | 1085 | continue; |
1051 | /* periodic qh self-unlinks on empty */ | 1086 | /* periodic qh self-unlinks on empty, and a COMPLETING qh |
1052 | if (!tmp) | 1087 | * may already be unlinked. |
1053 | goto nogood; | 1088 | */ |
1054 | unlink_async (ehci, qh); | 1089 | if (tmp) |
1090 | unlink_async(ehci, qh); | ||
1055 | /* FALL THROUGH */ | 1091 | /* FALL THROUGH */ |
1056 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | 1092 | case QH_STATE_UNLINK: /* wait for hw to finish? */ |
1057 | case QH_STATE_UNLINK_WAIT: | 1093 | case QH_STATE_UNLINK_WAIT: |
@@ -1068,7 +1104,6 @@ idle_timeout: | |||
1068 | } | 1104 | } |
1069 | /* else FALL THROUGH */ | 1105 | /* else FALL THROUGH */ |
1070 | default: | 1106 | default: |
1071 | nogood: | ||
1072 | /* caller was supposed to have unlinked any requests; | 1107 | /* caller was supposed to have unlinked any requests; |
1073 | * that's not our job. just leak this memory. | 1108 | * that's not our job. just leak this memory. |
1074 | */ | 1109 | */ |
@@ -1080,7 +1115,6 @@ nogood: | |||
1080 | ep->hcpriv = NULL; | 1115 | ep->hcpriv = NULL; |
1081 | done: | 1116 | done: |
1082 | spin_unlock_irqrestore (&ehci->lock, flags); | 1117 | spin_unlock_irqrestore (&ehci->lock, flags); |
1083 | return; | ||
1084 | } | 1118 | } |
1085 | 1119 | ||
1086 | static void | 1120 | static void |
@@ -1152,12 +1186,17 @@ MODULE_LICENSE ("GPL"); | |||
1152 | #define PLATFORM_DRIVER ehci_mxc_driver | 1186 | #define PLATFORM_DRIVER ehci_mxc_driver |
1153 | #endif | 1187 | #endif |
1154 | 1188 | ||
1189 | #ifdef CONFIG_USB_EHCI_SH | ||
1190 | #include "ehci-sh.c" | ||
1191 | #define PLATFORM_DRIVER ehci_hcd_sh_driver | ||
1192 | #endif | ||
1193 | |||
1155 | #ifdef CONFIG_SOC_AU1200 | 1194 | #ifdef CONFIG_SOC_AU1200 |
1156 | #include "ehci-au1xxx.c" | 1195 | #include "ehci-au1xxx.c" |
1157 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver | 1196 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
1158 | #endif | 1197 | #endif |
1159 | 1198 | ||
1160 | #ifdef CONFIG_ARCH_OMAP3 | 1199 | #ifdef CONFIG_USB_EHCI_HCD_OMAP |
1161 | #include "ehci-omap.c" | 1200 | #include "ehci-omap.c" |
1162 | #define PLATFORM_DRIVER ehci_hcd_omap_driver | 1201 | #define PLATFORM_DRIVER ehci_hcd_omap_driver |
1163 | #endif | 1202 | #endif |
@@ -1197,6 +1236,56 @@ MODULE_LICENSE ("GPL"); | |||
1197 | #define PLATFORM_DRIVER ehci_atmel_driver | 1236 | #define PLATFORM_DRIVER ehci_atmel_driver |
1198 | #endif | 1237 | #endif |
1199 | 1238 | ||
1239 | #ifdef CONFIG_USB_OCTEON_EHCI | ||
1240 | #include "ehci-octeon.c" | ||
1241 | #define PLATFORM_DRIVER ehci_octeon_driver | ||
1242 | #endif | ||
1243 | |||
1244 | #ifdef CONFIG_USB_CNS3XXX_EHCI | ||
1245 | #include "ehci-cns3xxx.c" | ||
1246 | #define PLATFORM_DRIVER cns3xxx_ehci_driver | ||
1247 | #endif | ||
1248 | |||
1249 | #ifdef CONFIG_ARCH_VT8500 | ||
1250 | #include "ehci-vt8500.c" | ||
1251 | #define PLATFORM_DRIVER vt8500_ehci_driver | ||
1252 | #endif | ||
1253 | |||
1254 | #ifdef CONFIG_PLAT_SPEAR | ||
1255 | #include "ehci-spear.c" | ||
1256 | #define PLATFORM_DRIVER spear_ehci_hcd_driver | ||
1257 | #endif | ||
1258 | |||
1259 | #ifdef CONFIG_USB_EHCI_MSM | ||
1260 | #include "ehci-msm.c" | ||
1261 | #define PLATFORM_DRIVER ehci_msm_driver | ||
1262 | #endif | ||
1263 | |||
1264 | #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP | ||
1265 | #include "ehci-pmcmsp.c" | ||
1266 | #define PLATFORM_DRIVER ehci_hcd_msp_driver | ||
1267 | #endif | ||
1268 | |||
1269 | #ifdef CONFIG_USB_EHCI_TEGRA | ||
1270 | #include "ehci-tegra.c" | ||
1271 | #define PLATFORM_DRIVER tegra_ehci_driver | ||
1272 | #endif | ||
1273 | |||
1274 | #ifdef CONFIG_USB_EHCI_S5P | ||
1275 | #include "ehci-s5p.c" | ||
1276 | #define PLATFORM_DRIVER s5p_ehci_driver | ||
1277 | #endif | ||
1278 | |||
1279 | #ifdef CONFIG_USB_EHCI_ATH79 | ||
1280 | #include "ehci-ath79.c" | ||
1281 | #define PLATFORM_DRIVER ehci_ath79_driver | ||
1282 | #endif | ||
1283 | |||
1284 | #ifdef CONFIG_SPARC_LEON | ||
1285 | #include "ehci-grlib.c" | ||
1286 | #define PLATFORM_DRIVER ehci_grlib_driver | ||
1287 | #endif | ||
1288 | |||
1200 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ | 1289 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
1201 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ | 1290 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ |
1202 | !defined(XILINX_OF_PLATFORM_DRIVER) | 1291 | !defined(XILINX_OF_PLATFORM_DRIVER) |
@@ -1249,24 +1338,24 @@ static int __init ehci_hcd_init(void) | |||
1249 | #endif | 1338 | #endif |
1250 | 1339 | ||
1251 | #ifdef OF_PLATFORM_DRIVER | 1340 | #ifdef OF_PLATFORM_DRIVER |
1252 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | 1341 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
1253 | if (retval < 0) | 1342 | if (retval < 0) |
1254 | goto clean3; | 1343 | goto clean3; |
1255 | #endif | 1344 | #endif |
1256 | 1345 | ||
1257 | #ifdef XILINX_OF_PLATFORM_DRIVER | 1346 | #ifdef XILINX_OF_PLATFORM_DRIVER |
1258 | retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); | 1347 | retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); |
1259 | if (retval < 0) | 1348 | if (retval < 0) |
1260 | goto clean4; | 1349 | goto clean4; |
1261 | #endif | 1350 | #endif |
1262 | return retval; | 1351 | return retval; |
1263 | 1352 | ||
1264 | #ifdef XILINX_OF_PLATFORM_DRIVER | 1353 | #ifdef XILINX_OF_PLATFORM_DRIVER |
1265 | /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ | 1354 | /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ |
1266 | clean4: | 1355 | clean4: |
1267 | #endif | 1356 | #endif |
1268 | #ifdef OF_PLATFORM_DRIVER | 1357 | #ifdef OF_PLATFORM_DRIVER |
1269 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | 1358 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
1270 | clean3: | 1359 | clean3: |
1271 | #endif | 1360 | #endif |
1272 | #ifdef PS3_SYSTEM_BUS_DRIVER | 1361 | #ifdef PS3_SYSTEM_BUS_DRIVER |
@@ -1294,10 +1383,10 @@ module_init(ehci_hcd_init); | |||
1294 | static void __exit ehci_hcd_cleanup(void) | 1383 | static void __exit ehci_hcd_cleanup(void) |
1295 | { | 1384 | { |
1296 | #ifdef XILINX_OF_PLATFORM_DRIVER | 1385 | #ifdef XILINX_OF_PLATFORM_DRIVER |
1297 | of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); | 1386 | platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); |
1298 | #endif | 1387 | #endif |
1299 | #ifdef OF_PLATFORM_DRIVER | 1388 | #ifdef OF_PLATFORM_DRIVER |
1300 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | 1389 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
1301 | #endif | 1390 | #endif |
1302 | #ifdef PLATFORM_DRIVER | 1391 | #ifdef PLATFORM_DRIVER |
1303 | platform_driver_unregister(&PLATFORM_DRIVER); | 1392 | platform_driver_unregister(&PLATFORM_DRIVER); |
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c index 796ea0c8900f..ea6184bf48d0 100644 --- a/drivers/usb/host/ehci-hub.c +++ b/drivers/usb/host/ehci-hub.c | |||
@@ -27,6 +27,7 @@ | |||
27 | */ | 27 | */ |
28 | 28 | ||
29 | /*-------------------------------------------------------------------------*/ | 29 | /*-------------------------------------------------------------------------*/ |
30 | #include <linux/usb/otg.h> | ||
30 | 31 | ||
31 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | 32 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
32 | 33 | ||
@@ -106,11 +107,33 @@ static void ehci_handover_companion_ports(struct ehci_hcd *ehci) | |||
106 | ehci->owned_ports = 0; | 107 | ehci->owned_ports = 0; |
107 | } | 108 | } |
108 | 109 | ||
109 | static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, | 110 | static int ehci_port_change(struct ehci_hcd *ehci) |
111 | { | ||
112 | int i = HCS_N_PORTS(ehci->hcs_params); | ||
113 | |||
114 | /* First check if the controller indicates a change event */ | ||
115 | |||
116 | if (ehci_readl(ehci, &ehci->regs->status) & STS_PCD) | ||
117 | return 1; | ||
118 | |||
119 | /* | ||
120 | * Not all controllers appear to update this while going from D3 to D0, | ||
121 | * so check the individual port status registers as well | ||
122 | */ | ||
123 | |||
124 | while (i--) | ||
125 | if (ehci_readl(ehci, &ehci->regs->port_status[i]) & PORT_CSC) | ||
126 | return 1; | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static __maybe_unused void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, | ||
110 | bool suspending, bool do_wakeup) | 132 | bool suspending, bool do_wakeup) |
111 | { | 133 | { |
112 | int port; | 134 | int port; |
113 | u32 temp; | 135 | u32 temp; |
136 | unsigned long flags; | ||
114 | 137 | ||
115 | /* If remote wakeup is enabled for the root hub but disabled | 138 | /* If remote wakeup is enabled for the root hub but disabled |
116 | * for the controller, we must adjust all the port wakeup flags | 139 | * for the controller, we must adjust all the port wakeup flags |
@@ -120,6 +143,8 @@ static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, | |||
120 | if (!ehci_to_hcd(ehci)->self.root_hub->do_remote_wakeup || do_wakeup) | 143 | if (!ehci_to_hcd(ehci)->self.root_hub->do_remote_wakeup || do_wakeup) |
121 | return; | 144 | return; |
122 | 145 | ||
146 | spin_lock_irqsave(&ehci->lock, flags); | ||
147 | |||
123 | /* clear phy low-power mode before changing wakeup flags */ | 148 | /* clear phy low-power mode before changing wakeup flags */ |
124 | if (ehci->has_hostpc) { | 149 | if (ehci->has_hostpc) { |
125 | port = HCS_N_PORTS(ehci->hcs_params); | 150 | port = HCS_N_PORTS(ehci->hcs_params); |
@@ -131,7 +156,9 @@ static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, | |||
131 | temp = ehci_readl(ehci, hostpc_reg); | 156 | temp = ehci_readl(ehci, hostpc_reg); |
132 | ehci_writel(ehci, temp & ~HOSTPC_PHCD, hostpc_reg); | 157 | ehci_writel(ehci, temp & ~HOSTPC_PHCD, hostpc_reg); |
133 | } | 158 | } |
159 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
134 | msleep(5); | 160 | msleep(5); |
161 | spin_lock_irqsave(&ehci->lock, flags); | ||
135 | } | 162 | } |
136 | 163 | ||
137 | port = HCS_N_PORTS(ehci->hcs_params); | 164 | port = HCS_N_PORTS(ehci->hcs_params); |
@@ -168,8 +195,10 @@ static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, | |||
168 | } | 195 | } |
169 | 196 | ||
170 | /* Does the root hub have a port wakeup pending? */ | 197 | /* Does the root hub have a port wakeup pending? */ |
171 | if (!suspending && (ehci_readl(ehci, &ehci->regs->status) & STS_PCD)) | 198 | if (!suspending && ehci_port_change(ehci)) |
172 | usb_hcd_resume_root_hub(ehci_to_hcd(ehci)); | 199 | usb_hcd_resume_root_hub(ehci_to_hcd(ehci)); |
200 | |||
201 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
173 | } | 202 | } |
174 | 203 | ||
175 | static int ehci_bus_suspend (struct usb_hcd *hcd) | 204 | static int ehci_bus_suspend (struct usb_hcd *hcd) |
@@ -531,14 +560,15 @@ static ssize_t store_companion(struct device *dev, | |||
531 | } | 560 | } |
532 | static DEVICE_ATTR(companion, 0644, show_companion, store_companion); | 561 | static DEVICE_ATTR(companion, 0644, show_companion, store_companion); |
533 | 562 | ||
534 | static inline void create_companion_file(struct ehci_hcd *ehci) | 563 | static inline int create_companion_file(struct ehci_hcd *ehci) |
535 | { | 564 | { |
536 | int i; | 565 | int i = 0; |
537 | 566 | ||
538 | /* with integrated TT there is no companion! */ | 567 | /* with integrated TT there is no companion! */ |
539 | if (!ehci_is_TDI(ehci)) | 568 | if (!ehci_is_TDI(ehci)) |
540 | i = device_create_file(ehci_to_hcd(ehci)->self.controller, | 569 | i = device_create_file(ehci_to_hcd(ehci)->self.controller, |
541 | &dev_attr_companion); | 570 | &dev_attr_companion); |
571 | return i; | ||
542 | } | 572 | } |
543 | 573 | ||
544 | static inline void remove_companion_file(struct ehci_hcd *ehci) | 574 | static inline void remove_companion_file(struct ehci_hcd *ehci) |
@@ -688,8 +718,8 @@ ehci_hub_descriptor ( | |||
688 | desc->bDescLength = 7 + 2 * temp; | 718 | desc->bDescLength = 7 + 2 * temp; |
689 | 719 | ||
690 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 720 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
691 | memset (&desc->bitmap [0], 0, temp); | 721 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
692 | memset (&desc->bitmap [temp], 0xff, temp); | 722 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
693 | 723 | ||
694 | temp = 0x0008; /* per-port overcurrent reporting */ | 724 | temp = 0x0008; /* per-port overcurrent reporting */ |
695 | if (HCS_PPC (ehci->hcs_params)) | 725 | if (HCS_PPC (ehci->hcs_params)) |
@@ -772,6 +802,13 @@ static int ehci_hub_control ( | |||
772 | goto error; | 802 | goto error; |
773 | if (ehci->no_selective_suspend) | 803 | if (ehci->no_selective_suspend) |
774 | break; | 804 | break; |
805 | #ifdef CONFIG_USB_OTG | ||
806 | if ((hcd->self.otg_port == (wIndex + 1)) | ||
807 | && hcd->self.b_hnp_enable) { | ||
808 | otg_start_hnp(ehci->transceiver); | ||
809 | break; | ||
810 | } | ||
811 | #endif | ||
775 | if (!(temp & PORT_SUSPEND)) | 812 | if (!(temp & PORT_SUSPEND)) |
776 | break; | 813 | break; |
777 | if ((temp & PORT_PE) == 0) | 814 | if ((temp & PORT_PE) == 0) |
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c index 89b7c70c6ed6..50e600d26e28 100644 --- a/drivers/usb/host/ehci-ixp4xx.c +++ b/drivers/usb/host/ehci-ixp4xx.c | |||
@@ -23,7 +23,7 @@ static int ixp4xx_ehci_init(struct usb_hcd *hcd) | |||
23 | 23 | ||
24 | ehci->caps = hcd->regs + 0x100; | 24 | ehci->caps = hcd->regs + 0x100; |
25 | ehci->regs = hcd->regs + 0x100 | 25 | ehci->regs = hcd->regs + 0x100 |
26 | + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 26 | + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
27 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | 27 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
28 | 28 | ||
29 | hcd->has_tt = 1; | 29 | hcd->has_tt = 1; |
diff --git a/drivers/usb/host/ehci-lpm.c b/drivers/usb/host/ehci-lpm.c index b4d4d63c13ed..2111627a19de 100644 --- a/drivers/usb/host/ehci-lpm.c +++ b/drivers/usb/host/ehci-lpm.c | |||
@@ -17,7 +17,8 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | /* this file is part of ehci-hcd.c */ | 19 | /* this file is part of ehci-hcd.c */ |
20 | static int ehci_lpm_set_da(struct ehci_hcd *ehci, int dev_addr, int port_num) | 20 | static int __maybe_unused ehci_lpm_set_da(struct ehci_hcd *ehci, |
21 | int dev_addr, int port_num) | ||
21 | { | 22 | { |
22 | u32 __iomem portsc; | 23 | u32 __iomem portsc; |
23 | 24 | ||
@@ -37,7 +38,7 @@ static int ehci_lpm_set_da(struct ehci_hcd *ehci, int dev_addr, int port_num) | |||
37 | * this function is used to check if the device support LPM | 38 | * this function is used to check if the device support LPM |
38 | * if yes, mark the PORTSC register with PORT_LPM bit | 39 | * if yes, mark the PORTSC register with PORT_LPM bit |
39 | */ | 40 | */ |
40 | static int ehci_lpm_check(struct ehci_hcd *ehci, int port) | 41 | static int __maybe_unused ehci_lpm_check(struct ehci_hcd *ehci, int port) |
41 | { | 42 | { |
42 | u32 __iomem *portsc ; | 43 | u32 __iomem *portsc ; |
43 | u32 val32; | 44 | u32 val32; |
diff --git a/drivers/usb/host/ehci-mem.c b/drivers/usb/host/ehci-mem.c index 1f3f01eacaf0..12f70c302b0b 100644 --- a/drivers/usb/host/ehci-mem.c +++ b/drivers/usb/host/ehci-mem.c | |||
@@ -40,7 +40,7 @@ static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd, | |||
40 | { | 40 | { |
41 | memset (qtd, 0, sizeof *qtd); | 41 | memset (qtd, 0, sizeof *qtd); |
42 | qtd->qtd_dma = dma; | 42 | qtd->qtd_dma = dma; |
43 | qtd->hw_token = cpu_to_le32 (QTD_STS_HALT); | 43 | qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); |
44 | qtd->hw_next = EHCI_LIST_END(ehci); | 44 | qtd->hw_next = EHCI_LIST_END(ehci); |
45 | qtd->hw_alt_next = EHCI_LIST_END(ehci); | 45 | qtd->hw_alt_next = EHCI_LIST_END(ehci); |
46 | INIT_LIST_HEAD (&qtd->qtd_list); | 46 | INIT_LIST_HEAD (&qtd->qtd_list); |
@@ -141,6 +141,10 @@ static void ehci_mem_cleanup (struct ehci_hcd *ehci) | |||
141 | qh_put (ehci->async); | 141 | qh_put (ehci->async); |
142 | ehci->async = NULL; | 142 | ehci->async = NULL; |
143 | 143 | ||
144 | if (ehci->dummy) | ||
145 | qh_put(ehci->dummy); | ||
146 | ehci->dummy = NULL; | ||
147 | |||
144 | /* DMA consistent memory and pools */ | 148 | /* DMA consistent memory and pools */ |
145 | if (ehci->qtd_pool) | 149 | if (ehci->qtd_pool) |
146 | dma_pool_destroy (ehci->qtd_pool); | 150 | dma_pool_destroy (ehci->qtd_pool); |
@@ -227,8 +231,26 @@ static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) | |||
227 | if (ehci->periodic == NULL) { | 231 | if (ehci->periodic == NULL) { |
228 | goto fail; | 232 | goto fail; |
229 | } | 233 | } |
230 | for (i = 0; i < ehci->periodic_size; i++) | 234 | |
231 | ehci->periodic [i] = EHCI_LIST_END(ehci); | 235 | if (ehci->use_dummy_qh) { |
236 | struct ehci_qh_hw *hw; | ||
237 | ehci->dummy = ehci_qh_alloc(ehci, flags); | ||
238 | if (!ehci->dummy) | ||
239 | goto fail; | ||
240 | |||
241 | hw = ehci->dummy->hw; | ||
242 | hw->hw_next = EHCI_LIST_END(ehci); | ||
243 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | ||
244 | hw->hw_alt_next = EHCI_LIST_END(ehci); | ||
245 | hw->hw_token &= ~QTD_STS_ACTIVE; | ||
246 | ehci->dummy->hw = hw; | ||
247 | |||
248 | for (i = 0; i < ehci->periodic_size; i++) | ||
249 | ehci->periodic[i] = ehci->dummy->qh_dma; | ||
250 | } else { | ||
251 | for (i = 0; i < ehci->periodic_size; i++) | ||
252 | ehci->periodic[i] = EHCI_LIST_END(ehci); | ||
253 | } | ||
232 | 254 | ||
233 | /* software shadow of hardware table */ | 255 | /* software shadow of hardware table */ |
234 | ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags); | 256 | ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags); |
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c new file mode 100644 index 000000000000..b5a0bf649c95 --- /dev/null +++ b/drivers/usb/host/ehci-msm.c | |||
@@ -0,0 +1,265 @@ | |||
1 | /* ehci-msm.c - HSUSB Host Controller Driver Implementation | ||
2 | * | ||
3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. | ||
4 | * | ||
5 | * Partly derived from ehci-fsl.c and ehci-hcd.c | ||
6 | * Copyright (c) 2000-2004 by David Brownell | ||
7 | * Copyright (c) 2005 MontaVista Software | ||
8 | * | ||
9 | * All source code in this file is licensed under the following license except | ||
10 | * where indicated. | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify it | ||
13 | * under the terms of the GNU General Public License version 2 as published | ||
14 | * by the Free Software Foundation. | ||
15 | * | ||
16 | * This program is distributed in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
19 | * | ||
20 | * See the GNU General Public License for more details. | ||
21 | * You should have received a copy of the GNU General Public License | ||
22 | * along with this program; if not, you can find it at http://www.fsf.org | ||
23 | */ | ||
24 | |||
25 | #include <linux/platform_device.h> | ||
26 | #include <linux/clk.h> | ||
27 | #include <linux/err.h> | ||
28 | #include <linux/pm_runtime.h> | ||
29 | |||
30 | #include <linux/usb/otg.h> | ||
31 | #include <linux/usb/msm_hsusb_hw.h> | ||
32 | |||
33 | #define MSM_USB_BASE (hcd->regs) | ||
34 | |||
35 | static struct otg_transceiver *otg; | ||
36 | |||
37 | static int ehci_msm_reset(struct usb_hcd *hcd) | ||
38 | { | ||
39 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
40 | int retval; | ||
41 | |||
42 | ehci->caps = USB_CAPLENGTH; | ||
43 | ehci->regs = USB_CAPLENGTH + | ||
44 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
45 | dbg_hcs_params(ehci, "reset"); | ||
46 | dbg_hcc_params(ehci, "reset"); | ||
47 | |||
48 | /* cache the data to minimize the chip reads*/ | ||
49 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
50 | |||
51 | hcd->has_tt = 1; | ||
52 | ehci->sbrn = HCD_USB2; | ||
53 | |||
54 | retval = ehci_halt(ehci); | ||
55 | if (retval) | ||
56 | return retval; | ||
57 | |||
58 | /* data structure init */ | ||
59 | retval = ehci_init(hcd); | ||
60 | if (retval) | ||
61 | return retval; | ||
62 | |||
63 | retval = ehci_reset(ehci); | ||
64 | if (retval) | ||
65 | return retval; | ||
66 | |||
67 | /* bursts of unspecified length. */ | ||
68 | writel(0, USB_AHBBURST); | ||
69 | /* Use the AHB transactor */ | ||
70 | writel(0, USB_AHBMODE); | ||
71 | /* Disable streaming mode and select host mode */ | ||
72 | writel(0x13, USB_USBMODE); | ||
73 | |||
74 | ehci_port_power(ehci, 1); | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | static struct hc_driver msm_hc_driver = { | ||
79 | .description = hcd_name, | ||
80 | .product_desc = "Qualcomm On-Chip EHCI Host Controller", | ||
81 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
82 | |||
83 | /* | ||
84 | * generic hardware linkage | ||
85 | */ | ||
86 | .irq = ehci_irq, | ||
87 | .flags = HCD_USB2 | HCD_MEMORY, | ||
88 | |||
89 | .reset = ehci_msm_reset, | ||
90 | .start = ehci_run, | ||
91 | |||
92 | .stop = ehci_stop, | ||
93 | .shutdown = ehci_shutdown, | ||
94 | |||
95 | /* | ||
96 | * managing i/o requests and associated device resources | ||
97 | */ | ||
98 | .urb_enqueue = ehci_urb_enqueue, | ||
99 | .urb_dequeue = ehci_urb_dequeue, | ||
100 | .endpoint_disable = ehci_endpoint_disable, | ||
101 | .endpoint_reset = ehci_endpoint_reset, | ||
102 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
103 | |||
104 | /* | ||
105 | * scheduling support | ||
106 | */ | ||
107 | .get_frame_number = ehci_get_frame, | ||
108 | |||
109 | /* | ||
110 | * root hub support | ||
111 | */ | ||
112 | .hub_status_data = ehci_hub_status_data, | ||
113 | .hub_control = ehci_hub_control, | ||
114 | .relinquish_port = ehci_relinquish_port, | ||
115 | .port_handed_over = ehci_port_handed_over, | ||
116 | |||
117 | /* | ||
118 | * PM support | ||
119 | */ | ||
120 | .bus_suspend = ehci_bus_suspend, | ||
121 | .bus_resume = ehci_bus_resume, | ||
122 | }; | ||
123 | |||
124 | static int ehci_msm_probe(struct platform_device *pdev) | ||
125 | { | ||
126 | struct usb_hcd *hcd; | ||
127 | struct resource *res; | ||
128 | int ret; | ||
129 | |||
130 | dev_dbg(&pdev->dev, "ehci_msm proble\n"); | ||
131 | |||
132 | hcd = usb_create_hcd(&msm_hc_driver, &pdev->dev, dev_name(&pdev->dev)); | ||
133 | if (!hcd) { | ||
134 | dev_err(&pdev->dev, "Unable to create HCD\n"); | ||
135 | return -ENOMEM; | ||
136 | } | ||
137 | |||
138 | hcd->irq = platform_get_irq(pdev, 0); | ||
139 | if (hcd->irq < 0) { | ||
140 | dev_err(&pdev->dev, "Unable to get IRQ resource\n"); | ||
141 | ret = hcd->irq; | ||
142 | goto put_hcd; | ||
143 | } | ||
144 | |||
145 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
146 | if (!res) { | ||
147 | dev_err(&pdev->dev, "Unable to get memory resource\n"); | ||
148 | ret = -ENODEV; | ||
149 | goto put_hcd; | ||
150 | } | ||
151 | |||
152 | hcd->rsrc_start = res->start; | ||
153 | hcd->rsrc_len = resource_size(res); | ||
154 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
155 | if (!hcd->regs) { | ||
156 | dev_err(&pdev->dev, "ioremap failed\n"); | ||
157 | ret = -ENOMEM; | ||
158 | goto put_hcd; | ||
159 | } | ||
160 | |||
161 | /* | ||
162 | * OTG driver takes care of PHY initialization, clock management, | ||
163 | * powering up VBUS, mapping of registers address space and power | ||
164 | * management. | ||
165 | */ | ||
166 | otg = otg_get_transceiver(); | ||
167 | if (!otg) { | ||
168 | dev_err(&pdev->dev, "unable to find transceiver\n"); | ||
169 | ret = -ENODEV; | ||
170 | goto unmap; | ||
171 | } | ||
172 | |||
173 | ret = otg_set_host(otg, &hcd->self); | ||
174 | if (ret < 0) { | ||
175 | dev_err(&pdev->dev, "unable to register with transceiver\n"); | ||
176 | goto put_transceiver; | ||
177 | } | ||
178 | |||
179 | device_init_wakeup(&pdev->dev, 1); | ||
180 | /* | ||
181 | * OTG device parent of HCD takes care of putting | ||
182 | * hardware into low power mode. | ||
183 | */ | ||
184 | pm_runtime_no_callbacks(&pdev->dev); | ||
185 | pm_runtime_enable(&pdev->dev); | ||
186 | |||
187 | return 0; | ||
188 | |||
189 | put_transceiver: | ||
190 | otg_put_transceiver(otg); | ||
191 | unmap: | ||
192 | iounmap(hcd->regs); | ||
193 | put_hcd: | ||
194 | usb_put_hcd(hcd); | ||
195 | |||
196 | return ret; | ||
197 | } | ||
198 | |||
199 | static int __devexit ehci_msm_remove(struct platform_device *pdev) | ||
200 | { | ||
201 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
202 | |||
203 | device_init_wakeup(&pdev->dev, 0); | ||
204 | pm_runtime_disable(&pdev->dev); | ||
205 | pm_runtime_set_suspended(&pdev->dev); | ||
206 | |||
207 | otg_set_host(otg, NULL); | ||
208 | otg_put_transceiver(otg); | ||
209 | |||
210 | usb_put_hcd(hcd); | ||
211 | |||
212 | return 0; | ||
213 | } | ||
214 | |||
215 | #ifdef CONFIG_PM | ||
216 | static int ehci_msm_pm_suspend(struct device *dev) | ||
217 | { | ||
218 | struct usb_hcd *hcd = dev_get_drvdata(dev); | ||
219 | bool wakeup = device_may_wakeup(dev); | ||
220 | |||
221 | dev_dbg(dev, "ehci-msm PM suspend\n"); | ||
222 | |||
223 | /* | ||
224 | * EHCI helper function has also the same check before manipulating | ||
225 | * port wakeup flags. We do check here the same condition before | ||
226 | * calling the same helper function to avoid bringing hardware | ||
227 | * from Low power mode when there is no need for adjusting port | ||
228 | * wakeup flags. | ||
229 | */ | ||
230 | if (hcd->self.root_hub->do_remote_wakeup && !wakeup) { | ||
231 | pm_runtime_resume(dev); | ||
232 | ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), | ||
233 | wakeup); | ||
234 | } | ||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | |||
239 | static int ehci_msm_pm_resume(struct device *dev) | ||
240 | { | ||
241 | struct usb_hcd *hcd = dev_get_drvdata(dev); | ||
242 | |||
243 | dev_dbg(dev, "ehci-msm PM resume\n"); | ||
244 | ehci_prepare_ports_for_controller_resume(hcd_to_ehci(hcd)); | ||
245 | |||
246 | return 0; | ||
247 | } | ||
248 | #else | ||
249 | #define ehci_msm_pm_suspend NULL | ||
250 | #define ehci_msm_pm_resume NULL | ||
251 | #endif | ||
252 | |||
253 | static const struct dev_pm_ops ehci_msm_dev_pm_ops = { | ||
254 | .suspend = ehci_msm_pm_suspend, | ||
255 | .resume = ehci_msm_pm_resume, | ||
256 | }; | ||
257 | |||
258 | static struct platform_driver ehci_msm_driver = { | ||
259 | .probe = ehci_msm_probe, | ||
260 | .remove = __devexit_p(ehci_msm_remove), | ||
261 | .driver = { | ||
262 | .name = "msm_hsusb_host", | ||
263 | .pm = &ehci_msm_dev_pm_ops, | ||
264 | }, | ||
265 | }; | ||
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index a8ad8ac120a2..0c058be35a38 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c | |||
@@ -21,17 +21,17 @@ | |||
21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/usb/otg.h> | 23 | #include <linux/usb/otg.h> |
24 | #include <linux/usb/ulpi.h> | ||
24 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
25 | 26 | ||
26 | #include <mach/mxc_ehci.h> | 27 | #include <mach/mxc_ehci.h> |
27 | 28 | ||
29 | #include <asm/mach-types.h> | ||
30 | |||
28 | #define ULPI_VIEWPORT_OFFSET 0x170 | 31 | #define ULPI_VIEWPORT_OFFSET 0x170 |
29 | #define PORTSC_OFFSET 0x184 | ||
30 | #define USBMODE_OFFSET 0x1a8 | ||
31 | #define USBMODE_CM_HOST 3 | ||
32 | 32 | ||
33 | struct ehci_mxc_priv { | 33 | struct ehci_mxc_priv { |
34 | struct clk *usbclk, *ahbclk; | 34 | struct clk *usbclk, *ahbclk, *phy1clk; |
35 | struct usb_hcd *hcd; | 35 | struct usb_hcd *hcd; |
36 | }; | 36 | }; |
37 | 37 | ||
@@ -41,16 +41,14 @@ static int ehci_mxc_setup(struct usb_hcd *hcd) | |||
41 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 41 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
42 | int retval; | 42 | int retval; |
43 | 43 | ||
44 | /* EHCI registers start at offset 0x100 */ | ||
45 | ehci->caps = hcd->regs + 0x100; | ||
46 | ehci->regs = hcd->regs + 0x100 + | ||
47 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
48 | dbg_hcs_params(ehci, "reset"); | 44 | dbg_hcs_params(ehci, "reset"); |
49 | dbg_hcc_params(ehci, "reset"); | 45 | dbg_hcc_params(ehci, "reset"); |
50 | 46 | ||
51 | /* cache this readonly data; minimize chip reads */ | 47 | /* cache this readonly data; minimize chip reads */ |
52 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | 48 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
53 | 49 | ||
50 | hcd->has_tt = 1; | ||
51 | |||
54 | retval = ehci_halt(ehci); | 52 | retval = ehci_halt(ehci); |
55 | if (retval) | 53 | if (retval) |
56 | return retval; | 54 | return retval; |
@@ -60,8 +58,6 @@ static int ehci_mxc_setup(struct usb_hcd *hcd) | |||
60 | if (retval) | 58 | if (retval) |
61 | return retval; | 59 | return retval; |
62 | 60 | ||
63 | hcd->has_tt = 1; | ||
64 | |||
65 | ehci->sbrn = 0x20; | 61 | ehci->sbrn = 0x20; |
66 | 62 | ||
67 | ehci_reset(ehci); | 63 | ehci_reset(ehci); |
@@ -95,6 +91,7 @@ static const struct hc_driver ehci_mxc_hc_driver = { | |||
95 | .urb_enqueue = ehci_urb_enqueue, | 91 | .urb_enqueue = ehci_urb_enqueue, |
96 | .urb_dequeue = ehci_urb_dequeue, | 92 | .urb_dequeue = ehci_urb_dequeue, |
97 | .endpoint_disable = ehci_endpoint_disable, | 93 | .endpoint_disable = ehci_endpoint_disable, |
94 | .endpoint_reset = ehci_endpoint_reset, | ||
98 | 95 | ||
99 | /* | 96 | /* |
100 | * scheduling support | 97 | * scheduling support |
@@ -110,6 +107,8 @@ static const struct hc_driver ehci_mxc_hc_driver = { | |||
110 | .bus_resume = ehci_bus_resume, | 107 | .bus_resume = ehci_bus_resume, |
111 | .relinquish_port = ehci_relinquish_port, | 108 | .relinquish_port = ehci_relinquish_port, |
112 | .port_handed_over = ehci_port_handed_over, | 109 | .port_handed_over = ehci_port_handed_over, |
110 | |||
111 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
113 | }; | 112 | }; |
114 | 113 | ||
115 | static int ehci_mxc_drv_probe(struct platform_device *pdev) | 114 | static int ehci_mxc_drv_probe(struct platform_device *pdev) |
@@ -117,9 +116,11 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) | |||
117 | struct mxc_usbh_platform_data *pdata = pdev->dev.platform_data; | 116 | struct mxc_usbh_platform_data *pdata = pdev->dev.platform_data; |
118 | struct usb_hcd *hcd; | 117 | struct usb_hcd *hcd; |
119 | struct resource *res; | 118 | struct resource *res; |
120 | int irq, ret, temp; | 119 | int irq, ret; |
120 | unsigned int flags; | ||
121 | struct ehci_mxc_priv *priv; | 121 | struct ehci_mxc_priv *priv; |
122 | struct device *dev = &pdev->dev; | 122 | struct device *dev = &pdev->dev; |
123 | struct ehci_hcd *ehci; | ||
123 | 124 | ||
124 | dev_info(&pdev->dev, "initializing i.MX USB Controller\n"); | 125 | dev_info(&pdev->dev, "initializing i.MX USB Controller\n"); |
125 | 126 | ||
@@ -163,17 +164,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) | |||
163 | goto err_ioremap; | 164 | goto err_ioremap; |
164 | } | 165 | } |
165 | 166 | ||
166 | /* call platform specific init function */ | ||
167 | if (pdata->init) { | ||
168 | ret = pdata->init(pdev); | ||
169 | if (ret) { | ||
170 | dev_err(dev, "platform init failed\n"); | ||
171 | goto err_init; | ||
172 | } | ||
173 | /* platforms need some time to settle changed IO settings */ | ||
174 | mdelay(10); | ||
175 | } | ||
176 | |||
177 | /* enable clocks */ | 167 | /* enable clocks */ |
178 | priv->usbclk = clk_get(dev, "usb"); | 168 | priv->usbclk = clk_get(dev, "usb"); |
179 | if (IS_ERR(priv->usbclk)) { | 169 | if (IS_ERR(priv->usbclk)) { |
@@ -191,18 +181,40 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) | |||
191 | clk_enable(priv->ahbclk); | 181 | clk_enable(priv->ahbclk); |
192 | } | 182 | } |
193 | 183 | ||
194 | /* set USBMODE to host mode */ | 184 | /* "dr" device has its own clock on i.MX51 */ |
195 | temp = readl(hcd->regs + USBMODE_OFFSET); | 185 | if (cpu_is_mx51() && (pdev->id == 0)) { |
196 | writel(temp | USBMODE_CM_HOST, hcd->regs + USBMODE_OFFSET); | 186 | priv->phy1clk = clk_get(dev, "usb_phy1"); |
187 | if (IS_ERR(priv->phy1clk)) { | ||
188 | ret = PTR_ERR(priv->phy1clk); | ||
189 | goto err_clk_phy; | ||
190 | } | ||
191 | clk_enable(priv->phy1clk); | ||
192 | } | ||
193 | |||
194 | |||
195 | /* call platform specific init function */ | ||
196 | if (pdata->init) { | ||
197 | ret = pdata->init(pdev); | ||
198 | if (ret) { | ||
199 | dev_err(dev, "platform init failed\n"); | ||
200 | goto err_init; | ||
201 | } | ||
202 | /* platforms need some time to settle changed IO settings */ | ||
203 | mdelay(10); | ||
204 | } | ||
205 | |||
206 | ehci = hcd_to_ehci(hcd); | ||
207 | |||
208 | /* EHCI registers start at offset 0x100 */ | ||
209 | ehci->caps = hcd->regs + 0x100; | ||
210 | ehci->regs = hcd->regs + 0x100 + | ||
211 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
197 | 212 | ||
198 | /* set up the PORTSCx register */ | 213 | /* set up the PORTSCx register */ |
199 | writel(pdata->portsc, hcd->regs + PORTSC_OFFSET); | 214 | ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]); |
200 | mdelay(10); | ||
201 | 215 | ||
202 | /* setup specific usb hw */ | 216 | /* is this really needed? */ |
203 | ret = mxc_initialize_usb_hw(pdev->id, pdata->flags); | 217 | msleep(10); |
204 | if (ret < 0) | ||
205 | goto err_init; | ||
206 | 218 | ||
207 | /* Initialize the transceiver */ | 219 | /* Initialize the transceiver */ |
208 | if (pdata->otg) { | 220 | if (pdata->otg) { |
@@ -227,12 +239,34 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) | |||
227 | if (ret) | 239 | if (ret) |
228 | goto err_add; | 240 | goto err_add; |
229 | 241 | ||
242 | if (pdata->otg) { | ||
243 | /* | ||
244 | * efikamx and efikasb have some hardware bug which is | ||
245 | * preventing usb to work unless CHRGVBUS is set. | ||
246 | * It's in violation of USB specs | ||
247 | */ | ||
248 | if (machine_is_mx51_efikamx() || machine_is_mx51_efikasb()) { | ||
249 | flags = otg_io_read(pdata->otg, ULPI_OTG_CTRL); | ||
250 | flags |= ULPI_OTG_CTRL_CHRGVBUS; | ||
251 | ret = otg_io_write(pdata->otg, flags, ULPI_OTG_CTRL); | ||
252 | if (ret) { | ||
253 | dev_err(dev, "unable to set CHRVBUS\n"); | ||
254 | goto err_add; | ||
255 | } | ||
256 | } | ||
257 | } | ||
258 | |||
230 | return 0; | 259 | return 0; |
231 | 260 | ||
232 | err_add: | 261 | err_add: |
233 | if (pdata && pdata->exit) | 262 | if (pdata && pdata->exit) |
234 | pdata->exit(pdev); | 263 | pdata->exit(pdev); |
235 | err_init: | 264 | err_init: |
265 | if (priv->phy1clk) { | ||
266 | clk_disable(priv->phy1clk); | ||
267 | clk_put(priv->phy1clk); | ||
268 | } | ||
269 | err_clk_phy: | ||
236 | if (priv->ahbclk) { | 270 | if (priv->ahbclk) { |
237 | clk_disable(priv->ahbclk); | 271 | clk_disable(priv->ahbclk); |
238 | clk_put(priv->ahbclk); | 272 | clk_put(priv->ahbclk); |
@@ -276,6 +310,10 @@ static int __exit ehci_mxc_drv_remove(struct platform_device *pdev) | |||
276 | clk_disable(priv->ahbclk); | 310 | clk_disable(priv->ahbclk); |
277 | clk_put(priv->ahbclk); | 311 | clk_put(priv->ahbclk); |
278 | } | 312 | } |
313 | if (priv->phy1clk) { | ||
314 | clk_disable(priv->phy1clk); | ||
315 | clk_put(priv->phy1clk); | ||
316 | } | ||
279 | 317 | ||
280 | kfree(priv); | 318 | kfree(priv); |
281 | 319 | ||
diff --git a/drivers/usb/host/ehci-octeon.c b/drivers/usb/host/ehci-octeon.c new file mode 100644 index 000000000000..ff55757ba7d8 --- /dev/null +++ b/drivers/usb/host/ehci-octeon.c | |||
@@ -0,0 +1,207 @@ | |||
1 | /* | ||
2 | * EHCI HCD glue for Cavium Octeon II SOCs. | ||
3 | * | ||
4 | * Loosely based on ehci-au1xxx.c | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | * | ||
10 | * Copyright (C) 2010 Cavium Networks | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/platform_device.h> | ||
15 | |||
16 | #include <asm/octeon/octeon.h> | ||
17 | #include <asm/octeon/cvmx-uctlx-defs.h> | ||
18 | |||
19 | #define OCTEON_EHCI_HCD_NAME "octeon-ehci" | ||
20 | |||
21 | /* Common clock init code. */ | ||
22 | void octeon2_usb_clocks_start(void); | ||
23 | void octeon2_usb_clocks_stop(void); | ||
24 | |||
25 | static void ehci_octeon_start(void) | ||
26 | { | ||
27 | union cvmx_uctlx_ehci_ctl ehci_ctl; | ||
28 | |||
29 | octeon2_usb_clocks_start(); | ||
30 | |||
31 | ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); | ||
32 | /* Use 64-bit addressing. */ | ||
33 | ehci_ctl.s.ehci_64b_addr_en = 1; | ||
34 | ehci_ctl.s.l2c_addr_msb = 0; | ||
35 | ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ | ||
36 | ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ | ||
37 | cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); | ||
38 | } | ||
39 | |||
40 | static void ehci_octeon_stop(void) | ||
41 | { | ||
42 | octeon2_usb_clocks_stop(); | ||
43 | } | ||
44 | |||
45 | static const struct hc_driver ehci_octeon_hc_driver = { | ||
46 | .description = hcd_name, | ||
47 | .product_desc = "Octeon EHCI", | ||
48 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
49 | |||
50 | /* | ||
51 | * generic hardware linkage | ||
52 | */ | ||
53 | .irq = ehci_irq, | ||
54 | .flags = HCD_MEMORY | HCD_USB2, | ||
55 | |||
56 | /* | ||
57 | * basic lifecycle operations | ||
58 | */ | ||
59 | .reset = ehci_init, | ||
60 | .start = ehci_run, | ||
61 | .stop = ehci_stop, | ||
62 | .shutdown = ehci_shutdown, | ||
63 | |||
64 | /* | ||
65 | * managing i/o requests and associated device resources | ||
66 | */ | ||
67 | .urb_enqueue = ehci_urb_enqueue, | ||
68 | .urb_dequeue = ehci_urb_dequeue, | ||
69 | .endpoint_disable = ehci_endpoint_disable, | ||
70 | .endpoint_reset = ehci_endpoint_reset, | ||
71 | |||
72 | /* | ||
73 | * scheduling support | ||
74 | */ | ||
75 | .get_frame_number = ehci_get_frame, | ||
76 | |||
77 | /* | ||
78 | * root hub support | ||
79 | */ | ||
80 | .hub_status_data = ehci_hub_status_data, | ||
81 | .hub_control = ehci_hub_control, | ||
82 | .bus_suspend = ehci_bus_suspend, | ||
83 | .bus_resume = ehci_bus_resume, | ||
84 | .relinquish_port = ehci_relinquish_port, | ||
85 | .port_handed_over = ehci_port_handed_over, | ||
86 | |||
87 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
88 | }; | ||
89 | |||
90 | static u64 ehci_octeon_dma_mask = DMA_BIT_MASK(64); | ||
91 | |||
92 | static int ehci_octeon_drv_probe(struct platform_device *pdev) | ||
93 | { | ||
94 | struct usb_hcd *hcd; | ||
95 | struct ehci_hcd *ehci; | ||
96 | struct resource *res_mem; | ||
97 | int irq; | ||
98 | int ret; | ||
99 | |||
100 | if (usb_disabled()) | ||
101 | return -ENODEV; | ||
102 | |||
103 | irq = platform_get_irq(pdev, 0); | ||
104 | if (irq < 0) { | ||
105 | dev_err(&pdev->dev, "No irq assigned\n"); | ||
106 | return -ENODEV; | ||
107 | } | ||
108 | |||
109 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
110 | if (res_mem == NULL) { | ||
111 | dev_err(&pdev->dev, "No register space assigned\n"); | ||
112 | return -ENODEV; | ||
113 | } | ||
114 | |||
115 | /* | ||
116 | * We can DMA from anywhere. But the descriptors must be in | ||
117 | * the lower 4GB. | ||
118 | */ | ||
119 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | ||
120 | pdev->dev.dma_mask = &ehci_octeon_dma_mask; | ||
121 | |||
122 | hcd = usb_create_hcd(&ehci_octeon_hc_driver, &pdev->dev, "octeon"); | ||
123 | if (!hcd) | ||
124 | return -ENOMEM; | ||
125 | |||
126 | hcd->rsrc_start = res_mem->start; | ||
127 | hcd->rsrc_len = res_mem->end - res_mem->start + 1; | ||
128 | |||
129 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, | ||
130 | OCTEON_EHCI_HCD_NAME)) { | ||
131 | dev_err(&pdev->dev, "request_mem_region failed\n"); | ||
132 | ret = -EBUSY; | ||
133 | goto err1; | ||
134 | } | ||
135 | |||
136 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
137 | if (!hcd->regs) { | ||
138 | dev_err(&pdev->dev, "ioremap failed\n"); | ||
139 | ret = -ENOMEM; | ||
140 | goto err2; | ||
141 | } | ||
142 | |||
143 | ehci_octeon_start(); | ||
144 | |||
145 | ehci = hcd_to_ehci(hcd); | ||
146 | |||
147 | /* Octeon EHCI matches CPU endianness. */ | ||
148 | #ifdef __BIG_ENDIAN | ||
149 | ehci->big_endian_mmio = 1; | ||
150 | #endif | ||
151 | |||
152 | ehci->caps = hcd->regs; | ||
153 | ehci->regs = hcd->regs + | ||
154 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
155 | /* cache this readonly data; minimize chip reads */ | ||
156 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
157 | |||
158 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | ||
159 | if (ret) { | ||
160 | dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); | ||
161 | goto err3; | ||
162 | } | ||
163 | |||
164 | platform_set_drvdata(pdev, hcd); | ||
165 | |||
166 | /* root ports should always stay powered */ | ||
167 | ehci_port_power(ehci, 1); | ||
168 | |||
169 | return 0; | ||
170 | err3: | ||
171 | ehci_octeon_stop(); | ||
172 | |||
173 | iounmap(hcd->regs); | ||
174 | err2: | ||
175 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
176 | err1: | ||
177 | usb_put_hcd(hcd); | ||
178 | return ret; | ||
179 | } | ||
180 | |||
181 | static int ehci_octeon_drv_remove(struct platform_device *pdev) | ||
182 | { | ||
183 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
184 | |||
185 | usb_remove_hcd(hcd); | ||
186 | |||
187 | ehci_octeon_stop(); | ||
188 | iounmap(hcd->regs); | ||
189 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
190 | usb_put_hcd(hcd); | ||
191 | |||
192 | platform_set_drvdata(pdev, NULL); | ||
193 | |||
194 | return 0; | ||
195 | } | ||
196 | |||
197 | static struct platform_driver ehci_octeon_driver = { | ||
198 | .probe = ehci_octeon_drv_probe, | ||
199 | .remove = ehci_octeon_drv_remove, | ||
200 | .shutdown = usb_hcd_platform_shutdown, | ||
201 | .driver = { | ||
202 | .name = OCTEON_EHCI_HCD_NAME, | ||
203 | .owner = THIS_MODULE, | ||
204 | } | ||
205 | }; | ||
206 | |||
207 | MODULE_ALIAS("platform:" OCTEON_EHCI_HCD_NAME); | ||
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 116ae280053a..55a57c23dd0f 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c | |||
@@ -1,11 +1,13 @@ | |||
1 | /* | 1 | /* |
2 | * ehci-omap.c - driver for USBHOST on OMAP 34xx processor | 2 | * ehci-omap.c - driver for USBHOST on OMAP3/4 processors |
3 | * | 3 | * |
4 | * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller | 4 | * Bus Glue for the EHCI controllers in OMAP3/4 |
5 | * Tested on OMAP3430 ES2.0 SDP | 5 | * Tested on several OMAP3 boards, and OMAP4 Pandaboard |
6 | * | 6 | * |
7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
8 | * Author: Vikram Pandita <vikram.pandita@ti.com> | 8 | * Author: Vikram Pandita <vikram.pandita@ti.com> |
9 | * Author: Anand Gadiyar <gadiyar@ti.com> | ||
10 | * Author: Keshava Munegowda <keshava_mgowda@ti.com> | ||
9 | * | 11 | * |
10 | * Copyright (C) 2009 Nokia Corporation | 12 | * Copyright (C) 2009 Nokia Corporation |
11 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> | 13 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> |
@@ -26,95 +28,19 @@ | |||
26 | * along with this program; if not, write to the Free Software | 28 | * along with this program; if not, write to the Free Software |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
28 | * | 30 | * |
29 | * TODO (last updated Feb 12, 2010): | 31 | * TODO (last updated Feb 27, 2010): |
30 | * - add kernel-doc | 32 | * - add kernel-doc |
31 | * - enable AUTOIDLE | 33 | * - enable AUTOIDLE |
32 | * - add suspend/resume | 34 | * - add suspend/resume |
33 | * - move workarounds to board-files | 35 | * - add HSIC and TLL support |
36 | * - convert to use hwmod and runtime PM | ||
34 | */ | 37 | */ |
35 | 38 | ||
36 | #include <linux/platform_device.h> | 39 | #include <linux/platform_device.h> |
37 | #include <linux/clk.h> | ||
38 | #include <linux/gpio.h> | ||
39 | #include <linux/regulator/consumer.h> | ||
40 | #include <linux/slab.h> | 40 | #include <linux/slab.h> |
41 | #include <linux/usb/ulpi.h> | 41 | #include <linux/usb/ulpi.h> |
42 | #include <plat/usb.h> | 42 | #include <plat/usb.h> |
43 | 43 | #include <linux/regulator/consumer.h> | |
44 | /* | ||
45 | * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES | ||
46 | * Use ehci_omap_readl()/ehci_omap_writel() functions | ||
47 | */ | ||
48 | |||
49 | /* TLL Register Set */ | ||
50 | #define OMAP_USBTLL_REVISION (0x00) | ||
51 | #define OMAP_USBTLL_SYSCONFIG (0x10) | ||
52 | #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) | ||
53 | #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) | ||
54 | #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) | ||
55 | #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) | ||
56 | #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) | ||
57 | |||
58 | #define OMAP_USBTLL_SYSSTATUS (0x14) | ||
59 | #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) | ||
60 | |||
61 | #define OMAP_USBTLL_IRQSTATUS (0x18) | ||
62 | #define OMAP_USBTLL_IRQENABLE (0x1C) | ||
63 | |||
64 | #define OMAP_TLL_SHARED_CONF (0x30) | ||
65 | #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) | ||
66 | #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) | ||
67 | #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) | ||
68 | #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) | ||
69 | #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) | ||
70 | |||
71 | #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) | ||
72 | #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) | ||
73 | #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) | ||
74 | #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) | ||
75 | #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) | ||
76 | #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) | ||
77 | |||
78 | #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) | ||
79 | #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) | ||
80 | #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) | ||
81 | #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) | ||
82 | #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) | ||
83 | #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) | ||
84 | #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) | ||
85 | #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) | ||
86 | #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) | ||
87 | |||
88 | #define OMAP_TLL_CHANNEL_COUNT 3 | ||
89 | #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1) | ||
90 | #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2) | ||
91 | #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4) | ||
92 | |||
93 | /* UHH Register Set */ | ||
94 | #define OMAP_UHH_REVISION (0x00) | ||
95 | #define OMAP_UHH_SYSCONFIG (0x10) | ||
96 | #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) | ||
97 | #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) | ||
98 | #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) | ||
99 | #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) | ||
100 | #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) | ||
101 | #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) | ||
102 | |||
103 | #define OMAP_UHH_SYSSTATUS (0x14) | ||
104 | #define OMAP_UHH_HOSTCONFIG (0x40) | ||
105 | #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) | ||
106 | #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) | ||
107 | #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) | ||
108 | #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) | ||
109 | #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) | ||
110 | #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) | ||
111 | #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) | ||
112 | #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) | ||
113 | #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) | ||
114 | #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) | ||
115 | #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) | ||
116 | |||
117 | #define OMAP_UHH_DEBUG_CSR (0x44) | ||
118 | 44 | ||
119 | /* EHCI Register Set */ | 45 | /* EHCI Register Set */ |
120 | #define EHCI_INSNREG04 (0xA0) | 46 | #define EHCI_INSNREG04 (0xA0) |
@@ -129,116 +55,22 @@ | |||
129 | 55 | ||
130 | /*-------------------------------------------------------------------------*/ | 56 | /*-------------------------------------------------------------------------*/ |
131 | 57 | ||
132 | static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val) | 58 | static const struct hc_driver ehci_omap_hc_driver; |
133 | { | ||
134 | __raw_writel(val, base + reg); | ||
135 | } | ||
136 | 59 | ||
137 | static inline u32 ehci_omap_readl(void __iomem *base, u32 reg) | ||
138 | { | ||
139 | return __raw_readl(base + reg); | ||
140 | } | ||
141 | 60 | ||
142 | static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val) | 61 | static inline void ehci_write(void __iomem *base, u32 reg, u32 val) |
143 | { | 62 | { |
144 | __raw_writeb(val, base + reg); | 63 | __raw_writel(val, base + reg); |
145 | } | 64 | } |
146 | 65 | ||
147 | static inline u8 ehci_omap_readb(void __iomem *base, u8 reg) | 66 | static inline u32 ehci_read(void __iomem *base, u32 reg) |
148 | { | 67 | { |
149 | return __raw_readb(base + reg); | 68 | return __raw_readl(base + reg); |
150 | } | ||
151 | |||
152 | /*-------------------------------------------------------------------------*/ | ||
153 | |||
154 | struct ehci_hcd_omap { | ||
155 | struct ehci_hcd *ehci; | ||
156 | struct device *dev; | ||
157 | |||
158 | struct clk *usbhost_ick; | ||
159 | struct clk *usbhost2_120m_fck; | ||
160 | struct clk *usbhost1_48m_fck; | ||
161 | struct clk *usbtll_fck; | ||
162 | struct clk *usbtll_ick; | ||
163 | |||
164 | /* FIXME the following two workarounds are | ||
165 | * board specific not silicon-specific so these | ||
166 | * should be moved to board-file instead. | ||
167 | * | ||
168 | * Maybe someone from TI will know better which | ||
169 | * board is affected and needs the workarounds | ||
170 | * to be applied | ||
171 | */ | ||
172 | |||
173 | /* gpio for resetting phy */ | ||
174 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; | ||
175 | |||
176 | /* phy reset workaround */ | ||
177 | int phy_reset; | ||
178 | |||
179 | /* desired phy_mode: TLL, PHY */ | ||
180 | enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; | ||
181 | |||
182 | void __iomem *uhh_base; | ||
183 | void __iomem *tll_base; | ||
184 | void __iomem *ehci_base; | ||
185 | |||
186 | /* Regulators for USB PHYs. | ||
187 | * Each PHY can have a separate regulator. | ||
188 | */ | ||
189 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; | ||
190 | }; | ||
191 | |||
192 | /*-------------------------------------------------------------------------*/ | ||
193 | |||
194 | static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask) | ||
195 | { | ||
196 | unsigned reg; | ||
197 | int i; | ||
198 | |||
199 | /* Program the 3 TLL channels upfront */ | ||
200 | for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { | ||
201 | reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); | ||
202 | |||
203 | /* Disable AutoIdle, BitStuffing and use SDR Mode */ | ||
204 | reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE | ||
205 | | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF | ||
206 | | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); | ||
207 | ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); | ||
208 | } | ||
209 | |||
210 | /* Program Common TLL register */ | ||
211 | reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF); | ||
212 | reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON | ||
213 | | OMAP_TLL_SHARED_CONF_USB_DIVRATION | ||
214 | | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN); | ||
215 | reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; | ||
216 | |||
217 | ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); | ||
218 | |||
219 | /* Enable channels now */ | ||
220 | for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { | ||
221 | reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); | ||
222 | |||
223 | /* Enable only the reg that is needed */ | ||
224 | if (!(tll_channel_mask & 1<<i)) | ||
225 | continue; | ||
226 | |||
227 | reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; | ||
228 | ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); | ||
229 | |||
230 | ehci_omap_writeb(omap->tll_base, | ||
231 | OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); | ||
232 | dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n", | ||
233 | i+1, ehci_omap_readb(omap->tll_base, | ||
234 | OMAP_TLL_ULPI_SCRATCH_REGISTER(i))); | ||
235 | } | ||
236 | } | 69 | } |
237 | 70 | ||
238 | /*-------------------------------------------------------------------------*/ | 71 | static void omap_ehci_soft_phy_reset(struct platform_device *pdev, u8 port) |
239 | |||
240 | static void omap_ehci_soft_phy_reset(struct ehci_hcd_omap *omap, u8 port) | ||
241 | { | 72 | { |
73 | struct usb_hcd *hcd = dev_get_drvdata(&pdev->dev); | ||
242 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | 74 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
243 | unsigned reg = 0; | 75 | unsigned reg = 0; |
244 | 76 | ||
@@ -252,336 +84,20 @@ static void omap_ehci_soft_phy_reset(struct ehci_hcd_omap *omap, u8 port) | |||
252 | /* start ULPI access*/ | 84 | /* start ULPI access*/ |
253 | | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT); | 85 | | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT); |
254 | 86 | ||
255 | ehci_omap_writel(omap->ehci_base, EHCI_INSNREG05_ULPI, reg); | 87 | ehci_write(hcd->regs, EHCI_INSNREG05_ULPI, reg); |
256 | 88 | ||
257 | /* Wait for ULPI access completion */ | 89 | /* Wait for ULPI access completion */ |
258 | while ((ehci_omap_readl(omap->ehci_base, EHCI_INSNREG05_ULPI) | 90 | while ((ehci_read(hcd->regs, EHCI_INSNREG05_ULPI) |
259 | & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT))) { | 91 | & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT))) { |
260 | cpu_relax(); | 92 | cpu_relax(); |
261 | 93 | ||
262 | if (time_after(jiffies, timeout)) { | 94 | if (time_after(jiffies, timeout)) { |
263 | dev_dbg(omap->dev, "phy reset operation timed out\n"); | 95 | dev_dbg(&pdev->dev, "phy reset operation timed out\n"); |
264 | break; | 96 | break; |
265 | } | 97 | } |
266 | } | 98 | } |
267 | } | 99 | } |
268 | 100 | ||
269 | /* omap_start_ehc | ||
270 | * - Start the TI USBHOST controller | ||
271 | */ | ||
272 | static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) | ||
273 | { | ||
274 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | ||
275 | u8 tll_ch_mask = 0; | ||
276 | unsigned reg = 0; | ||
277 | int ret = 0; | ||
278 | |||
279 | dev_dbg(omap->dev, "starting TI EHCI USB Controller\n"); | ||
280 | |||
281 | /* Enable Clocks for USBHOST */ | ||
282 | omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); | ||
283 | if (IS_ERR(omap->usbhost_ick)) { | ||
284 | ret = PTR_ERR(omap->usbhost_ick); | ||
285 | goto err_host_ick; | ||
286 | } | ||
287 | clk_enable(omap->usbhost_ick); | ||
288 | |||
289 | omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck"); | ||
290 | if (IS_ERR(omap->usbhost2_120m_fck)) { | ||
291 | ret = PTR_ERR(omap->usbhost2_120m_fck); | ||
292 | goto err_host_120m_fck; | ||
293 | } | ||
294 | clk_enable(omap->usbhost2_120m_fck); | ||
295 | |||
296 | omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck"); | ||
297 | if (IS_ERR(omap->usbhost1_48m_fck)) { | ||
298 | ret = PTR_ERR(omap->usbhost1_48m_fck); | ||
299 | goto err_host_48m_fck; | ||
300 | } | ||
301 | clk_enable(omap->usbhost1_48m_fck); | ||
302 | |||
303 | if (omap->phy_reset) { | ||
304 | /* Refer: ISSUE1 */ | ||
305 | if (gpio_is_valid(omap->reset_gpio_port[0])) { | ||
306 | gpio_request(omap->reset_gpio_port[0], | ||
307 | "USB1 PHY reset"); | ||
308 | gpio_direction_output(omap->reset_gpio_port[0], 0); | ||
309 | } | ||
310 | |||
311 | if (gpio_is_valid(omap->reset_gpio_port[1])) { | ||
312 | gpio_request(omap->reset_gpio_port[1], | ||
313 | "USB2 PHY reset"); | ||
314 | gpio_direction_output(omap->reset_gpio_port[1], 0); | ||
315 | } | ||
316 | |||
317 | /* Hold the PHY in RESET for enough time till DIR is high */ | ||
318 | udelay(10); | ||
319 | } | ||
320 | |||
321 | /* Configure TLL for 60Mhz clk for ULPI */ | ||
322 | omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); | ||
323 | if (IS_ERR(omap->usbtll_fck)) { | ||
324 | ret = PTR_ERR(omap->usbtll_fck); | ||
325 | goto err_tll_fck; | ||
326 | } | ||
327 | clk_enable(omap->usbtll_fck); | ||
328 | |||
329 | omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); | ||
330 | if (IS_ERR(omap->usbtll_ick)) { | ||
331 | ret = PTR_ERR(omap->usbtll_ick); | ||
332 | goto err_tll_ick; | ||
333 | } | ||
334 | clk_enable(omap->usbtll_ick); | ||
335 | |||
336 | /* perform TLL soft reset, and wait until reset is complete */ | ||
337 | ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, | ||
338 | OMAP_USBTLL_SYSCONFIG_SOFTRESET); | ||
339 | |||
340 | /* Wait for TLL reset to complete */ | ||
341 | while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) | ||
342 | & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { | ||
343 | cpu_relax(); | ||
344 | |||
345 | if (time_after(jiffies, timeout)) { | ||
346 | dev_dbg(omap->dev, "operation timed out\n"); | ||
347 | ret = -EINVAL; | ||
348 | goto err_sys_status; | ||
349 | } | ||
350 | } | ||
351 | |||
352 | dev_dbg(omap->dev, "TLL RESET DONE\n"); | ||
353 | |||
354 | /* (1<<3) = no idle mode only for initial debugging */ | ||
355 | ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, | ||
356 | OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | | ||
357 | OMAP_USBTLL_SYSCONFIG_SIDLEMODE | | ||
358 | OMAP_USBTLL_SYSCONFIG_CACTIVITY); | ||
359 | |||
360 | |||
361 | /* Put UHH in NoIdle/NoStandby mode */ | ||
362 | reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); | ||
363 | reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP | ||
364 | | OMAP_UHH_SYSCONFIG_SIDLEMODE | ||
365 | | OMAP_UHH_SYSCONFIG_CACTIVITY | ||
366 | | OMAP_UHH_SYSCONFIG_MIDLEMODE); | ||
367 | reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; | ||
368 | |||
369 | ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); | ||
370 | |||
371 | reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG); | ||
372 | |||
373 | /* setup ULPI bypass and burst configurations */ | ||
374 | reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | ||
375 | | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | ||
376 | | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); | ||
377 | reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; | ||
378 | |||
379 | if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN) | ||
380 | reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; | ||
381 | if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN) | ||
382 | reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; | ||
383 | if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN) | ||
384 | reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; | ||
385 | |||
386 | /* Bypass the TLL module for PHY mode operation */ | ||
387 | if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { | ||
388 | dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n"); | ||
389 | if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) || | ||
390 | (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) || | ||
391 | (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)) | ||
392 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; | ||
393 | else | ||
394 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; | ||
395 | } else { | ||
396 | dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); | ||
397 | if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) | ||
398 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | ||
399 | else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) | ||
400 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | ||
401 | |||
402 | if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) | ||
403 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; | ||
404 | else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) | ||
405 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; | ||
406 | |||
407 | if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY) | ||
408 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; | ||
409 | else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) | ||
410 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; | ||
411 | |||
412 | } | ||
413 | ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); | ||
414 | dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg); | ||
415 | |||
416 | |||
417 | /* | ||
418 | * An undocumented "feature" in the OMAP3 EHCI controller, | ||
419 | * causes suspended ports to be taken out of suspend when | ||
420 | * the USBCMD.Run/Stop bit is cleared (for example when | ||
421 | * we do ehci_bus_suspend). | ||
422 | * This breaks suspend-resume if the root-hub is allowed | ||
423 | * to suspend. Writing 1 to this undocumented register bit | ||
424 | * disables this feature and restores normal behavior. | ||
425 | */ | ||
426 | ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04, | ||
427 | EHCI_INSNREG04_DISABLE_UNSUSPEND); | ||
428 | |||
429 | if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || | ||
430 | (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) || | ||
431 | (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) { | ||
432 | |||
433 | if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) | ||
434 | tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK; | ||
435 | if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) | ||
436 | tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK; | ||
437 | if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) | ||
438 | tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK; | ||
439 | |||
440 | /* Enable UTMI mode for required TLL channels */ | ||
441 | omap_usb_utmi_init(omap, tll_ch_mask); | ||
442 | } | ||
443 | |||
444 | if (omap->phy_reset) { | ||
445 | /* Refer ISSUE1: | ||
446 | * Hold the PHY in RESET for enough time till | ||
447 | * PHY is settled and ready | ||
448 | */ | ||
449 | udelay(10); | ||
450 | |||
451 | if (gpio_is_valid(omap->reset_gpio_port[0])) | ||
452 | gpio_set_value(omap->reset_gpio_port[0], 1); | ||
453 | |||
454 | if (gpio_is_valid(omap->reset_gpio_port[1])) | ||
455 | gpio_set_value(omap->reset_gpio_port[1], 1); | ||
456 | } | ||
457 | |||
458 | /* Soft reset the PHY using PHY reset command over ULPI */ | ||
459 | if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) | ||
460 | omap_ehci_soft_phy_reset(omap, 0); | ||
461 | if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) | ||
462 | omap_ehci_soft_phy_reset(omap, 1); | ||
463 | |||
464 | return 0; | ||
465 | |||
466 | err_sys_status: | ||
467 | clk_disable(omap->usbtll_ick); | ||
468 | clk_put(omap->usbtll_ick); | ||
469 | |||
470 | err_tll_ick: | ||
471 | clk_disable(omap->usbtll_fck); | ||
472 | clk_put(omap->usbtll_fck); | ||
473 | |||
474 | err_tll_fck: | ||
475 | clk_disable(omap->usbhost1_48m_fck); | ||
476 | clk_put(omap->usbhost1_48m_fck); | ||
477 | |||
478 | if (omap->phy_reset) { | ||
479 | if (gpio_is_valid(omap->reset_gpio_port[0])) | ||
480 | gpio_free(omap->reset_gpio_port[0]); | ||
481 | |||
482 | if (gpio_is_valid(omap->reset_gpio_port[1])) | ||
483 | gpio_free(omap->reset_gpio_port[1]); | ||
484 | } | ||
485 | |||
486 | err_host_48m_fck: | ||
487 | clk_disable(omap->usbhost2_120m_fck); | ||
488 | clk_put(omap->usbhost2_120m_fck); | ||
489 | |||
490 | err_host_120m_fck: | ||
491 | clk_disable(omap->usbhost_ick); | ||
492 | clk_put(omap->usbhost_ick); | ||
493 | |||
494 | err_host_ick: | ||
495 | return ret; | ||
496 | } | ||
497 | |||
498 | static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) | ||
499 | { | ||
500 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | ||
501 | |||
502 | dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n"); | ||
503 | |||
504 | /* Reset OMAP modules for insmod/rmmod to work */ | ||
505 | ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, | ||
506 | OMAP_UHH_SYSCONFIG_SOFTRESET); | ||
507 | while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) | ||
508 | & (1 << 0))) { | ||
509 | cpu_relax(); | ||
510 | |||
511 | if (time_after(jiffies, timeout)) | ||
512 | dev_dbg(omap->dev, "operation timed out\n"); | ||
513 | } | ||
514 | |||
515 | while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) | ||
516 | & (1 << 1))) { | ||
517 | cpu_relax(); | ||
518 | |||
519 | if (time_after(jiffies, timeout)) | ||
520 | dev_dbg(omap->dev, "operation timed out\n"); | ||
521 | } | ||
522 | |||
523 | while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) | ||
524 | & (1 << 2))) { | ||
525 | cpu_relax(); | ||
526 | |||
527 | if (time_after(jiffies, timeout)) | ||
528 | dev_dbg(omap->dev, "operation timed out\n"); | ||
529 | } | ||
530 | |||
531 | ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); | ||
532 | |||
533 | while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) | ||
534 | & (1 << 0))) { | ||
535 | cpu_relax(); | ||
536 | |||
537 | if (time_after(jiffies, timeout)) | ||
538 | dev_dbg(omap->dev, "operation timed out\n"); | ||
539 | } | ||
540 | |||
541 | if (omap->usbtll_fck != NULL) { | ||
542 | clk_disable(omap->usbtll_fck); | ||
543 | clk_put(omap->usbtll_fck); | ||
544 | omap->usbtll_fck = NULL; | ||
545 | } | ||
546 | |||
547 | if (omap->usbhost_ick != NULL) { | ||
548 | clk_disable(omap->usbhost_ick); | ||
549 | clk_put(omap->usbhost_ick); | ||
550 | omap->usbhost_ick = NULL; | ||
551 | } | ||
552 | |||
553 | if (omap->usbhost1_48m_fck != NULL) { | ||
554 | clk_disable(omap->usbhost1_48m_fck); | ||
555 | clk_put(omap->usbhost1_48m_fck); | ||
556 | omap->usbhost1_48m_fck = NULL; | ||
557 | } | ||
558 | |||
559 | if (omap->usbhost2_120m_fck != NULL) { | ||
560 | clk_disable(omap->usbhost2_120m_fck); | ||
561 | clk_put(omap->usbhost2_120m_fck); | ||
562 | omap->usbhost2_120m_fck = NULL; | ||
563 | } | ||
564 | |||
565 | if (omap->usbtll_ick != NULL) { | ||
566 | clk_disable(omap->usbtll_ick); | ||
567 | clk_put(omap->usbtll_ick); | ||
568 | omap->usbtll_ick = NULL; | ||
569 | } | ||
570 | |||
571 | if (omap->phy_reset) { | ||
572 | if (gpio_is_valid(omap->reset_gpio_port[0])) | ||
573 | gpio_free(omap->reset_gpio_port[0]); | ||
574 | |||
575 | if (gpio_is_valid(omap->reset_gpio_port[1])) | ||
576 | gpio_free(omap->reset_gpio_port[1]); | ||
577 | } | ||
578 | |||
579 | dev_dbg(omap->dev, "Clock to USB host has been disabled\n"); | ||
580 | } | ||
581 | |||
582 | /*-------------------------------------------------------------------------*/ | ||
583 | |||
584 | static const struct hc_driver ehci_omap_hc_driver; | ||
585 | 101 | ||
586 | /* configure so an HC device and id are always provided */ | 102 | /* configure so an HC device and id are always provided */ |
587 | /* always called with process context; sleeping is OK */ | 103 | /* always called with process context; sleeping is OK */ |
@@ -595,155 +111,132 @@ static const struct hc_driver ehci_omap_hc_driver; | |||
595 | */ | 111 | */ |
596 | static int ehci_hcd_omap_probe(struct platform_device *pdev) | 112 | static int ehci_hcd_omap_probe(struct platform_device *pdev) |
597 | { | 113 | { |
598 | struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; | 114 | struct device *dev = &pdev->dev; |
599 | struct ehci_hcd_omap *omap; | 115 | struct ehci_hcd_omap_platform_data *pdata = dev->platform_data; |
600 | struct resource *res; | 116 | struct resource *res; |
601 | struct usb_hcd *hcd; | 117 | struct usb_hcd *hcd; |
602 | 118 | void __iomem *regs; | |
603 | int irq = platform_get_irq(pdev, 0); | 119 | struct ehci_hcd *omap_ehci; |
604 | int ret = -ENODEV; | 120 | int ret = -ENODEV; |
605 | int i; | 121 | int irq; |
606 | char supply[7]; | 122 | int i; |
607 | 123 | char supply[7]; | |
608 | if (!pdata) { | ||
609 | dev_dbg(&pdev->dev, "missing platform_data\n"); | ||
610 | goto err_pdata; | ||
611 | } | ||
612 | 124 | ||
613 | if (usb_disabled()) | 125 | if (usb_disabled()) |
614 | goto err_disabled; | 126 | return -ENODEV; |
615 | 127 | ||
616 | omap = kzalloc(sizeof(*omap), GFP_KERNEL); | 128 | if (!dev->parent) { |
617 | if (!omap) { | 129 | dev_err(dev, "Missing parent device\n"); |
618 | ret = -ENOMEM; | 130 | return -ENODEV; |
619 | goto err_disabled; | ||
620 | } | 131 | } |
621 | 132 | ||
622 | hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev, | 133 | irq = platform_get_irq_byname(pdev, "ehci-irq"); |
623 | dev_name(&pdev->dev)); | 134 | if (irq < 0) { |
624 | if (!hcd) { | 135 | dev_err(dev, "EHCI irq failed\n"); |
625 | dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret); | 136 | return -ENODEV; |
626 | ret = -ENOMEM; | ||
627 | goto err_create_hcd; | ||
628 | } | 137 | } |
629 | 138 | ||
630 | platform_set_drvdata(pdev, omap); | 139 | res = platform_get_resource_byname(pdev, |
631 | omap->dev = &pdev->dev; | 140 | IORESOURCE_MEM, "ehci"); |
632 | omap->phy_reset = pdata->phy_reset; | 141 | if (!res) { |
633 | omap->reset_gpio_port[0] = pdata->reset_gpio_port[0]; | 142 | dev_err(dev, "UHH EHCI get resource failed\n"); |
634 | omap->reset_gpio_port[1] = pdata->reset_gpio_port[1]; | 143 | return -ENODEV; |
635 | omap->reset_gpio_port[2] = pdata->reset_gpio_port[2]; | ||
636 | omap->port_mode[0] = pdata->port_mode[0]; | ||
637 | omap->port_mode[1] = pdata->port_mode[1]; | ||
638 | omap->port_mode[2] = pdata->port_mode[2]; | ||
639 | omap->ehci = hcd_to_ehci(hcd); | ||
640 | omap->ehci->sbrn = 0x20; | ||
641 | |||
642 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
643 | |||
644 | hcd->rsrc_start = res->start; | ||
645 | hcd->rsrc_len = resource_size(res); | ||
646 | |||
647 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
648 | if (!hcd->regs) { | ||
649 | dev_err(&pdev->dev, "EHCI ioremap failed\n"); | ||
650 | ret = -ENOMEM; | ||
651 | goto err_ioremap; | ||
652 | } | 144 | } |
653 | 145 | ||
654 | /* we know this is the memory we want, no need to ioremap again */ | 146 | regs = ioremap(res->start, resource_size(res)); |
655 | omap->ehci->caps = hcd->regs; | 147 | if (!regs) { |
656 | omap->ehci_base = hcd->regs; | 148 | dev_err(dev, "UHH EHCI ioremap failed\n"); |
657 | 149 | return -ENOMEM; | |
658 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
659 | omap->uhh_base = ioremap(res->start, resource_size(res)); | ||
660 | if (!omap->uhh_base) { | ||
661 | dev_err(&pdev->dev, "UHH ioremap failed\n"); | ||
662 | ret = -ENOMEM; | ||
663 | goto err_uhh_ioremap; | ||
664 | } | 150 | } |
665 | 151 | ||
666 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | 152 | hcd = usb_create_hcd(&ehci_omap_hc_driver, dev, |
667 | omap->tll_base = ioremap(res->start, resource_size(res)); | 153 | dev_name(dev)); |
668 | if (!omap->tll_base) { | 154 | if (!hcd) { |
669 | dev_err(&pdev->dev, "TLL ioremap failed\n"); | 155 | dev_err(dev, "failed to create hcd with err %d\n", ret); |
670 | ret = -ENOMEM; | 156 | ret = -ENOMEM; |
671 | goto err_tll_ioremap; | 157 | goto err_io; |
672 | } | 158 | } |
673 | 159 | ||
160 | hcd->rsrc_start = res->start; | ||
161 | hcd->rsrc_len = resource_size(res); | ||
162 | hcd->regs = regs; | ||
163 | |||
674 | /* get ehci regulator and enable */ | 164 | /* get ehci regulator and enable */ |
675 | for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { | 165 | for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { |
676 | if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) { | 166 | if (pdata->port_mode[i] != OMAP_EHCI_PORT_MODE_PHY) { |
677 | omap->regulator[i] = NULL; | 167 | pdata->regulator[i] = NULL; |
678 | continue; | 168 | continue; |
679 | } | 169 | } |
680 | snprintf(supply, sizeof(supply), "hsusb%d", i); | 170 | snprintf(supply, sizeof(supply), "hsusb%d", i); |
681 | omap->regulator[i] = regulator_get(omap->dev, supply); | 171 | pdata->regulator[i] = regulator_get(dev, supply); |
682 | if (IS_ERR(omap->regulator[i])) { | 172 | if (IS_ERR(pdata->regulator[i])) { |
683 | omap->regulator[i] = NULL; | 173 | pdata->regulator[i] = NULL; |
684 | dev_dbg(&pdev->dev, | 174 | dev_dbg(dev, |
685 | "failed to get ehci port%d regulator\n", i); | 175 | "failed to get ehci port%d regulator\n", i); |
686 | } else { | 176 | } else { |
687 | regulator_enable(omap->regulator[i]); | 177 | regulator_enable(pdata->regulator[i]); |
688 | } | 178 | } |
689 | } | 179 | } |
690 | 180 | ||
691 | ret = omap_start_ehc(omap, hcd); | 181 | ret = omap_usbhs_enable(dev); |
692 | if (ret) { | 182 | if (ret) { |
693 | dev_dbg(&pdev->dev, "failed to start ehci\n"); | 183 | dev_err(dev, "failed to start usbhs with err %d\n", ret); |
694 | goto err_start; | 184 | goto err_enable; |
695 | } | 185 | } |
696 | 186 | ||
697 | omap->ehci->regs = hcd->regs | 187 | /* |
698 | + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase)); | 188 | * An undocumented "feature" in the OMAP3 EHCI controller, |
189 | * causes suspended ports to be taken out of suspend when | ||
190 | * the USBCMD.Run/Stop bit is cleared (for example when | ||
191 | * we do ehci_bus_suspend). | ||
192 | * This breaks suspend-resume if the root-hub is allowed | ||
193 | * to suspend. Writing 1 to this undocumented register bit | ||
194 | * disables this feature and restores normal behavior. | ||
195 | */ | ||
196 | ehci_write(regs, EHCI_INSNREG04, | ||
197 | EHCI_INSNREG04_DISABLE_UNSUSPEND); | ||
198 | |||
199 | /* Soft reset the PHY using PHY reset command over ULPI */ | ||
200 | if (pdata->port_mode[0] == OMAP_EHCI_PORT_MODE_PHY) | ||
201 | omap_ehci_soft_phy_reset(pdev, 0); | ||
202 | if (pdata->port_mode[1] == OMAP_EHCI_PORT_MODE_PHY) | ||
203 | omap_ehci_soft_phy_reset(pdev, 1); | ||
204 | |||
205 | omap_ehci = hcd_to_ehci(hcd); | ||
206 | omap_ehci->sbrn = 0x20; | ||
699 | 207 | ||
700 | dbg_hcs_params(omap->ehci, "reset"); | 208 | /* we know this is the memory we want, no need to ioremap again */ |
701 | dbg_hcc_params(omap->ehci, "reset"); | 209 | omap_ehci->caps = hcd->regs; |
210 | omap_ehci->regs = hcd->regs | ||
211 | + HC_LENGTH(ehci, readl(&omap_ehci->caps->hc_capbase)); | ||
212 | |||
213 | dbg_hcs_params(omap_ehci, "reset"); | ||
214 | dbg_hcc_params(omap_ehci, "reset"); | ||
702 | 215 | ||
703 | /* cache this readonly data; minimize chip reads */ | 216 | /* cache this readonly data; minimize chip reads */ |
704 | omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params); | 217 | omap_ehci->hcs_params = readl(&omap_ehci->caps->hcs_params); |
705 | 218 | ||
706 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | 219 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); |
707 | if (ret) { | 220 | if (ret) { |
708 | dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); | 221 | dev_err(dev, "failed to add hcd with err %d\n", ret); |
709 | goto err_add_hcd; | 222 | goto err_add_hcd; |
710 | } | 223 | } |
711 | 224 | ||
712 | /* root ports should always stay powered */ | 225 | /* root ports should always stay powered */ |
713 | ehci_port_power(omap->ehci, 1); | 226 | ehci_port_power(omap_ehci, 1); |
714 | 227 | ||
715 | return 0; | 228 | return 0; |
716 | 229 | ||
717 | err_add_hcd: | 230 | err_add_hcd: |
718 | omap_stop_ehc(omap, hcd); | 231 | omap_usbhs_disable(dev); |
719 | |||
720 | err_start: | ||
721 | for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { | ||
722 | if (omap->regulator[i]) { | ||
723 | regulator_disable(omap->regulator[i]); | ||
724 | regulator_put(omap->regulator[i]); | ||
725 | } | ||
726 | } | ||
727 | iounmap(omap->tll_base); | ||
728 | |||
729 | err_tll_ioremap: | ||
730 | iounmap(omap->uhh_base); | ||
731 | 232 | ||
732 | err_uhh_ioremap: | 233 | err_enable: |
733 | iounmap(hcd->regs); | ||
734 | |||
735 | err_ioremap: | ||
736 | usb_put_hcd(hcd); | 234 | usb_put_hcd(hcd); |
737 | 235 | ||
738 | err_create_hcd: | 236 | err_io: |
739 | kfree(omap); | ||
740 | err_disabled: | ||
741 | err_pdata: | ||
742 | return ret; | 237 | return ret; |
743 | } | 238 | } |
744 | 239 | ||
745 | /* may be called without controller electrically present */ | ||
746 | /* may be called with controller, bus, and devices active */ | ||
747 | 240 | ||
748 | /** | 241 | /** |
749 | * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs | 242 | * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs |
@@ -755,31 +248,18 @@ err_pdata: | |||
755 | */ | 248 | */ |
756 | static int ehci_hcd_omap_remove(struct platform_device *pdev) | 249 | static int ehci_hcd_omap_remove(struct platform_device *pdev) |
757 | { | 250 | { |
758 | struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); | 251 | struct device *dev = &pdev->dev; |
759 | struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); | 252 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
760 | int i; | ||
761 | 253 | ||
762 | usb_remove_hcd(hcd); | 254 | usb_remove_hcd(hcd); |
763 | omap_stop_ehc(omap, hcd); | 255 | omap_usbhs_disable(dev); |
764 | iounmap(hcd->regs); | ||
765 | for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { | ||
766 | if (omap->regulator[i]) { | ||
767 | regulator_disable(omap->regulator[i]); | ||
768 | regulator_put(omap->regulator[i]); | ||
769 | } | ||
770 | } | ||
771 | iounmap(omap->tll_base); | ||
772 | iounmap(omap->uhh_base); | ||
773 | usb_put_hcd(hcd); | 256 | usb_put_hcd(hcd); |
774 | kfree(omap); | ||
775 | |||
776 | return 0; | 257 | return 0; |
777 | } | 258 | } |
778 | 259 | ||
779 | static void ehci_hcd_omap_shutdown(struct platform_device *pdev) | 260 | static void ehci_hcd_omap_shutdown(struct platform_device *pdev) |
780 | { | 261 | { |
781 | struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); | 262 | struct usb_hcd *hcd = dev_get_drvdata(&pdev->dev); |
782 | struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); | ||
783 | 263 | ||
784 | if (hcd->driver->shutdown) | 264 | if (hcd->driver->shutdown) |
785 | hcd->driver->shutdown(hcd); | 265 | hcd->driver->shutdown(hcd); |
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index 0f87dc72820a..395bdb0248d5 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c | |||
@@ -105,7 +105,8 @@ static int ehci_orion_setup(struct usb_hcd *hcd) | |||
105 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 105 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
106 | int retval; | 106 | int retval; |
107 | 107 | ||
108 | ehci_reset(ehci); | 108 | hcd->has_tt = 1; |
109 | |||
109 | retval = ehci_halt(ehci); | 110 | retval = ehci_halt(ehci); |
110 | if (retval) | 111 | if (retval) |
111 | return retval; | 112 | return retval; |
@@ -117,7 +118,7 @@ static int ehci_orion_setup(struct usb_hcd *hcd) | |||
117 | if (retval) | 118 | if (retval) |
118 | return retval; | 119 | return retval; |
119 | 120 | ||
120 | hcd->has_tt = 1; | 121 | ehci_reset(ehci); |
121 | 122 | ||
122 | ehci_port_power(ehci, 0); | 123 | ehci_port_power(ehci, 0); |
123 | 124 | ||
@@ -250,7 +251,7 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) | |||
250 | ehci = hcd_to_ehci(hcd); | 251 | ehci = hcd_to_ehci(hcd); |
251 | ehci->caps = hcd->regs + 0x100; | 252 | ehci->caps = hcd->regs + 0x100; |
252 | ehci->regs = hcd->regs + 0x100 + | 253 | ehci->regs = hcd->regs + 0x100 + |
253 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 254 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
254 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | 255 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
255 | hcd->has_tt = 1; | 256 | hcd->has_tt = 1; |
256 | ehci->sbrn = 0x20; | 257 | ehci->sbrn = 0x20; |
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index a1e8d273103f..1102ce65a3a9 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c | |||
@@ -22,6 +22,9 @@ | |||
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | 22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." |
23 | #endif | 23 | #endif |
24 | 24 | ||
25 | /* defined here to avoid adding to pci_ids.h for single instance use */ | ||
26 | #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 | ||
27 | |||
25 | /*-------------------------------------------------------------------------*/ | 28 | /*-------------------------------------------------------------------------*/ |
26 | 29 | ||
27 | /* called after powerup, by probe or system-pm "wakeup" */ | 30 | /* called after powerup, by probe or system-pm "wakeup" */ |
@@ -67,7 +70,7 @@ static int ehci_pci_setup(struct usb_hcd *hcd) | |||
67 | 70 | ||
68 | ehci->caps = hcd->regs; | 71 | ehci->caps = hcd->regs; |
69 | ehci->regs = hcd->regs + | 72 | ehci->regs = hcd->regs + |
70 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 73 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
71 | 74 | ||
72 | dbg_hcs_params(ehci, "reset"); | 75 | dbg_hcs_params(ehci, "reset"); |
73 | dbg_hcc_params(ehci, "reset"); | 76 | dbg_hcc_params(ehci, "reset"); |
@@ -103,6 +106,19 @@ static int ehci_pci_setup(struct usb_hcd *hcd) | |||
103 | if (retval) | 106 | if (retval) |
104 | return retval; | 107 | return retval; |
105 | 108 | ||
109 | if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) || | ||
110 | (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) { | ||
111 | /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | ||
112 | * read/write memory space which does not belong to it when | ||
113 | * there is NULL pointer with T-bit set to 1 in the frame list | ||
114 | * table. To avoid the issue, the frame list link pointer | ||
115 | * should always contain a valid pointer to a inactive qh. | ||
116 | */ | ||
117 | ehci->use_dummy_qh = 1; | ||
118 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI " | ||
119 | "dummy qh workaround\n"); | ||
120 | } | ||
121 | |||
106 | /* data structure init */ | 122 | /* data structure init */ |
107 | retval = ehci_init(hcd); | 123 | retval = ehci_init(hcd); |
108 | if (retval) | 124 | if (retval) |
@@ -124,6 +140,10 @@ static int ehci_pci_setup(struct usb_hcd *hcd) | |||
124 | ehci_info(ehci, "disable lpm for langwell/penwell\n"); | 140 | ehci_info(ehci, "disable lpm for langwell/penwell\n"); |
125 | ehci->has_lpm = 0; | 141 | ehci->has_lpm = 0; |
126 | } | 142 | } |
143 | if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) { | ||
144 | hcd->has_tt = 1; | ||
145 | tdi_reset(ehci); | ||
146 | } | ||
127 | break; | 147 | break; |
128 | case PCI_VENDOR_ID_TDI: | 148 | case PCI_VENDOR_ID_TDI: |
129 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | 149 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { |
@@ -132,6 +152,9 @@ static int ehci_pci_setup(struct usb_hcd *hcd) | |||
132 | } | 152 | } |
133 | break; | 153 | break; |
134 | case PCI_VENDOR_ID_AMD: | 154 | case PCI_VENDOR_ID_AMD: |
155 | /* AMD PLL quirk */ | ||
156 | if (usb_amd_find_chipset_info()) | ||
157 | ehci->amd_pll_fix = 1; | ||
135 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | 158 | /* AMD8111 EHCI doesn't work, according to AMD errata */ |
136 | if (pdev->device == 0x7463) { | 159 | if (pdev->device == 0x7463) { |
137 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | 160 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); |
@@ -148,6 +171,18 @@ static int ehci_pci_setup(struct usb_hcd *hcd) | |||
148 | if (pdev->revision < 0xa4) | 171 | if (pdev->revision < 0xa4) |
149 | ehci->no_selective_suspend = 1; | 172 | ehci->no_selective_suspend = 1; |
150 | break; | 173 | break; |
174 | |||
175 | /* MCP89 chips on the MacBookAir3,1 give EPROTO when | ||
176 | * fetching device descriptors unless LPM is disabled. | ||
177 | * There are also intermittent problems enumerating | ||
178 | * devices with PPCD enabled. | ||
179 | */ | ||
180 | case 0x0d9d: | ||
181 | ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89"); | ||
182 | ehci->has_lpm = 0; | ||
183 | ehci->has_ppcd = 0; | ||
184 | ehci->command &= ~CMD_PPCEE; | ||
185 | break; | ||
151 | } | 186 | } |
152 | break; | 187 | break; |
153 | case PCI_VENDOR_ID_VIA: | 188 | case PCI_VENDOR_ID_VIA: |
@@ -165,6 +200,9 @@ static int ehci_pci_setup(struct usb_hcd *hcd) | |||
165 | } | 200 | } |
166 | break; | 201 | break; |
167 | case PCI_VENDOR_ID_ATI: | 202 | case PCI_VENDOR_ID_ATI: |
203 | /* AMD PLL quirk */ | ||
204 | if (usb_amd_find_chipset_info()) | ||
205 | ehci->amd_pll_fix = 1; | ||
168 | /* SB600 and old version of SB700 have a bug in EHCI controller, | 206 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
169 | * which causes usb devices lose response in some cases. | 207 | * which causes usb devices lose response in some cases. |
170 | */ | 208 | */ |
@@ -296,8 +334,8 @@ static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |||
296 | * mark HW unaccessible. The PM and USB cores make sure that | 334 | * mark HW unaccessible. The PM and USB cores make sure that |
297 | * the root hub is either suspended or stopped. | 335 | * the root hub is either suspended or stopped. |
298 | */ | 336 | */ |
299 | spin_lock_irqsave (&ehci->lock, flags); | ||
300 | ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); | 337 | ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); |
338 | spin_lock_irqsave (&ehci->lock, flags); | ||
301 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | 339 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
302 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); | 340 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); |
303 | 341 | ||
@@ -310,11 +348,50 @@ static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |||
310 | return rc; | 348 | return rc; |
311 | } | 349 | } |
312 | 350 | ||
351 | static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) | ||
352 | { | ||
353 | return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && | ||
354 | pdev->vendor == PCI_VENDOR_ID_INTEL && | ||
355 | pdev->device == 0x1E26; | ||
356 | } | ||
357 | |||
358 | static void ehci_enable_xhci_companion(void) | ||
359 | { | ||
360 | struct pci_dev *companion = NULL; | ||
361 | |||
362 | /* The xHCI and EHCI controllers are not on the same PCI slot */ | ||
363 | for_each_pci_dev(companion) { | ||
364 | if (!usb_is_intel_switchable_xhci(companion)) | ||
365 | continue; | ||
366 | usb_enable_xhci_ports(companion); | ||
367 | return; | ||
368 | } | ||
369 | } | ||
370 | |||
313 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) | 371 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
314 | { | 372 | { |
315 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | 373 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
316 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | 374 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
317 | 375 | ||
376 | /* The BIOS on systems with the Intel Panther Point chipset may or may | ||
377 | * not support xHCI natively. That means that during system resume, it | ||
378 | * may switch the ports back to EHCI so that users can use their | ||
379 | * keyboard to select a kernel from GRUB after resume from hibernate. | ||
380 | * | ||
381 | * The BIOS is supposed to remember whether the OS had xHCI ports | ||
382 | * enabled before resume, and switch the ports back to xHCI when the | ||
383 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | ||
384 | * writers. | ||
385 | * | ||
386 | * Unconditionally switch the ports back to xHCI after a system resume. | ||
387 | * We can't tell whether the EHCI or xHCI controller will be resumed | ||
388 | * first, so we have to do the port switchover in both drivers. Writing | ||
389 | * a '1' to the port switchover registers should have no effect if the | ||
390 | * port was already switched over. | ||
391 | */ | ||
392 | if (usb_is_intel_switchable_ehci(pdev)) | ||
393 | ehci_enable_xhci_companion(); | ||
394 | |||
318 | // maybe restore FLADJ | 395 | // maybe restore FLADJ |
319 | 396 | ||
320 | if (time_before(jiffies, ehci->next_statechange)) | 397 | if (time_before(jiffies, ehci->next_statechange)) |
diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c new file mode 100644 index 000000000000..cd69099cda19 --- /dev/null +++ b/drivers/usb/host/ehci-pmcmsp.c | |||
@@ -0,0 +1,383 @@ | |||
1 | /* | ||
2 | * PMC MSP EHCI (Host Controller Driver) for USB. | ||
3 | * | ||
4 | * (C) Copyright 2006-2010 PMC-Sierra Inc | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | /* includes */ | ||
13 | #include <linux/platform_device.h> | ||
14 | #include <linux/gpio.h> | ||
15 | #include <linux/usb.h> | ||
16 | #include <msp_usb.h> | ||
17 | |||
18 | /* stream disable*/ | ||
19 | #define USB_CTRL_MODE_STREAM_DISABLE 0x10 | ||
20 | |||
21 | /* threshold */ | ||
22 | #define USB_CTRL_FIFO_THRESH 0x00300000 | ||
23 | |||
24 | /* register offset for usb_mode */ | ||
25 | #define USB_EHCI_REG_USB_MODE 0x68 | ||
26 | |||
27 | /* register offset for usb fifo */ | ||
28 | #define USB_EHCI_REG_USB_FIFO 0x24 | ||
29 | |||
30 | /* register offset for usb status */ | ||
31 | #define USB_EHCI_REG_USB_STATUS 0x44 | ||
32 | |||
33 | /* serial/parallel transceiver */ | ||
34 | #define USB_EHCI_REG_BIT_STAT_STS (1<<29) | ||
35 | |||
36 | /* TWI USB0 host device pin */ | ||
37 | #define MSP_PIN_USB0_HOST_DEV 49 | ||
38 | |||
39 | /* TWI USB1 host device pin */ | ||
40 | #define MSP_PIN_USB1_HOST_DEV 50 | ||
41 | |||
42 | |||
43 | static void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) | ||
44 | { | ||
45 | u8 *base; | ||
46 | u8 *statreg; | ||
47 | u8 *fiforeg; | ||
48 | u32 val; | ||
49 | struct ehci_regs *reg_base = ehci->regs; | ||
50 | |||
51 | /* get register base */ | ||
52 | base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; | ||
53 | statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; | ||
54 | fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; | ||
55 | |||
56 | /* Disable controller mode stream */ | ||
57 | val = ehci_readl(ehci, (u32 *)base); | ||
58 | ehci_writel(ehci, (val | USB_CTRL_MODE_STREAM_DISABLE), | ||
59 | (u32 *)base); | ||
60 | |||
61 | /* clear STS to select parallel transceiver interface */ | ||
62 | val = ehci_readl(ehci, (u32 *)statreg); | ||
63 | val = val & ~USB_EHCI_REG_BIT_STAT_STS; | ||
64 | ehci_writel(ehci, val, (u32 *)statreg); | ||
65 | |||
66 | /* write to set the proper fifo threshold */ | ||
67 | ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); | ||
68 | |||
69 | /* set TWI GPIO USB_HOST_DEV pin high */ | ||
70 | gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); | ||
71 | #ifdef CONFIG_MSP_HAS_DUAL_USB | ||
72 | gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); | ||
73 | #endif | ||
74 | } | ||
75 | |||
76 | /* called during probe() after chip reset completes */ | ||
77 | static int ehci_msp_setup(struct usb_hcd *hcd) | ||
78 | { | ||
79 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
80 | int retval; | ||
81 | ehci->big_endian_mmio = 1; | ||
82 | ehci->big_endian_desc = 1; | ||
83 | |||
84 | ehci->caps = hcd->regs; | ||
85 | ehci->regs = hcd->regs + | ||
86 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | ||
87 | dbg_hcs_params(ehci, "reset"); | ||
88 | dbg_hcc_params(ehci, "reset"); | ||
89 | |||
90 | /* cache this readonly data; minimize chip reads */ | ||
91 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
92 | hcd->has_tt = 1; | ||
93 | |||
94 | retval = ehci_halt(ehci); | ||
95 | if (retval) | ||
96 | return retval; | ||
97 | |||
98 | ehci_reset(ehci); | ||
99 | |||
100 | /* data structure init */ | ||
101 | retval = ehci_init(hcd); | ||
102 | if (retval) | ||
103 | return retval; | ||
104 | |||
105 | usb_hcd_tdi_set_mode(ehci); | ||
106 | ehci_port_power(ehci, 0); | ||
107 | |||
108 | return retval; | ||
109 | } | ||
110 | |||
111 | |||
112 | /* configure so an HC device and id are always provided | ||
113 | * always called with process context; sleeping is OK | ||
114 | */ | ||
115 | |||
116 | static int usb_hcd_msp_map_regs(struct mspusb_device *dev) | ||
117 | { | ||
118 | struct resource *res; | ||
119 | struct platform_device *pdev = &dev->dev; | ||
120 | u32 res_len; | ||
121 | int retval; | ||
122 | |||
123 | /* MAB register space */ | ||
124 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
125 | if (res == NULL) | ||
126 | return -ENOMEM; | ||
127 | res_len = res->end - res->start + 1; | ||
128 | if (!request_mem_region(res->start, res_len, "mab regs")) | ||
129 | return -EBUSY; | ||
130 | |||
131 | dev->mab_regs = ioremap_nocache(res->start, res_len); | ||
132 | if (dev->mab_regs == NULL) { | ||
133 | retval = -ENOMEM; | ||
134 | goto err1; | ||
135 | } | ||
136 | |||
137 | /* MSP USB register space */ | ||
138 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | ||
139 | if (res == NULL) { | ||
140 | retval = -ENOMEM; | ||
141 | goto err2; | ||
142 | } | ||
143 | res_len = res->end - res->start + 1; | ||
144 | if (!request_mem_region(res->start, res_len, "usbid regs")) { | ||
145 | retval = -EBUSY; | ||
146 | goto err2; | ||
147 | } | ||
148 | dev->usbid_regs = ioremap_nocache(res->start, res_len); | ||
149 | if (dev->usbid_regs == NULL) { | ||
150 | retval = -ENOMEM; | ||
151 | goto err3; | ||
152 | } | ||
153 | |||
154 | return 0; | ||
155 | err3: | ||
156 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | ||
157 | res_len = res->end - res->start + 1; | ||
158 | release_mem_region(res->start, res_len); | ||
159 | err2: | ||
160 | iounmap(dev->mab_regs); | ||
161 | err1: | ||
162 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
163 | res_len = res->end - res->start + 1; | ||
164 | release_mem_region(res->start, res_len); | ||
165 | dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); | ||
166 | return retval; | ||
167 | } | ||
168 | |||
169 | /** | ||
170 | * usb_hcd_msp_probe - initialize PMC MSP-based HCDs | ||
171 | * Context: !in_interrupt() | ||
172 | * | ||
173 | * Allocates basic resources for this USB host controller, and | ||
174 | * then invokes the start() method for the HCD associated with it | ||
175 | * through the hotplug entry's driver_data. | ||
176 | * | ||
177 | */ | ||
178 | int usb_hcd_msp_probe(const struct hc_driver *driver, | ||
179 | struct platform_device *dev) | ||
180 | { | ||
181 | int retval; | ||
182 | struct usb_hcd *hcd; | ||
183 | struct resource *res; | ||
184 | struct ehci_hcd *ehci ; | ||
185 | |||
186 | hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); | ||
187 | if (!hcd) | ||
188 | return -ENOMEM; | ||
189 | |||
190 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | ||
191 | if (res == NULL) { | ||
192 | pr_debug("No IOMEM resource info for %s.\n", dev->name); | ||
193 | retval = -ENOMEM; | ||
194 | goto err1; | ||
195 | } | ||
196 | hcd->rsrc_start = res->start; | ||
197 | hcd->rsrc_len = res->end - res->start + 1; | ||
198 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { | ||
199 | retval = -EBUSY; | ||
200 | goto err1; | ||
201 | } | ||
202 | hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); | ||
203 | if (!hcd->regs) { | ||
204 | pr_debug("ioremap failed"); | ||
205 | retval = -ENOMEM; | ||
206 | goto err2; | ||
207 | } | ||
208 | |||
209 | res = platform_get_resource(dev, IORESOURCE_IRQ, 0); | ||
210 | if (res == NULL) { | ||
211 | dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); | ||
212 | retval = -ENOMEM; | ||
213 | goto err3; | ||
214 | } | ||
215 | |||
216 | /* Map non-EHCI register spaces */ | ||
217 | retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); | ||
218 | if (retval != 0) | ||
219 | goto err3; | ||
220 | |||
221 | ehci = hcd_to_ehci(hcd); | ||
222 | ehci->big_endian_mmio = 1; | ||
223 | ehci->big_endian_desc = 1; | ||
224 | |||
225 | |||
226 | retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); | ||
227 | if (retval == 0) | ||
228 | return 0; | ||
229 | |||
230 | usb_remove_hcd(hcd); | ||
231 | err3: | ||
232 | iounmap(hcd->regs); | ||
233 | err2: | ||
234 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
235 | err1: | ||
236 | usb_put_hcd(hcd); | ||
237 | |||
238 | return retval; | ||
239 | } | ||
240 | |||
241 | |||
242 | |||
243 | /** | ||
244 | * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs | ||
245 | * @dev: USB Host Controller being removed | ||
246 | * Context: !in_interrupt() | ||
247 | * | ||
248 | * Reverses the effect of usb_hcd_msp_probe(), first invoking | ||
249 | * the HCD's stop() method. It is always called from a thread | ||
250 | * context, normally "rmmod", "apmd", or something similar. | ||
251 | * | ||
252 | * may be called without controller electrically present | ||
253 | * may be called with controller, bus, and devices active | ||
254 | */ | ||
255 | void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) | ||
256 | { | ||
257 | usb_remove_hcd(hcd); | ||
258 | iounmap(hcd->regs); | ||
259 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
260 | usb_put_hcd(hcd); | ||
261 | } | ||
262 | |||
263 | #ifdef CONFIG_MSP_HAS_DUAL_USB | ||
264 | /* | ||
265 | * Wrapper around the main ehci_irq. Since both USB host controllers are | ||
266 | * sharing the same IRQ, need to first determine whether we're the intended | ||
267 | * recipient of this interrupt. | ||
268 | */ | ||
269 | static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) | ||
270 | { | ||
271 | u32 int_src; | ||
272 | struct device *dev = hcd->self.controller; | ||
273 | struct platform_device *pdev; | ||
274 | struct mspusb_device *mdev; | ||
275 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
276 | /* need to reverse-map a couple of containers to get our device */ | ||
277 | pdev = to_platform_device(dev); | ||
278 | mdev = to_mspusb_device(pdev); | ||
279 | |||
280 | /* Check to see if this interrupt is for this host controller */ | ||
281 | int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); | ||
282 | if (int_src & (1 << pdev->id)) | ||
283 | return ehci_irq(hcd); | ||
284 | |||
285 | /* Not for this device */ | ||
286 | return IRQ_NONE; | ||
287 | } | ||
288 | #endif /* DUAL_USB */ | ||
289 | |||
290 | static const struct hc_driver ehci_msp_hc_driver = { | ||
291 | .description = hcd_name, | ||
292 | .product_desc = "PMC MSP EHCI", | ||
293 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
294 | |||
295 | /* | ||
296 | * generic hardware linkage | ||
297 | */ | ||
298 | #ifdef CONFIG_MSP_HAS_DUAL_USB | ||
299 | .irq = ehci_msp_irq, | ||
300 | #else | ||
301 | .irq = ehci_irq, | ||
302 | #endif | ||
303 | .flags = HCD_MEMORY | HCD_USB2, | ||
304 | |||
305 | /* | ||
306 | * basic lifecycle operations | ||
307 | */ | ||
308 | .reset = ehci_msp_setup, | ||
309 | .start = ehci_run, | ||
310 | .shutdown = ehci_shutdown, | ||
311 | .start = ehci_run, | ||
312 | .stop = ehci_stop, | ||
313 | |||
314 | /* | ||
315 | * managing i/o requests and associated device resources | ||
316 | */ | ||
317 | .urb_enqueue = ehci_urb_enqueue, | ||
318 | .urb_dequeue = ehci_urb_dequeue, | ||
319 | .endpoint_disable = ehci_endpoint_disable, | ||
320 | .endpoint_reset = ehci_endpoint_reset, | ||
321 | |||
322 | /* | ||
323 | * scheduling support | ||
324 | */ | ||
325 | .get_frame_number = ehci_get_frame, | ||
326 | |||
327 | /* | ||
328 | * root hub support | ||
329 | */ | ||
330 | .hub_status_data = ehci_hub_status_data, | ||
331 | .hub_control = ehci_hub_control, | ||
332 | .bus_suspend = ehci_bus_suspend, | ||
333 | .bus_resume = ehci_bus_resume, | ||
334 | .relinquish_port = ehci_relinquish_port, | ||
335 | .port_handed_over = ehci_port_handed_over, | ||
336 | |||
337 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
338 | }; | ||
339 | |||
340 | static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) | ||
341 | { | ||
342 | int ret; | ||
343 | |||
344 | pr_debug("In ehci_hcd_msp_drv_probe"); | ||
345 | |||
346 | if (usb_disabled()) | ||
347 | return -ENODEV; | ||
348 | |||
349 | gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); | ||
350 | #ifdef CONFIG_MSP_HAS_DUAL_USB | ||
351 | gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); | ||
352 | #endif | ||
353 | |||
354 | ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); | ||
355 | |||
356 | return ret; | ||
357 | } | ||
358 | |||
359 | static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) | ||
360 | { | ||
361 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
362 | |||
363 | usb_hcd_msp_remove(hcd, pdev); | ||
364 | |||
365 | /* free TWI GPIO USB_HOST_DEV pin */ | ||
366 | gpio_free(MSP_PIN_USB0_HOST_DEV); | ||
367 | #ifdef CONFIG_MSP_HAS_DUAL_USB | ||
368 | gpio_free(MSP_PIN_USB1_HOST_DEV); | ||
369 | #endif | ||
370 | |||
371 | return 0; | ||
372 | } | ||
373 | |||
374 | MODULE_ALIAS("pmcmsp-ehci"); | ||
375 | |||
376 | static struct platform_driver ehci_hcd_msp_driver = { | ||
377 | .probe = ehci_hcd_msp_drv_probe, | ||
378 | .remove = ehci_hcd_msp_drv_remove, | ||
379 | .driver = { | ||
380 | .name = "pmcmsp-ehci", | ||
381 | .owner = THIS_MODULE, | ||
382 | }, | ||
383 | }; | ||
diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c index ba52be473027..8552db6c29c9 100644 --- a/drivers/usb/host/ehci-ppc-of.c +++ b/drivers/usb/host/ehci-ppc-of.c | |||
@@ -105,8 +105,7 @@ ppc44x_enable_bmt(struct device_node *dn) | |||
105 | } | 105 | } |
106 | 106 | ||
107 | 107 | ||
108 | static int __devinit | 108 | static int __devinit ehci_hcd_ppc_of_probe(struct platform_device *op) |
109 | ehci_hcd_ppc_of_probe(struct platform_device *op, const struct of_device_id *match) | ||
110 | { | 109 | { |
111 | struct device_node *dn = op->dev.of_node; | 110 | struct device_node *dn = op->dev.of_node; |
112 | struct usb_hcd *hcd; | 111 | struct usb_hcd *hcd; |
@@ -180,7 +179,7 @@ ehci_hcd_ppc_of_probe(struct platform_device *op, const struct of_device_id *mat | |||
180 | 179 | ||
181 | ehci->caps = hcd->regs; | 180 | ehci->caps = hcd->regs; |
182 | ehci->regs = hcd->regs + | 181 | ehci->regs = hcd->regs + |
183 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 182 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
184 | 183 | ||
185 | /* cache this readonly data; minimize chip reads */ | 184 | /* cache this readonly data; minimize chip reads */ |
186 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | 185 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
@@ -255,14 +254,12 @@ static int ehci_hcd_ppc_of_remove(struct platform_device *op) | |||
255 | } | 254 | } |
256 | 255 | ||
257 | 256 | ||
258 | static int ehci_hcd_ppc_of_shutdown(struct platform_device *op) | 257 | static void ehci_hcd_ppc_of_shutdown(struct platform_device *op) |
259 | { | 258 | { |
260 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); | 259 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); |
261 | 260 | ||
262 | if (hcd->driver->shutdown) | 261 | if (hcd->driver->shutdown) |
263 | hcd->driver->shutdown(hcd); | 262 | hcd->driver->shutdown(hcd); |
264 | |||
265 | return 0; | ||
266 | } | 263 | } |
267 | 264 | ||
268 | 265 | ||
@@ -275,7 +272,7 @@ static const struct of_device_id ehci_hcd_ppc_of_match[] = { | |||
275 | MODULE_DEVICE_TABLE(of, ehci_hcd_ppc_of_match); | 272 | MODULE_DEVICE_TABLE(of, ehci_hcd_ppc_of_match); |
276 | 273 | ||
277 | 274 | ||
278 | static struct of_platform_driver ehci_hcd_ppc_of_driver = { | 275 | static struct platform_driver ehci_hcd_ppc_of_driver = { |
279 | .probe = ehci_hcd_ppc_of_probe, | 276 | .probe = ehci_hcd_ppc_of_probe, |
280 | .remove = ehci_hcd_ppc_of_remove, | 277 | .remove = ehci_hcd_ppc_of_remove, |
281 | .shutdown = ehci_hcd_ppc_of_shutdown, | 278 | .shutdown = ehci_hcd_ppc_of_shutdown, |
diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c index 1dee33b9139e..64626a777d61 100644 --- a/drivers/usb/host/ehci-ps3.c +++ b/drivers/usb/host/ehci-ps3.c | |||
@@ -29,7 +29,7 @@ static int ps3_ehci_hc_reset(struct usb_hcd *hcd) | |||
29 | ehci->big_endian_mmio = 1; | 29 | ehci->big_endian_mmio = 1; |
30 | 30 | ||
31 | ehci->caps = hcd->regs; | 31 | ehci->caps = hcd->regs; |
32 | ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, | 32 | ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci, |
33 | &ehci->caps->hc_capbase)); | 33 | &ehci->caps->hc_capbase)); |
34 | 34 | ||
35 | dbg_hcs_params(ehci, "reset"); | 35 | dbg_hcs_params(ehci, "reset"); |
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 233c288e3f93..5d6bc624c961 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c | |||
@@ -315,7 +315,6 @@ qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
315 | int stopped; | 315 | int stopped; |
316 | unsigned count = 0; | 316 | unsigned count = 0; |
317 | u8 state; | 317 | u8 state; |
318 | const __le32 halt = HALT_BIT(ehci); | ||
319 | struct ehci_qh_hw *hw = qh->hw; | 318 | struct ehci_qh_hw *hw = qh->hw; |
320 | 319 | ||
321 | if (unlikely (list_empty (&qh->qtd_list))) | 320 | if (unlikely (list_empty (&qh->qtd_list))) |
@@ -422,7 +421,6 @@ qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
422 | && !(qtd->hw_alt_next | 421 | && !(qtd->hw_alt_next |
423 | & EHCI_LIST_END(ehci))) { | 422 | & EHCI_LIST_END(ehci))) { |
424 | stopped = 1; | 423 | stopped = 1; |
425 | goto halt; | ||
426 | } | 424 | } |
427 | 425 | ||
428 | /* stop scanning when we reach qtds the hc is using */ | 426 | /* stop scanning when we reach qtds the hc is using */ |
@@ -456,16 +454,6 @@ qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
456 | */ | 454 | */ |
457 | ehci_clear_tt_buffer(ehci, qh, urb, token); | 455 | ehci_clear_tt_buffer(ehci, qh, urb, token); |
458 | } | 456 | } |
459 | |||
460 | /* force halt for unlinked or blocked qh, so we'll | ||
461 | * patch the qh later and so that completions can't | ||
462 | * activate it while we "know" it's stopped. | ||
463 | */ | ||
464 | if ((halt & hw->hw_token) == 0) { | ||
465 | halt: | ||
466 | hw->hw_token |= halt; | ||
467 | wmb (); | ||
468 | } | ||
469 | } | 457 | } |
470 | 458 | ||
471 | /* unless we already know the urb's status, collect qtd status | 459 | /* unless we already know the urb's status, collect qtd status |
@@ -838,6 +826,7 @@ qh_make ( | |||
838 | is_input, 0, | 826 | is_input, 0, |
839 | hb_mult(maxp) * max_packet(maxp))); | 827 | hb_mult(maxp) * max_packet(maxp))); |
840 | qh->start = NO_FRAME; | 828 | qh->start = NO_FRAME; |
829 | qh->stamp = ehci->periodic_stamp; | ||
841 | 830 | ||
842 | if (urb->dev->speed == USB_SPEED_HIGH) { | 831 | if (urb->dev->speed == USB_SPEED_HIGH) { |
843 | qh->c_usecs = 0; | 832 | qh->c_usecs = 0; |
@@ -1107,22 +1096,24 @@ submit_async ( | |||
1107 | struct list_head *qtd_list, | 1096 | struct list_head *qtd_list, |
1108 | gfp_t mem_flags | 1097 | gfp_t mem_flags |
1109 | ) { | 1098 | ) { |
1110 | struct ehci_qtd *qtd; | ||
1111 | int epnum; | 1099 | int epnum; |
1112 | unsigned long flags; | 1100 | unsigned long flags; |
1113 | struct ehci_qh *qh = NULL; | 1101 | struct ehci_qh *qh = NULL; |
1114 | int rc; | 1102 | int rc; |
1115 | 1103 | ||
1116 | qtd = list_entry (qtd_list->next, struct ehci_qtd, qtd_list); | ||
1117 | epnum = urb->ep->desc.bEndpointAddress; | 1104 | epnum = urb->ep->desc.bEndpointAddress; |
1118 | 1105 | ||
1119 | #ifdef EHCI_URB_TRACE | 1106 | #ifdef EHCI_URB_TRACE |
1120 | ehci_dbg (ehci, | 1107 | { |
1121 | "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", | 1108 | struct ehci_qtd *qtd; |
1122 | __func__, urb->dev->devpath, urb, | 1109 | qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list); |
1123 | epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", | 1110 | ehci_dbg(ehci, |
1124 | urb->transfer_buffer_length, | 1111 | "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", |
1125 | qtd, urb->ep->hcpriv); | 1112 | __func__, urb->dev->devpath, urb, |
1113 | epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", | ||
1114 | urb->transfer_buffer_length, | ||
1115 | qtd, urb->ep->hcpriv); | ||
1116 | } | ||
1126 | #endif | 1117 | #endif |
1127 | 1118 | ||
1128 | spin_lock_irqsave (&ehci->lock, flags); | 1119 | spin_lock_irqsave (&ehci->lock, flags); |
@@ -1193,6 +1184,10 @@ static void end_unlink_async (struct ehci_hcd *ehci) | |||
1193 | ehci->reclaim = NULL; | 1184 | ehci->reclaim = NULL; |
1194 | start_unlink_async (ehci, next); | 1185 | start_unlink_async (ehci, next); |
1195 | } | 1186 | } |
1187 | |||
1188 | if (ehci->has_synopsys_hc_bug) | ||
1189 | ehci_writel(ehci, (u32) ehci->async->qh_dma, | ||
1190 | &ehci->regs->async_next); | ||
1196 | } | 1191 | } |
1197 | 1192 | ||
1198 | /* makes sure the async qh will become idle */ | 1193 | /* makes sure the async qh will become idle */ |
@@ -1257,24 +1252,27 @@ static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
1257 | 1252 | ||
1258 | static void scan_async (struct ehci_hcd *ehci) | 1253 | static void scan_async (struct ehci_hcd *ehci) |
1259 | { | 1254 | { |
1255 | bool stopped; | ||
1260 | struct ehci_qh *qh; | 1256 | struct ehci_qh *qh; |
1261 | enum ehci_timer_action action = TIMER_IO_WATCHDOG; | 1257 | enum ehci_timer_action action = TIMER_IO_WATCHDOG; |
1262 | 1258 | ||
1263 | ehci->stamp = ehci_readl(ehci, &ehci->regs->frame_index); | 1259 | ehci->stamp = ehci_readl(ehci, &ehci->regs->frame_index); |
1264 | timer_action_done (ehci, TIMER_ASYNC_SHRINK); | 1260 | timer_action_done (ehci, TIMER_ASYNC_SHRINK); |
1265 | rescan: | 1261 | rescan: |
1262 | stopped = !HC_IS_RUNNING(ehci_to_hcd(ehci)->state); | ||
1266 | qh = ehci->async->qh_next.qh; | 1263 | qh = ehci->async->qh_next.qh; |
1267 | if (likely (qh != NULL)) { | 1264 | if (likely (qh != NULL)) { |
1268 | do { | 1265 | do { |
1269 | /* clean any finished work for this qh */ | 1266 | /* clean any finished work for this qh */ |
1270 | if (!list_empty (&qh->qtd_list) | 1267 | if (!list_empty(&qh->qtd_list) && (stopped || |
1271 | && qh->stamp != ehci->stamp) { | 1268 | qh->stamp != ehci->stamp)) { |
1272 | int temp; | 1269 | int temp; |
1273 | 1270 | ||
1274 | /* unlinks could happen here; completion | 1271 | /* unlinks could happen here; completion |
1275 | * reporting drops the lock. rescan using | 1272 | * reporting drops the lock. rescan using |
1276 | * the latest schedule, but don't rescan | 1273 | * the latest schedule, but don't rescan |
1277 | * qhs we already finished (no looping). | 1274 | * qhs we already finished (no looping) |
1275 | * unless the controller is stopped. | ||
1278 | */ | 1276 | */ |
1279 | qh = qh_get (qh); | 1277 | qh = qh_get (qh); |
1280 | qh->stamp = ehci->stamp; | 1278 | qh->stamp = ehci->stamp; |
@@ -1295,9 +1293,9 @@ rescan: | |||
1295 | */ | 1293 | */ |
1296 | if (list_empty(&qh->qtd_list) | 1294 | if (list_empty(&qh->qtd_list) |
1297 | && qh->qh_state == QH_STATE_LINKED) { | 1295 | && qh->qh_state == QH_STATE_LINKED) { |
1298 | if (!ehci->reclaim | 1296 | if (!ehci->reclaim && (stopped || |
1299 | && ((ehci->stamp - qh->stamp) & 0x1fff) | 1297 | ((ehci->stamp - qh->stamp) & 0x1fff) |
1300 | >= (EHCI_SHRINK_FRAMES * 8)) | 1298 | >= EHCI_SHRINK_FRAMES * 8)) |
1301 | start_unlink_async(ehci, qh); | 1299 | start_unlink_async(ehci, qh); |
1302 | else | 1300 | else |
1303 | action = TIMER_ASYNC_SHRINK; | 1301 | action = TIMER_ASYNC_SHRINK; |
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c new file mode 100644 index 000000000000..e3374c8f7b3f --- /dev/null +++ b/drivers/usb/host/ehci-s5p.c | |||
@@ -0,0 +1,202 @@ | |||
1 | /* | ||
2 | * SAMSUNG S5P USB HOST EHCI Controller | ||
3 | * | ||
4 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | ||
5 | * Author: Jingoo Han <jg1.han@samsung.com> | ||
6 | * Author: Joonyoung Shim <jy0922.shim@samsung.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | #include <linux/clk.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <mach/regs-pmu.h> | ||
18 | #include <plat/cpu.h> | ||
19 | #include <plat/ehci.h> | ||
20 | #include <plat/usb-phy.h> | ||
21 | |||
22 | struct s5p_ehci_hcd { | ||
23 | struct device *dev; | ||
24 | struct usb_hcd *hcd; | ||
25 | struct clk *clk; | ||
26 | }; | ||
27 | |||
28 | static const struct hc_driver s5p_ehci_hc_driver = { | ||
29 | .description = hcd_name, | ||
30 | .product_desc = "S5P EHCI Host Controller", | ||
31 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
32 | |||
33 | .irq = ehci_irq, | ||
34 | .flags = HCD_MEMORY | HCD_USB2, | ||
35 | |||
36 | .reset = ehci_init, | ||
37 | .start = ehci_run, | ||
38 | .stop = ehci_stop, | ||
39 | .shutdown = ehci_shutdown, | ||
40 | |||
41 | .get_frame_number = ehci_get_frame, | ||
42 | |||
43 | .urb_enqueue = ehci_urb_enqueue, | ||
44 | .urb_dequeue = ehci_urb_dequeue, | ||
45 | .endpoint_disable = ehci_endpoint_disable, | ||
46 | .endpoint_reset = ehci_endpoint_reset, | ||
47 | |||
48 | .hub_status_data = ehci_hub_status_data, | ||
49 | .hub_control = ehci_hub_control, | ||
50 | .bus_suspend = ehci_bus_suspend, | ||
51 | .bus_resume = ehci_bus_resume, | ||
52 | |||
53 | .relinquish_port = ehci_relinquish_port, | ||
54 | .port_handed_over = ehci_port_handed_over, | ||
55 | |||
56 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
57 | }; | ||
58 | |||
59 | static int __devinit s5p_ehci_probe(struct platform_device *pdev) | ||
60 | { | ||
61 | struct s5p_ehci_platdata *pdata; | ||
62 | struct s5p_ehci_hcd *s5p_ehci; | ||
63 | struct usb_hcd *hcd; | ||
64 | struct ehci_hcd *ehci; | ||
65 | struct resource *res; | ||
66 | int irq; | ||
67 | int err; | ||
68 | |||
69 | pdata = pdev->dev.platform_data; | ||
70 | if (!pdata) { | ||
71 | dev_err(&pdev->dev, "No platform data defined\n"); | ||
72 | return -EINVAL; | ||
73 | } | ||
74 | |||
75 | s5p_ehci = kzalloc(sizeof(struct s5p_ehci_hcd), GFP_KERNEL); | ||
76 | if (!s5p_ehci) | ||
77 | return -ENOMEM; | ||
78 | |||
79 | s5p_ehci->dev = &pdev->dev; | ||
80 | |||
81 | hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev, | ||
82 | dev_name(&pdev->dev)); | ||
83 | if (!hcd) { | ||
84 | dev_err(&pdev->dev, "Unable to create HCD\n"); | ||
85 | err = -ENOMEM; | ||
86 | goto fail_hcd; | ||
87 | } | ||
88 | |||
89 | s5p_ehci->clk = clk_get(&pdev->dev, "usbhost"); | ||
90 | |||
91 | if (IS_ERR(s5p_ehci->clk)) { | ||
92 | dev_err(&pdev->dev, "Failed to get usbhost clock\n"); | ||
93 | err = PTR_ERR(s5p_ehci->clk); | ||
94 | goto fail_clk; | ||
95 | } | ||
96 | |||
97 | err = clk_enable(s5p_ehci->clk); | ||
98 | if (err) | ||
99 | goto fail_clken; | ||
100 | |||
101 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
102 | if (!res) { | ||
103 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | ||
104 | err = -ENXIO; | ||
105 | goto fail_io; | ||
106 | } | ||
107 | |||
108 | hcd->rsrc_start = res->start; | ||
109 | hcd->rsrc_len = resource_size(res); | ||
110 | hcd->regs = ioremap(res->start, resource_size(res)); | ||
111 | if (!hcd->regs) { | ||
112 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | ||
113 | err = -ENOMEM; | ||
114 | goto fail_io; | ||
115 | } | ||
116 | |||
117 | irq = platform_get_irq(pdev, 0); | ||
118 | if (!irq) { | ||
119 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | ||
120 | err = -ENODEV; | ||
121 | goto fail; | ||
122 | } | ||
123 | |||
124 | if (pdata->phy_init) | ||
125 | pdata->phy_init(pdev, S5P_USB_PHY_HOST); | ||
126 | |||
127 | ehci = hcd_to_ehci(hcd); | ||
128 | ehci->caps = hcd->regs; | ||
129 | ehci->regs = hcd->regs + | ||
130 | HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); | ||
131 | |||
132 | dbg_hcs_params(ehci, "reset"); | ||
133 | dbg_hcc_params(ehci, "reset"); | ||
134 | |||
135 | /* cache this readonly data; minimize chip reads */ | ||
136 | ehci->hcs_params = readl(&ehci->caps->hcs_params); | ||
137 | |||
138 | err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | ||
139 | if (err) { | ||
140 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | ||
141 | goto fail; | ||
142 | } | ||
143 | |||
144 | platform_set_drvdata(pdev, s5p_ehci); | ||
145 | |||
146 | return 0; | ||
147 | |||
148 | fail: | ||
149 | iounmap(hcd->regs); | ||
150 | fail_io: | ||
151 | clk_disable(s5p_ehci->clk); | ||
152 | fail_clken: | ||
153 | clk_put(s5p_ehci->clk); | ||
154 | fail_clk: | ||
155 | usb_put_hcd(hcd); | ||
156 | fail_hcd: | ||
157 | kfree(s5p_ehci); | ||
158 | return err; | ||
159 | } | ||
160 | |||
161 | static int __devexit s5p_ehci_remove(struct platform_device *pdev) | ||
162 | { | ||
163 | struct s5p_ehci_platdata *pdata = pdev->dev.platform_data; | ||
164 | struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev); | ||
165 | struct usb_hcd *hcd = s5p_ehci->hcd; | ||
166 | |||
167 | usb_remove_hcd(hcd); | ||
168 | |||
169 | if (pdata && pdata->phy_exit) | ||
170 | pdata->phy_exit(pdev, S5P_USB_PHY_HOST); | ||
171 | |||
172 | iounmap(hcd->regs); | ||
173 | |||
174 | clk_disable(s5p_ehci->clk); | ||
175 | clk_put(s5p_ehci->clk); | ||
176 | |||
177 | usb_put_hcd(hcd); | ||
178 | kfree(s5p_ehci); | ||
179 | |||
180 | return 0; | ||
181 | } | ||
182 | |||
183 | static void s5p_ehci_shutdown(struct platform_device *pdev) | ||
184 | { | ||
185 | struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev); | ||
186 | struct usb_hcd *hcd = s5p_ehci->hcd; | ||
187 | |||
188 | if (hcd->driver->shutdown) | ||
189 | hcd->driver->shutdown(hcd); | ||
190 | } | ||
191 | |||
192 | static struct platform_driver s5p_ehci_driver = { | ||
193 | .probe = s5p_ehci_probe, | ||
194 | .remove = __devexit_p(s5p_ehci_remove), | ||
195 | .shutdown = s5p_ehci_shutdown, | ||
196 | .driver = { | ||
197 | .name = "s5p-ehci", | ||
198 | .owner = THIS_MODULE, | ||
199 | } | ||
200 | }; | ||
201 | |||
202 | MODULE_ALIAS("platform:s5p-ehci"); | ||
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c index a92526d6e5ae..6c9fbe352f73 100644 --- a/drivers/usb/host/ehci-sched.c +++ b/drivers/usb/host/ehci-sched.c | |||
@@ -98,7 +98,14 @@ static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr) | |||
98 | */ | 98 | */ |
99 | *prev_p = *periodic_next_shadow(ehci, &here, | 99 | *prev_p = *periodic_next_shadow(ehci, &here, |
100 | Q_NEXT_TYPE(ehci, *hw_p)); | 100 | Q_NEXT_TYPE(ehci, *hw_p)); |
101 | *hw_p = *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p)); | 101 | |
102 | if (!ehci->use_dummy_qh || | ||
103 | *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p)) | ||
104 | != EHCI_LIST_END(ehci)) | ||
105 | *hw_p = *shadow_next_periodic(ehci, &here, | ||
106 | Q_NEXT_TYPE(ehci, *hw_p)); | ||
107 | else | ||
108 | *hw_p = ehci->dummy->qh_dma; | ||
102 | } | 109 | } |
103 | 110 | ||
104 | /* how many of the uframe's 125 usecs are allocated? */ | 111 | /* how many of the uframe's 125 usecs are allocated? */ |
@@ -464,8 +471,10 @@ static int enable_periodic (struct ehci_hcd *ehci) | |||
464 | */ | 471 | */ |
465 | status = handshake_on_error_set_halt(ehci, &ehci->regs->status, | 472 | status = handshake_on_error_set_halt(ehci, &ehci->regs->status, |
466 | STS_PSS, 0, 9 * 125); | 473 | STS_PSS, 0, 9 * 125); |
467 | if (status) | 474 | if (status) { |
475 | usb_hc_died(ehci_to_hcd(ehci)); | ||
468 | return status; | 476 | return status; |
477 | } | ||
469 | 478 | ||
470 | cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE; | 479 | cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE; |
471 | ehci_writel(ehci, cmd, &ehci->regs->command); | 480 | ehci_writel(ehci, cmd, &ehci->regs->command); |
@@ -503,8 +512,10 @@ static int disable_periodic (struct ehci_hcd *ehci) | |||
503 | */ | 512 | */ |
504 | status = handshake_on_error_set_halt(ehci, &ehci->regs->status, | 513 | status = handshake_on_error_set_halt(ehci, &ehci->regs->status, |
505 | STS_PSS, STS_PSS, 9 * 125); | 514 | STS_PSS, STS_PSS, 9 * 125); |
506 | if (status) | 515 | if (status) { |
516 | usb_hc_died(ehci_to_hcd(ehci)); | ||
507 | return status; | 517 | return status; |
518 | } | ||
508 | 519 | ||
509 | cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE; | 520 | cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE; |
510 | ehci_writel(ehci, cmd, &ehci->regs->command); | 521 | ehci_writel(ehci, cmd, &ehci->regs->command); |
@@ -1041,8 +1052,6 @@ iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream) | |||
1041 | * not like a QH -- no persistent state (toggle, halt) | 1052 | * not like a QH -- no persistent state (toggle, halt) |
1042 | */ | 1053 | */ |
1043 | if (stream->refcount == 1) { | 1054 | if (stream->refcount == 1) { |
1044 | int is_in; | ||
1045 | |||
1046 | // BUG_ON (!list_empty(&stream->td_list)); | 1055 | // BUG_ON (!list_empty(&stream->td_list)); |
1047 | 1056 | ||
1048 | while (!list_empty (&stream->free_list)) { | 1057 | while (!list_empty (&stream->free_list)) { |
@@ -1069,7 +1078,6 @@ iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream) | |||
1069 | } | 1078 | } |
1070 | } | 1079 | } |
1071 | 1080 | ||
1072 | is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0; | ||
1073 | stream->bEndpointAddress &= 0x0f; | 1081 | stream->bEndpointAddress &= 0x0f; |
1074 | if (stream->ep) | 1082 | if (stream->ep) |
1075 | stream->ep->hcpriv = NULL; | 1083 | stream->ep->hcpriv = NULL; |
@@ -1609,6 +1617,12 @@ itd_link_urb ( | |||
1609 | urb->interval, | 1617 | urb->interval, |
1610 | next_uframe >> 3, next_uframe & 0x7); | 1618 | next_uframe >> 3, next_uframe & 0x7); |
1611 | } | 1619 | } |
1620 | |||
1621 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | ||
1622 | if (ehci->amd_pll_fix == 1) | ||
1623 | usb_amd_quirk_pll_disable(); | ||
1624 | } | ||
1625 | |||
1612 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; | 1626 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
1613 | 1627 | ||
1614 | /* fill iTDs uframe by uframe */ | 1628 | /* fill iTDs uframe by uframe */ |
@@ -1733,6 +1747,11 @@ itd_complete ( | |||
1733 | (void) disable_periodic(ehci); | 1747 | (void) disable_periodic(ehci); |
1734 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; | 1748 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
1735 | 1749 | ||
1750 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | ||
1751 | if (ehci->amd_pll_fix == 1) | ||
1752 | usb_amd_quirk_pll_enable(); | ||
1753 | } | ||
1754 | |||
1736 | if (unlikely(list_is_singular(&stream->td_list))) { | 1755 | if (unlikely(list_is_singular(&stream->td_list))) { |
1737 | ehci_to_hcd(ehci)->self.bandwidth_allocated | 1756 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
1738 | -= stream->bandwidth; | 1757 | -= stream->bandwidth; |
@@ -2018,6 +2037,12 @@ sitd_link_urb ( | |||
2018 | (next_uframe >> 3) & (ehci->periodic_size - 1), | 2037 | (next_uframe >> 3) & (ehci->periodic_size - 1), |
2019 | stream->interval, hc32_to_cpu(ehci, stream->splits)); | 2038 | stream->interval, hc32_to_cpu(ehci, stream->splits)); |
2020 | } | 2039 | } |
2040 | |||
2041 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | ||
2042 | if (ehci->amd_pll_fix == 1) | ||
2043 | usb_amd_quirk_pll_disable(); | ||
2044 | } | ||
2045 | |||
2021 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; | 2046 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
2022 | 2047 | ||
2023 | /* fill sITDs frame by frame */ | 2048 | /* fill sITDs frame by frame */ |
@@ -2118,6 +2143,11 @@ sitd_complete ( | |||
2118 | (void) disable_periodic(ehci); | 2143 | (void) disable_periodic(ehci); |
2119 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; | 2144 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
2120 | 2145 | ||
2146 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | ||
2147 | if (ehci->amd_pll_fix == 1) | ||
2148 | usb_amd_quirk_pll_enable(); | ||
2149 | } | ||
2150 | |||
2121 | if (list_is_singular(&stream->td_list)) { | 2151 | if (list_is_singular(&stream->td_list)) { |
2122 | ehci_to_hcd(ehci)->self.bandwidth_allocated | 2152 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
2123 | -= stream->bandwidth; | 2153 | -= stream->bandwidth; |
@@ -2261,6 +2291,7 @@ scan_periodic (struct ehci_hcd *ehci) | |||
2261 | } | 2291 | } |
2262 | clock &= mod - 1; | 2292 | clock &= mod - 1; |
2263 | clock_frame = clock >> 3; | 2293 | clock_frame = clock >> 3; |
2294 | ++ehci->periodic_stamp; | ||
2264 | 2295 | ||
2265 | for (;;) { | 2296 | for (;;) { |
2266 | union ehci_shadow q, *q_p; | 2297 | union ehci_shadow q, *q_p; |
@@ -2289,10 +2320,14 @@ restart: | |||
2289 | temp.qh = qh_get (q.qh); | 2320 | temp.qh = qh_get (q.qh); |
2290 | type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next); | 2321 | type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next); |
2291 | q = q.qh->qh_next; | 2322 | q = q.qh->qh_next; |
2292 | modified = qh_completions (ehci, temp.qh); | 2323 | if (temp.qh->stamp != ehci->periodic_stamp) { |
2293 | if (unlikely(list_empty(&temp.qh->qtd_list) || | 2324 | modified = qh_completions(ehci, temp.qh); |
2294 | temp.qh->needs_rescan)) | 2325 | if (!modified) |
2295 | intr_deschedule (ehci, temp.qh); | 2326 | temp.qh->stamp = ehci->periodic_stamp; |
2327 | if (unlikely(list_empty(&temp.qh->qtd_list) || | ||
2328 | temp.qh->needs_rescan)) | ||
2329 | intr_deschedule(ehci, temp.qh); | ||
2330 | } | ||
2296 | qh_put (temp.qh); | 2331 | qh_put (temp.qh); |
2297 | break; | 2332 | break; |
2298 | case Q_TYPE_FSTN: | 2333 | case Q_TYPE_FSTN: |
@@ -2335,7 +2370,11 @@ restart: | |||
2335 | * pointer for much longer, if at all. | 2370 | * pointer for much longer, if at all. |
2336 | */ | 2371 | */ |
2337 | *q_p = q.itd->itd_next; | 2372 | *q_p = q.itd->itd_next; |
2338 | *hw_p = q.itd->hw_next; | 2373 | if (!ehci->use_dummy_qh || |
2374 | q.itd->hw_next != EHCI_LIST_END(ehci)) | ||
2375 | *hw_p = q.itd->hw_next; | ||
2376 | else | ||
2377 | *hw_p = ehci->dummy->qh_dma; | ||
2339 | type = Q_NEXT_TYPE(ehci, q.itd->hw_next); | 2378 | type = Q_NEXT_TYPE(ehci, q.itd->hw_next); |
2340 | wmb(); | 2379 | wmb(); |
2341 | modified = itd_complete (ehci, q.itd); | 2380 | modified = itd_complete (ehci, q.itd); |
@@ -2368,7 +2407,11 @@ restart: | |||
2368 | * URB completion. | 2407 | * URB completion. |
2369 | */ | 2408 | */ |
2370 | *q_p = q.sitd->sitd_next; | 2409 | *q_p = q.sitd->sitd_next; |
2371 | *hw_p = q.sitd->hw_next; | 2410 | if (!ehci->use_dummy_qh || |
2411 | q.sitd->hw_next != EHCI_LIST_END(ehci)) | ||
2412 | *hw_p = q.sitd->hw_next; | ||
2413 | else | ||
2414 | *hw_p = ehci->dummy->qh_dma; | ||
2372 | type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); | 2415 | type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); |
2373 | wmb(); | 2416 | wmb(); |
2374 | modified = sitd_complete (ehci, q.sitd); | 2417 | modified = sitd_complete (ehci, q.sitd); |
@@ -2426,6 +2469,7 @@ restart: | |||
2426 | if (ehci->clock_frame != clock_frame) { | 2469 | if (ehci->clock_frame != clock_frame) { |
2427 | free_cached_lists(ehci); | 2470 | free_cached_lists(ehci); |
2428 | ehci->clock_frame = clock_frame; | 2471 | ehci->clock_frame = clock_frame; |
2472 | ++ehci->periodic_stamp; | ||
2429 | } | 2473 | } |
2430 | } else { | 2474 | } else { |
2431 | now_uframe++; | 2475 | now_uframe++; |
diff --git a/drivers/usb/host/ehci-sh.c b/drivers/usb/host/ehci-sh.c new file mode 100644 index 000000000000..86a95bb80a61 --- /dev/null +++ b/drivers/usb/host/ehci-sh.c | |||
@@ -0,0 +1,243 @@ | |||
1 | /* | ||
2 | * SuperH EHCI host controller driver | ||
3 | * | ||
4 | * Copyright (C) 2010 Paul Mundt | ||
5 | * | ||
6 | * Based on ohci-sh.c and ehci-atmel.c. | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file "COPYING" in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | #include <linux/platform_device.h> | ||
13 | #include <linux/clk.h> | ||
14 | |||
15 | struct ehci_sh_priv { | ||
16 | struct clk *iclk, *fclk; | ||
17 | struct usb_hcd *hcd; | ||
18 | }; | ||
19 | |||
20 | static int ehci_sh_reset(struct usb_hcd *hcd) | ||
21 | { | ||
22 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
23 | int ret; | ||
24 | |||
25 | ehci->caps = hcd->regs; | ||
26 | ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci, | ||
27 | &ehci->caps->hc_capbase)); | ||
28 | |||
29 | dbg_hcs_params(ehci, "reset"); | ||
30 | dbg_hcc_params(ehci, "reset"); | ||
31 | |||
32 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
33 | |||
34 | ret = ehci_halt(ehci); | ||
35 | if (unlikely(ret)) | ||
36 | return ret; | ||
37 | |||
38 | ret = ehci_init(hcd); | ||
39 | if (unlikely(ret)) | ||
40 | return ret; | ||
41 | |||
42 | ehci->sbrn = 0x20; | ||
43 | |||
44 | ehci_reset(ehci); | ||
45 | ehci_port_power(ehci, 0); | ||
46 | |||
47 | return ret; | ||
48 | } | ||
49 | |||
50 | static const struct hc_driver ehci_sh_hc_driver = { | ||
51 | .description = hcd_name, | ||
52 | .product_desc = "SuperH EHCI", | ||
53 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
54 | |||
55 | /* | ||
56 | * generic hardware linkage | ||
57 | */ | ||
58 | .irq = ehci_irq, | ||
59 | .flags = HCD_USB2 | HCD_MEMORY, | ||
60 | |||
61 | /* | ||
62 | * basic lifecycle operations | ||
63 | */ | ||
64 | .reset = ehci_sh_reset, | ||
65 | .start = ehci_run, | ||
66 | .stop = ehci_stop, | ||
67 | .shutdown = ehci_shutdown, | ||
68 | |||
69 | /* | ||
70 | * managing i/o requests and associated device resources | ||
71 | */ | ||
72 | .urb_enqueue = ehci_urb_enqueue, | ||
73 | .urb_dequeue = ehci_urb_dequeue, | ||
74 | .endpoint_disable = ehci_endpoint_disable, | ||
75 | .endpoint_reset = ehci_endpoint_reset, | ||
76 | |||
77 | /* | ||
78 | * scheduling support | ||
79 | */ | ||
80 | .get_frame_number = ehci_get_frame, | ||
81 | |||
82 | /* | ||
83 | * root hub support | ||
84 | */ | ||
85 | .hub_status_data = ehci_hub_status_data, | ||
86 | .hub_control = ehci_hub_control, | ||
87 | |||
88 | #ifdef CONFIG_PM | ||
89 | .bus_suspend = ehci_bus_suspend, | ||
90 | .bus_resume = ehci_bus_resume, | ||
91 | #endif | ||
92 | |||
93 | .relinquish_port = ehci_relinquish_port, | ||
94 | .port_handed_over = ehci_port_handed_over, | ||
95 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
96 | }; | ||
97 | |||
98 | static int ehci_hcd_sh_probe(struct platform_device *pdev) | ||
99 | { | ||
100 | const struct hc_driver *driver = &ehci_sh_hc_driver; | ||
101 | struct resource *res; | ||
102 | struct ehci_sh_priv *priv; | ||
103 | struct usb_hcd *hcd; | ||
104 | int irq, ret; | ||
105 | |||
106 | if (usb_disabled()) | ||
107 | return -ENODEV; | ||
108 | |||
109 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
110 | if (!res) { | ||
111 | dev_err(&pdev->dev, | ||
112 | "Found HC with no register addr. Check %s setup!\n", | ||
113 | dev_name(&pdev->dev)); | ||
114 | ret = -ENODEV; | ||
115 | goto fail_create_hcd; | ||
116 | } | ||
117 | |||
118 | irq = platform_get_irq(pdev, 0); | ||
119 | if (irq <= 0) { | ||
120 | dev_err(&pdev->dev, | ||
121 | "Found HC with no IRQ. Check %s setup!\n", | ||
122 | dev_name(&pdev->dev)); | ||
123 | ret = -ENODEV; | ||
124 | goto fail_create_hcd; | ||
125 | } | ||
126 | |||
127 | /* initialize hcd */ | ||
128 | hcd = usb_create_hcd(&ehci_sh_hc_driver, &pdev->dev, | ||
129 | dev_name(&pdev->dev)); | ||
130 | if (!hcd) { | ||
131 | ret = -ENOMEM; | ||
132 | goto fail_create_hcd; | ||
133 | } | ||
134 | |||
135 | hcd->rsrc_start = res->start; | ||
136 | hcd->rsrc_len = resource_size(res); | ||
137 | |||
138 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, | ||
139 | driver->description)) { | ||
140 | dev_dbg(&pdev->dev, "controller already in use\n"); | ||
141 | ret = -EBUSY; | ||
142 | goto fail_request_resource; | ||
143 | } | ||
144 | |||
145 | hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); | ||
146 | if (hcd->regs == NULL) { | ||
147 | dev_dbg(&pdev->dev, "error mapping memory\n"); | ||
148 | ret = -ENXIO; | ||
149 | goto fail_ioremap; | ||
150 | } | ||
151 | |||
152 | priv = kmalloc(sizeof(struct ehci_sh_priv), GFP_KERNEL); | ||
153 | if (!priv) { | ||
154 | dev_dbg(&pdev->dev, "error allocating priv data\n"); | ||
155 | ret = -ENOMEM; | ||
156 | goto fail_alloc; | ||
157 | } | ||
158 | |||
159 | /* These are optional, we don't care if they fail */ | ||
160 | priv->fclk = clk_get(&pdev->dev, "usb_fck"); | ||
161 | if (IS_ERR(priv->fclk)) | ||
162 | priv->fclk = NULL; | ||
163 | |||
164 | priv->iclk = clk_get(&pdev->dev, "usb_ick"); | ||
165 | if (IS_ERR(priv->iclk)) | ||
166 | priv->iclk = NULL; | ||
167 | |||
168 | clk_enable(priv->fclk); | ||
169 | clk_enable(priv->iclk); | ||
170 | |||
171 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | ||
172 | if (ret != 0) { | ||
173 | dev_err(&pdev->dev, "Failed to add hcd"); | ||
174 | goto fail_add_hcd; | ||
175 | } | ||
176 | |||
177 | priv->hcd = hcd; | ||
178 | platform_set_drvdata(pdev, priv); | ||
179 | |||
180 | return ret; | ||
181 | |||
182 | fail_add_hcd: | ||
183 | clk_disable(priv->iclk); | ||
184 | clk_disable(priv->fclk); | ||
185 | |||
186 | clk_put(priv->iclk); | ||
187 | clk_put(priv->fclk); | ||
188 | |||
189 | kfree(priv); | ||
190 | fail_alloc: | ||
191 | iounmap(hcd->regs); | ||
192 | fail_ioremap: | ||
193 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
194 | fail_request_resource: | ||
195 | usb_put_hcd(hcd); | ||
196 | fail_create_hcd: | ||
197 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret); | ||
198 | |||
199 | return ret; | ||
200 | } | ||
201 | |||
202 | static int __exit ehci_hcd_sh_remove(struct platform_device *pdev) | ||
203 | { | ||
204 | struct ehci_sh_priv *priv = platform_get_drvdata(pdev); | ||
205 | struct usb_hcd *hcd = priv->hcd; | ||
206 | |||
207 | usb_remove_hcd(hcd); | ||
208 | iounmap(hcd->regs); | ||
209 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
210 | usb_put_hcd(hcd); | ||
211 | platform_set_drvdata(pdev, NULL); | ||
212 | |||
213 | clk_disable(priv->fclk); | ||
214 | clk_disable(priv->iclk); | ||
215 | |||
216 | clk_put(priv->fclk); | ||
217 | clk_put(priv->iclk); | ||
218 | |||
219 | kfree(priv); | ||
220 | |||
221 | return 0; | ||
222 | } | ||
223 | |||
224 | static void ehci_hcd_sh_shutdown(struct platform_device *pdev) | ||
225 | { | ||
226 | struct ehci_sh_priv *priv = platform_get_drvdata(pdev); | ||
227 | struct usb_hcd *hcd = priv->hcd; | ||
228 | |||
229 | if (hcd->driver->shutdown) | ||
230 | hcd->driver->shutdown(hcd); | ||
231 | } | ||
232 | |||
233 | static struct platform_driver ehci_hcd_sh_driver = { | ||
234 | .probe = ehci_hcd_sh_probe, | ||
235 | .remove = __exit_p(ehci_hcd_sh_remove), | ||
236 | .shutdown = ehci_hcd_sh_shutdown, | ||
237 | .driver = { | ||
238 | .name = "sh_ehci", | ||
239 | .owner = THIS_MODULE, | ||
240 | }, | ||
241 | }; | ||
242 | |||
243 | MODULE_ALIAS("platform:sh_ehci"); | ||
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c new file mode 100644 index 000000000000..dbf1e4ef3c17 --- /dev/null +++ b/drivers/usb/host/ehci-spear.c | |||
@@ -0,0 +1,212 @@ | |||
1 | /* | ||
2 | * Driver for EHCI HCD on SPEAR SOC | ||
3 | * | ||
4 | * Copyright (C) 2010 ST Micro Electronics, | ||
5 | * Deepak Sikri <deepak.sikri@st.com> | ||
6 | * | ||
7 | * Based on various ehci-*.c drivers | ||
8 | * | ||
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file COPYING in the main directory of this archive for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <linux/platform_device.h> | ||
15 | #include <linux/clk.h> | ||
16 | |||
17 | struct spear_ehci { | ||
18 | struct ehci_hcd ehci; | ||
19 | struct clk *clk; | ||
20 | }; | ||
21 | |||
22 | #define to_spear_ehci(hcd) (struct spear_ehci *)hcd_to_ehci(hcd) | ||
23 | |||
24 | static void spear_start_ehci(struct spear_ehci *ehci) | ||
25 | { | ||
26 | clk_enable(ehci->clk); | ||
27 | } | ||
28 | |||
29 | static void spear_stop_ehci(struct spear_ehci *ehci) | ||
30 | { | ||
31 | clk_disable(ehci->clk); | ||
32 | } | ||
33 | |||
34 | static int ehci_spear_setup(struct usb_hcd *hcd) | ||
35 | { | ||
36 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
37 | int retval = 0; | ||
38 | |||
39 | /* registers start at offset 0x0 */ | ||
40 | ehci->caps = hcd->regs; | ||
41 | ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci, | ||
42 | &ehci->caps->hc_capbase)); | ||
43 | /* cache this readonly data; minimize chip reads */ | ||
44 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | ||
45 | retval = ehci_halt(ehci); | ||
46 | if (retval) | ||
47 | return retval; | ||
48 | |||
49 | retval = ehci_init(hcd); | ||
50 | if (retval) | ||
51 | return retval; | ||
52 | |||
53 | ehci_reset(ehci); | ||
54 | ehci_port_power(ehci, 0); | ||
55 | |||
56 | return retval; | ||
57 | } | ||
58 | |||
59 | static const struct hc_driver ehci_spear_hc_driver = { | ||
60 | .description = hcd_name, | ||
61 | .product_desc = "SPEAr EHCI", | ||
62 | .hcd_priv_size = sizeof(struct spear_ehci), | ||
63 | |||
64 | /* generic hardware linkage */ | ||
65 | .irq = ehci_irq, | ||
66 | .flags = HCD_MEMORY | HCD_USB2, | ||
67 | |||
68 | /* basic lifecycle operations */ | ||
69 | .reset = ehci_spear_setup, | ||
70 | .start = ehci_run, | ||
71 | .stop = ehci_stop, | ||
72 | .shutdown = ehci_shutdown, | ||
73 | |||
74 | /* managing i/o requests and associated device resources */ | ||
75 | .urb_enqueue = ehci_urb_enqueue, | ||
76 | .urb_dequeue = ehci_urb_dequeue, | ||
77 | .endpoint_disable = ehci_endpoint_disable, | ||
78 | .endpoint_reset = ehci_endpoint_reset, | ||
79 | |||
80 | /* scheduling support */ | ||
81 | .get_frame_number = ehci_get_frame, | ||
82 | |||
83 | /* root hub support */ | ||
84 | .hub_status_data = ehci_hub_status_data, | ||
85 | .hub_control = ehci_hub_control, | ||
86 | .bus_suspend = ehci_bus_suspend, | ||
87 | .bus_resume = ehci_bus_resume, | ||
88 | .relinquish_port = ehci_relinquish_port, | ||
89 | .port_handed_over = ehci_port_handed_over, | ||
90 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
91 | }; | ||
92 | |||
93 | static int spear_ehci_hcd_drv_probe(struct platform_device *pdev) | ||
94 | { | ||
95 | struct usb_hcd *hcd ; | ||
96 | struct spear_ehci *ehci; | ||
97 | struct resource *res; | ||
98 | struct clk *usbh_clk; | ||
99 | const struct hc_driver *driver = &ehci_spear_hc_driver; | ||
100 | int *pdata = pdev->dev.platform_data; | ||
101 | int irq, retval; | ||
102 | char clk_name[20] = "usbh_clk"; | ||
103 | |||
104 | if (pdata == NULL) | ||
105 | return -EFAULT; | ||
106 | |||
107 | if (usb_disabled()) | ||
108 | return -ENODEV; | ||
109 | |||
110 | irq = platform_get_irq(pdev, 0); | ||
111 | if (irq < 0) { | ||
112 | retval = irq; | ||
113 | goto fail_irq_get; | ||
114 | } | ||
115 | |||
116 | if (*pdata >= 0) | ||
117 | sprintf(clk_name, "usbh.%01d_clk", *pdata); | ||
118 | |||
119 | usbh_clk = clk_get(NULL, clk_name); | ||
120 | if (IS_ERR(usbh_clk)) { | ||
121 | dev_err(&pdev->dev, "Error getting interface clock\n"); | ||
122 | retval = PTR_ERR(usbh_clk); | ||
123 | goto fail_get_usbh_clk; | ||
124 | } | ||
125 | |||
126 | hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); | ||
127 | if (!hcd) { | ||
128 | retval = -ENOMEM; | ||
129 | goto fail_create_hcd; | ||
130 | } | ||
131 | |||
132 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
133 | if (!res) { | ||
134 | retval = -ENODEV; | ||
135 | goto fail_request_resource; | ||
136 | } | ||
137 | |||
138 | hcd->rsrc_start = res->start; | ||
139 | hcd->rsrc_len = resource_size(res); | ||
140 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, | ||
141 | driver->description)) { | ||
142 | retval = -EBUSY; | ||
143 | goto fail_request_resource; | ||
144 | } | ||
145 | |||
146 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
147 | if (hcd->regs == NULL) { | ||
148 | dev_dbg(&pdev->dev, "error mapping memory\n"); | ||
149 | retval = -ENOMEM; | ||
150 | goto fail_ioremap; | ||
151 | } | ||
152 | |||
153 | ehci = (struct spear_ehci *)hcd_to_ehci(hcd); | ||
154 | ehci->clk = usbh_clk; | ||
155 | |||
156 | spear_start_ehci(ehci); | ||
157 | retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_DISABLED); | ||
158 | if (retval) | ||
159 | goto fail_add_hcd; | ||
160 | |||
161 | return retval; | ||
162 | |||
163 | fail_add_hcd: | ||
164 | spear_stop_ehci(ehci); | ||
165 | iounmap(hcd->regs); | ||
166 | fail_ioremap: | ||
167 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
168 | fail_request_resource: | ||
169 | usb_put_hcd(hcd); | ||
170 | fail_create_hcd: | ||
171 | clk_put(usbh_clk); | ||
172 | fail_get_usbh_clk: | ||
173 | fail_irq_get: | ||
174 | dev_err(&pdev->dev, "init fail, %d\n", retval); | ||
175 | |||
176 | return retval ; | ||
177 | } | ||
178 | |||
179 | static int spear_ehci_hcd_drv_remove(struct platform_device *pdev) | ||
180 | { | ||
181 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
182 | struct spear_ehci *ehci_p = to_spear_ehci(hcd); | ||
183 | |||
184 | if (!hcd) | ||
185 | return 0; | ||
186 | if (in_interrupt()) | ||
187 | BUG(); | ||
188 | usb_remove_hcd(hcd); | ||
189 | |||
190 | if (ehci_p->clk) | ||
191 | spear_stop_ehci(ehci_p); | ||
192 | iounmap(hcd->regs); | ||
193 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
194 | usb_put_hcd(hcd); | ||
195 | |||
196 | if (ehci_p->clk) | ||
197 | clk_put(ehci_p->clk); | ||
198 | |||
199 | return 0; | ||
200 | } | ||
201 | |||
202 | static struct platform_driver spear_ehci_hcd_driver = { | ||
203 | .probe = spear_ehci_hcd_drv_probe, | ||
204 | .remove = spear_ehci_hcd_drv_remove, | ||
205 | .shutdown = usb_hcd_platform_shutdown, | ||
206 | .driver = { | ||
207 | .name = "spear-ehci", | ||
208 | .bus = &platform_bus_type | ||
209 | } | ||
210 | }; | ||
211 | |||
212 | MODULE_ALIAS("platform:spear-ehci"); | ||
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c new file mode 100644 index 000000000000..02b2bfd49a10 --- /dev/null +++ b/drivers/usb/host/ehci-tegra.c | |||
@@ -0,0 +1,787 @@ | |||
1 | /* | ||
2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs | ||
3 | * | ||
4 | * Copyright (C) 2010 Google, Inc. | ||
5 | * Copyright (C) 2009 NVIDIA Corporation | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | #include <linux/clk.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/platform_data/tegra_usb.h> | ||
22 | #include <linux/irq.h> | ||
23 | #include <linux/usb/otg.h> | ||
24 | #include <mach/usb_phy.h> | ||
25 | |||
26 | #define TEGRA_USB_DMA_ALIGN 32 | ||
27 | |||
28 | struct tegra_ehci_hcd { | ||
29 | struct ehci_hcd *ehci; | ||
30 | struct tegra_usb_phy *phy; | ||
31 | struct clk *clk; | ||
32 | struct clk *emc_clk; | ||
33 | struct otg_transceiver *transceiver; | ||
34 | int host_resumed; | ||
35 | int bus_suspended; | ||
36 | int port_resuming; | ||
37 | int power_down_on_bus_suspend; | ||
38 | enum tegra_usb_phy_port_speed port_speed; | ||
39 | }; | ||
40 | |||
41 | static void tegra_ehci_power_up(struct usb_hcd *hcd) | ||
42 | { | ||
43 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
44 | |||
45 | clk_enable(tegra->emc_clk); | ||
46 | clk_enable(tegra->clk); | ||
47 | tegra_usb_phy_power_on(tegra->phy); | ||
48 | tegra->host_resumed = 1; | ||
49 | } | ||
50 | |||
51 | static void tegra_ehci_power_down(struct usb_hcd *hcd) | ||
52 | { | ||
53 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
54 | |||
55 | tegra->host_resumed = 0; | ||
56 | tegra_usb_phy_power_off(tegra->phy); | ||
57 | clk_disable(tegra->clk); | ||
58 | clk_disable(tegra->emc_clk); | ||
59 | } | ||
60 | |||
61 | static int tegra_ehci_internal_port_reset( | ||
62 | struct ehci_hcd *ehci, | ||
63 | u32 __iomem *portsc_reg | ||
64 | ) | ||
65 | { | ||
66 | u32 temp; | ||
67 | unsigned long flags; | ||
68 | int retval = 0; | ||
69 | int i, tries; | ||
70 | u32 saved_usbintr; | ||
71 | |||
72 | spin_lock_irqsave(&ehci->lock, flags); | ||
73 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); | ||
74 | /* disable USB interrupt */ | ||
75 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | ||
76 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
77 | |||
78 | /* | ||
79 | * Here we have to do Port Reset at most twice for | ||
80 | * Port Enable bit to be set. | ||
81 | */ | ||
82 | for (i = 0; i < 2; i++) { | ||
83 | temp = ehci_readl(ehci, portsc_reg); | ||
84 | temp |= PORT_RESET; | ||
85 | ehci_writel(ehci, temp, portsc_reg); | ||
86 | mdelay(10); | ||
87 | temp &= ~PORT_RESET; | ||
88 | ehci_writel(ehci, temp, portsc_reg); | ||
89 | mdelay(1); | ||
90 | tries = 100; | ||
91 | do { | ||
92 | mdelay(1); | ||
93 | /* | ||
94 | * Up to this point, Port Enable bit is | ||
95 | * expected to be set after 2 ms waiting. | ||
96 | * USB1 usually takes extra 45 ms, for safety, | ||
97 | * we take 100 ms as timeout. | ||
98 | */ | ||
99 | temp = ehci_readl(ehci, portsc_reg); | ||
100 | } while (!(temp & PORT_PE) && tries--); | ||
101 | if (temp & PORT_PE) | ||
102 | break; | ||
103 | } | ||
104 | if (i == 2) | ||
105 | retval = -ETIMEDOUT; | ||
106 | |||
107 | /* | ||
108 | * Clear Connect Status Change bit if it's set. | ||
109 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. | ||
110 | */ | ||
111 | if (temp & PORT_CSC) | ||
112 | ehci_writel(ehci, PORT_CSC, portsc_reg); | ||
113 | |||
114 | /* | ||
115 | * Write to clear any interrupt status bits that might be set | ||
116 | * during port reset. | ||
117 | */ | ||
118 | temp = ehci_readl(ehci, &ehci->regs->status); | ||
119 | ehci_writel(ehci, temp, &ehci->regs->status); | ||
120 | |||
121 | /* restore original interrupt enable bits */ | ||
122 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); | ||
123 | return retval; | ||
124 | } | ||
125 | |||
126 | static int tegra_ehci_hub_control( | ||
127 | struct usb_hcd *hcd, | ||
128 | u16 typeReq, | ||
129 | u16 wValue, | ||
130 | u16 wIndex, | ||
131 | char *buf, | ||
132 | u16 wLength | ||
133 | ) | ||
134 | { | ||
135 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
136 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
137 | u32 __iomem *status_reg; | ||
138 | u32 temp; | ||
139 | unsigned long flags; | ||
140 | int retval = 0; | ||
141 | |||
142 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; | ||
143 | |||
144 | spin_lock_irqsave(&ehci->lock, flags); | ||
145 | |||
146 | /* | ||
147 | * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits | ||
148 | * that are write on clear, by writing back the register read value, so | ||
149 | * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits | ||
150 | */ | ||
151 | if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) { | ||
152 | temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS; | ||
153 | ehci_writel(ehci, temp & ~PORT_PE, status_reg); | ||
154 | goto done; | ||
155 | } | ||
156 | |||
157 | else if (typeReq == GetPortStatus) { | ||
158 | temp = ehci_readl(ehci, status_reg); | ||
159 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { | ||
160 | /* Resume completed, re-enable disconnect detection */ | ||
161 | tegra->port_resuming = 0; | ||
162 | tegra_usb_phy_postresume(tegra->phy); | ||
163 | } | ||
164 | } | ||
165 | |||
166 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { | ||
167 | temp = ehci_readl(ehci, status_reg); | ||
168 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { | ||
169 | retval = -EPIPE; | ||
170 | goto done; | ||
171 | } | ||
172 | |||
173 | temp &= ~PORT_WKCONN_E; | ||
174 | temp |= PORT_WKDISC_E | PORT_WKOC_E; | ||
175 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); | ||
176 | |||
177 | /* | ||
178 | * If a transaction is in progress, there may be a delay in | ||
179 | * suspending the port. Poll until the port is suspended. | ||
180 | */ | ||
181 | if (handshake(ehci, status_reg, PORT_SUSPEND, | ||
182 | PORT_SUSPEND, 5000)) | ||
183 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | ||
184 | |||
185 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); | ||
186 | goto done; | ||
187 | } | ||
188 | |||
189 | /* For USB1 port we need to issue Port Reset twice internally */ | ||
190 | if (tegra->phy->instance == 0 && | ||
191 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { | ||
192 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
193 | return tegra_ehci_internal_port_reset(ehci, status_reg); | ||
194 | } | ||
195 | |||
196 | /* | ||
197 | * Tegra host controller will time the resume operation to clear the bit | ||
198 | * when the port control state switches to HS or FS Idle. This behavior | ||
199 | * is different from EHCI where the host controller driver is required | ||
200 | * to set this bit to a zero after the resume duration is timed in the | ||
201 | * driver. | ||
202 | */ | ||
203 | else if (typeReq == ClearPortFeature && | ||
204 | wValue == USB_PORT_FEAT_SUSPEND) { | ||
205 | temp = ehci_readl(ehci, status_reg); | ||
206 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { | ||
207 | retval = -EPIPE; | ||
208 | goto done; | ||
209 | } | ||
210 | |||
211 | if (!(temp & PORT_SUSPEND)) | ||
212 | goto done; | ||
213 | |||
214 | /* Disable disconnect detection during port resume */ | ||
215 | tegra_usb_phy_preresume(tegra->phy); | ||
216 | |||
217 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); | ||
218 | |||
219 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | ||
220 | /* start resume signalling */ | ||
221 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); | ||
222 | |||
223 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
224 | msleep(20); | ||
225 | spin_lock_irqsave(&ehci->lock, flags); | ||
226 | |||
227 | /* Poll until the controller clears RESUME and SUSPEND */ | ||
228 | if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) | ||
229 | pr_err("%s: timeout waiting for RESUME\n", __func__); | ||
230 | if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) | ||
231 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | ||
232 | |||
233 | ehci->reset_done[wIndex-1] = 0; | ||
234 | |||
235 | tegra->port_resuming = 1; | ||
236 | goto done; | ||
237 | } | ||
238 | |||
239 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
240 | |||
241 | /* Handle the hub control events here */ | ||
242 | return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); | ||
243 | done: | ||
244 | spin_unlock_irqrestore(&ehci->lock, flags); | ||
245 | return retval; | ||
246 | } | ||
247 | |||
248 | static void tegra_ehci_restart(struct usb_hcd *hcd) | ||
249 | { | ||
250 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
251 | |||
252 | ehci_reset(ehci); | ||
253 | |||
254 | /* setup the frame list and Async q heads */ | ||
255 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); | ||
256 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | ||
257 | /* setup the command register and set the controller in RUN mode */ | ||
258 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); | ||
259 | ehci->command |= CMD_RUN; | ||
260 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | ||
261 | |||
262 | down_write(&ehci_cf_port_reset_rwsem); | ||
263 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | ||
264 | /* flush posted writes */ | ||
265 | ehci_readl(ehci, &ehci->regs->command); | ||
266 | up_write(&ehci_cf_port_reset_rwsem); | ||
267 | } | ||
268 | |||
269 | static int tegra_usb_suspend(struct usb_hcd *hcd) | ||
270 | { | ||
271 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
272 | struct ehci_regs __iomem *hw = tegra->ehci->regs; | ||
273 | unsigned long flags; | ||
274 | |||
275 | spin_lock_irqsave(&tegra->ehci->lock, flags); | ||
276 | |||
277 | tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; | ||
278 | ehci_halt(tegra->ehci); | ||
279 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
280 | |||
281 | spin_unlock_irqrestore(&tegra->ehci->lock, flags); | ||
282 | |||
283 | tegra_ehci_power_down(hcd); | ||
284 | return 0; | ||
285 | } | ||
286 | |||
287 | static int tegra_usb_resume(struct usb_hcd *hcd) | ||
288 | { | ||
289 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
290 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
291 | struct ehci_regs __iomem *hw = ehci->regs; | ||
292 | unsigned long val; | ||
293 | |||
294 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
295 | tegra_ehci_power_up(hcd); | ||
296 | |||
297 | if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { | ||
298 | /* Wait for the phy to detect new devices | ||
299 | * before we restart the controller */ | ||
300 | msleep(10); | ||
301 | goto restart; | ||
302 | } | ||
303 | |||
304 | /* Force the phy to keep data lines in suspend state */ | ||
305 | tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed); | ||
306 | |||
307 | /* Enable host mode */ | ||
308 | tdi_reset(ehci); | ||
309 | |||
310 | /* Enable Port Power */ | ||
311 | val = readl(&hw->port_status[0]); | ||
312 | val |= PORT_POWER; | ||
313 | writel(val, &hw->port_status[0]); | ||
314 | udelay(10); | ||
315 | |||
316 | /* Check if the phy resume from LP0. When the phy resume from LP0 | ||
317 | * USB register will be reset. */ | ||
318 | if (!readl(&hw->async_next)) { | ||
319 | /* Program the field PTC based on the saved speed mode */ | ||
320 | val = readl(&hw->port_status[0]); | ||
321 | val &= ~PORT_TEST(~0); | ||
322 | if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) | ||
323 | val |= PORT_TEST_FORCE; | ||
324 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) | ||
325 | val |= PORT_TEST(6); | ||
326 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | ||
327 | val |= PORT_TEST(7); | ||
328 | writel(val, &hw->port_status[0]); | ||
329 | udelay(10); | ||
330 | |||
331 | /* Disable test mode by setting PTC field to NORMAL_OP */ | ||
332 | val = readl(&hw->port_status[0]); | ||
333 | val &= ~PORT_TEST(~0); | ||
334 | writel(val, &hw->port_status[0]); | ||
335 | udelay(10); | ||
336 | } | ||
337 | |||
338 | /* Poll until CCS is enabled */ | ||
339 | if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, | ||
340 | PORT_CONNECT, 2000)) { | ||
341 | pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); | ||
342 | goto restart; | ||
343 | } | ||
344 | |||
345 | /* Poll until PE is enabled */ | ||
346 | if (handshake(ehci, &hw->port_status[0], PORT_PE, | ||
347 | PORT_PE, 2000)) { | ||
348 | pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); | ||
349 | goto restart; | ||
350 | } | ||
351 | |||
352 | /* Clear the PCI status, to avoid an interrupt taken upon resume */ | ||
353 | val = readl(&hw->status); | ||
354 | val |= STS_PCD; | ||
355 | writel(val, &hw->status); | ||
356 | |||
357 | /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ | ||
358 | val = readl(&hw->port_status[0]); | ||
359 | if ((val & PORT_POWER) && (val & PORT_PE)) { | ||
360 | val |= PORT_SUSPEND; | ||
361 | writel(val, &hw->port_status[0]); | ||
362 | |||
363 | /* Wait until port suspend completes */ | ||
364 | if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, | ||
365 | PORT_SUSPEND, 1000)) { | ||
366 | pr_err("%s: timeout waiting for PORT_SUSPEND\n", | ||
367 | __func__); | ||
368 | goto restart; | ||
369 | } | ||
370 | } | ||
371 | |||
372 | tegra_ehci_phy_restore_end(tegra->phy); | ||
373 | return 0; | ||
374 | |||
375 | restart: | ||
376 | if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) | ||
377 | tegra_ehci_phy_restore_end(tegra->phy); | ||
378 | |||
379 | tegra_ehci_restart(hcd); | ||
380 | return 0; | ||
381 | } | ||
382 | |||
383 | static void tegra_ehci_shutdown(struct usb_hcd *hcd) | ||
384 | { | ||
385 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
386 | |||
387 | /* ehci_shutdown touches the USB controller registers, make sure | ||
388 | * controller has clocks to it */ | ||
389 | if (!tegra->host_resumed) | ||
390 | tegra_ehci_power_up(hcd); | ||
391 | |||
392 | ehci_shutdown(hcd); | ||
393 | } | ||
394 | |||
395 | static int tegra_ehci_setup(struct usb_hcd *hcd) | ||
396 | { | ||
397 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
398 | int retval; | ||
399 | |||
400 | /* EHCI registers start at offset 0x100 */ | ||
401 | ehci->caps = hcd->regs + 0x100; | ||
402 | ehci->regs = hcd->regs + 0x100 + | ||
403 | HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); | ||
404 | |||
405 | dbg_hcs_params(ehci, "reset"); | ||
406 | dbg_hcc_params(ehci, "reset"); | ||
407 | |||
408 | /* cache this readonly data; minimize chip reads */ | ||
409 | ehci->hcs_params = readl(&ehci->caps->hcs_params); | ||
410 | |||
411 | /* switch to host mode */ | ||
412 | hcd->has_tt = 1; | ||
413 | ehci_reset(ehci); | ||
414 | |||
415 | retval = ehci_halt(ehci); | ||
416 | if (retval) | ||
417 | return retval; | ||
418 | |||
419 | /* data structure init */ | ||
420 | retval = ehci_init(hcd); | ||
421 | if (retval) | ||
422 | return retval; | ||
423 | |||
424 | ehci->sbrn = 0x20; | ||
425 | |||
426 | ehci_port_power(ehci, 1); | ||
427 | return retval; | ||
428 | } | ||
429 | |||
430 | #ifdef CONFIG_PM | ||
431 | static int tegra_ehci_bus_suspend(struct usb_hcd *hcd) | ||
432 | { | ||
433 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
434 | int error_status = 0; | ||
435 | |||
436 | error_status = ehci_bus_suspend(hcd); | ||
437 | if (!error_status && tegra->power_down_on_bus_suspend) { | ||
438 | tegra_usb_suspend(hcd); | ||
439 | tegra->bus_suspended = 1; | ||
440 | } | ||
441 | |||
442 | return error_status; | ||
443 | } | ||
444 | |||
445 | static int tegra_ehci_bus_resume(struct usb_hcd *hcd) | ||
446 | { | ||
447 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | ||
448 | |||
449 | if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) { | ||
450 | tegra_usb_resume(hcd); | ||
451 | tegra->bus_suspended = 0; | ||
452 | } | ||
453 | |||
454 | tegra_usb_phy_preresume(tegra->phy); | ||
455 | tegra->port_resuming = 1; | ||
456 | return ehci_bus_resume(hcd); | ||
457 | } | ||
458 | #endif | ||
459 | |||
460 | struct temp_buffer { | ||
461 | void *kmalloc_ptr; | ||
462 | void *old_xfer_buffer; | ||
463 | u8 data[0]; | ||
464 | }; | ||
465 | |||
466 | static void free_temp_buffer(struct urb *urb) | ||
467 | { | ||
468 | enum dma_data_direction dir; | ||
469 | struct temp_buffer *temp; | ||
470 | |||
471 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | ||
472 | return; | ||
473 | |||
474 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | ||
475 | |||
476 | temp = container_of(urb->transfer_buffer, struct temp_buffer, | ||
477 | data); | ||
478 | |||
479 | if (dir == DMA_FROM_DEVICE) | ||
480 | memcpy(temp->old_xfer_buffer, temp->data, | ||
481 | urb->transfer_buffer_length); | ||
482 | urb->transfer_buffer = temp->old_xfer_buffer; | ||
483 | kfree(temp->kmalloc_ptr); | ||
484 | |||
485 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | ||
486 | } | ||
487 | |||
488 | static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) | ||
489 | { | ||
490 | enum dma_data_direction dir; | ||
491 | struct temp_buffer *temp, *kmalloc_ptr; | ||
492 | size_t kmalloc_size; | ||
493 | |||
494 | if (urb->num_sgs || urb->sg || | ||
495 | urb->transfer_buffer_length == 0 || | ||
496 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) | ||
497 | return 0; | ||
498 | |||
499 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | ||
500 | |||
501 | /* Allocate a buffer with enough padding for alignment */ | ||
502 | kmalloc_size = urb->transfer_buffer_length + | ||
503 | sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1; | ||
504 | |||
505 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | ||
506 | if (!kmalloc_ptr) | ||
507 | return -ENOMEM; | ||
508 | |||
509 | /* Position our struct temp_buffer such that data is aligned */ | ||
510 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; | ||
511 | |||
512 | temp->kmalloc_ptr = kmalloc_ptr; | ||
513 | temp->old_xfer_buffer = urb->transfer_buffer; | ||
514 | if (dir == DMA_TO_DEVICE) | ||
515 | memcpy(temp->data, urb->transfer_buffer, | ||
516 | urb->transfer_buffer_length); | ||
517 | urb->transfer_buffer = temp->data; | ||
518 | |||
519 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | ||
520 | |||
521 | return 0; | ||
522 | } | ||
523 | |||
524 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | ||
525 | gfp_t mem_flags) | ||
526 | { | ||
527 | int ret; | ||
528 | |||
529 | ret = alloc_temp_buffer(urb, mem_flags); | ||
530 | if (ret) | ||
531 | return ret; | ||
532 | |||
533 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | ||
534 | if (ret) | ||
535 | free_temp_buffer(urb); | ||
536 | |||
537 | return ret; | ||
538 | } | ||
539 | |||
540 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | ||
541 | { | ||
542 | usb_hcd_unmap_urb_for_dma(hcd, urb); | ||
543 | free_temp_buffer(urb); | ||
544 | } | ||
545 | |||
546 | static const struct hc_driver tegra_ehci_hc_driver = { | ||
547 | .description = hcd_name, | ||
548 | .product_desc = "Tegra EHCI Host Controller", | ||
549 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
550 | |||
551 | .flags = HCD_USB2 | HCD_MEMORY, | ||
552 | |||
553 | .reset = tegra_ehci_setup, | ||
554 | .irq = ehci_irq, | ||
555 | |||
556 | .start = ehci_run, | ||
557 | .stop = ehci_stop, | ||
558 | .shutdown = tegra_ehci_shutdown, | ||
559 | .urb_enqueue = ehci_urb_enqueue, | ||
560 | .urb_dequeue = ehci_urb_dequeue, | ||
561 | .map_urb_for_dma = tegra_ehci_map_urb_for_dma, | ||
562 | .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, | ||
563 | .endpoint_disable = ehci_endpoint_disable, | ||
564 | .endpoint_reset = ehci_endpoint_reset, | ||
565 | .get_frame_number = ehci_get_frame, | ||
566 | .hub_status_data = ehci_hub_status_data, | ||
567 | .hub_control = tegra_ehci_hub_control, | ||
568 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
569 | #ifdef CONFIG_PM | ||
570 | .bus_suspend = tegra_ehci_bus_suspend, | ||
571 | .bus_resume = tegra_ehci_bus_resume, | ||
572 | #endif | ||
573 | .relinquish_port = ehci_relinquish_port, | ||
574 | .port_handed_over = ehci_port_handed_over, | ||
575 | }; | ||
576 | |||
577 | static int tegra_ehci_probe(struct platform_device *pdev) | ||
578 | { | ||
579 | struct resource *res; | ||
580 | struct usb_hcd *hcd; | ||
581 | struct tegra_ehci_hcd *tegra; | ||
582 | struct tegra_ehci_platform_data *pdata; | ||
583 | int err = 0; | ||
584 | int irq; | ||
585 | int instance = pdev->id; | ||
586 | |||
587 | pdata = pdev->dev.platform_data; | ||
588 | if (!pdata) { | ||
589 | dev_err(&pdev->dev, "Platform data missing\n"); | ||
590 | return -EINVAL; | ||
591 | } | ||
592 | |||
593 | tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); | ||
594 | if (!tegra) | ||
595 | return -ENOMEM; | ||
596 | |||
597 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, | ||
598 | dev_name(&pdev->dev)); | ||
599 | if (!hcd) { | ||
600 | dev_err(&pdev->dev, "Unable to create HCD\n"); | ||
601 | err = -ENOMEM; | ||
602 | goto fail_hcd; | ||
603 | } | ||
604 | |||
605 | platform_set_drvdata(pdev, tegra); | ||
606 | |||
607 | tegra->clk = clk_get(&pdev->dev, NULL); | ||
608 | if (IS_ERR(tegra->clk)) { | ||
609 | dev_err(&pdev->dev, "Can't get ehci clock\n"); | ||
610 | err = PTR_ERR(tegra->clk); | ||
611 | goto fail_clk; | ||
612 | } | ||
613 | |||
614 | err = clk_enable(tegra->clk); | ||
615 | if (err) | ||
616 | goto fail_clken; | ||
617 | |||
618 | tegra->emc_clk = clk_get(&pdev->dev, "emc"); | ||
619 | if (IS_ERR(tegra->emc_clk)) { | ||
620 | dev_err(&pdev->dev, "Can't get emc clock\n"); | ||
621 | err = PTR_ERR(tegra->emc_clk); | ||
622 | goto fail_emc_clk; | ||
623 | } | ||
624 | |||
625 | clk_enable(tegra->emc_clk); | ||
626 | clk_set_rate(tegra->emc_clk, 400000000); | ||
627 | |||
628 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
629 | if (!res) { | ||
630 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | ||
631 | err = -ENXIO; | ||
632 | goto fail_io; | ||
633 | } | ||
634 | hcd->rsrc_start = res->start; | ||
635 | hcd->rsrc_len = resource_size(res); | ||
636 | hcd->regs = ioremap(res->start, resource_size(res)); | ||
637 | if (!hcd->regs) { | ||
638 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | ||
639 | err = -ENOMEM; | ||
640 | goto fail_io; | ||
641 | } | ||
642 | |||
643 | tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config, | ||
644 | TEGRA_USB_PHY_MODE_HOST); | ||
645 | if (IS_ERR(tegra->phy)) { | ||
646 | dev_err(&pdev->dev, "Failed to open USB phy\n"); | ||
647 | err = -ENXIO; | ||
648 | goto fail_phy; | ||
649 | } | ||
650 | |||
651 | err = tegra_usb_phy_power_on(tegra->phy); | ||
652 | if (err) { | ||
653 | dev_err(&pdev->dev, "Failed to power on the phy\n"); | ||
654 | goto fail; | ||
655 | } | ||
656 | |||
657 | tegra->host_resumed = 1; | ||
658 | tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend; | ||
659 | tegra->ehci = hcd_to_ehci(hcd); | ||
660 | |||
661 | irq = platform_get_irq(pdev, 0); | ||
662 | if (!irq) { | ||
663 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | ||
664 | err = -ENODEV; | ||
665 | goto fail; | ||
666 | } | ||
667 | set_irq_flags(irq, IRQF_VALID); | ||
668 | |||
669 | #ifdef CONFIG_USB_OTG_UTILS | ||
670 | if (pdata->operating_mode == TEGRA_USB_OTG) { | ||
671 | tegra->transceiver = otg_get_transceiver(); | ||
672 | if (tegra->transceiver) | ||
673 | otg_set_host(tegra->transceiver, &hcd->self); | ||
674 | } | ||
675 | #endif | ||
676 | |||
677 | err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | ||
678 | if (err) { | ||
679 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | ||
680 | goto fail; | ||
681 | } | ||
682 | |||
683 | return err; | ||
684 | |||
685 | fail: | ||
686 | #ifdef CONFIG_USB_OTG_UTILS | ||
687 | if (tegra->transceiver) { | ||
688 | otg_set_host(tegra->transceiver, NULL); | ||
689 | otg_put_transceiver(tegra->transceiver); | ||
690 | } | ||
691 | #endif | ||
692 | tegra_usb_phy_close(tegra->phy); | ||
693 | fail_phy: | ||
694 | iounmap(hcd->regs); | ||
695 | fail_io: | ||
696 | clk_disable(tegra->emc_clk); | ||
697 | clk_put(tegra->emc_clk); | ||
698 | fail_emc_clk: | ||
699 | clk_disable(tegra->clk); | ||
700 | fail_clken: | ||
701 | clk_put(tegra->clk); | ||
702 | fail_clk: | ||
703 | usb_put_hcd(hcd); | ||
704 | fail_hcd: | ||
705 | kfree(tegra); | ||
706 | return err; | ||
707 | } | ||
708 | |||
709 | #ifdef CONFIG_PM | ||
710 | static int tegra_ehci_resume(struct platform_device *pdev) | ||
711 | { | ||
712 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | ||
713 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | ||
714 | |||
715 | if (tegra->bus_suspended) | ||
716 | return 0; | ||
717 | |||
718 | return tegra_usb_resume(hcd); | ||
719 | } | ||
720 | |||
721 | static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state) | ||
722 | { | ||
723 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | ||
724 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | ||
725 | |||
726 | if (tegra->bus_suspended) | ||
727 | return 0; | ||
728 | |||
729 | if (time_before(jiffies, tegra->ehci->next_statechange)) | ||
730 | msleep(10); | ||
731 | |||
732 | return tegra_usb_suspend(hcd); | ||
733 | } | ||
734 | #endif | ||
735 | |||
736 | static int tegra_ehci_remove(struct platform_device *pdev) | ||
737 | { | ||
738 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | ||
739 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | ||
740 | |||
741 | if (tegra == NULL || hcd == NULL) | ||
742 | return -EINVAL; | ||
743 | |||
744 | #ifdef CONFIG_USB_OTG_UTILS | ||
745 | if (tegra->transceiver) { | ||
746 | otg_set_host(tegra->transceiver, NULL); | ||
747 | otg_put_transceiver(tegra->transceiver); | ||
748 | } | ||
749 | #endif | ||
750 | |||
751 | usb_remove_hcd(hcd); | ||
752 | usb_put_hcd(hcd); | ||
753 | |||
754 | tegra_usb_phy_close(tegra->phy); | ||
755 | iounmap(hcd->regs); | ||
756 | |||
757 | clk_disable(tegra->clk); | ||
758 | clk_put(tegra->clk); | ||
759 | |||
760 | clk_disable(tegra->emc_clk); | ||
761 | clk_put(tegra->emc_clk); | ||
762 | |||
763 | kfree(tegra); | ||
764 | return 0; | ||
765 | } | ||
766 | |||
767 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) | ||
768 | { | ||
769 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | ||
770 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | ||
771 | |||
772 | if (hcd->driver->shutdown) | ||
773 | hcd->driver->shutdown(hcd); | ||
774 | } | ||
775 | |||
776 | static struct platform_driver tegra_ehci_driver = { | ||
777 | .probe = tegra_ehci_probe, | ||
778 | .remove = tegra_ehci_remove, | ||
779 | #ifdef CONFIG_PM | ||
780 | .suspend = tegra_ehci_suspend, | ||
781 | .resume = tegra_ehci_resume, | ||
782 | #endif | ||
783 | .shutdown = tegra_ehci_hcd_shutdown, | ||
784 | .driver = { | ||
785 | .name = "tegra-ehci", | ||
786 | } | ||
787 | }; | ||
diff --git a/drivers/usb/host/ehci-vt8500.c b/drivers/usb/host/ehci-vt8500.c new file mode 100644 index 000000000000..47d749631bc7 --- /dev/null +++ b/drivers/usb/host/ehci-vt8500.c | |||
@@ -0,0 +1,173 @@ | |||
1 | /* | ||
2 | * drivers/usb/host/ehci-vt8500.c | ||
3 | * | ||
4 | * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> | ||
5 | * | ||
6 | * Based on ehci-au1xxx.c | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | #include <linux/platform_device.h> | ||
20 | |||
21 | static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) | ||
22 | { | ||
23 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | ||
24 | int rc = 0; | ||
25 | |||
26 | if (!udev->parent) /* udev is root hub itself, impossible */ | ||
27 | rc = -1; | ||
28 | /* we only support lpm device connected to root hub yet */ | ||
29 | if (ehci->has_lpm && !udev->parent->parent) { | ||
30 | rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); | ||
31 | if (!rc) | ||
32 | rc = ehci_lpm_check(ehci, udev->portnum); | ||
33 | } | ||
34 | return rc; | ||
35 | } | ||
36 | |||
37 | static const struct hc_driver vt8500_ehci_hc_driver = { | ||
38 | .description = hcd_name, | ||
39 | .product_desc = "VT8500 EHCI", | ||
40 | .hcd_priv_size = sizeof(struct ehci_hcd), | ||
41 | |||
42 | /* | ||
43 | * generic hardware linkage | ||
44 | */ | ||
45 | .irq = ehci_irq, | ||
46 | .flags = HCD_MEMORY | HCD_USB2, | ||
47 | |||
48 | /* | ||
49 | * basic lifecycle operations | ||
50 | */ | ||
51 | .reset = ehci_init, | ||
52 | .start = ehci_run, | ||
53 | .stop = ehci_stop, | ||
54 | .shutdown = ehci_shutdown, | ||
55 | |||
56 | /* | ||
57 | * managing i/o requests and associated device resources | ||
58 | */ | ||
59 | .urb_enqueue = ehci_urb_enqueue, | ||
60 | .urb_dequeue = ehci_urb_dequeue, | ||
61 | .endpoint_disable = ehci_endpoint_disable, | ||
62 | .endpoint_reset = ehci_endpoint_reset, | ||
63 | |||
64 | /* | ||
65 | * scheduling support | ||
66 | */ | ||
67 | .get_frame_number = ehci_get_frame, | ||
68 | |||
69 | /* | ||
70 | * root hub support | ||
71 | */ | ||
72 | .hub_status_data = ehci_hub_status_data, | ||
73 | .hub_control = ehci_hub_control, | ||
74 | .bus_suspend = ehci_bus_suspend, | ||
75 | .bus_resume = ehci_bus_resume, | ||
76 | .relinquish_port = ehci_relinquish_port, | ||
77 | .port_handed_over = ehci_port_handed_over, | ||
78 | |||
79 | /* | ||
80 | * call back when device connected and addressed | ||
81 | */ | ||
82 | .update_device = ehci_update_device, | ||
83 | |||
84 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
85 | }; | ||
86 | |||
87 | static int vt8500_ehci_drv_probe(struct platform_device *pdev) | ||
88 | { | ||
89 | struct usb_hcd *hcd; | ||
90 | struct ehci_hcd *ehci; | ||
91 | struct resource *res; | ||
92 | int ret; | ||
93 | |||
94 | if (usb_disabled()) | ||
95 | return -ENODEV; | ||
96 | |||
97 | if (pdev->resource[1].flags != IORESOURCE_IRQ) { | ||
98 | pr_debug("resource[1] is not IORESOURCE_IRQ"); | ||
99 | return -ENOMEM; | ||
100 | } | ||
101 | hcd = usb_create_hcd(&vt8500_ehci_hc_driver, &pdev->dev, "VT8500"); | ||
102 | if (!hcd) | ||
103 | return -ENOMEM; | ||
104 | |||
105 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
106 | hcd->rsrc_start = res->start; | ||
107 | hcd->rsrc_len = resource_size(res); | ||
108 | |||
109 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
110 | pr_debug("request_mem_region failed"); | ||
111 | ret = -EBUSY; | ||
112 | goto err1; | ||
113 | } | ||
114 | |||
115 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
116 | if (!hcd->regs) { | ||
117 | pr_debug("ioremap failed"); | ||
118 | ret = -ENOMEM; | ||
119 | goto err2; | ||
120 | } | ||
121 | |||
122 | ehci = hcd_to_ehci(hcd); | ||
123 | ehci->caps = hcd->regs; | ||
124 | ehci->regs = hcd->regs + | ||
125 | HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); | ||
126 | |||
127 | dbg_hcs_params(ehci, "reset"); | ||
128 | dbg_hcc_params(ehci, "reset"); | ||
129 | |||
130 | /* cache this readonly data; minimize chip reads */ | ||
131 | ehci->hcs_params = readl(&ehci->caps->hcs_params); | ||
132 | |||
133 | ehci_port_power(ehci, 1); | ||
134 | |||
135 | ret = usb_add_hcd(hcd, pdev->resource[1].start, | ||
136 | IRQF_DISABLED | IRQF_SHARED); | ||
137 | if (ret == 0) { | ||
138 | platform_set_drvdata(pdev, hcd); | ||
139 | return ret; | ||
140 | } | ||
141 | |||
142 | iounmap(hcd->regs); | ||
143 | err2: | ||
144 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
145 | err1: | ||
146 | usb_put_hcd(hcd); | ||
147 | return ret; | ||
148 | } | ||
149 | |||
150 | static int vt8500_ehci_drv_remove(struct platform_device *pdev) | ||
151 | { | ||
152 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
153 | |||
154 | usb_remove_hcd(hcd); | ||
155 | iounmap(hcd->regs); | ||
156 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
157 | usb_put_hcd(hcd); | ||
158 | platform_set_drvdata(pdev, NULL); | ||
159 | |||
160 | return 0; | ||
161 | } | ||
162 | |||
163 | static struct platform_driver vt8500_ehci_driver = { | ||
164 | .probe = vt8500_ehci_drv_probe, | ||
165 | .remove = vt8500_ehci_drv_remove, | ||
166 | .shutdown = usb_hcd_platform_shutdown, | ||
167 | .driver = { | ||
168 | .name = "vt8500-ehci", | ||
169 | .owner = THIS_MODULE, | ||
170 | } | ||
171 | }; | ||
172 | |||
173 | MODULE_ALIAS("platform:vt8500-ehci"); | ||
diff --git a/drivers/usb/host/ehci-w90x900.c b/drivers/usb/host/ehci-w90x900.c index cfa21ea20f82..52a027aaa370 100644 --- a/drivers/usb/host/ehci-w90x900.c +++ b/drivers/usb/host/ehci-w90x900.c | |||
@@ -57,7 +57,7 @@ static int __devinit usb_w90x900_probe(const struct hc_driver *driver, | |||
57 | ehci = hcd_to_ehci(hcd); | 57 | ehci = hcd_to_ehci(hcd); |
58 | ehci->caps = hcd->regs; | 58 | ehci->caps = hcd->regs; |
59 | ehci->regs = hcd->regs + | 59 | ehci->regs = hcd->regs + |
60 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 60 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
61 | 61 | ||
62 | /* enable PHY 0,1,the regs only apply to w90p910 | 62 | /* enable PHY 0,1,the regs only apply to w90p910 |
63 | * 0xA4,0xA8 were offsets of PHY0 and PHY1 controller of | 63 | * 0xA4,0xA8 were offsets of PHY0 and PHY1 controller of |
@@ -130,6 +130,7 @@ static const struct hc_driver ehci_w90x900_hc_driver = { | |||
130 | .urb_enqueue = ehci_urb_enqueue, | 130 | .urb_enqueue = ehci_urb_enqueue, |
131 | .urb_dequeue = ehci_urb_dequeue, | 131 | .urb_dequeue = ehci_urb_dequeue, |
132 | .endpoint_disable = ehci_endpoint_disable, | 132 | .endpoint_disable = ehci_endpoint_disable, |
133 | .endpoint_reset = ehci_endpoint_reset, | ||
133 | 134 | ||
134 | /* | 135 | /* |
135 | * scheduling support | 136 | * scheduling support |
@@ -147,6 +148,8 @@ static const struct hc_driver ehci_w90x900_hc_driver = { | |||
147 | #endif | 148 | #endif |
148 | .relinquish_port = ehci_relinquish_port, | 149 | .relinquish_port = ehci_relinquish_port, |
149 | .port_handed_over = ehci_port_handed_over, | 150 | .port_handed_over = ehci_port_handed_over, |
151 | |||
152 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | ||
150 | }; | 153 | }; |
151 | 154 | ||
152 | static int __devinit ehci_w90x900_probe(struct platform_device *pdev) | 155 | static int __devinit ehci_w90x900_probe(struct platform_device *pdev) |
diff --git a/drivers/usb/host/ehci-xilinx-of.c b/drivers/usb/host/ehci-xilinx-of.c index 6c8076ad821d..a64d6d66d760 100644 --- a/drivers/usb/host/ehci-xilinx-of.c +++ b/drivers/usb/host/ehci-xilinx-of.c | |||
@@ -29,6 +29,7 @@ | |||
29 | 29 | ||
30 | #include <linux/of.h> | 30 | #include <linux/of.h> |
31 | #include <linux/of_platform.h> | 31 | #include <linux/of_platform.h> |
32 | #include <linux/of_address.h> | ||
32 | 33 | ||
33 | /** | 34 | /** |
34 | * ehci_xilinx_of_setup - Initialize the device for ehci_reset() | 35 | * ehci_xilinx_of_setup - Initialize the device for ehci_reset() |
@@ -117,6 +118,7 @@ static const struct hc_driver ehci_xilinx_of_hc_driver = { | |||
117 | .urb_enqueue = ehci_urb_enqueue, | 118 | .urb_enqueue = ehci_urb_enqueue, |
118 | .urb_dequeue = ehci_urb_dequeue, | 119 | .urb_dequeue = ehci_urb_dequeue, |
119 | .endpoint_disable = ehci_endpoint_disable, | 120 | .endpoint_disable = ehci_endpoint_disable, |
121 | .endpoint_reset = ehci_endpoint_reset, | ||
120 | 122 | ||
121 | /* | 123 | /* |
122 | * scheduling support | 124 | * scheduling support |
@@ -141,15 +143,13 @@ static const struct hc_driver ehci_xilinx_of_hc_driver = { | |||
141 | /** | 143 | /** |
142 | * ehci_hcd_xilinx_of_probe - Probe method for the USB host controller | 144 | * ehci_hcd_xilinx_of_probe - Probe method for the USB host controller |
143 | * @op: pointer to the platform_device bound to the host controller | 145 | * @op: pointer to the platform_device bound to the host controller |
144 | * @match: pointer to of_device_id structure, not used | ||
145 | * | 146 | * |
146 | * This function requests resources and sets up appropriate properties for the | 147 | * This function requests resources and sets up appropriate properties for the |
147 | * host controller. Because the Xilinx USB host controller can be configured | 148 | * host controller. Because the Xilinx USB host controller can be configured |
148 | * as HS only or HS/FS only, it checks the configuration in the device tree | 149 | * as HS only or HS/FS only, it checks the configuration in the device tree |
149 | * entry, and sets an appropriate value for hcd->has_tt. | 150 | * entry, and sets an appropriate value for hcd->has_tt. |
150 | */ | 151 | */ |
151 | static int __devinit | 152 | static int __devinit ehci_hcd_xilinx_of_probe(struct platform_device *op) |
152 | ehci_hcd_xilinx_of_probe(struct platform_device *op, const struct of_device_id *match) | ||
153 | { | 153 | { |
154 | struct device_node *dn = op->dev.of_node; | 154 | struct device_node *dn = op->dev.of_node; |
155 | struct usb_hcd *hcd; | 155 | struct usb_hcd *hcd; |
@@ -220,7 +220,7 @@ ehci_hcd_xilinx_of_probe(struct platform_device *op, const struct of_device_id * | |||
220 | */ | 220 | */ |
221 | ehci->caps = hcd->regs + 0x100; | 221 | ehci->caps = hcd->regs + 0x100; |
222 | ehci->regs = hcd->regs + 0x100 + | 222 | ehci->regs = hcd->regs + 0x100 + |
223 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | 223 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
224 | 224 | ||
225 | /* cache this readonly data; minimize chip reads */ | 225 | /* cache this readonly data; minimize chip reads */ |
226 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | 226 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
@@ -287,7 +287,7 @@ static const struct of_device_id ehci_hcd_xilinx_of_match[] = { | |||
287 | }; | 287 | }; |
288 | MODULE_DEVICE_TABLE(of, ehci_hcd_xilinx_of_match); | 288 | MODULE_DEVICE_TABLE(of, ehci_hcd_xilinx_of_match); |
289 | 289 | ||
290 | static struct of_platform_driver ehci_hcd_xilinx_of_driver = { | 290 | static struct platform_driver ehci_hcd_xilinx_of_driver = { |
291 | .probe = ehci_hcd_xilinx_of_probe, | 291 | .probe = ehci_hcd_xilinx_of_probe, |
292 | .remove = ehci_hcd_xilinx_of_remove, | 292 | .remove = ehci_hcd_xilinx_of_remove, |
293 | .shutdown = ehci_hcd_xilinx_of_shutdown, | 293 | .shutdown = ehci_hcd_xilinx_of_shutdown, |
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index bde823f704e9..bd6ff489baf9 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h | |||
@@ -73,6 +73,7 @@ struct ehci_hcd { /* one per controller */ | |||
73 | 73 | ||
74 | /* async schedule support */ | 74 | /* async schedule support */ |
75 | struct ehci_qh *async; | 75 | struct ehci_qh *async; |
76 | struct ehci_qh *dummy; /* For AMD quirk use */ | ||
76 | struct ehci_qh *reclaim; | 77 | struct ehci_qh *reclaim; |
77 | unsigned scanning : 1; | 78 | unsigned scanning : 1; |
78 | 79 | ||
@@ -117,6 +118,7 @@ struct ehci_hcd { /* one per controller */ | |||
117 | struct timer_list watchdog; | 118 | struct timer_list watchdog; |
118 | unsigned long actions; | 119 | unsigned long actions; |
119 | unsigned stamp; | 120 | unsigned stamp; |
121 | unsigned periodic_stamp; | ||
120 | unsigned random_frame; | 122 | unsigned random_frame; |
121 | unsigned long next_statechange; | 123 | unsigned long next_statechange; |
122 | ktime_t last_periodic_enable; | 124 | ktime_t last_periodic_enable; |
@@ -127,10 +129,14 @@ struct ehci_hcd { /* one per controller */ | |||
127 | unsigned has_fsl_port_bug:1; /* FreeScale */ | 129 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
128 | unsigned big_endian_mmio:1; | 130 | unsigned big_endian_mmio:1; |
129 | unsigned big_endian_desc:1; | 131 | unsigned big_endian_desc:1; |
132 | unsigned big_endian_capbase:1; | ||
130 | unsigned has_amcc_usb23:1; | 133 | unsigned has_amcc_usb23:1; |
131 | unsigned need_io_watchdog:1; | 134 | unsigned need_io_watchdog:1; |
132 | unsigned broken_periodic:1; | 135 | unsigned broken_periodic:1; |
136 | unsigned amd_pll_fix:1; | ||
133 | unsigned fs_i_thresh:1; /* Intel iso scheduling */ | 137 | unsigned fs_i_thresh:1; /* Intel iso scheduling */ |
138 | unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ | ||
139 | unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ | ||
134 | 140 | ||
135 | /* required for usb32 quirk */ | 141 | /* required for usb32 quirk */ |
136 | #define OHCI_CTRL_HCFS (3 << 6) | 142 | #define OHCI_CTRL_HCFS (3 << 6) |
@@ -157,6 +163,10 @@ struct ehci_hcd { /* one per controller */ | |||
157 | #ifdef DEBUG | 163 | #ifdef DEBUG |
158 | struct dentry *debug_dir; | 164 | struct dentry *debug_dir; |
159 | #endif | 165 | #endif |
166 | /* | ||
167 | * OTG controllers and transceivers need software interaction | ||
168 | */ | ||
169 | struct otg_transceiver *transceiver; | ||
160 | }; | 170 | }; |
161 | 171 | ||
162 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ | 172 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
@@ -597,12 +607,18 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |||
597 | * This attempts to support either format at compile time without a | 607 | * This attempts to support either format at compile time without a |
598 | * runtime penalty, or both formats with the additional overhead | 608 | * runtime penalty, or both formats with the additional overhead |
599 | * of checking a flag bit. | 609 | * of checking a flag bit. |
610 | * | ||
611 | * ehci_big_endian_capbase is a special quirk for controllers that | ||
612 | * implement the HC capability registers as separate registers and not | ||
613 | * as fields of a 32-bit register. | ||
600 | */ | 614 | */ |
601 | 615 | ||
602 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | 616 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
603 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | 617 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) |
618 | #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) | ||
604 | #else | 619 | #else |
605 | #define ehci_big_endian_mmio(e) 0 | 620 | #define ehci_big_endian_mmio(e) 0 |
621 | #define ehci_big_endian_capbase(e) 0 | ||
606 | #endif | 622 | #endif |
607 | 623 | ||
608 | /* | 624 | /* |
@@ -641,7 +657,7 @@ static inline void ehci_writel(const struct ehci_hcd *ehci, | |||
641 | /* | 657 | /* |
642 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with | 658 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with |
643 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. | 659 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. |
644 | * Other common bits are dependant on has_amcc_usb23 quirk flag. | 660 | * Other common bits are dependent on has_amcc_usb23 quirk flag. |
645 | */ | 661 | */ |
646 | #ifdef CONFIG_44x | 662 | #ifdef CONFIG_44x |
647 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | 663 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) |
diff --git a/drivers/usb/host/fhci-hcd.c b/drivers/usb/host/fhci-hcd.c index 20092a27a1e8..19223c7449e1 100644 --- a/drivers/usb/host/fhci-hcd.c +++ b/drivers/usb/host/fhci-hcd.c | |||
@@ -98,13 +98,13 @@ void fhci_usb_enable_interrupt(struct fhci_usb *usb) | |||
98 | usb->intr_nesting_cnt--; | 98 | usb->intr_nesting_cnt--; |
99 | } | 99 | } |
100 | 100 | ||
101 | /* diable the usb interrupt */ | 101 | /* disable the usb interrupt */ |
102 | void fhci_usb_disable_interrupt(struct fhci_usb *usb) | 102 | void fhci_usb_disable_interrupt(struct fhci_usb *usb) |
103 | { | 103 | { |
104 | struct fhci_hcd *fhci = usb->fhci; | 104 | struct fhci_hcd *fhci = usb->fhci; |
105 | 105 | ||
106 | if (usb->intr_nesting_cnt == 0) { | 106 | if (usb->intr_nesting_cnt == 0) { |
107 | /* diable the timer interrupt */ | 107 | /* disable the timer interrupt */ |
108 | disable_irq_nosync(fhci->timer->irq); | 108 | disable_irq_nosync(fhci->timer->irq); |
109 | 109 | ||
110 | /* disable the usb interrupt */ | 110 | /* disable the usb interrupt */ |
@@ -401,7 +401,7 @@ static int fhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | |||
401 | /* 1 td fro setup,1 for ack */ | 401 | /* 1 td fro setup,1 for ack */ |
402 | size = 2; | 402 | size = 2; |
403 | case PIPE_BULK: | 403 | case PIPE_BULK: |
404 | /* one td for every 4096 bytes(can be upto 8k) */ | 404 | /* one td for every 4096 bytes(can be up to 8k) */ |
405 | size += urb->transfer_buffer_length / 4096; | 405 | size += urb->transfer_buffer_length / 4096; |
406 | /* ...add for any remaining bytes... */ | 406 | /* ...add for any remaining bytes... */ |
407 | if ((urb->transfer_buffer_length % 4096) != 0) | 407 | if ((urb->transfer_buffer_length % 4096) != 0) |
@@ -561,8 +561,7 @@ static const struct hc_driver fhci_driver = { | |||
561 | .hub_control = fhci_hub_control, | 561 | .hub_control = fhci_hub_control, |
562 | }; | 562 | }; |
563 | 563 | ||
564 | static int __devinit of_fhci_probe(struct platform_device *ofdev, | 564 | static int __devinit of_fhci_probe(struct platform_device *ofdev) |
565 | const struct of_device_id *ofid) | ||
566 | { | 565 | { |
567 | struct device *dev = &ofdev->dev; | 566 | struct device *dev = &ofdev->dev; |
568 | struct device_node *node = dev->of_node; | 567 | struct device_node *node = dev->of_node; |
@@ -812,7 +811,7 @@ static const struct of_device_id of_fhci_match[] = { | |||
812 | }; | 811 | }; |
813 | MODULE_DEVICE_TABLE(of, of_fhci_match); | 812 | MODULE_DEVICE_TABLE(of, of_fhci_match); |
814 | 813 | ||
815 | static struct of_platform_driver of_fhci_driver = { | 814 | static struct platform_driver of_fhci_driver = { |
816 | .driver = { | 815 | .driver = { |
817 | .name = "fsl,usb-fhci", | 816 | .name = "fsl,usb-fhci", |
818 | .owner = THIS_MODULE, | 817 | .owner = THIS_MODULE, |
@@ -824,13 +823,13 @@ static struct of_platform_driver of_fhci_driver = { | |||
824 | 823 | ||
825 | static int __init fhci_module_init(void) | 824 | static int __init fhci_module_init(void) |
826 | { | 825 | { |
827 | return of_register_platform_driver(&of_fhci_driver); | 826 | return platform_driver_register(&of_fhci_driver); |
828 | } | 827 | } |
829 | module_init(fhci_module_init); | 828 | module_init(fhci_module_init); |
830 | 829 | ||
831 | static void __exit fhci_module_exit(void) | 830 | static void __exit fhci_module_exit(void) |
832 | { | 831 | { |
833 | of_unregister_platform_driver(&of_fhci_driver); | 832 | platform_driver_unregister(&of_fhci_driver); |
834 | } | 833 | } |
835 | module_exit(fhci_module_exit); | 834 | module_exit(fhci_module_exit); |
836 | 835 | ||
diff --git a/drivers/usb/host/fhci-tds.c b/drivers/usb/host/fhci-tds.c index 7be548ca2183..0ea577bfca2a 100644 --- a/drivers/usb/host/fhci-tds.c +++ b/drivers/usb/host/fhci-tds.c | |||
@@ -40,7 +40,7 @@ | |||
40 | #define TD_RXER 0x0020 /* Rx error or not */ | 40 | #define TD_RXER 0x0020 /* Rx error or not */ |
41 | 41 | ||
42 | #define TD_NAK 0x0010 /* No ack. */ | 42 | #define TD_NAK 0x0010 /* No ack. */ |
43 | #define TD_STAL 0x0008 /* Stall recieved */ | 43 | #define TD_STAL 0x0008 /* Stall received */ |
44 | #define TD_TO 0x0004 /* time out */ | 44 | #define TD_TO 0x0004 /* time out */ |
45 | #define TD_UN 0x0002 /* underrun */ | 45 | #define TD_UN 0x0002 /* underrun */ |
46 | #define TD_NO 0x0010 /* Rx Non Octet Aligned Packet */ | 46 | #define TD_NO 0x0010 /* Rx Non Octet Aligned Packet */ |
@@ -271,10 +271,10 @@ void fhci_init_ep_registers(struct fhci_usb *usb, struct endpoint *ep, | |||
271 | 271 | ||
272 | /* | 272 | /* |
273 | * Collect the submitted frames and inform the application about them | 273 | * Collect the submitted frames and inform the application about them |
274 | * It is also prepearing the TDs for new frames. If the Tx interrupts | 274 | * It is also preparing the TDs for new frames. If the Tx interrupts |
275 | * are diabled, the application should call that routine to get | 275 | * are disabled, the application should call that routine to get |
276 | * confirmation about the submitted frames. Otherwise, the routine is | 276 | * confirmation about the submitted frames. Otherwise, the routine is |
277 | * called frome the interrupt service routine during the Tx interrupt. | 277 | * called from the interrupt service routine during the Tx interrupt. |
278 | * In that case the application is informed by calling the application | 278 | * In that case the application is informed by calling the application |
279 | * specific 'fhci_transaction_confirm' routine | 279 | * specific 'fhci_transaction_confirm' routine |
280 | */ | 280 | */ |
@@ -337,7 +337,7 @@ static void fhci_td_transaction_confirm(struct fhci_usb *usb) | |||
337 | pkt->status = USB_TD_RX_ER_NONOCT; | 337 | pkt->status = USB_TD_RX_ER_NONOCT; |
338 | else | 338 | else |
339 | fhci_err(usb->fhci, "illegal error " | 339 | fhci_err(usb->fhci, "illegal error " |
340 | "occured\n"); | 340 | "occurred\n"); |
341 | } else if (td_status & TD_NAK) | 341 | } else if (td_status & TD_NAK) |
342 | pkt->status = USB_TD_TX_ER_NAK; | 342 | pkt->status = USB_TD_TX_ER_NAK; |
343 | else if (td_status & TD_TO) | 343 | else if (td_status & TD_TO) |
@@ -347,7 +347,7 @@ static void fhci_td_transaction_confirm(struct fhci_usb *usb) | |||
347 | else if (td_status & TD_STAL) | 347 | else if (td_status & TD_STAL) |
348 | pkt->status = USB_TD_TX_ER_STALL; | 348 | pkt->status = USB_TD_TX_ER_STALL; |
349 | else | 349 | else |
350 | fhci_err(usb->fhci, "illegal error occured\n"); | 350 | fhci_err(usb->fhci, "illegal error occurred\n"); |
351 | } else if ((extra_data & TD_TOK_IN) && | 351 | } else if ((extra_data & TD_TOK_IN) && |
352 | pkt->len > td_length - CRC_SIZE) { | 352 | pkt->len > td_length - CRC_SIZE) { |
353 | pkt->status = USB_TD_RX_DATA_UNDERUN; | 353 | pkt->status = USB_TD_RX_DATA_UNDERUN; |
diff --git a/drivers/usb/host/fhci.h b/drivers/usb/host/fhci.h index 71c3caaea4c1..dc6939a44a1a 100644 --- a/drivers/usb/host/fhci.h +++ b/drivers/usb/host/fhci.h | |||
@@ -82,7 +82,7 @@ | |||
82 | #define USB_TD_RX_ER_NONOCT 0x40000000 /* Tx Non Octet Aligned Packet */ | 82 | #define USB_TD_RX_ER_NONOCT 0x40000000 /* Tx Non Octet Aligned Packet */ |
83 | #define USB_TD_RX_ER_BITSTUFF 0x20000000 /* Frame Aborted-Received pkt */ | 83 | #define USB_TD_RX_ER_BITSTUFF 0x20000000 /* Frame Aborted-Received pkt */ |
84 | #define USB_TD_RX_ER_CRC 0x10000000 /* CRC error */ | 84 | #define USB_TD_RX_ER_CRC 0x10000000 /* CRC error */ |
85 | #define USB_TD_RX_ER_OVERUN 0x08000000 /* Over - run occured */ | 85 | #define USB_TD_RX_ER_OVERUN 0x08000000 /* Over - run occurred */ |
86 | #define USB_TD_RX_ER_PID 0x04000000 /* wrong PID received */ | 86 | #define USB_TD_RX_ER_PID 0x04000000 /* wrong PID received */ |
87 | #define USB_TD_RX_DATA_UNDERUN 0x02000000 /* shorter than expected */ | 87 | #define USB_TD_RX_DATA_UNDERUN 0x02000000 /* shorter than expected */ |
88 | #define USB_TD_RX_DATA_OVERUN 0x01000000 /* longer than expected */ | 88 | #define USB_TD_RX_DATA_OVERUN 0x01000000 /* longer than expected */ |
@@ -363,7 +363,7 @@ struct ed { | |||
363 | struct td { | 363 | struct td { |
364 | void *data; /* a pointer to the data buffer */ | 364 | void *data; /* a pointer to the data buffer */ |
365 | unsigned int len; /* length of the data to be submitted */ | 365 | unsigned int len; /* length of the data to be submitted */ |
366 | unsigned int actual_len; /* actual bytes transfered on this td */ | 366 | unsigned int actual_len; /* actual bytes transferred on this td */ |
367 | enum fhci_ta_type type; /* transaction type */ | 367 | enum fhci_ta_type type; /* transaction type */ |
368 | u8 toggle; /* toggle for next trans. within this TD */ | 368 | u8 toggle; /* toggle for next trans. within this TD */ |
369 | u16 iso_index; /* ISO transaction index */ | 369 | u16 iso_index; /* ISO transaction index */ |
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c new file mode 100644 index 000000000000..79a66d622f9c --- /dev/null +++ b/drivers/usb/host/fsl-mph-dr-of.c | |||
@@ -0,0 +1,313 @@ | |||
1 | /* | ||
2 | * Setup platform devices needed by the Freescale multi-port host | ||
3 | * and/or dual-role USB controller modules based on the description | ||
4 | * in flat device tree. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/platform_device.h> | ||
14 | #include <linux/fsl_devices.h> | ||
15 | #include <linux/err.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/of_platform.h> | ||
18 | #include <linux/clk.h> | ||
19 | |||
20 | struct fsl_usb2_dev_data { | ||
21 | char *dr_mode; /* controller mode */ | ||
22 | char *drivers[3]; /* drivers to instantiate for this mode */ | ||
23 | enum fsl_usb2_operating_modes op_mode; /* operating mode */ | ||
24 | }; | ||
25 | |||
26 | struct fsl_usb2_dev_data dr_mode_data[] __devinitdata = { | ||
27 | { | ||
28 | .dr_mode = "host", | ||
29 | .drivers = { "fsl-ehci", NULL, NULL, }, | ||
30 | .op_mode = FSL_USB2_DR_HOST, | ||
31 | }, | ||
32 | { | ||
33 | .dr_mode = "otg", | ||
34 | .drivers = { "fsl-usb2-otg", "fsl-ehci", "fsl-usb2-udc", }, | ||
35 | .op_mode = FSL_USB2_DR_OTG, | ||
36 | }, | ||
37 | { | ||
38 | .dr_mode = "peripheral", | ||
39 | .drivers = { "fsl-usb2-udc", NULL, NULL, }, | ||
40 | .op_mode = FSL_USB2_DR_DEVICE, | ||
41 | }, | ||
42 | }; | ||
43 | |||
44 | struct fsl_usb2_dev_data * __devinit get_dr_mode_data(struct device_node *np) | ||
45 | { | ||
46 | const unsigned char *prop; | ||
47 | int i; | ||
48 | |||
49 | prop = of_get_property(np, "dr_mode", NULL); | ||
50 | if (prop) { | ||
51 | for (i = 0; i < ARRAY_SIZE(dr_mode_data); i++) { | ||
52 | if (!strcmp(prop, dr_mode_data[i].dr_mode)) | ||
53 | return &dr_mode_data[i]; | ||
54 | } | ||
55 | } | ||
56 | pr_warn("%s: Invalid 'dr_mode' property, fallback to host mode\n", | ||
57 | np->full_name); | ||
58 | return &dr_mode_data[0]; /* mode not specified, use host */ | ||
59 | } | ||
60 | |||
61 | static enum fsl_usb2_phy_modes __devinit determine_usb_phy(const char *phy_type) | ||
62 | { | ||
63 | if (!phy_type) | ||
64 | return FSL_USB2_PHY_NONE; | ||
65 | if (!strcasecmp(phy_type, "ulpi")) | ||
66 | return FSL_USB2_PHY_ULPI; | ||
67 | if (!strcasecmp(phy_type, "utmi")) | ||
68 | return FSL_USB2_PHY_UTMI; | ||
69 | if (!strcasecmp(phy_type, "utmi_wide")) | ||
70 | return FSL_USB2_PHY_UTMI_WIDE; | ||
71 | if (!strcasecmp(phy_type, "serial")) | ||
72 | return FSL_USB2_PHY_SERIAL; | ||
73 | |||
74 | return FSL_USB2_PHY_NONE; | ||
75 | } | ||
76 | |||
77 | struct platform_device * __devinit fsl_usb2_device_register( | ||
78 | struct platform_device *ofdev, | ||
79 | struct fsl_usb2_platform_data *pdata, | ||
80 | const char *name, int id) | ||
81 | { | ||
82 | struct platform_device *pdev; | ||
83 | const struct resource *res = ofdev->resource; | ||
84 | unsigned int num = ofdev->num_resources; | ||
85 | int retval; | ||
86 | |||
87 | pdev = platform_device_alloc(name, id); | ||
88 | if (!pdev) { | ||
89 | retval = -ENOMEM; | ||
90 | goto error; | ||
91 | } | ||
92 | |||
93 | pdev->dev.parent = &ofdev->dev; | ||
94 | |||
95 | pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask; | ||
96 | pdev->dev.dma_mask = &pdev->archdata.dma_mask; | ||
97 | *pdev->dev.dma_mask = *ofdev->dev.dma_mask; | ||
98 | |||
99 | retval = platform_device_add_data(pdev, pdata, sizeof(*pdata)); | ||
100 | if (retval) | ||
101 | goto error; | ||
102 | |||
103 | if (num) { | ||
104 | retval = platform_device_add_resources(pdev, res, num); | ||
105 | if (retval) | ||
106 | goto error; | ||
107 | } | ||
108 | |||
109 | retval = platform_device_add(pdev); | ||
110 | if (retval) | ||
111 | goto error; | ||
112 | |||
113 | return pdev; | ||
114 | |||
115 | error: | ||
116 | platform_device_put(pdev); | ||
117 | return ERR_PTR(retval); | ||
118 | } | ||
119 | |||
120 | static const struct of_device_id fsl_usb2_mph_dr_of_match[]; | ||
121 | |||
122 | static int __devinit fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev) | ||
123 | { | ||
124 | struct device_node *np = ofdev->dev.of_node; | ||
125 | struct platform_device *usb_dev; | ||
126 | struct fsl_usb2_platform_data data, *pdata; | ||
127 | struct fsl_usb2_dev_data *dev_data; | ||
128 | const struct of_device_id *match; | ||
129 | const unsigned char *prop; | ||
130 | static unsigned int idx; | ||
131 | int i; | ||
132 | |||
133 | if (!of_device_is_available(np)) | ||
134 | return -ENODEV; | ||
135 | |||
136 | match = of_match_device(fsl_usb2_mph_dr_of_match, &ofdev->dev); | ||
137 | if (!match) | ||
138 | return -ENODEV; | ||
139 | |||
140 | pdata = &data; | ||
141 | if (match->data) | ||
142 | memcpy(pdata, match->data, sizeof(data)); | ||
143 | else | ||
144 | memset(pdata, 0, sizeof(data)); | ||
145 | |||
146 | dev_data = get_dr_mode_data(np); | ||
147 | |||
148 | if (of_device_is_compatible(np, "fsl-usb2-mph")) { | ||
149 | if (of_get_property(np, "port0", NULL)) | ||
150 | pdata->port_enables |= FSL_USB2_PORT0_ENABLED; | ||
151 | |||
152 | if (of_get_property(np, "port1", NULL)) | ||
153 | pdata->port_enables |= FSL_USB2_PORT1_ENABLED; | ||
154 | |||
155 | pdata->operating_mode = FSL_USB2_MPH_HOST; | ||
156 | } else { | ||
157 | if (of_get_property(np, "fsl,invert-drvvbus", NULL)) | ||
158 | pdata->invert_drvvbus = 1; | ||
159 | |||
160 | if (of_get_property(np, "fsl,invert-pwr-fault", NULL)) | ||
161 | pdata->invert_pwr_fault = 1; | ||
162 | |||
163 | /* setup mode selected in the device tree */ | ||
164 | pdata->operating_mode = dev_data->op_mode; | ||
165 | } | ||
166 | |||
167 | prop = of_get_property(np, "phy_type", NULL); | ||
168 | pdata->phy_mode = determine_usb_phy(prop); | ||
169 | |||
170 | for (i = 0; i < ARRAY_SIZE(dev_data->drivers); i++) { | ||
171 | if (!dev_data->drivers[i]) | ||
172 | continue; | ||
173 | usb_dev = fsl_usb2_device_register(ofdev, pdata, | ||
174 | dev_data->drivers[i], idx); | ||
175 | if (IS_ERR(usb_dev)) { | ||
176 | dev_err(&ofdev->dev, "Can't register usb device\n"); | ||
177 | return PTR_ERR(usb_dev); | ||
178 | } | ||
179 | } | ||
180 | idx++; | ||
181 | return 0; | ||
182 | } | ||
183 | |||
184 | static int __devexit __unregister_subdev(struct device *dev, void *d) | ||
185 | { | ||
186 | platform_device_unregister(to_platform_device(dev)); | ||
187 | return 0; | ||
188 | } | ||
189 | |||
190 | static int __devexit fsl_usb2_mph_dr_of_remove(struct platform_device *ofdev) | ||
191 | { | ||
192 | device_for_each_child(&ofdev->dev, NULL, __unregister_subdev); | ||
193 | return 0; | ||
194 | } | ||
195 | |||
196 | #ifdef CONFIG_PPC_MPC512x | ||
197 | |||
198 | #define USBGENCTRL 0x200 /* NOTE: big endian */ | ||
199 | #define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ | ||
200 | #define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ | ||
201 | #define GC_PPP (1 << 3) /* Inv. Port Power Polarity */ | ||
202 | #define GC_PFP (1 << 2) /* Inv. Power Fault Polarity */ | ||
203 | #define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ | ||
204 | #define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ | ||
205 | |||
206 | #define ISIPHYCTRL 0x204 /* NOTE: big endian */ | ||
207 | #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ | ||
208 | #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ | ||
209 | #define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ | ||
210 | #define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ | ||
211 | #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ | ||
212 | |||
213 | int fsl_usb2_mpc5121_init(struct platform_device *pdev) | ||
214 | { | ||
215 | struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; | ||
216 | struct clk *clk; | ||
217 | char clk_name[10]; | ||
218 | int base, clk_num; | ||
219 | |||
220 | base = pdev->resource->start & 0xf000; | ||
221 | if (base == 0x3000) | ||
222 | clk_num = 1; | ||
223 | else if (base == 0x4000) | ||
224 | clk_num = 2; | ||
225 | else | ||
226 | return -ENODEV; | ||
227 | |||
228 | snprintf(clk_name, sizeof(clk_name), "usb%d_clk", clk_num); | ||
229 | clk = clk_get(&pdev->dev, clk_name); | ||
230 | if (IS_ERR(clk)) { | ||
231 | dev_err(&pdev->dev, "failed to get clk\n"); | ||
232 | return PTR_ERR(clk); | ||
233 | } | ||
234 | |||
235 | clk_enable(clk); | ||
236 | pdata->clk = clk; | ||
237 | |||
238 | if (pdata->phy_mode == FSL_USB2_PHY_UTMI_WIDE) { | ||
239 | u32 reg = 0; | ||
240 | |||
241 | if (pdata->invert_drvvbus) | ||
242 | reg |= GC_PPP; | ||
243 | |||
244 | if (pdata->invert_pwr_fault) | ||
245 | reg |= GC_PFP; | ||
246 | |||
247 | out_be32(pdata->regs + ISIPHYCTRL, PHYCTRL_PHYE | PHYCTRL_PXE); | ||
248 | out_be32(pdata->regs + USBGENCTRL, reg); | ||
249 | } | ||
250 | return 0; | ||
251 | } | ||
252 | |||
253 | static void fsl_usb2_mpc5121_exit(struct platform_device *pdev) | ||
254 | { | ||
255 | struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; | ||
256 | |||
257 | pdata->regs = NULL; | ||
258 | |||
259 | if (pdata->clk) { | ||
260 | clk_disable(pdata->clk); | ||
261 | clk_put(pdata->clk); | ||
262 | } | ||
263 | } | ||
264 | |||
265 | static struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = { | ||
266 | .big_endian_desc = 1, | ||
267 | .big_endian_mmio = 1, | ||
268 | .es = 1, | ||
269 | .have_sysif_regs = 0, | ||
270 | .le_setup_buf = 1, | ||
271 | .init = fsl_usb2_mpc5121_init, | ||
272 | .exit = fsl_usb2_mpc5121_exit, | ||
273 | }; | ||
274 | #endif /* CONFIG_PPC_MPC512x */ | ||
275 | |||
276 | static struct fsl_usb2_platform_data fsl_usb2_mpc8xxx_pd = { | ||
277 | .have_sysif_regs = 1, | ||
278 | }; | ||
279 | |||
280 | static const struct of_device_id fsl_usb2_mph_dr_of_match[] = { | ||
281 | { .compatible = "fsl-usb2-mph", .data = &fsl_usb2_mpc8xxx_pd, }, | ||
282 | { .compatible = "fsl-usb2-dr", .data = &fsl_usb2_mpc8xxx_pd, }, | ||
283 | #ifdef CONFIG_PPC_MPC512x | ||
284 | { .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, }, | ||
285 | #endif | ||
286 | {}, | ||
287 | }; | ||
288 | |||
289 | static struct platform_driver fsl_usb2_mph_dr_driver = { | ||
290 | .driver = { | ||
291 | .name = "fsl-usb2-mph-dr", | ||
292 | .owner = THIS_MODULE, | ||
293 | .of_match_table = fsl_usb2_mph_dr_of_match, | ||
294 | }, | ||
295 | .probe = fsl_usb2_mph_dr_of_probe, | ||
296 | .remove = __devexit_p(fsl_usb2_mph_dr_of_remove), | ||
297 | }; | ||
298 | |||
299 | static int __init fsl_usb2_mph_dr_init(void) | ||
300 | { | ||
301 | return platform_driver_register(&fsl_usb2_mph_dr_driver); | ||
302 | } | ||
303 | module_init(fsl_usb2_mph_dr_init); | ||
304 | |||
305 | static void __exit fsl_usb2_mph_dr_exit(void) | ||
306 | { | ||
307 | platform_driver_unregister(&fsl_usb2_mph_dr_driver); | ||
308 | } | ||
309 | module_exit(fsl_usb2_mph_dr_exit); | ||
310 | |||
311 | MODULE_DESCRIPTION("FSL MPH DR OF devices driver"); | ||
312 | MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); | ||
313 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/usb/host/imx21-dbg.c b/drivers/usb/host/imx21-dbg.c index 512f647448ca..6d7533427163 100644 --- a/drivers/usb/host/imx21-dbg.c +++ b/drivers/usb/host/imx21-dbg.c | |||
@@ -384,7 +384,7 @@ static void debug_isoc_show_one(struct seq_file *s, | |||
384 | seq_printf(s, "%s %d:\n" | 384 | seq_printf(s, "%s %d:\n" |
385 | "cc=0X%02X\n" | 385 | "cc=0X%02X\n" |
386 | "scheduled frame %d (%d)\n" | 386 | "scheduled frame %d (%d)\n" |
387 | "submittted frame %d (%d)\n" | 387 | "submitted frame %d (%d)\n" |
388 | "completed frame %d (%d)\n" | 388 | "completed frame %d (%d)\n" |
389 | "requested length=%d\n" | 389 | "requested length=%d\n" |
390 | "completed length=%d\n\n", | 390 | "completed length=%d\n\n", |
diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c index 3e5630369c31..af05718bdc73 100644 --- a/drivers/usb/host/imx21-hcd.c +++ b/drivers/usb/host/imx21-hcd.c | |||
@@ -27,8 +27,8 @@ | |||
27 | * * 32 transfer descriptors (called ETDs) | 27 | * * 32 transfer descriptors (called ETDs) |
28 | * * 4Kb of Data memory | 28 | * * 4Kb of Data memory |
29 | * | 29 | * |
30 | * The data memory is shared between the host and fuction controlers | 30 | * The data memory is shared between the host and function controllers |
31 | * (but this driver only supports the host controler) | 31 | * (but this driver only supports the host controller) |
32 | * | 32 | * |
33 | * So setting up a transfer involves: | 33 | * So setting up a transfer involves: |
34 | * * Allocating a ETD | 34 | * * Allocating a ETD |
@@ -57,6 +57,7 @@ | |||
57 | #include <linux/slab.h> | 57 | #include <linux/slab.h> |
58 | #include <linux/usb.h> | 58 | #include <linux/usb.h> |
59 | #include <linux/usb/hcd.h> | 59 | #include <linux/usb/hcd.h> |
60 | #include <linux/dma-mapping.h> | ||
60 | 61 | ||
61 | #include "imx21-hcd.h" | 62 | #include "imx21-hcd.h" |
62 | 63 | ||
@@ -136,9 +137,18 @@ static int imx21_hc_get_frame(struct usb_hcd *hcd) | |||
136 | return wrap_frame(readl(imx21->regs + USBH_FRMNUB)); | 137 | return wrap_frame(readl(imx21->regs + USBH_FRMNUB)); |
137 | } | 138 | } |
138 | 139 | ||
140 | static inline bool unsuitable_for_dma(dma_addr_t addr) | ||
141 | { | ||
142 | return (addr & 3) != 0; | ||
143 | } | ||
139 | 144 | ||
140 | #include "imx21-dbg.c" | 145 | #include "imx21-dbg.c" |
141 | 146 | ||
147 | static void nonisoc_urb_completed_for_etd( | ||
148 | struct imx21 *imx21, struct etd_priv *etd, int status); | ||
149 | static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb); | ||
150 | static void free_dmem(struct imx21 *imx21, struct etd_priv *etd); | ||
151 | |||
142 | /* =========================================== */ | 152 | /* =========================================== */ |
143 | /* ETD management */ | 153 | /* ETD management */ |
144 | /* =========================================== */ | 154 | /* =========================================== */ |
@@ -185,7 +195,8 @@ static void reset_etd(struct imx21 *imx21, int num) | |||
185 | etd_writel(imx21, num, i, 0); | 195 | etd_writel(imx21, num, i, 0); |
186 | etd->urb = NULL; | 196 | etd->urb = NULL; |
187 | etd->ep = NULL; | 197 | etd->ep = NULL; |
188 | etd->td = NULL;; | 198 | etd->td = NULL; |
199 | etd->bounce_buffer = NULL; | ||
189 | } | 200 | } |
190 | 201 | ||
191 | static void free_etd(struct imx21 *imx21, int num) | 202 | static void free_etd(struct imx21 *imx21, int num) |
@@ -221,26 +232,94 @@ static void setup_etd_dword0(struct imx21 *imx21, | |||
221 | ((u32) maxpacket << DW0_MAXPKTSIZ)); | 232 | ((u32) maxpacket << DW0_MAXPKTSIZ)); |
222 | } | 233 | } |
223 | 234 | ||
224 | static void activate_etd(struct imx21 *imx21, | 235 | /** |
225 | int etd_num, dma_addr_t dma, u8 dir) | 236 | * Copy buffer to data controller data memory. |
237 | * We cannot use memcpy_toio() because the hardware requires 32bit writes | ||
238 | */ | ||
239 | static void copy_to_dmem( | ||
240 | struct imx21 *imx21, int dmem_offset, void *src, int count) | ||
241 | { | ||
242 | void __iomem *dmem = imx21->regs + USBOTG_DMEM + dmem_offset; | ||
243 | u32 word = 0; | ||
244 | u8 *p = src; | ||
245 | int byte = 0; | ||
246 | int i; | ||
247 | |||
248 | for (i = 0; i < count; i++) { | ||
249 | byte = i % 4; | ||
250 | word += (*p++ << (byte * 8)); | ||
251 | if (byte == 3) { | ||
252 | writel(word, dmem); | ||
253 | dmem += 4; | ||
254 | word = 0; | ||
255 | } | ||
256 | } | ||
257 | |||
258 | if (count && byte != 3) | ||
259 | writel(word, dmem); | ||
260 | } | ||
261 | |||
262 | static void activate_etd(struct imx21 *imx21, int etd_num, u8 dir) | ||
226 | { | 263 | { |
227 | u32 etd_mask = 1 << etd_num; | 264 | u32 etd_mask = 1 << etd_num; |
228 | struct etd_priv *etd = &imx21->etd[etd_num]; | 265 | struct etd_priv *etd = &imx21->etd[etd_num]; |
229 | 266 | ||
267 | if (etd->dma_handle && unsuitable_for_dma(etd->dma_handle)) { | ||
268 | /* For non aligned isoc the condition below is always true */ | ||
269 | if (etd->len <= etd->dmem_size) { | ||
270 | /* Fits into data memory, use PIO */ | ||
271 | if (dir != TD_DIR_IN) { | ||
272 | copy_to_dmem(imx21, | ||
273 | etd->dmem_offset, | ||
274 | etd->cpu_buffer, etd->len); | ||
275 | } | ||
276 | etd->dma_handle = 0; | ||
277 | |||
278 | } else { | ||
279 | /* Too big for data memory, use bounce buffer */ | ||
280 | enum dma_data_direction dmadir; | ||
281 | |||
282 | if (dir == TD_DIR_IN) { | ||
283 | dmadir = DMA_FROM_DEVICE; | ||
284 | etd->bounce_buffer = kmalloc(etd->len, | ||
285 | GFP_ATOMIC); | ||
286 | } else { | ||
287 | dmadir = DMA_TO_DEVICE; | ||
288 | etd->bounce_buffer = kmemdup(etd->cpu_buffer, | ||
289 | etd->len, | ||
290 | GFP_ATOMIC); | ||
291 | } | ||
292 | if (!etd->bounce_buffer) { | ||
293 | dev_err(imx21->dev, "failed bounce alloc\n"); | ||
294 | goto err_bounce_alloc; | ||
295 | } | ||
296 | |||
297 | etd->dma_handle = | ||
298 | dma_map_single(imx21->dev, | ||
299 | etd->bounce_buffer, | ||
300 | etd->len, | ||
301 | dmadir); | ||
302 | if (dma_mapping_error(imx21->dev, etd->dma_handle)) { | ||
303 | dev_err(imx21->dev, "failed bounce map\n"); | ||
304 | goto err_bounce_map; | ||
305 | } | ||
306 | } | ||
307 | } | ||
308 | |||
230 | clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask); | 309 | clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask); |
231 | set_register_bits(imx21, USBH_ETDDONEEN, etd_mask); | 310 | set_register_bits(imx21, USBH_ETDDONEEN, etd_mask); |
232 | clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); | 311 | clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); |
233 | clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); | 312 | clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); |
234 | 313 | ||
235 | if (dma) { | 314 | if (etd->dma_handle) { |
236 | set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask); | 315 | set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask); |
237 | clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask); | 316 | clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask); |
238 | clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask); | 317 | clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask); |
239 | writel(dma, imx21->regs + USB_ETDSMSA(etd_num)); | 318 | writel(etd->dma_handle, imx21->regs + USB_ETDSMSA(etd_num)); |
240 | set_register_bits(imx21, USB_ETDDMAEN, etd_mask); | 319 | set_register_bits(imx21, USB_ETDDMAEN, etd_mask); |
241 | } else { | 320 | } else { |
242 | if (dir != TD_DIR_IN) { | 321 | if (dir != TD_DIR_IN) { |
243 | /* need to set for ZLP */ | 322 | /* need to set for ZLP and PIO */ |
244 | set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); | 323 | set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); |
245 | set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); | 324 | set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); |
246 | } | 325 | } |
@@ -263,6 +342,14 @@ static void activate_etd(struct imx21 *imx21, | |||
263 | 342 | ||
264 | etd->active_count = 1; | 343 | etd->active_count = 1; |
265 | writel(etd_mask, imx21->regs + USBH_ETDENSET); | 344 | writel(etd_mask, imx21->regs + USBH_ETDENSET); |
345 | return; | ||
346 | |||
347 | err_bounce_map: | ||
348 | kfree(etd->bounce_buffer); | ||
349 | |||
350 | err_bounce_alloc: | ||
351 | free_dmem(imx21, etd); | ||
352 | nonisoc_urb_completed_for_etd(imx21, etd, -ENOMEM); | ||
266 | } | 353 | } |
267 | 354 | ||
268 | /* =========================================== */ | 355 | /* =========================================== */ |
@@ -323,16 +410,23 @@ static void activate_queued_etd(struct imx21 *imx21, | |||
323 | etd_writel(imx21, etd_num, 1, | 410 | etd_writel(imx21, etd_num, 1, |
324 | ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset); | 411 | ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset); |
325 | 412 | ||
413 | etd->dmem_offset = dmem_offset; | ||
326 | urb_priv->active = 1; | 414 | urb_priv->active = 1; |
327 | activate_etd(imx21, etd_num, etd->dma_handle, dir); | 415 | activate_etd(imx21, etd_num, dir); |
328 | } | 416 | } |
329 | 417 | ||
330 | static void free_dmem(struct imx21 *imx21, int offset) | 418 | static void free_dmem(struct imx21 *imx21, struct etd_priv *etd) |
331 | { | 419 | { |
332 | struct imx21_dmem_area *area; | 420 | struct imx21_dmem_area *area; |
333 | struct etd_priv *etd, *tmp; | 421 | struct etd_priv *tmp; |
334 | int found = 0; | 422 | int found = 0; |
423 | int offset; | ||
335 | 424 | ||
425 | if (!etd->dmem_size) | ||
426 | return; | ||
427 | etd->dmem_size = 0; | ||
428 | |||
429 | offset = etd->dmem_offset; | ||
336 | list_for_each_entry(area, &imx21->dmem_list, list) { | 430 | list_for_each_entry(area, &imx21->dmem_list, list) { |
337 | if (area->offset == offset) { | 431 | if (area->offset == offset) { |
338 | debug_dmem_freed(imx21, area->size); | 432 | debug_dmem_freed(imx21, area->size); |
@@ -378,20 +472,23 @@ static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep) | |||
378 | /* =========================================== */ | 472 | /* =========================================== */ |
379 | /* End handling */ | 473 | /* End handling */ |
380 | /* =========================================== */ | 474 | /* =========================================== */ |
381 | static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb); | ||
382 | 475 | ||
383 | /* Endpoint now idle - release it's ETD(s) or asssign to queued request */ | 476 | /* Endpoint now idle - release it's ETD(s) or asssign to queued request */ |
384 | static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv) | 477 | static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv) |
385 | { | 478 | { |
386 | int etd_num; | ||
387 | int i; | 479 | int i; |
388 | 480 | ||
389 | for (i = 0; i < NUM_ISO_ETDS; i++) { | 481 | for (i = 0; i < NUM_ISO_ETDS; i++) { |
390 | etd_num = ep_priv->etd[i]; | 482 | int etd_num = ep_priv->etd[i]; |
483 | struct etd_priv *etd; | ||
391 | if (etd_num < 0) | 484 | if (etd_num < 0) |
392 | continue; | 485 | continue; |
393 | 486 | ||
487 | etd = &imx21->etd[etd_num]; | ||
394 | ep_priv->etd[i] = -1; | 488 | ep_priv->etd[i] = -1; |
489 | |||
490 | free_dmem(imx21, etd); /* for isoc */ | ||
491 | |||
395 | if (list_empty(&imx21->queue_for_etd)) { | 492 | if (list_empty(&imx21->queue_for_etd)) { |
396 | free_etd(imx21, etd_num); | 493 | free_etd(imx21, etd_num); |
397 | continue; | 494 | continue; |
@@ -437,6 +534,24 @@ __acquires(imx21->lock) | |||
437 | ep_idle(imx21, ep_priv); | 534 | ep_idle(imx21, ep_priv); |
438 | } | 535 | } |
439 | 536 | ||
537 | static void nonisoc_urb_completed_for_etd( | ||
538 | struct imx21 *imx21, struct etd_priv *etd, int status) | ||
539 | { | ||
540 | struct usb_host_endpoint *ep = etd->ep; | ||
541 | |||
542 | urb_done(imx21->hcd, etd->urb, status); | ||
543 | etd->urb = NULL; | ||
544 | |||
545 | if (!list_empty(&ep->urb_list)) { | ||
546 | struct urb *urb = list_first_entry( | ||
547 | &ep->urb_list, struct urb, urb_list); | ||
548 | |||
549 | dev_vdbg(imx21->dev, "next URB %p\n", urb); | ||
550 | schedule_nonisoc_etd(imx21, urb); | ||
551 | } | ||
552 | } | ||
553 | |||
554 | |||
440 | /* =========================================== */ | 555 | /* =========================================== */ |
441 | /* ISOC Handling ... */ | 556 | /* ISOC Handling ... */ |
442 | /* =========================================== */ | 557 | /* =========================================== */ |
@@ -489,6 +604,8 @@ too_late: | |||
489 | etd->ep = td->ep; | 604 | etd->ep = td->ep; |
490 | etd->urb = td->urb; | 605 | etd->urb = td->urb; |
491 | etd->len = td->len; | 606 | etd->len = td->len; |
607 | etd->dma_handle = td->dma_handle; | ||
608 | etd->cpu_buffer = td->cpu_buffer; | ||
492 | 609 | ||
493 | debug_isoc_submitted(imx21, cur_frame, td); | 610 | debug_isoc_submitted(imx21, cur_frame, td); |
494 | 611 | ||
@@ -502,16 +619,17 @@ too_late: | |||
502 | (TD_NOTACCESSED << DW3_COMPCODE0) | | 619 | (TD_NOTACCESSED << DW3_COMPCODE0) | |
503 | (td->len << DW3_PKTLEN0)); | 620 | (td->len << DW3_PKTLEN0)); |
504 | 621 | ||
505 | activate_etd(imx21, etd_num, td->data, dir); | 622 | activate_etd(imx21, etd_num, dir); |
506 | } | 623 | } |
507 | } | 624 | } |
508 | 625 | ||
509 | static void isoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num) | 626 | static void isoc_etd_done(struct usb_hcd *hcd, int etd_num) |
510 | { | 627 | { |
511 | struct imx21 *imx21 = hcd_to_imx21(hcd); | 628 | struct imx21 *imx21 = hcd_to_imx21(hcd); |
512 | int etd_mask = 1 << etd_num; | 629 | int etd_mask = 1 << etd_num; |
513 | struct urb_priv *urb_priv = urb->hcpriv; | ||
514 | struct etd_priv *etd = imx21->etd + etd_num; | 630 | struct etd_priv *etd = imx21->etd + etd_num; |
631 | struct urb *urb = etd->urb; | ||
632 | struct urb_priv *urb_priv = urb->hcpriv; | ||
515 | struct td *td = etd->td; | 633 | struct td *td = etd->td; |
516 | struct usb_host_endpoint *ep = etd->ep; | 634 | struct usb_host_endpoint *ep = etd->ep; |
517 | int isoc_index = td->isoc_index; | 635 | int isoc_index = td->isoc_index; |
@@ -545,8 +663,13 @@ static void isoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num) | |||
545 | bytes_xfrd, td->len, urb, etd_num, isoc_index); | 663 | bytes_xfrd, td->len, urb, etd_num, isoc_index); |
546 | } | 664 | } |
547 | 665 | ||
548 | if (dir_in) | 666 | if (dir_in) { |
549 | clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); | 667 | clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); |
668 | if (!etd->dma_handle) | ||
669 | memcpy_fromio(etd->cpu_buffer, | ||
670 | imx21->regs + USBOTG_DMEM + etd->dmem_offset, | ||
671 | bytes_xfrd); | ||
672 | } | ||
550 | 673 | ||
551 | urb->actual_length += bytes_xfrd; | 674 | urb->actual_length += bytes_xfrd; |
552 | urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd; | 675 | urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd; |
@@ -569,30 +692,43 @@ static struct ep_priv *alloc_isoc_ep( | |||
569 | int i; | 692 | int i; |
570 | 693 | ||
571 | ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC); | 694 | ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC); |
572 | if (ep_priv == NULL) | 695 | if (!ep_priv) |
573 | return NULL; | 696 | return NULL; |
574 | 697 | ||
575 | /* Allocate the ETDs */ | 698 | for (i = 0; i < NUM_ISO_ETDS; i++) |
576 | for (i = 0; i < NUM_ISO_ETDS; i++) { | 699 | ep_priv->etd[i] = -1; |
577 | ep_priv->etd[i] = alloc_etd(imx21); | ||
578 | if (ep_priv->etd[i] < 0) { | ||
579 | int j; | ||
580 | dev_err(imx21->dev, "isoc: Couldn't allocate etd\n"); | ||
581 | for (j = 0; j < i; j++) | ||
582 | free_etd(imx21, ep_priv->etd[j]); | ||
583 | goto alloc_etd_failed; | ||
584 | } | ||
585 | imx21->etd[ep_priv->etd[i]].ep = ep; | ||
586 | } | ||
587 | 700 | ||
588 | INIT_LIST_HEAD(&ep_priv->td_list); | 701 | INIT_LIST_HEAD(&ep_priv->td_list); |
589 | ep_priv->ep = ep; | 702 | ep_priv->ep = ep; |
590 | ep->hcpriv = ep_priv; | 703 | ep->hcpriv = ep_priv; |
591 | return ep_priv; | 704 | return ep_priv; |
705 | } | ||
706 | |||
707 | static int alloc_isoc_etds(struct imx21 *imx21, struct ep_priv *ep_priv) | ||
708 | { | ||
709 | int i, j; | ||
710 | int etd_num; | ||
711 | |||
712 | /* Allocate the ETDs if required */ | ||
713 | for (i = 0; i < NUM_ISO_ETDS; i++) { | ||
714 | if (ep_priv->etd[i] < 0) { | ||
715 | etd_num = alloc_etd(imx21); | ||
716 | if (etd_num < 0) | ||
717 | goto alloc_etd_failed; | ||
718 | |||
719 | ep_priv->etd[i] = etd_num; | ||
720 | imx21->etd[etd_num].ep = ep_priv->ep; | ||
721 | } | ||
722 | } | ||
723 | return 0; | ||
592 | 724 | ||
593 | alloc_etd_failed: | 725 | alloc_etd_failed: |
594 | kfree(ep_priv); | 726 | dev_err(imx21->dev, "isoc: Couldn't allocate etd\n"); |
595 | return NULL; | 727 | for (j = 0; j < i; j++) { |
728 | free_etd(imx21, ep_priv->etd[j]); | ||
729 | ep_priv->etd[j] = -1; | ||
730 | } | ||
731 | return -ENOMEM; | ||
596 | } | 732 | } |
597 | 733 | ||
598 | static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd, | 734 | static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd, |
@@ -632,6 +768,10 @@ static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd, | |||
632 | ep_priv = ep->hcpriv; | 768 | ep_priv = ep->hcpriv; |
633 | } | 769 | } |
634 | 770 | ||
771 | ret = alloc_isoc_etds(imx21, ep_priv); | ||
772 | if (ret) | ||
773 | goto alloc_etd_failed; | ||
774 | |||
635 | ret = usb_hcd_link_urb_to_ep(hcd, urb); | 775 | ret = usb_hcd_link_urb_to_ep(hcd, urb); |
636 | if (ret) | 776 | if (ret) |
637 | goto link_failed; | 777 | goto link_failed; |
@@ -688,12 +828,14 @@ static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd, | |||
688 | /* set up transfers */ | 828 | /* set up transfers */ |
689 | td = urb_priv->isoc_td; | 829 | td = urb_priv->isoc_td; |
690 | for (i = 0; i < urb->number_of_packets; i++, td++) { | 830 | for (i = 0; i < urb->number_of_packets; i++, td++) { |
831 | unsigned int offset = urb->iso_frame_desc[i].offset; | ||
691 | td->ep = ep; | 832 | td->ep = ep; |
692 | td->urb = urb; | 833 | td->urb = urb; |
693 | td->len = urb->iso_frame_desc[i].length; | 834 | td->len = urb->iso_frame_desc[i].length; |
694 | td->isoc_index = i; | 835 | td->isoc_index = i; |
695 | td->frame = wrap_frame(urb->start_frame + urb->interval * i); | 836 | td->frame = wrap_frame(urb->start_frame + urb->interval * i); |
696 | td->data = urb->transfer_dma + urb->iso_frame_desc[i].offset; | 837 | td->dma_handle = urb->transfer_dma + offset; |
838 | td->cpu_buffer = urb->transfer_buffer + offset; | ||
697 | list_add_tail(&td->list, &ep_priv->td_list); | 839 | list_add_tail(&td->list, &ep_priv->td_list); |
698 | } | 840 | } |
699 | 841 | ||
@@ -711,6 +853,7 @@ alloc_dmem_failed: | |||
711 | usb_hcd_unlink_urb_from_ep(hcd, urb); | 853 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
712 | 854 | ||
713 | link_failed: | 855 | link_failed: |
856 | alloc_etd_failed: | ||
714 | alloc_ep_failed: | 857 | alloc_ep_failed: |
715 | spin_unlock_irqrestore(&imx21->lock, flags); | 858 | spin_unlock_irqrestore(&imx21->lock, flags); |
716 | kfree(urb_priv->isoc_td); | 859 | kfree(urb_priv->isoc_td); |
@@ -734,9 +877,7 @@ static void dequeue_isoc_urb(struct imx21 *imx21, | |||
734 | struct etd_priv *etd = imx21->etd + etd_num; | 877 | struct etd_priv *etd = imx21->etd + etd_num; |
735 | 878 | ||
736 | reset_etd(imx21, etd_num); | 879 | reset_etd(imx21, etd_num); |
737 | if (etd->dmem_size) | 880 | free_dmem(imx21, etd); |
738 | free_dmem(imx21, etd->dmem_offset); | ||
739 | etd->dmem_size = 0; | ||
740 | } | 881 | } |
741 | } | 882 | } |
742 | } | 883 | } |
@@ -761,7 +902,6 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb) | |||
761 | int state = urb_priv->state; | 902 | int state = urb_priv->state; |
762 | int etd_num = ep_priv->etd[0]; | 903 | int etd_num = ep_priv->etd[0]; |
763 | struct etd_priv *etd; | 904 | struct etd_priv *etd; |
764 | int dmem_offset; | ||
765 | u32 count; | 905 | u32 count; |
766 | u16 etd_buf_size; | 906 | u16 etd_buf_size; |
767 | u16 maxpacket; | 907 | u16 maxpacket; |
@@ -786,13 +926,16 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb) | |||
786 | if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) { | 926 | if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) { |
787 | if (state == US_CTRL_SETUP) { | 927 | if (state == US_CTRL_SETUP) { |
788 | dir = TD_DIR_SETUP; | 928 | dir = TD_DIR_SETUP; |
929 | if (unsuitable_for_dma(urb->setup_dma)) | ||
930 | usb_hcd_unmap_urb_setup_for_dma(imx21->hcd, | ||
931 | urb); | ||
789 | etd->dma_handle = urb->setup_dma; | 932 | etd->dma_handle = urb->setup_dma; |
933 | etd->cpu_buffer = urb->setup_packet; | ||
790 | bufround = 0; | 934 | bufround = 0; |
791 | count = 8; | 935 | count = 8; |
792 | datatoggle = TD_TOGGLE_DATA0; | 936 | datatoggle = TD_TOGGLE_DATA0; |
793 | } else { /* US_CTRL_ACK */ | 937 | } else { /* US_CTRL_ACK */ |
794 | dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT; | 938 | dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT; |
795 | etd->dma_handle = urb->transfer_dma; | ||
796 | bufround = 0; | 939 | bufround = 0; |
797 | count = 0; | 940 | count = 0; |
798 | datatoggle = TD_TOGGLE_DATA1; | 941 | datatoggle = TD_TOGGLE_DATA1; |
@@ -800,7 +943,11 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb) | |||
800 | } else { | 943 | } else { |
801 | dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN; | 944 | dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN; |
802 | bufround = (dir == TD_DIR_IN) ? 1 : 0; | 945 | bufround = (dir == TD_DIR_IN) ? 1 : 0; |
946 | if (unsuitable_for_dma(urb->transfer_dma)) | ||
947 | usb_hcd_unmap_urb_for_dma(imx21->hcd, urb); | ||
948 | |||
803 | etd->dma_handle = urb->transfer_dma; | 949 | etd->dma_handle = urb->transfer_dma; |
950 | etd->cpu_buffer = urb->transfer_buffer; | ||
804 | if (usb_pipebulk(pipe) && (state == US_BULK0)) | 951 | if (usb_pipebulk(pipe) && (state == US_BULK0)) |
805 | count = 0; | 952 | count = 0; |
806 | else | 953 | else |
@@ -855,8 +1002,8 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb) | |||
855 | 1002 | ||
856 | /* allocate x and y buffer space at once */ | 1003 | /* allocate x and y buffer space at once */ |
857 | etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket; | 1004 | etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket; |
858 | dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep); | 1005 | etd->dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep); |
859 | if (dmem_offset < 0) { | 1006 | if (etd->dmem_offset < 0) { |
860 | /* Setup everything we can in HW and update when we get DMEM */ | 1007 | /* Setup everything we can in HW and update when we get DMEM */ |
861 | etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16); | 1008 | etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16); |
862 | 1009 | ||
@@ -867,26 +1014,26 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb) | |||
867 | } | 1014 | } |
868 | 1015 | ||
869 | etd_writel(imx21, etd_num, 1, | 1016 | etd_writel(imx21, etd_num, 1, |
870 | (((u32) dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) | | 1017 | (((u32) etd->dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) | |
871 | (u32) dmem_offset); | 1018 | (u32) etd->dmem_offset); |
872 | 1019 | ||
873 | urb_priv->active = 1; | 1020 | urb_priv->active = 1; |
874 | 1021 | ||
875 | /* enable the ETD to kick off transfer */ | 1022 | /* enable the ETD to kick off transfer */ |
876 | dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n", | 1023 | dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n", |
877 | etd_num, count, dir != TD_DIR_IN ? "out" : "in"); | 1024 | etd_num, count, dir != TD_DIR_IN ? "out" : "in"); |
878 | activate_etd(imx21, etd_num, etd->dma_handle, dir); | 1025 | activate_etd(imx21, etd_num, dir); |
879 | 1026 | ||
880 | } | 1027 | } |
881 | 1028 | ||
882 | static void nonisoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num) | 1029 | static void nonisoc_etd_done(struct usb_hcd *hcd, int etd_num) |
883 | { | 1030 | { |
884 | struct imx21 *imx21 = hcd_to_imx21(hcd); | 1031 | struct imx21 *imx21 = hcd_to_imx21(hcd); |
885 | struct etd_priv *etd = &imx21->etd[etd_num]; | 1032 | struct etd_priv *etd = &imx21->etd[etd_num]; |
1033 | struct urb *urb = etd->urb; | ||
886 | u32 etd_mask = 1 << etd_num; | 1034 | u32 etd_mask = 1 << etd_num; |
887 | struct urb_priv *urb_priv = urb->hcpriv; | 1035 | struct urb_priv *urb_priv = urb->hcpriv; |
888 | int dir; | 1036 | int dir; |
889 | u16 xbufaddr; | ||
890 | int cc; | 1037 | int cc; |
891 | u32 bytes_xfrd; | 1038 | u32 bytes_xfrd; |
892 | int etd_done; | 1039 | int etd_done; |
@@ -894,7 +1041,6 @@ static void nonisoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num) | |||
894 | disactivate_etd(imx21, etd_num); | 1041 | disactivate_etd(imx21, etd_num); |
895 | 1042 | ||
896 | dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3; | 1043 | dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3; |
897 | xbufaddr = etd_readl(imx21, etd_num, 1) & 0xffff; | ||
898 | cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf; | 1044 | cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf; |
899 | bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff); | 1045 | bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff); |
900 | 1046 | ||
@@ -906,8 +1052,21 @@ static void nonisoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num) | |||
906 | if (dir == TD_DIR_IN) { | 1052 | if (dir == TD_DIR_IN) { |
907 | clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); | 1053 | clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); |
908 | clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); | 1054 | clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); |
1055 | |||
1056 | if (etd->bounce_buffer) { | ||
1057 | memcpy(etd->cpu_buffer, etd->bounce_buffer, bytes_xfrd); | ||
1058 | dma_unmap_single(imx21->dev, | ||
1059 | etd->dma_handle, etd->len, DMA_FROM_DEVICE); | ||
1060 | } else if (!etd->dma_handle && bytes_xfrd) {/* PIO */ | ||
1061 | memcpy_fromio(etd->cpu_buffer, | ||
1062 | imx21->regs + USBOTG_DMEM + etd->dmem_offset, | ||
1063 | bytes_xfrd); | ||
1064 | } | ||
909 | } | 1065 | } |
910 | free_dmem(imx21, xbufaddr); | 1066 | |
1067 | kfree(etd->bounce_buffer); | ||
1068 | etd->bounce_buffer = NULL; | ||
1069 | free_dmem(imx21, etd); | ||
911 | 1070 | ||
912 | urb->error_count = 0; | 1071 | urb->error_count = 0; |
913 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK) | 1072 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK) |
@@ -964,24 +1123,15 @@ static void nonisoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num) | |||
964 | break; | 1123 | break; |
965 | } | 1124 | } |
966 | 1125 | ||
967 | if (!etd_done) { | 1126 | if (etd_done) |
1127 | nonisoc_urb_completed_for_etd(imx21, etd, cc_to_error[cc]); | ||
1128 | else { | ||
968 | dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state); | 1129 | dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state); |
969 | schedule_nonisoc_etd(imx21, urb); | 1130 | schedule_nonisoc_etd(imx21, urb); |
970 | } else { | ||
971 | struct usb_host_endpoint *ep = urb->ep; | ||
972 | |||
973 | urb_done(hcd, urb, cc_to_error[cc]); | ||
974 | etd->urb = NULL; | ||
975 | |||
976 | if (!list_empty(&ep->urb_list)) { | ||
977 | urb = list_first_entry(&ep->urb_list, | ||
978 | struct urb, urb_list); | ||
979 | dev_vdbg(imx21->dev, "next URB %p\n", urb); | ||
980 | schedule_nonisoc_etd(imx21, urb); | ||
981 | } | ||
982 | } | 1131 | } |
983 | } | 1132 | } |
984 | 1133 | ||
1134 | |||
985 | static struct ep_priv *alloc_ep(void) | 1135 | static struct ep_priv *alloc_ep(void) |
986 | { | 1136 | { |
987 | int i; | 1137 | int i; |
@@ -1007,7 +1157,6 @@ static int imx21_hc_urb_enqueue(struct usb_hcd *hcd, | |||
1007 | struct etd_priv *etd; | 1157 | struct etd_priv *etd; |
1008 | int ret; | 1158 | int ret; |
1009 | unsigned long flags; | 1159 | unsigned long flags; |
1010 | int new_ep = 0; | ||
1011 | 1160 | ||
1012 | dev_vdbg(imx21->dev, | 1161 | dev_vdbg(imx21->dev, |
1013 | "enqueue urb=%p ep=%p len=%d " | 1162 | "enqueue urb=%p ep=%p len=%d " |
@@ -1035,7 +1184,6 @@ static int imx21_hc_urb_enqueue(struct usb_hcd *hcd, | |||
1035 | } | 1184 | } |
1036 | ep->hcpriv = ep_priv; | 1185 | ep->hcpriv = ep_priv; |
1037 | ep_priv->ep = ep; | 1186 | ep_priv->ep = ep; |
1038 | new_ep = 1; | ||
1039 | } | 1187 | } |
1040 | 1188 | ||
1041 | ret = usb_hcd_link_urb_to_ep(hcd, urb); | 1189 | ret = usb_hcd_link_urb_to_ep(hcd, urb); |
@@ -1124,9 +1272,13 @@ static int imx21_hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, | |||
1124 | } else if (urb_priv->active) { | 1272 | } else if (urb_priv->active) { |
1125 | int etd_num = ep_priv->etd[0]; | 1273 | int etd_num = ep_priv->etd[0]; |
1126 | if (etd_num != -1) { | 1274 | if (etd_num != -1) { |
1275 | struct etd_priv *etd = &imx21->etd[etd_num]; | ||
1276 | |||
1127 | disactivate_etd(imx21, etd_num); | 1277 | disactivate_etd(imx21, etd_num); |
1128 | free_dmem(imx21, etd_readl(imx21, etd_num, 1) & 0xffff); | 1278 | free_dmem(imx21, etd); |
1129 | imx21->etd[etd_num].urb = NULL; | 1279 | etd->urb = NULL; |
1280 | kfree(etd->bounce_buffer); | ||
1281 | etd->bounce_buffer = NULL; | ||
1130 | } | 1282 | } |
1131 | } | 1283 | } |
1132 | 1284 | ||
@@ -1171,7 +1323,7 @@ static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof) | |||
1171 | * (and hence no interrupt occurs). | 1323 | * (and hence no interrupt occurs). |
1172 | * This causes the transfer in question to hang. | 1324 | * This causes the transfer in question to hang. |
1173 | * The kludge below checks for this condition at each SOF and processes any | 1325 | * The kludge below checks for this condition at each SOF and processes any |
1174 | * blocked ETDs (after an arbitary 10 frame wait) | 1326 | * blocked ETDs (after an arbitrary 10 frame wait) |
1175 | * | 1327 | * |
1176 | * With a single active transfer the usbtest test suite will run for days | 1328 | * With a single active transfer the usbtest test suite will run for days |
1177 | * without the kludge. | 1329 | * without the kludge. |
@@ -1226,9 +1378,9 @@ static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof) | |||
1226 | } | 1378 | } |
1227 | 1379 | ||
1228 | if (usb_pipeisoc(etd->urb->pipe)) | 1380 | if (usb_pipeisoc(etd->urb->pipe)) |
1229 | isoc_etd_done(hcd, etd->urb, etd_num); | 1381 | isoc_etd_done(hcd, etd_num); |
1230 | else | 1382 | else |
1231 | nonisoc_etd_done(hcd, etd->urb, etd_num); | 1383 | nonisoc_etd_done(hcd, etd_num); |
1232 | } | 1384 | } |
1233 | 1385 | ||
1234 | /* only enable SOF interrupt if it may be needed for the kludge */ | 1386 | /* only enable SOF interrupt if it may be needed for the kludge */ |
@@ -1320,8 +1472,8 @@ static int get_hub_descriptor(struct usb_hcd *hcd, | |||
1320 | 0x0010 | /* No over current protection */ | 1472 | 0x0010 | /* No over current protection */ |
1321 | 0); | 1473 | 0); |
1322 | 1474 | ||
1323 | desc->bitmap[0] = 1 << 1; | 1475 | desc->u.hs.DeviceRemovable[0] = 1 << 1; |
1324 | desc->bitmap[1] = ~0; | 1476 | desc->u.hs.DeviceRemovable[1] = ~0; |
1325 | return 0; | 1477 | return 0; |
1326 | } | 1478 | } |
1327 | 1479 | ||
@@ -1507,7 +1659,7 @@ static int imx21_hc_reset(struct usb_hcd *hcd) | |||
1507 | 1659 | ||
1508 | spin_lock_irqsave(&imx21->lock, flags); | 1660 | spin_lock_irqsave(&imx21->lock, flags); |
1509 | 1661 | ||
1510 | /* Reset the Host controler modules */ | 1662 | /* Reset the Host controller modules */ |
1511 | writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH | | 1663 | writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH | |
1512 | USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC, | 1664 | USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC, |
1513 | imx21->regs + USBOTG_RST_CTRL); | 1665 | imx21->regs + USBOTG_RST_CTRL); |
@@ -1696,6 +1848,7 @@ static int imx21_probe(struct platform_device *pdev) | |||
1696 | } | 1848 | } |
1697 | 1849 | ||
1698 | imx21 = hcd_to_imx21(hcd); | 1850 | imx21 = hcd_to_imx21(hcd); |
1851 | imx21->hcd = hcd; | ||
1699 | imx21->dev = &pdev->dev; | 1852 | imx21->dev = &pdev->dev; |
1700 | imx21->pdata = pdev->dev.platform_data; | 1853 | imx21->pdata = pdev->dev.platform_data; |
1701 | if (!imx21->pdata) | 1854 | if (!imx21->pdata) |
@@ -1754,7 +1907,7 @@ failed_clock_set: | |||
1754 | failed_clock_get: | 1907 | failed_clock_get: |
1755 | iounmap(imx21->regs); | 1908 | iounmap(imx21->regs); |
1756 | failed_ioremap: | 1909 | failed_ioremap: |
1757 | release_mem_region(res->start, res->end - res->start); | 1910 | release_mem_region(res->start, resource_size(res)); |
1758 | failed_request_mem: | 1911 | failed_request_mem: |
1759 | remove_debug_files(imx21); | 1912 | remove_debug_files(imx21); |
1760 | usb_put_hcd(hcd); | 1913 | usb_put_hcd(hcd); |
diff --git a/drivers/usb/host/imx21-hcd.h b/drivers/usb/host/imx21-hcd.h index 1b0d913780a5..87b29fd971b4 100644 --- a/drivers/usb/host/imx21-hcd.h +++ b/drivers/usb/host/imx21-hcd.h | |||
@@ -250,6 +250,7 @@ | |||
250 | #define USBCTRL_USB_BYP (1 << 2) | 250 | #define USBCTRL_USB_BYP (1 << 2) |
251 | #define USBCTRL_HOST1_TXEN_OE (1 << 1) | 251 | #define USBCTRL_HOST1_TXEN_OE (1 << 1) |
252 | 252 | ||
253 | #define USBOTG_DMEM 0x1000 | ||
253 | 254 | ||
254 | /* Values in TD blocks */ | 255 | /* Values in TD blocks */ |
255 | #define TD_DIR_SETUP 0 | 256 | #define TD_DIR_SETUP 0 |
@@ -346,8 +347,8 @@ struct td { | |||
346 | struct list_head list; | 347 | struct list_head list; |
347 | struct urb *urb; | 348 | struct urb *urb; |
348 | struct usb_host_endpoint *ep; | 349 | struct usb_host_endpoint *ep; |
349 | dma_addr_t data; | 350 | dma_addr_t dma_handle; |
350 | unsigned long buf_addr; | 351 | void *cpu_buffer; |
351 | int len; | 352 | int len; |
352 | int frame; | 353 | int frame; |
353 | int isoc_index; | 354 | int isoc_index; |
@@ -360,6 +361,8 @@ struct etd_priv { | |||
360 | struct td *td; | 361 | struct td *td; |
361 | struct list_head queue; | 362 | struct list_head queue; |
362 | dma_addr_t dma_handle; | 363 | dma_addr_t dma_handle; |
364 | void *cpu_buffer; | ||
365 | void *bounce_buffer; | ||
363 | int alloc; | 366 | int alloc; |
364 | int len; | 367 | int len; |
365 | int dmem_size; | 368 | int dmem_size; |
@@ -412,6 +415,7 @@ struct debug_isoc_trace { | |||
412 | struct imx21 { | 415 | struct imx21 { |
413 | spinlock_t lock; | 416 | spinlock_t lock; |
414 | struct device *dev; | 417 | struct device *dev; |
418 | struct usb_hcd *hcd; | ||
415 | struct mx21_usbh_platform_data *pdata; | 419 | struct mx21_usbh_platform_data *pdata; |
416 | struct list_head dmem_list; | 420 | struct list_head dmem_list; |
417 | struct list_head queue_for_etd; /* eps queued due to etd shortage */ | 421 | struct list_head queue_for_etd; /* eps queued due to etd shortage */ |
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index d9e82123de2a..baae4ccd16ac 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c | |||
@@ -612,6 +612,7 @@ static irqreturn_t isp116x_irq(struct usb_hcd *hcd) | |||
612 | /* IRQ's are off, we do no DMA, | 612 | /* IRQ's are off, we do no DMA, |
613 | perfectly ready to die ... */ | 613 | perfectly ready to die ... */ |
614 | hcd->state = HC_STATE_HALT; | 614 | hcd->state = HC_STATE_HALT; |
615 | usb_hc_died(hcd); | ||
615 | ret = IRQ_HANDLED; | 616 | ret = IRQ_HANDLED; |
616 | goto done; | 617 | goto done; |
617 | } | 618 | } |
@@ -951,9 +952,9 @@ static void isp116x_hub_descriptor(struct isp116x *isp116x, | |||
951 | /* Power switching, device type, overcurrent. */ | 952 | /* Power switching, device type, overcurrent. */ |
952 | desc->wHubCharacteristics = cpu_to_le16((u16) ((reg >> 8) & 0x1f)); | 953 | desc->wHubCharacteristics = cpu_to_le16((u16) ((reg >> 8) & 0x1f)); |
953 | desc->bPwrOn2PwrGood = (u8) ((reg >> 24) & 0xff); | 954 | desc->bPwrOn2PwrGood = (u8) ((reg >> 24) & 0xff); |
954 | /* two bitmaps: ports removable, and legacy PortPwrCtrlMask */ | 955 | /* ports removable, and legacy PortPwrCtrlMask */ |
955 | desc->bitmap[0] = 0; | 956 | desc->u.hs.DeviceRemovable[0] = 0; |
956 | desc->bitmap[1] = ~0; | 957 | desc->u.hs.DeviceRemovable[1] = ~0; |
957 | } | 958 | } |
958 | 959 | ||
959 | /* Perform reset of a given port. | 960 | /* Perform reset of a given port. |
@@ -1557,8 +1558,6 @@ static int isp116x_remove(struct platform_device *pdev) | |||
1557 | return 0; | 1558 | return 0; |
1558 | } | 1559 | } |
1559 | 1560 | ||
1560 | #define resource_len(r) (((r)->end - (r)->start) + 1) | ||
1561 | |||
1562 | static int __devinit isp116x_probe(struct platform_device *pdev) | 1561 | static int __devinit isp116x_probe(struct platform_device *pdev) |
1563 | { | 1562 | { |
1564 | struct usb_hcd *hcd; | 1563 | struct usb_hcd *hcd; |
@@ -1597,7 +1596,7 @@ static int __devinit isp116x_probe(struct platform_device *pdev) | |||
1597 | ret = -EBUSY; | 1596 | ret = -EBUSY; |
1598 | goto err1; | 1597 | goto err1; |
1599 | } | 1598 | } |
1600 | addr_reg = ioremap(addr->start, resource_len(addr)); | 1599 | addr_reg = ioremap(addr->start, resource_size(addr)); |
1601 | if (addr_reg == NULL) { | 1600 | if (addr_reg == NULL) { |
1602 | ret = -ENOMEM; | 1601 | ret = -ENOMEM; |
1603 | goto err2; | 1602 | goto err2; |
@@ -1606,7 +1605,7 @@ static int __devinit isp116x_probe(struct platform_device *pdev) | |||
1606 | ret = -EBUSY; | 1605 | ret = -EBUSY; |
1607 | goto err3; | 1606 | goto err3; |
1608 | } | 1607 | } |
1609 | data_reg = ioremap(data->start, resource_len(data)); | 1608 | data_reg = ioremap(data->start, resource_size(data)); |
1610 | if (data_reg == NULL) { | 1609 | if (data_reg == NULL) { |
1611 | ret = -ENOMEM; | 1610 | ret = -ENOMEM; |
1612 | goto err4; | 1611 | goto err4; |
diff --git a/drivers/usb/host/isp116x.h b/drivers/usb/host/isp116x.h index 12db961acdfb..9a2c400e6090 100644 --- a/drivers/usb/host/isp116x.h +++ b/drivers/usb/host/isp116x.h | |||
@@ -13,7 +13,7 @@ | |||
13 | 13 | ||
14 | /* Full speed: max # of bytes to transfer for a single urb | 14 | /* Full speed: max # of bytes to transfer for a single urb |
15 | at a time must be < 1024 && must be multiple of 64. | 15 | at a time must be < 1024 && must be multiple of 64. |
16 | 832 allows transfering 4kiB within 5 frames. */ | 16 | 832 allows transferring 4kiB within 5 frames. */ |
17 | #define MAX_TRANSFER_SIZE_FULLSPEED 832 | 17 | #define MAX_TRANSFER_SIZE_FULLSPEED 832 |
18 | 18 | ||
19 | /* Low speed: there is no reason to schedule in very big | 19 | /* Low speed: there is no reason to schedule in very big |
diff --git a/drivers/usb/host/isp1362-hcd.c b/drivers/usb/host/isp1362-hcd.c index 0587ad4ce5c2..9c37dad3e816 100644 --- a/drivers/usb/host/isp1362-hcd.c +++ b/drivers/usb/host/isp1362-hcd.c | |||
@@ -70,7 +70,6 @@ | |||
70 | #include <linux/ioport.h> | 70 | #include <linux/ioport.h> |
71 | #include <linux/sched.h> | 71 | #include <linux/sched.h> |
72 | #include <linux/slab.h> | 72 | #include <linux/slab.h> |
73 | #include <linux/smp_lock.h> | ||
74 | #include <linux/errno.h> | 73 | #include <linux/errno.h> |
75 | #include <linux/init.h> | 74 | #include <linux/init.h> |
76 | #include <linux/list.h> | 75 | #include <linux/list.h> |
@@ -82,6 +81,7 @@ | |||
82 | #include <linux/pm.h> | 81 | #include <linux/pm.h> |
83 | #include <linux/io.h> | 82 | #include <linux/io.h> |
84 | #include <linux/bitmap.h> | 83 | #include <linux/bitmap.h> |
84 | #include <linux/prefetch.h> | ||
85 | 85 | ||
86 | #include <asm/irq.h> | 86 | #include <asm/irq.h> |
87 | #include <asm/system.h> | 87 | #include <asm/system.h> |
@@ -227,7 +227,6 @@ static int claim_ptd_buffers(struct isp1362_ep_queue *epq, | |||
227 | 227 | ||
228 | static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1362_ep *ep) | 228 | static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1362_ep *ep) |
229 | { | 229 | { |
230 | int index = ep->ptd_index; | ||
231 | int last = ep->ptd_index + ep->num_ptds; | 230 | int last = ep->ptd_index + ep->num_ptds; |
232 | 231 | ||
233 | if (last > epq->buf_count) | 232 | if (last > epq->buf_count) |
@@ -237,10 +236,8 @@ static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1 | |||
237 | epq->buf_map, epq->skip_map); | 236 | epq->buf_map, epq->skip_map); |
238 | BUG_ON(last > epq->buf_count); | 237 | BUG_ON(last > epq->buf_count); |
239 | 238 | ||
240 | for (; index < last; index++) { | 239 | bitmap_clear(&epq->buf_map, ep->ptd_index, ep->num_ptds); |
241 | __clear_bit(index, &epq->buf_map); | 240 | bitmap_set(&epq->skip_map, ep->ptd_index, ep->num_ptds); |
242 | __set_bit(index, &epq->skip_map); | ||
243 | } | ||
244 | epq->buf_avail += ep->num_ptds; | 241 | epq->buf_avail += ep->num_ptds; |
245 | epq->ptd_count--; | 242 | epq->ptd_count--; |
246 | 243 | ||
@@ -550,7 +547,7 @@ static void postproc_ep(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep *ep) | |||
550 | if (usb_pipecontrol(urb->pipe)) { | 547 | if (usb_pipecontrol(urb->pipe)) { |
551 | ep->nextpid = USB_PID_ACK; | 548 | ep->nextpid = USB_PID_ACK; |
552 | /* save the data underrun error code for later and | 549 | /* save the data underrun error code for later and |
553 | * procede with the status stage | 550 | * proceed with the status stage |
554 | */ | 551 | */ |
555 | urb->actual_length += PTD_GET_COUNT(ptd); | 552 | urb->actual_length += PTD_GET_COUNT(ptd); |
556 | BUG_ON(urb->actual_length > urb->transfer_buffer_length); | 553 | BUG_ON(urb->actual_length > urb->transfer_buffer_length); |
@@ -1556,9 +1553,9 @@ static void isp1362_hub_descriptor(struct isp1362_hcd *isp1362_hcd, | |||
1556 | desc->wHubCharacteristics = cpu_to_le16((reg >> 8) & 0x1f); | 1553 | desc->wHubCharacteristics = cpu_to_le16((reg >> 8) & 0x1f); |
1557 | DBG(0, "%s: hubcharacteristics = %02x\n", __func__, cpu_to_le16((reg >> 8) & 0x1f)); | 1554 | DBG(0, "%s: hubcharacteristics = %02x\n", __func__, cpu_to_le16((reg >> 8) & 0x1f)); |
1558 | desc->bPwrOn2PwrGood = (reg >> 24) & 0xff; | 1555 | desc->bPwrOn2PwrGood = (reg >> 24) & 0xff; |
1559 | /* two bitmaps: ports removable, and legacy PortPwrCtrlMask */ | 1556 | /* ports removable, and legacy PortPwrCtrlMask */ |
1560 | desc->bitmap[0] = desc->bNbrPorts == 1 ? 1 << 1 : 3 << 1; | 1557 | desc->u.hs.DeviceRemovable[0] = desc->bNbrPorts == 1 ? 1 << 1 : 3 << 1; |
1561 | desc->bitmap[1] = ~0; | 1558 | desc->u.hs.DeviceRemovable[1] = ~0; |
1562 | 1559 | ||
1563 | DBG(3, "%s: exit\n", __func__); | 1560 | DBG(3, "%s: exit\n", __func__); |
1564 | } | 1561 | } |
@@ -1676,13 +1673,6 @@ static int isp1362_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
1676 | switch (wValue) { | 1673 | switch (wValue) { |
1677 | case USB_PORT_FEAT_SUSPEND: | 1674 | case USB_PORT_FEAT_SUSPEND: |
1678 | _DBG(0, "USB_PORT_FEAT_SUSPEND\n"); | 1675 | _DBG(0, "USB_PORT_FEAT_SUSPEND\n"); |
1679 | #ifdef CONFIG_USB_OTG | ||
1680 | if (ohci->hcd.self.otg_port == (wIndex + 1) && | ||
1681 | ohci->hcd.self.b_hnp_enable) { | ||
1682 | start_hnp(ohci); | ||
1683 | break; | ||
1684 | } | ||
1685 | #endif | ||
1686 | spin_lock_irqsave(&isp1362_hcd->lock, flags); | 1676 | spin_lock_irqsave(&isp1362_hcd->lock, flags); |
1687 | isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + wIndex, RH_PS_PSS); | 1677 | isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + wIndex, RH_PS_PSS); |
1688 | isp1362_hcd->rhport[wIndex] = | 1678 | isp1362_hcd->rhport[wIndex] = |
@@ -2656,8 +2646,6 @@ static struct hc_driver isp1362_hc_driver = { | |||
2656 | 2646 | ||
2657 | /*-------------------------------------------------------------------------*/ | 2647 | /*-------------------------------------------------------------------------*/ |
2658 | 2648 | ||
2659 | #define resource_len(r) (((r)->end - (r)->start) + 1) | ||
2660 | |||
2661 | static int __devexit isp1362_remove(struct platform_device *pdev) | 2649 | static int __devexit isp1362_remove(struct platform_device *pdev) |
2662 | { | 2650 | { |
2663 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | 2651 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
@@ -2679,12 +2667,12 @@ static int __devexit isp1362_remove(struct platform_device *pdev) | |||
2679 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | 2667 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
2680 | DBG(0, "%s: release mem_region: %08lx\n", __func__, (long unsigned int)res->start); | 2668 | DBG(0, "%s: release mem_region: %08lx\n", __func__, (long unsigned int)res->start); |
2681 | if (res) | 2669 | if (res) |
2682 | release_mem_region(res->start, resource_len(res)); | 2670 | release_mem_region(res->start, resource_size(res)); |
2683 | 2671 | ||
2684 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 2672 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2685 | DBG(0, "%s: release mem_region: %08lx\n", __func__, (long unsigned int)res->start); | 2673 | DBG(0, "%s: release mem_region: %08lx\n", __func__, (long unsigned int)res->start); |
2686 | if (res) | 2674 | if (res) |
2687 | release_mem_region(res->start, resource_len(res)); | 2675 | release_mem_region(res->start, resource_size(res)); |
2688 | 2676 | ||
2689 | DBG(0, "%s: put_hcd\n", __func__); | 2677 | DBG(0, "%s: put_hcd\n", __func__); |
2690 | usb_put_hcd(hcd); | 2678 | usb_put_hcd(hcd); |
@@ -2693,7 +2681,7 @@ static int __devexit isp1362_remove(struct platform_device *pdev) | |||
2693 | return 0; | 2681 | return 0; |
2694 | } | 2682 | } |
2695 | 2683 | ||
2696 | static int __init isp1362_probe(struct platform_device *pdev) | 2684 | static int __devinit isp1362_probe(struct platform_device *pdev) |
2697 | { | 2685 | { |
2698 | struct usb_hcd *hcd; | 2686 | struct usb_hcd *hcd; |
2699 | struct isp1362_hcd *isp1362_hcd; | 2687 | struct isp1362_hcd *isp1362_hcd; |
@@ -2730,21 +2718,21 @@ static int __init isp1362_probe(struct platform_device *pdev) | |||
2730 | goto err1; | 2718 | goto err1; |
2731 | } | 2719 | } |
2732 | 2720 | ||
2733 | if (!request_mem_region(addr->start, resource_len(addr), hcd_name)) { | 2721 | if (!request_mem_region(addr->start, resource_size(addr), hcd_name)) { |
2734 | retval = -EBUSY; | 2722 | retval = -EBUSY; |
2735 | goto err1; | 2723 | goto err1; |
2736 | } | 2724 | } |
2737 | addr_reg = ioremap(addr->start, resource_len(addr)); | 2725 | addr_reg = ioremap(addr->start, resource_size(addr)); |
2738 | if (addr_reg == NULL) { | 2726 | if (addr_reg == NULL) { |
2739 | retval = -ENOMEM; | 2727 | retval = -ENOMEM; |
2740 | goto err2; | 2728 | goto err2; |
2741 | } | 2729 | } |
2742 | 2730 | ||
2743 | if (!request_mem_region(data->start, resource_len(data), hcd_name)) { | 2731 | if (!request_mem_region(data->start, resource_size(data), hcd_name)) { |
2744 | retval = -EBUSY; | 2732 | retval = -EBUSY; |
2745 | goto err3; | 2733 | goto err3; |
2746 | } | 2734 | } |
2747 | data_reg = ioremap(data->start, resource_len(data)); | 2735 | data_reg = ioremap(data->start, resource_size(data)); |
2748 | if (data_reg == NULL) { | 2736 | if (data_reg == NULL) { |
2749 | retval = -ENOMEM; | 2737 | retval = -ENOMEM; |
2750 | goto err4; | 2738 | goto err4; |
@@ -2802,13 +2790,13 @@ static int __init isp1362_probe(struct platform_device *pdev) | |||
2802 | iounmap(data_reg); | 2790 | iounmap(data_reg); |
2803 | err4: | 2791 | err4: |
2804 | DBG(0, "%s: Releasing mem region %08lx\n", __func__, (long unsigned int)data->start); | 2792 | DBG(0, "%s: Releasing mem region %08lx\n", __func__, (long unsigned int)data->start); |
2805 | release_mem_region(data->start, resource_len(data)); | 2793 | release_mem_region(data->start, resource_size(data)); |
2806 | err3: | 2794 | err3: |
2807 | DBG(0, "%s: Unmapping addr_reg @ %p\n", __func__, addr_reg); | 2795 | DBG(0, "%s: Unmapping addr_reg @ %p\n", __func__, addr_reg); |
2808 | iounmap(addr_reg); | 2796 | iounmap(addr_reg); |
2809 | err2: | 2797 | err2: |
2810 | DBG(0, "%s: Releasing mem region %08lx\n", __func__, (long unsigned int)addr->start); | 2798 | DBG(0, "%s: Releasing mem region %08lx\n", __func__, (long unsigned int)addr->start); |
2811 | release_mem_region(addr->start, resource_len(addr)); | 2799 | release_mem_region(addr->start, resource_size(addr)); |
2812 | err1: | 2800 | err1: |
2813 | pr_err("%s: init error, %d\n", __func__, retval); | 2801 | pr_err("%s: init error, %d\n", __func__, retval); |
2814 | 2802 | ||
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c index bdba8c5d844a..55d3d5859ac5 100644 --- a/drivers/usb/host/isp1760-hcd.c +++ b/drivers/usb/host/isp1760-hcd.c | |||
@@ -8,6 +8,8 @@ | |||
8 | * | 8 | * |
9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | 9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> |
10 | * | 10 | * |
11 | * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> | ||
12 | * | ||
11 | */ | 13 | */ |
12 | #include <linux/module.h> | 14 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
@@ -26,13 +28,18 @@ | |||
26 | 28 | ||
27 | static struct kmem_cache *qtd_cachep; | 29 | static struct kmem_cache *qtd_cachep; |
28 | static struct kmem_cache *qh_cachep; | 30 | static struct kmem_cache *qh_cachep; |
31 | static struct kmem_cache *urb_listitem_cachep; | ||
29 | 32 | ||
30 | struct isp1760_hcd { | 33 | struct isp1760_hcd { |
31 | u32 hcs_params; | 34 | u32 hcs_params; |
32 | spinlock_t lock; | 35 | spinlock_t lock; |
33 | struct inter_packet_info atl_ints[32]; | 36 | struct slotinfo atl_slots[32]; |
34 | struct inter_packet_info int_ints[32]; | 37 | int atl_done_map; |
38 | struct slotinfo int_slots[32]; | ||
39 | int int_done_map; | ||
35 | struct memory_chunk memory_pool[BLOCKS]; | 40 | struct memory_chunk memory_pool[BLOCKS]; |
41 | struct list_head controlqhs, bulkqhs, interruptqhs; | ||
42 | int active_ptds; | ||
36 | 43 | ||
37 | /* periodic schedule support */ | 44 | /* periodic schedule support */ |
38 | #define DEFAULT_I_TDPS 1024 | 45 | #define DEFAULT_I_TDPS 1024 |
@@ -47,10 +54,6 @@ static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | |||
47 | { | 54 | { |
48 | return (struct isp1760_hcd *) (hcd->hcd_priv); | 55 | return (struct isp1760_hcd *) (hcd->hcd_priv); |
49 | } | 56 | } |
50 | static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv) | ||
51 | { | ||
52 | return container_of((void *) priv, struct usb_hcd, hcd_priv); | ||
53 | } | ||
54 | 57 | ||
55 | /* Section 2.2 Host Controller Capability Registers */ | 58 | /* Section 2.2 Host Controller Capability Registers */ |
56 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ | 59 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
@@ -80,217 +83,270 @@ static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv) | |||
80 | #define PORT_RWC_BITS (PORT_CSC) | 83 | #define PORT_RWC_BITS (PORT_CSC) |
81 | 84 | ||
82 | struct isp1760_qtd { | 85 | struct isp1760_qtd { |
83 | struct isp1760_qtd *hw_next; | ||
84 | u8 packet_type; | 86 | u8 packet_type; |
85 | u8 toggle; | ||
86 | |||
87 | void *data_buffer; | 87 | void *data_buffer; |
88 | u32 payload_addr; | ||
89 | |||
88 | /* the rest is HCD-private */ | 90 | /* the rest is HCD-private */ |
89 | struct list_head qtd_list; | 91 | struct list_head qtd_list; |
90 | struct urb *urb; | 92 | struct urb *urb; |
91 | size_t length; | 93 | size_t length; |
92 | 94 | size_t actual_length; | |
93 | /* isp special*/ | 95 | |
96 | /* QTD_ENQUEUED: waiting for transfer (inactive) */ | ||
97 | /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ | ||
98 | /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only | ||
99 | interrupt handler may touch this qtd! */ | ||
100 | /* QTD_XFER_COMPLETE: payload has been transferred successfully */ | ||
101 | /* QTD_RETIRE: transfer error/abort qtd */ | ||
102 | #define QTD_ENQUEUED 0 | ||
103 | #define QTD_PAYLOAD_ALLOC 1 | ||
104 | #define QTD_XFER_STARTED 2 | ||
105 | #define QTD_XFER_COMPLETE 3 | ||
106 | #define QTD_RETIRE 4 | ||
94 | u32 status; | 107 | u32 status; |
95 | #define URB_COMPLETE_NOTIFY (1 << 0) | ||
96 | #define URB_ENQUEUED (1 << 1) | ||
97 | #define URB_TYPE_ATL (1 << 2) | ||
98 | #define URB_TYPE_INT (1 << 3) | ||
99 | }; | 108 | }; |
100 | 109 | ||
110 | /* Queue head, one for each active endpoint */ | ||
101 | struct isp1760_qh { | 111 | struct isp1760_qh { |
102 | /* first part defined by EHCI spec */ | 112 | struct list_head qh_list; |
103 | struct list_head qtd_list; | 113 | struct list_head qtd_list; |
104 | struct isp1760_hcd *priv; | ||
105 | |||
106 | /* periodic schedule info */ | ||
107 | unsigned short period; /* polling interval */ | ||
108 | struct usb_device *dev; | ||
109 | |||
110 | u32 toggle; | 114 | u32 toggle; |
111 | u32 ping; | 115 | u32 ping; |
116 | int slot; | ||
112 | }; | 117 | }; |
113 | 118 | ||
114 | #define ehci_port_speed(priv, portsc) USB_PORT_STAT_HIGH_SPEED | 119 | struct urb_listitem { |
120 | struct list_head urb_list; | ||
121 | struct urb *urb; | ||
122 | }; | ||
115 | 123 | ||
116 | static unsigned int isp1760_readl(__u32 __iomem *regs) | 124 | /* |
125 | * Access functions for isp176x registers (addresses 0..0x03FF). | ||
126 | */ | ||
127 | static u32 reg_read32(void __iomem *base, u32 reg) | ||
117 | { | 128 | { |
118 | return readl(regs); | 129 | return readl(base + reg); |
119 | } | 130 | } |
120 | 131 | ||
121 | static void isp1760_writel(const unsigned int val, __u32 __iomem *regs) | 132 | static void reg_write32(void __iomem *base, u32 reg, u32 val) |
122 | { | 133 | { |
123 | writel(val, regs); | 134 | writel(val, base + reg); |
124 | } | 135 | } |
125 | 136 | ||
126 | /* | 137 | /* |
127 | * The next two copy via MMIO data to/from the device. memcpy_{to|from}io() | 138 | * Access functions for isp176x memory (offset >= 0x0400). |
139 | * | ||
140 | * bank_reads8() reads memory locations prefetched by an earlier write to | ||
141 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- | ||
142 | * bank optimizations, you should use the more generic mem_reads8() below. | ||
143 | * | ||
144 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() | ||
145 | * below. | ||
146 | * | ||
147 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() | ||
128 | * doesn't quite work because some people have to enforce 32-bit access | 148 | * doesn't quite work because some people have to enforce 32-bit access |
129 | */ | 149 | */ |
130 | static void priv_read_copy(struct isp1760_hcd *priv, u32 *src, | 150 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
131 | __u32 __iomem *dst, u32 len) | 151 | __u32 *dst, u32 bytes) |
132 | { | 152 | { |
153 | __u32 __iomem *src; | ||
133 | u32 val; | 154 | u32 val; |
134 | u8 *buff8; | 155 | __u8 *src_byteptr; |
156 | __u8 *dst_byteptr; | ||
135 | 157 | ||
136 | if (!src) { | 158 | src = src_base + (bank_addr | src_offset); |
137 | printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len); | ||
138 | return; | ||
139 | } | ||
140 | 159 | ||
141 | while (len >= 4) { | 160 | if (src_offset < PAYLOAD_OFFSET) { |
142 | *src = __raw_readl(dst); | 161 | while (bytes >= 4) { |
143 | len -= 4; | 162 | *dst = le32_to_cpu(__raw_readl(src)); |
144 | src++; | 163 | bytes -= 4; |
145 | dst++; | 164 | src++; |
165 | dst++; | ||
166 | } | ||
167 | } else { | ||
168 | while (bytes >= 4) { | ||
169 | *dst = __raw_readl(src); | ||
170 | bytes -= 4; | ||
171 | src++; | ||
172 | dst++; | ||
173 | } | ||
146 | } | 174 | } |
147 | 175 | ||
148 | if (!len) | 176 | if (!bytes) |
149 | return; | 177 | return; |
150 | 178 | ||
151 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | 179 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully |
152 | * allocated. | 180 | * allocated. |
153 | */ | 181 | */ |
154 | val = isp1760_readl(dst); | 182 | if (src_offset < PAYLOAD_OFFSET) |
155 | 183 | val = le32_to_cpu(__raw_readl(src)); | |
156 | buff8 = (u8 *)src; | 184 | else |
157 | while (len) { | 185 | val = __raw_readl(src); |
158 | 186 | ||
159 | *buff8 = val; | 187 | dst_byteptr = (void *) dst; |
160 | val >>= 8; | 188 | src_byteptr = (void *) &val; |
161 | len--; | 189 | while (bytes > 0) { |
162 | buff8++; | 190 | *dst_byteptr = *src_byteptr; |
191 | dst_byteptr++; | ||
192 | src_byteptr++; | ||
193 | bytes--; | ||
163 | } | 194 | } |
164 | } | 195 | } |
165 | 196 | ||
166 | static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src, | 197 | static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, |
167 | __u32 __iomem *dst, u32 len) | 198 | u32 bytes) |
168 | { | 199 | { |
169 | while (len >= 4) { | 200 | reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); |
170 | __raw_writel(*src, dst); | 201 | ndelay(90); |
171 | len -= 4; | 202 | bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); |
172 | src++; | 203 | } |
173 | dst++; | 204 | |
205 | static void mem_writes8(void __iomem *dst_base, u32 dst_offset, | ||
206 | __u32 const *src, u32 bytes) | ||
207 | { | ||
208 | __u32 __iomem *dst; | ||
209 | |||
210 | dst = dst_base + dst_offset; | ||
211 | |||
212 | if (dst_offset < PAYLOAD_OFFSET) { | ||
213 | while (bytes >= 4) { | ||
214 | __raw_writel(cpu_to_le32(*src), dst); | ||
215 | bytes -= 4; | ||
216 | src++; | ||
217 | dst++; | ||
218 | } | ||
219 | } else { | ||
220 | while (bytes >= 4) { | ||
221 | __raw_writel(*src, dst); | ||
222 | bytes -= 4; | ||
223 | src++; | ||
224 | dst++; | ||
225 | } | ||
174 | } | 226 | } |
175 | 227 | ||
176 | if (!len) | 228 | if (!bytes) |
177 | return; | 229 | return; |
178 | /* in case we have 3, 2 or 1 by left. The buffer is allocated and the | 230 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
179 | * extra bytes should not be read by the HW | 231 | * extra bytes should not be read by the HW. |
180 | */ | 232 | */ |
181 | 233 | ||
182 | __raw_writel(*src, dst); | 234 | if (dst_offset < PAYLOAD_OFFSET) |
235 | __raw_writel(cpu_to_le32(*src), dst); | ||
236 | else | ||
237 | __raw_writel(*src, dst); | ||
183 | } | 238 | } |
184 | 239 | ||
240 | /* | ||
241 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, | ||
242 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. | ||
243 | */ | ||
244 | static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, | ||
245 | struct ptd *ptd) | ||
246 | { | ||
247 | reg_write32(base, HC_MEMORY_REG, | ||
248 | ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); | ||
249 | ndelay(90); | ||
250 | bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), | ||
251 | (void *) ptd, sizeof(*ptd)); | ||
252 | } | ||
253 | |||
254 | static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, | ||
255 | struct ptd *ptd) | ||
256 | { | ||
257 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), | ||
258 | &ptd->dw1, 7*sizeof(ptd->dw1)); | ||
259 | /* Make sure dw0 gets written last (after other dw's and after payload) | ||
260 | since it contains the enable bit */ | ||
261 | wmb(); | ||
262 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, | ||
263 | sizeof(ptd->dw0)); | ||
264 | } | ||
265 | |||
266 | |||
185 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ | 267 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
186 | static void init_memory(struct isp1760_hcd *priv) | 268 | static void init_memory(struct isp1760_hcd *priv) |
187 | { | 269 | { |
188 | int i; | 270 | int i, curr; |
189 | u32 payload; | 271 | u32 payload_addr; |
190 | 272 | ||
191 | payload = 0x1000; | 273 | payload_addr = PAYLOAD_OFFSET; |
192 | for (i = 0; i < BLOCK_1_NUM; i++) { | 274 | for (i = 0; i < BLOCK_1_NUM; i++) { |
193 | priv->memory_pool[i].start = payload; | 275 | priv->memory_pool[i].start = payload_addr; |
194 | priv->memory_pool[i].size = BLOCK_1_SIZE; | 276 | priv->memory_pool[i].size = BLOCK_1_SIZE; |
195 | priv->memory_pool[i].free = 1; | 277 | priv->memory_pool[i].free = 1; |
196 | payload += priv->memory_pool[i].size; | 278 | payload_addr += priv->memory_pool[i].size; |
197 | } | 279 | } |
198 | 280 | ||
199 | 281 | curr = i; | |
200 | for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) { | 282 | for (i = 0; i < BLOCK_2_NUM; i++) { |
201 | priv->memory_pool[i].start = payload; | 283 | priv->memory_pool[curr + i].start = payload_addr; |
202 | priv->memory_pool[i].size = BLOCK_2_SIZE; | 284 | priv->memory_pool[curr + i].size = BLOCK_2_SIZE; |
203 | priv->memory_pool[i].free = 1; | 285 | priv->memory_pool[curr + i].free = 1; |
204 | payload += priv->memory_pool[i].size; | 286 | payload_addr += priv->memory_pool[curr + i].size; |
205 | } | 287 | } |
206 | 288 | ||
207 | 289 | curr = i; | |
208 | for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) { | 290 | for (i = 0; i < BLOCK_3_NUM; i++) { |
209 | priv->memory_pool[i].start = payload; | 291 | priv->memory_pool[curr + i].start = payload_addr; |
210 | priv->memory_pool[i].size = BLOCK_3_SIZE; | 292 | priv->memory_pool[curr + i].size = BLOCK_3_SIZE; |
211 | priv->memory_pool[i].free = 1; | 293 | priv->memory_pool[curr + i].free = 1; |
212 | payload += priv->memory_pool[i].size; | 294 | payload_addr += priv->memory_pool[curr + i].size; |
213 | } | 295 | } |
214 | 296 | ||
215 | BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE); | 297 | WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); |
216 | } | 298 | } |
217 | 299 | ||
218 | static u32 alloc_mem(struct isp1760_hcd *priv, u32 size) | 300 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
219 | { | 301 | { |
302 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
220 | int i; | 303 | int i; |
221 | 304 | ||
222 | if (!size) | 305 | WARN_ON(qtd->payload_addr); |
223 | return ISP1760_NULL_POINTER; | 306 | |
307 | if (!qtd->length) | ||
308 | return; | ||
224 | 309 | ||
225 | for (i = 0; i < BLOCKS; i++) { | 310 | for (i = 0; i < BLOCKS; i++) { |
226 | if (priv->memory_pool[i].size >= size && | 311 | if (priv->memory_pool[i].size >= qtd->length && |
227 | priv->memory_pool[i].free) { | 312 | priv->memory_pool[i].free) { |
228 | |||
229 | priv->memory_pool[i].free = 0; | 313 | priv->memory_pool[i].free = 0; |
230 | return priv->memory_pool[i].start; | 314 | qtd->payload_addr = priv->memory_pool[i].start; |
315 | return; | ||
231 | } | 316 | } |
232 | } | 317 | } |
233 | |||
234 | printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n", | ||
235 | size); | ||
236 | printk(KERN_ERR "Current memory map:\n"); | ||
237 | for (i = 0; i < BLOCKS; i++) { | ||
238 | printk(KERN_ERR "Pool %2d size %4d status: %d\n", | ||
239 | i, priv->memory_pool[i].size, | ||
240 | priv->memory_pool[i].free); | ||
241 | } | ||
242 | /* XXX maybe -ENOMEM could be possible */ | ||
243 | BUG(); | ||
244 | return 0; | ||
245 | } | 318 | } |
246 | 319 | ||
247 | static void free_mem(struct isp1760_hcd *priv, u32 mem) | 320 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
248 | { | 321 | { |
322 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
249 | int i; | 323 | int i; |
250 | 324 | ||
251 | if (mem == ISP1760_NULL_POINTER) | 325 | if (!qtd->payload_addr) |
252 | return; | 326 | return; |
253 | 327 | ||
254 | for (i = 0; i < BLOCKS; i++) { | 328 | for (i = 0; i < BLOCKS; i++) { |
255 | if (priv->memory_pool[i].start == mem) { | 329 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
256 | 330 | WARN_ON(priv->memory_pool[i].free); | |
257 | BUG_ON(priv->memory_pool[i].free); | ||
258 | |||
259 | priv->memory_pool[i].free = 1; | 331 | priv->memory_pool[i].free = 1; |
260 | return ; | 332 | qtd->payload_addr = 0; |
333 | return; | ||
261 | } | 334 | } |
262 | } | 335 | } |
263 | 336 | ||
264 | printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n", | 337 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", |
265 | mem); | 338 | __func__, qtd->payload_addr); |
266 | BUG(); | 339 | WARN_ON(1); |
267 | } | 340 | qtd->payload_addr = 0; |
268 | |||
269 | static void isp1760_init_regs(struct usb_hcd *hcd) | ||
270 | { | ||
271 | isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG); | ||
272 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | ||
273 | HC_ATL_PTD_SKIPMAP_REG); | ||
274 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | ||
275 | HC_INT_PTD_SKIPMAP_REG); | ||
276 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | ||
277 | HC_ISO_PTD_SKIPMAP_REG); | ||
278 | |||
279 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | ||
280 | HC_ATL_PTD_DONEMAP_REG); | ||
281 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | ||
282 | HC_INT_PTD_DONEMAP_REG); | ||
283 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | ||
284 | HC_ISO_PTD_DONEMAP_REG); | ||
285 | } | 341 | } |
286 | 342 | ||
287 | static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, | 343 | static int handshake(struct usb_hcd *hcd, u32 reg, |
288 | u32 mask, u32 done, int usec) | 344 | u32 mask, u32 done, int usec) |
289 | { | 345 | { |
290 | u32 result; | 346 | u32 result; |
291 | 347 | ||
292 | do { | 348 | do { |
293 | result = isp1760_readl(ptr); | 349 | result = reg_read32(hcd->regs, reg); |
294 | if (result == ~0) | 350 | if (result == ~0) |
295 | return -ENODEV; | 351 | return -ENODEV; |
296 | result &= mask; | 352 | result &= mask; |
@@ -303,48 +359,43 @@ static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, | |||
303 | } | 359 | } |
304 | 360 | ||
305 | /* reset a non-running (STS_HALT == 1) controller */ | 361 | /* reset a non-running (STS_HALT == 1) controller */ |
306 | static int ehci_reset(struct isp1760_hcd *priv) | 362 | static int ehci_reset(struct usb_hcd *hcd) |
307 | { | 363 | { |
308 | int retval; | 364 | int retval; |
309 | struct usb_hcd *hcd = priv_to_hcd(priv); | 365 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
310 | u32 command = isp1760_readl(hcd->regs + HC_USBCMD); | 366 | |
367 | u32 command = reg_read32(hcd->regs, HC_USBCMD); | ||
311 | 368 | ||
312 | command |= CMD_RESET; | 369 | command |= CMD_RESET; |
313 | isp1760_writel(command, hcd->regs + HC_USBCMD); | 370 | reg_write32(hcd->regs, HC_USBCMD, command); |
314 | hcd->state = HC_STATE_HALT; | 371 | hcd->state = HC_STATE_HALT; |
315 | priv->next_statechange = jiffies; | 372 | priv->next_statechange = jiffies; |
316 | retval = handshake(priv, hcd->regs + HC_USBCMD, | 373 | retval = handshake(hcd, HC_USBCMD, |
317 | CMD_RESET, 0, 250 * 1000); | 374 | CMD_RESET, 0, 250 * 1000); |
318 | return retval; | 375 | return retval; |
319 | } | 376 | } |
320 | 377 | ||
321 | static void qh_destroy(struct isp1760_qh *qh) | 378 | static struct isp1760_qh *qh_alloc(gfp_t flags) |
322 | { | ||
323 | BUG_ON(!list_empty(&qh->qtd_list)); | ||
324 | kmem_cache_free(qh_cachep, qh); | ||
325 | } | ||
326 | |||
327 | static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv, | ||
328 | gfp_t flags) | ||
329 | { | 379 | { |
330 | struct isp1760_qh *qh; | 380 | struct isp1760_qh *qh; |
331 | 381 | ||
332 | qh = kmem_cache_zalloc(qh_cachep, flags); | 382 | qh = kmem_cache_zalloc(qh_cachep, flags); |
333 | if (!qh) | 383 | if (!qh) |
334 | return qh; | 384 | return NULL; |
335 | 385 | ||
386 | INIT_LIST_HEAD(&qh->qh_list); | ||
336 | INIT_LIST_HEAD(&qh->qtd_list); | 387 | INIT_LIST_HEAD(&qh->qtd_list); |
337 | qh->priv = priv; | 388 | qh->slot = -1; |
389 | |||
338 | return qh; | 390 | return qh; |
339 | } | 391 | } |
340 | 392 | ||
341 | /* magic numbers that can affect system performance */ | 393 | static void qh_free(struct isp1760_qh *qh) |
342 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | 394 | { |
343 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | 395 | WARN_ON(!list_empty(&qh->qtd_list)); |
344 | #define EHCI_TUNE_RL_TT 0 | 396 | WARN_ON(qh->slot > -1); |
345 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | 397 | kmem_cache_free(qh_cachep, qh); |
346 | #define EHCI_TUNE_MULT_TT 1 | 398 | } |
347 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | ||
348 | 399 | ||
349 | /* one-time init, only for memory state */ | 400 | /* one-time init, only for memory state */ |
350 | static int priv_init(struct usb_hcd *hcd) | 401 | static int priv_init(struct usb_hcd *hcd) |
@@ -354,6 +405,10 @@ static int priv_init(struct usb_hcd *hcd) | |||
354 | 405 | ||
355 | spin_lock_init(&priv->lock); | 406 | spin_lock_init(&priv->lock); |
356 | 407 | ||
408 | INIT_LIST_HEAD(&priv->interruptqhs); | ||
409 | INIT_LIST_HEAD(&priv->controlqhs); | ||
410 | INIT_LIST_HEAD(&priv->bulkqhs); | ||
411 | |||
357 | /* | 412 | /* |
358 | * hw default: 1K periodic list heads, one per frame. | 413 | * hw default: 1K periodic list heads, one per frame. |
359 | * periodic_size can shrink by USBCMD update if hcc_params allows. | 414 | * periodic_size can shrink by USBCMD update if hcc_params allows. |
@@ -361,7 +416,7 @@ static int priv_init(struct usb_hcd *hcd) | |||
361 | priv->periodic_size = DEFAULT_I_TDPS; | 416 | priv->periodic_size = DEFAULT_I_TDPS; |
362 | 417 | ||
363 | /* controllers may cache some of the periodic schedule ... */ | 418 | /* controllers may cache some of the periodic schedule ... */ |
364 | hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS); | 419 | hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); |
365 | /* full frame cache */ | 420 | /* full frame cache */ |
366 | if (HCC_ISOC_CACHE(hcc_params)) | 421 | if (HCC_ISOC_CACHE(hcc_params)) |
367 | priv->i_thresh = 8; | 422 | priv->i_thresh = 8; |
@@ -398,46 +453,52 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) | |||
398 | * Write it twice to ensure correct upper bits if switching | 453 | * Write it twice to ensure correct upper bits if switching |
399 | * to 16-bit mode. | 454 | * to 16-bit mode. |
400 | */ | 455 | */ |
401 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | 456 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
402 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | 457 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
403 | 458 | ||
404 | isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG); | 459 | reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); |
405 | /* Change bus pattern */ | 460 | /* Change bus pattern */ |
406 | scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); | 461 | scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
407 | scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG); | 462 | scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); |
408 | if (scratch != 0xdeadbabe) { | 463 | if (scratch != 0xdeadbabe) { |
409 | printk(KERN_ERR "ISP1760: Scratch test failed.\n"); | 464 | dev_err(hcd->self.controller, "Scratch test failed.\n"); |
410 | return -ENODEV; | 465 | return -ENODEV; |
411 | } | 466 | } |
412 | 467 | ||
413 | /* pre reset */ | 468 | /* pre reset */ |
414 | isp1760_init_regs(hcd); | 469 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); |
470 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | ||
471 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | ||
472 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | ||
415 | 473 | ||
416 | /* reset */ | 474 | /* reset */ |
417 | isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG); | 475 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); |
418 | mdelay(100); | 476 | mdelay(100); |
419 | 477 | ||
420 | isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG); | 478 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); |
421 | mdelay(100); | 479 | mdelay(100); |
422 | 480 | ||
423 | result = ehci_reset(priv); | 481 | result = ehci_reset(hcd); |
424 | if (result) | 482 | if (result) |
425 | return result; | 483 | return result; |
426 | 484 | ||
427 | /* Step 11 passed */ | 485 | /* Step 11 passed */ |
428 | 486 | ||
429 | isp1760_info(priv, "bus width: %d, oc: %s\n", | 487 | dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", |
430 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? | 488 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? |
431 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? | 489 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? |
432 | "analog" : "digital"); | 490 | "analog" : "digital"); |
433 | 491 | ||
492 | /* This is weird: at the first plug-in of a device there seems to be | ||
493 | one packet queued that never gets returned? */ | ||
494 | priv->active_ptds = -1; | ||
495 | |||
434 | /* ATL reset */ | 496 | /* ATL reset */ |
435 | isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL); | 497 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); |
436 | mdelay(10); | 498 | mdelay(10); |
437 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | 499 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
438 | 500 | ||
439 | isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG); | 501 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); |
440 | isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE); | ||
441 | 502 | ||
442 | /* | 503 | /* |
443 | * PORT 1 Control register of the ISP1760 is the OTG control | 504 | * PORT 1 Control register of the ISP1760 is the OTG control |
@@ -445,11 +506,10 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) | |||
445 | * support in this driver, we use port 1 as a "normal" USB host port on | 506 | * support in this driver, we use port 1 as a "normal" USB host port on |
446 | * both chips. | 507 | * both chips. |
447 | */ | 508 | */ |
448 | isp1760_writel(PORT1_POWER | PORT1_INIT2, | 509 | reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); |
449 | hcd->regs + HC_PORT1_CTRL); | ||
450 | mdelay(10); | 510 | mdelay(10); |
451 | 511 | ||
452 | priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS); | 512 | priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); |
453 | 513 | ||
454 | return priv_init(hcd); | 514 | return priv_init(hcd); |
455 | } | 515 | } |
@@ -457,25 +517,31 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) | |||
457 | static void isp1760_init_maps(struct usb_hcd *hcd) | 517 | static void isp1760_init_maps(struct usb_hcd *hcd) |
458 | { | 518 | { |
459 | /*set last maps, for iso its only 1, else 32 tds bitmap*/ | 519 | /*set last maps, for iso its only 1, else 32 tds bitmap*/ |
460 | isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG); | 520 | reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); |
461 | isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG); | 521 | reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); |
462 | isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG); | 522 | reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); |
523 | |||
524 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); | ||
525 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); | ||
526 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); | ||
527 | |||
528 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, | ||
529 | ATL_BUF_FILL | INT_BUF_FILL); | ||
463 | } | 530 | } |
464 | 531 | ||
465 | static void isp1760_enable_interrupts(struct usb_hcd *hcd) | 532 | static void isp1760_enable_interrupts(struct usb_hcd *hcd) |
466 | { | 533 | { |
467 | isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG); | 534 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); |
468 | isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | 535 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); |
469 | isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG); | 536 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); |
470 | isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG); | 537 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); |
471 | isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG); | 538 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); |
472 | isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG); | 539 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); |
473 | /* step 23 passed */ | 540 | /* step 23 passed */ |
474 | } | 541 | } |
475 | 542 | ||
476 | static int isp1760_run(struct usb_hcd *hcd) | 543 | static int isp1760_run(struct usb_hcd *hcd) |
477 | { | 544 | { |
478 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
479 | int retval; | 545 | int retval; |
480 | u32 temp; | 546 | u32 temp; |
481 | u32 command; | 547 | u32 command; |
@@ -485,16 +551,15 @@ static int isp1760_run(struct usb_hcd *hcd) | |||
485 | 551 | ||
486 | hcd->state = HC_STATE_RUNNING; | 552 | hcd->state = HC_STATE_RUNNING; |
487 | isp1760_enable_interrupts(hcd); | 553 | isp1760_enable_interrupts(hcd); |
488 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | 554 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
489 | isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | 555 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); |
490 | 556 | ||
491 | command = isp1760_readl(hcd->regs + HC_USBCMD); | 557 | command = reg_read32(hcd->regs, HC_USBCMD); |
492 | command &= ~(CMD_LRESET|CMD_RESET); | 558 | command &= ~(CMD_LRESET|CMD_RESET); |
493 | command |= CMD_RUN; | 559 | command |= CMD_RUN; |
494 | isp1760_writel(command, hcd->regs + HC_USBCMD); | 560 | reg_write32(hcd->regs, HC_USBCMD, command); |
495 | 561 | ||
496 | retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN, | 562 | retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); |
497 | 250 * 1000); | ||
498 | if (retval) | 563 | if (retval) |
499 | return retval; | 564 | return retval; |
500 | 565 | ||
@@ -504,17 +569,16 @@ static int isp1760_run(struct usb_hcd *hcd) | |||
504 | * the semaphore while doing so. | 569 | * the semaphore while doing so. |
505 | */ | 570 | */ |
506 | down_write(&ehci_cf_port_reset_rwsem); | 571 | down_write(&ehci_cf_port_reset_rwsem); |
507 | isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG); | 572 | reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); |
508 | 573 | ||
509 | retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF, | 574 | retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); |
510 | 250 * 1000); | ||
511 | up_write(&ehci_cf_port_reset_rwsem); | 575 | up_write(&ehci_cf_port_reset_rwsem); |
512 | if (retval) | 576 | if (retval) |
513 | return retval; | 577 | return retval; |
514 | 578 | ||
515 | chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); | 579 | chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
516 | isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff, | 580 | dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", |
517 | chipid >> 16); | 581 | chipid & 0xffff, chipid >> 16); |
518 | 582 | ||
519 | /* PTD Register Init Part 2, Step 28 */ | 583 | /* PTD Register Init Part 2, Step 28 */ |
520 | /* enable INTs */ | 584 | /* enable INTs */ |
@@ -532,378 +596,169 @@ static u32 base_to_chip(u32 base) | |||
532 | return ((base - 0x400) >> 3); | 596 | return ((base - 0x400) >> 3); |
533 | } | 597 | } |
534 | 598 | ||
535 | static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh, | 599 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
536 | struct isp1760_qtd *qtd, struct urb *urb, | 600 | { |
537 | u32 payload, struct ptd *ptd) | 601 | struct urb *urb; |
602 | |||
603 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) | ||
604 | return 1; | ||
605 | |||
606 | urb = qtd->urb; | ||
607 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); | ||
608 | return (qtd->urb != urb); | ||
609 | } | ||
610 | |||
611 | /* magic numbers that can affect system performance */ | ||
612 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | ||
613 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | ||
614 | #define EHCI_TUNE_RL_TT 0 | ||
615 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | ||
616 | #define EHCI_TUNE_MULT_TT 1 | ||
617 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | ||
618 | |||
619 | static void create_ptd_atl(struct isp1760_qh *qh, | ||
620 | struct isp1760_qtd *qtd, struct ptd *ptd) | ||
538 | { | 621 | { |
539 | u32 dw0; | ||
540 | u32 dw1; | ||
541 | u32 dw2; | ||
542 | u32 dw3; | ||
543 | u32 maxpacket; | 622 | u32 maxpacket; |
544 | u32 multi; | 623 | u32 multi; |
545 | u32 pid_code; | ||
546 | u32 rl = RL_COUNTER; | 624 | u32 rl = RL_COUNTER; |
547 | u32 nak = NAK_COUNTER; | 625 | u32 nak = NAK_COUNTER; |
548 | 626 | ||
627 | memset(ptd, 0, sizeof(*ptd)); | ||
628 | |||
549 | /* according to 3.6.2, max packet len can not be > 0x400 */ | 629 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
550 | maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); | 630 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, |
631 | usb_pipeout(qtd->urb->pipe)); | ||
551 | multi = 1 + ((maxpacket >> 11) & 0x3); | 632 | multi = 1 + ((maxpacket >> 11) & 0x3); |
552 | maxpacket &= 0x7ff; | 633 | maxpacket &= 0x7ff; |
553 | 634 | ||
554 | /* DW0 */ | 635 | /* DW0 */ |
555 | dw0 = PTD_VALID; | 636 | ptd->dw0 = DW0_VALID_BIT; |
556 | dw0 |= PTD_LENGTH(qtd->length); | 637 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); |
557 | dw0 |= PTD_MAXPACKET(maxpacket); | 638 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); |
558 | dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe)); | 639 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); |
559 | dw1 = usb_pipeendpoint(urb->pipe) >> 1; | ||
560 | 640 | ||
561 | /* DW1 */ | 641 | /* DW1 */ |
562 | dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe)); | 642 | ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; |
643 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); | ||
644 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); | ||
563 | 645 | ||
564 | pid_code = qtd->packet_type; | 646 | if (usb_pipebulk(qtd->urb->pipe)) |
565 | dw1 |= PTD_PID_TOKEN(pid_code); | 647 | ptd->dw1 |= DW1_TRANS_BULK; |
648 | else if (usb_pipeint(qtd->urb->pipe)) | ||
649 | ptd->dw1 |= DW1_TRANS_INT; | ||
566 | 650 | ||
567 | if (usb_pipebulk(urb->pipe)) | 651 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
568 | dw1 |= PTD_TRANS_BULK; | ||
569 | else if (usb_pipeint(urb->pipe)) | ||
570 | dw1 |= PTD_TRANS_INT; | ||
571 | |||
572 | if (urb->dev->speed != USB_SPEED_HIGH) { | ||
573 | /* split transaction */ | 652 | /* split transaction */ |
574 | 653 | ||
575 | dw1 |= PTD_TRANS_SPLIT; | 654 | ptd->dw1 |= DW1_TRANS_SPLIT; |
576 | if (urb->dev->speed == USB_SPEED_LOW) | 655 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
577 | dw1 |= PTD_SE_USB_LOSPEED; | 656 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
578 | 657 | ||
579 | dw1 |= PTD_PORT_NUM(urb->dev->ttport); | 658 | ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); |
580 | dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum); | 659 | ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); |
581 | 660 | ||
582 | /* SE bit for Split INT transfers */ | 661 | /* SE bit for Split INT transfers */ |
583 | if (usb_pipeint(urb->pipe) && | 662 | if (usb_pipeint(qtd->urb->pipe) && |
584 | (urb->dev->speed == USB_SPEED_LOW)) | 663 | (qtd->urb->dev->speed == USB_SPEED_LOW)) |
585 | dw1 |= 2 << 16; | 664 | ptd->dw1 |= 2 << 16; |
586 | 665 | ||
587 | dw3 = 0; | ||
588 | rl = 0; | 666 | rl = 0; |
589 | nak = 0; | 667 | nak = 0; |
590 | } else { | 668 | } else { |
591 | dw0 |= PTD_MULTI(multi); | 669 | ptd->dw0 |= TO_DW0_MULTI(multi); |
592 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) | 670 | if (usb_pipecontrol(qtd->urb->pipe) || |
593 | dw3 = qh->ping; | 671 | usb_pipebulk(qtd->urb->pipe)) |
594 | else | 672 | ptd->dw3 |= TO_DW3_PING(qh->ping); |
595 | dw3 = 0; | ||
596 | } | 673 | } |
597 | /* DW2 */ | 674 | /* DW2 */ |
598 | dw2 = 0; | 675 | ptd->dw2 = 0; |
599 | dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload)); | 676 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
600 | dw2 |= PTD_RL_CNT(rl); | 677 | ptd->dw2 |= TO_DW2_RL(rl); |
601 | dw3 |= PTD_NAC_CNT(nak); | ||
602 | 678 | ||
603 | /* DW3 */ | 679 | /* DW3 */ |
604 | if (usb_pipecontrol(urb->pipe)) | 680 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
605 | dw3 |= PTD_DATA_TOGGLE(qtd->toggle); | 681 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); |
606 | else | 682 | if (usb_pipecontrol(qtd->urb->pipe)) { |
607 | dw3 |= qh->toggle; | 683 | if (qtd->data_buffer == qtd->urb->setup_packet) |
608 | 684 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); | |
685 | else if (last_qtd_of_urb(qtd, qh)) | ||
686 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); | ||
687 | } | ||
609 | 688 | ||
610 | dw3 |= PTD_ACTIVE; | 689 | ptd->dw3 |= DW3_ACTIVE_BIT; |
611 | /* Cerr */ | 690 | /* Cerr */ |
612 | dw3 |= PTD_CERR(ERR_COUNTER); | 691 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
613 | |||
614 | memset(ptd, 0, sizeof(*ptd)); | ||
615 | |||
616 | ptd->dw0 = cpu_to_le32(dw0); | ||
617 | ptd->dw1 = cpu_to_le32(dw1); | ||
618 | ptd->dw2 = cpu_to_le32(dw2); | ||
619 | ptd->dw3 = cpu_to_le32(dw3); | ||
620 | } | 692 | } |
621 | 693 | ||
622 | static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, | 694 | static void transform_add_int(struct isp1760_qh *qh, |
623 | struct isp1760_qtd *qtd, struct urb *urb, | 695 | struct isp1760_qtd *qtd, struct ptd *ptd) |
624 | u32 payload, struct ptd *ptd) | ||
625 | { | 696 | { |
626 | u32 maxpacket; | 697 | u32 usof; |
627 | u32 multi; | ||
628 | u32 numberofusofs; | ||
629 | u32 i; | ||
630 | u32 usofmask, usof; | ||
631 | u32 period; | 698 | u32 period; |
632 | 699 | ||
633 | maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); | 700 | /* |
634 | multi = 1 + ((maxpacket >> 11) & 0x3); | 701 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and |
635 | maxpacket &= 0x7ff; | 702 | * the algorithm from the original Philips driver code, which was |
636 | /* length of the data per uframe */ | 703 | * pretty much used in this driver before as well, is quite horrendous |
637 | maxpacket = multi * maxpacket; | 704 | * and, i believe, incorrect. The code below follows the datasheet and |
638 | 705 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much | |
639 | numberofusofs = urb->transfer_buffer_length / maxpacket; | 706 | * more reliable this way (fingers crossed...). |
640 | if (urb->transfer_buffer_length % maxpacket) | 707 | */ |
641 | numberofusofs += 1; | ||
642 | |||
643 | usofmask = 1; | ||
644 | usof = 0; | ||
645 | for (i = 0; i < numberofusofs; i++) { | ||
646 | usof |= usofmask; | ||
647 | usofmask <<= 1; | ||
648 | } | ||
649 | |||
650 | if (urb->dev->speed != USB_SPEED_HIGH) { | ||
651 | /* split */ | ||
652 | ptd->dw5 = cpu_to_le32(0x1c); | ||
653 | 708 | ||
654 | if (qh->period >= 32) | 709 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
655 | period = qh->period / 2; | 710 | /* urb->interval is in units of microframes (1/8 ms) */ |
711 | period = qtd->urb->interval >> 3; | ||
712 | |||
713 | if (qtd->urb->interval > 4) | ||
714 | usof = 0x01; /* One bit set => | ||
715 | interval 1 ms * uFrame-match */ | ||
716 | else if (qtd->urb->interval > 2) | ||
717 | usof = 0x22; /* Two bits set => interval 1/2 ms */ | ||
718 | else if (qtd->urb->interval > 1) | ||
719 | usof = 0x55; /* Four bits set => interval 1/4 ms */ | ||
656 | else | 720 | else |
657 | period = qh->period; | 721 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
658 | |||
659 | } else { | 722 | } else { |
723 | /* urb->interval is in units of frames (1 ms) */ | ||
724 | period = qtd->urb->interval; | ||
725 | usof = 0x0f; /* Execute Start Split on any of the | ||
726 | four first uFrames */ | ||
660 | 727 | ||
661 | if (qh->period >= 8) | 728 | /* |
662 | period = qh->period/8; | 729 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the |
663 | else | 730 | * complete split needs to be sent. Valid only for IN." Also, |
664 | period = qh->period; | 731 | * "All bits can be set to one for every transfer." (p 82, |
665 | 732 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did | |
666 | if (period >= 32) | 733 | * that number come from? 0xff seems to work fine... |
667 | period = 16; | 734 | */ |
668 | 735 | /* ptd->dw5 = 0x1c; */ | |
669 | if (qh->period >= 8) { | 736 | ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ |
670 | /* millisecond period */ | ||
671 | period = (period << 3); | ||
672 | } else { | ||
673 | /* usof based tranmsfers */ | ||
674 | /* minimum 4 usofs */ | ||
675 | usof = 0x11; | ||
676 | } | ||
677 | } | ||
678 | |||
679 | ptd->dw2 |= cpu_to_le32(period); | ||
680 | ptd->dw4 = cpu_to_le32(usof); | ||
681 | } | ||
682 | |||
683 | static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, | ||
684 | struct isp1760_qtd *qtd, struct urb *urb, | ||
685 | u32 payload, struct ptd *ptd) | ||
686 | { | ||
687 | transform_into_atl(priv, qh, qtd, urb, payload, ptd); | ||
688 | transform_add_int(priv, qh, qtd, urb, payload, ptd); | ||
689 | } | ||
690 | |||
691 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len, | ||
692 | u32 token) | ||
693 | { | ||
694 | int count; | ||
695 | |||
696 | qtd->data_buffer = databuffer; | ||
697 | qtd->packet_type = GET_QTD_TOKEN_TYPE(token); | ||
698 | qtd->toggle = GET_DATA_TOGGLE(token); | ||
699 | |||
700 | if (len > HC_ATL_PL_SIZE) | ||
701 | count = HC_ATL_PL_SIZE; | ||
702 | else | ||
703 | count = len; | ||
704 | |||
705 | qtd->length = count; | ||
706 | return count; | ||
707 | } | ||
708 | |||
709 | static int check_error(struct ptd *ptd) | ||
710 | { | ||
711 | int error = 0; | ||
712 | u32 dw3; | ||
713 | |||
714 | dw3 = le32_to_cpu(ptd->dw3); | ||
715 | if (dw3 & DW3_HALT_BIT) { | ||
716 | error = -EPIPE; | ||
717 | |||
718 | if (dw3 & DW3_ERROR_BIT) | ||
719 | pr_err("error bit is set in DW3\n"); | ||
720 | } | ||
721 | |||
722 | if (dw3 & DW3_QTD_ACTIVE) { | ||
723 | printk(KERN_ERR "transfer active bit is set DW3\n"); | ||
724 | printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf, | ||
725 | (le32_to_cpu(ptd->dw2) >> 25) & 0xf); | ||
726 | } | ||
727 | |||
728 | return error; | ||
729 | } | ||
730 | |||
731 | static void check_int_err_status(u32 dw4) | ||
732 | { | ||
733 | u32 i; | ||
734 | |||
735 | dw4 >>= 8; | ||
736 | |||
737 | for (i = 0; i < 8; i++) { | ||
738 | switch (dw4 & 0x7) { | ||
739 | case INT_UNDERRUN: | ||
740 | printk(KERN_ERR "ERROR: under run , %d\n", i); | ||
741 | break; | ||
742 | |||
743 | case INT_EXACT: | ||
744 | printk(KERN_ERR "ERROR: transaction error, %d\n", i); | ||
745 | break; | ||
746 | |||
747 | case INT_BABBLE: | ||
748 | printk(KERN_ERR "ERROR: babble error, %d\n", i); | ||
749 | break; | ||
750 | } | ||
751 | dw4 >>= 3; | ||
752 | } | ||
753 | } | ||
754 | |||
755 | static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv, | ||
756 | u32 payload) | ||
757 | { | ||
758 | u32 token; | ||
759 | struct usb_hcd *hcd = priv_to_hcd(priv); | ||
760 | |||
761 | token = qtd->packet_type; | ||
762 | |||
763 | if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) { | ||
764 | switch (token) { | ||
765 | case IN_PID: | ||
766 | break; | ||
767 | case OUT_PID: | ||
768 | case SETUP_PID: | ||
769 | priv_write_copy(priv, qtd->data_buffer, | ||
770 | hcd->regs + payload, | ||
771 | qtd->length); | ||
772 | } | ||
773 | } | 737 | } |
774 | } | ||
775 | |||
776 | static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload, | ||
777 | struct isp1760_hcd *priv, struct isp1760_qh *qh, | ||
778 | struct urb *urb, u32 slot, struct isp1760_qtd *qtd) | ||
779 | { | ||
780 | struct ptd ptd; | ||
781 | struct usb_hcd *hcd = priv_to_hcd(priv); | ||
782 | |||
783 | transform_into_atl(priv, qh, qtd, urb, payload, &ptd); | ||
784 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd)); | ||
785 | enqueue_one_qtd(qtd, priv, payload); | ||
786 | |||
787 | priv->atl_ints[slot].urb = urb; | ||
788 | priv->atl_ints[slot].qh = qh; | ||
789 | priv->atl_ints[slot].qtd = qtd; | ||
790 | priv->atl_ints[slot].data_buffer = qtd->data_buffer; | ||
791 | priv->atl_ints[slot].payload = payload; | ||
792 | qtd->status |= URB_ENQUEUED | URB_TYPE_ATL; | ||
793 | qtd->status |= slot << 16; | ||
794 | } | ||
795 | |||
796 | static void enqueue_one_int_qtd(u32 int_regs, u32 payload, | ||
797 | struct isp1760_hcd *priv, struct isp1760_qh *qh, | ||
798 | struct urb *urb, u32 slot, struct isp1760_qtd *qtd) | ||
799 | { | ||
800 | struct ptd ptd; | ||
801 | struct usb_hcd *hcd = priv_to_hcd(priv); | ||
802 | |||
803 | transform_into_int(priv, qh, qtd, urb, payload, &ptd); | ||
804 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd)); | ||
805 | enqueue_one_qtd(qtd, priv, payload); | ||
806 | |||
807 | priv->int_ints[slot].urb = urb; | ||
808 | priv->int_ints[slot].qh = qh; | ||
809 | priv->int_ints[slot].qtd = qtd; | ||
810 | priv->int_ints[slot].data_buffer = qtd->data_buffer; | ||
811 | priv->int_ints[slot].payload = payload; | ||
812 | qtd->status |= URB_ENQUEUED | URB_TYPE_INT; | ||
813 | qtd->status |= slot << 16; | ||
814 | } | ||
815 | |||
816 | static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, | ||
817 | struct isp1760_qtd *qtd) | ||
818 | { | ||
819 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
820 | u32 skip_map, or_map; | ||
821 | u32 queue_entry; | ||
822 | u32 slot; | ||
823 | u32 atl_regs, payload; | ||
824 | u32 buffstatus; | ||
825 | |||
826 | /* | ||
827 | * When this function is called from the interrupt handler to enqueue | ||
828 | * a follow-up packet, the SKIP register gets written and read back | ||
829 | * almost immediately. With ISP1761, this register requires a delay of | ||
830 | * 195ns between a write and subsequent read (see section 15.1.1.3). | ||
831 | */ | ||
832 | mmiowb(); | ||
833 | ndelay(195); | ||
834 | skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG); | ||
835 | |||
836 | BUG_ON(!skip_map); | ||
837 | slot = __ffs(skip_map); | ||
838 | queue_entry = 1 << slot; | ||
839 | |||
840 | atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd); | ||
841 | 738 | ||
842 | payload = alloc_mem(priv, qtd->length); | 739 | period = period >> 1;/* Ensure equal or shorter period than requested */ |
740 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ | ||
843 | 741 | ||
844 | enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd); | 742 | ptd->dw2 |= period; |
845 | 743 | ptd->dw4 = usof; | |
846 | or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
847 | or_map |= queue_entry; | ||
848 | isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
849 | |||
850 | skip_map &= ~queue_entry; | ||
851 | isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG); | ||
852 | |||
853 | buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); | ||
854 | buffstatus |= ATL_BUFFER; | ||
855 | isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); | ||
856 | } | 744 | } |
857 | 745 | ||
858 | static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, | 746 | static void create_ptd_int(struct isp1760_qh *qh, |
859 | struct isp1760_qtd *qtd) | 747 | struct isp1760_qtd *qtd, struct ptd *ptd) |
860 | { | 748 | { |
861 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 749 | create_ptd_atl(qh, qtd, ptd); |
862 | u32 skip_map, or_map; | 750 | transform_add_int(qh, qtd, ptd); |
863 | u32 queue_entry; | ||
864 | u32 slot; | ||
865 | u32 int_regs, payload; | ||
866 | u32 buffstatus; | ||
867 | |||
868 | /* | ||
869 | * When this function is called from the interrupt handler to enqueue | ||
870 | * a follow-up packet, the SKIP register gets written and read back | ||
871 | * almost immediately. With ISP1761, this register requires a delay of | ||
872 | * 195ns between a write and subsequent read (see section 15.1.1.3). | ||
873 | */ | ||
874 | mmiowb(); | ||
875 | ndelay(195); | ||
876 | skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG); | ||
877 | |||
878 | BUG_ON(!skip_map); | ||
879 | slot = __ffs(skip_map); | ||
880 | queue_entry = 1 << slot; | ||
881 | |||
882 | int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd); | ||
883 | |||
884 | payload = alloc_mem(priv, qtd->length); | ||
885 | |||
886 | enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd); | ||
887 | |||
888 | or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG); | ||
889 | or_map |= queue_entry; | ||
890 | isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG); | ||
891 | |||
892 | skip_map &= ~queue_entry; | ||
893 | isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG); | ||
894 | |||
895 | buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); | ||
896 | buffstatus |= INT_BUFFER; | ||
897 | isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); | ||
898 | } | 751 | } |
899 | 752 | ||
900 | static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status) | 753 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
901 | __releases(priv->lock) | 754 | __releases(priv->lock) |
902 | __acquires(priv->lock) | 755 | __acquires(priv->lock) |
903 | { | 756 | { |
757 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
758 | |||
904 | if (!urb->unlinked) { | 759 | if (!urb->unlinked) { |
905 | if (status == -EINPROGRESS) | 760 | if (urb->status == -EINPROGRESS) |
906 | status = 0; | 761 | urb->status = 0; |
907 | } | 762 | } |
908 | 763 | ||
909 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { | 764 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
@@ -915,679 +770,660 @@ __acquires(priv->lock) | |||
915 | } | 770 | } |
916 | 771 | ||
917 | /* complete() can reenter this HCD */ | 772 | /* complete() can reenter this HCD */ |
918 | usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); | 773 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
919 | spin_unlock(&priv->lock); | 774 | spin_unlock(&priv->lock); |
920 | usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status); | 775 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
921 | spin_lock(&priv->lock); | 776 | spin_lock(&priv->lock); |
922 | } | 777 | } |
923 | 778 | ||
924 | static void isp1760_qtd_free(struct isp1760_qtd *qtd) | 779 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
780 | u8 packet_type) | ||
925 | { | 781 | { |
926 | kmem_cache_free(qtd_cachep, qtd); | 782 | struct isp1760_qtd *qtd; |
927 | } | ||
928 | |||
929 | static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd) | ||
930 | { | ||
931 | struct isp1760_qtd *tmp_qtd; | ||
932 | |||
933 | tmp_qtd = qtd->hw_next; | ||
934 | list_del(&qtd->qtd_list); | ||
935 | isp1760_qtd_free(qtd); | ||
936 | return tmp_qtd; | ||
937 | } | ||
938 | 783 | ||
939 | /* | 784 | qtd = kmem_cache_zalloc(qtd_cachep, flags); |
940 | * Remove this QTD from the QH list and free its memory. If this QTD | 785 | if (!qtd) |
941 | * isn't the last one than remove also his successor(s). | 786 | return NULL; |
942 | * Returns the QTD which is part of an new URB and should be enqueued. | ||
943 | */ | ||
944 | static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd) | ||
945 | { | ||
946 | struct isp1760_qtd *tmp_qtd; | ||
947 | int last_one; | ||
948 | 787 | ||
949 | do { | 788 | INIT_LIST_HEAD(&qtd->qtd_list); |
950 | tmp_qtd = qtd->hw_next; | 789 | qtd->urb = urb; |
951 | last_one = qtd->status & URB_COMPLETE_NOTIFY; | 790 | qtd->packet_type = packet_type; |
952 | list_del(&qtd->qtd_list); | 791 | qtd->status = QTD_ENQUEUED; |
953 | isp1760_qtd_free(qtd); | 792 | qtd->actual_length = 0; |
954 | qtd = tmp_qtd; | ||
955 | } while (!last_one && qtd); | ||
956 | 793 | ||
957 | return qtd; | 794 | return qtd; |
958 | } | 795 | } |
959 | 796 | ||
960 | static void do_atl_int(struct usb_hcd *usb_hcd) | 797 | static void qtd_free(struct isp1760_qtd *qtd) |
961 | { | 798 | { |
962 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | 799 | WARN_ON(qtd->payload_addr); |
963 | u32 done_map, skip_map; | 800 | kmem_cache_free(qtd_cachep, qtd); |
964 | struct ptd ptd; | 801 | } |
965 | struct urb *urb = NULL; | ||
966 | u32 atl_regs_base; | ||
967 | u32 atl_regs; | ||
968 | u32 queue_entry; | ||
969 | u32 payload; | ||
970 | u32 length; | ||
971 | u32 or_map; | ||
972 | u32 status = -EINVAL; | ||
973 | int error; | ||
974 | struct isp1760_qtd *qtd; | ||
975 | struct isp1760_qh *qh; | ||
976 | u32 rl; | ||
977 | u32 nakcount; | ||
978 | |||
979 | done_map = isp1760_readl(usb_hcd->regs + | ||
980 | HC_ATL_PTD_DONEMAP_REG); | ||
981 | skip_map = isp1760_readl(usb_hcd->regs + | ||
982 | HC_ATL_PTD_SKIPMAP_REG); | ||
983 | |||
984 | or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
985 | or_map &= ~done_map; | ||
986 | isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
987 | |||
988 | atl_regs_base = ATL_REGS_OFFSET; | ||
989 | while (done_map) { | ||
990 | u32 dw1; | ||
991 | u32 dw2; | ||
992 | u32 dw3; | ||
993 | |||
994 | status = 0; | ||
995 | |||
996 | queue_entry = __ffs(done_map); | ||
997 | done_map &= ~(1 << queue_entry); | ||
998 | skip_map |= 1 << queue_entry; | ||
999 | |||
1000 | atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd); | ||
1001 | |||
1002 | urb = priv->atl_ints[queue_entry].urb; | ||
1003 | qtd = priv->atl_ints[queue_entry].qtd; | ||
1004 | qh = priv->atl_ints[queue_entry].qh; | ||
1005 | payload = priv->atl_ints[queue_entry].payload; | ||
1006 | |||
1007 | if (!qh) { | ||
1008 | printk(KERN_ERR "qh is 0\n"); | ||
1009 | continue; | ||
1010 | } | ||
1011 | isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs + | ||
1012 | HC_MEMORY_REG); | ||
1013 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | ||
1014 | HC_MEMORY_REG); | ||
1015 | /* | ||
1016 | * write bank1 address twice to ensure the 90ns delay (time | ||
1017 | * between BANK0 write and the priv_read_copy() call is at | ||
1018 | * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns) | ||
1019 | */ | ||
1020 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | ||
1021 | HC_MEMORY_REG); | ||
1022 | |||
1023 | priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs + | ||
1024 | ISP_BANK(0), sizeof(ptd)); | ||
1025 | 802 | ||
1026 | dw1 = le32_to_cpu(ptd.dw1); | 803 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
1027 | dw2 = le32_to_cpu(ptd.dw2); | 804 | struct slotinfo *slots, struct isp1760_qtd *qtd, |
1028 | dw3 = le32_to_cpu(ptd.dw3); | 805 | struct isp1760_qh *qh, struct ptd *ptd) |
1029 | rl = (dw2 >> 25) & 0x0f; | 806 | { |
1030 | nakcount = (dw3 >> 19) & 0xf; | 807 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
808 | int skip_map; | ||
809 | |||
810 | WARN_ON((slot < 0) || (slot > 31)); | ||
811 | WARN_ON(qtd->length && !qtd->payload_addr); | ||
812 | WARN_ON(slots[slot].qtd); | ||
813 | WARN_ON(slots[slot].qh); | ||
814 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); | ||
815 | |||
816 | slots[slot].qtd = qtd; | ||
817 | slots[slot].qh = qh; | ||
818 | qh->slot = slot; | ||
819 | qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since | ||
820 | interrupt routine may preempt and expects this value. */ | ||
821 | ptd_write(hcd->regs, ptd_offset, slot, ptd); | ||
822 | priv->active_ptds++; | ||
823 | |||
824 | /* Make sure done map has not triggered from some unlinked transfer */ | ||
825 | if (ptd_offset == ATL_PTD_OFFSET) { | ||
826 | priv->atl_done_map |= reg_read32(hcd->regs, | ||
827 | HC_ATL_PTD_DONEMAP_REG); | ||
828 | priv->atl_done_map &= ~(1 << qh->slot); | ||
829 | |||
830 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | ||
831 | skip_map &= ~(1 << qh->slot); | ||
832 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | ||
833 | } else { | ||
834 | priv->int_done_map |= reg_read32(hcd->regs, | ||
835 | HC_INT_PTD_DONEMAP_REG); | ||
836 | priv->int_done_map &= ~(1 << qh->slot); | ||
1031 | 837 | ||
1032 | /* Transfer Error, *but* active and no HALT -> reload */ | 838 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
1033 | if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) && | 839 | skip_map &= ~(1 << qh->slot); |
1034 | !(dw3 & DW3_HALT_BIT)) { | 840 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); |
1035 | 841 | } | |
1036 | /* according to ppriv code, we have to | 842 | } |
1037 | * reload this one if trasfered bytes != requested bytes | ||
1038 | * else act like everything went smooth.. | ||
1039 | * XXX This just doesn't feel right and hasn't | ||
1040 | * triggered so far. | ||
1041 | */ | ||
1042 | 843 | ||
1043 | length = PTD_XFERRED_LENGTH(dw3); | 844 | static int is_short_bulk(struct isp1760_qtd *qtd) |
1044 | printk(KERN_ERR "Should reload now.... transfered %d " | 845 | { |
1045 | "of %zu\n", length, qtd->length); | 846 | return (usb_pipebulk(qtd->urb->pipe) && |
1046 | BUG(); | 847 | (qtd->actual_length < qtd->length)); |
1047 | } | 848 | } |
1048 | 849 | ||
1049 | if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) { | 850 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
1050 | u32 buffstatus; | 851 | struct list_head *urb_list) |
852 | { | ||
853 | int last_qtd; | ||
854 | struct isp1760_qtd *qtd, *qtd_next; | ||
855 | struct urb_listitem *urb_listitem; | ||
1051 | 856 | ||
1052 | /* | 857 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
1053 | * NAKs are handled in HW by the chip. Usually if the | 858 | if (qtd->status < QTD_XFER_COMPLETE) |
1054 | * device is not able to send data fast enough. | 859 | break; |
1055 | * This happens mostly on slower hardware. | ||
1056 | */ | ||
1057 | printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: " | ||
1058 | "%d of %zu done: %08x cur: %08x\n", qtd, | ||
1059 | urb, qh, PTD_XFERRED_LENGTH(dw3), | ||
1060 | qtd->length, done_map, | ||
1061 | (1 << queue_entry)); | ||
1062 | 860 | ||
1063 | /* RL counter = ERR counter */ | 861 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) |
1064 | dw3 &= ~(0xf << 19); | 862 | last_qtd = 1; |
1065 | dw3 |= rl << 19; | 863 | else |
1066 | dw3 &= ~(3 << (55 - 32)); | 864 | last_qtd = qtd->urb != qtd_next->urb; |
1067 | dw3 |= ERR_COUNTER << (55 - 32); | 865 | |
1068 | 866 | if ((!last_qtd) && (qtd->status == QTD_RETIRE)) | |
1069 | /* | 867 | qtd_next->status = QTD_RETIRE; |
1070 | * It is not needed to write skip map back because it | 868 | |
1071 | * is unchanged. Just make sure that this entry is | 869 | if (qtd->status == QTD_XFER_COMPLETE) { |
1072 | * unskipped once it gets written to the HW. | 870 | if (qtd->actual_length) { |
1073 | */ | 871 | switch (qtd->packet_type) { |
1074 | skip_map &= ~(1 << queue_entry); | 872 | case IN_PID: |
1075 | or_map = isp1760_readl(usb_hcd->regs + | 873 | mem_reads8(hcd->regs, qtd->payload_addr, |
1076 | HC_ATL_IRQ_MASK_OR_REG); | 874 | qtd->data_buffer, |
1077 | or_map |= 1 << queue_entry; | 875 | qtd->actual_length); |
1078 | isp1760_writel(or_map, usb_hcd->regs + | 876 | /* Fall through (?) */ |
1079 | HC_ATL_IRQ_MASK_OR_REG); | 877 | case OUT_PID: |
1080 | 878 | qtd->urb->actual_length += | |
1081 | ptd.dw3 = cpu_to_le32(dw3); | 879 | qtd->actual_length; |
1082 | priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + | 880 | /* Fall through ... */ |
1083 | atl_regs, sizeof(ptd)); | 881 | case SETUP_PID: |
1084 | 882 | break; | |
1085 | ptd.dw0 |= cpu_to_le32(PTD_VALID); | 883 | } |
1086 | priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + | 884 | } |
1087 | atl_regs, sizeof(ptd)); | ||
1088 | |||
1089 | buffstatus = isp1760_readl(usb_hcd->regs + | ||
1090 | HC_BUFFER_STATUS_REG); | ||
1091 | buffstatus |= ATL_BUFFER; | ||
1092 | isp1760_writel(buffstatus, usb_hcd->regs + | ||
1093 | HC_BUFFER_STATUS_REG); | ||
1094 | continue; | ||
1095 | } | ||
1096 | 885 | ||
1097 | error = check_error(&ptd); | 886 | if (is_short_bulk(qtd)) { |
1098 | if (error) { | 887 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) |
1099 | status = error; | 888 | qtd->urb->status = -EREMOTEIO; |
1100 | priv->atl_ints[queue_entry].qh->toggle = 0; | 889 | if (!last_qtd) |
1101 | priv->atl_ints[queue_entry].qh->ping = 0; | 890 | qtd_next->status = QTD_RETIRE; |
1102 | urb->status = -EPIPE; | ||
1103 | |||
1104 | #if 0 | ||
1105 | printk(KERN_ERR "Error in %s().\n", __func__); | ||
1106 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | ||
1107 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | ||
1108 | "%08x dw7: %08x\n", | ||
1109 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | ||
1110 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | ||
1111 | #endif | ||
1112 | } else { | ||
1113 | if (usb_pipetype(urb->pipe) == PIPE_BULK) { | ||
1114 | priv->atl_ints[queue_entry].qh->toggle = dw3 & | ||
1115 | (1 << 25); | ||
1116 | priv->atl_ints[queue_entry].qh->ping = dw3 & | ||
1117 | (1 << 26); | ||
1118 | } | 891 | } |
1119 | } | 892 | } |
1120 | 893 | ||
1121 | length = PTD_XFERRED_LENGTH(dw3); | 894 | if (qtd->payload_addr) |
1122 | if (length) { | 895 | free_mem(hcd, qtd); |
1123 | switch (DW1_GET_PID(dw1)) { | 896 | |
1124 | case IN_PID: | 897 | if (last_qtd) { |
1125 | priv_read_copy(priv, | 898 | if ((qtd->status == QTD_RETIRE) && |
1126 | priv->atl_ints[queue_entry].data_buffer, | 899 | (qtd->urb->status == -EINPROGRESS)) |
1127 | usb_hcd->regs + payload + ISP_BANK(1), | 900 | qtd->urb->status = -EPIPE; |
1128 | length); | 901 | /* Defer calling of urb_done() since it releases lock */ |
1129 | 902 | urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, | |
1130 | case OUT_PID: | 903 | GFP_ATOMIC); |
1131 | 904 | if (unlikely(!urb_listitem)) | |
1132 | urb->actual_length += length; | ||
1133 | |||
1134 | case SETUP_PID: | ||
1135 | break; | 905 | break; |
1136 | } | 906 | urb_listitem->urb = qtd->urb; |
907 | list_add_tail(&urb_listitem->urb_list, urb_list); | ||
1137 | } | 908 | } |
1138 | 909 | ||
1139 | priv->atl_ints[queue_entry].data_buffer = NULL; | 910 | list_del(&qtd->qtd_list); |
1140 | priv->atl_ints[queue_entry].urb = NULL; | 911 | qtd_free(qtd); |
1141 | priv->atl_ints[queue_entry].qtd = NULL; | 912 | } |
1142 | priv->atl_ints[queue_entry].qh = NULL; | 913 | } |
1143 | 914 | ||
1144 | free_mem(priv, payload); | 915 | #define ENQUEUE_DEPTH 2 |
916 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) | ||
917 | { | ||
918 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
919 | int ptd_offset; | ||
920 | struct slotinfo *slots; | ||
921 | int curr_slot, free_slot; | ||
922 | int n; | ||
923 | struct ptd ptd; | ||
924 | struct isp1760_qtd *qtd; | ||
1145 | 925 | ||
1146 | isp1760_writel(skip_map, usb_hcd->regs + | 926 | if (unlikely(list_empty(&qh->qtd_list))) { |
1147 | HC_ATL_PTD_SKIPMAP_REG); | 927 | WARN_ON(1); |
928 | return; | ||
929 | } | ||
1148 | 930 | ||
1149 | if (urb->status == -EPIPE) { | 931 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
1150 | /* HALT was received */ | 932 | qtd_list)->urb->pipe)) { |
933 | ptd_offset = INT_PTD_OFFSET; | ||
934 | slots = priv->int_slots; | ||
935 | } else { | ||
936 | ptd_offset = ATL_PTD_OFFSET; | ||
937 | slots = priv->atl_slots; | ||
938 | } | ||
1151 | 939 | ||
1152 | qtd = clean_up_qtdlist(qtd); | 940 | free_slot = -1; |
1153 | isp1760_urb_done(priv, urb, urb->status); | 941 | for (curr_slot = 0; curr_slot < 32; curr_slot++) { |
942 | if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) | ||
943 | free_slot = curr_slot; | ||
944 | if (slots[curr_slot].qh == qh) | ||
945 | break; | ||
946 | } | ||
1154 | 947 | ||
1155 | } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) { | 948 | n = 0; |
1156 | /* short BULK received */ | 949 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
950 | if (qtd->status == QTD_ENQUEUED) { | ||
951 | WARN_ON(qtd->payload_addr); | ||
952 | alloc_mem(hcd, qtd); | ||
953 | if ((qtd->length) && (!qtd->payload_addr)) | ||
954 | break; | ||
1157 | 955 | ||
1158 | if (urb->transfer_flags & URB_SHORT_NOT_OK) { | 956 | if ((qtd->length) && |
1159 | urb->status = -EREMOTEIO; | 957 | ((qtd->packet_type == SETUP_PID) || |
1160 | isp1760_dbg(priv, "short bulk, %d instead %zu " | 958 | (qtd->packet_type == OUT_PID))) { |
1161 | "with URB_SHORT_NOT_OK flag.\n", | 959 | mem_writes8(hcd->regs, qtd->payload_addr, |
1162 | length, qtd->length); | 960 | qtd->data_buffer, qtd->length); |
1163 | } | 961 | } |
1164 | 962 | ||
1165 | if (urb->status == -EINPROGRESS) | 963 | qtd->status = QTD_PAYLOAD_ALLOC; |
1166 | urb->status = 0; | ||
1167 | |||
1168 | qtd = clean_up_qtdlist(qtd); | ||
1169 | |||
1170 | isp1760_urb_done(priv, urb, urb->status); | ||
1171 | |||
1172 | } else if (qtd->status & URB_COMPLETE_NOTIFY) { | ||
1173 | /* that was the last qtd of that URB */ | ||
1174 | |||
1175 | if (urb->status == -EINPROGRESS) | ||
1176 | urb->status = 0; | ||
1177 | |||
1178 | qtd = clean_this_qtd(qtd); | ||
1179 | isp1760_urb_done(priv, urb, urb->status); | ||
1180 | |||
1181 | } else { | ||
1182 | /* next QTD of this URB */ | ||
1183 | |||
1184 | qtd = clean_this_qtd(qtd); | ||
1185 | BUG_ON(!qtd); | ||
1186 | } | 964 | } |
1187 | 965 | ||
1188 | if (qtd) | 966 | if (qtd->status == QTD_PAYLOAD_ALLOC) { |
1189 | enqueue_an_ATL_packet(usb_hcd, qh, qtd); | 967 | /* |
968 | if ((curr_slot > 31) && (free_slot == -1)) | ||
969 | dev_dbg(hcd->self.controller, "%s: No slot " | ||
970 | "available for transfer\n", __func__); | ||
971 | */ | ||
972 | /* Start xfer for this endpoint if not already done */ | ||
973 | if ((curr_slot > 31) && (free_slot > -1)) { | ||
974 | if (usb_pipeint(qtd->urb->pipe)) | ||
975 | create_ptd_int(qh, qtd, &ptd); | ||
976 | else | ||
977 | create_ptd_atl(qh, qtd, &ptd); | ||
978 | |||
979 | start_bus_transfer(hcd, ptd_offset, free_slot, | ||
980 | slots, qtd, qh, &ptd); | ||
981 | curr_slot = free_slot; | ||
982 | } | ||
1190 | 983 | ||
1191 | skip_map = isp1760_readl(usb_hcd->regs + | 984 | n++; |
1192 | HC_ATL_PTD_SKIPMAP_REG); | 985 | if (n >= ENQUEUE_DEPTH) |
986 | break; | ||
987 | } | ||
1193 | } | 988 | } |
1194 | } | 989 | } |
1195 | 990 | ||
1196 | static void do_intl_int(struct usb_hcd *usb_hcd) | 991 | void schedule_ptds(struct usb_hcd *hcd) |
1197 | { | 992 | { |
1198 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | 993 | struct isp1760_hcd *priv; |
1199 | u32 done_map, skip_map; | 994 | struct isp1760_qh *qh, *qh_next; |
1200 | struct ptd ptd; | 995 | struct list_head *ep_queue; |
1201 | struct urb *urb = NULL; | 996 | struct usb_host_endpoint *ep; |
1202 | u32 int_regs; | 997 | LIST_HEAD(urb_list); |
1203 | u32 int_regs_base; | 998 | struct urb_listitem *urb_listitem, *urb_listitem_next; |
1204 | u32 payload; | 999 | |
1205 | u32 length; | 1000 | if (!hcd) { |
1206 | u32 or_map; | 1001 | WARN_ON(1); |
1207 | int error; | 1002 | return; |
1208 | u32 queue_entry; | 1003 | } |
1209 | struct isp1760_qtd *qtd; | ||
1210 | struct isp1760_qh *qh; | ||
1211 | |||
1212 | done_map = isp1760_readl(usb_hcd->regs + | ||
1213 | HC_INT_PTD_DONEMAP_REG); | ||
1214 | skip_map = isp1760_readl(usb_hcd->regs + | ||
1215 | HC_INT_PTD_SKIPMAP_REG); | ||
1216 | 1004 | ||
1217 | or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); | 1005 | priv = hcd_to_priv(hcd); |
1218 | or_map &= ~done_map; | ||
1219 | isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); | ||
1220 | 1006 | ||
1221 | int_regs_base = INT_REGS_OFFSET; | 1007 | /* |
1008 | * check finished/retired xfers, transfer payloads, call urb_done() | ||
1009 | */ | ||
1010 | ep_queue = &priv->interruptqhs; | ||
1011 | while (ep_queue) { | ||
1012 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { | ||
1013 | ep = list_entry(qh->qtd_list.next, struct isp1760_qtd, | ||
1014 | qtd_list)->urb->ep; | ||
1015 | collect_qtds(hcd, qh, &urb_list); | ||
1016 | if (list_empty(&qh->qtd_list)) { | ||
1017 | list_del(&qh->qh_list); | ||
1018 | if (ep->hcpriv == NULL) { | ||
1019 | /* Endpoint has been disabled, so we | ||
1020 | can free the associated queue head. */ | ||
1021 | qh_free(qh); | ||
1022 | } | ||
1023 | } | ||
1024 | } | ||
1222 | 1025 | ||
1223 | while (done_map) { | 1026 | if (ep_queue == &priv->interruptqhs) |
1224 | u32 dw1; | 1027 | ep_queue = &priv->controlqhs; |
1225 | u32 dw3; | 1028 | else if (ep_queue == &priv->controlqhs) |
1029 | ep_queue = &priv->bulkqhs; | ||
1030 | else | ||
1031 | ep_queue = NULL; | ||
1032 | } | ||
1226 | 1033 | ||
1227 | queue_entry = __ffs(done_map); | 1034 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
1228 | done_map &= ~(1 << queue_entry); | 1035 | urb_list) { |
1229 | skip_map |= 1 << queue_entry; | 1036 | isp1760_urb_done(hcd, urb_listitem->urb); |
1037 | kmem_cache_free(urb_listitem_cachep, urb_listitem); | ||
1038 | } | ||
1230 | 1039 | ||
1231 | int_regs = int_regs_base + queue_entry * sizeof(struct ptd); | 1040 | /* |
1232 | urb = priv->int_ints[queue_entry].urb; | 1041 | * Schedule packets for transfer. |
1233 | qtd = priv->int_ints[queue_entry].qtd; | 1042 | * |
1234 | qh = priv->int_ints[queue_entry].qh; | 1043 | * According to USB2.0 specification: |
1235 | payload = priv->int_ints[queue_entry].payload; | 1044 | * |
1045 | * 1st prio: interrupt xfers, up to 80 % of bandwidth | ||
1046 | * 2nd prio: control xfers | ||
1047 | * 3rd prio: bulk xfers | ||
1048 | * | ||
1049 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc | ||
1050 | * is very unclear on how to prioritize traffic): | ||
1051 | * | ||
1052 | * 1) Enqueue any queued control transfers, as long as payload chip mem | ||
1053 | * and PTD ATL slots are available. | ||
1054 | * 2) Enqueue any queued INT transfers, as long as payload chip mem | ||
1055 | * and PTD INT slots are available. | ||
1056 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem | ||
1057 | * and PTD ATL slots are available. | ||
1058 | * | ||
1059 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between | ||
1060 | * conservation of chip mem and performance. | ||
1061 | * | ||
1062 | * I'm sure this scheme could be improved upon! | ||
1063 | */ | ||
1064 | ep_queue = &priv->controlqhs; | ||
1065 | while (ep_queue) { | ||
1066 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) | ||
1067 | enqueue_qtds(hcd, qh); | ||
1068 | |||
1069 | if (ep_queue == &priv->controlqhs) | ||
1070 | ep_queue = &priv->interruptqhs; | ||
1071 | else if (ep_queue == &priv->interruptqhs) | ||
1072 | ep_queue = &priv->bulkqhs; | ||
1073 | else | ||
1074 | ep_queue = NULL; | ||
1075 | } | ||
1076 | } | ||
1236 | 1077 | ||
1237 | if (!qh) { | 1078 | #define PTD_STATE_QTD_DONE 1 |
1238 | printk(KERN_ERR "(INT) qh is 0\n"); | 1079 | #define PTD_STATE_QTD_RELOAD 2 |
1239 | continue; | 1080 | #define PTD_STATE_URB_RETIRE 3 |
1240 | } | ||
1241 | 1081 | ||
1242 | isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs + | 1082 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1243 | HC_MEMORY_REG); | 1083 | struct urb *urb) |
1244 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | 1084 | { |
1245 | HC_MEMORY_REG); | 1085 | __dw dw4; |
1246 | /* | 1086 | int i; |
1247 | * write bank1 address twice to ensure the 90ns delay (time | ||
1248 | * between BANK0 write and the priv_read_copy() call is at | ||
1249 | * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns) | ||
1250 | */ | ||
1251 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | ||
1252 | HC_MEMORY_REG); | ||
1253 | |||
1254 | priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs + | ||
1255 | ISP_BANK(0), sizeof(ptd)); | ||
1256 | dw1 = le32_to_cpu(ptd.dw1); | ||
1257 | dw3 = le32_to_cpu(ptd.dw3); | ||
1258 | check_int_err_status(le32_to_cpu(ptd.dw4)); | ||
1259 | |||
1260 | error = check_error(&ptd); | ||
1261 | if (error) { | ||
1262 | #if 0 | ||
1263 | printk(KERN_ERR "Error in %s().\n", __func__); | ||
1264 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | ||
1265 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | ||
1266 | "%08x dw7: %08x\n", | ||
1267 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | ||
1268 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | ||
1269 | #endif | ||
1270 | urb->status = -EPIPE; | ||
1271 | priv->int_ints[queue_entry].qh->toggle = 0; | ||
1272 | priv->int_ints[queue_entry].qh->ping = 0; | ||
1273 | 1087 | ||
1274 | } else { | 1088 | dw4 = ptd->dw4; |
1275 | priv->int_ints[queue_entry].qh->toggle = | 1089 | dw4 >>= 8; |
1276 | dw3 & (1 << 25); | ||
1277 | priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26); | ||
1278 | } | ||
1279 | 1090 | ||
1280 | if (urb->dev->speed != USB_SPEED_HIGH) | 1091 | /* FIXME: ISP1761 datasheet does not say what to do with these. Do we |
1281 | length = PTD_XFERRED_LENGTH_LO(dw3); | 1092 | need to handle these errors? Is it done in hardware? */ |
1282 | else | ||
1283 | length = PTD_XFERRED_LENGTH(dw3); | ||
1284 | 1093 | ||
1285 | if (length) { | 1094 | if (ptd->dw3 & DW3_HALT_BIT) { |
1286 | switch (DW1_GET_PID(dw1)) { | ||
1287 | case IN_PID: | ||
1288 | priv_read_copy(priv, | ||
1289 | priv->int_ints[queue_entry].data_buffer, | ||
1290 | usb_hcd->regs + payload + ISP_BANK(1), | ||
1291 | length); | ||
1292 | case OUT_PID: | ||
1293 | 1095 | ||
1294 | urb->actual_length += length; | 1096 | urb->status = -EPROTO; /* Default unknown error */ |
1295 | 1097 | ||
1296 | case SETUP_PID: | 1098 | for (i = 0; i < 8; i++) { |
1099 | switch (dw4 & 0x7) { | ||
1100 | case INT_UNDERRUN: | ||
1101 | dev_dbg(hcd->self.controller, "%s: underrun " | ||
1102 | "during uFrame %d\n", | ||
1103 | __func__, i); | ||
1104 | urb->status = -ECOMM; /* Could not write data */ | ||
1105 | break; | ||
1106 | case INT_EXACT: | ||
1107 | dev_dbg(hcd->self.controller, "%s: transaction " | ||
1108 | "error during uFrame %d\n", | ||
1109 | __func__, i); | ||
1110 | urb->status = -EPROTO; /* timeout, bad CRC, PID | ||
1111 | error etc. */ | ||
1112 | break; | ||
1113 | case INT_BABBLE: | ||
1114 | dev_dbg(hcd->self.controller, "%s: babble " | ||
1115 | "error during uFrame %d\n", | ||
1116 | __func__, i); | ||
1117 | urb->status = -EOVERFLOW; | ||
1297 | break; | 1118 | break; |
1298 | } | 1119 | } |
1120 | dw4 >>= 3; | ||
1299 | } | 1121 | } |
1300 | 1122 | ||
1301 | priv->int_ints[queue_entry].data_buffer = NULL; | 1123 | return PTD_STATE_URB_RETIRE; |
1302 | priv->int_ints[queue_entry].urb = NULL; | 1124 | } |
1303 | priv->int_ints[queue_entry].qtd = NULL; | ||
1304 | priv->int_ints[queue_entry].qh = NULL; | ||
1305 | |||
1306 | isp1760_writel(skip_map, usb_hcd->regs + | ||
1307 | HC_INT_PTD_SKIPMAP_REG); | ||
1308 | free_mem(priv, payload); | ||
1309 | |||
1310 | if (urb->status == -EPIPE) { | ||
1311 | /* HALT received */ | ||
1312 | |||
1313 | qtd = clean_up_qtdlist(qtd); | ||
1314 | isp1760_urb_done(priv, urb, urb->status); | ||
1315 | |||
1316 | } else if (qtd->status & URB_COMPLETE_NOTIFY) { | ||
1317 | |||
1318 | if (urb->status == -EINPROGRESS) | ||
1319 | urb->status = 0; | ||
1320 | |||
1321 | qtd = clean_this_qtd(qtd); | ||
1322 | isp1760_urb_done(priv, urb, urb->status); | ||
1323 | 1125 | ||
1324 | } else { | 1126 | return PTD_STATE_QTD_DONE; |
1325 | /* next QTD of this URB */ | 1127 | } |
1326 | 1128 | ||
1327 | qtd = clean_this_qtd(qtd); | 1129 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1328 | BUG_ON(!qtd); | 1130 | struct urb *urb) |
1329 | } | 1131 | { |
1132 | WARN_ON(!ptd); | ||
1133 | if (ptd->dw3 & DW3_HALT_BIT) { | ||
1134 | if (ptd->dw3 & DW3_BABBLE_BIT) | ||
1135 | urb->status = -EOVERFLOW; | ||
1136 | else if (FROM_DW3_CERR(ptd->dw3)) | ||
1137 | urb->status = -EPIPE; /* Stall */ | ||
1138 | else if (ptd->dw3 & DW3_ERROR_BIT) | ||
1139 | urb->status = -EPROTO; /* XactErr */ | ||
1140 | else | ||
1141 | urb->status = -EPROTO; /* Unknown */ | ||
1142 | /* | ||
1143 | dev_dbg(hcd->self.controller, "%s: ptd error:\n" | ||
1144 | " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" | ||
1145 | " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", | ||
1146 | __func__, | ||
1147 | ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, | ||
1148 | ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); | ||
1149 | */ | ||
1150 | return PTD_STATE_URB_RETIRE; | ||
1151 | } | ||
1330 | 1152 | ||
1331 | if (qtd) | 1153 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1332 | enqueue_an_INT_packet(usb_hcd, qh, qtd); | 1154 | /* Transfer Error, *but* active and no HALT -> reload */ |
1155 | dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); | ||
1156 | return PTD_STATE_QTD_RELOAD; | ||
1157 | } | ||
1333 | 1158 | ||
1334 | skip_map = isp1760_readl(usb_hcd->regs + | 1159 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1335 | HC_INT_PTD_SKIPMAP_REG); | 1160 | /* |
1161 | * NAKs are handled in HW by the chip. Usually if the | ||
1162 | * device is not able to send data fast enough. | ||
1163 | * This happens mostly on slower hardware. | ||
1164 | */ | ||
1165 | return PTD_STATE_QTD_RELOAD; | ||
1336 | } | 1166 | } |
1167 | |||
1168 | return PTD_STATE_QTD_DONE; | ||
1337 | } | 1169 | } |
1338 | 1170 | ||
1339 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | 1171 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) |
1340 | static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb, | ||
1341 | gfp_t flags) | ||
1342 | { | 1172 | { |
1173 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
1174 | u32 imask; | ||
1175 | irqreturn_t irqret = IRQ_NONE; | ||
1176 | struct ptd ptd; | ||
1343 | struct isp1760_qh *qh; | 1177 | struct isp1760_qh *qh; |
1344 | int is_input, type; | 1178 | int slot; |
1345 | 1179 | int state; | |
1346 | qh = isp1760_qh_alloc(priv, flags); | 1180 | struct slotinfo *slots; |
1347 | if (!qh) | 1181 | u32 ptd_offset; |
1348 | return qh; | 1182 | struct isp1760_qtd *qtd; |
1349 | 1183 | int modified; | |
1350 | /* | 1184 | static int last_active_ptds; |
1351 | * init endpoint/device data for this QH | 1185 | int int_skip_map, atl_skip_map; |
1352 | */ | ||
1353 | is_input = usb_pipein(urb->pipe); | ||
1354 | type = usb_pipetype(urb->pipe); | ||
1355 | 1186 | ||
1356 | if (type == PIPE_INTERRUPT) { | 1187 | spin_lock(&priv->lock); |
1357 | 1188 | ||
1358 | if (urb->dev->speed == USB_SPEED_HIGH) { | 1189 | if (!(hcd->state & HC_STATE_RUNNING)) |
1190 | goto leave; | ||
1359 | 1191 | ||
1360 | qh->period = urb->interval >> 3; | 1192 | imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); |
1361 | if (qh->period == 0 && urb->interval != 1) { | 1193 | if (unlikely(!imask)) |
1362 | /* NOTE interval 2 or 4 uframes could work. | 1194 | goto leave; |
1363 | * But interval 1 scheduling is simpler, and | 1195 | reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ |
1364 | * includes high bandwidth. | 1196 | |
1365 | */ | 1197 | int_skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
1366 | printk(KERN_ERR "intr period %d uframes, NYET!", | 1198 | atl_skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
1367 | urb->interval); | 1199 | priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); |
1368 | qh_destroy(qh); | 1200 | priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); |
1369 | return NULL; | 1201 | priv->int_done_map &= ~int_skip_map; |
1202 | priv->atl_done_map &= ~atl_skip_map; | ||
1203 | |||
1204 | modified = priv->int_done_map | priv->atl_done_map; | ||
1205 | |||
1206 | while (priv->int_done_map || priv->atl_done_map) { | ||
1207 | if (priv->int_done_map) { | ||
1208 | /* INT ptd */ | ||
1209 | slot = __ffs(priv->int_done_map); | ||
1210 | priv->int_done_map &= ~(1 << slot); | ||
1211 | slots = priv->int_slots; | ||
1212 | /* This should not trigger, and could be removed if | ||
1213 | noone have any problems with it triggering: */ | ||
1214 | if (!slots[slot].qh) { | ||
1215 | WARN_ON(1); | ||
1216 | continue; | ||
1370 | } | 1217 | } |
1218 | ptd_offset = INT_PTD_OFFSET; | ||
1219 | ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); | ||
1220 | state = check_int_transfer(hcd, &ptd, | ||
1221 | slots[slot].qtd->urb); | ||
1371 | } else { | 1222 | } else { |
1372 | qh->period = urb->interval; | 1223 | /* ATL ptd */ |
1224 | slot = __ffs(priv->atl_done_map); | ||
1225 | priv->atl_done_map &= ~(1 << slot); | ||
1226 | slots = priv->atl_slots; | ||
1227 | /* This should not trigger, and could be removed if | ||
1228 | noone have any problems with it triggering: */ | ||
1229 | if (!slots[slot].qh) { | ||
1230 | WARN_ON(1); | ||
1231 | continue; | ||
1232 | } | ||
1233 | ptd_offset = ATL_PTD_OFFSET; | ||
1234 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); | ||
1235 | state = check_atl_transfer(hcd, &ptd, | ||
1236 | slots[slot].qtd->urb); | ||
1373 | } | 1237 | } |
1374 | } | ||
1375 | 1238 | ||
1376 | /* support for tt scheduling, and access to toggles */ | 1239 | qtd = slots[slot].qtd; |
1377 | qh->dev = urb->dev; | 1240 | slots[slot].qtd = NULL; |
1241 | qh = slots[slot].qh; | ||
1242 | slots[slot].qh = NULL; | ||
1243 | priv->active_ptds--; | ||
1244 | qh->slot = -1; | ||
1245 | |||
1246 | WARN_ON(qtd->status != QTD_XFER_STARTED); | ||
1247 | |||
1248 | switch (state) { | ||
1249 | case PTD_STATE_QTD_DONE: | ||
1250 | if ((usb_pipeint(qtd->urb->pipe)) && | ||
1251 | (qtd->urb->dev->speed != USB_SPEED_HIGH)) | ||
1252 | qtd->actual_length = | ||
1253 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); | ||
1254 | else | ||
1255 | qtd->actual_length = | ||
1256 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); | ||
1257 | |||
1258 | qtd->status = QTD_XFER_COMPLETE; | ||
1259 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || | ||
1260 | is_short_bulk(qtd)) | ||
1261 | qtd = NULL; | ||
1262 | else | ||
1263 | qtd = list_entry(qtd->qtd_list.next, | ||
1264 | typeof(*qtd), qtd_list); | ||
1265 | |||
1266 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | ||
1267 | qh->ping = FROM_DW3_PING(ptd.dw3); | ||
1268 | break; | ||
1378 | 1269 | ||
1379 | if (!usb_pipecontrol(urb->pipe)) | 1270 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
1380 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, | 1271 | qtd->status = QTD_PAYLOAD_ALLOC; |
1381 | 1); | 1272 | ptd.dw0 |= DW0_VALID_BIT; |
1382 | return qh; | 1273 | /* RL counter = ERR counter */ |
1383 | } | 1274 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); |
1275 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); | ||
1276 | ptd.dw3 &= ~TO_DW3_CERR(3); | ||
1277 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); | ||
1278 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | ||
1279 | qh->ping = FROM_DW3_PING(ptd.dw3); | ||
1280 | break; | ||
1384 | 1281 | ||
1385 | /* | 1282 | case PTD_STATE_URB_RETIRE: |
1386 | * For control/bulk/interrupt, return QH with these TDs appended. | 1283 | qtd->status = QTD_RETIRE; |
1387 | * Allocates and initializes the QH if necessary. | 1284 | qtd = NULL; |
1388 | * Returns null if it can't allocate a QH it needs to. | 1285 | qh->toggle = 0; |
1389 | * If the QH has TDs (urbs) already, that's great. | 1286 | qh->ping = 0; |
1390 | */ | 1287 | break; |
1391 | static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv, | ||
1392 | struct urb *urb, struct list_head *qtd_list, int epnum, | ||
1393 | void **ptr) | ||
1394 | { | ||
1395 | struct isp1760_qh *qh; | ||
1396 | struct isp1760_qtd *qtd; | ||
1397 | struct isp1760_qtd *prev_qtd; | ||
1398 | 1288 | ||
1399 | qh = (struct isp1760_qh *)*ptr; | 1289 | default: |
1400 | if (!qh) { | 1290 | WARN_ON(1); |
1401 | /* can't sleep here, we have priv->lock... */ | 1291 | continue; |
1402 | qh = qh_make(priv, urb, GFP_ATOMIC); | 1292 | } |
1403 | if (!qh) | ||
1404 | return qh; | ||
1405 | *ptr = qh; | ||
1406 | } | ||
1407 | 1293 | ||
1408 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, | 1294 | if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { |
1409 | qtd_list); | 1295 | if (slots == priv->int_slots) { |
1410 | if (!list_empty(&qh->qtd_list)) | 1296 | if (state == PTD_STATE_QTD_RELOAD) |
1411 | prev_qtd = list_entry(qh->qtd_list.prev, | 1297 | dev_err(hcd->self.controller, |
1412 | struct isp1760_qtd, qtd_list); | 1298 | "%s: PTD_STATE_QTD_RELOAD on " |
1413 | else | 1299 | "interrupt packet\n", __func__); |
1414 | prev_qtd = NULL; | 1300 | if (state != PTD_STATE_QTD_RELOAD) |
1301 | create_ptd_int(qh, qtd, &ptd); | ||
1302 | } else { | ||
1303 | if (state != PTD_STATE_QTD_RELOAD) | ||
1304 | create_ptd_atl(qh, qtd, &ptd); | ||
1305 | } | ||
1415 | 1306 | ||
1416 | list_splice(qtd_list, qh->qtd_list.prev); | 1307 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
1417 | if (prev_qtd) { | 1308 | qh, &ptd); |
1418 | BUG_ON(prev_qtd->hw_next); | 1309 | } |
1419 | prev_qtd->hw_next = qtd; | ||
1420 | } | 1310 | } |
1421 | 1311 | ||
1422 | urb->hcpriv = qh; | 1312 | if (modified) |
1423 | return qh; | 1313 | schedule_ptds(hcd); |
1424 | } | ||
1425 | |||
1426 | static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb, | ||
1427 | struct list_head *qtd_list) | ||
1428 | { | ||
1429 | struct list_head *entry, *temp; | ||
1430 | 1314 | ||
1431 | list_for_each_safe(entry, temp, qtd_list) { | 1315 | /* ISP1760 Errata 2 explains that interrupts may be missed (or not |
1432 | struct isp1760_qtd *qtd; | 1316 | happen?) if two USB devices are running simultaneously. Perhaps |
1317 | this happens when a PTD is finished during interrupt handling; | ||
1318 | enable SOF interrupts if PTDs are still scheduled when exiting this | ||
1319 | interrupt handler, just to be safe. */ | ||
1433 | 1320 | ||
1434 | qtd = list_entry(entry, struct isp1760_qtd, qtd_list); | 1321 | if (priv->active_ptds != last_active_ptds) { |
1435 | list_del(&qtd->qtd_list); | 1322 | if (priv->active_ptds > 0) |
1436 | isp1760_qtd_free(qtd); | 1323 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, |
1324 | INTERRUPT_ENABLE_SOT_MASK); | ||
1325 | else | ||
1326 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, | ||
1327 | INTERRUPT_ENABLE_MASK); | ||
1328 | last_active_ptds = priv->active_ptds; | ||
1437 | } | 1329 | } |
1438 | } | ||
1439 | |||
1440 | static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb, | ||
1441 | struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p) | ||
1442 | { | ||
1443 | struct isp1760_qtd *qtd; | ||
1444 | int epnum; | ||
1445 | unsigned long flags; | ||
1446 | struct isp1760_qh *qh = NULL; | ||
1447 | int rc; | ||
1448 | int qh_busy; | ||
1449 | |||
1450 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list); | ||
1451 | epnum = urb->ep->desc.bEndpointAddress; | ||
1452 | 1330 | ||
1453 | spin_lock_irqsave(&priv->lock, flags); | 1331 | irqret = IRQ_HANDLED; |
1454 | if (!HCD_HW_ACCESSIBLE(priv_to_hcd(priv))) { | 1332 | leave: |
1455 | rc = -ESHUTDOWN; | 1333 | spin_unlock(&priv->lock); |
1456 | goto done; | ||
1457 | } | ||
1458 | rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb); | ||
1459 | if (rc) | ||
1460 | goto done; | ||
1461 | 1334 | ||
1462 | qh = urb->ep->hcpriv; | 1335 | return irqret; |
1463 | if (qh) | 1336 | } |
1464 | qh_busy = !list_empty(&qh->qtd_list); | ||
1465 | else | ||
1466 | qh_busy = 0; | ||
1467 | 1337 | ||
1468 | qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv); | 1338 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
1469 | if (!qh) { | 1339 | { |
1470 | usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); | 1340 | qtd->data_buffer = databuffer; |
1471 | rc = -ENOMEM; | ||
1472 | goto done; | ||
1473 | } | ||
1474 | 1341 | ||
1475 | if (!qh_busy) | 1342 | if (len > MAX_PAYLOAD_SIZE) |
1476 | p(priv_to_hcd(priv), qh, qtd); | 1343 | len = MAX_PAYLOAD_SIZE; |
1344 | qtd->length = len; | ||
1477 | 1345 | ||
1478 | done: | 1346 | return qtd->length; |
1479 | spin_unlock_irqrestore(&priv->lock, flags); | ||
1480 | if (!qh) | ||
1481 | qtd_list_free(priv, urb, qtd_list); | ||
1482 | return rc; | ||
1483 | } | 1347 | } |
1484 | 1348 | ||
1485 | static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv, | 1349 | static void qtd_list_free(struct list_head *qtd_list) |
1486 | gfp_t flags) | ||
1487 | { | 1350 | { |
1488 | struct isp1760_qtd *qtd; | 1351 | struct isp1760_qtd *qtd, *qtd_next; |
1489 | 1352 | ||
1490 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | 1353 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
1491 | if (qtd) | 1354 | list_del(&qtd->qtd_list); |
1492 | INIT_LIST_HEAD(&qtd->qtd_list); | 1355 | qtd_free(qtd); |
1493 | 1356 | } | |
1494 | return qtd; | ||
1495 | } | 1357 | } |
1496 | 1358 | ||
1497 | /* | 1359 | /* |
1498 | * create a list of filled qtds for this URB; won't link into qh. | 1360 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
1361 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. | ||
1499 | */ | 1362 | */ |
1500 | static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, | 1363 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
1364 | static void packetize_urb(struct usb_hcd *hcd, | ||
1501 | struct urb *urb, struct list_head *head, gfp_t flags) | 1365 | struct urb *urb, struct list_head *head, gfp_t flags) |
1502 | { | 1366 | { |
1503 | struct isp1760_qtd *qtd, *qtd_prev; | 1367 | struct isp1760_qtd *qtd; |
1504 | void *buf; | 1368 | void *buf; |
1505 | int len, maxpacket; | 1369 | int len, maxpacketsize; |
1506 | int is_input; | 1370 | u8 packet_type; |
1507 | u32 token; | ||
1508 | 1371 | ||
1509 | /* | 1372 | /* |
1510 | * URBs map to sequences of QTDs: one logical transaction | 1373 | * URBs map to sequences of QTDs: one logical transaction |
1511 | */ | 1374 | */ |
1512 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1513 | if (!qtd) | ||
1514 | return NULL; | ||
1515 | 1375 | ||
1516 | list_add_tail(&qtd->qtd_list, head); | 1376 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
1517 | qtd->urb = urb; | 1377 | /* XXX This looks like usb storage / SCSI bug */ |
1518 | urb->status = -EINPROGRESS; | 1378 | dev_err(hcd->self.controller, |
1379 | "buf is null, dma is %08lx len is %d\n", | ||
1380 | (long unsigned)urb->transfer_dma, | ||
1381 | urb->transfer_buffer_length); | ||
1382 | WARN_ON(1); | ||
1383 | } | ||
1519 | 1384 | ||
1520 | token = 0; | 1385 | if (usb_pipein(urb->pipe)) |
1521 | /* for split transactions, SplitXState initialized to zero */ | 1386 | packet_type = IN_PID; |
1387 | else | ||
1388 | packet_type = OUT_PID; | ||
1522 | 1389 | ||
1523 | len = urb->transfer_buffer_length; | ||
1524 | is_input = usb_pipein(urb->pipe); | ||
1525 | if (usb_pipecontrol(urb->pipe)) { | 1390 | if (usb_pipecontrol(urb->pipe)) { |
1526 | /* SETUP pid */ | 1391 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
1527 | qtd_fill(qtd, urb->setup_packet, | ||
1528 | sizeof(struct usb_ctrlrequest), | ||
1529 | token | SETUP_PID); | ||
1530 | |||
1531 | /* ... and always at least one more pid */ | ||
1532 | token ^= DATA_TOGGLE; | ||
1533 | qtd_prev = qtd; | ||
1534 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1535 | if (!qtd) | 1392 | if (!qtd) |
1536 | goto cleanup; | 1393 | goto cleanup; |
1537 | qtd->urb = urb; | 1394 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
1538 | qtd_prev->hw_next = qtd; | ||
1539 | list_add_tail(&qtd->qtd_list, head); | 1395 | list_add_tail(&qtd->qtd_list, head); |
1540 | 1396 | ||
1541 | /* for zero length DATA stages, STATUS is always IN */ | 1397 | /* for zero length DATA stages, STATUS is always IN */ |
1542 | if (len == 0) | 1398 | if (urb->transfer_buffer_length == 0) |
1543 | token |= IN_PID; | 1399 | packet_type = IN_PID; |
1544 | } | 1400 | } |
1545 | 1401 | ||
1546 | /* | 1402 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, |
1547 | * data transfer stage: buffer setup | 1403 | usb_pipeout(urb->pipe))); |
1548 | */ | ||
1549 | buf = urb->transfer_buffer; | ||
1550 | |||
1551 | if (is_input) | ||
1552 | token |= IN_PID; | ||
1553 | else | ||
1554 | token |= OUT_PID; | ||
1555 | |||
1556 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); | ||
1557 | 1404 | ||
1558 | /* | 1405 | /* |
1559 | * buffer gets wrapped in one or more qtds; | 1406 | * buffer gets wrapped in one or more qtds; |
1560 | * last one may be "short" (including zero len) | 1407 | * last one may be "short" (including zero len) |
1561 | * and may serve as a control status ack | 1408 | * and may serve as a control status ack |
1562 | */ | 1409 | */ |
1410 | buf = urb->transfer_buffer; | ||
1411 | len = urb->transfer_buffer_length; | ||
1412 | |||
1563 | for (;;) { | 1413 | for (;;) { |
1564 | int this_qtd_len; | 1414 | int this_qtd_len; |
1565 | 1415 | ||
1566 | if (!buf && len) { | 1416 | qtd = qtd_alloc(flags, urb, packet_type); |
1567 | /* XXX This looks like usb storage / SCSI bug */ | 1417 | if (!qtd) |
1568 | printk(KERN_ERR "buf is null, dma is %08lx len is %d\n", | 1418 | goto cleanup; |
1569 | (long unsigned)urb->transfer_dma, len); | 1419 | this_qtd_len = qtd_fill(qtd, buf, len); |
1570 | WARN_ON(1); | 1420 | list_add_tail(&qtd->qtd_list, head); |
1571 | } | ||
1572 | 1421 | ||
1573 | this_qtd_len = qtd_fill(qtd, buf, len, token); | ||
1574 | len -= this_qtd_len; | 1422 | len -= this_qtd_len; |
1575 | buf += this_qtd_len; | 1423 | buf += this_qtd_len; |
1576 | 1424 | ||
1577 | /* qh makes control packets use qtd toggle; maybe switch it */ | ||
1578 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) | ||
1579 | token ^= DATA_TOGGLE; | ||
1580 | |||
1581 | if (len <= 0) | 1425 | if (len <= 0) |
1582 | break; | 1426 | break; |
1583 | |||
1584 | qtd_prev = qtd; | ||
1585 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1586 | if (!qtd) | ||
1587 | goto cleanup; | ||
1588 | qtd->urb = urb; | ||
1589 | qtd_prev->hw_next = qtd; | ||
1590 | list_add_tail(&qtd->qtd_list, head); | ||
1591 | } | 1427 | } |
1592 | 1428 | ||
1593 | /* | 1429 | /* |
@@ -1599,187 +1435,204 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, | |||
1599 | 1435 | ||
1600 | if (usb_pipecontrol(urb->pipe)) { | 1436 | if (usb_pipecontrol(urb->pipe)) { |
1601 | one_more = 1; | 1437 | one_more = 1; |
1602 | /* "in" <--> "out" */ | 1438 | if (packet_type == IN_PID) |
1603 | token ^= IN_PID; | 1439 | packet_type = OUT_PID; |
1604 | /* force DATA1 */ | 1440 | else |
1605 | token |= DATA_TOGGLE; | 1441 | packet_type = IN_PID; |
1606 | } else if (usb_pipebulk(urb->pipe) | 1442 | } else if (usb_pipebulk(urb->pipe) |
1607 | && (urb->transfer_flags & URB_ZERO_PACKET) | 1443 | && (urb->transfer_flags & URB_ZERO_PACKET) |
1608 | && !(urb->transfer_buffer_length % maxpacket)) { | 1444 | && !(urb->transfer_buffer_length % |
1445 | maxpacketsize)) { | ||
1609 | one_more = 1; | 1446 | one_more = 1; |
1610 | } | 1447 | } |
1611 | if (one_more) { | 1448 | if (one_more) { |
1612 | qtd_prev = qtd; | 1449 | qtd = qtd_alloc(flags, urb, packet_type); |
1613 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1614 | if (!qtd) | 1450 | if (!qtd) |
1615 | goto cleanup; | 1451 | goto cleanup; |
1616 | qtd->urb = urb; | ||
1617 | qtd_prev->hw_next = qtd; | ||
1618 | list_add_tail(&qtd->qtd_list, head); | ||
1619 | 1452 | ||
1620 | /* never any data in such packets */ | 1453 | /* never any data in such packets */ |
1621 | qtd_fill(qtd, NULL, 0, token); | 1454 | qtd_fill(qtd, NULL, 0); |
1455 | list_add_tail(&qtd->qtd_list, head); | ||
1622 | } | 1456 | } |
1623 | } | 1457 | } |
1624 | 1458 | ||
1625 | qtd->status = URB_COMPLETE_NOTIFY; | 1459 | return; |
1626 | return head; | ||
1627 | 1460 | ||
1628 | cleanup: | 1461 | cleanup: |
1629 | qtd_list_free(priv, urb, head); | 1462 | qtd_list_free(head); |
1630 | return NULL; | ||
1631 | } | 1463 | } |
1632 | 1464 | ||
1633 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | 1465 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
1634 | gfp_t mem_flags) | 1466 | gfp_t mem_flags) |
1635 | { | 1467 | { |
1636 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1468 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1637 | struct list_head qtd_list; | 1469 | struct list_head *ep_queue; |
1638 | packet_enqueue *pe; | 1470 | struct isp1760_qh *qh, *qhit; |
1639 | 1471 | unsigned long spinflags; | |
1640 | INIT_LIST_HEAD(&qtd_list); | 1472 | LIST_HEAD(new_qtds); |
1473 | int retval; | ||
1474 | int qh_in_queue; | ||
1641 | 1475 | ||
1642 | switch (usb_pipetype(urb->pipe)) { | 1476 | switch (usb_pipetype(urb->pipe)) { |
1643 | case PIPE_CONTROL: | 1477 | case PIPE_CONTROL: |
1478 | ep_queue = &priv->controlqhs; | ||
1479 | break; | ||
1644 | case PIPE_BULK: | 1480 | case PIPE_BULK: |
1645 | 1481 | ep_queue = &priv->bulkqhs; | |
1646 | if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) | ||
1647 | return -ENOMEM; | ||
1648 | pe = enqueue_an_ATL_packet; | ||
1649 | break; | 1482 | break; |
1650 | |||
1651 | case PIPE_INTERRUPT: | 1483 | case PIPE_INTERRUPT: |
1652 | if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) | 1484 | if (urb->interval < 0) |
1653 | return -ENOMEM; | 1485 | return -EINVAL; |
1654 | pe = enqueue_an_INT_packet; | 1486 | /* FIXME: Check bandwidth */ |
1487 | ep_queue = &priv->interruptqhs; | ||
1655 | break; | 1488 | break; |
1656 | |||
1657 | case PIPE_ISOCHRONOUS: | 1489 | case PIPE_ISOCHRONOUS: |
1658 | printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n"); | 1490 | dev_err(hcd->self.controller, "%s: isochronous USB packets " |
1491 | "not yet supported\n", | ||
1492 | __func__); | ||
1493 | return -EPIPE; | ||
1659 | default: | 1494 | default: |
1495 | dev_err(hcd->self.controller, "%s: unknown pipe type\n", | ||
1496 | __func__); | ||
1660 | return -EPIPE; | 1497 | return -EPIPE; |
1661 | } | 1498 | } |
1662 | 1499 | ||
1663 | return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe); | 1500 | if (usb_pipein(urb->pipe)) |
1501 | urb->actual_length = 0; | ||
1502 | |||
1503 | packetize_urb(hcd, urb, &new_qtds, mem_flags); | ||
1504 | if (list_empty(&new_qtds)) | ||
1505 | return -ENOMEM; | ||
1506 | urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */ | ||
1507 | |||
1508 | retval = 0; | ||
1509 | spin_lock_irqsave(&priv->lock, spinflags); | ||
1510 | |||
1511 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { | ||
1512 | retval = -ESHUTDOWN; | ||
1513 | goto out; | ||
1514 | } | ||
1515 | retval = usb_hcd_link_urb_to_ep(hcd, urb); | ||
1516 | if (retval) | ||
1517 | goto out; | ||
1518 | |||
1519 | qh = urb->ep->hcpriv; | ||
1520 | if (qh) { | ||
1521 | qh_in_queue = 0; | ||
1522 | list_for_each_entry(qhit, ep_queue, qh_list) { | ||
1523 | if (qhit == qh) { | ||
1524 | qh_in_queue = 1; | ||
1525 | break; | ||
1526 | } | ||
1527 | } | ||
1528 | if (!qh_in_queue) | ||
1529 | list_add_tail(&qh->qh_list, ep_queue); | ||
1530 | } else { | ||
1531 | qh = qh_alloc(GFP_ATOMIC); | ||
1532 | if (!qh) { | ||
1533 | retval = -ENOMEM; | ||
1534 | goto out; | ||
1535 | } | ||
1536 | list_add_tail(&qh->qh_list, ep_queue); | ||
1537 | urb->ep->hcpriv = qh; | ||
1538 | } | ||
1539 | |||
1540 | list_splice_tail(&new_qtds, &qh->qtd_list); | ||
1541 | schedule_ptds(hcd); | ||
1542 | |||
1543 | out: | ||
1544 | spin_unlock_irqrestore(&priv->lock, spinflags); | ||
1545 | return retval; | ||
1546 | } | ||
1547 | |||
1548 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, | ||
1549 | struct isp1760_qh *qh) | ||
1550 | { | ||
1551 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
1552 | int skip_map; | ||
1553 | |||
1554 | WARN_ON(qh->slot == -1); | ||
1555 | |||
1556 | /* We need to forcefully reclaim the slot since some transfers never | ||
1557 | return, e.g. interrupt transfers and NAKed bulk transfers. */ | ||
1558 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { | ||
1559 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | ||
1560 | skip_map |= (1 << qh->slot); | ||
1561 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | ||
1562 | priv->atl_slots[qh->slot].qh = NULL; | ||
1563 | priv->atl_slots[qh->slot].qtd = NULL; | ||
1564 | } else { | ||
1565 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | ||
1566 | skip_map |= (1 << qh->slot); | ||
1567 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); | ||
1568 | priv->int_slots[qh->slot].qh = NULL; | ||
1569 | priv->int_slots[qh->slot].qtd = NULL; | ||
1570 | } | ||
1571 | |||
1572 | qh->slot = -1; | ||
1573 | priv->active_ptds--; | ||
1664 | } | 1574 | } |
1665 | 1575 | ||
1666 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, | 1576 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, |
1667 | int status) | 1577 | int status) |
1668 | { | 1578 | { |
1669 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1579 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1670 | struct inter_packet_info *ints; | 1580 | unsigned long spinflags; |
1671 | u32 i; | 1581 | struct isp1760_qh *qh; |
1672 | u32 reg_base, or_reg, skip_reg; | 1582 | struct isp1760_qtd *qtd; |
1673 | unsigned long flags; | 1583 | int retval = 0; |
1674 | struct ptd ptd; | ||
1675 | packet_enqueue *pe; | ||
1676 | |||
1677 | switch (usb_pipetype(urb->pipe)) { | ||
1678 | case PIPE_ISOCHRONOUS: | ||
1679 | return -EPIPE; | ||
1680 | break; | ||
1681 | 1584 | ||
1682 | case PIPE_INTERRUPT: | 1585 | spin_lock_irqsave(&priv->lock, spinflags); |
1683 | ints = priv->int_ints; | ||
1684 | reg_base = INT_REGS_OFFSET; | ||
1685 | or_reg = HC_INT_IRQ_MASK_OR_REG; | ||
1686 | skip_reg = HC_INT_PTD_SKIPMAP_REG; | ||
1687 | pe = enqueue_an_INT_packet; | ||
1688 | break; | ||
1689 | 1586 | ||
1690 | default: | 1587 | qh = urb->ep->hcpriv; |
1691 | ints = priv->atl_ints; | 1588 | if (!qh) { |
1692 | reg_base = ATL_REGS_OFFSET; | 1589 | retval = -EINVAL; |
1693 | or_reg = HC_ATL_IRQ_MASK_OR_REG; | 1590 | goto out; |
1694 | skip_reg = HC_ATL_PTD_SKIPMAP_REG; | ||
1695 | pe = enqueue_an_ATL_packet; | ||
1696 | break; | ||
1697 | } | 1591 | } |
1698 | 1592 | ||
1699 | memset(&ptd, 0, sizeof(ptd)); | 1593 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
1700 | spin_lock_irqsave(&priv->lock, flags); | 1594 | if (qtd->urb == urb) { |
1701 | 1595 | if (qtd->status == QTD_XFER_STARTED) | |
1702 | for (i = 0; i < 32; i++) { | 1596 | kill_transfer(hcd, urb, qh); |
1703 | if (ints->urb == urb) { | 1597 | qtd->status = QTD_RETIRE; |
1704 | u32 skip_map; | ||
1705 | u32 or_map; | ||
1706 | struct isp1760_qtd *qtd; | ||
1707 | struct isp1760_qh *qh = ints->qh; | ||
1708 | |||
1709 | skip_map = isp1760_readl(hcd->regs + skip_reg); | ||
1710 | skip_map |= 1 << i; | ||
1711 | isp1760_writel(skip_map, hcd->regs + skip_reg); | ||
1712 | |||
1713 | or_map = isp1760_readl(hcd->regs + or_reg); | ||
1714 | or_map &= ~(1 << i); | ||
1715 | isp1760_writel(or_map, hcd->regs + or_reg); | ||
1716 | |||
1717 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base | ||
1718 | + i * sizeof(ptd), sizeof(ptd)); | ||
1719 | qtd = ints->qtd; | ||
1720 | qtd = clean_up_qtdlist(qtd); | ||
1721 | |||
1722 | free_mem(priv, ints->payload); | ||
1723 | |||
1724 | ints->urb = NULL; | ||
1725 | ints->qh = NULL; | ||
1726 | ints->qtd = NULL; | ||
1727 | ints->data_buffer = NULL; | ||
1728 | ints->payload = 0; | ||
1729 | |||
1730 | isp1760_urb_done(priv, urb, status); | ||
1731 | if (qtd) | ||
1732 | pe(hcd, qh, qtd); | ||
1733 | break; | ||
1734 | |||
1735 | } else if (ints->qtd) { | ||
1736 | struct isp1760_qtd *qtd, *prev_qtd = ints->qtd; | ||
1737 | |||
1738 | for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) { | ||
1739 | if (qtd->urb == urb) { | ||
1740 | prev_qtd->hw_next = clean_up_qtdlist(qtd); | ||
1741 | isp1760_urb_done(priv, urb, status); | ||
1742 | break; | ||
1743 | } | ||
1744 | prev_qtd = qtd; | ||
1745 | } | ||
1746 | /* we found the urb before the end of the list */ | ||
1747 | if (qtd) | ||
1748 | break; | ||
1749 | } | 1598 | } |
1750 | ints++; | ||
1751 | } | ||
1752 | 1599 | ||
1753 | spin_unlock_irqrestore(&priv->lock, flags); | 1600 | urb->status = status; |
1754 | return 0; | 1601 | schedule_ptds(hcd); |
1602 | |||
1603 | out: | ||
1604 | spin_unlock_irqrestore(&priv->lock, spinflags); | ||
1605 | return retval; | ||
1755 | } | 1606 | } |
1756 | 1607 | ||
1757 | static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd) | 1608 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
1609 | struct usb_host_endpoint *ep) | ||
1758 | { | 1610 | { |
1759 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | 1611 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1760 | u32 imask; | 1612 | unsigned long spinflags; |
1761 | irqreturn_t irqret = IRQ_NONE; | 1613 | struct isp1760_qh *qh; |
1614 | struct isp1760_qtd *qtd; | ||
1762 | 1615 | ||
1763 | spin_lock(&priv->lock); | 1616 | spin_lock_irqsave(&priv->lock, spinflags); |
1764 | 1617 | ||
1765 | if (!(usb_hcd->state & HC_STATE_RUNNING)) | 1618 | qh = ep->hcpriv; |
1766 | goto leave; | 1619 | if (!qh) |
1620 | goto out; | ||
1767 | 1621 | ||
1768 | imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG); | 1622 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
1769 | if (unlikely(!imask)) | 1623 | if (qtd->status == QTD_XFER_STARTED) |
1770 | goto leave; | 1624 | kill_transfer(hcd, qtd->urb, qh); |
1625 | qtd->status = QTD_RETIRE; | ||
1626 | qtd->urb->status = -ECONNRESET; | ||
1627 | } | ||
1771 | 1628 | ||
1772 | isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG); | 1629 | ep->hcpriv = NULL; |
1773 | if (imask & HC_ATL_INT) | 1630 | /* Cannot free qh here since it will be parsed by schedule_ptds() */ |
1774 | do_atl_int(usb_hcd); | ||
1775 | 1631 | ||
1776 | if (imask & HC_INTL_INT) | 1632 | schedule_ptds(hcd); |
1777 | do_intl_int(usb_hcd); | ||
1778 | 1633 | ||
1779 | irqret = IRQ_HANDLED; | 1634 | out: |
1780 | leave: | 1635 | spin_unlock_irqrestore(&priv->lock, spinflags); |
1781 | spin_unlock(&priv->lock); | ||
1782 | return irqret; | ||
1783 | } | 1636 | } |
1784 | 1637 | ||
1785 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | 1638 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) |
@@ -1799,12 +1652,12 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | |||
1799 | mask = PORT_CSC; | 1652 | mask = PORT_CSC; |
1800 | 1653 | ||
1801 | spin_lock_irqsave(&priv->lock, flags); | 1654 | spin_lock_irqsave(&priv->lock, flags); |
1802 | temp = isp1760_readl(hcd->regs + HC_PORTSC1); | 1655 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1803 | 1656 | ||
1804 | if (temp & PORT_OWNER) { | 1657 | if (temp & PORT_OWNER) { |
1805 | if (temp & PORT_CSC) { | 1658 | if (temp & PORT_CSC) { |
1806 | temp &= ~PORT_CSC; | 1659 | temp &= ~PORT_CSC; |
1807 | isp1760_writel(temp, hcd->regs + HC_PORTSC1); | 1660 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
1808 | goto done; | 1661 | goto done; |
1809 | } | 1662 | } |
1810 | } | 1663 | } |
@@ -1844,9 +1697,9 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |||
1844 | temp = 1 + (ports / 8); | 1697 | temp = 1 + (ports / 8); |
1845 | desc->bDescLength = 7 + 2 * temp; | 1698 | desc->bDescLength = 7 + 2 * temp; |
1846 | 1699 | ||
1847 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 1700 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
1848 | memset(&desc->bitmap[0], 0, temp); | 1701 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
1849 | memset(&desc->bitmap[temp], 0xff, temp); | 1702 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
1850 | 1703 | ||
1851 | /* per-port overcurrent reporting */ | 1704 | /* per-port overcurrent reporting */ |
1852 | temp = 0x0008; | 1705 | temp = 0x0008; |
@@ -1861,8 +1714,8 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |||
1861 | 1714 | ||
1862 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | 1715 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
1863 | 1716 | ||
1864 | static int check_reset_complete(struct isp1760_hcd *priv, int index, | 1717 | static int check_reset_complete(struct usb_hcd *hcd, int index, |
1865 | u32 __iomem *status_reg, int port_status) | 1718 | int port_status) |
1866 | { | 1719 | { |
1867 | if (!(port_status & PORT_CONNECT)) | 1720 | if (!(port_status & PORT_CONNECT)) |
1868 | return port_status; | 1721 | return port_status; |
@@ -1870,15 +1723,17 @@ static int check_reset_complete(struct isp1760_hcd *priv, int index, | |||
1870 | /* if reset finished and it's still not enabled -- handoff */ | 1723 | /* if reset finished and it's still not enabled -- handoff */ |
1871 | if (!(port_status & PORT_PE)) { | 1724 | if (!(port_status & PORT_PE)) { |
1872 | 1725 | ||
1873 | printk(KERN_ERR "port %d full speed --> companion\n", | 1726 | dev_info(hcd->self.controller, |
1874 | index + 1); | 1727 | "port %d full speed --> companion\n", |
1728 | index + 1); | ||
1875 | 1729 | ||
1876 | port_status |= PORT_OWNER; | 1730 | port_status |= PORT_OWNER; |
1877 | port_status &= ~PORT_RWC_BITS; | 1731 | port_status &= ~PORT_RWC_BITS; |
1878 | isp1760_writel(port_status, status_reg); | 1732 | reg_write32(hcd->regs, HC_PORTSC1, port_status); |
1879 | 1733 | ||
1880 | } else | 1734 | } else |
1881 | printk(KERN_ERR "port %d high speed\n", index + 1); | 1735 | dev_info(hcd->self.controller, "port %d high speed\n", |
1736 | index + 1); | ||
1882 | 1737 | ||
1883 | return port_status; | 1738 | return port_status; |
1884 | } | 1739 | } |
@@ -1888,7 +1743,6 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1888 | { | 1743 | { |
1889 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1744 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1890 | int ports = HCS_N_PORTS(priv->hcs_params); | 1745 | int ports = HCS_N_PORTS(priv->hcs_params); |
1891 | u32 __iomem *status_reg = hcd->regs + HC_PORTSC1; | ||
1892 | u32 temp, status; | 1746 | u32 temp, status; |
1893 | unsigned long flags; | 1747 | unsigned long flags; |
1894 | int retval = 0; | 1748 | int retval = 0; |
@@ -1917,7 +1771,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1917 | if (!wIndex || wIndex > ports) | 1771 | if (!wIndex || wIndex > ports) |
1918 | goto error; | 1772 | goto error; |
1919 | wIndex--; | 1773 | wIndex--; |
1920 | temp = isp1760_readl(status_reg); | 1774 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1921 | 1775 | ||
1922 | /* | 1776 | /* |
1923 | * Even if OWNER is set, so the port is owned by the | 1777 | * Even if OWNER is set, so the port is owned by the |
@@ -1928,7 +1782,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1928 | 1782 | ||
1929 | switch (wValue) { | 1783 | switch (wValue) { |
1930 | case USB_PORT_FEAT_ENABLE: | 1784 | case USB_PORT_FEAT_ENABLE: |
1931 | isp1760_writel(temp & ~PORT_PE, status_reg); | 1785 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); |
1932 | break; | 1786 | break; |
1933 | case USB_PORT_FEAT_C_ENABLE: | 1787 | case USB_PORT_FEAT_C_ENABLE: |
1934 | /* XXX error? */ | 1788 | /* XXX error? */ |
@@ -1942,8 +1796,8 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1942 | goto error; | 1796 | goto error; |
1943 | /* resume signaling for 20 msec */ | 1797 | /* resume signaling for 20 msec */ |
1944 | temp &= ~(PORT_RWC_BITS); | 1798 | temp &= ~(PORT_RWC_BITS); |
1945 | isp1760_writel(temp | PORT_RESUME, | 1799 | reg_write32(hcd->regs, HC_PORTSC1, |
1946 | status_reg); | 1800 | temp | PORT_RESUME); |
1947 | priv->reset_done = jiffies + | 1801 | priv->reset_done = jiffies + |
1948 | msecs_to_jiffies(20); | 1802 | msecs_to_jiffies(20); |
1949 | } | 1803 | } |
@@ -1953,11 +1807,11 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1953 | break; | 1807 | break; |
1954 | case USB_PORT_FEAT_POWER: | 1808 | case USB_PORT_FEAT_POWER: |
1955 | if (HCS_PPC(priv->hcs_params)) | 1809 | if (HCS_PPC(priv->hcs_params)) |
1956 | isp1760_writel(temp & ~PORT_POWER, status_reg); | 1810 | reg_write32(hcd->regs, HC_PORTSC1, |
1811 | temp & ~PORT_POWER); | ||
1957 | break; | 1812 | break; |
1958 | case USB_PORT_FEAT_C_CONNECTION: | 1813 | case USB_PORT_FEAT_C_CONNECTION: |
1959 | isp1760_writel(temp | PORT_CSC, | 1814 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); |
1960 | status_reg); | ||
1961 | break; | 1815 | break; |
1962 | case USB_PORT_FEAT_C_OVER_CURRENT: | 1816 | case USB_PORT_FEAT_C_OVER_CURRENT: |
1963 | /* XXX error ?*/ | 1817 | /* XXX error ?*/ |
@@ -1968,7 +1822,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1968 | default: | 1822 | default: |
1969 | goto error; | 1823 | goto error; |
1970 | } | 1824 | } |
1971 | isp1760_readl(hcd->regs + HC_USBCMD); | 1825 | reg_read32(hcd->regs, HC_USBCMD); |
1972 | break; | 1826 | break; |
1973 | case GetHubDescriptor: | 1827 | case GetHubDescriptor: |
1974 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | 1828 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) |
@@ -1983,7 +1837,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1983 | goto error; | 1837 | goto error; |
1984 | wIndex--; | 1838 | wIndex--; |
1985 | status = 0; | 1839 | status = 0; |
1986 | temp = isp1760_readl(status_reg); | 1840 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1987 | 1841 | ||
1988 | /* wPortChange bits */ | 1842 | /* wPortChange bits */ |
1989 | if (temp & PORT_CSC) | 1843 | if (temp & PORT_CSC) |
@@ -1992,7 +1846,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1992 | 1846 | ||
1993 | /* whoever resumes must GetPortStatus to complete it!! */ | 1847 | /* whoever resumes must GetPortStatus to complete it!! */ |
1994 | if (temp & PORT_RESUME) { | 1848 | if (temp & PORT_RESUME) { |
1995 | printk(KERN_ERR "Port resume should be skipped.\n"); | 1849 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); |
1996 | 1850 | ||
1997 | /* Remote Wakeup received? */ | 1851 | /* Remote Wakeup received? */ |
1998 | if (!priv->reset_done) { | 1852 | if (!priv->reset_done) { |
@@ -2000,8 +1854,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2000 | priv->reset_done = jiffies | 1854 | priv->reset_done = jiffies |
2001 | + msecs_to_jiffies(20); | 1855 | + msecs_to_jiffies(20); |
2002 | /* check the port again */ | 1856 | /* check the port again */ |
2003 | mod_timer(&priv_to_hcd(priv)->rh_timer, | 1857 | mod_timer(&hcd->rh_timer, priv->reset_done); |
2004 | priv->reset_done); | ||
2005 | } | 1858 | } |
2006 | 1859 | ||
2007 | /* resume completed? */ | 1860 | /* resume completed? */ |
@@ -2011,14 +1864,13 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2011 | priv->reset_done = 0; | 1864 | priv->reset_done = 0; |
2012 | 1865 | ||
2013 | /* stop resume signaling */ | 1866 | /* stop resume signaling */ |
2014 | temp = isp1760_readl(status_reg); | 1867 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
2015 | isp1760_writel( | 1868 | reg_write32(hcd->regs, HC_PORTSC1, |
2016 | temp & ~(PORT_RWC_BITS | PORT_RESUME), | 1869 | temp & ~(PORT_RWC_BITS | PORT_RESUME)); |
2017 | status_reg); | 1870 | retval = handshake(hcd, HC_PORTSC1, |
2018 | retval = handshake(priv, status_reg, | ||
2019 | PORT_RESUME, 0, 2000 /* 2msec */); | 1871 | PORT_RESUME, 0, 2000 /* 2msec */); |
2020 | if (retval != 0) { | 1872 | if (retval != 0) { |
2021 | isp1760_err(priv, | 1873 | dev_err(hcd->self.controller, |
2022 | "port %d resume error %d\n", | 1874 | "port %d resume error %d\n", |
2023 | wIndex + 1, retval); | 1875 | wIndex + 1, retval); |
2024 | goto error; | 1876 | goto error; |
@@ -2035,22 +1887,21 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2035 | priv->reset_done = 0; | 1887 | priv->reset_done = 0; |
2036 | 1888 | ||
2037 | /* force reset to complete */ | 1889 | /* force reset to complete */ |
2038 | isp1760_writel(temp & ~PORT_RESET, | 1890 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); |
2039 | status_reg); | ||
2040 | /* REVISIT: some hardware needs 550+ usec to clear | 1891 | /* REVISIT: some hardware needs 550+ usec to clear |
2041 | * this bit; seems too long to spin routinely... | 1892 | * this bit; seems too long to spin routinely... |
2042 | */ | 1893 | */ |
2043 | retval = handshake(priv, status_reg, | 1894 | retval = handshake(hcd, HC_PORTSC1, |
2044 | PORT_RESET, 0, 750); | 1895 | PORT_RESET, 0, 750); |
2045 | if (retval != 0) { | 1896 | if (retval != 0) { |
2046 | isp1760_err(priv, "port %d reset error %d\n", | 1897 | dev_err(hcd->self.controller, "port %d reset error %d\n", |
2047 | wIndex + 1, retval); | 1898 | wIndex + 1, retval); |
2048 | goto error; | 1899 | goto error; |
2049 | } | 1900 | } |
2050 | 1901 | ||
2051 | /* see what we found out */ | 1902 | /* see what we found out */ |
2052 | temp = check_reset_complete(priv, wIndex, status_reg, | 1903 | temp = check_reset_complete(hcd, wIndex, |
2053 | isp1760_readl(status_reg)); | 1904 | reg_read32(hcd->regs, HC_PORTSC1)); |
2054 | } | 1905 | } |
2055 | /* | 1906 | /* |
2056 | * Even if OWNER is set, there's no harm letting khubd | 1907 | * Even if OWNER is set, there's no harm letting khubd |
@@ -2059,12 +1910,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2059 | */ | 1910 | */ |
2060 | 1911 | ||
2061 | if (temp & PORT_OWNER) | 1912 | if (temp & PORT_OWNER) |
2062 | printk(KERN_ERR "Warning: PORT_OWNER is set\n"); | 1913 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); |
2063 | 1914 | ||
2064 | if (temp & PORT_CONNECT) { | 1915 | if (temp & PORT_CONNECT) { |
2065 | status |= USB_PORT_STAT_CONNECTION; | 1916 | status |= USB_PORT_STAT_CONNECTION; |
2066 | /* status may be from integrated TT */ | 1917 | /* status may be from integrated TT */ |
2067 | status |= ehci_port_speed(priv, temp); | 1918 | status |= USB_PORT_STAT_HIGH_SPEED; |
2068 | } | 1919 | } |
2069 | if (temp & PORT_PE) | 1920 | if (temp & PORT_PE) |
2070 | status |= USB_PORT_STAT_ENABLE; | 1921 | status |= USB_PORT_STAT_ENABLE; |
@@ -2093,14 +1944,14 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2093 | if (!wIndex || wIndex > ports) | 1944 | if (!wIndex || wIndex > ports) |
2094 | goto error; | 1945 | goto error; |
2095 | wIndex--; | 1946 | wIndex--; |
2096 | temp = isp1760_readl(status_reg); | 1947 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
2097 | if (temp & PORT_OWNER) | 1948 | if (temp & PORT_OWNER) |
2098 | break; | 1949 | break; |
2099 | 1950 | ||
2100 | /* temp &= ~PORT_RWC_BITS; */ | 1951 | /* temp &= ~PORT_RWC_BITS; */ |
2101 | switch (wValue) { | 1952 | switch (wValue) { |
2102 | case USB_PORT_FEAT_ENABLE: | 1953 | case USB_PORT_FEAT_ENABLE: |
2103 | isp1760_writel(temp | PORT_PE, status_reg); | 1954 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); |
2104 | break; | 1955 | break; |
2105 | 1956 | ||
2106 | case USB_PORT_FEAT_SUSPEND: | 1957 | case USB_PORT_FEAT_SUSPEND: |
@@ -2108,12 +1959,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2108 | || (temp & PORT_RESET) != 0) | 1959 | || (temp & PORT_RESET) != 0) |
2109 | goto error; | 1960 | goto error; |
2110 | 1961 | ||
2111 | isp1760_writel(temp | PORT_SUSPEND, status_reg); | 1962 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); |
2112 | break; | 1963 | break; |
2113 | case USB_PORT_FEAT_POWER: | 1964 | case USB_PORT_FEAT_POWER: |
2114 | if (HCS_PPC(priv->hcs_params)) | 1965 | if (HCS_PPC(priv->hcs_params)) |
2115 | isp1760_writel(temp | PORT_POWER, | 1966 | reg_write32(hcd->regs, HC_PORTSC1, |
2116 | status_reg); | 1967 | temp | PORT_POWER); |
2117 | break; | 1968 | break; |
2118 | case USB_PORT_FEAT_RESET: | 1969 | case USB_PORT_FEAT_RESET: |
2119 | if (temp & PORT_RESUME) | 1970 | if (temp & PORT_RESUME) |
@@ -2136,12 +1987,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2136 | priv->reset_done = jiffies + | 1987 | priv->reset_done = jiffies + |
2137 | msecs_to_jiffies(50); | 1988 | msecs_to_jiffies(50); |
2138 | } | 1989 | } |
2139 | isp1760_writel(temp, status_reg); | 1990 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
2140 | break; | 1991 | break; |
2141 | default: | 1992 | default: |
2142 | goto error; | 1993 | goto error; |
2143 | } | 1994 | } |
2144 | isp1760_readl(hcd->regs + HC_USBCMD); | 1995 | reg_read32(hcd->regs, HC_USBCMD); |
2145 | break; | 1996 | break; |
2146 | 1997 | ||
2147 | default: | 1998 | default: |
@@ -2153,57 +2004,12 @@ error: | |||
2153 | return retval; | 2004 | return retval; |
2154 | } | 2005 | } |
2155 | 2006 | ||
2156 | static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd, | ||
2157 | struct usb_host_endpoint *ep) | ||
2158 | { | ||
2159 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | ||
2160 | struct isp1760_qh *qh; | ||
2161 | struct isp1760_qtd *qtd; | ||
2162 | unsigned long flags; | ||
2163 | |||
2164 | spin_lock_irqsave(&priv->lock, flags); | ||
2165 | qh = ep->hcpriv; | ||
2166 | if (!qh) | ||
2167 | goto out; | ||
2168 | |||
2169 | ep->hcpriv = NULL; | ||
2170 | do { | ||
2171 | /* more than entry might get removed */ | ||
2172 | if (list_empty(&qh->qtd_list)) | ||
2173 | break; | ||
2174 | |||
2175 | qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd, | ||
2176 | qtd_list); | ||
2177 | |||
2178 | if (qtd->status & URB_ENQUEUED) { | ||
2179 | |||
2180 | spin_unlock_irqrestore(&priv->lock, flags); | ||
2181 | isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET); | ||
2182 | spin_lock_irqsave(&priv->lock, flags); | ||
2183 | } else { | ||
2184 | struct urb *urb; | ||
2185 | |||
2186 | urb = qtd->urb; | ||
2187 | clean_up_qtdlist(qtd); | ||
2188 | isp1760_urb_done(priv, urb, -ECONNRESET); | ||
2189 | } | ||
2190 | } while (1); | ||
2191 | |||
2192 | qh_destroy(qh); | ||
2193 | /* remove requests and leak them. | ||
2194 | * ATL are pretty fast done, INT could take a while... | ||
2195 | * The latter shoule be removed | ||
2196 | */ | ||
2197 | out: | ||
2198 | spin_unlock_irqrestore(&priv->lock, flags); | ||
2199 | } | ||
2200 | |||
2201 | static int isp1760_get_frame(struct usb_hcd *hcd) | 2007 | static int isp1760_get_frame(struct usb_hcd *hcd) |
2202 | { | 2008 | { |
2203 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 2009 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
2204 | u32 fr; | 2010 | u32 fr; |
2205 | 2011 | ||
2206 | fr = isp1760_readl(hcd->regs + HC_FRINDEX); | 2012 | fr = reg_read32(hcd->regs, HC_FRINDEX); |
2207 | return (fr >> 3) % priv->periodic_size; | 2013 | return (fr >> 3) % priv->periodic_size; |
2208 | } | 2014 | } |
2209 | 2015 | ||
@@ -2217,13 +2023,13 @@ static void isp1760_stop(struct usb_hcd *hcd) | |||
2217 | mdelay(20); | 2023 | mdelay(20); |
2218 | 2024 | ||
2219 | spin_lock_irq(&priv->lock); | 2025 | spin_lock_irq(&priv->lock); |
2220 | ehci_reset(priv); | 2026 | ehci_reset(hcd); |
2221 | /* Disable IRQ */ | 2027 | /* Disable IRQ */ |
2222 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | 2028 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2223 | isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | 2029 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); |
2224 | spin_unlock_irq(&priv->lock); | 2030 | spin_unlock_irq(&priv->lock); |
2225 | 2031 | ||
2226 | isp1760_writel(0, hcd->regs + HC_CONFIGFLAG); | 2032 | reg_write32(hcd->regs, HC_CONFIGFLAG, 0); |
2227 | } | 2033 | } |
2228 | 2034 | ||
2229 | static void isp1760_shutdown(struct usb_hcd *hcd) | 2035 | static void isp1760_shutdown(struct usb_hcd *hcd) |
@@ -2231,12 +2037,12 @@ static void isp1760_shutdown(struct usb_hcd *hcd) | |||
2231 | u32 command, temp; | 2037 | u32 command, temp; |
2232 | 2038 | ||
2233 | isp1760_stop(hcd); | 2039 | isp1760_stop(hcd); |
2234 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | 2040 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2235 | isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | 2041 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); |
2236 | 2042 | ||
2237 | command = isp1760_readl(hcd->regs + HC_USBCMD); | 2043 | command = reg_read32(hcd->regs, HC_USBCMD); |
2238 | command &= ~CMD_RUN; | 2044 | command &= ~CMD_RUN; |
2239 | isp1760_writel(command, hcd->regs + HC_USBCMD); | 2045 | reg_write32(hcd->regs, HC_USBCMD, command); |
2240 | } | 2046 | } |
2241 | 2047 | ||
2242 | static const struct hc_driver isp1760_hc_driver = { | 2048 | static const struct hc_driver isp1760_hc_driver = { |
@@ -2259,6 +2065,13 @@ static const struct hc_driver isp1760_hc_driver = { | |||
2259 | 2065 | ||
2260 | int __init init_kmem_once(void) | 2066 | int __init init_kmem_once(void) |
2261 | { | 2067 | { |
2068 | urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem", | ||
2069 | sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | | ||
2070 | SLAB_MEM_SPREAD, NULL); | ||
2071 | |||
2072 | if (!urb_listitem_cachep) | ||
2073 | return -ENOMEM; | ||
2074 | |||
2262 | qtd_cachep = kmem_cache_create("isp1760_qtd", | 2075 | qtd_cachep = kmem_cache_create("isp1760_qtd", |
2263 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | 2076 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | |
2264 | SLAB_MEM_SPREAD, NULL); | 2077 | SLAB_MEM_SPREAD, NULL); |
@@ -2281,6 +2094,7 @@ void deinit_kmem_cache(void) | |||
2281 | { | 2094 | { |
2282 | kmem_cache_destroy(qtd_cachep); | 2095 | kmem_cache_destroy(qtd_cachep); |
2283 | kmem_cache_destroy(qh_cachep); | 2096 | kmem_cache_destroy(qh_cachep); |
2097 | kmem_cache_destroy(urb_listitem_cachep); | ||
2284 | } | 2098 | } |
2285 | 2099 | ||
2286 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, | 2100 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, |
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h index 6931ef5c9650..014a7dfadf91 100644 --- a/drivers/usb/host/isp1760-hcd.h +++ b/drivers/usb/host/isp1760-hcd.h | |||
@@ -49,10 +49,9 @@ void deinit_kmem_cache(void); | |||
49 | #define SW_RESET_RESET_ALL (1 << 0) | 49 | #define SW_RESET_RESET_ALL (1 << 0) |
50 | 50 | ||
51 | #define HC_BUFFER_STATUS_REG 0x334 | 51 | #define HC_BUFFER_STATUS_REG 0x334 |
52 | #define ATL_BUFFER 0x1 | 52 | #define ISO_BUF_FILL (1 << 2) |
53 | #define INT_BUFFER 0x2 | 53 | #define INT_BUF_FILL (1 << 1) |
54 | #define ISO_BUFFER 0x4 | 54 | #define ATL_BUF_FILL (1 << 0) |
55 | #define BUFFER_MAP 0x7 | ||
56 | 55 | ||
57 | #define HC_MEMORY_REG 0x33c | 56 | #define HC_MEMORY_REG 0x33c |
58 | #define ISP_BANK(x) ((x) << 16) | 57 | #define ISP_BANK(x) ((x) << 16) |
@@ -68,13 +67,13 @@ void deinit_kmem_cache(void); | |||
68 | #define HC_INTERRUPT_REG 0x310 | 67 | #define HC_INTERRUPT_REG 0x310 |
69 | 68 | ||
70 | #define HC_INTERRUPT_ENABLE 0x314 | 69 | #define HC_INTERRUPT_ENABLE 0x314 |
71 | #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT) | ||
72 | |||
73 | #define HC_ISO_INT (1 << 9) | 70 | #define HC_ISO_INT (1 << 9) |
74 | #define HC_ATL_INT (1 << 8) | 71 | #define HC_ATL_INT (1 << 8) |
75 | #define HC_INTL_INT (1 << 7) | 72 | #define HC_INTL_INT (1 << 7) |
76 | #define HC_EOT_INT (1 << 3) | 73 | #define HC_EOT_INT (1 << 3) |
77 | #define HC_SOT_INT (1 << 1) | 74 | #define HC_SOT_INT (1 << 1) |
75 | #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) | ||
76 | #define INTERRUPT_ENABLE_SOT_MASK (HC_SOT_INT) | ||
78 | 77 | ||
79 | #define HC_ISO_IRQ_MASK_OR_REG 0x318 | 78 | #define HC_ISO_IRQ_MASK_OR_REG 0x318 |
80 | #define HC_INT_IRQ_MASK_OR_REG 0x31C | 79 | #define HC_INT_IRQ_MASK_OR_REG 0x31C |
@@ -83,37 +82,29 @@ void deinit_kmem_cache(void); | |||
83 | #define HC_INT_IRQ_MASK_AND_REG 0x328 | 82 | #define HC_INT_IRQ_MASK_AND_REG 0x328 |
84 | #define HC_ATL_IRQ_MASK_AND_REG 0x32C | 83 | #define HC_ATL_IRQ_MASK_AND_REG 0x32C |
85 | 84 | ||
86 | /* Register sets */ | ||
87 | #define HC_BEGIN_OF_ATL 0x0c00 | ||
88 | #define HC_BEGIN_OF_INT 0x0800 | ||
89 | #define HC_BEGIN_OF_ISO 0x0400 | ||
90 | #define HC_BEGIN_OF_PAYLOAD 0x1000 | ||
91 | |||
92 | /* urb state*/ | 85 | /* urb state*/ |
93 | #define DELETE_URB (0x0008) | 86 | #define DELETE_URB (0x0008) |
94 | #define NO_TRANSFER_ACTIVE (0xffffffff) | 87 | #define NO_TRANSFER_ACTIVE (0xffffffff) |
95 | 88 | ||
96 | #define ATL_REGS_OFFSET (0xc00) | 89 | /* Philips Proprietary Transfer Descriptor (PTD) */ |
97 | #define INT_REGS_OFFSET (0x800) | 90 | typedef __u32 __bitwise __dw; |
98 | |||
99 | /* Philips Transfer Descriptor (PTD) */ | ||
100 | struct ptd { | 91 | struct ptd { |
101 | __le32 dw0; | 92 | __dw dw0; |
102 | __le32 dw1; | 93 | __dw dw1; |
103 | __le32 dw2; | 94 | __dw dw2; |
104 | __le32 dw3; | 95 | __dw dw3; |
105 | __le32 dw4; | 96 | __dw dw4; |
106 | __le32 dw5; | 97 | __dw dw5; |
107 | __le32 dw6; | 98 | __dw dw6; |
108 | __le32 dw7; | 99 | __dw dw7; |
109 | }; | 100 | }; |
101 | #define PTD_OFFSET 0x0400 | ||
102 | #define ISO_PTD_OFFSET 0x0400 | ||
103 | #define INT_PTD_OFFSET 0x0800 | ||
104 | #define ATL_PTD_OFFSET 0x0c00 | ||
105 | #define PAYLOAD_OFFSET 0x1000 | ||
110 | 106 | ||
111 | struct inter_packet_info { | 107 | struct slotinfo { |
112 | void *data_buffer; | ||
113 | u32 payload; | ||
114 | #define PTD_FIRE_NEXT (1 << 0) | ||
115 | #define PTD_URB_FINISHED (1 << 1) | ||
116 | struct urb *urb; | ||
117 | struct isp1760_qh *qh; | 108 | struct isp1760_qh *qh; |
118 | struct isp1760_qtd *qtd; | 109 | struct isp1760_qtd *qtd; |
119 | }; | 110 | }; |
@@ -122,15 +113,6 @@ struct inter_packet_info { | |||
122 | typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, | 113 | typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, |
123 | struct isp1760_qtd *qtd); | 114 | struct isp1760_qtd *qtd); |
124 | 115 | ||
125 | #define isp1760_dbg(priv, fmt, args...) \ | ||
126 | dev_dbg(priv_to_hcd(priv)->self.controller, fmt, ##args) | ||
127 | |||
128 | #define isp1760_info(priv, fmt, args...) \ | ||
129 | dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args) | ||
130 | |||
131 | #define isp1760_err(priv, fmt, args...) \ | ||
132 | dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args) | ||
133 | |||
134 | /* | 116 | /* |
135 | * Device flags that can vary from board to board. All of these | 117 | * Device flags that can vary from board to board. All of these |
136 | * indicate the most "atypical" case, so that a devflags of 0 is | 118 | * indicate the most "atypical" case, so that a devflags of 0 is |
@@ -167,63 +149,57 @@ struct memory_chunk { | |||
167 | #define BLOCK_2_SIZE 1024 | 149 | #define BLOCK_2_SIZE 1024 |
168 | #define BLOCK_3_SIZE 8192 | 150 | #define BLOCK_3_SIZE 8192 |
169 | #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) | 151 | #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) |
170 | #define PAYLOAD_SIZE 0xf000 | 152 | #define MAX_PAYLOAD_SIZE BLOCK_3_SIZE |
171 | 153 | #define PAYLOAD_AREA_SIZE 0xf000 | |
172 | /* I saw if some reloads if the pointer was negative */ | ||
173 | #define ISP1760_NULL_POINTER (0x400) | ||
174 | 154 | ||
175 | /* ATL */ | 155 | /* ATL */ |
176 | /* DW0 */ | 156 | /* DW0 */ |
177 | #define PTD_VALID 1 | 157 | #define DW0_VALID_BIT 1 |
178 | #define PTD_LENGTH(x) (((u32) x) << 3) | 158 | #define FROM_DW0_VALID(x) ((x) & 0x01) |
179 | #define PTD_MAXPACKET(x) (((u32) x) << 18) | 159 | #define TO_DW0_LENGTH(x) (((u32) x) << 3) |
180 | #define PTD_MULTI(x) (((u32) x) << 29) | 160 | #define TO_DW0_MAXPACKET(x) (((u32) x) << 18) |
181 | #define PTD_ENDPOINT(x) (((u32) x) << 31) | 161 | #define TO_DW0_MULTI(x) (((u32) x) << 29) |
162 | #define TO_DW0_ENDPOINT(x) (((u32) x) << 31) | ||
182 | /* DW1 */ | 163 | /* DW1 */ |
183 | #define PTD_DEVICE_ADDR(x) (((u32) x) << 3) | 164 | #define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3) |
184 | #define PTD_PID_TOKEN(x) (((u32) x) << 10) | 165 | #define TO_DW1_PID_TOKEN(x) (((u32) x) << 10) |
185 | #define PTD_TRANS_BULK ((u32) 2 << 12) | 166 | #define DW1_TRANS_BULK ((u32) 2 << 12) |
186 | #define PTD_TRANS_INT ((u32) 3 << 12) | 167 | #define DW1_TRANS_INT ((u32) 3 << 12) |
187 | #define PTD_TRANS_SPLIT ((u32) 1 << 14) | 168 | #define DW1_TRANS_SPLIT ((u32) 1 << 14) |
188 | #define PTD_SE_USB_LOSPEED ((u32) 2 << 16) | 169 | #define DW1_SE_USB_LOSPEED ((u32) 2 << 16) |
189 | #define PTD_PORT_NUM(x) (((u32) x) << 18) | 170 | #define TO_DW1_PORT_NUM(x) (((u32) x) << 18) |
190 | #define PTD_HUB_NUM(x) (((u32) x) << 25) | 171 | #define TO_DW1_HUB_NUM(x) (((u32) x) << 25) |
191 | #define PTD_PING(x) (((u32) x) << 26) | ||
192 | /* DW2 */ | 172 | /* DW2 */ |
193 | #define PTD_RL_CNT(x) (((u32) x) << 25) | 173 | #define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8) |
194 | #define PTD_DATA_START_ADDR(x) (((u32) x) << 8) | 174 | #define TO_DW2_RL(x) ((x) << 25) |
195 | #define BASE_ADDR 0x1000 | 175 | #define FROM_DW2_RL(x) (((x) >> 25) & 0xf) |
196 | /* DW3 */ | 176 | /* DW3 */ |
197 | #define PTD_CERR(x) (((u32) x) << 23) | 177 | #define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff) |
198 | #define PTD_NAC_CNT(x) (((u32) x) << 19) | 178 | #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff) |
199 | #define PTD_ACTIVE ((u32) 1 << 31) | 179 | #define TO_DW3_NAKCOUNT(x) ((x) << 19) |
200 | #define PTD_DATA_TOGGLE(x) (((u32) x) << 25) | 180 | #define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf) |
201 | 181 | #define TO_DW3_CERR(x) ((x) << 23) | |
202 | #define DW3_HALT_BIT (1 << 30) | 182 | #define FROM_DW3_CERR(x) (((x) >> 23) & 0x3) |
183 | #define TO_DW3_DATA_TOGGLE(x) ((x) << 25) | ||
184 | #define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1) | ||
185 | #define TO_DW3_PING(x) ((x) << 26) | ||
186 | #define FROM_DW3_PING(x) (((x) >> 26) & 0x1) | ||
203 | #define DW3_ERROR_BIT (1 << 28) | 187 | #define DW3_ERROR_BIT (1 << 28) |
204 | #define DW3_QTD_ACTIVE (1 << 31) | 188 | #define DW3_BABBLE_BIT (1 << 29) |
189 | #define DW3_HALT_BIT (1 << 30) | ||
190 | #define DW3_ACTIVE_BIT (1 << 31) | ||
205 | 191 | ||
206 | #define INT_UNDERRUN (1 << 2) | 192 | #define INT_UNDERRUN (1 << 2) |
207 | #define INT_BABBLE (1 << 1) | 193 | #define INT_BABBLE (1 << 1) |
208 | #define INT_EXACT (1 << 0) | 194 | #define INT_EXACT (1 << 0) |
209 | 195 | ||
210 | #define DW1_GET_PID(x) (((x) >> 10) & 0x3) | ||
211 | #define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff) | ||
212 | #define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff) | ||
213 | |||
214 | #define SETUP_PID (2) | 196 | #define SETUP_PID (2) |
215 | #define IN_PID (1) | 197 | #define IN_PID (1) |
216 | #define OUT_PID (0) | 198 | #define OUT_PID (0) |
217 | #define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3) | ||
218 | |||
219 | #define DATA_TOGGLE (1 << 31) | ||
220 | #define GET_DATA_TOGGLE(x) ((x) >> 31) | ||
221 | 199 | ||
222 | /* Errata 1 */ | 200 | /* Errata 1 */ |
223 | #define RL_COUNTER (0) | 201 | #define RL_COUNTER (0) |
224 | #define NAK_COUNTER (0) | 202 | #define NAK_COUNTER (0) |
225 | #define ERR_COUNTER (2) | 203 | #define ERR_COUNTER (2) |
226 | 204 | ||
227 | #define HC_ATL_PL_SIZE (8192) | 205 | #endif /* _ISP1760_HCD_H_ */ |
228 | |||
229 | #endif | ||
diff --git a/drivers/usb/host/isp1760-if.c b/drivers/usb/host/isp1760-if.c index 3b28dbfca058..7ee30056f373 100644 --- a/drivers/usb/host/isp1760-if.c +++ b/drivers/usb/host/isp1760-if.c | |||
@@ -27,8 +27,7 @@ | |||
27 | #endif | 27 | #endif |
28 | 28 | ||
29 | #ifdef CONFIG_PPC_OF | 29 | #ifdef CONFIG_PPC_OF |
30 | static int of_isp1760_probe(struct platform_device *dev, | 30 | static int of_isp1760_probe(struct platform_device *dev) |
31 | const struct of_device_id *match) | ||
32 | { | 31 | { |
33 | struct usb_hcd *hcd; | 32 | struct usb_hcd *hcd; |
34 | struct device_node *dp = dev->dev.of_node; | 33 | struct device_node *dp = dev->dev.of_node; |
@@ -119,7 +118,7 @@ static const struct of_device_id of_isp1760_match[] = { | |||
119 | }; | 118 | }; |
120 | MODULE_DEVICE_TABLE(of, of_isp1760_match); | 119 | MODULE_DEVICE_TABLE(of, of_isp1760_match); |
121 | 120 | ||
122 | static struct of_platform_driver isp1760_of_driver = { | 121 | static struct platform_driver isp1760_of_driver = { |
123 | .driver = { | 122 | .driver = { |
124 | .name = "nxp-isp1760", | 123 | .name = "nxp-isp1760", |
125 | .owner = THIS_MODULE, | 124 | .owner = THIS_MODULE, |
@@ -398,7 +397,7 @@ static int __init isp1760_init(void) | |||
398 | if (!ret) | 397 | if (!ret) |
399 | any_ret = 0; | 398 | any_ret = 0; |
400 | #ifdef CONFIG_PPC_OF | 399 | #ifdef CONFIG_PPC_OF |
401 | ret = of_register_platform_driver(&isp1760_of_driver); | 400 | ret = platform_driver_register(&isp1760_of_driver); |
402 | if (!ret) | 401 | if (!ret) |
403 | any_ret = 0; | 402 | any_ret = 0; |
404 | #endif | 403 | #endif |
@@ -418,7 +417,7 @@ static void __exit isp1760_exit(void) | |||
418 | { | 417 | { |
419 | platform_driver_unregister(&isp1760_plat_driver); | 418 | platform_driver_unregister(&isp1760_plat_driver); |
420 | #ifdef CONFIG_PPC_OF | 419 | #ifdef CONFIG_PPC_OF |
421 | of_unregister_platform_driver(&isp1760_of_driver); | 420 | platform_driver_unregister(&isp1760_of_driver); |
422 | #endif | 421 | #endif |
423 | #ifdef CONFIG_PCI | 422 | #ifdef CONFIG_PCI |
424 | pci_unregister_driver(&isp1761_pci_driver); | 423 | pci_unregister_driver(&isp1761_pci_driver); |
diff --git a/drivers/usb/host/octeon2-common.c b/drivers/usb/host/octeon2-common.c new file mode 100644 index 000000000000..d9df423f3d12 --- /dev/null +++ b/drivers/usb/host/octeon2-common.c | |||
@@ -0,0 +1,200 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2010, 2011 Cavium Networks | ||
7 | */ | ||
8 | |||
9 | #include <linux/module.h> | ||
10 | #include <linux/mutex.h> | ||
11 | #include <linux/delay.h> | ||
12 | |||
13 | #include <asm/octeon/octeon.h> | ||
14 | #include <asm/octeon/cvmx-uctlx-defs.h> | ||
15 | |||
16 | static DEFINE_MUTEX(octeon2_usb_clocks_mutex); | ||
17 | |||
18 | static int octeon2_usb_clock_start_cnt; | ||
19 | |||
20 | void octeon2_usb_clocks_start(void) | ||
21 | { | ||
22 | u64 div; | ||
23 | union cvmx_uctlx_if_ena if_ena; | ||
24 | union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; | ||
25 | union cvmx_uctlx_uphy_ctl_status uphy_ctl_status; | ||
26 | union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; | ||
27 | int i; | ||
28 | unsigned long io_clk_64_to_ns; | ||
29 | |||
30 | |||
31 | mutex_lock(&octeon2_usb_clocks_mutex); | ||
32 | |||
33 | octeon2_usb_clock_start_cnt++; | ||
34 | if (octeon2_usb_clock_start_cnt != 1) | ||
35 | goto exit; | ||
36 | |||
37 | io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); | ||
38 | |||
39 | /* | ||
40 | * Step 1: Wait for voltages stable. That surely happened | ||
41 | * before starting the kernel. | ||
42 | * | ||
43 | * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 | ||
44 | */ | ||
45 | if_ena.u64 = 0; | ||
46 | if_ena.s.en = 1; | ||
47 | cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); | ||
48 | |||
49 | /* Step 3: Configure the reference clock, PHY, and HCLK */ | ||
50 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); | ||
51 | |||
52 | /* | ||
53 | * If the UCTL looks like it has already been started, skip | ||
54 | * the initialization, otherwise bus errors are obtained. | ||
55 | */ | ||
56 | if (clk_rst_ctl.s.hrst) | ||
57 | goto end_clock; | ||
58 | /* 3a */ | ||
59 | clk_rst_ctl.s.p_por = 1; | ||
60 | clk_rst_ctl.s.hrst = 0; | ||
61 | clk_rst_ctl.s.p_prst = 0; | ||
62 | clk_rst_ctl.s.h_clkdiv_rst = 0; | ||
63 | clk_rst_ctl.s.o_clkdiv_rst = 0; | ||
64 | clk_rst_ctl.s.h_clkdiv_en = 0; | ||
65 | clk_rst_ctl.s.o_clkdiv_en = 0; | ||
66 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
67 | |||
68 | /* 3b */ | ||
69 | /* 12MHz crystal. */ | ||
70 | clk_rst_ctl.s.p_refclk_sel = 0; | ||
71 | clk_rst_ctl.s.p_refclk_div = 0; | ||
72 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
73 | |||
74 | /* 3c */ | ||
75 | div = octeon_get_io_clock_rate() / 130000000ull; | ||
76 | |||
77 | switch (div) { | ||
78 | case 0: | ||
79 | div = 1; | ||
80 | break; | ||
81 | case 1: | ||
82 | case 2: | ||
83 | case 3: | ||
84 | case 4: | ||
85 | break; | ||
86 | case 5: | ||
87 | div = 4; | ||
88 | break; | ||
89 | case 6: | ||
90 | case 7: | ||
91 | div = 6; | ||
92 | break; | ||
93 | case 8: | ||
94 | case 9: | ||
95 | case 10: | ||
96 | case 11: | ||
97 | div = 8; | ||
98 | break; | ||
99 | default: | ||
100 | div = 12; | ||
101 | break; | ||
102 | } | ||
103 | clk_rst_ctl.s.h_div = div; | ||
104 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
105 | /* Read it back, */ | ||
106 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); | ||
107 | clk_rst_ctl.s.h_clkdiv_en = 1; | ||
108 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
109 | /* 3d */ | ||
110 | clk_rst_ctl.s.h_clkdiv_rst = 1; | ||
111 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
112 | |||
113 | /* 3e: delay 64 io clocks */ | ||
114 | ndelay(io_clk_64_to_ns); | ||
115 | |||
116 | /* | ||
117 | * Step 4: Program the power-on reset field in the UCTL | ||
118 | * clock-reset-control register. | ||
119 | */ | ||
120 | clk_rst_ctl.s.p_por = 0; | ||
121 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
122 | |||
123 | /* Step 5: Wait 1 ms for the PHY clock to start. */ | ||
124 | mdelay(1); | ||
125 | |||
126 | /* | ||
127 | * Step 6: Program the reset input from automatic test | ||
128 | * equipment field in the UPHY CSR | ||
129 | */ | ||
130 | uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0)); | ||
131 | uphy_ctl_status.s.ate_reset = 1; | ||
132 | cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); | ||
133 | |||
134 | /* Step 7: Wait for at least 10ns. */ | ||
135 | ndelay(10); | ||
136 | |||
137 | /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */ | ||
138 | uphy_ctl_status.s.ate_reset = 0; | ||
139 | cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); | ||
140 | |||
141 | /* | ||
142 | * Step 9: Wait for at least 20ns for UPHY to output PHY clock | ||
143 | * signals and OHCI_CLK48 | ||
144 | */ | ||
145 | ndelay(20); | ||
146 | |||
147 | /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ | ||
148 | /* 10a */ | ||
149 | clk_rst_ctl.s.o_clkdiv_rst = 1; | ||
150 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
151 | |||
152 | /* 10b */ | ||
153 | clk_rst_ctl.s.o_clkdiv_en = 1; | ||
154 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
155 | |||
156 | /* 10c */ | ||
157 | ndelay(io_clk_64_to_ns); | ||
158 | |||
159 | /* | ||
160 | * Step 11: Program the PHY reset field: | ||
161 | * UCTL0_CLK_RST_CTL[P_PRST] = 1 | ||
162 | */ | ||
163 | clk_rst_ctl.s.p_prst = 1; | ||
164 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
165 | |||
166 | /* Step 12: Wait 1 uS. */ | ||
167 | udelay(1); | ||
168 | |||
169 | /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ | ||
170 | clk_rst_ctl.s.hrst = 1; | ||
171 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); | ||
172 | |||
173 | end_clock: | ||
174 | /* Now we can set some other registers. */ | ||
175 | |||
176 | for (i = 0; i <= 1; i++) { | ||
177 | port_ctl_status.u64 = | ||
178 | cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); | ||
179 | /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ | ||
180 | port_ctl_status.s.txvreftune = 15; | ||
181 | port_ctl_status.s.txrisetune = 1; | ||
182 | port_ctl_status.s.txpreemphasistune = 1; | ||
183 | cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), | ||
184 | port_ctl_status.u64); | ||
185 | } | ||
186 | |||
187 | /* Set uSOF cycle period to 60,000 bits. */ | ||
188 | cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); | ||
189 | exit: | ||
190 | mutex_unlock(&octeon2_usb_clocks_mutex); | ||
191 | } | ||
192 | EXPORT_SYMBOL(octeon2_usb_clocks_start); | ||
193 | |||
194 | void octeon2_usb_clocks_stop(void) | ||
195 | { | ||
196 | mutex_lock(&octeon2_usb_clocks_mutex); | ||
197 | octeon2_usb_clock_start_cnt--; | ||
198 | mutex_unlock(&octeon2_usb_clocks_mutex); | ||
199 | } | ||
200 | EXPORT_SYMBOL(octeon2_usb_clocks_stop); | ||
diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c new file mode 100644 index 000000000000..ffea3e7cb0a8 --- /dev/null +++ b/drivers/usb/host/ohci-ath79.c | |||
@@ -0,0 +1,151 @@ | |||
1 | /* | ||
2 | * OHCI HCD (Host Controller Driver) for USB. | ||
3 | * | ||
4 | * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. | ||
5 | * | ||
6 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> | ||
7 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | ||
8 | * | ||
9 | * Parts of this file are based on Atheros' 2.6.15 BSP | ||
10 | * Copyright (C) 2007 Atheros Communications, Inc. | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify it | ||
13 | * under the terms of the GNU General Public License version 2 as published | ||
14 | * by the Free Software Foundation. | ||
15 | */ | ||
16 | |||
17 | #include <linux/platform_device.h> | ||
18 | |||
19 | static int __devinit ohci_ath79_start(struct usb_hcd *hcd) | ||
20 | { | ||
21 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | ||
22 | int ret; | ||
23 | |||
24 | ret = ohci_init(ohci); | ||
25 | if (ret < 0) | ||
26 | return ret; | ||
27 | |||
28 | ret = ohci_run(ohci); | ||
29 | if (ret < 0) | ||
30 | goto err; | ||
31 | |||
32 | return 0; | ||
33 | |||
34 | err: | ||
35 | ohci_stop(hcd); | ||
36 | return ret; | ||
37 | } | ||
38 | |||
39 | static const struct hc_driver ohci_ath79_hc_driver = { | ||
40 | .description = hcd_name, | ||
41 | .product_desc = "Atheros built-in OHCI controller", | ||
42 | .hcd_priv_size = sizeof(struct ohci_hcd), | ||
43 | |||
44 | .irq = ohci_irq, | ||
45 | .flags = HCD_USB11 | HCD_MEMORY, | ||
46 | |||
47 | .start = ohci_ath79_start, | ||
48 | .stop = ohci_stop, | ||
49 | .shutdown = ohci_shutdown, | ||
50 | |||
51 | .urb_enqueue = ohci_urb_enqueue, | ||
52 | .urb_dequeue = ohci_urb_dequeue, | ||
53 | .endpoint_disable = ohci_endpoint_disable, | ||
54 | |||
55 | /* | ||
56 | * scheduling support | ||
57 | */ | ||
58 | .get_frame_number = ohci_get_frame, | ||
59 | |||
60 | /* | ||
61 | * root hub support | ||
62 | */ | ||
63 | .hub_status_data = ohci_hub_status_data, | ||
64 | .hub_control = ohci_hub_control, | ||
65 | .start_port_reset = ohci_start_port_reset, | ||
66 | }; | ||
67 | |||
68 | static int ohci_ath79_probe(struct platform_device *pdev) | ||
69 | { | ||
70 | struct usb_hcd *hcd; | ||
71 | struct resource *res; | ||
72 | int irq; | ||
73 | int ret; | ||
74 | |||
75 | if (usb_disabled()) | ||
76 | return -ENODEV; | ||
77 | |||
78 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
79 | if (!res) { | ||
80 | dev_dbg(&pdev->dev, "no IRQ specified\n"); | ||
81 | return -ENODEV; | ||
82 | } | ||
83 | irq = res->start; | ||
84 | |||
85 | hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, | ||
86 | dev_name(&pdev->dev)); | ||
87 | if (!hcd) | ||
88 | return -ENOMEM; | ||
89 | |||
90 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
91 | if (!res) { | ||
92 | dev_dbg(&pdev->dev, "no base address specified\n"); | ||
93 | ret = -ENODEV; | ||
94 | goto err_put_hcd; | ||
95 | } | ||
96 | hcd->rsrc_start = res->start; | ||
97 | hcd->rsrc_len = res->end - res->start + 1; | ||
98 | |||
99 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
100 | dev_dbg(&pdev->dev, "controller already in use\n"); | ||
101 | ret = -EBUSY; | ||
102 | goto err_put_hcd; | ||
103 | } | ||
104 | |||
105 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
106 | if (!hcd->regs) { | ||
107 | dev_dbg(&pdev->dev, "error mapping memory\n"); | ||
108 | ret = -EFAULT; | ||
109 | goto err_release_region; | ||
110 | } | ||
111 | |||
112 | ohci_hcd_init(hcd_to_ohci(hcd)); | ||
113 | |||
114 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); | ||
115 | if (ret) | ||
116 | goto err_stop_hcd; | ||
117 | |||
118 | return 0; | ||
119 | |||
120 | err_stop_hcd: | ||
121 | iounmap(hcd->regs); | ||
122 | err_release_region: | ||
123 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
124 | err_put_hcd: | ||
125 | usb_put_hcd(hcd); | ||
126 | return ret; | ||
127 | } | ||
128 | |||
129 | static int ohci_ath79_remove(struct platform_device *pdev) | ||
130 | { | ||
131 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
132 | |||
133 | usb_remove_hcd(hcd); | ||
134 | iounmap(hcd->regs); | ||
135 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
136 | usb_put_hcd(hcd); | ||
137 | |||
138 | return 0; | ||
139 | } | ||
140 | |||
141 | static struct platform_driver ohci_hcd_ath79_driver = { | ||
142 | .probe = ohci_ath79_probe, | ||
143 | .remove = ohci_ath79_remove, | ||
144 | .shutdown = usb_hcd_platform_shutdown, | ||
145 | .driver = { | ||
146 | .name = "ath79-ohci", | ||
147 | .owner = THIS_MODULE, | ||
148 | }, | ||
149 | }; | ||
150 | |||
151 | MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); | ||
diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 17a6043c1fa0..958d985f2951 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c | |||
@@ -33,7 +33,7 @@ | |||
33 | 33 | ||
34 | #ifdef __LITTLE_ENDIAN | 34 | #ifdef __LITTLE_ENDIAN |
35 | #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) | 35 | #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) |
36 | #elif __BIG_ENDIAN | 36 | #elif defined(__BIG_ENDIAN) |
37 | #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ | 37 | #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ |
38 | USBH_ENABLE_BE) | 38 | USBH_ENABLE_BE) |
39 | #else | 39 | #else |
diff --git a/drivers/usb/host/ohci-cns3xxx.c b/drivers/usb/host/ohci-cns3xxx.c new file mode 100644 index 000000000000..f05ef87e934c --- /dev/null +++ b/drivers/usb/host/ohci-cns3xxx.c | |||
@@ -0,0 +1,165 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Cavium Networks | ||
3 | * | ||
4 | * This file is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License, Version 2, as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #include <linux/platform_device.h> | ||
10 | #include <linux/atomic.h> | ||
11 | #include <mach/cns3xxx.h> | ||
12 | #include <mach/pm.h> | ||
13 | |||
14 | static int __devinit | ||
15 | cns3xxx_ohci_start(struct usb_hcd *hcd) | ||
16 | { | ||
17 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | ||
18 | int ret; | ||
19 | |||
20 | /* | ||
21 | * EHCI and OHCI share the same clock and power, | ||
22 | * resetting twice would cause the 1st controller been reset. | ||
23 | * Therefore only do power up at the first up device, and | ||
24 | * power down at the last down device. | ||
25 | * | ||
26 | * Set USB AHB INCR length to 16 | ||
27 | */ | ||
28 | if (atomic_inc_return(&usb_pwr_ref) == 1) { | ||
29 | cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); | ||
30 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); | ||
31 | cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); | ||
32 | __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), | ||
33 | MISC_CHIP_CONFIG_REG); | ||
34 | } | ||
35 | |||
36 | ret = ohci_init(ohci); | ||
37 | if (ret < 0) | ||
38 | return ret; | ||
39 | |||
40 | ohci->num_ports = 1; | ||
41 | |||
42 | ret = ohci_run(ohci); | ||
43 | if (ret < 0) { | ||
44 | err("can't start %s", hcd->self.bus_name); | ||
45 | ohci_stop(hcd); | ||
46 | return ret; | ||
47 | } | ||
48 | return 0; | ||
49 | } | ||
50 | |||
51 | static const struct hc_driver cns3xxx_ohci_hc_driver = { | ||
52 | .description = hcd_name, | ||
53 | .product_desc = "CNS3XXX OHCI Host controller", | ||
54 | .hcd_priv_size = sizeof(struct ohci_hcd), | ||
55 | .irq = ohci_irq, | ||
56 | .flags = HCD_USB11 | HCD_MEMORY, | ||
57 | .start = cns3xxx_ohci_start, | ||
58 | .stop = ohci_stop, | ||
59 | .shutdown = ohci_shutdown, | ||
60 | .urb_enqueue = ohci_urb_enqueue, | ||
61 | .urb_dequeue = ohci_urb_dequeue, | ||
62 | .endpoint_disable = ohci_endpoint_disable, | ||
63 | .get_frame_number = ohci_get_frame, | ||
64 | .hub_status_data = ohci_hub_status_data, | ||
65 | .hub_control = ohci_hub_control, | ||
66 | #ifdef CONFIG_PM | ||
67 | .bus_suspend = ohci_bus_suspend, | ||
68 | .bus_resume = ohci_bus_resume, | ||
69 | #endif | ||
70 | .start_port_reset = ohci_start_port_reset, | ||
71 | }; | ||
72 | |||
73 | static int cns3xxx_ohci_probe(struct platform_device *pdev) | ||
74 | { | ||
75 | struct device *dev = &pdev->dev; | ||
76 | struct usb_hcd *hcd; | ||
77 | const struct hc_driver *driver = &cns3xxx_ohci_hc_driver; | ||
78 | struct resource *res; | ||
79 | int irq; | ||
80 | int retval; | ||
81 | |||
82 | if (usb_disabled()) | ||
83 | return -ENODEV; | ||
84 | |||
85 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
86 | if (!res) { | ||
87 | dev_err(dev, "Found HC with no IRQ.\n"); | ||
88 | return -ENODEV; | ||
89 | } | ||
90 | irq = res->start; | ||
91 | |||
92 | hcd = usb_create_hcd(driver, dev, dev_name(dev)); | ||
93 | if (!hcd) | ||
94 | return -ENOMEM; | ||
95 | |||
96 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
97 | if (!res) { | ||
98 | dev_err(dev, "Found HC with no register addr.\n"); | ||
99 | retval = -ENODEV; | ||
100 | goto err1; | ||
101 | } | ||
102 | hcd->rsrc_start = res->start; | ||
103 | hcd->rsrc_len = res->end - res->start + 1; | ||
104 | |||
105 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, | ||
106 | driver->description)) { | ||
107 | dev_dbg(dev, "controller already in use\n"); | ||
108 | retval = -EBUSY; | ||
109 | goto err1; | ||
110 | } | ||
111 | |||
112 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
113 | if (!hcd->regs) { | ||
114 | dev_dbg(dev, "error mapping memory\n"); | ||
115 | retval = -EFAULT; | ||
116 | goto err2; | ||
117 | } | ||
118 | |||
119 | ohci_hcd_init(hcd_to_ohci(hcd)); | ||
120 | |||
121 | retval = usb_add_hcd(hcd, irq, IRQF_SHARED); | ||
122 | if (retval == 0) | ||
123 | return retval; | ||
124 | |||
125 | iounmap(hcd->regs); | ||
126 | err2: | ||
127 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
128 | err1: | ||
129 | usb_put_hcd(hcd); | ||
130 | return retval; | ||
131 | } | ||
132 | |||
133 | static int cns3xxx_ohci_remove(struct platform_device *pdev) | ||
134 | { | ||
135 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
136 | |||
137 | usb_remove_hcd(hcd); | ||
138 | iounmap(hcd->regs); | ||
139 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
140 | |||
141 | /* | ||
142 | * EHCI and OHCI share the same clock and power, | ||
143 | * resetting twice would cause the 1st controller been reset. | ||
144 | * Therefore only do power up at the first up device, and | ||
145 | * power down at the last down device. | ||
146 | */ | ||
147 | if (atomic_dec_return(&usb_pwr_ref) == 0) | ||
148 | cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); | ||
149 | |||
150 | usb_put_hcd(hcd); | ||
151 | |||
152 | platform_set_drvdata(pdev, NULL); | ||
153 | |||
154 | return 0; | ||
155 | } | ||
156 | |||
157 | MODULE_ALIAS("platform:cns3xxx-ohci"); | ||
158 | |||
159 | static struct platform_driver ohci_hcd_cns3xxx_driver = { | ||
160 | .probe = cns3xxx_ohci_probe, | ||
161 | .remove = cns3xxx_ohci_remove, | ||
162 | .driver = { | ||
163 | .name = "cns3xxx-ohci", | ||
164 | }, | ||
165 | }; | ||
diff --git a/drivers/usb/host/ohci-dbg.c b/drivers/usb/host/ohci-dbg.c index 36abd2baa3ea..d7d34492934a 100644 --- a/drivers/usb/host/ohci-dbg.c +++ b/drivers/usb/host/ohci-dbg.c | |||
@@ -413,18 +413,21 @@ static const struct file_operations debug_async_fops = { | |||
413 | .open = debug_async_open, | 413 | .open = debug_async_open, |
414 | .read = debug_output, | 414 | .read = debug_output, |
415 | .release = debug_close, | 415 | .release = debug_close, |
416 | .llseek = default_llseek, | ||
416 | }; | 417 | }; |
417 | static const struct file_operations debug_periodic_fops = { | 418 | static const struct file_operations debug_periodic_fops = { |
418 | .owner = THIS_MODULE, | 419 | .owner = THIS_MODULE, |
419 | .open = debug_periodic_open, | 420 | .open = debug_periodic_open, |
420 | .read = debug_output, | 421 | .read = debug_output, |
421 | .release = debug_close, | 422 | .release = debug_close, |
423 | .llseek = default_llseek, | ||
422 | }; | 424 | }; |
423 | static const struct file_operations debug_registers_fops = { | 425 | static const struct file_operations debug_registers_fops = { |
424 | .owner = THIS_MODULE, | 426 | .owner = THIS_MODULE, |
425 | .open = debug_registers_open, | 427 | .open = debug_registers_open, |
426 | .read = debug_output, | 428 | .read = debug_output, |
427 | .release = debug_close, | 429 | .release = debug_close, |
430 | .llseek = default_llseek, | ||
428 | }; | 431 | }; |
429 | 432 | ||
430 | static struct dentry *ohci_debug_root; | 433 | static struct dentry *ohci_debug_root; |
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index c3b4ccc7337b..f9cf3f04b742 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c | |||
@@ -1,5 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | 2 | * Open Host Controller Interface (OHCI) driver for USB. |
3 | * | ||
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | ||
3 | * | 5 | * |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | 6 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | 7 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> |
@@ -75,6 +77,7 @@ static const char hcd_name [] = "ohci_hcd"; | |||
75 | #define STATECHANGE_DELAY msecs_to_jiffies(300) | 77 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
76 | 78 | ||
77 | #include "ohci.h" | 79 | #include "ohci.h" |
80 | #include "pci-quirks.h" | ||
78 | 81 | ||
79 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | 82 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); |
80 | static int ohci_init (struct ohci_hcd *ohci); | 83 | static int ohci_init (struct ohci_hcd *ohci); |
@@ -85,18 +88,8 @@ static int ohci_restart (struct ohci_hcd *ohci); | |||
85 | #endif | 88 | #endif |
86 | 89 | ||
87 | #ifdef CONFIG_PCI | 90 | #ifdef CONFIG_PCI |
88 | static void quirk_amd_pll(int state); | ||
89 | static void amd_iso_dev_put(void); | ||
90 | static void sb800_prefetch(struct ohci_hcd *ohci, int on); | 91 | static void sb800_prefetch(struct ohci_hcd *ohci, int on); |
91 | #else | 92 | #else |
92 | static inline void quirk_amd_pll(int state) | ||
93 | { | ||
94 | return; | ||
95 | } | ||
96 | static inline void amd_iso_dev_put(void) | ||
97 | { | ||
98 | return; | ||
99 | } | ||
100 | static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) | 93 | static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) |
101 | { | 94 | { |
102 | return; | 95 | return; |
@@ -171,7 +164,7 @@ static int ohci_urb_enqueue ( | |||
171 | // case PIPE_INTERRUPT: | 164 | // case PIPE_INTERRUPT: |
172 | // case PIPE_BULK: | 165 | // case PIPE_BULK: |
173 | default: | 166 | default: |
174 | /* one TD for every 4096 Bytes (can be upto 8K) */ | 167 | /* one TD for every 4096 Bytes (can be up to 8K) */ |
175 | size += urb->transfer_buffer_length / 4096; | 168 | size += urb->transfer_buffer_length / 4096; |
176 | /* ... and for any remaining bytes ... */ | 169 | /* ... and for any remaining bytes ... */ |
177 | if ((urb->transfer_buffer_length % 4096) != 0) | 170 | if ((urb->transfer_buffer_length % 4096) != 0) |
@@ -370,7 +363,6 @@ sanitize: | |||
370 | } | 363 | } |
371 | ep->hcpriv = NULL; | 364 | ep->hcpriv = NULL; |
372 | spin_unlock_irqrestore (&ohci->lock, flags); | 365 | spin_unlock_irqrestore (&ohci->lock, flags); |
373 | return; | ||
374 | } | 366 | } |
375 | 367 | ||
376 | static int ohci_get_frame (struct usb_hcd *hcd) | 368 | static int ohci_get_frame (struct usb_hcd *hcd) |
@@ -398,7 +390,14 @@ ohci_shutdown (struct usb_hcd *hcd) | |||
398 | 390 | ||
399 | ohci = hcd_to_ohci (hcd); | 391 | ohci = hcd_to_ohci (hcd); |
400 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | 392 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
401 | ohci_usb_reset (ohci); | 393 | ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); |
394 | |||
395 | /* If the SHUTDOWN quirk is set, don't put the controller in RESET */ | ||
396 | ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ? | ||
397 | OHCI_CTRL_RWC | OHCI_CTRL_HCFS : | ||
398 | OHCI_CTRL_RWC); | ||
399 | ohci_writel(ohci, ohci->hc_control, &ohci->regs->control); | ||
400 | |||
402 | /* flush the writes */ | 401 | /* flush the writes */ |
403 | (void) ohci_readl (ohci, &ohci->regs->control); | 402 | (void) ohci_readl (ohci, &ohci->regs->control); |
404 | } | 403 | } |
@@ -767,6 +766,7 @@ static irqreturn_t ohci_irq (struct usb_hcd *hcd) | |||
767 | if (ints == ~(u32)0) { | 766 | if (ints == ~(u32)0) { |
768 | disable (ohci); | 767 | disable (ohci); |
769 | ohci_dbg (ohci, "device removed!\n"); | 768 | ohci_dbg (ohci, "device removed!\n"); |
769 | usb_hc_died(hcd); | ||
770 | return IRQ_HANDLED; | 770 | return IRQ_HANDLED; |
771 | } | 771 | } |
772 | 772 | ||
@@ -774,7 +774,7 @@ static irqreturn_t ohci_irq (struct usb_hcd *hcd) | |||
774 | ints &= ohci_readl(ohci, ®s->intrenable); | 774 | ints &= ohci_readl(ohci, ®s->intrenable); |
775 | 775 | ||
776 | /* interrupt for some other device? */ | 776 | /* interrupt for some other device? */ |
777 | if (ints == 0) | 777 | if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT)) |
778 | return IRQ_NOTMINE; | 778 | return IRQ_NOTMINE; |
779 | 779 | ||
780 | if (ints & OHCI_INTR_UE) { | 780 | if (ints & OHCI_INTR_UE) { |
@@ -791,6 +791,7 @@ static irqreturn_t ohci_irq (struct usb_hcd *hcd) | |||
791 | } else { | 791 | } else { |
792 | disable (ohci); | 792 | disable (ohci); |
793 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | 793 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); |
794 | usb_hc_died(hcd); | ||
794 | } | 795 | } |
795 | 796 | ||
796 | ohci_dump (ohci, 1); | 797 | ohci_dump (ohci, 1); |
@@ -895,7 +896,8 @@ static void ohci_stop (struct usb_hcd *hcd) | |||
895 | 896 | ||
896 | ohci_dump (ohci, 1); | 897 | ohci_dump (ohci, 1); |
897 | 898 | ||
898 | flush_scheduled_work(); | 899 | if (quirk_nec(ohci)) |
900 | flush_work_sync(&ohci->nec_work); | ||
899 | 901 | ||
900 | ohci_usb_reset (ohci); | 902 | ohci_usb_reset (ohci); |
901 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | 903 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
@@ -905,7 +907,7 @@ static void ohci_stop (struct usb_hcd *hcd) | |||
905 | if (quirk_zfmicro(ohci)) | 907 | if (quirk_zfmicro(ohci)) |
906 | del_timer(&ohci->unlink_watchdog); | 908 | del_timer(&ohci->unlink_watchdog); |
907 | if (quirk_amdiso(ohci)) | 909 | if (quirk_amdiso(ohci)) |
908 | amd_iso_dev_put(); | 910 | usb_amd_dev_put(); |
909 | 911 | ||
910 | remove_debug_files (ohci); | 912 | remove_debug_files (ohci); |
911 | ohci_mem_cleanup (ohci); | 913 | ohci_mem_cleanup (ohci); |
@@ -1016,11 +1018,6 @@ MODULE_LICENSE ("GPL"); | |||
1016 | #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver | 1018 | #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver |
1017 | #endif | 1019 | #endif |
1018 | 1020 | ||
1019 | #ifdef CONFIG_ARCH_LH7A404 | ||
1020 | #include "ohci-lh7a404.c" | ||
1021 | #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver | ||
1022 | #endif | ||
1023 | |||
1024 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | 1021 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
1025 | #include "ohci-pxa27x.c" | 1022 | #include "ohci-pxa27x.c" |
1026 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver | 1023 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver |
@@ -1061,10 +1058,7 @@ MODULE_LICENSE ("GPL"); | |||
1061 | #define PLATFORM_DRIVER ohci_hcd_da8xx_driver | 1058 | #define PLATFORM_DRIVER ohci_hcd_da8xx_driver |
1062 | #endif | 1059 | #endif |
1063 | 1060 | ||
1064 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 1061 | #ifdef CONFIG_USB_OHCI_SH |
1065 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
1066 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | ||
1067 | defined(CONFIG_CPU_SUBTYPE_SH7786) | ||
1068 | #include "ohci-sh.c" | 1062 | #include "ohci-sh.c" |
1069 | #define PLATFORM_DRIVER ohci_hcd_sh_driver | 1063 | #define PLATFORM_DRIVER ohci_hcd_sh_driver |
1070 | #endif | 1064 | #endif |
@@ -1075,6 +1069,11 @@ MODULE_LICENSE ("GPL"); | |||
1075 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | 1069 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver |
1076 | #endif | 1070 | #endif |
1077 | 1071 | ||
1072 | #ifdef CONFIG_PLAT_SPEAR | ||
1073 | #include "ohci-spear.c" | ||
1074 | #define PLATFORM_DRIVER spear_ohci_hcd_driver | ||
1075 | #endif | ||
1076 | |||
1078 | #ifdef CONFIG_PPC_PS3 | 1077 | #ifdef CONFIG_PPC_PS3 |
1079 | #include "ohci-ps3.c" | 1078 | #include "ohci-ps3.c" |
1080 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver | 1079 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
@@ -1100,6 +1099,21 @@ MODULE_LICENSE ("GPL"); | |||
1100 | #define PLATFORM_DRIVER ohci_hcd_jz4740_driver | 1099 | #define PLATFORM_DRIVER ohci_hcd_jz4740_driver |
1101 | #endif | 1100 | #endif |
1102 | 1101 | ||
1102 | #ifdef CONFIG_USB_OCTEON_OHCI | ||
1103 | #include "ohci-octeon.c" | ||
1104 | #define PLATFORM_DRIVER ohci_octeon_driver | ||
1105 | #endif | ||
1106 | |||
1107 | #ifdef CONFIG_USB_CNS3XXX_OHCI | ||
1108 | #include "ohci-cns3xxx.c" | ||
1109 | #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver | ||
1110 | #endif | ||
1111 | |||
1112 | #ifdef CONFIG_USB_OHCI_ATH79 | ||
1113 | #include "ohci-ath79.c" | ||
1114 | #define PLATFORM_DRIVER ohci_hcd_ath79_driver | ||
1115 | #endif | ||
1116 | |||
1103 | #if !defined(PCI_DRIVER) && \ | 1117 | #if !defined(PCI_DRIVER) && \ |
1104 | !defined(PLATFORM_DRIVER) && \ | 1118 | !defined(PLATFORM_DRIVER) && \ |
1105 | !defined(OMAP1_PLATFORM_DRIVER) && \ | 1119 | !defined(OMAP1_PLATFORM_DRIVER) && \ |
@@ -1158,7 +1172,7 @@ static int __init ohci_hcd_mod_init(void) | |||
1158 | #endif | 1172 | #endif |
1159 | 1173 | ||
1160 | #ifdef OF_PLATFORM_DRIVER | 1174 | #ifdef OF_PLATFORM_DRIVER |
1161 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | 1175 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
1162 | if (retval < 0) | 1176 | if (retval < 0) |
1163 | goto error_of_platform; | 1177 | goto error_of_platform; |
1164 | #endif | 1178 | #endif |
@@ -1217,7 +1231,7 @@ static int __init ohci_hcd_mod_init(void) | |||
1217 | error_sa1111: | 1231 | error_sa1111: |
1218 | #endif | 1232 | #endif |
1219 | #ifdef OF_PLATFORM_DRIVER | 1233 | #ifdef OF_PLATFORM_DRIVER |
1220 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | 1234 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
1221 | error_of_platform: | 1235 | error_of_platform: |
1222 | #endif | 1236 | #endif |
1223 | #ifdef PLATFORM_DRIVER | 1237 | #ifdef PLATFORM_DRIVER |
@@ -1265,11 +1279,14 @@ static void __exit ohci_hcd_mod_exit(void) | |||
1265 | sa1111_driver_unregister(&SA1111_DRIVER); | 1279 | sa1111_driver_unregister(&SA1111_DRIVER); |
1266 | #endif | 1280 | #endif |
1267 | #ifdef OF_PLATFORM_DRIVER | 1281 | #ifdef OF_PLATFORM_DRIVER |
1268 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | 1282 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
1269 | #endif | 1283 | #endif |
1270 | #ifdef PLATFORM_DRIVER | 1284 | #ifdef PLATFORM_DRIVER |
1271 | platform_driver_unregister(&PLATFORM_DRIVER); | 1285 | platform_driver_unregister(&PLATFORM_DRIVER); |
1272 | #endif | 1286 | #endif |
1287 | #ifdef OMAP3_PLATFORM_DRIVER | ||
1288 | platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); | ||
1289 | #endif | ||
1273 | #ifdef PS3_SYSTEM_BUS_DRIVER | 1290 | #ifdef PS3_SYSTEM_BUS_DRIVER |
1274 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | 1291 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
1275 | #endif | 1292 | #endif |
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c index cddcda95b579..9154615292db 100644 --- a/drivers/usb/host/ohci-hub.c +++ b/drivers/usb/host/ohci-hub.c | |||
@@ -580,15 +580,16 @@ ohci_hub_descriptor ( | |||
580 | temp |= 0x0008; | 580 | temp |= 0x0008; |
581 | desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ohci, temp); | 581 | desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ohci, temp); |
582 | 582 | ||
583 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 583 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
584 | rh = roothub_b (ohci); | 584 | rh = roothub_b (ohci); |
585 | memset(desc->bitmap, 0xff, sizeof(desc->bitmap)); | 585 | memset(desc->u.hs.DeviceRemovable, 0xff, |
586 | desc->bitmap [0] = rh & RH_B_DR; | 586 | sizeof(desc->u.hs.DeviceRemovable)); |
587 | desc->u.hs.DeviceRemovable[0] = rh & RH_B_DR; | ||
587 | if (ohci->num_ports > 7) { | 588 | if (ohci->num_ports > 7) { |
588 | desc->bitmap [1] = (rh & RH_B_DR) >> 8; | 589 | desc->u.hs.DeviceRemovable[1] = (rh & RH_B_DR) >> 8; |
589 | desc->bitmap [2] = 0xff; | 590 | desc->u.hs.DeviceRemovable[2] = 0xff; |
590 | } else | 591 | } else |
591 | desc->bitmap [1] = 0xff; | 592 | desc->u.hs.DeviceRemovable[1] = 0xff; |
592 | } | 593 | } |
593 | 594 | ||
594 | /*-------------------------------------------------------------------------*/ | 595 | /*-------------------------------------------------------------------------*/ |
diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c index 10e1872f3ab9..931d588c3fb5 100644 --- a/drivers/usb/host/ohci-jz4740.c +++ b/drivers/usb/host/ohci-jz4740.c | |||
@@ -273,4 +273,4 @@ static struct platform_driver ohci_hcd_jz4740_driver = { | |||
273 | }, | 273 | }, |
274 | }; | 274 | }; |
275 | 275 | ||
276 | MODULE_ALIAS("platfrom:jz4740-ohci"); | 276 | MODULE_ALIAS("platform:jz4740-ohci"); |
diff --git a/drivers/usb/host/ohci-lh7a404.c b/drivers/usb/host/ohci-lh7a404.c deleted file mode 100644 index 18d39f0463ee..000000000000 --- a/drivers/usb/host/ohci-lh7a404.c +++ /dev/null | |||
@@ -1,252 +0,0 @@ | |||
1 | /* | ||
2 | * OHCI HCD (Host Controller Driver) for USB. | ||
3 | * | ||
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | ||
5 | * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> | ||
6 | * (C) Copyright 2002 Hewlett-Packard Company | ||
7 | * | ||
8 | * Bus Glue for Sharp LH7A404 | ||
9 | * | ||
10 | * Written by Christopher Hoover <ch@hpl.hp.com> | ||
11 | * Based on fragments of previous driver by Russell King et al. | ||
12 | * | ||
13 | * Modified for LH7A404 from ohci-sa1111.c | ||
14 | * by Durgesh Pattamatta <pattamattad@sharpsec.com> | ||
15 | * | ||
16 | * This file is licenced under the GPL. | ||
17 | */ | ||
18 | |||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/signal.h> | ||
21 | |||
22 | #include <mach/hardware.h> | ||
23 | |||
24 | |||
25 | extern int usb_disabled(void); | ||
26 | |||
27 | /*-------------------------------------------------------------------------*/ | ||
28 | |||
29 | static void lh7a404_start_hc(struct platform_device *dev) | ||
30 | { | ||
31 | printk(KERN_DEBUG "%s: starting LH7A404 OHCI USB Controller\n", | ||
32 | __FILE__); | ||
33 | |||
34 | /* | ||
35 | * Now, carefully enable the USB clock, and take | ||
36 | * the USB host controller out of reset. | ||
37 | */ | ||
38 | CSC_PWRCNT |= CSC_PWRCNT_USBH_EN; /* Enable clock */ | ||
39 | udelay(1000); | ||
40 | USBH_CMDSTATUS = OHCI_HCR; | ||
41 | |||
42 | printk(KERN_DEBUG "%s: Clock to USB host has been enabled \n", __FILE__); | ||
43 | } | ||
44 | |||
45 | static void lh7a404_stop_hc(struct platform_device *dev) | ||
46 | { | ||
47 | printk(KERN_DEBUG "%s: stopping LH7A404 OHCI USB Controller\n", | ||
48 | __FILE__); | ||
49 | |||
50 | CSC_PWRCNT &= ~CSC_PWRCNT_USBH_EN; /* Disable clock */ | ||
51 | } | ||
52 | |||
53 | |||
54 | /*-------------------------------------------------------------------------*/ | ||
55 | |||
56 | /* configure so an HC device and id are always provided */ | ||
57 | /* always called with process context; sleeping is OK */ | ||
58 | |||
59 | |||
60 | /** | ||
61 | * usb_hcd_lh7a404_probe - initialize LH7A404-based HCDs | ||
62 | * Context: !in_interrupt() | ||
63 | * | ||
64 | * Allocates basic resources for this USB host controller, and | ||
65 | * then invokes the start() method for the HCD associated with it | ||
66 | * through the hotplug entry's driver_data. | ||
67 | * | ||
68 | */ | ||
69 | int usb_hcd_lh7a404_probe (const struct hc_driver *driver, | ||
70 | struct platform_device *dev) | ||
71 | { | ||
72 | int retval; | ||
73 | struct usb_hcd *hcd; | ||
74 | |||
75 | if (dev->resource[1].flags != IORESOURCE_IRQ) { | ||
76 | pr_debug("resource[1] is not IORESOURCE_IRQ"); | ||
77 | return -ENOMEM; | ||
78 | } | ||
79 | |||
80 | hcd = usb_create_hcd(driver, &dev->dev, "lh7a404"); | ||
81 | if (!hcd) | ||
82 | return -ENOMEM; | ||
83 | hcd->rsrc_start = dev->resource[0].start; | ||
84 | hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1; | ||
85 | |||
86 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
87 | pr_debug("request_mem_region failed"); | ||
88 | retval = -EBUSY; | ||
89 | goto err1; | ||
90 | } | ||
91 | |||
92 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
93 | if (!hcd->regs) { | ||
94 | pr_debug("ioremap failed"); | ||
95 | retval = -ENOMEM; | ||
96 | goto err2; | ||
97 | } | ||
98 | |||
99 | lh7a404_start_hc(dev); | ||
100 | ohci_hcd_init(hcd_to_ohci(hcd)); | ||
101 | |||
102 | retval = usb_add_hcd(hcd, dev->resource[1].start, IRQF_DISABLED); | ||
103 | if (retval == 0) | ||
104 | return retval; | ||
105 | |||
106 | lh7a404_stop_hc(dev); | ||
107 | iounmap(hcd->regs); | ||
108 | err2: | ||
109 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
110 | err1: | ||
111 | usb_put_hcd(hcd); | ||
112 | return retval; | ||
113 | } | ||
114 | |||
115 | |||
116 | /* may be called without controller electrically present */ | ||
117 | /* may be called with controller, bus, and devices active */ | ||
118 | |||
119 | /** | ||
120 | * usb_hcd_lh7a404_remove - shutdown processing for LH7A404-based HCDs | ||
121 | * @dev: USB Host Controller being removed | ||
122 | * Context: !in_interrupt() | ||
123 | * | ||
124 | * Reverses the effect of usb_hcd_lh7a404_probe(), first invoking | ||
125 | * the HCD's stop() method. It is always called from a thread | ||
126 | * context, normally "rmmod", "apmd", or something similar. | ||
127 | * | ||
128 | */ | ||
129 | void usb_hcd_lh7a404_remove (struct usb_hcd *hcd, struct platform_device *dev) | ||
130 | { | ||
131 | usb_remove_hcd(hcd); | ||
132 | lh7a404_stop_hc(dev); | ||
133 | iounmap(hcd->regs); | ||
134 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
135 | usb_put_hcd(hcd); | ||
136 | } | ||
137 | |||
138 | /*-------------------------------------------------------------------------*/ | ||
139 | |||
140 | static int __devinit | ||
141 | ohci_lh7a404_start (struct usb_hcd *hcd) | ||
142 | { | ||
143 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | ||
144 | int ret; | ||
145 | |||
146 | ohci_dbg (ohci, "ohci_lh7a404_start, ohci:%p", ohci); | ||
147 | if ((ret = ohci_init(ohci)) < 0) | ||
148 | return ret; | ||
149 | |||
150 | if ((ret = ohci_run (ohci)) < 0) { | ||
151 | err ("can't start %s", hcd->self.bus_name); | ||
152 | ohci_stop (hcd); | ||
153 | return ret; | ||
154 | } | ||
155 | return 0; | ||
156 | } | ||
157 | |||
158 | /*-------------------------------------------------------------------------*/ | ||
159 | |||
160 | static const struct hc_driver ohci_lh7a404_hc_driver = { | ||
161 | .description = hcd_name, | ||
162 | .product_desc = "LH7A404 OHCI", | ||
163 | .hcd_priv_size = sizeof(struct ohci_hcd), | ||
164 | |||
165 | /* | ||
166 | * generic hardware linkage | ||
167 | */ | ||
168 | .irq = ohci_irq, | ||
169 | .flags = HCD_USB11 | HCD_MEMORY, | ||
170 | |||
171 | /* | ||
172 | * basic lifecycle operations | ||
173 | */ | ||
174 | .start = ohci_lh7a404_start, | ||
175 | .stop = ohci_stop, | ||
176 | .shutdown = ohci_shutdown, | ||
177 | |||
178 | /* | ||
179 | * managing i/o requests and associated device resources | ||
180 | */ | ||
181 | .urb_enqueue = ohci_urb_enqueue, | ||
182 | .urb_dequeue = ohci_urb_dequeue, | ||
183 | .endpoint_disable = ohci_endpoint_disable, | ||
184 | |||
185 | /* | ||
186 | * scheduling support | ||
187 | */ | ||
188 | .get_frame_number = ohci_get_frame, | ||
189 | |||
190 | /* | ||
191 | * root hub support | ||
192 | */ | ||
193 | .hub_status_data = ohci_hub_status_data, | ||
194 | .hub_control = ohci_hub_control, | ||
195 | #ifdef CONFIG_PM | ||
196 | .bus_suspend = ohci_bus_suspend, | ||
197 | .bus_resume = ohci_bus_resume, | ||
198 | #endif | ||
199 | .start_port_reset = ohci_start_port_reset, | ||
200 | }; | ||
201 | |||
202 | /*-------------------------------------------------------------------------*/ | ||
203 | |||
204 | static int ohci_hcd_lh7a404_drv_probe(struct platform_device *pdev) | ||
205 | { | ||
206 | int ret; | ||
207 | |||
208 | pr_debug ("In ohci_hcd_lh7a404_drv_probe"); | ||
209 | |||
210 | if (usb_disabled()) | ||
211 | return -ENODEV; | ||
212 | |||
213 | ret = usb_hcd_lh7a404_probe(&ohci_lh7a404_hc_driver, pdev); | ||
214 | return ret; | ||
215 | } | ||
216 | |||
217 | static int ohci_hcd_lh7a404_drv_remove(struct platform_device *pdev) | ||
218 | { | ||
219 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
220 | |||
221 | usb_hcd_lh7a404_remove(hcd, pdev); | ||
222 | return 0; | ||
223 | } | ||
224 | /*TBD*/ | ||
225 | /*static int ohci_hcd_lh7a404_drv_suspend(struct platform_device *dev) | ||
226 | { | ||
227 | struct usb_hcd *hcd = platform_get_drvdata(dev); | ||
228 | |||
229 | return 0; | ||
230 | } | ||
231 | static int ohci_hcd_lh7a404_drv_resume(struct platform_device *dev) | ||
232 | { | ||
233 | struct usb_hcd *hcd = platform_get_drvdata(dev); | ||
234 | |||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | */ | ||
239 | |||
240 | static struct platform_driver ohci_hcd_lh7a404_driver = { | ||
241 | .probe = ohci_hcd_lh7a404_drv_probe, | ||
242 | .remove = ohci_hcd_lh7a404_drv_remove, | ||
243 | .shutdown = usb_hcd_platform_shutdown, | ||
244 | /*.suspend = ohci_hcd_lh7a404_drv_suspend, */ | ||
245 | /*.resume = ohci_hcd_lh7a404_drv_resume, */ | ||
246 | .driver = { | ||
247 | .name = "lh7a404-ohci", | ||
248 | .owner = THIS_MODULE, | ||
249 | }, | ||
250 | }; | ||
251 | |||
252 | MODULE_ALIAS("platform:lh7a404-ohci"); | ||
diff --git a/drivers/usb/host/ohci-octeon.c b/drivers/usb/host/ohci-octeon.c new file mode 100644 index 000000000000..e4ddfaf8870f --- /dev/null +++ b/drivers/usb/host/ohci-octeon.c | |||
@@ -0,0 +1,214 @@ | |||
1 | /* | ||
2 | * EHCI HCD glue for Cavium Octeon II SOCs. | ||
3 | * | ||
4 | * Loosely based on ehci-au1xxx.c | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | * | ||
10 | * Copyright (C) 2010 Cavium Networks | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/platform_device.h> | ||
15 | |||
16 | #include <asm/octeon/octeon.h> | ||
17 | #include <asm/octeon/cvmx-uctlx-defs.h> | ||
18 | |||
19 | #define OCTEON_OHCI_HCD_NAME "octeon-ohci" | ||
20 | |||
21 | /* Common clock init code. */ | ||
22 | void octeon2_usb_clocks_start(void); | ||
23 | void octeon2_usb_clocks_stop(void); | ||
24 | |||
25 | static void ohci_octeon_hw_start(void) | ||
26 | { | ||
27 | union cvmx_uctlx_ohci_ctl ohci_ctl; | ||
28 | |||
29 | octeon2_usb_clocks_start(); | ||
30 | |||
31 | ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); | ||
32 | ohci_ctl.s.l2c_addr_msb = 0; | ||
33 | ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ | ||
34 | ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ | ||
35 | cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); | ||
36 | |||
37 | } | ||
38 | |||
39 | static void ohci_octeon_hw_stop(void) | ||
40 | { | ||
41 | /* Undo ohci_octeon_start() */ | ||
42 | octeon2_usb_clocks_stop(); | ||
43 | } | ||
44 | |||
45 | static int __devinit ohci_octeon_start(struct usb_hcd *hcd) | ||
46 | { | ||
47 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | ||
48 | int ret; | ||
49 | |||
50 | ret = ohci_init(ohci); | ||
51 | |||
52 | if (ret < 0) | ||
53 | return ret; | ||
54 | |||
55 | ret = ohci_run(ohci); | ||
56 | |||
57 | if (ret < 0) { | ||
58 | ohci_err(ohci, "can't start %s", hcd->self.bus_name); | ||
59 | ohci_stop(hcd); | ||
60 | return ret; | ||
61 | } | ||
62 | |||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | static const struct hc_driver ohci_octeon_hc_driver = { | ||
67 | .description = hcd_name, | ||
68 | .product_desc = "Octeon OHCI", | ||
69 | .hcd_priv_size = sizeof(struct ohci_hcd), | ||
70 | |||
71 | /* | ||
72 | * generic hardware linkage | ||
73 | */ | ||
74 | .irq = ohci_irq, | ||
75 | .flags = HCD_USB11 | HCD_MEMORY, | ||
76 | |||
77 | /* | ||
78 | * basic lifecycle operations | ||
79 | */ | ||
80 | .start = ohci_octeon_start, | ||
81 | .stop = ohci_stop, | ||
82 | .shutdown = ohci_shutdown, | ||
83 | |||
84 | /* | ||
85 | * managing i/o requests and associated device resources | ||
86 | */ | ||
87 | .urb_enqueue = ohci_urb_enqueue, | ||
88 | .urb_dequeue = ohci_urb_dequeue, | ||
89 | .endpoint_disable = ohci_endpoint_disable, | ||
90 | |||
91 | /* | ||
92 | * scheduling support | ||
93 | */ | ||
94 | .get_frame_number = ohci_get_frame, | ||
95 | |||
96 | /* | ||
97 | * root hub support | ||
98 | */ | ||
99 | .hub_status_data = ohci_hub_status_data, | ||
100 | .hub_control = ohci_hub_control, | ||
101 | |||
102 | .start_port_reset = ohci_start_port_reset, | ||
103 | }; | ||
104 | |||
105 | static int ohci_octeon_drv_probe(struct platform_device *pdev) | ||
106 | { | ||
107 | struct usb_hcd *hcd; | ||
108 | struct ohci_hcd *ohci; | ||
109 | void *reg_base; | ||
110 | struct resource *res_mem; | ||
111 | int irq; | ||
112 | int ret; | ||
113 | |||
114 | if (usb_disabled()) | ||
115 | return -ENODEV; | ||
116 | |||
117 | irq = platform_get_irq(pdev, 0); | ||
118 | if (irq < 0) { | ||
119 | dev_err(&pdev->dev, "No irq assigned\n"); | ||
120 | return -ENODEV; | ||
121 | } | ||
122 | |||
123 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
124 | if (res_mem == NULL) { | ||
125 | dev_err(&pdev->dev, "No register space assigned\n"); | ||
126 | return -ENODEV; | ||
127 | } | ||
128 | |||
129 | /* Ohci is a 32-bit device. */ | ||
130 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | ||
131 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | ||
132 | |||
133 | hcd = usb_create_hcd(&ohci_octeon_hc_driver, &pdev->dev, "octeon"); | ||
134 | if (!hcd) | ||
135 | return -ENOMEM; | ||
136 | |||
137 | hcd->rsrc_start = res_mem->start; | ||
138 | hcd->rsrc_len = res_mem->end - res_mem->start + 1; | ||
139 | |||
140 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, | ||
141 | OCTEON_OHCI_HCD_NAME)) { | ||
142 | dev_err(&pdev->dev, "request_mem_region failed\n"); | ||
143 | ret = -EBUSY; | ||
144 | goto err1; | ||
145 | } | ||
146 | |||
147 | reg_base = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
148 | if (!reg_base) { | ||
149 | dev_err(&pdev->dev, "ioremap failed\n"); | ||
150 | ret = -ENOMEM; | ||
151 | goto err2; | ||
152 | } | ||
153 | |||
154 | ohci_octeon_hw_start(); | ||
155 | |||
156 | hcd->regs = reg_base; | ||
157 | |||
158 | ohci = hcd_to_ohci(hcd); | ||
159 | |||
160 | /* Octeon OHCI matches CPU endianness. */ | ||
161 | #ifdef __BIG_ENDIAN | ||
162 | ohci->flags |= OHCI_QUIRK_BE_MMIO; | ||
163 | #endif | ||
164 | |||
165 | ohci_hcd_init(ohci); | ||
166 | |||
167 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | ||
168 | if (ret) { | ||
169 | dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); | ||
170 | goto err3; | ||
171 | } | ||
172 | |||
173 | platform_set_drvdata(pdev, hcd); | ||
174 | |||
175 | return 0; | ||
176 | |||
177 | err3: | ||
178 | ohci_octeon_hw_stop(); | ||
179 | |||
180 | iounmap(hcd->regs); | ||
181 | err2: | ||
182 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
183 | err1: | ||
184 | usb_put_hcd(hcd); | ||
185 | return ret; | ||
186 | } | ||
187 | |||
188 | static int ohci_octeon_drv_remove(struct platform_device *pdev) | ||
189 | { | ||
190 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
191 | |||
192 | usb_remove_hcd(hcd); | ||
193 | |||
194 | ohci_octeon_hw_stop(); | ||
195 | iounmap(hcd->regs); | ||
196 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
197 | usb_put_hcd(hcd); | ||
198 | |||
199 | platform_set_drvdata(pdev, NULL); | ||
200 | |||
201 | return 0; | ||
202 | } | ||
203 | |||
204 | static struct platform_driver ohci_octeon_driver = { | ||
205 | .probe = ohci_octeon_drv_probe, | ||
206 | .remove = ohci_octeon_drv_remove, | ||
207 | .shutdown = usb_hcd_platform_shutdown, | ||
208 | .driver = { | ||
209 | .name = OCTEON_OHCI_HCD_NAME, | ||
210 | .owner = THIS_MODULE, | ||
211 | } | ||
212 | }; | ||
213 | |||
214 | MODULE_ALIAS("platform:" OCTEON_OHCI_HCD_NAME); | ||
diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c index 2cc8a504b18c..6048f2f64f73 100644 --- a/drivers/usb/host/ohci-omap3.c +++ b/drivers/usb/host/ohci-omap3.c | |||
@@ -7,6 +7,7 @@ | |||
7 | * Copyright (C) 2007-2010 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
8 | * Author: Vikram Pandita <vikram.pandita@ti.com> | 8 | * Author: Vikram Pandita <vikram.pandita@ti.com> |
9 | * Author: Anand Gadiyar <gadiyar@ti.com> | 9 | * Author: Anand Gadiyar <gadiyar@ti.com> |
10 | * Author: Keshava Munegowda <keshava_mgowda@ti.com> | ||
10 | * | 11 | * |
11 | * Based on ehci-omap.c and some other ohci glue layers | 12 | * Based on ehci-omap.c and some other ohci glue layers |
12 | * | 13 | * |
@@ -24,150 +25,15 @@ | |||
24 | * along with this program; if not, write to the Free Software | 25 | * along with this program; if not, write to the Free Software |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
26 | * | 27 | * |
27 | * TODO (last updated Mar 10th, 2010): | 28 | * TODO (last updated Feb 27, 2011): |
28 | * - add kernel-doc | 29 | * - add kernel-doc |
29 | * - Factor out code common to EHCI to a separate file | ||
30 | * - Make EHCI and OHCI coexist together | ||
31 | * - needs newer silicon versions to actually work | ||
32 | * - the last one to be loaded currently steps on the other's toes | ||
33 | * - Add hooks for configuring transceivers, etc. at init/exit | ||
34 | * - Add aggressive clock-management code | ||
35 | */ | 30 | */ |
36 | 31 | ||
37 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
38 | #include <linux/clk.h> | ||
39 | |||
40 | #include <plat/usb.h> | 33 | #include <plat/usb.h> |
41 | 34 | ||
42 | /* | ||
43 | * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES | ||
44 | * Use ohci_omap_readl()/ohci_omap_writel() functions | ||
45 | */ | ||
46 | |||
47 | /* TLL Register Set */ | ||
48 | #define OMAP_USBTLL_REVISION (0x00) | ||
49 | #define OMAP_USBTLL_SYSCONFIG (0x10) | ||
50 | #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) | ||
51 | #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) | ||
52 | #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) | ||
53 | #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) | ||
54 | #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) | ||
55 | |||
56 | #define OMAP_USBTLL_SYSSTATUS (0x14) | ||
57 | #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) | ||
58 | |||
59 | #define OMAP_USBTLL_IRQSTATUS (0x18) | ||
60 | #define OMAP_USBTLL_IRQENABLE (0x1C) | ||
61 | |||
62 | #define OMAP_TLL_SHARED_CONF (0x30) | ||
63 | #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) | ||
64 | #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) | ||
65 | #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) | ||
66 | #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) | ||
67 | #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) | ||
68 | |||
69 | #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) | ||
70 | #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 | ||
71 | #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) | ||
72 | #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) | ||
73 | #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) | ||
74 | #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) | ||
75 | #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) | ||
76 | #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) | ||
77 | |||
78 | #define OMAP_TLL_CHANNEL_COUNT 3 | ||
79 | |||
80 | /* UHH Register Set */ | ||
81 | #define OMAP_UHH_REVISION (0x00) | ||
82 | #define OMAP_UHH_SYSCONFIG (0x10) | ||
83 | #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) | ||
84 | #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) | ||
85 | #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) | ||
86 | #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) | ||
87 | #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) | ||
88 | #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) | ||
89 | |||
90 | #define OMAP_UHH_SYSSTATUS (0x14) | ||
91 | #define OMAP_UHH_SYSSTATUS_UHHRESETDONE (1 << 0) | ||
92 | #define OMAP_UHH_SYSSTATUS_OHCIRESETDONE (1 << 1) | ||
93 | #define OMAP_UHH_SYSSTATUS_EHCIRESETDONE (1 << 2) | ||
94 | #define OMAP_UHH_HOSTCONFIG (0x40) | ||
95 | #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) | ||
96 | #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) | ||
97 | #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) | ||
98 | #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) | ||
99 | #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) | ||
100 | #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) | ||
101 | #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) | ||
102 | #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) | ||
103 | #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) | ||
104 | #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) | ||
105 | #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) | ||
106 | |||
107 | #define OMAP_UHH_DEBUG_CSR (0x44) | ||
108 | |||
109 | /*-------------------------------------------------------------------------*/ | 35 | /*-------------------------------------------------------------------------*/ |
110 | 36 | ||
111 | static inline void ohci_omap_writel(void __iomem *base, u32 reg, u32 val) | ||
112 | { | ||
113 | __raw_writel(val, base + reg); | ||
114 | } | ||
115 | |||
116 | static inline u32 ohci_omap_readl(void __iomem *base, u32 reg) | ||
117 | { | ||
118 | return __raw_readl(base + reg); | ||
119 | } | ||
120 | |||
121 | static inline void ohci_omap_writeb(void __iomem *base, u8 reg, u8 val) | ||
122 | { | ||
123 | __raw_writeb(val, base + reg); | ||
124 | } | ||
125 | |||
126 | static inline u8 ohci_omap_readb(void __iomem *base, u8 reg) | ||
127 | { | ||
128 | return __raw_readb(base + reg); | ||
129 | } | ||
130 | |||
131 | /*-------------------------------------------------------------------------*/ | ||
132 | |||
133 | struct ohci_hcd_omap3 { | ||
134 | struct ohci_hcd *ohci; | ||
135 | struct device *dev; | ||
136 | |||
137 | struct clk *usbhost_ick; | ||
138 | struct clk *usbhost2_120m_fck; | ||
139 | struct clk *usbhost1_48m_fck; | ||
140 | struct clk *usbtll_fck; | ||
141 | struct clk *usbtll_ick; | ||
142 | |||
143 | /* port_mode: TLL/PHY, 2/3/4/6-PIN, DP-DM/DAT-SE0 */ | ||
144 | enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS]; | ||
145 | void __iomem *uhh_base; | ||
146 | void __iomem *tll_base; | ||
147 | void __iomem *ohci_base; | ||
148 | |||
149 | unsigned es2_compatibility:1; | ||
150 | }; | ||
151 | |||
152 | /*-------------------------------------------------------------------------*/ | ||
153 | |||
154 | static void ohci_omap3_clock_power(struct ohci_hcd_omap3 *omap, int on) | ||
155 | { | ||
156 | if (on) { | ||
157 | clk_enable(omap->usbtll_ick); | ||
158 | clk_enable(omap->usbtll_fck); | ||
159 | clk_enable(omap->usbhost_ick); | ||
160 | clk_enable(omap->usbhost1_48m_fck); | ||
161 | clk_enable(omap->usbhost2_120m_fck); | ||
162 | } else { | ||
163 | clk_disable(omap->usbhost2_120m_fck); | ||
164 | clk_disable(omap->usbhost1_48m_fck); | ||
165 | clk_disable(omap->usbhost_ick); | ||
166 | clk_disable(omap->usbtll_fck); | ||
167 | clk_disable(omap->usbtll_ick); | ||
168 | } | ||
169 | } | ||
170 | |||
171 | static int ohci_omap3_init(struct usb_hcd *hcd) | 37 | static int ohci_omap3_init(struct usb_hcd *hcd) |
172 | { | 38 | { |
173 | dev_dbg(hcd->self.controller, "starting OHCI controller\n"); | 39 | dev_dbg(hcd->self.controller, "starting OHCI controller\n"); |
@@ -175,7 +41,6 @@ static int ohci_omap3_init(struct usb_hcd *hcd) | |||
175 | return ohci_init(hcd_to_ohci(hcd)); | 41 | return ohci_init(hcd_to_ohci(hcd)); |
176 | } | 42 | } |
177 | 43 | ||
178 | |||
179 | /*-------------------------------------------------------------------------*/ | 44 | /*-------------------------------------------------------------------------*/ |
180 | 45 | ||
181 | static int ohci_omap3_start(struct usb_hcd *hcd) | 46 | static int ohci_omap3_start(struct usb_hcd *hcd) |
@@ -202,325 +67,6 @@ static int ohci_omap3_start(struct usb_hcd *hcd) | |||
202 | 67 | ||
203 | /*-------------------------------------------------------------------------*/ | 68 | /*-------------------------------------------------------------------------*/ |
204 | 69 | ||
205 | /* | ||
206 | * convert the port-mode enum to a value we can use in the FSLSMODE | ||
207 | * field of USBTLL_CHANNEL_CONF | ||
208 | */ | ||
209 | static unsigned ohci_omap3_fslsmode(enum ohci_omap3_port_mode mode) | ||
210 | { | ||
211 | switch (mode) { | ||
212 | case OMAP_OHCI_PORT_MODE_UNUSED: | ||
213 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | ||
214 | return 0x0; | ||
215 | |||
216 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | ||
217 | return 0x1; | ||
218 | |||
219 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | ||
220 | return 0x2; | ||
221 | |||
222 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | ||
223 | return 0x3; | ||
224 | |||
225 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | ||
226 | return 0x4; | ||
227 | |||
228 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | ||
229 | return 0x5; | ||
230 | |||
231 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | ||
232 | return 0x6; | ||
233 | |||
234 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | ||
235 | return 0x7; | ||
236 | |||
237 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | ||
238 | return 0xA; | ||
239 | |||
240 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | ||
241 | return 0xB; | ||
242 | default: | ||
243 | pr_warning("Invalid port mode, using default\n"); | ||
244 | return 0x0; | ||
245 | } | ||
246 | } | ||
247 | |||
248 | static void ohci_omap3_tll_config(struct ohci_hcd_omap3 *omap) | ||
249 | { | ||
250 | u32 reg; | ||
251 | int i; | ||
252 | |||
253 | /* Program TLL SHARED CONF */ | ||
254 | reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF); | ||
255 | reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; | ||
256 | reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; | ||
257 | reg |= OMAP_TLL_SHARED_CONF_USB_DIVRATION; | ||
258 | reg |= OMAP_TLL_SHARED_CONF_FCLK_IS_ON; | ||
259 | ohci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); | ||
260 | |||
261 | /* Program each TLL channel */ | ||
262 | /* | ||
263 | * REVISIT: Only the 3-pin and 4-pin PHY modes have | ||
264 | * actually been tested. | ||
265 | */ | ||
266 | for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { | ||
267 | |||
268 | /* Enable only those channels that are actually used */ | ||
269 | if (omap->port_mode[i] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
270 | continue; | ||
271 | |||
272 | reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); | ||
273 | reg |= ohci_omap3_fslsmode(omap->port_mode[i]) | ||
274 | << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; | ||
275 | reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; | ||
276 | reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; | ||
277 | ohci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); | ||
278 | } | ||
279 | } | ||
280 | |||
281 | /* omap3_start_ohci | ||
282 | * - Start the TI USBHOST controller | ||
283 | */ | ||
284 | static int omap3_start_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd) | ||
285 | { | ||
286 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | ||
287 | u32 reg = 0; | ||
288 | int ret = 0; | ||
289 | |||
290 | dev_dbg(omap->dev, "starting TI OHCI USB Controller\n"); | ||
291 | |||
292 | /* Get all the clock handles we need */ | ||
293 | omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); | ||
294 | if (IS_ERR(omap->usbhost_ick)) { | ||
295 | dev_err(omap->dev, "could not get usbhost_ick\n"); | ||
296 | ret = PTR_ERR(omap->usbhost_ick); | ||
297 | goto err_host_ick; | ||
298 | } | ||
299 | |||
300 | omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck"); | ||
301 | if (IS_ERR(omap->usbhost2_120m_fck)) { | ||
302 | dev_err(omap->dev, "could not get usbhost_120m_fck\n"); | ||
303 | ret = PTR_ERR(omap->usbhost2_120m_fck); | ||
304 | goto err_host_120m_fck; | ||
305 | } | ||
306 | |||
307 | omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck"); | ||
308 | if (IS_ERR(omap->usbhost1_48m_fck)) { | ||
309 | dev_err(omap->dev, "could not get usbhost_48m_fck\n"); | ||
310 | ret = PTR_ERR(omap->usbhost1_48m_fck); | ||
311 | goto err_host_48m_fck; | ||
312 | } | ||
313 | |||
314 | omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); | ||
315 | if (IS_ERR(omap->usbtll_fck)) { | ||
316 | dev_err(omap->dev, "could not get usbtll_fck\n"); | ||
317 | ret = PTR_ERR(omap->usbtll_fck); | ||
318 | goto err_tll_fck; | ||
319 | } | ||
320 | |||
321 | omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); | ||
322 | if (IS_ERR(omap->usbtll_ick)) { | ||
323 | dev_err(omap->dev, "could not get usbtll_ick\n"); | ||
324 | ret = PTR_ERR(omap->usbtll_ick); | ||
325 | goto err_tll_ick; | ||
326 | } | ||
327 | |||
328 | /* Now enable all the clocks in the correct order */ | ||
329 | ohci_omap3_clock_power(omap, 1); | ||
330 | |||
331 | /* perform TLL soft reset, and wait until reset is complete */ | ||
332 | ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, | ||
333 | OMAP_USBTLL_SYSCONFIG_SOFTRESET); | ||
334 | |||
335 | /* Wait for TLL reset to complete */ | ||
336 | while (!(ohci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) | ||
337 | & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { | ||
338 | cpu_relax(); | ||
339 | |||
340 | if (time_after(jiffies, timeout)) { | ||
341 | dev_dbg(omap->dev, "operation timed out\n"); | ||
342 | ret = -EINVAL; | ||
343 | goto err_sys_status; | ||
344 | } | ||
345 | } | ||
346 | |||
347 | dev_dbg(omap->dev, "TLL reset done\n"); | ||
348 | |||
349 | /* (1<<3) = no idle mode only for initial debugging */ | ||
350 | ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, | ||
351 | OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | | ||
352 | OMAP_USBTLL_SYSCONFIG_SIDLEMODE | | ||
353 | OMAP_USBTLL_SYSCONFIG_CACTIVITY); | ||
354 | |||
355 | |||
356 | /* Put UHH in NoIdle/NoStandby mode */ | ||
357 | reg = ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); | ||
358 | reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP | ||
359 | | OMAP_UHH_SYSCONFIG_SIDLEMODE | ||
360 | | OMAP_UHH_SYSCONFIG_CACTIVITY | ||
361 | | OMAP_UHH_SYSCONFIG_MIDLEMODE); | ||
362 | reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; | ||
363 | reg &= ~OMAP_UHH_SYSCONFIG_SOFTRESET; | ||
364 | |||
365 | ohci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); | ||
366 | |||
367 | reg = ohci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG); | ||
368 | |||
369 | /* setup ULPI bypass and burst configurations */ | ||
370 | reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | ||
371 | | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | ||
372 | | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); | ||
373 | reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; | ||
374 | |||
375 | /* | ||
376 | * REVISIT: Pi_CONNECT_STATUS controls MStandby | ||
377 | * assertion and Swakeup generation - let us not | ||
378 | * worry about this for now. OMAP HWMOD framework | ||
379 | * might take care of this later. If not, we can | ||
380 | * update these registers when adding aggressive | ||
381 | * clock management code. | ||
382 | * | ||
383 | * For now, turn off all the Pi_CONNECT_STATUS bits | ||
384 | * | ||
385 | if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
386 | reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; | ||
387 | if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
388 | reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; | ||
389 | if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
390 | reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; | ||
391 | */ | ||
392 | reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; | ||
393 | reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; | ||
394 | reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; | ||
395 | |||
396 | if (omap->es2_compatibility) { | ||
397 | /* | ||
398 | * All OHCI modes need to go through the TLL, | ||
399 | * unlike in the EHCI case. So use UTMI mode | ||
400 | * for all ports for OHCI, on ES2.x silicon | ||
401 | */ | ||
402 | dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n"); | ||
403 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; | ||
404 | } else { | ||
405 | dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); | ||
406 | if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
407 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | ||
408 | else | ||
409 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | ||
410 | |||
411 | if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
412 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; | ||
413 | else | ||
414 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; | ||
415 | |||
416 | if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED) | ||
417 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; | ||
418 | else | ||
419 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; | ||
420 | |||
421 | } | ||
422 | ohci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); | ||
423 | dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg); | ||
424 | |||
425 | ohci_omap3_tll_config(omap); | ||
426 | |||
427 | return 0; | ||
428 | |||
429 | err_sys_status: | ||
430 | ohci_omap3_clock_power(omap, 0); | ||
431 | clk_put(omap->usbtll_ick); | ||
432 | |||
433 | err_tll_ick: | ||
434 | clk_put(omap->usbtll_fck); | ||
435 | |||
436 | err_tll_fck: | ||
437 | clk_put(omap->usbhost1_48m_fck); | ||
438 | |||
439 | err_host_48m_fck: | ||
440 | clk_put(omap->usbhost2_120m_fck); | ||
441 | |||
442 | err_host_120m_fck: | ||
443 | clk_put(omap->usbhost_ick); | ||
444 | |||
445 | err_host_ick: | ||
446 | return ret; | ||
447 | } | ||
448 | |||
449 | static void omap3_stop_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd) | ||
450 | { | ||
451 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | ||
452 | |||
453 | dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n"); | ||
454 | |||
455 | /* Reset USBHOST for insmod/rmmod to work */ | ||
456 | ohci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, | ||
457 | OMAP_UHH_SYSCONFIG_SOFTRESET); | ||
458 | while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) | ||
459 | & OMAP_UHH_SYSSTATUS_UHHRESETDONE)) { | ||
460 | cpu_relax(); | ||
461 | |||
462 | if (time_after(jiffies, timeout)) | ||
463 | dev_dbg(omap->dev, "operation timed out\n"); | ||
464 | } | ||
465 | |||
466 | while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) | ||
467 | & OMAP_UHH_SYSSTATUS_OHCIRESETDONE)) { | ||
468 | cpu_relax(); | ||
469 | |||
470 | if (time_after(jiffies, timeout)) | ||
471 | dev_dbg(omap->dev, "operation timed out\n"); | ||
472 | } | ||
473 | |||
474 | while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) | ||
475 | & OMAP_UHH_SYSSTATUS_EHCIRESETDONE)) { | ||
476 | cpu_relax(); | ||
477 | |||
478 | if (time_after(jiffies, timeout)) | ||
479 | dev_dbg(omap->dev, "operation timed out\n"); | ||
480 | } | ||
481 | |||
482 | ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); | ||
483 | |||
484 | while (!(ohci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) | ||
485 | & (1 << 0))) { | ||
486 | cpu_relax(); | ||
487 | |||
488 | if (time_after(jiffies, timeout)) | ||
489 | dev_dbg(omap->dev, "operation timed out\n"); | ||
490 | } | ||
491 | |||
492 | ohci_omap3_clock_power(omap, 0); | ||
493 | |||
494 | if (omap->usbtll_fck != NULL) { | ||
495 | clk_put(omap->usbtll_fck); | ||
496 | omap->usbtll_fck = NULL; | ||
497 | } | ||
498 | |||
499 | if (omap->usbhost_ick != NULL) { | ||
500 | clk_put(omap->usbhost_ick); | ||
501 | omap->usbhost_ick = NULL; | ||
502 | } | ||
503 | |||
504 | if (omap->usbhost1_48m_fck != NULL) { | ||
505 | clk_put(omap->usbhost1_48m_fck); | ||
506 | omap->usbhost1_48m_fck = NULL; | ||
507 | } | ||
508 | |||
509 | if (omap->usbhost2_120m_fck != NULL) { | ||
510 | clk_put(omap->usbhost2_120m_fck); | ||
511 | omap->usbhost2_120m_fck = NULL; | ||
512 | } | ||
513 | |||
514 | if (omap->usbtll_ick != NULL) { | ||
515 | clk_put(omap->usbtll_ick); | ||
516 | omap->usbtll_ick = NULL; | ||
517 | } | ||
518 | |||
519 | dev_dbg(omap->dev, "Clock to USB host has been disabled\n"); | ||
520 | } | ||
521 | |||
522 | /*-------------------------------------------------------------------------*/ | ||
523 | |||
524 | static const struct hc_driver ohci_omap3_hc_driver = { | 70 | static const struct hc_driver ohci_omap3_hc_driver = { |
525 | .description = hcd_name, | 71 | .description = hcd_name, |
526 | .product_desc = "OMAP3 OHCI Host Controller", | 72 | .product_desc = "OMAP3 OHCI Host Controller", |
@@ -580,107 +126,77 @@ static const struct hc_driver ohci_omap3_hc_driver = { | |||
580 | */ | 126 | */ |
581 | static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev) | 127 | static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev) |
582 | { | 128 | { |
583 | struct ohci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; | 129 | struct device *dev = &pdev->dev; |
584 | struct ohci_hcd_omap3 *omap; | 130 | struct usb_hcd *hcd = NULL; |
585 | struct resource *res; | 131 | void __iomem *regs = NULL; |
586 | struct usb_hcd *hcd; | 132 | struct resource *res; |
587 | int ret = -ENODEV; | 133 | int ret = -ENODEV; |
588 | int irq; | 134 | int irq; |
589 | 135 | ||
590 | if (usb_disabled()) | 136 | if (usb_disabled()) |
591 | goto err_disabled; | 137 | goto err_end; |
592 | 138 | ||
593 | if (!pdata) { | 139 | if (!dev->parent) { |
594 | dev_dbg(&pdev->dev, "missing platform_data\n"); | 140 | dev_err(dev, "Missing parent device\n"); |
595 | goto err_pdata; | 141 | return -ENODEV; |
596 | } | 142 | } |
597 | 143 | ||
598 | irq = platform_get_irq(pdev, 0); | 144 | irq = platform_get_irq_byname(pdev, "ohci-irq"); |
145 | if (irq < 0) { | ||
146 | dev_err(dev, "OHCI irq failed\n"); | ||
147 | return -ENODEV; | ||
148 | } | ||
599 | 149 | ||
600 | omap = kzalloc(sizeof(*omap), GFP_KERNEL); | 150 | res = platform_get_resource_byname(pdev, |
601 | if (!omap) { | 151 | IORESOURCE_MEM, "ohci"); |
602 | ret = -ENOMEM; | 152 | if (!ret) { |
603 | goto err_disabled; | 153 | dev_err(dev, "UHH OHCI get resource failed\n"); |
154 | return -ENOMEM; | ||
604 | } | 155 | } |
605 | 156 | ||
606 | hcd = usb_create_hcd(&ohci_omap3_hc_driver, &pdev->dev, | 157 | regs = ioremap(res->start, resource_size(res)); |
607 | dev_name(&pdev->dev)); | 158 | if (!regs) { |
608 | if (!hcd) { | 159 | dev_err(dev, "UHH OHCI ioremap failed\n"); |
609 | ret = -ENOMEM; | 160 | return -ENOMEM; |
610 | goto err_create_hcd; | ||
611 | } | 161 | } |
612 | 162 | ||
613 | platform_set_drvdata(pdev, omap); | ||
614 | omap->dev = &pdev->dev; | ||
615 | omap->port_mode[0] = pdata->port_mode[0]; | ||
616 | omap->port_mode[1] = pdata->port_mode[1]; | ||
617 | omap->port_mode[2] = pdata->port_mode[2]; | ||
618 | omap->es2_compatibility = pdata->es2_compatibility; | ||
619 | omap->ohci = hcd_to_ohci(hcd); | ||
620 | 163 | ||
621 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 164 | hcd = usb_create_hcd(&ohci_omap3_hc_driver, dev, |
165 | dev_name(dev)); | ||
166 | if (!hcd) { | ||
167 | dev_err(dev, "usb_create_hcd failed\n"); | ||
168 | goto err_io; | ||
169 | } | ||
622 | 170 | ||
623 | hcd->rsrc_start = res->start; | 171 | hcd->rsrc_start = res->start; |
624 | hcd->rsrc_len = resource_size(res); | 172 | hcd->rsrc_len = resource_size(res); |
173 | hcd->regs = regs; | ||
625 | 174 | ||
626 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | 175 | ret = omap_usbhs_enable(dev); |
627 | if (!hcd->regs) { | ||
628 | dev_err(&pdev->dev, "OHCI ioremap failed\n"); | ||
629 | ret = -ENOMEM; | ||
630 | goto err_ioremap; | ||
631 | } | ||
632 | |||
633 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
634 | omap->uhh_base = ioremap(res->start, resource_size(res)); | ||
635 | if (!omap->uhh_base) { | ||
636 | dev_err(&pdev->dev, "UHH ioremap failed\n"); | ||
637 | ret = -ENOMEM; | ||
638 | goto err_uhh_ioremap; | ||
639 | } | ||
640 | |||
641 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | ||
642 | omap->tll_base = ioremap(res->start, resource_size(res)); | ||
643 | if (!omap->tll_base) { | ||
644 | dev_err(&pdev->dev, "TLL ioremap failed\n"); | ||
645 | ret = -ENOMEM; | ||
646 | goto err_tll_ioremap; | ||
647 | } | ||
648 | |||
649 | ret = omap3_start_ohci(omap, hcd); | ||
650 | if (ret) { | 176 | if (ret) { |
651 | dev_dbg(&pdev->dev, "failed to start ehci\n"); | 177 | dev_dbg(dev, "failed to start ohci\n"); |
652 | goto err_start; | 178 | goto err_end; |
653 | } | 179 | } |
654 | 180 | ||
655 | ohci_hcd_init(omap->ohci); | 181 | ohci_hcd_init(hcd_to_ohci(hcd)); |
656 | 182 | ||
657 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); | 183 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); |
658 | if (ret) { | 184 | if (ret) { |
659 | dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); | 185 | dev_dbg(dev, "failed to add hcd with err %d\n", ret); |
660 | goto err_add_hcd; | 186 | goto err_add_hcd; |
661 | } | 187 | } |
662 | 188 | ||
663 | return 0; | 189 | return 0; |
664 | 190 | ||
665 | err_add_hcd: | 191 | err_add_hcd: |
666 | omap3_stop_ohci(omap, hcd); | 192 | omap_usbhs_disable(dev); |
667 | |||
668 | err_start: | ||
669 | iounmap(omap->tll_base); | ||
670 | |||
671 | err_tll_ioremap: | ||
672 | iounmap(omap->uhh_base); | ||
673 | |||
674 | err_uhh_ioremap: | ||
675 | iounmap(hcd->regs); | ||
676 | 193 | ||
677 | err_ioremap: | 194 | err_end: |
678 | usb_put_hcd(hcd); | 195 | usb_put_hcd(hcd); |
679 | 196 | ||
680 | err_create_hcd: | 197 | err_io: |
681 | kfree(omap); | 198 | iounmap(regs); |
682 | err_pdata: | 199 | |
683 | err_disabled: | ||
684 | return ret; | 200 | return ret; |
685 | } | 201 | } |
686 | 202 | ||
@@ -699,24 +215,20 @@ err_disabled: | |||
699 | */ | 215 | */ |
700 | static int __devexit ohci_hcd_omap3_remove(struct platform_device *pdev) | 216 | static int __devexit ohci_hcd_omap3_remove(struct platform_device *pdev) |
701 | { | 217 | { |
702 | struct ohci_hcd_omap3 *omap = platform_get_drvdata(pdev); | 218 | struct device *dev = &pdev->dev; |
703 | struct usb_hcd *hcd = ohci_to_hcd(omap->ohci); | 219 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
704 | 220 | ||
705 | usb_remove_hcd(hcd); | ||
706 | omap3_stop_ohci(omap, hcd); | ||
707 | iounmap(hcd->regs); | 221 | iounmap(hcd->regs); |
708 | iounmap(omap->tll_base); | 222 | usb_remove_hcd(hcd); |
709 | iounmap(omap->uhh_base); | 223 | omap_usbhs_disable(dev); |
710 | usb_put_hcd(hcd); | 224 | usb_put_hcd(hcd); |
711 | kfree(omap); | ||
712 | 225 | ||
713 | return 0; | 226 | return 0; |
714 | } | 227 | } |
715 | 228 | ||
716 | static void ohci_hcd_omap3_shutdown(struct platform_device *pdev) | 229 | static void ohci_hcd_omap3_shutdown(struct platform_device *pdev) |
717 | { | 230 | { |
718 | struct ohci_hcd_omap3 *omap = platform_get_drvdata(pdev); | 231 | struct usb_hcd *hcd = dev_get_drvdata(&pdev->dev); |
719 | struct usb_hcd *hcd = ohci_to_hcd(omap->ohci); | ||
720 | 232 | ||
721 | if (hcd->driver->shutdown) | 233 | if (hcd->driver->shutdown) |
722 | hcd->driver->shutdown(hcd); | 234 | hcd->driver->shutdown(hcd); |
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c index 6bdc8b25a6a1..ad8166c681e2 100644 --- a/drivers/usb/host/ohci-pci.c +++ b/drivers/usb/host/ohci-pci.c | |||
@@ -22,24 +22,6 @@ | |||
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | 23 | ||
24 | 24 | ||
25 | /* constants used to work around PM-related transfer | ||
26 | * glitches in some AMD 700 series southbridges | ||
27 | */ | ||
28 | #define AB_REG_BAR 0xf0 | ||
29 | #define AB_INDX(addr) ((addr) + 0x00) | ||
30 | #define AB_DATA(addr) ((addr) + 0x04) | ||
31 | #define AX_INDXC 0X30 | ||
32 | #define AX_DATAC 0x34 | ||
33 | |||
34 | #define NB_PCIE_INDX_ADDR 0xe0 | ||
35 | #define NB_PCIE_INDX_DATA 0xe4 | ||
36 | #define PCIE_P_CNTL 0x10040 | ||
37 | #define BIF_NB 0x10002 | ||
38 | |||
39 | static struct pci_dev *amd_smbus_dev; | ||
40 | static struct pci_dev *amd_hb_dev; | ||
41 | static int amd_ohci_iso_count; | ||
42 | |||
43 | /*-------------------------------------------------------------------------*/ | 25 | /*-------------------------------------------------------------------------*/ |
44 | 26 | ||
45 | static int broken_suspend(struct usb_hcd *hcd) | 27 | static int broken_suspend(struct usb_hcd *hcd) |
@@ -168,15 +150,18 @@ static int ohci_quirk_nec(struct usb_hcd *hcd) | |||
168 | static int ohci_quirk_amd700(struct usb_hcd *hcd) | 150 | static int ohci_quirk_amd700(struct usb_hcd *hcd) |
169 | { | 151 | { |
170 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | 152 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
171 | u8 rev = 0; | 153 | struct pci_dev *amd_smbus_dev; |
154 | u8 rev; | ||
172 | 155 | ||
173 | if (!amd_smbus_dev) | 156 | if (usb_amd_find_chipset_info()) |
174 | amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, | 157 | ohci->flags |= OHCI_QUIRK_AMD_PLL; |
175 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); | 158 | |
159 | amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, | ||
160 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); | ||
176 | if (!amd_smbus_dev) | 161 | if (!amd_smbus_dev) |
177 | return 0; | 162 | return 0; |
178 | 163 | ||
179 | pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev); | 164 | rev = amd_smbus_dev->revision; |
180 | 165 | ||
181 | /* SB800 needs pre-fetch fix */ | 166 | /* SB800 needs pre-fetch fix */ |
182 | if ((rev >= 0x40) && (rev <= 0x4f)) { | 167 | if ((rev >= 0x40) && (rev <= 0x4f)) { |
@@ -184,89 +169,32 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd) | |||
184 | ohci_dbg(ohci, "enabled AMD prefetch quirk\n"); | 169 | ohci_dbg(ohci, "enabled AMD prefetch quirk\n"); |
185 | } | 170 | } |
186 | 171 | ||
187 | if ((rev > 0x3b) || (rev < 0x30)) { | 172 | pci_dev_put(amd_smbus_dev); |
188 | pci_dev_put(amd_smbus_dev); | 173 | amd_smbus_dev = NULL; |
189 | amd_smbus_dev = NULL; | ||
190 | return 0; | ||
191 | } | ||
192 | |||
193 | amd_ohci_iso_count++; | ||
194 | |||
195 | if (!amd_hb_dev) | ||
196 | amd_hb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9600, NULL); | ||
197 | |||
198 | ohci->flags |= OHCI_QUIRK_AMD_ISO; | ||
199 | ohci_dbg(ohci, "enabled AMD ISO transfers quirk\n"); | ||
200 | 174 | ||
201 | return 0; | 175 | return 0; |
202 | } | 176 | } |
203 | 177 | ||
204 | /* | 178 | /* nVidia controllers continue to drive Reset signalling on the bus |
205 | * The hardware normally enables the A-link power management feature, which | 179 | * even after system shutdown, wasting power. This flag tells the |
206 | * lets the system lower the power consumption in idle states. | 180 | * shutdown routine to leave the controller OPERATIONAL instead of RESET. |
207 | * | ||
208 | * Assume the system is configured to have USB 1.1 ISO transfers going | ||
209 | * to or from a USB device. Without this quirk, that stream may stutter | ||
210 | * or have breaks occasionally. For transfers going to speakers, this | ||
211 | * makes a very audible mess... | ||
212 | * | ||
213 | * That audio playback corruption is due to the audio stream getting | ||
214 | * interrupted occasionally when the link goes in lower power state | ||
215 | * This USB quirk prevents the link going into that lower power state | ||
216 | * during audio playback or other ISO operations. | ||
217 | */ | 181 | */ |
218 | static void quirk_amd_pll(int on) | 182 | static int ohci_quirk_nvidia_shutdown(struct usb_hcd *hcd) |
219 | { | 183 | { |
220 | u32 addr; | 184 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
221 | u32 val; | 185 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
222 | u32 bit = (on > 0) ? 1 : 0; | ||
223 | |||
224 | pci_read_config_dword(amd_smbus_dev, AB_REG_BAR, &addr); | ||
225 | |||
226 | /* BIT names/meanings are NDA-protected, sorry ... */ | ||
227 | |||
228 | outl(AX_INDXC, AB_INDX(addr)); | ||
229 | outl(0x40, AB_DATA(addr)); | ||
230 | outl(AX_DATAC, AB_INDX(addr)); | ||
231 | val = inl(AB_DATA(addr)); | ||
232 | val &= ~((1 << 3) | (1 << 4) | (1 << 9)); | ||
233 | val |= (bit << 3) | ((!bit) << 4) | ((!bit) << 9); | ||
234 | outl(val, AB_DATA(addr)); | ||
235 | |||
236 | if (amd_hb_dev) { | ||
237 | addr = PCIE_P_CNTL; | ||
238 | pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr); | ||
239 | |||
240 | pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val); | ||
241 | val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); | ||
242 | val |= bit | (bit << 3) | (bit << 12); | ||
243 | val |= ((!bit) << 4) | ((!bit) << 9); | ||
244 | pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val); | ||
245 | |||
246 | addr = BIF_NB; | ||
247 | pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr); | ||
248 | |||
249 | pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val); | ||
250 | val &= ~(1 << 8); | ||
251 | val |= bit << 8; | ||
252 | pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val); | ||
253 | } | ||
254 | } | ||
255 | 186 | ||
256 | static void amd_iso_dev_put(void) | 187 | /* Evidently nVidia fixed their later hardware; this is a guess at |
257 | { | 188 | * the changeover point. |
258 | amd_ohci_iso_count--; | 189 | */ |
259 | if (amd_ohci_iso_count == 0) { | 190 | #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB 0x026d |
260 | if (amd_smbus_dev) { | 191 | |
261 | pci_dev_put(amd_smbus_dev); | 192 | if (pdev->device < PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB) { |
262 | amd_smbus_dev = NULL; | 193 | ohci->flags |= OHCI_QUIRK_SHUTDOWN; |
263 | } | 194 | ohci_dbg(ohci, "enabled nVidia shutdown quirk\n"); |
264 | if (amd_hb_dev) { | ||
265 | pci_dev_put(amd_hb_dev); | ||
266 | amd_hb_dev = NULL; | ||
267 | } | ||
268 | } | 195 | } |
269 | 196 | ||
197 | return 0; | ||
270 | } | 198 | } |
271 | 199 | ||
272 | static void sb800_prefetch(struct ohci_hcd *ohci, int on) | 200 | static void sb800_prefetch(struct ohci_hcd *ohci, int on) |
@@ -332,6 +260,10 @@ static const struct pci_device_id ohci_pci_quirks[] = { | |||
332 | PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399), | 260 | PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399), |
333 | .driver_data = (unsigned long)ohci_quirk_amd700, | 261 | .driver_data = (unsigned long)ohci_quirk_amd700, |
334 | }, | 262 | }, |
263 | { | ||
264 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | ||
265 | .driver_data = (unsigned long) ohci_quirk_nvidia_shutdown, | ||
266 | }, | ||
335 | 267 | ||
336 | /* FIXME for some of the early AMD 760 southbridges, OHCI | 268 | /* FIXME for some of the early AMD 760 southbridges, OHCI |
337 | * won't work at all. blacklist them. | 269 | * won't work at all. blacklist them. |
diff --git a/drivers/usb/host/ohci-ppc-of.c b/drivers/usb/host/ohci-ppc-of.c index b2c2dbf08766..1ca1821320f4 100644 --- a/drivers/usb/host/ohci-ppc-of.c +++ b/drivers/usb/host/ohci-ppc-of.c | |||
@@ -80,8 +80,7 @@ static const struct hc_driver ohci_ppc_of_hc_driver = { | |||
80 | }; | 80 | }; |
81 | 81 | ||
82 | 82 | ||
83 | static int __devinit | 83 | static int __devinit ohci_hcd_ppc_of_probe(struct platform_device *op) |
84 | ohci_hcd_ppc_of_probe(struct platform_device *op, const struct of_device_id *match) | ||
85 | { | 84 | { |
86 | struct device_node *dn = op->dev.of_node; | 85 | struct device_node *dn = op->dev.of_node; |
87 | struct usb_hcd *hcd; | 86 | struct usb_hcd *hcd; |
@@ -201,14 +200,12 @@ static int ohci_hcd_ppc_of_remove(struct platform_device *op) | |||
201 | return 0; | 200 | return 0; |
202 | } | 201 | } |
203 | 202 | ||
204 | static int ohci_hcd_ppc_of_shutdown(struct platform_device *op) | 203 | static void ohci_hcd_ppc_of_shutdown(struct platform_device *op) |
205 | { | 204 | { |
206 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); | 205 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); |
207 | 206 | ||
208 | if (hcd->driver->shutdown) | 207 | if (hcd->driver->shutdown) |
209 | hcd->driver->shutdown(hcd); | 208 | hcd->driver->shutdown(hcd); |
210 | |||
211 | return 0; | ||
212 | } | 209 | } |
213 | 210 | ||
214 | 211 | ||
@@ -243,7 +240,7 @@ MODULE_DEVICE_TABLE(of, ohci_hcd_ppc_of_match); | |||
243 | #endif | 240 | #endif |
244 | 241 | ||
245 | 242 | ||
246 | static struct of_platform_driver ohci_hcd_ppc_of_driver = { | 243 | static struct platform_driver ohci_hcd_ppc_of_driver = { |
247 | .probe = ohci_hcd_ppc_of_probe, | 244 | .probe = ohci_hcd_ppc_of_probe, |
248 | .remove = ohci_hcd_ppc_of_remove, | 245 | .remove = ohci_hcd_ppc_of_remove, |
249 | .shutdown = ohci_hcd_ppc_of_shutdown, | 246 | .shutdown = ohci_hcd_ppc_of_shutdown, |
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index 418163894775..80be5472783a 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | 25 | #include <linux/clk.h> |
26 | #include <mach/ohci.h> | 26 | #include <mach/ohci.h> |
27 | #include <mach/pxa3xx-u2d.h> | ||
27 | 28 | ||
28 | /* | 29 | /* |
29 | * UHC: USB Host Controller (OHCI-like) register definitions | 30 | * UHC: USB Host Controller (OHCI-like) register definitions |
@@ -235,6 +236,9 @@ static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev) | |||
235 | if (retval < 0) | 236 | if (retval < 0) |
236 | return retval; | 237 | return retval; |
237 | 238 | ||
239 | if (cpu_is_pxa3xx()) | ||
240 | pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self); | ||
241 | |||
238 | uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE; | 242 | uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE; |
239 | __raw_writel(uhchr, ohci->mmio_base + UHCHR); | 243 | __raw_writel(uhchr, ohci->mmio_base + UHCHR); |
240 | __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE); | 244 | __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE); |
@@ -251,6 +255,9 @@ static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev) | |||
251 | 255 | ||
252 | inf = dev->platform_data; | 256 | inf = dev->platform_data; |
253 | 257 | ||
258 | if (cpu_is_pxa3xx()) | ||
259 | pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self); | ||
260 | |||
254 | if (inf->exit) | 261 | if (inf->exit) |
255 | inf->exit(dev); | 262 | inf->exit(dev); |
256 | 263 | ||
@@ -305,8 +312,10 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device | |||
305 | return PTR_ERR(usb_clk); | 312 | return PTR_ERR(usb_clk); |
306 | 313 | ||
307 | hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); | 314 | hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); |
308 | if (!hcd) | 315 | if (!hcd) { |
309 | return -ENOMEM; | 316 | retval = -ENOMEM; |
317 | goto err0; | ||
318 | } | ||
310 | 319 | ||
311 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 320 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
312 | if (!r) { | 321 | if (!r) { |
@@ -361,6 +370,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device | |||
361 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | 370 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); |
362 | err1: | 371 | err1: |
363 | usb_put_hcd(hcd); | 372 | usb_put_hcd(hcd); |
373 | err0: | ||
364 | clk_put(usb_clk); | 374 | clk_put(usb_clk); |
365 | return retval; | 375 | return retval; |
366 | } | 376 | } |
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c index 83094d067e0f..dd24fc115e48 100644 --- a/drivers/usb/host/ohci-q.c +++ b/drivers/usb/host/ohci-q.c | |||
@@ -52,7 +52,7 @@ __acquires(ohci->lock) | |||
52 | ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; | 52 | ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; |
53 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { | 53 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { |
54 | if (quirk_amdiso(ohci)) | 54 | if (quirk_amdiso(ohci)) |
55 | quirk_amd_pll(1); | 55 | usb_amd_quirk_pll_enable(); |
56 | if (quirk_amdprefetch(ohci)) | 56 | if (quirk_amdprefetch(ohci)) |
57 | sb800_prefetch(ohci, 0); | 57 | sb800_prefetch(ohci, 0); |
58 | } | 58 | } |
@@ -686,7 +686,7 @@ static void td_submit_urb ( | |||
686 | } | 686 | } |
687 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { | 687 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { |
688 | if (quirk_amdiso(ohci)) | 688 | if (quirk_amdiso(ohci)) |
689 | quirk_amd_pll(0); | 689 | usb_amd_quirk_pll_disable(); |
690 | if (quirk_amdprefetch(ohci)) | 690 | if (quirk_amdprefetch(ohci)) |
691 | sb800_prefetch(ohci, 1); | 691 | sb800_prefetch(ohci, 1); |
692 | } | 692 | } |
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c index a68af2dd55ca..7c9a4d55526b 100644 --- a/drivers/usb/host/ohci-s3c2410.c +++ b/drivers/usb/host/ohci-s3c2410.c | |||
@@ -56,9 +56,8 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd) | |||
56 | info->hcd = hcd; | 56 | info->hcd = hcd; |
57 | info->report_oc = s3c2410_hcd_oc; | 57 | info->report_oc = s3c2410_hcd_oc; |
58 | 58 | ||
59 | if (info->enable_oc != NULL) { | 59 | if (info->enable_oc != NULL) |
60 | (info->enable_oc)(info, 1); | 60 | (info->enable_oc)(info, 1); |
61 | } | ||
62 | } | 61 | } |
63 | } | 62 | } |
64 | 63 | ||
@@ -72,9 +71,8 @@ static void s3c2410_stop_hc(struct platform_device *dev) | |||
72 | info->report_oc = NULL; | 71 | info->report_oc = NULL; |
73 | info->hcd = NULL; | 72 | info->hcd = NULL; |
74 | 73 | ||
75 | if (info->enable_oc != NULL) { | 74 | if (info->enable_oc != NULL) |
76 | (info->enable_oc)(info, 0); | 75 | (info->enable_oc)(info, 0); |
77 | } | ||
78 | } | 76 | } |
79 | 77 | ||
80 | clk_disable(clk); | 78 | clk_disable(clk); |
@@ -88,14 +86,14 @@ static void s3c2410_stop_hc(struct platform_device *dev) | |||
88 | */ | 86 | */ |
89 | 87 | ||
90 | static int | 88 | static int |
91 | ohci_s3c2410_hub_status_data (struct usb_hcd *hcd, char *buf) | 89 | ohci_s3c2410_hub_status_data(struct usb_hcd *hcd, char *buf) |
92 | { | 90 | { |
93 | struct s3c2410_hcd_info *info = to_s3c2410_info(hcd); | 91 | struct s3c2410_hcd_info *info = to_s3c2410_info(hcd); |
94 | struct s3c2410_hcd_port *port; | 92 | struct s3c2410_hcd_port *port; |
95 | int orig; | 93 | int orig; |
96 | int portno; | 94 | int portno; |
97 | 95 | ||
98 | orig = ohci_hub_status_data (hcd, buf); | 96 | orig = ohci_hub_status_data(hcd, buf); |
99 | 97 | ||
100 | if (info == NULL) | 98 | if (info == NULL) |
101 | return orig; | 99 | return orig; |
@@ -145,7 +143,7 @@ static void s3c2410_usb_set_power(struct s3c2410_hcd_info *info, | |||
145 | * request. | 143 | * request. |
146 | */ | 144 | */ |
147 | 145 | ||
148 | static int ohci_s3c2410_hub_control ( | 146 | static int ohci_s3c2410_hub_control( |
149 | struct usb_hcd *hcd, | 147 | struct usb_hcd *hcd, |
150 | u16 typeReq, | 148 | u16 typeReq, |
151 | u16 wValue, | 149 | u16 wValue, |
@@ -199,9 +197,8 @@ static int ohci_s3c2410_hub_control ( | |||
199 | dev_dbg(hcd->self.controller, | 197 | dev_dbg(hcd->self.controller, |
200 | "ClearPortFeature: OVER_CURRENT\n"); | 198 | "ClearPortFeature: OVER_CURRENT\n"); |
201 | 199 | ||
202 | if (valid_port(wIndex)) { | 200 | if (valid_port(wIndex)) |
203 | info->port[wIndex-1].oc_status = 0; | 201 | info->port[wIndex-1].oc_status = 0; |
204 | } | ||
205 | 202 | ||
206 | goto out; | 203 | goto out; |
207 | 204 | ||
@@ -242,8 +239,11 @@ static int ohci_s3c2410_hub_control ( | |||
242 | desc->wHubCharacteristics |= cpu_to_le16(0x0001); | 239 | desc->wHubCharacteristics |= cpu_to_le16(0x0001); |
243 | 240 | ||
244 | if (info->enable_oc) { | 241 | if (info->enable_oc) { |
245 | desc->wHubCharacteristics &= ~cpu_to_le16(HUB_CHAR_OCPM); | 242 | desc->wHubCharacteristics &= ~cpu_to_le16( |
246 | desc->wHubCharacteristics |= cpu_to_le16(0x0008|0x0001); | 243 | HUB_CHAR_OCPM); |
244 | desc->wHubCharacteristics |= cpu_to_le16( | ||
245 | 0x0008 | | ||
246 | 0x0001); | ||
247 | } | 247 | } |
248 | 248 | ||
249 | dev_dbg(hcd->self.controller, "wHubCharacteristics after 0x%04x\n", | 249 | dev_dbg(hcd->self.controller, "wHubCharacteristics after 0x%04x\n", |
@@ -257,13 +257,11 @@ static int ohci_s3c2410_hub_control ( | |||
257 | dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex); | 257 | dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex); |
258 | 258 | ||
259 | if (valid_port(wIndex)) { | 259 | if (valid_port(wIndex)) { |
260 | if (info->port[wIndex-1].oc_changed) { | 260 | if (info->port[wIndex-1].oc_changed) |
261 | *data |= cpu_to_le32(RH_PS_OCIC); | 261 | *data |= cpu_to_le32(RH_PS_OCIC); |
262 | } | ||
263 | 262 | ||
264 | if (info->port[wIndex-1].oc_status) { | 263 | if (info->port[wIndex-1].oc_status) |
265 | *data |= cpu_to_le32(RH_PS_POCI); | 264 | *data |= cpu_to_le32(RH_PS_POCI); |
266 | } | ||
267 | } | 265 | } |
268 | } | 266 | } |
269 | 267 | ||
@@ -321,7 +319,7 @@ static void s3c2410_hcd_oc(struct s3c2410_hcd_info *info, int port_oc) | |||
321 | */ | 319 | */ |
322 | 320 | ||
323 | static void | 321 | static void |
324 | usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev) | 322 | usb_hcd_s3c2410_remove(struct usb_hcd *hcd, struct platform_device *dev) |
325 | { | 323 | { |
326 | usb_remove_hcd(hcd); | 324 | usb_remove_hcd(hcd); |
327 | s3c2410_stop_hc(dev); | 325 | s3c2410_stop_hc(dev); |
@@ -339,7 +337,7 @@ usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev) | |||
339 | * through the hotplug entry's driver_data. | 337 | * through the hotplug entry's driver_data. |
340 | * | 338 | * |
341 | */ | 339 | */ |
342 | static int usb_hcd_s3c2410_probe (const struct hc_driver *driver, | 340 | static int usb_hcd_s3c2410_probe(const struct hc_driver *driver, |
343 | struct platform_device *dev) | 341 | struct platform_device *dev) |
344 | { | 342 | { |
345 | struct usb_hcd *hcd = NULL; | 343 | struct usb_hcd *hcd = NULL; |
@@ -353,7 +351,7 @@ static int usb_hcd_s3c2410_probe (const struct hc_driver *driver, | |||
353 | return -ENOMEM; | 351 | return -ENOMEM; |
354 | 352 | ||
355 | hcd->rsrc_start = dev->resource[0].start; | 353 | hcd->rsrc_start = dev->resource[0].start; |
356 | hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1; | 354 | hcd->rsrc_len = resource_size(&dev->resource[0]); |
357 | 355 | ||
358 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | 356 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { |
359 | dev_err(&dev->dev, "request_mem_region failed\n"); | 357 | dev_err(&dev->dev, "request_mem_region failed\n"); |
@@ -364,14 +362,14 @@ static int usb_hcd_s3c2410_probe (const struct hc_driver *driver, | |||
364 | clk = clk_get(&dev->dev, "usb-host"); | 362 | clk = clk_get(&dev->dev, "usb-host"); |
365 | if (IS_ERR(clk)) { | 363 | if (IS_ERR(clk)) { |
366 | dev_err(&dev->dev, "cannot get usb-host clock\n"); | 364 | dev_err(&dev->dev, "cannot get usb-host clock\n"); |
367 | retval = -ENOENT; | 365 | retval = PTR_ERR(clk); |
368 | goto err_mem; | 366 | goto err_mem; |
369 | } | 367 | } |
370 | 368 | ||
371 | usb_clk = clk_get(&dev->dev, "usb-bus-host"); | 369 | usb_clk = clk_get(&dev->dev, "usb-bus-host"); |
372 | if (IS_ERR(usb_clk)) { | 370 | if (IS_ERR(usb_clk)) { |
373 | dev_err(&dev->dev, "cannot get usb-bus-host clock\n"); | 371 | dev_err(&dev->dev, "cannot get usb-bus-host clock\n"); |
374 | retval = -ENOENT; | 372 | retval = PTR_ERR(usb_clk); |
375 | goto err_clk; | 373 | goto err_clk; |
376 | } | 374 | } |
377 | 375 | ||
@@ -411,17 +409,19 @@ static int usb_hcd_s3c2410_probe (const struct hc_driver *driver, | |||
411 | /*-------------------------------------------------------------------------*/ | 409 | /*-------------------------------------------------------------------------*/ |
412 | 410 | ||
413 | static int | 411 | static int |
414 | ohci_s3c2410_start (struct usb_hcd *hcd) | 412 | ohci_s3c2410_start(struct usb_hcd *hcd) |
415 | { | 413 | { |
416 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | 414 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
417 | int ret; | 415 | int ret; |
418 | 416 | ||
419 | if ((ret = ohci_init(ohci)) < 0) | 417 | ret = ohci_init(ohci); |
418 | if (ret < 0) | ||
420 | return ret; | 419 | return ret; |
421 | 420 | ||
422 | if ((ret = ohci_run (ohci)) < 0) { | 421 | ret = ohci_run(ohci); |
423 | err ("can't start %s", hcd->self.bus_name); | 422 | if (ret < 0) { |
424 | ohci_stop (hcd); | 423 | err("can't start %s", hcd->self.bus_name); |
424 | ohci_stop(hcd); | ||
425 | return ret; | 425 | return ret; |
426 | } | 426 | } |
427 | 427 | ||
@@ -473,12 +473,12 @@ static const struct hc_driver ohci_s3c2410_hc_driver = { | |||
473 | 473 | ||
474 | /* device driver */ | 474 | /* device driver */ |
475 | 475 | ||
476 | static int ohci_hcd_s3c2410_drv_probe(struct platform_device *pdev) | 476 | static int __devinit ohci_hcd_s3c2410_drv_probe(struct platform_device *pdev) |
477 | { | 477 | { |
478 | return usb_hcd_s3c2410_probe(&ohci_s3c2410_hc_driver, pdev); | 478 | return usb_hcd_s3c2410_probe(&ohci_s3c2410_hc_driver, pdev); |
479 | } | 479 | } |
480 | 480 | ||
481 | static int ohci_hcd_s3c2410_drv_remove(struct platform_device *pdev) | 481 | static int __devexit ohci_hcd_s3c2410_drv_remove(struct platform_device *pdev) |
482 | { | 482 | { |
483 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | 483 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
484 | 484 | ||
@@ -488,7 +488,7 @@ static int ohci_hcd_s3c2410_drv_remove(struct platform_device *pdev) | |||
488 | 488 | ||
489 | static struct platform_driver ohci_hcd_s3c2410_driver = { | 489 | static struct platform_driver ohci_hcd_s3c2410_driver = { |
490 | .probe = ohci_hcd_s3c2410_drv_probe, | 490 | .probe = ohci_hcd_s3c2410_drv_probe, |
491 | .remove = ohci_hcd_s3c2410_drv_remove, | 491 | .remove = __devexit_p(ohci_hcd_s3c2410_drv_remove), |
492 | .shutdown = usb_hcd_platform_shutdown, | 492 | .shutdown = usb_hcd_platform_shutdown, |
493 | /*.suspend = ohci_hcd_s3c2410_drv_suspend, */ | 493 | /*.suspend = ohci_hcd_s3c2410_drv_suspend, */ |
494 | /*.resume = ohci_hcd_s3c2410_drv_resume, */ | 494 | /*.resume = ohci_hcd_s3c2410_drv_resume, */ |
diff --git a/drivers/usb/host/ohci-sh.c b/drivers/usb/host/ohci-sh.c index 60f03cc7ec4f..f47867ff78c7 100644 --- a/drivers/usb/host/ohci-sh.c +++ b/drivers/usb/host/ohci-sh.c | |||
@@ -77,7 +77,6 @@ static const struct hc_driver ohci_sh_hc_driver = { | |||
77 | 77 | ||
78 | /*-------------------------------------------------------------------------*/ | 78 | /*-------------------------------------------------------------------------*/ |
79 | 79 | ||
80 | #define resource_len(r) (((r)->end - (r)->start) + 1) | ||
81 | static int ohci_hcd_sh_probe(struct platform_device *pdev) | 80 | static int ohci_hcd_sh_probe(struct platform_device *pdev) |
82 | { | 81 | { |
83 | struct resource *res = NULL; | 82 | struct resource *res = NULL; |
@@ -109,8 +108,8 @@ static int ohci_hcd_sh_probe(struct platform_device *pdev) | |||
109 | 108 | ||
110 | hcd->regs = (void __iomem *)res->start; | 109 | hcd->regs = (void __iomem *)res->start; |
111 | hcd->rsrc_start = res->start; | 110 | hcd->rsrc_start = res->start; |
112 | hcd->rsrc_len = resource_len(res); | 111 | hcd->rsrc_len = resource_size(res); |
113 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); | 112 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); |
114 | if (ret != 0) { | 113 | if (ret != 0) { |
115 | err("Failed to add hcd"); | 114 | err("Failed to add hcd"); |
116 | usb_put_hcd(hcd); | 115 | usb_put_hcd(hcd); |
diff --git a/drivers/usb/host/ohci-sm501.c b/drivers/usb/host/ohci-sm501.c index cff23637cfcc..041d30f30c10 100644 --- a/drivers/usb/host/ohci-sm501.c +++ b/drivers/usb/host/ohci-sm501.c | |||
@@ -168,7 +168,7 @@ static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev) | |||
168 | 168 | ||
169 | retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); | 169 | retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); |
170 | if (retval) | 170 | if (retval) |
171 | goto err4; | 171 | goto err5; |
172 | 172 | ||
173 | /* enable power and unmask interrupts */ | 173 | /* enable power and unmask interrupts */ |
174 | 174 | ||
@@ -176,6 +176,8 @@ static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev) | |||
176 | sm501_modify_reg(dev->parent, SM501_IRQ_MASK, 1 << 6, 0); | 176 | sm501_modify_reg(dev->parent, SM501_IRQ_MASK, 1 << 6, 0); |
177 | 177 | ||
178 | return 0; | 178 | return 0; |
179 | err5: | ||
180 | iounmap(hcd->regs); | ||
179 | err4: | 181 | err4: |
180 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | 182 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); |
181 | err3: | 183 | err3: |
diff --git a/drivers/usb/host/ohci-spear.c b/drivers/usb/host/ohci-spear.c new file mode 100644 index 000000000000..4fd4bea9ac7a --- /dev/null +++ b/drivers/usb/host/ohci-spear.c | |||
@@ -0,0 +1,240 @@ | |||
1 | /* | ||
2 | * OHCI HCD (Host Controller Driver) for USB. | ||
3 | * | ||
4 | * Copyright (C) 2010 ST Microelectronics. | ||
5 | * Deepak Sikri<deepak.sikri@st.com> | ||
6 | * | ||
7 | * Based on various ohci-*.c drivers | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <linux/signal.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/clk.h> | ||
17 | |||
18 | struct spear_ohci { | ||
19 | struct ohci_hcd ohci; | ||
20 | struct clk *clk; | ||
21 | }; | ||
22 | |||
23 | #define to_spear_ohci(hcd) (struct spear_ohci *)hcd_to_ohci(hcd) | ||
24 | |||
25 | static void spear_start_ohci(struct spear_ohci *ohci) | ||
26 | { | ||
27 | clk_enable(ohci->clk); | ||
28 | } | ||
29 | |||
30 | static void spear_stop_ohci(struct spear_ohci *ohci) | ||
31 | { | ||
32 | clk_disable(ohci->clk); | ||
33 | } | ||
34 | |||
35 | static int __devinit ohci_spear_start(struct usb_hcd *hcd) | ||
36 | { | ||
37 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | ||
38 | int ret; | ||
39 | |||
40 | ret = ohci_init(ohci); | ||
41 | if (ret < 0) | ||
42 | return ret; | ||
43 | ohci->regs = hcd->regs; | ||
44 | |||
45 | ret = ohci_run(ohci); | ||
46 | if (ret < 0) { | ||
47 | dev_err(hcd->self.controller, "can't start\n"); | ||
48 | ohci_stop(hcd); | ||
49 | return ret; | ||
50 | } | ||
51 | |||
52 | create_debug_files(ohci); | ||
53 | |||
54 | #ifdef DEBUG | ||
55 | ohci_dump(ohci, 1); | ||
56 | #endif | ||
57 | return 0; | ||
58 | } | ||
59 | |||
60 | static const struct hc_driver ohci_spear_hc_driver = { | ||
61 | .description = hcd_name, | ||
62 | .product_desc = "SPEAr OHCI", | ||
63 | .hcd_priv_size = sizeof(struct spear_ohci), | ||
64 | |||
65 | /* generic hardware linkage */ | ||
66 | .irq = ohci_irq, | ||
67 | .flags = HCD_USB11 | HCD_MEMORY, | ||
68 | |||
69 | /* basic lifecycle operations */ | ||
70 | .start = ohci_spear_start, | ||
71 | .stop = ohci_stop, | ||
72 | .shutdown = ohci_shutdown, | ||
73 | #ifdef CONFIG_PM | ||
74 | .bus_suspend = ohci_bus_suspend, | ||
75 | .bus_resume = ohci_bus_resume, | ||
76 | #endif | ||
77 | |||
78 | /* managing i/o requests and associated device resources */ | ||
79 | .urb_enqueue = ohci_urb_enqueue, | ||
80 | .urb_dequeue = ohci_urb_dequeue, | ||
81 | .endpoint_disable = ohci_endpoint_disable, | ||
82 | |||
83 | /* scheduling support */ | ||
84 | .get_frame_number = ohci_get_frame, | ||
85 | |||
86 | /* root hub support */ | ||
87 | .hub_status_data = ohci_hub_status_data, | ||
88 | .hub_control = ohci_hub_control, | ||
89 | |||
90 | .start_port_reset = ohci_start_port_reset, | ||
91 | }; | ||
92 | |||
93 | static int spear_ohci_hcd_drv_probe(struct platform_device *pdev) | ||
94 | { | ||
95 | const struct hc_driver *driver = &ohci_spear_hc_driver; | ||
96 | struct usb_hcd *hcd = NULL; | ||
97 | struct clk *usbh_clk; | ||
98 | struct spear_ohci *ohci_p; | ||
99 | struct resource *res; | ||
100 | int retval, irq; | ||
101 | int *pdata = pdev->dev.platform_data; | ||
102 | char clk_name[20] = "usbh_clk"; | ||
103 | |||
104 | if (pdata == NULL) | ||
105 | return -EFAULT; | ||
106 | |||
107 | irq = platform_get_irq(pdev, 0); | ||
108 | if (irq < 0) { | ||
109 | retval = irq; | ||
110 | goto fail_irq_get; | ||
111 | } | ||
112 | |||
113 | if (*pdata >= 0) | ||
114 | sprintf(clk_name, "usbh.%01d_clk", *pdata); | ||
115 | |||
116 | usbh_clk = clk_get(NULL, clk_name); | ||
117 | if (IS_ERR(usbh_clk)) { | ||
118 | dev_err(&pdev->dev, "Error getting interface clock\n"); | ||
119 | retval = PTR_ERR(usbh_clk); | ||
120 | goto fail_get_usbh_clk; | ||
121 | } | ||
122 | |||
123 | hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); | ||
124 | if (!hcd) { | ||
125 | retval = -ENOMEM; | ||
126 | goto fail_create_hcd; | ||
127 | } | ||
128 | |||
129 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
130 | if (!res) { | ||
131 | retval = -ENODEV; | ||
132 | goto fail_request_resource; | ||
133 | } | ||
134 | |||
135 | hcd->rsrc_start = pdev->resource[0].start; | ||
136 | hcd->rsrc_len = resource_size(res); | ||
137 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
138 | dev_dbg(&pdev->dev, "request_mem_region failed\n"); | ||
139 | retval = -EBUSY; | ||
140 | goto fail_request_resource; | ||
141 | } | ||
142 | |||
143 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
144 | if (!hcd->regs) { | ||
145 | dev_dbg(&pdev->dev, "ioremap failed\n"); | ||
146 | retval = -ENOMEM; | ||
147 | goto fail_ioremap; | ||
148 | } | ||
149 | |||
150 | ohci_p = (struct spear_ohci *)hcd_to_ohci(hcd); | ||
151 | ohci_p->clk = usbh_clk; | ||
152 | spear_start_ohci(ohci_p); | ||
153 | ohci_hcd_init(hcd_to_ohci(hcd)); | ||
154 | |||
155 | retval = usb_add_hcd(hcd, platform_get_irq(pdev, 0), IRQF_DISABLED); | ||
156 | if (retval == 0) | ||
157 | return retval; | ||
158 | |||
159 | spear_stop_ohci(ohci_p); | ||
160 | iounmap(hcd->regs); | ||
161 | fail_ioremap: | ||
162 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
163 | fail_request_resource: | ||
164 | usb_put_hcd(hcd); | ||
165 | fail_create_hcd: | ||
166 | clk_put(usbh_clk); | ||
167 | fail_get_usbh_clk: | ||
168 | fail_irq_get: | ||
169 | dev_err(&pdev->dev, "init fail, %d\n", retval); | ||
170 | |||
171 | return retval; | ||
172 | } | ||
173 | |||
174 | static int spear_ohci_hcd_drv_remove(struct platform_device *pdev) | ||
175 | { | ||
176 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | ||
177 | struct spear_ohci *ohci_p = to_spear_ohci(hcd); | ||
178 | |||
179 | usb_remove_hcd(hcd); | ||
180 | if (ohci_p->clk) | ||
181 | spear_stop_ohci(ohci_p); | ||
182 | |||
183 | iounmap(hcd->regs); | ||
184 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
185 | usb_put_hcd(hcd); | ||
186 | |||
187 | if (ohci_p->clk) | ||
188 | clk_put(ohci_p->clk); | ||
189 | platform_set_drvdata(pdev, NULL); | ||
190 | return 0; | ||
191 | } | ||
192 | |||
193 | #if defined(CONFIG_PM) | ||
194 | static int spear_ohci_hcd_drv_suspend(struct platform_device *dev, | ||
195 | pm_message_t message) | ||
196 | { | ||
197 | struct usb_hcd *hcd = platform_get_drvdata(dev); | ||
198 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | ||
199 | struct spear_ohci *ohci_p = to_spear_ohci(hcd); | ||
200 | |||
201 | if (time_before(jiffies, ohci->next_statechange)) | ||
202 | msleep(5); | ||
203 | ohci->next_statechange = jiffies; | ||
204 | |||
205 | spear_stop_ohci(ohci_p); | ||
206 | ohci_to_hcd(ohci)->state = HC_STATE_SUSPENDED; | ||
207 | return 0; | ||
208 | } | ||
209 | |||
210 | static int spear_ohci_hcd_drv_resume(struct platform_device *dev) | ||
211 | { | ||
212 | struct usb_hcd *hcd = platform_get_drvdata(dev); | ||
213 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | ||
214 | struct spear_ohci *ohci_p = to_spear_ohci(hcd); | ||
215 | |||
216 | if (time_before(jiffies, ohci->next_statechange)) | ||
217 | msleep(5); | ||
218 | ohci->next_statechange = jiffies; | ||
219 | |||
220 | spear_start_ohci(ohci_p); | ||
221 | ohci_finish_controller_resume(hcd); | ||
222 | return 0; | ||
223 | } | ||
224 | #endif | ||
225 | |||
226 | /* Driver definition to register with the platform bus */ | ||
227 | static struct platform_driver spear_ohci_hcd_driver = { | ||
228 | .probe = spear_ohci_hcd_drv_probe, | ||
229 | .remove = spear_ohci_hcd_drv_remove, | ||
230 | #ifdef CONFIG_PM | ||
231 | .suspend = spear_ohci_hcd_drv_suspend, | ||
232 | .resume = spear_ohci_hcd_drv_resume, | ||
233 | #endif | ||
234 | .driver = { | ||
235 | .owner = THIS_MODULE, | ||
236 | .name = "spear-ohci", | ||
237 | }, | ||
238 | }; | ||
239 | |||
240 | MODULE_ALIAS("platform:spear-ohci"); | ||
diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c index 8dabe8e31d8c..3558491dd87d 100644 --- a/drivers/usb/host/ohci-tmio.c +++ b/drivers/usb/host/ohci-tmio.c | |||
@@ -185,7 +185,7 @@ static struct platform_driver ohci_hcd_tmio_driver; | |||
185 | 185 | ||
186 | static int __devinit ohci_hcd_tmio_drv_probe(struct platform_device *dev) | 186 | static int __devinit ohci_hcd_tmio_drv_probe(struct platform_device *dev) |
187 | { | 187 | { |
188 | struct mfd_cell *cell = dev->dev.platform_data; | 188 | const struct mfd_cell *cell = mfd_get_cell(dev); |
189 | struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0); | 189 | struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0); |
190 | struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1); | 190 | struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1); |
191 | struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2); | 191 | struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2); |
@@ -274,7 +274,7 @@ static int __devexit ohci_hcd_tmio_drv_remove(struct platform_device *dev) | |||
274 | { | 274 | { |
275 | struct usb_hcd *hcd = platform_get_drvdata(dev); | 275 | struct usb_hcd *hcd = platform_get_drvdata(dev); |
276 | struct tmio_hcd *tmio = hcd_to_tmio(hcd); | 276 | struct tmio_hcd *tmio = hcd_to_tmio(hcd); |
277 | struct mfd_cell *cell = dev->dev.platform_data; | 277 | const struct mfd_cell *cell = mfd_get_cell(dev); |
278 | 278 | ||
279 | usb_remove_hcd(hcd); | 279 | usb_remove_hcd(hcd); |
280 | tmio_stop_hc(dev); | 280 | tmio_stop_hc(dev); |
@@ -293,7 +293,7 @@ static int __devexit ohci_hcd_tmio_drv_remove(struct platform_device *dev) | |||
293 | #ifdef CONFIG_PM | 293 | #ifdef CONFIG_PM |
294 | static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state) | 294 | static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state) |
295 | { | 295 | { |
296 | struct mfd_cell *cell = dev->dev.platform_data; | 296 | const struct mfd_cell *cell = mfd_get_cell(dev); |
297 | struct usb_hcd *hcd = platform_get_drvdata(dev); | 297 | struct usb_hcd *hcd = platform_get_drvdata(dev); |
298 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | 298 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
299 | struct tmio_hcd *tmio = hcd_to_tmio(hcd); | 299 | struct tmio_hcd *tmio = hcd_to_tmio(hcd); |
@@ -326,7 +326,7 @@ static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t s | |||
326 | 326 | ||
327 | static int ohci_hcd_tmio_drv_resume(struct platform_device *dev) | 327 | static int ohci_hcd_tmio_drv_resume(struct platform_device *dev) |
328 | { | 328 | { |
329 | struct mfd_cell *cell = dev->dev.platform_data; | 329 | const struct mfd_cell *cell = mfd_get_cell(dev); |
330 | struct usb_hcd *hcd = platform_get_drvdata(dev); | 330 | struct usb_hcd *hcd = platform_get_drvdata(dev); |
331 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | 331 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
332 | struct tmio_hcd *tmio = hcd_to_tmio(hcd); | 332 | struct tmio_hcd *tmio = hcd_to_tmio(hcd); |
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index 5bf15fed0d9f..35e5fd640ce7 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h | |||
@@ -401,8 +401,9 @@ struct ohci_hcd { | |||
401 | #define OHCI_QUIRK_NEC 0x40 /* lost interrupts */ | 401 | #define OHCI_QUIRK_NEC 0x40 /* lost interrupts */ |
402 | #define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ | 402 | #define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ |
403 | #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ | 403 | #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ |
404 | #define OHCI_QUIRK_AMD_ISO 0x200 /* ISO transfers*/ | 404 | #define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/ |
405 | #define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ | 405 | #define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ |
406 | #define OHCI_QUIRK_SHUTDOWN 0x800 /* nVidia power bug */ | ||
406 | // there are also chip quirks/bugs in init logic | 407 | // there are also chip quirks/bugs in init logic |
407 | 408 | ||
408 | struct work_struct nec_work; /* Worker for NEC quirk */ | 409 | struct work_struct nec_work; /* Worker for NEC quirk */ |
@@ -432,7 +433,7 @@ static inline int quirk_zfmicro(struct ohci_hcd *ohci) | |||
432 | } | 433 | } |
433 | static inline int quirk_amdiso(struct ohci_hcd *ohci) | 434 | static inline int quirk_amdiso(struct ohci_hcd *ohci) |
434 | { | 435 | { |
435 | return ohci->flags & OHCI_QUIRK_AMD_ISO; | 436 | return ohci->flags & OHCI_QUIRK_AMD_PLL; |
436 | } | 437 | } |
437 | static inline int quirk_amdprefetch(struct ohci_hcd *ohci) | 438 | static inline int quirk_amdprefetch(struct ohci_hcd *ohci) |
438 | { | 439 | { |
@@ -574,18 +575,8 @@ static inline void _ohci_writel (const struct ohci_hcd *ohci, | |||
574 | #endif | 575 | #endif |
575 | } | 576 | } |
576 | 577 | ||
577 | #ifdef CONFIG_ARCH_LH7A404 | ||
578 | /* Marc Singer: at the time this code was written, the LH7A404 | ||
579 | * had a problem reading the USB host registers. This | ||
580 | * implementation of the ohci_readl function performs the read | ||
581 | * twice as a work-around. | ||
582 | */ | ||
583 | #define ohci_readl(o,r) (_ohci_readl(o,r),_ohci_readl(o,r)) | ||
584 | #define ohci_writel(o,v,r) _ohci_writel(o,v,r) | ||
585 | #else | ||
586 | #define ohci_readl(o,r) _ohci_readl(o,r) | 578 | #define ohci_readl(o,r) _ohci_readl(o,r) |
587 | #define ohci_writel(o,v,r) _ohci_writel(o,v,r) | 579 | #define ohci_writel(o,v,r) _ohci_writel(o,v,r) |
588 | #endif | ||
589 | 580 | ||
590 | 581 | ||
591 | /*-------------------------------------------------------------------------*/ | 582 | /*-------------------------------------------------------------------------*/ |
diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c index d9c85a292737..5fbe997dc6df 100644 --- a/drivers/usb/host/oxu210hp-hcd.c +++ b/drivers/usb/host/oxu210hp-hcd.c | |||
@@ -451,9 +451,9 @@ static void ehci_hub_descriptor(struct oxu_hcd *oxu, | |||
451 | temp = 1 + (ports / 8); | 451 | temp = 1 + (ports / 8); |
452 | desc->bDescLength = 7 + 2 * temp; | 452 | desc->bDescLength = 7 + 2 * temp; |
453 | 453 | ||
454 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 454 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
455 | memset(&desc->bitmap[0], 0, temp); | 455 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
456 | memset(&desc->bitmap[temp], 0xff, temp); | 456 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
457 | 457 | ||
458 | temp = 0x0008; /* per-port overcurrent reporting */ | 458 | temp = 0x0008; /* per-port overcurrent reporting */ |
459 | if (HCS_PPC(oxu->hcs_params)) | 459 | if (HCS_PPC(oxu->hcs_params)) |
@@ -544,8 +544,6 @@ static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) | |||
544 | qtd->buffer = NULL; | 544 | qtd->buffer = NULL; |
545 | 545 | ||
546 | spin_unlock(&oxu->mem_lock); | 546 | spin_unlock(&oxu->mem_lock); |
547 | |||
548 | return; | ||
549 | } | 547 | } |
550 | 548 | ||
551 | static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma) | 549 | static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma) |
@@ -571,8 +569,6 @@ static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) | |||
571 | oxu->qtd_used[index] = 0; | 569 | oxu->qtd_used[index] = 0; |
572 | 570 | ||
573 | spin_unlock(&oxu->mem_lock); | 571 | spin_unlock(&oxu->mem_lock); |
574 | |||
575 | return; | ||
576 | } | 572 | } |
577 | 573 | ||
578 | static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu) | 574 | static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu) |
@@ -615,8 +611,6 @@ static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh) | |||
615 | oxu->qh_used[index] = 0; | 611 | oxu->qh_used[index] = 0; |
616 | 612 | ||
617 | spin_unlock(&oxu->mem_lock); | 613 | spin_unlock(&oxu->mem_lock); |
618 | |||
619 | return; | ||
620 | } | 614 | } |
621 | 615 | ||
622 | static void qh_destroy(struct kref *kref) | 616 | static void qh_destroy(struct kref *kref) |
@@ -693,8 +687,6 @@ static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb) | |||
693 | oxu->murb_used[index] = 0; | 687 | oxu->murb_used[index] = 0; |
694 | 688 | ||
695 | spin_unlock(&oxu->mem_lock); | 689 | spin_unlock(&oxu->mem_lock); |
696 | |||
697 | return; | ||
698 | } | 690 | } |
699 | 691 | ||
700 | static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu) | 692 | static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu) |
@@ -1892,6 +1884,7 @@ static int enable_periodic(struct oxu_hcd *oxu) | |||
1892 | status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125); | 1884 | status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125); |
1893 | if (status != 0) { | 1885 | if (status != 0) { |
1894 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 1886 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
1887 | usb_hc_died(oxu_to_hcd(oxu)); | ||
1895 | return status; | 1888 | return status; |
1896 | } | 1889 | } |
1897 | 1890 | ||
@@ -1917,6 +1910,7 @@ static int disable_periodic(struct oxu_hcd *oxu) | |||
1917 | status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125); | 1910 | status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125); |
1918 | if (status != 0) { | 1911 | if (status != 0) { |
1919 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 1912 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
1913 | usb_hc_died(oxu_to_hcd(oxu)); | ||
1920 | return status; | 1914 | return status; |
1921 | } | 1915 | } |
1922 | 1916 | ||
@@ -2457,8 +2451,9 @@ static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd) | |||
2457 | goto dead; | 2451 | goto dead; |
2458 | } | 2452 | } |
2459 | 2453 | ||
2454 | /* Shared IRQ? */ | ||
2460 | status &= INTR_MASK; | 2455 | status &= INTR_MASK; |
2461 | if (!status) { /* irq sharing? */ | 2456 | if (!status || unlikely(hcd->state == HC_STATE_HALT)) { |
2462 | spin_unlock(&oxu->lock); | 2457 | spin_unlock(&oxu->lock); |
2463 | return IRQ_NONE; | 2458 | return IRQ_NONE; |
2464 | } | 2459 | } |
@@ -2524,6 +2519,7 @@ static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd) | |||
2524 | dead: | 2519 | dead: |
2525 | ehci_reset(oxu); | 2520 | ehci_reset(oxu); |
2526 | writel(0, &oxu->regs->configured_flag); | 2521 | writel(0, &oxu->regs->configured_flag); |
2522 | usb_hc_died(hcd); | ||
2527 | /* generic layer kills/unlinks all urbs, then | 2523 | /* generic layer kills/unlinks all urbs, then |
2528 | * uses oxu_stop to clean up the rest | 2524 | * uses oxu_stop to clean up the rest |
2529 | */ | 2525 | */ |
@@ -2887,7 +2883,7 @@ static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | |||
2887 | /* Ok, we have more job to do! :) */ | 2883 | /* Ok, we have more job to do! :) */ |
2888 | 2884 | ||
2889 | for (i = 0; i < num - 1; i++) { | 2885 | for (i = 0; i < num - 1; i++) { |
2890 | /* Get free micro URB poll till a free urb is recieved */ | 2886 | /* Get free micro URB poll till a free urb is received */ |
2891 | 2887 | ||
2892 | do { | 2888 | do { |
2893 | murb = (struct urb *) oxu_murb_alloc(oxu); | 2889 | murb = (struct urb *) oxu_murb_alloc(oxu); |
@@ -2919,7 +2915,7 @@ static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | |||
2919 | 2915 | ||
2920 | /* Last urb requires special handling */ | 2916 | /* Last urb requires special handling */ |
2921 | 2917 | ||
2922 | /* Get free micro URB poll till a free urb is recieved */ | 2918 | /* Get free micro URB poll till a free urb is received */ |
2923 | do { | 2919 | do { |
2924 | murb = (struct urb *) oxu_murb_alloc(oxu); | 2920 | murb = (struct urb *) oxu_murb_alloc(oxu); |
2925 | if (!murb) | 2921 | if (!murb) |
@@ -3070,7 +3066,6 @@ nogood: | |||
3070 | ep->hcpriv = NULL; | 3066 | ep->hcpriv = NULL; |
3071 | done: | 3067 | done: |
3072 | spin_unlock_irqrestore(&oxu->lock, flags); | 3068 | spin_unlock_irqrestore(&oxu->lock, flags); |
3073 | return; | ||
3074 | } | 3069 | } |
3075 | 3070 | ||
3076 | static int oxu_get_frame(struct usb_hcd *hcd) | 3071 | static int oxu_get_frame(struct usb_hcd *hcd) |
@@ -3103,7 +3098,7 @@ static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf) | |||
3103 | 3098 | ||
3104 | /* Some boards (mostly VIA?) report bogus overcurrent indications, | 3099 | /* Some boards (mostly VIA?) report bogus overcurrent indications, |
3105 | * causing massive log spam unless we completely ignore them. It | 3100 | * causing massive log spam unless we completely ignore them. It |
3106 | * may be relevant that VIA VT8235 controlers, where PORT_POWER is | 3101 | * may be relevant that VIA VT8235 controllers, where PORT_POWER is |
3107 | * always set, seem to clear PORT_OCC and PORT_CSC when writing to | 3102 | * always set, seem to clear PORT_OCC and PORT_CSC when writing to |
3108 | * PORT_POWER; that's surprising, but maybe within-spec. | 3103 | * PORT_POWER; that's surprising, but maybe within-spec. |
3109 | */ | 3104 | */ |
@@ -3696,7 +3691,7 @@ static void oxu_configuration(struct platform_device *pdev, void *base) | |||
3696 | static int oxu_verify_id(struct platform_device *pdev, void *base) | 3691 | static int oxu_verify_id(struct platform_device *pdev, void *base) |
3697 | { | 3692 | { |
3698 | u32 id; | 3693 | u32 id; |
3699 | char *bo[] = { | 3694 | static const char * const bo[] = { |
3700 | "reserved", | 3695 | "reserved", |
3701 | "128-pin LQFP", | 3696 | "128-pin LQFP", |
3702 | "84-pin TFBGA", | 3697 | "84-pin TFBGA", |
@@ -3841,7 +3836,7 @@ static int oxu_drv_probe(struct platform_device *pdev) | |||
3841 | return -EBUSY; | 3836 | return -EBUSY; |
3842 | } | 3837 | } |
3843 | 3838 | ||
3844 | ret = set_irq_type(irq, IRQF_TRIGGER_FALLING); | 3839 | ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING); |
3845 | if (ret) { | 3840 | if (ret) { |
3846 | dev_err(&pdev->dev, "error setting irq type\n"); | 3841 | dev_err(&pdev->dev, "error setting irq type\n"); |
3847 | ret = -EFAULT; | 3842 | ret = -EFAULT; |
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index 83b5f9cea85a..fd930618c28f 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
16 | #include <linux/acpi.h> | 16 | #include <linux/acpi.h> |
17 | #include <linux/dmi.h> | ||
17 | #include "pci-quirks.h" | 18 | #include "pci-quirks.h" |
18 | #include "xhci-ext-caps.h" | 19 | #include "xhci-ext-caps.h" |
19 | 20 | ||
@@ -52,6 +53,298 @@ | |||
52 | #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ | 53 | #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ |
53 | #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ | 54 | #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ |
54 | 55 | ||
56 | /* AMD quirk use */ | ||
57 | #define AB_REG_BAR_LOW 0xe0 | ||
58 | #define AB_REG_BAR_HIGH 0xe1 | ||
59 | #define AB_REG_BAR_SB700 0xf0 | ||
60 | #define AB_INDX(addr) ((addr) + 0x00) | ||
61 | #define AB_DATA(addr) ((addr) + 0x04) | ||
62 | #define AX_INDXC 0x30 | ||
63 | #define AX_DATAC 0x34 | ||
64 | |||
65 | #define NB_PCIE_INDX_ADDR 0xe0 | ||
66 | #define NB_PCIE_INDX_DATA 0xe4 | ||
67 | #define PCIE_P_CNTL 0x10040 | ||
68 | #define BIF_NB 0x10002 | ||
69 | #define NB_PIF0_PWRDOWN_0 0x01100012 | ||
70 | #define NB_PIF0_PWRDOWN_1 0x01100013 | ||
71 | |||
72 | #define USB_INTEL_XUSB2PR 0xD0 | ||
73 | #define USB_INTEL_USB3_PSSEN 0xD8 | ||
74 | |||
75 | static struct amd_chipset_info { | ||
76 | struct pci_dev *nb_dev; | ||
77 | struct pci_dev *smbus_dev; | ||
78 | int nb_type; | ||
79 | int sb_type; | ||
80 | int isoc_reqs; | ||
81 | int probe_count; | ||
82 | int probe_result; | ||
83 | } amd_chipset; | ||
84 | |||
85 | static DEFINE_SPINLOCK(amd_lock); | ||
86 | |||
87 | int usb_amd_find_chipset_info(void) | ||
88 | { | ||
89 | u8 rev = 0; | ||
90 | unsigned long flags; | ||
91 | struct amd_chipset_info info; | ||
92 | int ret; | ||
93 | |||
94 | spin_lock_irqsave(&amd_lock, flags); | ||
95 | |||
96 | /* probe only once */ | ||
97 | if (amd_chipset.probe_count > 0) { | ||
98 | amd_chipset.probe_count++; | ||
99 | spin_unlock_irqrestore(&amd_lock, flags); | ||
100 | return amd_chipset.probe_result; | ||
101 | } | ||
102 | memset(&info, 0, sizeof(info)); | ||
103 | spin_unlock_irqrestore(&amd_lock, flags); | ||
104 | |||
105 | info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL); | ||
106 | if (info.smbus_dev) { | ||
107 | rev = info.smbus_dev->revision; | ||
108 | if (rev >= 0x40) | ||
109 | info.sb_type = 1; | ||
110 | else if (rev >= 0x30 && rev <= 0x3b) | ||
111 | info.sb_type = 3; | ||
112 | } else { | ||
113 | info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | ||
114 | 0x780b, NULL); | ||
115 | if (!info.smbus_dev) { | ||
116 | ret = 0; | ||
117 | goto commit; | ||
118 | } | ||
119 | |||
120 | rev = info.smbus_dev->revision; | ||
121 | if (rev >= 0x11 && rev <= 0x18) | ||
122 | info.sb_type = 2; | ||
123 | } | ||
124 | |||
125 | if (info.sb_type == 0) { | ||
126 | if (info.smbus_dev) { | ||
127 | pci_dev_put(info.smbus_dev); | ||
128 | info.smbus_dev = NULL; | ||
129 | } | ||
130 | ret = 0; | ||
131 | goto commit; | ||
132 | } | ||
133 | |||
134 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); | ||
135 | if (info.nb_dev) { | ||
136 | info.nb_type = 1; | ||
137 | } else { | ||
138 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); | ||
139 | if (info.nb_dev) { | ||
140 | info.nb_type = 2; | ||
141 | } else { | ||
142 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, | ||
143 | 0x9600, NULL); | ||
144 | if (info.nb_dev) | ||
145 | info.nb_type = 3; | ||
146 | } | ||
147 | } | ||
148 | |||
149 | ret = info.probe_result = 1; | ||
150 | printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); | ||
151 | |||
152 | commit: | ||
153 | |||
154 | spin_lock_irqsave(&amd_lock, flags); | ||
155 | if (amd_chipset.probe_count > 0) { | ||
156 | /* race - someone else was faster - drop devices */ | ||
157 | |||
158 | /* Mark that we where here */ | ||
159 | amd_chipset.probe_count++; | ||
160 | ret = amd_chipset.probe_result; | ||
161 | |||
162 | spin_unlock_irqrestore(&amd_lock, flags); | ||
163 | |||
164 | if (info.nb_dev) | ||
165 | pci_dev_put(info.nb_dev); | ||
166 | if (info.smbus_dev) | ||
167 | pci_dev_put(info.smbus_dev); | ||
168 | |||
169 | } else { | ||
170 | /* no race - commit the result */ | ||
171 | info.probe_count++; | ||
172 | amd_chipset = info; | ||
173 | spin_unlock_irqrestore(&amd_lock, flags); | ||
174 | } | ||
175 | |||
176 | return ret; | ||
177 | } | ||
178 | EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); | ||
179 | |||
180 | /* | ||
181 | * The hardware normally enables the A-link power management feature, which | ||
182 | * lets the system lower the power consumption in idle states. | ||
183 | * | ||
184 | * This USB quirk prevents the link going into that lower power state | ||
185 | * during isochronous transfers. | ||
186 | * | ||
187 | * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of | ||
188 | * some AMD platforms may stutter or have breaks occasionally. | ||
189 | */ | ||
190 | static void usb_amd_quirk_pll(int disable) | ||
191 | { | ||
192 | u32 addr, addr_low, addr_high, val; | ||
193 | u32 bit = disable ? 0 : 1; | ||
194 | unsigned long flags; | ||
195 | |||
196 | spin_lock_irqsave(&amd_lock, flags); | ||
197 | |||
198 | if (disable) { | ||
199 | amd_chipset.isoc_reqs++; | ||
200 | if (amd_chipset.isoc_reqs > 1) { | ||
201 | spin_unlock_irqrestore(&amd_lock, flags); | ||
202 | return; | ||
203 | } | ||
204 | } else { | ||
205 | amd_chipset.isoc_reqs--; | ||
206 | if (amd_chipset.isoc_reqs > 0) { | ||
207 | spin_unlock_irqrestore(&amd_lock, flags); | ||
208 | return; | ||
209 | } | ||
210 | } | ||
211 | |||
212 | if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) { | ||
213 | outb_p(AB_REG_BAR_LOW, 0xcd6); | ||
214 | addr_low = inb_p(0xcd7); | ||
215 | outb_p(AB_REG_BAR_HIGH, 0xcd6); | ||
216 | addr_high = inb_p(0xcd7); | ||
217 | addr = addr_high << 8 | addr_low; | ||
218 | |||
219 | outl_p(0x30, AB_INDX(addr)); | ||
220 | outl_p(0x40, AB_DATA(addr)); | ||
221 | outl_p(0x34, AB_INDX(addr)); | ||
222 | val = inl_p(AB_DATA(addr)); | ||
223 | } else if (amd_chipset.sb_type == 3) { | ||
224 | pci_read_config_dword(amd_chipset.smbus_dev, | ||
225 | AB_REG_BAR_SB700, &addr); | ||
226 | outl(AX_INDXC, AB_INDX(addr)); | ||
227 | outl(0x40, AB_DATA(addr)); | ||
228 | outl(AX_DATAC, AB_INDX(addr)); | ||
229 | val = inl(AB_DATA(addr)); | ||
230 | } else { | ||
231 | spin_unlock_irqrestore(&amd_lock, flags); | ||
232 | return; | ||
233 | } | ||
234 | |||
235 | if (disable) { | ||
236 | val &= ~0x08; | ||
237 | val |= (1 << 4) | (1 << 9); | ||
238 | } else { | ||
239 | val |= 0x08; | ||
240 | val &= ~((1 << 4) | (1 << 9)); | ||
241 | } | ||
242 | outl_p(val, AB_DATA(addr)); | ||
243 | |||
244 | if (!amd_chipset.nb_dev) { | ||
245 | spin_unlock_irqrestore(&amd_lock, flags); | ||
246 | return; | ||
247 | } | ||
248 | |||
249 | if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { | ||
250 | addr = PCIE_P_CNTL; | ||
251 | pci_write_config_dword(amd_chipset.nb_dev, | ||
252 | NB_PCIE_INDX_ADDR, addr); | ||
253 | pci_read_config_dword(amd_chipset.nb_dev, | ||
254 | NB_PCIE_INDX_DATA, &val); | ||
255 | |||
256 | val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); | ||
257 | val |= bit | (bit << 3) | (bit << 12); | ||
258 | val |= ((!bit) << 4) | ((!bit) << 9); | ||
259 | pci_write_config_dword(amd_chipset.nb_dev, | ||
260 | NB_PCIE_INDX_DATA, val); | ||
261 | |||
262 | addr = BIF_NB; | ||
263 | pci_write_config_dword(amd_chipset.nb_dev, | ||
264 | NB_PCIE_INDX_ADDR, addr); | ||
265 | pci_read_config_dword(amd_chipset.nb_dev, | ||
266 | NB_PCIE_INDX_DATA, &val); | ||
267 | val &= ~(1 << 8); | ||
268 | val |= bit << 8; | ||
269 | |||
270 | pci_write_config_dword(amd_chipset.nb_dev, | ||
271 | NB_PCIE_INDX_DATA, val); | ||
272 | } else if (amd_chipset.nb_type == 2) { | ||
273 | addr = NB_PIF0_PWRDOWN_0; | ||
274 | pci_write_config_dword(amd_chipset.nb_dev, | ||
275 | NB_PCIE_INDX_ADDR, addr); | ||
276 | pci_read_config_dword(amd_chipset.nb_dev, | ||
277 | NB_PCIE_INDX_DATA, &val); | ||
278 | if (disable) | ||
279 | val &= ~(0x3f << 7); | ||
280 | else | ||
281 | val |= 0x3f << 7; | ||
282 | |||
283 | pci_write_config_dword(amd_chipset.nb_dev, | ||
284 | NB_PCIE_INDX_DATA, val); | ||
285 | |||
286 | addr = NB_PIF0_PWRDOWN_1; | ||
287 | pci_write_config_dword(amd_chipset.nb_dev, | ||
288 | NB_PCIE_INDX_ADDR, addr); | ||
289 | pci_read_config_dword(amd_chipset.nb_dev, | ||
290 | NB_PCIE_INDX_DATA, &val); | ||
291 | if (disable) | ||
292 | val &= ~(0x3f << 7); | ||
293 | else | ||
294 | val |= 0x3f << 7; | ||
295 | |||
296 | pci_write_config_dword(amd_chipset.nb_dev, | ||
297 | NB_PCIE_INDX_DATA, val); | ||
298 | } | ||
299 | |||
300 | spin_unlock_irqrestore(&amd_lock, flags); | ||
301 | return; | ||
302 | } | ||
303 | |||
304 | void usb_amd_quirk_pll_disable(void) | ||
305 | { | ||
306 | usb_amd_quirk_pll(1); | ||
307 | } | ||
308 | EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); | ||
309 | |||
310 | void usb_amd_quirk_pll_enable(void) | ||
311 | { | ||
312 | usb_amd_quirk_pll(0); | ||
313 | } | ||
314 | EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); | ||
315 | |||
316 | void usb_amd_dev_put(void) | ||
317 | { | ||
318 | struct pci_dev *nb, *smbus; | ||
319 | unsigned long flags; | ||
320 | |||
321 | spin_lock_irqsave(&amd_lock, flags); | ||
322 | |||
323 | amd_chipset.probe_count--; | ||
324 | if (amd_chipset.probe_count > 0) { | ||
325 | spin_unlock_irqrestore(&amd_lock, flags); | ||
326 | return; | ||
327 | } | ||
328 | |||
329 | /* save them to pci_dev_put outside of spinlock */ | ||
330 | nb = amd_chipset.nb_dev; | ||
331 | smbus = amd_chipset.smbus_dev; | ||
332 | |||
333 | amd_chipset.nb_dev = NULL; | ||
334 | amd_chipset.smbus_dev = NULL; | ||
335 | amd_chipset.nb_type = 0; | ||
336 | amd_chipset.sb_type = 0; | ||
337 | amd_chipset.isoc_reqs = 0; | ||
338 | amd_chipset.probe_result = 0; | ||
339 | |||
340 | spin_unlock_irqrestore(&amd_lock, flags); | ||
341 | |||
342 | if (nb) | ||
343 | pci_dev_put(nb); | ||
344 | if (smbus) | ||
345 | pci_dev_put(smbus); | ||
346 | } | ||
347 | EXPORT_SYMBOL_GPL(usb_amd_dev_put); | ||
55 | 348 | ||
56 | /* | 349 | /* |
57 | * Make sure the controller is completely inactive, unable to | 350 | * Make sure the controller is completely inactive, unable to |
@@ -169,6 +462,7 @@ static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) | |||
169 | static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) | 462 | static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) |
170 | { | 463 | { |
171 | void __iomem *base; | 464 | void __iomem *base; |
465 | u32 control; | ||
172 | 466 | ||
173 | if (!mmio_resource_enabled(pdev, 0)) | 467 | if (!mmio_resource_enabled(pdev, 0)) |
174 | return; | 468 | return; |
@@ -177,10 +471,14 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) | |||
177 | if (base == NULL) | 471 | if (base == NULL) |
178 | return; | 472 | return; |
179 | 473 | ||
474 | control = readl(base + OHCI_CONTROL); | ||
475 | |||
180 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | 476 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ |
181 | #ifndef __hppa__ | 477 | #ifdef __hppa__ |
182 | { | 478 | #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) |
183 | u32 control = readl(base + OHCI_CONTROL); | 479 | #else |
480 | #define OHCI_CTRL_MASK OHCI_CTRL_RWC | ||
481 | |||
184 | if (control & OHCI_CTRL_IR) { | 482 | if (control & OHCI_CTRL_IR) { |
185 | int wait_time = 500; /* arbitrary; 5 seconds */ | 483 | int wait_time = 500; /* arbitrary; 5 seconds */ |
186 | writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); | 484 | writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); |
@@ -194,13 +492,12 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) | |||
194 | dev_warn(&pdev->dev, "OHCI: BIOS handoff failed" | 492 | dev_warn(&pdev->dev, "OHCI: BIOS handoff failed" |
195 | " (BIOS bug?) %08x\n", | 493 | " (BIOS bug?) %08x\n", |
196 | readl(base + OHCI_CONTROL)); | 494 | readl(base + OHCI_CONTROL)); |
197 | |||
198 | /* reset controller, preserving RWC */ | ||
199 | writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL); | ||
200 | } | 495 | } |
201 | } | ||
202 | #endif | 496 | #endif |
203 | 497 | ||
498 | /* reset controller, preserving RWC (and possibly IR) */ | ||
499 | writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); | ||
500 | |||
204 | /* | 501 | /* |
205 | * disable interrupts | 502 | * disable interrupts |
206 | */ | 503 | */ |
@@ -210,14 +507,84 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) | |||
210 | iounmap(base); | 507 | iounmap(base); |
211 | } | 508 | } |
212 | 509 | ||
510 | static void __devinit ehci_bios_handoff(struct pci_dev *pdev, | ||
511 | void __iomem *op_reg_base, | ||
512 | u32 cap, u8 offset) | ||
513 | { | ||
514 | int try_handoff = 1, tried_handoff = 0; | ||
515 | |||
516 | /* The Pegatron Lucid (ExoPC) tablet sporadically waits for 90 | ||
517 | * seconds trying the handoff on its unused controller. Skip | ||
518 | * it. */ | ||
519 | if (pdev->vendor == 0x8086 && pdev->device == 0x283a) { | ||
520 | const char *dmi_bn = dmi_get_system_info(DMI_BOARD_NAME); | ||
521 | const char *dmi_bv = dmi_get_system_info(DMI_BIOS_VERSION); | ||
522 | if (dmi_bn && !strcmp(dmi_bn, "EXOPG06411") && | ||
523 | dmi_bv && !strcmp(dmi_bv, "Lucid-CE-133")) | ||
524 | try_handoff = 0; | ||
525 | } | ||
526 | |||
527 | if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { | ||
528 | dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); | ||
529 | |||
530 | #if 0 | ||
531 | /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, | ||
532 | * but that seems dubious in general (the BIOS left it off intentionally) | ||
533 | * and is known to prevent some systems from booting. so we won't do this | ||
534 | * unless maybe we can determine when we're on a system that needs SMI forced. | ||
535 | */ | ||
536 | /* BIOS workaround (?): be sure the pre-Linux code | ||
537 | * receives the SMI | ||
538 | */ | ||
539 | pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); | ||
540 | pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, | ||
541 | val | EHCI_USBLEGCTLSTS_SOOE); | ||
542 | #endif | ||
543 | |||
544 | /* some systems get upset if this semaphore is | ||
545 | * set for any other reason than forcing a BIOS | ||
546 | * handoff.. | ||
547 | */ | ||
548 | pci_write_config_byte(pdev, offset + 3, 1); | ||
549 | } | ||
550 | |||
551 | /* if boot firmware now owns EHCI, spin till it hands it over. */ | ||
552 | if (try_handoff) { | ||
553 | int msec = 1000; | ||
554 | while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { | ||
555 | tried_handoff = 1; | ||
556 | msleep(10); | ||
557 | msec -= 10; | ||
558 | pci_read_config_dword(pdev, offset, &cap); | ||
559 | } | ||
560 | } | ||
561 | |||
562 | if (cap & EHCI_USBLEGSUP_BIOS) { | ||
563 | /* well, possibly buggy BIOS... try to shut it down, | ||
564 | * and hope nothing goes too wrong | ||
565 | */ | ||
566 | if (try_handoff) | ||
567 | dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" | ||
568 | " (BIOS bug?) %08x\n", cap); | ||
569 | pci_write_config_byte(pdev, offset + 2, 0); | ||
570 | } | ||
571 | |||
572 | /* just in case, always disable EHCI SMIs */ | ||
573 | pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); | ||
574 | |||
575 | /* If the BIOS ever owned the controller then we can't expect | ||
576 | * any power sessions to remain intact. | ||
577 | */ | ||
578 | if (tried_handoff) | ||
579 | writel(0, op_reg_base + EHCI_CONFIGFLAG); | ||
580 | } | ||
581 | |||
213 | static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) | 582 | static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) |
214 | { | 583 | { |
215 | int wait_time, delta; | ||
216 | void __iomem *base, *op_reg_base; | 584 | void __iomem *base, *op_reg_base; |
217 | u32 hcc_params, val; | 585 | u32 hcc_params, cap, val; |
218 | u8 offset, cap_length; | 586 | u8 offset, cap_length; |
219 | int count = 256/4; | 587 | int wait_time, delta, count = 256/4; |
220 | int tried_handoff = 0; | ||
221 | 588 | ||
222 | if (!mmio_resource_enabled(pdev, 0)) | 589 | if (!mmio_resource_enabled(pdev, 0)) |
223 | return; | 590 | return; |
@@ -236,77 +603,17 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) | |||
236 | hcc_params = readl(base + EHCI_HCC_PARAMS); | 603 | hcc_params = readl(base + EHCI_HCC_PARAMS); |
237 | offset = (hcc_params >> 8) & 0xff; | 604 | offset = (hcc_params >> 8) & 0xff; |
238 | while (offset && --count) { | 605 | while (offset && --count) { |
239 | u32 cap; | ||
240 | int msec; | ||
241 | |||
242 | pci_read_config_dword(pdev, offset, &cap); | 606 | pci_read_config_dword(pdev, offset, &cap); |
243 | switch (cap & 0xff) { | ||
244 | case 1: /* BIOS/SMM/... handoff support */ | ||
245 | if ((cap & EHCI_USBLEGSUP_BIOS)) { | ||
246 | dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); | ||
247 | 607 | ||
248 | #if 0 | 608 | switch (cap & 0xff) { |
249 | /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, | 609 | case 1: |
250 | * but that seems dubious in general (the BIOS left it off intentionally) | 610 | ehci_bios_handoff(pdev, op_reg_base, cap, offset); |
251 | * and is known to prevent some systems from booting. so we won't do this | ||
252 | * unless maybe we can determine when we're on a system that needs SMI forced. | ||
253 | */ | ||
254 | /* BIOS workaround (?): be sure the | ||
255 | * pre-Linux code receives the SMI | ||
256 | */ | ||
257 | pci_read_config_dword(pdev, | ||
258 | offset + EHCI_USBLEGCTLSTS, | ||
259 | &val); | ||
260 | pci_write_config_dword(pdev, | ||
261 | offset + EHCI_USBLEGCTLSTS, | ||
262 | val | EHCI_USBLEGCTLSTS_SOOE); | ||
263 | #endif | ||
264 | |||
265 | /* some systems get upset if this semaphore is | ||
266 | * set for any other reason than forcing a BIOS | ||
267 | * handoff.. | ||
268 | */ | ||
269 | pci_write_config_byte(pdev, offset + 3, 1); | ||
270 | } | ||
271 | |||
272 | /* if boot firmware now owns EHCI, spin till | ||
273 | * it hands it over. | ||
274 | */ | ||
275 | msec = 1000; | ||
276 | while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { | ||
277 | tried_handoff = 1; | ||
278 | msleep(10); | ||
279 | msec -= 10; | ||
280 | pci_read_config_dword(pdev, offset, &cap); | ||
281 | } | ||
282 | |||
283 | if (cap & EHCI_USBLEGSUP_BIOS) { | ||
284 | /* well, possibly buggy BIOS... try to shut | ||
285 | * it down, and hope nothing goes too wrong | ||
286 | */ | ||
287 | dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" | ||
288 | " (BIOS bug?) %08x\n", cap); | ||
289 | pci_write_config_byte(pdev, offset + 2, 0); | ||
290 | } | ||
291 | |||
292 | /* just in case, always disable EHCI SMIs */ | ||
293 | pci_write_config_dword(pdev, | ||
294 | offset + EHCI_USBLEGCTLSTS, | ||
295 | 0); | ||
296 | |||
297 | /* If the BIOS ever owned the controller then we | ||
298 | * can't expect any power sessions to remain intact. | ||
299 | */ | ||
300 | if (tried_handoff) | ||
301 | writel(0, op_reg_base + EHCI_CONFIGFLAG); | ||
302 | break; | 611 | break; |
303 | case 0: /* illegal reserved capability */ | 612 | case 0: /* Illegal reserved cap, set cap=0 so we exit */ |
304 | cap = 0; | 613 | cap = 0; /* then fallthrough... */ |
305 | /* FALLTHROUGH */ | ||
306 | default: | 614 | default: |
307 | dev_warn(&pdev->dev, "EHCI: unrecognized capability " | 615 | dev_warn(&pdev->dev, "EHCI: unrecognized capability " |
308 | "%02x\n", cap & 0xff); | 616 | "%02x\n", cap & 0xff); |
309 | break; | ||
310 | } | 617 | } |
311 | offset = (cap >> 8) & 0xff; | 618 | offset = (cap >> 8) & 0xff; |
312 | } | 619 | } |
@@ -338,8 +645,6 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) | |||
338 | writel(0x3f, op_reg_base + EHCI_USBSTS); | 645 | writel(0x3f, op_reg_base + EHCI_USBSTS); |
339 | 646 | ||
340 | iounmap(base); | 647 | iounmap(base); |
341 | |||
342 | return; | ||
343 | } | 648 | } |
344 | 649 | ||
345 | /* | 650 | /* |
@@ -371,6 +676,64 @@ static int handshake(void __iomem *ptr, u32 mask, u32 done, | |||
371 | return -ETIMEDOUT; | 676 | return -ETIMEDOUT; |
372 | } | 677 | } |
373 | 678 | ||
679 | bool usb_is_intel_switchable_xhci(struct pci_dev *pdev) | ||
680 | { | ||
681 | return pdev->class == PCI_CLASS_SERIAL_USB_XHCI && | ||
682 | pdev->vendor == PCI_VENDOR_ID_INTEL && | ||
683 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI; | ||
684 | } | ||
685 | EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci); | ||
686 | |||
687 | /* | ||
688 | * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that | ||
689 | * share some number of ports. These ports can be switched between either | ||
690 | * controller. Not all of the ports under the EHCI host controller may be | ||
691 | * switchable. | ||
692 | * | ||
693 | * The ports should be switched over to xHCI before PCI probes for any device | ||
694 | * start. This avoids active devices under EHCI being disconnected during the | ||
695 | * port switchover, which could cause loss of data on USB storage devices, or | ||
696 | * failed boot when the root file system is on a USB mass storage device and is | ||
697 | * enumerated under EHCI first. | ||
698 | * | ||
699 | * We write into the xHC's PCI configuration space in some Intel-specific | ||
700 | * registers to switch the ports over. The USB 3.0 terminations and the USB | ||
701 | * 2.0 data wires are switched separately. We want to enable the SuperSpeed | ||
702 | * terminations before switching the USB 2.0 wires over, so that USB 3.0 | ||
703 | * devices connect at SuperSpeed, rather than at USB 2.0 speeds. | ||
704 | */ | ||
705 | void usb_enable_xhci_ports(struct pci_dev *xhci_pdev) | ||
706 | { | ||
707 | u32 ports_available; | ||
708 | |||
709 | ports_available = 0xffffffff; | ||
710 | /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable | ||
711 | * Register, to turn on SuperSpeed terminations for all | ||
712 | * available ports. | ||
713 | */ | ||
714 | pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, | ||
715 | cpu_to_le32(ports_available)); | ||
716 | |||
717 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, | ||
718 | &ports_available); | ||
719 | dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled " | ||
720 | "under xHCI: 0x%x\n", ports_available); | ||
721 | |||
722 | ports_available = 0xffffffff; | ||
723 | /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to | ||
724 | * switch the USB 2.0 power and data lines over to the xHCI | ||
725 | * host. | ||
726 | */ | ||
727 | pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, | ||
728 | cpu_to_le32(ports_available)); | ||
729 | |||
730 | pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, | ||
731 | &ports_available); | ||
732 | dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over " | ||
733 | "to xHCI: 0x%x\n", ports_available); | ||
734 | } | ||
735 | EXPORT_SYMBOL_GPL(usb_enable_xhci_ports); | ||
736 | |||
374 | /** | 737 | /** |
375 | * PCI Quirks for xHCI. | 738 | * PCI Quirks for xHCI. |
376 | * | 739 | * |
@@ -430,6 +793,8 @@ static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev) | |||
430 | writel(XHCI_LEGACY_DISABLE_SMI, | 793 | writel(XHCI_LEGACY_DISABLE_SMI, |
431 | base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); | 794 | base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); |
432 | 795 | ||
796 | if (usb_is_intel_switchable_xhci(pdev)) | ||
797 | usb_enable_xhci_ports(pdev); | ||
433 | hc_init: | 798 | hc_init: |
434 | op_reg_base = base + XHCI_HC_LENGTH(readl(base)); | 799 | op_reg_base = base + XHCI_HC_LENGTH(readl(base)); |
435 | 800 | ||
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h index 1564edfff6fe..b1002a8ef96f 100644 --- a/drivers/usb/host/pci-quirks.h +++ b/drivers/usb/host/pci-quirks.h | |||
@@ -1,7 +1,19 @@ | |||
1 | #ifndef __LINUX_USB_PCI_QUIRKS_H | 1 | #ifndef __LINUX_USB_PCI_QUIRKS_H |
2 | #define __LINUX_USB_PCI_QUIRKS_H | 2 | #define __LINUX_USB_PCI_QUIRKS_H |
3 | 3 | ||
4 | #ifdef CONFIG_PCI | ||
4 | void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); | 5 | void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); |
5 | int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); | 6 | int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); |
7 | int usb_amd_find_chipset_info(void); | ||
8 | void usb_amd_dev_put(void); | ||
9 | void usb_amd_quirk_pll_disable(void); | ||
10 | void usb_amd_quirk_pll_enable(void); | ||
11 | bool usb_is_intel_switchable_xhci(struct pci_dev *pdev); | ||
12 | void usb_enable_xhci_ports(struct pci_dev *xhci_pdev); | ||
13 | #else | ||
14 | static inline void usb_amd_quirk_pll_disable(void) {} | ||
15 | static inline void usb_amd_quirk_pll_enable(void) {} | ||
16 | static inline void usb_amd_dev_put(void) {} | ||
17 | #endif /* CONFIG_PCI */ | ||
6 | 18 | ||
7 | #endif /* __LINUX_USB_PCI_QUIRKS_H */ | 19 | #endif /* __LINUX_USB_PCI_QUIRKS_H */ |
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 77be3c24a427..4586369dda00 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c | |||
@@ -2150,8 +2150,9 @@ static void r8a66597_hub_descriptor(struct r8a66597 *r8a66597, | |||
2150 | desc->bDescLength = 9; | 2150 | desc->bDescLength = 9; |
2151 | desc->bPwrOn2PwrGood = 0; | 2151 | desc->bPwrOn2PwrGood = 0; |
2152 | desc->wHubCharacteristics = cpu_to_le16(0x0011); | 2152 | desc->wHubCharacteristics = cpu_to_le16(0x0011); |
2153 | desc->bitmap[0] = ((1 << r8a66597->max_root_hub) - 1) << 1; | 2153 | desc->u.hs.DeviceRemovable[0] = |
2154 | desc->bitmap[1] = ~0; | 2154 | ((1 << r8a66597->max_root_hub) - 1) << 1; |
2155 | desc->u.hs.DeviceRemovable[1] = ~0; | ||
2155 | } | 2156 | } |
2156 | 2157 | ||
2157 | static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | 2158 | static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
@@ -2397,7 +2398,7 @@ static const struct dev_pm_ops r8a66597_dev_pm_ops = { | |||
2397 | #define R8A66597_DEV_PM_OPS NULL | 2398 | #define R8A66597_DEV_PM_OPS NULL |
2398 | #endif | 2399 | #endif |
2399 | 2400 | ||
2400 | static int __init_or_module r8a66597_remove(struct platform_device *pdev) | 2401 | static int __devexit r8a66597_remove(struct platform_device *pdev) |
2401 | { | 2402 | { |
2402 | struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev); | 2403 | struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev); |
2403 | struct usb_hcd *hcd = r8a66597_to_hcd(r8a66597); | 2404 | struct usb_hcd *hcd = r8a66597_to_hcd(r8a66597); |
@@ -2516,6 +2517,7 @@ static int __devinit r8a66597_probe(struct platform_device *pdev) | |||
2516 | INIT_LIST_HEAD(&r8a66597->child_device); | 2517 | INIT_LIST_HEAD(&r8a66597->child_device); |
2517 | 2518 | ||
2518 | hcd->rsrc_start = res->start; | 2519 | hcd->rsrc_start = res->start; |
2520 | hcd->has_tt = 1; | ||
2519 | 2521 | ||
2520 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | irq_trigger); | 2522 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | irq_trigger); |
2521 | if (ret != 0) { | 2523 | if (ret != 0) { |
@@ -2542,7 +2544,7 @@ clean_up: | |||
2542 | 2544 | ||
2543 | static struct platform_driver r8a66597_driver = { | 2545 | static struct platform_driver r8a66597_driver = { |
2544 | .probe = r8a66597_probe, | 2546 | .probe = r8a66597_probe, |
2545 | .remove = r8a66597_remove, | 2547 | .remove = __devexit_p(r8a66597_remove), |
2546 | .driver = { | 2548 | .driver = { |
2547 | .name = (char *) hcd_name, | 2549 | .name = (char *) hcd_name, |
2548 | .owner = THIS_MODULE, | 2550 | .owner = THIS_MODULE, |
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index 95d0f5adfdcf..25563e9a90bc 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h | |||
@@ -227,7 +227,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, | |||
227 | int odd = len & 0x0001; | 227 | int odd = len & 0x0001; |
228 | 228 | ||
229 | len = len / 2; | 229 | len = len / 2; |
230 | ioread16_rep(fifoaddr, buf, len); | 230 | iowrite16_rep(fifoaddr, buf, len); |
231 | if (unlikely(odd)) { | 231 | if (unlikely(odd)) { |
232 | buf = &buf[len]; | 232 | buf = &buf[len]; |
233 | iowrite8((unsigned char)*buf, fifoaddr); | 233 | iowrite8((unsigned char)*buf, fifoaddr); |
diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c index 990f06b89eaa..1a996245ab98 100644 --- a/drivers/usb/host/sl811-hcd.c +++ b/drivers/usb/host/sl811-hcd.c | |||
@@ -47,6 +47,7 @@ | |||
47 | #include <linux/usb/sl811.h> | 47 | #include <linux/usb/sl811.h> |
48 | #include <linux/usb/hcd.h> | 48 | #include <linux/usb/hcd.h> |
49 | #include <linux/platform_device.h> | 49 | #include <linux/platform_device.h> |
50 | #include <linux/prefetch.h> | ||
50 | 51 | ||
51 | #include <asm/io.h> | 52 | #include <asm/io.h> |
52 | #include <asm/irq.h> | 53 | #include <asm/irq.h> |
@@ -71,12 +72,6 @@ MODULE_ALIAS("platform:sl811-hcd"); | |||
71 | /* for now, use only one transfer register bank */ | 72 | /* for now, use only one transfer register bank */ |
72 | #undef USE_B | 73 | #undef USE_B |
73 | 74 | ||
74 | /* this doesn't understand urb->iso_frame_desc[], but if you had a driver | ||
75 | * that just queued one ISO frame per URB then iso transfers "should" work | ||
76 | * using the normal urb status fields. | ||
77 | */ | ||
78 | #define DISABLE_ISO | ||
79 | |||
80 | // #define QUIRK2 | 75 | // #define QUIRK2 |
81 | #define QUIRK3 | 76 | #define QUIRK3 |
82 | 77 | ||
@@ -807,7 +802,7 @@ static int sl811h_urb_enqueue( | |||
807 | int retval; | 802 | int retval; |
808 | struct usb_host_endpoint *hep = urb->ep; | 803 | struct usb_host_endpoint *hep = urb->ep; |
809 | 804 | ||
810 | #ifdef DISABLE_ISO | 805 | #ifndef CONFIG_USB_SL811_HCD_ISO |
811 | if (type == PIPE_ISOCHRONOUS) | 806 | if (type == PIPE_ISOCHRONOUS) |
812 | return -ENOSPC; | 807 | return -ENOSPC; |
813 | #endif | 808 | #endif |
@@ -861,6 +856,7 @@ static int sl811h_urb_enqueue( | |||
861 | DBG("dev %d ep%d maxpacket %d\n", | 856 | DBG("dev %d ep%d maxpacket %d\n", |
862 | udev->devnum, epnum, ep->maxpacket); | 857 | udev->devnum, epnum, ep->maxpacket); |
863 | retval = -EINVAL; | 858 | retval = -EINVAL; |
859 | kfree(ep); | ||
864 | goto fail; | 860 | goto fail; |
865 | } | 861 | } |
866 | 862 | ||
@@ -1110,9 +1106,9 @@ sl811h_hub_descriptor ( | |||
1110 | 1106 | ||
1111 | desc->wHubCharacteristics = cpu_to_le16(temp); | 1107 | desc->wHubCharacteristics = cpu_to_le16(temp); |
1112 | 1108 | ||
1113 | /* two bitmaps: ports removable, and legacy PortPwrCtrlMask */ | 1109 | /* ports removable, and legacy PortPwrCtrlMask */ |
1114 | desc->bitmap[0] = 0 << 1; | 1110 | desc->u.hs.DeviceRemovable[0] = 0 << 1; |
1115 | desc->bitmap[1] = ~0; | 1111 | desc->u.hs.DeviceRemovable[1] = ~0; |
1116 | } | 1112 | } |
1117 | 1113 | ||
1118 | static void | 1114 | static void |
diff --git a/drivers/usb/host/sl811_cs.c b/drivers/usb/host/sl811_cs.c index 0e13a00eb2ed..3b6f50eaec91 100644 --- a/drivers/usb/host/sl811_cs.c +++ b/drivers/usb/host/sl811_cs.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/ioport.h> | 20 | #include <linux/ioport.h> |
21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
22 | 22 | ||
23 | #include <pcmcia/cs.h> | ||
24 | #include <pcmcia/cistpl.h> | 23 | #include <pcmcia/cistpl.h> |
25 | #include <pcmcia/cisreg.h> | 24 | #include <pcmcia/cisreg.h> |
26 | #include <pcmcia/ds.h> | 25 | #include <pcmcia/ds.h> |
@@ -132,49 +131,12 @@ static void sl811_cs_release(struct pcmcia_device * link) | |||
132 | platform_device_unregister(&platform_dev); | 131 | platform_device_unregister(&platform_dev); |
133 | } | 132 | } |
134 | 133 | ||
135 | static int sl811_cs_config_check(struct pcmcia_device *p_dev, | 134 | static int sl811_cs_config_check(struct pcmcia_device *p_dev, void *priv_data) |
136 | cistpl_cftable_entry_t *cfg, | ||
137 | cistpl_cftable_entry_t *dflt, | ||
138 | unsigned int vcc, | ||
139 | void *priv_data) | ||
140 | { | 135 | { |
141 | if (cfg->index == 0) | 136 | if (p_dev->config_index == 0) |
142 | return -ENODEV; | 137 | return -EINVAL; |
143 | 138 | ||
144 | /* Use power settings for Vcc and Vpp if present */ | 139 | return pcmcia_request_io(p_dev); |
145 | /* Note that the CIS values need to be rescaled */ | ||
146 | if (cfg->vcc.present & (1<<CISTPL_POWER_VNOM)) { | ||
147 | if (cfg->vcc.param[CISTPL_POWER_VNOM]/10000 != vcc) | ||
148 | return -ENODEV; | ||
149 | } else if (dflt->vcc.present & (1<<CISTPL_POWER_VNOM)) { | ||
150 | if (dflt->vcc.param[CISTPL_POWER_VNOM]/10000 != vcc) | ||
151 | return -ENODEV; | ||
152 | } | ||
153 | |||
154 | if (cfg->vpp1.present & (1<<CISTPL_POWER_VNOM)) | ||
155 | p_dev->conf.Vpp = | ||
156 | cfg->vpp1.param[CISTPL_POWER_VNOM]/10000; | ||
157 | else if (dflt->vpp1.present & (1<<CISTPL_POWER_VNOM)) | ||
158 | p_dev->conf.Vpp = | ||
159 | dflt->vpp1.param[CISTPL_POWER_VNOM]/10000; | ||
160 | |||
161 | /* we need an interrupt */ | ||
162 | p_dev->conf.Attributes |= CONF_ENABLE_IRQ; | ||
163 | |||
164 | /* IO window settings */ | ||
165 | p_dev->resource[0]->end = p_dev->resource[1]->end = 0; | ||
166 | if ((cfg->io.nwin > 0) || (dflt->io.nwin > 0)) { | ||
167 | cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt->io; | ||
168 | p_dev->io_lines = io->flags & CISTPL_IO_LINES_MASK; | ||
169 | |||
170 | p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8; | ||
171 | p_dev->resource[0]->start = io->win[0].base; | ||
172 | p_dev->resource[0]->end = io->win[0].len; | ||
173 | |||
174 | return pcmcia_request_io(p_dev); | ||
175 | } | ||
176 | pcmcia_disable_device(p_dev); | ||
177 | return -ENODEV; | ||
178 | } | 140 | } |
179 | 141 | ||
180 | 142 | ||
@@ -185,6 +147,9 @@ static int sl811_cs_config(struct pcmcia_device *link) | |||
185 | 147 | ||
186 | dev_dbg(&link->dev, "sl811_cs_config\n"); | 148 | dev_dbg(&link->dev, "sl811_cs_config\n"); |
187 | 149 | ||
150 | link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_VPP | | ||
151 | CONF_AUTO_CHECK_VCC | CONF_AUTO_SET_IO; | ||
152 | |||
188 | if (pcmcia_loop_config(link, sl811_cs_config_check, NULL)) | 153 | if (pcmcia_loop_config(link, sl811_cs_config_check, NULL)) |
189 | goto failed; | 154 | goto failed; |
190 | 155 | ||
@@ -195,18 +160,10 @@ static int sl811_cs_config(struct pcmcia_device *link) | |||
195 | if (!link->irq) | 160 | if (!link->irq) |
196 | goto failed; | 161 | goto failed; |
197 | 162 | ||
198 | ret = pcmcia_request_configuration(link, &link->conf); | 163 | ret = pcmcia_enable_device(link); |
199 | if (ret) | 164 | if (ret) |
200 | goto failed; | 165 | goto failed; |
201 | 166 | ||
202 | dev_info(&link->dev, "index 0x%02x: ", | ||
203 | link->conf.ConfigIndex); | ||
204 | if (link->conf.Vpp) | ||
205 | printk(", Vpp %d.%d", link->conf.Vpp/10, link->conf.Vpp%10); | ||
206 | printk(", irq %d", link->irq); | ||
207 | printk(", io %pR", link->resource[0]); | ||
208 | printk("\n"); | ||
209 | |||
210 | if (sl811_hc_init(parent, link->resource[0]->start, link->irq) | 167 | if (sl811_hc_init(parent, link->resource[0]->start, link->irq) |
211 | < 0) { | 168 | < 0) { |
212 | failed: | 169 | failed: |
@@ -227,13 +184,10 @@ static int sl811_cs_probe(struct pcmcia_device *link) | |||
227 | local->p_dev = link; | 184 | local->p_dev = link; |
228 | link->priv = local; | 185 | link->priv = local; |
229 | 186 | ||
230 | link->conf.Attributes = 0; | ||
231 | link->conf.IntType = INT_MEMORY_AND_IO; | ||
232 | |||
233 | return sl811_cs_config(link); | 187 | return sl811_cs_config(link); |
234 | } | 188 | } |
235 | 189 | ||
236 | static struct pcmcia_device_id sl811_ids[] = { | 190 | static const struct pcmcia_device_id sl811_ids[] = { |
237 | PCMCIA_DEVICE_MANF_CARD(0xc015, 0x0001), /* RATOC USB HOST CF+ Card */ | 191 | PCMCIA_DEVICE_MANF_CARD(0xc015, 0x0001), /* RATOC USB HOST CF+ Card */ |
238 | PCMCIA_DEVICE_NULL, | 192 | PCMCIA_DEVICE_NULL, |
239 | }; | 193 | }; |
@@ -241,9 +195,7 @@ MODULE_DEVICE_TABLE(pcmcia, sl811_ids); | |||
241 | 195 | ||
242 | static struct pcmcia_driver sl811_cs_driver = { | 196 | static struct pcmcia_driver sl811_cs_driver = { |
243 | .owner = THIS_MODULE, | 197 | .owner = THIS_MODULE, |
244 | .drv = { | 198 | .name = "sl811_cs", |
245 | .name = "sl811_cs", | ||
246 | }, | ||
247 | .probe = sl811_cs_probe, | 199 | .probe = sl811_cs_probe, |
248 | .remove = sl811_cs_detach, | 200 | .remove = sl811_cs_detach, |
249 | .id_table = sl811_ids, | 201 | .id_table = sl811_ids, |
diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c index 5b31bae92dbc..533d12cca371 100644 --- a/drivers/usb/host/u132-hcd.c +++ b/drivers/usb/host/u132-hcd.c | |||
@@ -316,7 +316,6 @@ static void u132_ring_requeue_work(struct u132 *u132, struct u132_ring *ring, | |||
316 | } else if (queue_delayed_work(workqueue, &ring->scheduler, 0)) | 316 | } else if (queue_delayed_work(workqueue, &ring->scheduler, 0)) |
317 | return; | 317 | return; |
318 | kref_put(&u132->kref, u132_hcd_delete); | 318 | kref_put(&u132->kref, u132_hcd_delete); |
319 | return; | ||
320 | } | 319 | } |
321 | 320 | ||
322 | static void u132_ring_queue_work(struct u132 *u132, struct u132_ring *ring, | 321 | static void u132_ring_queue_work(struct u132 *u132, struct u132_ring *ring, |
@@ -324,7 +323,6 @@ static void u132_ring_queue_work(struct u132 *u132, struct u132_ring *ring, | |||
324 | { | 323 | { |
325 | kref_get(&u132->kref); | 324 | kref_get(&u132->kref); |
326 | u132_ring_requeue_work(u132, ring, delta); | 325 | u132_ring_requeue_work(u132, ring, delta); |
327 | return; | ||
328 | } | 326 | } |
329 | 327 | ||
330 | static void u132_ring_cancel_work(struct u132 *u132, struct u132_ring *ring) | 328 | static void u132_ring_cancel_work(struct u132 *u132, struct u132_ring *ring) |
@@ -543,7 +541,6 @@ static void u132_hcd_giveback_urb(struct u132 *u132, struct u132_endp *endp, | |||
543 | mutex_unlock(&u132->scheduler_lock); | 541 | mutex_unlock(&u132->scheduler_lock); |
544 | u132_endp_put_kref(u132, endp); | 542 | u132_endp_put_kref(u132, endp); |
545 | usb_hcd_giveback_urb(hcd, urb, status); | 543 | usb_hcd_giveback_urb(hcd, urb, status); |
546 | return; | ||
547 | } | 544 | } |
548 | 545 | ||
549 | static void u132_hcd_forget_urb(struct u132 *u132, struct u132_endp *endp, | 546 | static void u132_hcd_forget_urb(struct u132 *u132, struct u132_endp *endp, |
@@ -574,8 +571,8 @@ static void u132_hcd_abandon_urb(struct u132 *u132, struct u132_endp *endp, | |||
574 | endp->active = 0; | 571 | endp->active = 0; |
575 | spin_unlock_irqrestore(&endp->queue_lock.slock, irqs); | 572 | spin_unlock_irqrestore(&endp->queue_lock.slock, irqs); |
576 | kfree(urbq); | 573 | kfree(urbq); |
577 | } usb_hcd_giveback_urb(hcd, urb, status); | 574 | } |
578 | return; | 575 | usb_hcd_giveback_urb(hcd, urb, status); |
579 | } | 576 | } |
580 | 577 | ||
581 | static inline int edset_input(struct u132 *u132, struct u132_ring *ring, | 578 | static inline int edset_input(struct u132 *u132, struct u132_ring *ring, |
@@ -2607,13 +2604,14 @@ static int u132_roothub_descriptor(struct u132 *u132, | |||
2607 | retval = u132_read_pcimem(u132, roothub.b, &rh_b); | 2604 | retval = u132_read_pcimem(u132, roothub.b, &rh_b); |
2608 | if (retval) | 2605 | if (retval) |
2609 | return retval; | 2606 | return retval; |
2610 | memset(desc->bitmap, 0xff, sizeof(desc->bitmap)); | 2607 | memset(desc->u.hs.DeviceRemovable, 0xff, |
2611 | desc->bitmap[0] = rh_b & RH_B_DR; | 2608 | sizeof(desc->u.hs.DeviceRemovable)); |
2609 | desc->u.hs.DeviceRemovable[0] = rh_b & RH_B_DR; | ||
2612 | if (u132->num_ports > 7) { | 2610 | if (u132->num_ports > 7) { |
2613 | desc->bitmap[1] = (rh_b & RH_B_DR) >> 8; | 2611 | desc->u.hs.DeviceRemovable[1] = (rh_b & RH_B_DR) >> 8; |
2614 | desc->bitmap[2] = 0xff; | 2612 | desc->u.hs.DeviceRemovable[2] = 0xff; |
2615 | } else | 2613 | } else |
2616 | desc->bitmap[1] = 0xff; | 2614 | desc->u.hs.DeviceRemovable[1] = 0xff; |
2617 | return 0; | 2615 | return 0; |
2618 | } | 2616 | } |
2619 | 2617 | ||
@@ -3085,7 +3083,6 @@ static void u132_initialise(struct u132 *u132, struct platform_device *pdev) | |||
3085 | u132->endp[endps] = NULL; | 3083 | u132->endp[endps] = NULL; |
3086 | 3084 | ||
3087 | mutex_unlock(&u132->sw_lock); | 3085 | mutex_unlock(&u132->sw_lock); |
3088 | return; | ||
3089 | } | 3086 | } |
3090 | 3087 | ||
3091 | static int __devinit u132_probe(struct platform_device *pdev) | 3088 | static int __devinit u132_probe(struct platform_device *pdev) |
@@ -3233,8 +3230,7 @@ static int __init u132_hcd_init(void) | |||
3233 | mutex_init(&u132_module_lock); | 3230 | mutex_init(&u132_module_lock); |
3234 | if (usb_disabled()) | 3231 | if (usb_disabled()) |
3235 | return -ENODEV; | 3232 | return -ENODEV; |
3236 | printk(KERN_INFO "driver %s built at %s on %s\n", hcd_name, __TIME__, | 3233 | printk(KERN_INFO "driver %s\n", hcd_name); |
3237 | __DATE__); | ||
3238 | workqueue = create_singlethread_workqueue("u132"); | 3234 | workqueue = create_singlethread_workqueue("u132"); |
3239 | retval = platform_driver_register(&u132_platform_driver); | 3235 | retval = platform_driver_register(&u132_platform_driver); |
3240 | return retval; | 3236 | return retval; |
diff --git a/drivers/usb/host/uhci-debug.c b/drivers/usb/host/uhci-debug.c index 6e7fb5f38db6..fc0b0daac93d 100644 --- a/drivers/usb/host/uhci-debug.c +++ b/drivers/usb/host/uhci-debug.c | |||
@@ -12,7 +12,6 @@ | |||
12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/debugfs.h> | 14 | #include <linux/debugfs.h> |
15 | #include <linux/smp_lock.h> | ||
16 | #include <asm/io.h> | 15 | #include <asm/io.h> |
17 | 16 | ||
18 | #include "uhci-hcd.h" | 17 | #include "uhci-hcd.h" |
@@ -38,7 +37,8 @@ static void lprintk(char *buf) | |||
38 | } | 37 | } |
39 | } | 38 | } |
40 | 39 | ||
41 | static int uhci_show_td(struct uhci_td *td, char *buf, int len, int space) | 40 | static int uhci_show_td(struct uhci_hcd *uhci, struct uhci_td *td, char *buf, |
41 | int len, int space) | ||
42 | { | 42 | { |
43 | char *out = buf; | 43 | char *out = buf; |
44 | char *spid; | 44 | char *spid; |
@@ -48,8 +48,9 @@ static int uhci_show_td(struct uhci_td *td, char *buf, int len, int space) | |||
48 | if (len < 160) | 48 | if (len < 160) |
49 | return 0; | 49 | return 0; |
50 | 50 | ||
51 | status = td_status(td); | 51 | status = td_status(uhci, td); |
52 | out += sprintf(out, "%*s[%p] link (%08x) ", space, "", td, le32_to_cpu(td->link)); | 52 | out += sprintf(out, "%*s[%p] link (%08x) ", space, "", td, |
53 | hc32_to_cpu(uhci, td->link)); | ||
53 | out += sprintf(out, "e%d %s%s%s%s%s%s%s%s%s%sLength=%x ", | 54 | out += sprintf(out, "e%d %s%s%s%s%s%s%s%s%s%sLength=%x ", |
54 | ((status >> 27) & 3), | 55 | ((status >> 27) & 3), |
55 | (status & TD_CTRL_SPD) ? "SPD " : "", | 56 | (status & TD_CTRL_SPD) ? "SPD " : "", |
@@ -64,7 +65,7 @@ static int uhci_show_td(struct uhci_td *td, char *buf, int len, int space) | |||
64 | (status & TD_CTRL_BITSTUFF) ? "BitStuff " : "", | 65 | (status & TD_CTRL_BITSTUFF) ? "BitStuff " : "", |
65 | status & 0x7ff); | 66 | status & 0x7ff); |
66 | 67 | ||
67 | token = td_token(td); | 68 | token = td_token(uhci, td); |
68 | switch (uhci_packetid(token)) { | 69 | switch (uhci_packetid(token)) { |
69 | case USB_PID_SETUP: | 70 | case USB_PID_SETUP: |
70 | spid = "SETUP"; | 71 | spid = "SETUP"; |
@@ -87,12 +88,13 @@ static int uhci_show_td(struct uhci_td *td, char *buf, int len, int space) | |||
87 | (token >> 8) & 127, | 88 | (token >> 8) & 127, |
88 | (token & 0xff), | 89 | (token & 0xff), |
89 | spid); | 90 | spid); |
90 | out += sprintf(out, "(buf=%08x)\n", le32_to_cpu(td->buffer)); | 91 | out += sprintf(out, "(buf=%08x)\n", hc32_to_cpu(uhci, td->buffer)); |
91 | 92 | ||
92 | return out - buf; | 93 | return out - buf; |
93 | } | 94 | } |
94 | 95 | ||
95 | static int uhci_show_urbp(struct urb_priv *urbp, char *buf, int len, int space) | 96 | static int uhci_show_urbp(struct uhci_hcd *uhci, struct urb_priv *urbp, |
97 | char *buf, int len, int space) | ||
96 | { | 98 | { |
97 | char *out = buf; | 99 | char *out = buf; |
98 | struct uhci_td *td; | 100 | struct uhci_td *td; |
@@ -131,9 +133,10 @@ static int uhci_show_urbp(struct urb_priv *urbp, char *buf, int len, int space) | |||
131 | if (urbp->qh->type != USB_ENDPOINT_XFER_ISOC && | 133 | if (urbp->qh->type != USB_ENDPOINT_XFER_ISOC && |
132 | (++i <= 10 || debug > 2)) { | 134 | (++i <= 10 || debug > 2)) { |
133 | out += sprintf(out, "%*s%d: ", space + 2, "", i); | 135 | out += sprintf(out, "%*s%d: ", space + 2, "", i); |
134 | out += uhci_show_td(td, out, len - (out - buf), 0); | 136 | out += uhci_show_td(uhci, td, out, |
137 | len - (out - buf), 0); | ||
135 | } else { | 138 | } else { |
136 | if (td_status(td) & TD_CTRL_ACTIVE) | 139 | if (td_status(uhci, td) & TD_CTRL_ACTIVE) |
137 | ++nactive; | 140 | ++nactive; |
138 | else | 141 | else |
139 | ++ninactive; | 142 | ++ninactive; |
@@ -152,7 +155,7 @@ static int uhci_show_qh(struct uhci_hcd *uhci, | |||
152 | { | 155 | { |
153 | char *out = buf; | 156 | char *out = buf; |
154 | int i, nurbs; | 157 | int i, nurbs; |
155 | __le32 element = qh_element(qh); | 158 | __hc32 element = qh_element(qh); |
156 | char *qtype; | 159 | char *qtype; |
157 | 160 | ||
158 | /* Try to make sure there's enough memory */ | 161 | /* Try to make sure there's enough memory */ |
@@ -169,7 +172,8 @@ static int uhci_show_qh(struct uhci_hcd *uhci, | |||
169 | 172 | ||
170 | out += sprintf(out, "%*s[%p] %s QH link (%08x) element (%08x)\n", | 173 | out += sprintf(out, "%*s[%p] %s QH link (%08x) element (%08x)\n", |
171 | space, "", qh, qtype, | 174 | space, "", qh, qtype, |
172 | le32_to_cpu(qh->link), le32_to_cpu(element)); | 175 | hc32_to_cpu(uhci, qh->link), |
176 | hc32_to_cpu(uhci, element)); | ||
173 | if (qh->type == USB_ENDPOINT_XFER_ISOC) | 177 | if (qh->type == USB_ENDPOINT_XFER_ISOC) |
174 | out += sprintf(out, "%*s period %d phase %d load %d us, " | 178 | out += sprintf(out, "%*s period %d phase %d load %d us, " |
175 | "frame %x desc [%p]\n", | 179 | "frame %x desc [%p]\n", |
@@ -179,22 +183,22 @@ static int uhci_show_qh(struct uhci_hcd *uhci, | |||
179 | out += sprintf(out, "%*s period %d phase %d load %d us\n", | 183 | out += sprintf(out, "%*s period %d phase %d load %d us\n", |
180 | space, "", qh->period, qh->phase, qh->load); | 184 | space, "", qh->period, qh->phase, qh->load); |
181 | 185 | ||
182 | if (element & UHCI_PTR_QH) | 186 | if (element & UHCI_PTR_QH(uhci)) |
183 | out += sprintf(out, "%*s Element points to QH (bug?)\n", space, ""); | 187 | out += sprintf(out, "%*s Element points to QH (bug?)\n", space, ""); |
184 | 188 | ||
185 | if (element & UHCI_PTR_DEPTH) | 189 | if (element & UHCI_PTR_DEPTH(uhci)) |
186 | out += sprintf(out, "%*s Depth traverse\n", space, ""); | 190 | out += sprintf(out, "%*s Depth traverse\n", space, ""); |
187 | 191 | ||
188 | if (element & cpu_to_le32(8)) | 192 | if (element & cpu_to_hc32(uhci, 8)) |
189 | out += sprintf(out, "%*s Bit 3 set (bug?)\n", space, ""); | 193 | out += sprintf(out, "%*s Bit 3 set (bug?)\n", space, ""); |
190 | 194 | ||
191 | if (!(element & ~(UHCI_PTR_QH | UHCI_PTR_DEPTH))) | 195 | if (!(element & ~(UHCI_PTR_QH(uhci) | UHCI_PTR_DEPTH(uhci)))) |
192 | out += sprintf(out, "%*s Element is NULL (bug?)\n", space, ""); | 196 | out += sprintf(out, "%*s Element is NULL (bug?)\n", space, ""); |
193 | 197 | ||
194 | if (list_empty(&qh->queue)) { | 198 | if (list_empty(&qh->queue)) { |
195 | out += sprintf(out, "%*s queue is empty\n", space, ""); | 199 | out += sprintf(out, "%*s queue is empty\n", space, ""); |
196 | if (qh == uhci->skel_async_qh) | 200 | if (qh == uhci->skel_async_qh) |
197 | out += uhci_show_td(uhci->term_td, out, | 201 | out += uhci_show_td(uhci, uhci->term_td, out, |
198 | len - (out - buf), 0); | 202 | len - (out - buf), 0); |
199 | } else { | 203 | } else { |
200 | struct urb_priv *urbp = list_entry(qh->queue.next, | 204 | struct urb_priv *urbp = list_entry(qh->queue.next, |
@@ -202,13 +206,13 @@ static int uhci_show_qh(struct uhci_hcd *uhci, | |||
202 | struct uhci_td *td = list_entry(urbp->td_list.next, | 206 | struct uhci_td *td = list_entry(urbp->td_list.next, |
203 | struct uhci_td, list); | 207 | struct uhci_td, list); |
204 | 208 | ||
205 | if (element != LINK_TO_TD(td)) | 209 | if (element != LINK_TO_TD(uhci, td)) |
206 | out += sprintf(out, "%*s Element != First TD\n", | 210 | out += sprintf(out, "%*s Element != First TD\n", |
207 | space, ""); | 211 | space, ""); |
208 | i = nurbs = 0; | 212 | i = nurbs = 0; |
209 | list_for_each_entry(urbp, &qh->queue, node) { | 213 | list_for_each_entry(urbp, &qh->queue, node) { |
210 | if (++i <= 10) | 214 | if (++i <= 10) |
211 | out += uhci_show_urbp(urbp, out, | 215 | out += uhci_show_urbp(uhci, urbp, out, |
212 | len - (out - buf), space + 2); | 216 | len - (out - buf), space + 2); |
213 | else | 217 | else |
214 | ++nurbs; | 218 | ++nurbs; |
@@ -220,7 +224,8 @@ static int uhci_show_qh(struct uhci_hcd *uhci, | |||
220 | 224 | ||
221 | if (qh->dummy_td) { | 225 | if (qh->dummy_td) { |
222 | out += sprintf(out, "%*s Dummy TD\n", space, ""); | 226 | out += sprintf(out, "%*s Dummy TD\n", space, ""); |
223 | out += uhci_show_td(qh->dummy_td, out, len - (out - buf), 0); | 227 | out += uhci_show_td(uhci, qh->dummy_td, out, |
228 | len - (out - buf), 0); | ||
224 | } | 229 | } |
225 | 230 | ||
226 | return out - buf; | 231 | return out - buf; |
@@ -286,7 +291,6 @@ static int uhci_show_root_hub_state(struct uhci_hcd *uhci, char *buf, int len) | |||
286 | static int uhci_show_status(struct uhci_hcd *uhci, char *buf, int len) | 291 | static int uhci_show_status(struct uhci_hcd *uhci, char *buf, int len) |
287 | { | 292 | { |
288 | char *out = buf; | 293 | char *out = buf; |
289 | unsigned long io_addr = uhci->io_addr; | ||
290 | unsigned short usbcmd, usbstat, usbint, usbfrnum; | 294 | unsigned short usbcmd, usbstat, usbint, usbfrnum; |
291 | unsigned int flbaseadd; | 295 | unsigned int flbaseadd; |
292 | unsigned char sof; | 296 | unsigned char sof; |
@@ -296,14 +300,14 @@ static int uhci_show_status(struct uhci_hcd *uhci, char *buf, int len) | |||
296 | if (len < 80 * 9) | 300 | if (len < 80 * 9) |
297 | return 0; | 301 | return 0; |
298 | 302 | ||
299 | usbcmd = inw(io_addr + 0); | 303 | usbcmd = uhci_readw(uhci, 0); |
300 | usbstat = inw(io_addr + 2); | 304 | usbstat = uhci_readw(uhci, 2); |
301 | usbint = inw(io_addr + 4); | 305 | usbint = uhci_readw(uhci, 4); |
302 | usbfrnum = inw(io_addr + 6); | 306 | usbfrnum = uhci_readw(uhci, 6); |
303 | flbaseadd = inl(io_addr + 8); | 307 | flbaseadd = uhci_readl(uhci, 8); |
304 | sof = inb(io_addr + 12); | 308 | sof = uhci_readb(uhci, 12); |
305 | portsc1 = inw(io_addr + 16); | 309 | portsc1 = uhci_readw(uhci, 16); |
306 | portsc2 = inw(io_addr + 18); | 310 | portsc2 = uhci_readw(uhci, 18); |
307 | 311 | ||
308 | out += sprintf(out, " usbcmd = %04x %s%s%s%s%s%s%s%s\n", | 312 | out += sprintf(out, " usbcmd = %04x %s%s%s%s%s%s%s%s\n", |
309 | usbcmd, | 313 | usbcmd, |
@@ -348,8 +352,8 @@ static int uhci_sprint_schedule(struct uhci_hcd *uhci, char *buf, int len) | |||
348 | struct uhci_td *td; | 352 | struct uhci_td *td; |
349 | struct list_head *tmp, *head; | 353 | struct list_head *tmp, *head; |
350 | int nframes, nerrs; | 354 | int nframes, nerrs; |
351 | __le32 link; | 355 | __hc32 link; |
352 | __le32 fsbr_link; | 356 | __hc32 fsbr_link; |
353 | 357 | ||
354 | static const char * const qh_names[] = { | 358 | static const char * const qh_names[] = { |
355 | "unlink", "iso", "int128", "int64", "int32", "int16", | 359 | "unlink", "iso", "int128", "int64", "int32", "int16", |
@@ -377,7 +381,7 @@ static int uhci_sprint_schedule(struct uhci_hcd *uhci, char *buf, int len) | |||
377 | nframes = 10; | 381 | nframes = 10; |
378 | nerrs = 0; | 382 | nerrs = 0; |
379 | for (i = 0; i < UHCI_NUMFRAMES; ++i) { | 383 | for (i = 0; i < UHCI_NUMFRAMES; ++i) { |
380 | __le32 qh_dma; | 384 | __hc32 qh_dma; |
381 | 385 | ||
382 | j = 0; | 386 | j = 0; |
383 | td = uhci->frame_cpu[i]; | 387 | td = uhci->frame_cpu[i]; |
@@ -387,7 +391,7 @@ static int uhci_sprint_schedule(struct uhci_hcd *uhci, char *buf, int len) | |||
387 | 391 | ||
388 | if (nframes > 0) { | 392 | if (nframes > 0) { |
389 | out += sprintf(out, "- Frame %d -> (%08x)\n", | 393 | out += sprintf(out, "- Frame %d -> (%08x)\n", |
390 | i, le32_to_cpu(link)); | 394 | i, hc32_to_cpu(uhci, link)); |
391 | j = 1; | 395 | j = 1; |
392 | } | 396 | } |
393 | 397 | ||
@@ -396,7 +400,7 @@ static int uhci_sprint_schedule(struct uhci_hcd *uhci, char *buf, int len) | |||
396 | do { | 400 | do { |
397 | td = list_entry(tmp, struct uhci_td, fl_list); | 401 | td = list_entry(tmp, struct uhci_td, fl_list); |
398 | tmp = tmp->next; | 402 | tmp = tmp->next; |
399 | if (link != LINK_TO_TD(td)) { | 403 | if (link != LINK_TO_TD(uhci, td)) { |
400 | if (nframes > 0) | 404 | if (nframes > 0) |
401 | out += sprintf(out, " link does " | 405 | out += sprintf(out, " link does " |
402 | "not match list entry!\n"); | 406 | "not match list entry!\n"); |
@@ -404,7 +408,7 @@ static int uhci_sprint_schedule(struct uhci_hcd *uhci, char *buf, int len) | |||
404 | ++nerrs; | 408 | ++nerrs; |
405 | } | 409 | } |
406 | if (nframes > 0) | 410 | if (nframes > 0) |
407 | out += uhci_show_td(td, out, | 411 | out += uhci_show_td(uhci, td, out, |
408 | len - (out - buf), 4); | 412 | len - (out - buf), 4); |
409 | link = td->link; | 413 | link = td->link; |
410 | } while (tmp != head); | 414 | } while (tmp != head); |
@@ -416,11 +420,12 @@ check_link: | |||
416 | if (!j) { | 420 | if (!j) { |
417 | out += sprintf(out, | 421 | out += sprintf(out, |
418 | "- Frame %d -> (%08x)\n", | 422 | "- Frame %d -> (%08x)\n", |
419 | i, le32_to_cpu(link)); | 423 | i, hc32_to_cpu(uhci, link)); |
420 | j = 1; | 424 | j = 1; |
421 | } | 425 | } |
422 | out += sprintf(out, " link does not match " | 426 | out += sprintf(out, " link does not match " |
423 | "QH (%08x)!\n", le32_to_cpu(qh_dma)); | 427 | "QH (%08x)!\n", |
428 | hc32_to_cpu(uhci, qh_dma)); | ||
424 | } else | 429 | } else |
425 | ++nerrs; | 430 | ++nerrs; |
426 | } | 431 | } |
@@ -441,11 +446,11 @@ check_link: | |||
441 | 446 | ||
442 | /* Last QH is the Terminating QH, it's different */ | 447 | /* Last QH is the Terminating QH, it's different */ |
443 | if (i == SKEL_TERM) { | 448 | if (i == SKEL_TERM) { |
444 | if (qh_element(qh) != LINK_TO_TD(uhci->term_td)) | 449 | if (qh_element(qh) != LINK_TO_TD(uhci, uhci->term_td)) |
445 | out += sprintf(out, " skel_term_qh element is not set to term_td!\n"); | 450 | out += sprintf(out, " skel_term_qh element is not set to term_td!\n"); |
446 | link = fsbr_link; | 451 | link = fsbr_link; |
447 | if (!link) | 452 | if (!link) |
448 | link = LINK_TO_QH(uhci->skel_term_qh); | 453 | link = LINK_TO_QH(uhci, uhci->skel_term_qh); |
449 | goto check_qh_link; | 454 | goto check_qh_link; |
450 | } | 455 | } |
451 | 456 | ||
@@ -459,20 +464,20 @@ check_link: | |||
459 | out += uhci_show_qh(uhci, qh, out, | 464 | out += uhci_show_qh(uhci, qh, out, |
460 | len - (out - buf), 4); | 465 | len - (out - buf), 4); |
461 | if (!fsbr_link && qh->skel >= SKEL_FSBR) | 466 | if (!fsbr_link && qh->skel >= SKEL_FSBR) |
462 | fsbr_link = LINK_TO_QH(qh); | 467 | fsbr_link = LINK_TO_QH(uhci, qh); |
463 | } | 468 | } |
464 | if ((cnt -= 10) > 0) | 469 | if ((cnt -= 10) > 0) |
465 | out += sprintf(out, " Skipped %d QHs\n", cnt); | 470 | out += sprintf(out, " Skipped %d QHs\n", cnt); |
466 | 471 | ||
467 | link = UHCI_PTR_TERM; | 472 | link = UHCI_PTR_TERM(uhci); |
468 | if (i <= SKEL_ISO) | 473 | if (i <= SKEL_ISO) |
469 | ; | 474 | ; |
470 | else if (i < SKEL_ASYNC) | 475 | else if (i < SKEL_ASYNC) |
471 | link = LINK_TO_QH(uhci->skel_async_qh); | 476 | link = LINK_TO_QH(uhci, uhci->skel_async_qh); |
472 | else if (!uhci->fsbr_is_on) | 477 | else if (!uhci->fsbr_is_on) |
473 | ; | 478 | ; |
474 | else | 479 | else |
475 | link = LINK_TO_QH(uhci->skel_term_qh); | 480 | link = LINK_TO_QH(uhci, uhci->skel_term_qh); |
476 | check_qh_link: | 481 | check_qh_link: |
477 | if (qh->link != link) | 482 | if (qh->link != link) |
478 | out += sprintf(out, " last QH not linked to next skeleton!\n"); | 483 | out += sprintf(out, " last QH not linked to next skeleton!\n"); |
diff --git a/drivers/usb/host/uhci-grlib.c b/drivers/usb/host/uhci-grlib.c new file mode 100644 index 000000000000..d01c1e227681 --- /dev/null +++ b/drivers/usb/host/uhci-grlib.c | |||
@@ -0,0 +1,208 @@ | |||
1 | /* | ||
2 | * UHCI HCD (Host Controller Driver) for GRLIB GRUSBHC | ||
3 | * | ||
4 | * Copyright (c) 2011 Jan Andersson <jan@gaisler.com> | ||
5 | * | ||
6 | * This file is based on UHCI PCI HCD: | ||
7 | * (C) Copyright 1999 Linus Torvalds | ||
8 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | ||
9 | * (C) Copyright 1999 Randy Dunlap | ||
10 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | ||
11 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | ||
12 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | ||
13 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | ||
14 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | ||
15 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | ||
16 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | ||
17 | * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu | ||
18 | */ | ||
19 | |||
20 | #include <linux/of_irq.h> | ||
21 | #include <linux/of_address.h> | ||
22 | #include <linux/of_platform.h> | ||
23 | |||
24 | static int uhci_grlib_init(struct usb_hcd *hcd) | ||
25 | { | ||
26 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
27 | |||
28 | /* | ||
29 | * Probe to determine the endianness of the controller. | ||
30 | * We know that bit 7 of the PORTSC1 register is always set | ||
31 | * and bit 15 is always clear. If uhci_readw() yields a value | ||
32 | * with bit 7 (0x80) turned on then the current little-endian | ||
33 | * setting is correct. Otherwise we assume the value was | ||
34 | * byte-swapped; hence the register interface and presumably | ||
35 | * also the descriptors are big-endian. | ||
36 | */ | ||
37 | if (!(uhci_readw(uhci, USBPORTSC1) & 0x80)) { | ||
38 | uhci->big_endian_mmio = 1; | ||
39 | uhci->big_endian_desc = 1; | ||
40 | } | ||
41 | |||
42 | uhci->rh_numports = uhci_count_ports(hcd); | ||
43 | |||
44 | /* Set up pointers to to generic functions */ | ||
45 | uhci->reset_hc = uhci_generic_reset_hc; | ||
46 | uhci->check_and_reset_hc = uhci_generic_check_and_reset_hc; | ||
47 | /* No special actions need to be taken for the functions below */ | ||
48 | uhci->configure_hc = NULL; | ||
49 | uhci->resume_detect_interrupts_are_broken = NULL; | ||
50 | uhci->global_suspend_mode_is_broken = NULL; | ||
51 | |||
52 | /* Reset if the controller isn't already safely quiescent. */ | ||
53 | check_and_reset_hc(uhci); | ||
54 | return 0; | ||
55 | } | ||
56 | |||
57 | static const struct hc_driver uhci_grlib_hc_driver = { | ||
58 | .description = hcd_name, | ||
59 | .product_desc = "GRLIB GRUSBHC UHCI Host Controller", | ||
60 | .hcd_priv_size = sizeof(struct uhci_hcd), | ||
61 | |||
62 | /* Generic hardware linkage */ | ||
63 | .irq = uhci_irq, | ||
64 | .flags = HCD_MEMORY | HCD_USB11, | ||
65 | |||
66 | /* Basic lifecycle operations */ | ||
67 | .reset = uhci_grlib_init, | ||
68 | .start = uhci_start, | ||
69 | #ifdef CONFIG_PM | ||
70 | .pci_suspend = NULL, | ||
71 | .pci_resume = NULL, | ||
72 | .bus_suspend = uhci_rh_suspend, | ||
73 | .bus_resume = uhci_rh_resume, | ||
74 | #endif | ||
75 | .stop = uhci_stop, | ||
76 | |||
77 | .urb_enqueue = uhci_urb_enqueue, | ||
78 | .urb_dequeue = uhci_urb_dequeue, | ||
79 | |||
80 | .endpoint_disable = uhci_hcd_endpoint_disable, | ||
81 | .get_frame_number = uhci_hcd_get_frame_number, | ||
82 | |||
83 | .hub_status_data = uhci_hub_status_data, | ||
84 | .hub_control = uhci_hub_control, | ||
85 | }; | ||
86 | |||
87 | |||
88 | static int __devinit uhci_hcd_grlib_probe(struct platform_device *op) | ||
89 | { | ||
90 | struct device_node *dn = op->dev.of_node; | ||
91 | struct usb_hcd *hcd; | ||
92 | struct uhci_hcd *uhci = NULL; | ||
93 | struct resource res; | ||
94 | int irq; | ||
95 | int rv; | ||
96 | |||
97 | if (usb_disabled()) | ||
98 | return -ENODEV; | ||
99 | |||
100 | dev_dbg(&op->dev, "initializing GRUSBHC UHCI USB Controller\n"); | ||
101 | |||
102 | rv = of_address_to_resource(dn, 0, &res); | ||
103 | if (rv) | ||
104 | return rv; | ||
105 | |||
106 | /* usb_create_hcd requires dma_mask != NULL */ | ||
107 | op->dev.dma_mask = &op->dev.coherent_dma_mask; | ||
108 | hcd = usb_create_hcd(&uhci_grlib_hc_driver, &op->dev, | ||
109 | "GRUSBHC UHCI USB"); | ||
110 | if (!hcd) | ||
111 | return -ENOMEM; | ||
112 | |||
113 | hcd->rsrc_start = res.start; | ||
114 | hcd->rsrc_len = res.end - res.start + 1; | ||
115 | |||
116 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | ||
117 | printk(KERN_ERR "%s: request_mem_region failed\n", __FILE__); | ||
118 | rv = -EBUSY; | ||
119 | goto err_rmr; | ||
120 | } | ||
121 | |||
122 | irq = irq_of_parse_and_map(dn, 0); | ||
123 | if (irq == NO_IRQ) { | ||
124 | printk(KERN_ERR "%s: irq_of_parse_and_map failed\n", __FILE__); | ||
125 | rv = -EBUSY; | ||
126 | goto err_irq; | ||
127 | } | ||
128 | |||
129 | hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); | ||
130 | if (!hcd->regs) { | ||
131 | printk(KERN_ERR "%s: ioremap failed\n", __FILE__); | ||
132 | rv = -ENOMEM; | ||
133 | goto err_ioremap; | ||
134 | } | ||
135 | |||
136 | uhci = hcd_to_uhci(hcd); | ||
137 | |||
138 | uhci->regs = hcd->regs; | ||
139 | |||
140 | rv = usb_add_hcd(hcd, irq, 0); | ||
141 | if (rv) | ||
142 | goto err_uhci; | ||
143 | |||
144 | return 0; | ||
145 | |||
146 | err_uhci: | ||
147 | iounmap(hcd->regs); | ||
148 | err_ioremap: | ||
149 | irq_dispose_mapping(irq); | ||
150 | err_irq: | ||
151 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
152 | err_rmr: | ||
153 | usb_put_hcd(hcd); | ||
154 | |||
155 | return rv; | ||
156 | } | ||
157 | |||
158 | static int uhci_hcd_grlib_remove(struct platform_device *op) | ||
159 | { | ||
160 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); | ||
161 | |||
162 | dev_set_drvdata(&op->dev, NULL); | ||
163 | |||
164 | dev_dbg(&op->dev, "stopping GRLIB GRUSBHC UHCI USB Controller\n"); | ||
165 | |||
166 | usb_remove_hcd(hcd); | ||
167 | |||
168 | iounmap(hcd->regs); | ||
169 | irq_dispose_mapping(hcd->irq); | ||
170 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | ||
171 | |||
172 | usb_put_hcd(hcd); | ||
173 | |||
174 | return 0; | ||
175 | } | ||
176 | |||
177 | /* Make sure the controller is quiescent and that we're not using it | ||
178 | * any more. This is mainly for the benefit of programs which, like kexec, | ||
179 | * expect the hardware to be idle: not doing DMA or generating IRQs. | ||
180 | * | ||
181 | * This routine may be called in a damaged or failing kernel. Hence we | ||
182 | * do not acquire the spinlock before shutting down the controller. | ||
183 | */ | ||
184 | static void uhci_hcd_grlib_shutdown(struct platform_device *op) | ||
185 | { | ||
186 | struct usb_hcd *hcd = dev_get_drvdata(&op->dev); | ||
187 | |||
188 | uhci_hc_died(hcd_to_uhci(hcd)); | ||
189 | } | ||
190 | |||
191 | static const struct of_device_id uhci_hcd_grlib_of_match[] = { | ||
192 | { .name = "GAISLER_UHCI", }, | ||
193 | { .name = "01_027", }, | ||
194 | {}, | ||
195 | }; | ||
196 | MODULE_DEVICE_TABLE(of, uhci_hcd_grlib_of_match); | ||
197 | |||
198 | |||
199 | static struct platform_driver uhci_grlib_driver = { | ||
200 | .probe = uhci_hcd_grlib_probe, | ||
201 | .remove = uhci_hcd_grlib_remove, | ||
202 | .shutdown = uhci_hcd_grlib_shutdown, | ||
203 | .driver = { | ||
204 | .name = "grlib-uhci", | ||
205 | .owner = THIS_MODULE, | ||
206 | .of_match_table = uhci_hcd_grlib_of_match, | ||
207 | }, | ||
208 | }; | ||
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c index f52d04db28f4..fba99b120588 100644 --- a/drivers/usb/host/uhci-hcd.c +++ b/drivers/usb/host/uhci-hcd.c | |||
@@ -48,14 +48,14 @@ | |||
48 | #include <asm/system.h> | 48 | #include <asm/system.h> |
49 | 49 | ||
50 | #include "uhci-hcd.h" | 50 | #include "uhci-hcd.h" |
51 | #include "pci-quirks.h" | ||
52 | 51 | ||
53 | /* | 52 | /* |
54 | * Version Information | 53 | * Version Information |
55 | */ | 54 | */ |
56 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ | 55 | #define DRIVER_AUTHOR \ |
57 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | 56 | "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \ |
58 | Alan Stern" | 57 | "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \ |
58 | "Roman Weissgaerber, Alan Stern" | ||
59 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | 59 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" |
60 | 60 | ||
61 | /* for flakey hardware, ignore overcurrent indicators */ | 61 | /* for flakey hardware, ignore overcurrent indicators */ |
@@ -93,7 +93,7 @@ static void uhci_get_current_frame_number(struct uhci_hcd *uhci); | |||
93 | /* | 93 | /* |
94 | * Calculate the link pointer DMA value for the first Skeleton QH in a frame. | 94 | * Calculate the link pointer DMA value for the first Skeleton QH in a frame. |
95 | */ | 95 | */ |
96 | static __le32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) | 96 | static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) |
97 | { | 97 | { |
98 | int skelnum; | 98 | int skelnum; |
99 | 99 | ||
@@ -115,7 +115,7 @@ static __le32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) | |||
115 | skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); | 115 | skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); |
116 | if (skelnum <= 1) | 116 | if (skelnum <= 1) |
117 | skelnum = 9; | 117 | skelnum = 9; |
118 | return LINK_TO_QH(uhci->skelqh[skelnum]); | 118 | return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); |
119 | } | 119 | } |
120 | 120 | ||
121 | #include "uhci-debug.c" | 121 | #include "uhci-debug.c" |
@@ -134,15 +134,12 @@ static void finish_reset(struct uhci_hcd *uhci) | |||
134 | * We have to clear them by hand. | 134 | * We have to clear them by hand. |
135 | */ | 135 | */ |
136 | for (port = 0; port < uhci->rh_numports; ++port) | 136 | for (port = 0; port < uhci->rh_numports; ++port) |
137 | outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); | 137 | uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); |
138 | 138 | ||
139 | uhci->port_c_suspend = uhci->resuming_ports = 0; | 139 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
140 | uhci->rh_state = UHCI_RH_RESET; | 140 | uhci->rh_state = UHCI_RH_RESET; |
141 | uhci->is_stopped = UHCI_IS_STOPPED; | 141 | uhci->is_stopped = UHCI_IS_STOPPED; |
142 | uhci_to_hcd(uhci)->state = HC_STATE_HALT; | ||
143 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | 142 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
144 | |||
145 | uhci->dead = 0; /* Full reset resurrects the controller */ | ||
146 | } | 143 | } |
147 | 144 | ||
148 | /* | 145 | /* |
@@ -152,7 +149,7 @@ static void finish_reset(struct uhci_hcd *uhci) | |||
152 | static void uhci_hc_died(struct uhci_hcd *uhci) | 149 | static void uhci_hc_died(struct uhci_hcd *uhci) |
153 | { | 150 | { |
154 | uhci_get_current_frame_number(uhci); | 151 | uhci_get_current_frame_number(uhci); |
155 | uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr); | 152 | uhci->reset_hc(uhci); |
156 | finish_reset(uhci); | 153 | finish_reset(uhci); |
157 | uhci->dead = 1; | 154 | uhci->dead = 1; |
158 | 155 | ||
@@ -167,97 +164,118 @@ static void uhci_hc_died(struct uhci_hcd *uhci) | |||
167 | */ | 164 | */ |
168 | static void check_and_reset_hc(struct uhci_hcd *uhci) | 165 | static void check_and_reset_hc(struct uhci_hcd *uhci) |
169 | { | 166 | { |
170 | if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr)) | 167 | if (uhci->check_and_reset_hc(uhci)) |
171 | finish_reset(uhci); | 168 | finish_reset(uhci); |
172 | } | 169 | } |
173 | 170 | ||
171 | #if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) | ||
172 | /* | ||
173 | * The two functions below are generic reset functions that are used on systems | ||
174 | * that do not have keyboard and mouse legacy support. We assume that we are | ||
175 | * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined. | ||
176 | */ | ||
177 | |||
178 | /* | ||
179 | * Make sure the controller is completely inactive, unable to | ||
180 | * generate interrupts or do DMA. | ||
181 | */ | ||
182 | static void uhci_generic_reset_hc(struct uhci_hcd *uhci) | ||
183 | { | ||
184 | /* Reset the HC - this will force us to get a | ||
185 | * new notification of any already connected | ||
186 | * ports due to the virtual disconnect that it | ||
187 | * implies. | ||
188 | */ | ||
189 | uhci_writew(uhci, USBCMD_HCRESET, USBCMD); | ||
190 | mb(); | ||
191 | udelay(5); | ||
192 | if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET) | ||
193 | dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); | ||
194 | |||
195 | /* Just to be safe, disable interrupt requests and | ||
196 | * make sure the controller is stopped. | ||
197 | */ | ||
198 | uhci_writew(uhci, 0, USBINTR); | ||
199 | uhci_writew(uhci, 0, USBCMD); | ||
200 | } | ||
201 | |||
202 | /* | ||
203 | * Initialize a controller that was newly discovered or has just been | ||
204 | * resumed. In either case we can't be sure of its previous state. | ||
205 | * | ||
206 | * Returns: 1 if the controller was reset, 0 otherwise. | ||
207 | */ | ||
208 | static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci) | ||
209 | { | ||
210 | unsigned int cmd, intr; | ||
211 | |||
212 | /* | ||
213 | * When restarting a suspended controller, we expect all the | ||
214 | * settings to be the same as we left them: | ||
215 | * | ||
216 | * Controller is stopped and configured with EGSM set; | ||
217 | * No interrupts enabled except possibly Resume Detect. | ||
218 | * | ||
219 | * If any of these conditions are violated we do a complete reset. | ||
220 | */ | ||
221 | |||
222 | cmd = uhci_readw(uhci, USBCMD); | ||
223 | if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { | ||
224 | dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", | ||
225 | __func__, cmd); | ||
226 | goto reset_needed; | ||
227 | } | ||
228 | |||
229 | intr = uhci_readw(uhci, USBINTR); | ||
230 | if (intr & (~USBINTR_RESUME)) { | ||
231 | dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", | ||
232 | __func__, intr); | ||
233 | goto reset_needed; | ||
234 | } | ||
235 | return 0; | ||
236 | |||
237 | reset_needed: | ||
238 | dev_dbg(uhci_dev(uhci), "Performing full reset\n"); | ||
239 | uhci_generic_reset_hc(uhci); | ||
240 | return 1; | ||
241 | } | ||
242 | #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ | ||
243 | |||
174 | /* | 244 | /* |
175 | * Store the basic register settings needed by the controller. | 245 | * Store the basic register settings needed by the controller. |
176 | */ | 246 | */ |
177 | static void configure_hc(struct uhci_hcd *uhci) | 247 | static void configure_hc(struct uhci_hcd *uhci) |
178 | { | 248 | { |
179 | struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci)); | ||
180 | |||
181 | /* Set the frame length to the default: 1 ms exactly */ | 249 | /* Set the frame length to the default: 1 ms exactly */ |
182 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | 250 | uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); |
183 | 251 | ||
184 | /* Store the frame list base address */ | 252 | /* Store the frame list base address */ |
185 | outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD); | 253 | uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); |
186 | 254 | ||
187 | /* Set the current frame number */ | 255 | /* Set the current frame number */ |
188 | outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER, | 256 | uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
189 | uhci->io_addr + USBFRNUM); | 257 | USBFRNUM); |
190 | |||
191 | /* Mark controller as not halted before we enable interrupts */ | ||
192 | uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED; | ||
193 | mb(); | ||
194 | |||
195 | /* Enable PIRQ */ | ||
196 | pci_write_config_word(pdev, USBLEGSUP, USBLEGSUP_DEFAULT); | ||
197 | 258 | ||
198 | /* Disable platform-specific non-PME# wakeup */ | 259 | /* perform any arch/bus specific configuration */ |
199 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | 260 | if (uhci->configure_hc) |
200 | pci_write_config_byte(pdev, USBRES_INTEL, 0); | 261 | uhci->configure_hc(uhci); |
201 | } | 262 | } |
202 | 263 | ||
203 | |||
204 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) | 264 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
205 | { | 265 | { |
206 | int port; | ||
207 | |||
208 | /* If we have to ignore overcurrent events then almost by definition | 266 | /* If we have to ignore overcurrent events then almost by definition |
209 | * we can't depend on resume-detect interrupts. */ | 267 | * we can't depend on resume-detect interrupts. */ |
210 | if (ignore_oc) | 268 | if (ignore_oc) |
211 | return 1; | 269 | return 1; |
212 | 270 | ||
213 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { | 271 | return uhci->resume_detect_interrupts_are_broken ? |
214 | default: | 272 | uhci->resume_detect_interrupts_are_broken(uhci) : 0; |
215 | break; | ||
216 | |||
217 | case PCI_VENDOR_ID_GENESYS: | ||
218 | /* Genesys Logic's GL880S controllers don't generate | ||
219 | * resume-detect interrupts. | ||
220 | */ | ||
221 | return 1; | ||
222 | |||
223 | case PCI_VENDOR_ID_INTEL: | ||
224 | /* Some of Intel's USB controllers have a bug that causes | ||
225 | * resume-detect interrupts if any port has an over-current | ||
226 | * condition. To make matters worse, some motherboards | ||
227 | * hardwire unused USB ports' over-current inputs active! | ||
228 | * To prevent problems, we will not enable resume-detect | ||
229 | * interrupts if any ports are OC. | ||
230 | */ | ||
231 | for (port = 0; port < uhci->rh_numports; ++port) { | ||
232 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | ||
233 | USBPORTSC_OC) | ||
234 | return 1; | ||
235 | } | ||
236 | break; | ||
237 | } | ||
238 | return 0; | ||
239 | } | 273 | } |
240 | 274 | ||
241 | static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) | 275 | static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) |
242 | { | 276 | { |
243 | int port; | 277 | return uhci->global_suspend_mode_is_broken ? |
244 | const char *sys_info; | 278 | uhci->global_suspend_mode_is_broken(uhci) : 0; |
245 | static char bad_Asus_board[] = "A7V8X"; | ||
246 | |||
247 | /* One of Asus's motherboards has a bug which causes it to | ||
248 | * wake up immediately from suspend-to-RAM if any of the ports | ||
249 | * are connected. In such cases we will not set EGSM. | ||
250 | */ | ||
251 | sys_info = dmi_get_system_info(DMI_BOARD_NAME); | ||
252 | if (sys_info && !strcmp(sys_info, bad_Asus_board)) { | ||
253 | for (port = 0; port < uhci->rh_numports; ++port) { | ||
254 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | ||
255 | USBPORTSC_CCS) | ||
256 | return 1; | ||
257 | } | ||
258 | } | ||
259 | |||
260 | return 0; | ||
261 | } | 279 | } |
262 | 280 | ||
263 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) | 281 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
@@ -320,8 +338,8 @@ __acquires(uhci->lock) | |||
320 | !int_enable) | 338 | !int_enable) |
321 | uhci->RD_enable = int_enable = 0; | 339 | uhci->RD_enable = int_enable = 0; |
322 | 340 | ||
323 | outw(int_enable, uhci->io_addr + USBINTR); | 341 | uhci_writew(uhci, int_enable, USBINTR); |
324 | outw(egsm_enable | USBCMD_CF, uhci->io_addr + USBCMD); | 342 | uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); |
325 | mb(); | 343 | mb(); |
326 | udelay(5); | 344 | udelay(5); |
327 | 345 | ||
@@ -330,7 +348,7 @@ __acquires(uhci->lock) | |||
330 | * controller should stop after a few microseconds. Otherwise | 348 | * controller should stop after a few microseconds. Otherwise |
331 | * we will give the controller one frame to stop. | 349 | * we will give the controller one frame to stop. |
332 | */ | 350 | */ |
333 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | 351 | if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { |
334 | uhci->rh_state = UHCI_RH_SUSPENDING; | 352 | uhci->rh_state = UHCI_RH_SUSPENDING; |
335 | spin_unlock_irq(&uhci->lock); | 353 | spin_unlock_irq(&uhci->lock); |
336 | msleep(1); | 354 | msleep(1); |
@@ -338,7 +356,7 @@ __acquires(uhci->lock) | |||
338 | if (uhci->dead) | 356 | if (uhci->dead) |
339 | return; | 357 | return; |
340 | } | 358 | } |
341 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | 359 | if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) |
342 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); | 360 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); |
343 | 361 | ||
344 | uhci_get_current_frame_number(uhci); | 362 | uhci_get_current_frame_number(uhci); |
@@ -360,15 +378,14 @@ __acquires(uhci->lock) | |||
360 | 378 | ||
361 | static void start_rh(struct uhci_hcd *uhci) | 379 | static void start_rh(struct uhci_hcd *uhci) |
362 | { | 380 | { |
363 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; | ||
364 | uhci->is_stopped = 0; | 381 | uhci->is_stopped = 0; |
365 | 382 | ||
366 | /* Mark it configured and running with a 64-byte max packet. | 383 | /* Mark it configured and running with a 64-byte max packet. |
367 | * All interrupts are enabled, even though RESUME won't do anything. | 384 | * All interrupts are enabled, even though RESUME won't do anything. |
368 | */ | 385 | */ |
369 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | 386 | uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); |
370 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | 387 | uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | |
371 | uhci->io_addr + USBINTR); | 388 | USBINTR_IOC | USBINTR_SP, USBINTR); |
372 | mb(); | 389 | mb(); |
373 | uhci->rh_state = UHCI_RH_RUNNING; | 390 | uhci->rh_state = UHCI_RH_RUNNING; |
374 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | 391 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
@@ -391,9 +408,9 @@ __acquires(uhci->lock) | |||
391 | unsigned egsm; | 408 | unsigned egsm; |
392 | 409 | ||
393 | /* Keep EGSM on if it was set before */ | 410 | /* Keep EGSM on if it was set before */ |
394 | egsm = inw(uhci->io_addr + USBCMD) & USBCMD_EGSM; | 411 | egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; |
395 | uhci->rh_state = UHCI_RH_RESUMING; | 412 | uhci->rh_state = UHCI_RH_RESUMING; |
396 | outw(USBCMD_FGR | USBCMD_CF | egsm, uhci->io_addr + USBCMD); | 413 | uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); |
397 | spin_unlock_irq(&uhci->lock); | 414 | spin_unlock_irq(&uhci->lock); |
398 | msleep(20); | 415 | msleep(20); |
399 | spin_lock_irq(&uhci->lock); | 416 | spin_lock_irq(&uhci->lock); |
@@ -401,10 +418,10 @@ __acquires(uhci->lock) | |||
401 | return; | 418 | return; |
402 | 419 | ||
403 | /* End Global Resume and wait for EOP to be sent */ | 420 | /* End Global Resume and wait for EOP to be sent */ |
404 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | 421 | uhci_writew(uhci, USBCMD_CF, USBCMD); |
405 | mb(); | 422 | mb(); |
406 | udelay(4); | 423 | udelay(4); |
407 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | 424 | if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) |
408 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | 425 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); |
409 | } | 426 | } |
410 | 427 | ||
@@ -424,10 +441,10 @@ static irqreturn_t uhci_irq(struct usb_hcd *hcd) | |||
424 | * interrupt cause. Contrary to the UHCI specification, the | 441 | * interrupt cause. Contrary to the UHCI specification, the |
425 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | 442 | * "HC Halted" status bit is persistent: it is RO, not R/WC. |
426 | */ | 443 | */ |
427 | status = inw(uhci->io_addr + USBSTS); | 444 | status = uhci_readw(uhci, USBSTS); |
428 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ | 445 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
429 | return IRQ_NONE; | 446 | return IRQ_NONE; |
430 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ | 447 | uhci_writew(uhci, status, USBSTS); /* Clear it */ |
431 | 448 | ||
432 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | 449 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { |
433 | if (status & USBSTS_HSE) | 450 | if (status & USBSTS_HSE) |
@@ -449,6 +466,7 @@ static irqreturn_t uhci_irq(struct usb_hcd *hcd) | |||
449 | lprintk(errbuf); | 466 | lprintk(errbuf); |
450 | } | 467 | } |
451 | uhci_hc_died(uhci); | 468 | uhci_hc_died(uhci); |
469 | usb_hc_died(hcd); | ||
452 | 470 | ||
453 | /* Force a callback in case there are | 471 | /* Force a callback in case there are |
454 | * pending unlinks */ | 472 | * pending unlinks */ |
@@ -471,7 +489,7 @@ static irqreturn_t uhci_irq(struct usb_hcd *hcd) | |||
471 | 489 | ||
472 | /* | 490 | /* |
473 | * Store the current frame number in uhci->frame_number if the controller | 491 | * Store the current frame number in uhci->frame_number if the controller |
474 | * is runnning. Expand from 11 bits (of which we use only 10) to a | 492 | * is running. Expand from 11 bits (of which we use only 10) to a |
475 | * full-sized integer. | 493 | * full-sized integer. |
476 | * | 494 | * |
477 | * Like many other parts of the driver, this code relies on being polled | 495 | * Like many other parts of the driver, this code relies on being polled |
@@ -482,7 +500,7 @@ static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |||
482 | if (!uhci->is_stopped) { | 500 | if (!uhci->is_stopped) { |
483 | unsigned delta; | 501 | unsigned delta; |
484 | 502 | ||
485 | delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) & | 503 | delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & |
486 | (UHCI_NUMFRAMES - 1); | 504 | (UHCI_NUMFRAMES - 1); |
487 | uhci->frame_number += delta; | 505 | uhci->frame_number += delta; |
488 | } | 506 | } |
@@ -519,61 +537,6 @@ static void release_uhci(struct uhci_hcd *uhci) | |||
519 | uhci->frame, uhci->frame_dma_handle); | 537 | uhci->frame, uhci->frame_dma_handle); |
520 | } | 538 | } |
521 | 539 | ||
522 | static int uhci_init(struct usb_hcd *hcd) | ||
523 | { | ||
524 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
525 | unsigned io_size = (unsigned) hcd->rsrc_len; | ||
526 | int port; | ||
527 | |||
528 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | ||
529 | |||
530 | /* The UHCI spec says devices must have 2 ports, and goes on to say | ||
531 | * they may have more but gives no way to determine how many there | ||
532 | * are. However according to the UHCI spec, Bit 7 of the port | ||
533 | * status and control register is always set to 1. So we try to | ||
534 | * use this to our advantage. Another common failure mode when | ||
535 | * a nonexistent register is addressed is to return all ones, so | ||
536 | * we test for that also. | ||
537 | */ | ||
538 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | ||
539 | unsigned int portstatus; | ||
540 | |||
541 | portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); | ||
542 | if (!(portstatus & 0x0080) || portstatus == 0xffff) | ||
543 | break; | ||
544 | } | ||
545 | if (debug) | ||
546 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | ||
547 | |||
548 | /* Anything greater than 7 is weird so we'll ignore it. */ | ||
549 | if (port > UHCI_RH_MAXCHILD) { | ||
550 | dev_info(uhci_dev(uhci), "port count misdetected? " | ||
551 | "forcing to 2 ports\n"); | ||
552 | port = 2; | ||
553 | } | ||
554 | uhci->rh_numports = port; | ||
555 | |||
556 | /* Kick BIOS off this hardware and reset if the controller | ||
557 | * isn't already safely quiescent. | ||
558 | */ | ||
559 | check_and_reset_hc(uhci); | ||
560 | return 0; | ||
561 | } | ||
562 | |||
563 | /* Make sure the controller is quiescent and that we're not using it | ||
564 | * any more. This is mainly for the benefit of programs which, like kexec, | ||
565 | * expect the hardware to be idle: not doing DMA or generating IRQs. | ||
566 | * | ||
567 | * This routine may be called in a damaged or failing kernel. Hence we | ||
568 | * do not acquire the spinlock before shutting down the controller. | ||
569 | */ | ||
570 | static void uhci_shutdown(struct pci_dev *pdev) | ||
571 | { | ||
572 | struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev); | ||
573 | |||
574 | uhci_hc_died(hcd_to_uhci(hcd)); | ||
575 | } | ||
576 | |||
577 | /* | 540 | /* |
578 | * Allocate a frame list, and then setup the skeleton | 541 | * Allocate a frame list, and then setup the skeleton |
579 | * | 542 | * |
@@ -668,16 +631,16 @@ static int uhci_start(struct usb_hcd *hcd) | |||
668 | * 8 Interrupt queues; link all higher int queues to int1 = async | 631 | * 8 Interrupt queues; link all higher int queues to int1 = async |
669 | */ | 632 | */ |
670 | for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) | 633 | for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) |
671 | uhci->skelqh[i]->link = LINK_TO_QH(uhci->skel_async_qh); | 634 | uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh); |
672 | uhci->skel_async_qh->link = UHCI_PTR_TERM; | 635 | uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci); |
673 | uhci->skel_term_qh->link = LINK_TO_QH(uhci->skel_term_qh); | 636 | uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); |
674 | 637 | ||
675 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | 638 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ |
676 | uhci_fill_td(uhci->term_td, 0, uhci_explen(0) | | 639 | uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) | |
677 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); | 640 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); |
678 | uhci->term_td->link = UHCI_PTR_TERM; | 641 | uhci->term_td->link = UHCI_PTR_TERM(uhci); |
679 | uhci->skel_async_qh->element = uhci->skel_term_qh->element = | 642 | uhci->skel_async_qh->element = uhci->skel_term_qh->element = |
680 | LINK_TO_TD(uhci->term_td); | 643 | LINK_TO_TD(uhci, uhci->term_td); |
681 | 644 | ||
682 | /* | 645 | /* |
683 | * Fill the frame list: make all entries point to the proper | 646 | * Fill the frame list: make all entries point to the proper |
@@ -790,86 +753,6 @@ static int uhci_rh_resume(struct usb_hcd *hcd) | |||
790 | return rc; | 753 | return rc; |
791 | } | 754 | } |
792 | 755 | ||
793 | static int uhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | ||
794 | { | ||
795 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
796 | struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci)); | ||
797 | int rc = 0; | ||
798 | |||
799 | dev_dbg(uhci_dev(uhci), "%s\n", __func__); | ||
800 | |||
801 | spin_lock_irq(&uhci->lock); | ||
802 | if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) | ||
803 | goto done_okay; /* Already suspended or dead */ | ||
804 | |||
805 | if (uhci->rh_state > UHCI_RH_SUSPENDED) { | ||
806 | dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); | ||
807 | rc = -EBUSY; | ||
808 | goto done; | ||
809 | }; | ||
810 | |||
811 | /* All PCI host controllers are required to disable IRQ generation | ||
812 | * at the source, so we must turn off PIRQ. | ||
813 | */ | ||
814 | pci_write_config_word(pdev, USBLEGSUP, 0); | ||
815 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | ||
816 | |||
817 | /* Enable platform-specific non-PME# wakeup */ | ||
818 | if (do_wakeup) { | ||
819 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | ||
820 | pci_write_config_byte(pdev, USBRES_INTEL, | ||
821 | USBPORT1EN | USBPORT2EN); | ||
822 | } | ||
823 | |||
824 | done_okay: | ||
825 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
826 | done: | ||
827 | spin_unlock_irq(&uhci->lock); | ||
828 | return rc; | ||
829 | } | ||
830 | |||
831 | static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | ||
832 | { | ||
833 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
834 | |||
835 | dev_dbg(uhci_dev(uhci), "%s\n", __func__); | ||
836 | |||
837 | /* Since we aren't in D3 any more, it's safe to set this flag | ||
838 | * even if the controller was dead. | ||
839 | */ | ||
840 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
841 | |||
842 | spin_lock_irq(&uhci->lock); | ||
843 | |||
844 | /* Make sure resume from hibernation re-enumerates everything */ | ||
845 | if (hibernated) | ||
846 | uhci_hc_died(uhci); | ||
847 | |||
848 | /* The firmware or a boot kernel may have changed the controller | ||
849 | * settings during a system wakeup. Check it and reconfigure | ||
850 | * to avoid problems. | ||
851 | */ | ||
852 | check_and_reset_hc(uhci); | ||
853 | |||
854 | /* If the controller was dead before, it's back alive now */ | ||
855 | configure_hc(uhci); | ||
856 | |||
857 | /* Tell the core if the controller had to be reset */ | ||
858 | if (uhci->rh_state == UHCI_RH_RESET) | ||
859 | usb_root_hub_lost_power(hcd->self.root_hub); | ||
860 | |||
861 | spin_unlock_irq(&uhci->lock); | ||
862 | |||
863 | /* If interrupts don't work and remote wakeup is enabled then | ||
864 | * the suspended root hub needs to be polled. | ||
865 | */ | ||
866 | if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup) | ||
867 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | ||
868 | |||
869 | /* Does the root hub have a port wakeup pending? */ | ||
870 | usb_hcd_poll_rh_status(hcd); | ||
871 | return 0; | ||
872 | } | ||
873 | #endif | 756 | #endif |
874 | 757 | ||
875 | /* Wait until a particular device/endpoint's QH is idle, and free it */ | 758 | /* Wait until a particular device/endpoint's QH is idle, and free it */ |
@@ -907,67 +790,62 @@ static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |||
907 | /* Minimize latency by avoiding the spinlock */ | 790 | /* Minimize latency by avoiding the spinlock */ |
908 | frame_number = uhci->frame_number; | 791 | frame_number = uhci->frame_number; |
909 | barrier(); | 792 | barrier(); |
910 | delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) & | 793 | delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & |
911 | (UHCI_NUMFRAMES - 1); | 794 | (UHCI_NUMFRAMES - 1); |
912 | return frame_number + delta; | 795 | return frame_number + delta; |
913 | } | 796 | } |
914 | 797 | ||
915 | static const char hcd_name[] = "uhci_hcd"; | 798 | /* Determines number of ports on controller */ |
916 | 799 | static int uhci_count_ports(struct usb_hcd *hcd) | |
917 | static const struct hc_driver uhci_driver = { | 800 | { |
918 | .description = hcd_name, | 801 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); |
919 | .product_desc = "UHCI Host Controller", | 802 | unsigned io_size = (unsigned) hcd->rsrc_len; |
920 | .hcd_priv_size = sizeof(struct uhci_hcd), | 803 | int port; |
921 | |||
922 | /* Generic hardware linkage */ | ||
923 | .irq = uhci_irq, | ||
924 | .flags = HCD_USB11, | ||
925 | |||
926 | /* Basic lifecycle operations */ | ||
927 | .reset = uhci_init, | ||
928 | .start = uhci_start, | ||
929 | #ifdef CONFIG_PM | ||
930 | .pci_suspend = uhci_pci_suspend, | ||
931 | .pci_resume = uhci_pci_resume, | ||
932 | .bus_suspend = uhci_rh_suspend, | ||
933 | .bus_resume = uhci_rh_resume, | ||
934 | #endif | ||
935 | .stop = uhci_stop, | ||
936 | 804 | ||
937 | .urb_enqueue = uhci_urb_enqueue, | 805 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
938 | .urb_dequeue = uhci_urb_dequeue, | 806 | * they may have more but gives no way to determine how many there |
807 | * are. However according to the UHCI spec, Bit 7 of the port | ||
808 | * status and control register is always set to 1. So we try to | ||
809 | * use this to our advantage. Another common failure mode when | ||
810 | * a nonexistent register is addressed is to return all ones, so | ||
811 | * we test for that also. | ||
812 | */ | ||
813 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | ||
814 | unsigned int portstatus; | ||
939 | 815 | ||
940 | .endpoint_disable = uhci_hcd_endpoint_disable, | 816 | portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); |
941 | .get_frame_number = uhci_hcd_get_frame_number, | 817 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
818 | break; | ||
819 | } | ||
820 | if (debug) | ||
821 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | ||
942 | 822 | ||
943 | .hub_status_data = uhci_hub_status_data, | 823 | /* Anything greater than 7 is weird so we'll ignore it. */ |
944 | .hub_control = uhci_hub_control, | 824 | if (port > UHCI_RH_MAXCHILD) { |
945 | }; | 825 | dev_info(uhci_dev(uhci), "port count misdetected? " |
826 | "forcing to 2 ports\n"); | ||
827 | port = 2; | ||
828 | } | ||
946 | 829 | ||
947 | static const struct pci_device_id uhci_pci_ids[] = { { | 830 | return port; |
948 | /* handle any USB UHCI controller */ | 831 | } |
949 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0), | ||
950 | .driver_data = (unsigned long) &uhci_driver, | ||
951 | }, { /* end: all zeroes */ } | ||
952 | }; | ||
953 | 832 | ||
954 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | 833 | static const char hcd_name[] = "uhci_hcd"; |
955 | 834 | ||
956 | static struct pci_driver uhci_pci_driver = { | 835 | #ifdef CONFIG_PCI |
957 | .name = (char *)hcd_name, | 836 | #include "uhci-pci.c" |
958 | .id_table = uhci_pci_ids, | 837 | #define PCI_DRIVER uhci_pci_driver |
838 | #endif | ||
959 | 839 | ||
960 | .probe = usb_hcd_pci_probe, | 840 | #ifdef CONFIG_SPARC_LEON |
961 | .remove = usb_hcd_pci_remove, | 841 | #include "uhci-grlib.c" |
962 | .shutdown = uhci_shutdown, | 842 | #define PLATFORM_DRIVER uhci_grlib_driver |
843 | #endif | ||
963 | 844 | ||
964 | #ifdef CONFIG_PM_SLEEP | 845 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) |
965 | .driver = { | 846 | #error "missing bus glue for uhci-hcd" |
966 | .pm = &usb_hcd_pci_pm_ops | ||
967 | }, | ||
968 | #endif | 847 | #endif |
969 | }; | 848 | |
970 | |||
971 | static int __init uhci_hcd_init(void) | 849 | static int __init uhci_hcd_init(void) |
972 | { | 850 | { |
973 | int retval = -ENOMEM; | 851 | int retval = -ENOMEM; |
@@ -993,13 +871,27 @@ static int __init uhci_hcd_init(void) | |||
993 | if (!uhci_up_cachep) | 871 | if (!uhci_up_cachep) |
994 | goto up_failed; | 872 | goto up_failed; |
995 | 873 | ||
996 | retval = pci_register_driver(&uhci_pci_driver); | 874 | #ifdef PLATFORM_DRIVER |
997 | if (retval) | 875 | retval = platform_driver_register(&PLATFORM_DRIVER); |
998 | goto init_failed; | 876 | if (retval < 0) |
877 | goto clean0; | ||
878 | #endif | ||
879 | |||
880 | #ifdef PCI_DRIVER | ||
881 | retval = pci_register_driver(&PCI_DRIVER); | ||
882 | if (retval < 0) | ||
883 | goto clean1; | ||
884 | #endif | ||
999 | 885 | ||
1000 | return 0; | 886 | return 0; |
1001 | 887 | ||
1002 | init_failed: | 888 | #ifdef PCI_DRIVER |
889 | clean1: | ||
890 | #endif | ||
891 | #ifdef PLATFORM_DRIVER | ||
892 | platform_driver_unregister(&PLATFORM_DRIVER); | ||
893 | clean0: | ||
894 | #endif | ||
1003 | kmem_cache_destroy(uhci_up_cachep); | 895 | kmem_cache_destroy(uhci_up_cachep); |
1004 | 896 | ||
1005 | up_failed: | 897 | up_failed: |
@@ -1016,7 +908,12 @@ errbuf_failed: | |||
1016 | 908 | ||
1017 | static void __exit uhci_hcd_cleanup(void) | 909 | static void __exit uhci_hcd_cleanup(void) |
1018 | { | 910 | { |
1019 | pci_unregister_driver(&uhci_pci_driver); | 911 | #ifdef PLATFORM_DRIVER |
912 | platform_driver_unregister(&PLATFORM_DRIVER); | ||
913 | #endif | ||
914 | #ifdef PCI_DRIVER | ||
915 | pci_unregister_driver(&PCI_DRIVER); | ||
916 | #endif | ||
1020 | kmem_cache_destroy(uhci_up_cachep); | 917 | kmem_cache_destroy(uhci_up_cachep); |
1021 | debugfs_remove(uhci_debugfs_root); | 918 | debugfs_remove(uhci_debugfs_root); |
1022 | kfree(errbuf); | 919 | kfree(errbuf); |
diff --git a/drivers/usb/host/uhci-hcd.h b/drivers/usb/host/uhci-hcd.h index 49bf2790f9c2..7af2b7052047 100644 --- a/drivers/usb/host/uhci-hcd.h +++ b/drivers/usb/host/uhci-hcd.h | |||
@@ -78,11 +78,11 @@ | |||
78 | #define USBPORT1EN 0x01 | 78 | #define USBPORT1EN 0x01 |
79 | #define USBPORT2EN 0x02 | 79 | #define USBPORT2EN 0x02 |
80 | 80 | ||
81 | #define UHCI_PTR_BITS cpu_to_le32(0x000F) | 81 | #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F) |
82 | #define UHCI_PTR_TERM cpu_to_le32(0x0001) | 82 | #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001) |
83 | #define UHCI_PTR_QH cpu_to_le32(0x0002) | 83 | #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002) |
84 | #define UHCI_PTR_DEPTH cpu_to_le32(0x0004) | 84 | #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004) |
85 | #define UHCI_PTR_BREADTH cpu_to_le32(0x0000) | 85 | #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000) |
86 | 86 | ||
87 | #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ | 87 | #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ |
88 | #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ | 88 | #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ |
@@ -99,6 +99,22 @@ | |||
99 | 99 | ||
100 | 100 | ||
101 | /* | 101 | /* |
102 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | ||
103 | * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on | ||
104 | * the host controller implementation. | ||
105 | * | ||
106 | * To facilitate the strongest possible byte-order checking from "sparse" | ||
107 | * and so on, we use __leXX unless that's not practical. | ||
108 | */ | ||
109 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC | ||
110 | typedef __u32 __bitwise __hc32; | ||
111 | typedef __u16 __bitwise __hc16; | ||
112 | #else | ||
113 | #define __hc32 __le32 | ||
114 | #define __hc16 __le16 | ||
115 | #endif | ||
116 | |||
117 | /* | ||
102 | * Queue Headers | 118 | * Queue Headers |
103 | */ | 119 | */ |
104 | 120 | ||
@@ -130,8 +146,8 @@ | |||
130 | 146 | ||
131 | struct uhci_qh { | 147 | struct uhci_qh { |
132 | /* Hardware fields */ | 148 | /* Hardware fields */ |
133 | __le32 link; /* Next QH in the schedule */ | 149 | __hc32 link; /* Next QH in the schedule */ |
134 | __le32 element; /* Queue element (TD) pointer */ | 150 | __hc32 element; /* Queue element (TD) pointer */ |
135 | 151 | ||
136 | /* Software fields */ | 152 | /* Software fields */ |
137 | dma_addr_t dma_handle; | 153 | dma_addr_t dma_handle; |
@@ -168,14 +184,10 @@ struct uhci_qh { | |||
168 | * We need a special accessor for the element pointer because it is | 184 | * We need a special accessor for the element pointer because it is |
169 | * subject to asynchronous updates by the controller. | 185 | * subject to asynchronous updates by the controller. |
170 | */ | 186 | */ |
171 | static inline __le32 qh_element(struct uhci_qh *qh) { | 187 | #define qh_element(qh) ACCESS_ONCE((qh)->element) |
172 | __le32 element = qh->element; | ||
173 | 188 | ||
174 | barrier(); | 189 | #define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \ |
175 | return element; | 190 | cpu_to_hc32((uhci), (qh)->dma_handle)) |
176 | } | ||
177 | |||
178 | #define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle)) | ||
179 | 191 | ||
180 | 192 | ||
181 | /* | 193 | /* |
@@ -212,7 +224,7 @@ static inline __le32 qh_element(struct uhci_qh *qh) { | |||
212 | /* | 224 | /* |
213 | * for TD <info>: (a.k.a. Token) | 225 | * for TD <info>: (a.k.a. Token) |
214 | */ | 226 | */ |
215 | #define td_token(td) le32_to_cpu((td)->token) | 227 | #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token) |
216 | #define TD_TOKEN_DEVADDR_SHIFT 8 | 228 | #define TD_TOKEN_DEVADDR_SHIFT 8 |
217 | #define TD_TOKEN_TOGGLE_SHIFT 19 | 229 | #define TD_TOKEN_TOGGLE_SHIFT 19 |
218 | #define TD_TOKEN_TOGGLE (1 << 19) | 230 | #define TD_TOKEN_TOGGLE (1 << 19) |
@@ -245,10 +257,10 @@ static inline __le32 qh_element(struct uhci_qh *qh) { | |||
245 | */ | 257 | */ |
246 | struct uhci_td { | 258 | struct uhci_td { |
247 | /* Hardware fields */ | 259 | /* Hardware fields */ |
248 | __le32 link; | 260 | __hc32 link; |
249 | __le32 status; | 261 | __hc32 status; |
250 | __le32 token; | 262 | __hc32 token; |
251 | __le32 buffer; | 263 | __hc32 buffer; |
252 | 264 | ||
253 | /* Software fields */ | 265 | /* Software fields */ |
254 | dma_addr_t dma_handle; | 266 | dma_addr_t dma_handle; |
@@ -263,14 +275,10 @@ struct uhci_td { | |||
263 | * We need a special accessor for the control/status word because it is | 275 | * We need a special accessor for the control/status word because it is |
264 | * subject to asynchronous updates by the controller. | 276 | * subject to asynchronous updates by the controller. |
265 | */ | 277 | */ |
266 | static inline u32 td_status(struct uhci_td *td) { | 278 | #define td_status(uhci, td) hc32_to_cpu((uhci), \ |
267 | __le32 status = td->status; | 279 | ACCESS_ONCE((td)->status)) |
268 | 280 | ||
269 | barrier(); | 281 | #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle)) |
270 | return le32_to_cpu(status); | ||
271 | } | ||
272 | |||
273 | #define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle)) | ||
274 | 282 | ||
275 | 283 | ||
276 | /* | 284 | /* |
@@ -380,6 +388,9 @@ struct uhci_hcd { | |||
380 | /* Grabbed from PCI */ | 388 | /* Grabbed from PCI */ |
381 | unsigned long io_addr; | 389 | unsigned long io_addr; |
382 | 390 | ||
391 | /* Used when registers are memory mapped */ | ||
392 | void __iomem *regs; | ||
393 | |||
383 | struct dma_pool *qh_pool; | 394 | struct dma_pool *qh_pool; |
384 | struct dma_pool *td_pool; | 395 | struct dma_pool *td_pool; |
385 | 396 | ||
@@ -390,7 +401,7 @@ struct uhci_hcd { | |||
390 | spinlock_t lock; | 401 | spinlock_t lock; |
391 | 402 | ||
392 | dma_addr_t frame_dma_handle; /* Hardware frame list */ | 403 | dma_addr_t frame_dma_handle; /* Hardware frame list */ |
393 | __le32 *frame; | 404 | __hc32 *frame; |
394 | void **frame_cpu; /* CPU's frame list */ | 405 | void **frame_cpu; /* CPU's frame list */ |
395 | 406 | ||
396 | enum uhci_rh_state rh_state; | 407 | enum uhci_rh_state rh_state; |
@@ -415,6 +426,12 @@ struct uhci_hcd { | |||
415 | 426 | ||
416 | struct timer_list fsbr_timer; /* For turning off FBSR */ | 427 | struct timer_list fsbr_timer; /* For turning off FBSR */ |
417 | 428 | ||
429 | /* Silicon quirks */ | ||
430 | unsigned int oc_low:1; /* OverCurrent bit active low */ | ||
431 | unsigned int wait_for_hp:1; /* Wait for HP port reset */ | ||
432 | unsigned int big_endian_mmio:1; /* Big endian registers */ | ||
433 | unsigned int big_endian_desc:1; /* Big endian descriptors */ | ||
434 | |||
418 | /* Support for port suspend/resume/reset */ | 435 | /* Support for port suspend/resume/reset */ |
419 | unsigned long port_c_suspend; /* Bit-arrays of ports */ | 436 | unsigned long port_c_suspend; /* Bit-arrays of ports */ |
420 | unsigned long resuming_ports; | 437 | unsigned long resuming_ports; |
@@ -429,6 +446,16 @@ struct uhci_hcd { | |||
429 | 446 | ||
430 | int total_load; /* Sum of array values */ | 447 | int total_load; /* Sum of array values */ |
431 | short load[MAX_PHASE]; /* Periodic allocations */ | 448 | short load[MAX_PHASE]; /* Periodic allocations */ |
449 | |||
450 | /* Reset host controller */ | ||
451 | void (*reset_hc) (struct uhci_hcd *uhci); | ||
452 | int (*check_and_reset_hc) (struct uhci_hcd *uhci); | ||
453 | /* configure_hc should perform arch specific settings, if needed */ | ||
454 | void (*configure_hc) (struct uhci_hcd *uhci); | ||
455 | /* Check for broken resume detect interrupts */ | ||
456 | int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci); | ||
457 | /* Check for broken global suspend */ | ||
458 | int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci); | ||
432 | }; | 459 | }; |
433 | 460 | ||
434 | /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ | 461 | /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ |
@@ -467,4 +494,171 @@ struct urb_priv { | |||
467 | #define PCI_VENDOR_ID_GENESYS 0x17a0 | 494 | #define PCI_VENDOR_ID_GENESYS 0x17a0 |
468 | #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 | 495 | #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 |
469 | 496 | ||
497 | /* | ||
498 | * Functions used to access controller registers. The UCHI spec says that host | ||
499 | * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts | ||
500 | * we use memory mapped registers. | ||
501 | */ | ||
502 | |||
503 | #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC | ||
504 | /* Support PCI only */ | ||
505 | static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) | ||
506 | { | ||
507 | return inl(uhci->io_addr + reg); | ||
508 | } | ||
509 | |||
510 | static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) | ||
511 | { | ||
512 | outl(val, uhci->io_addr + reg); | ||
513 | } | ||
514 | |||
515 | static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) | ||
516 | { | ||
517 | return inw(uhci->io_addr + reg); | ||
518 | } | ||
519 | |||
520 | static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) | ||
521 | { | ||
522 | outw(val, uhci->io_addr + reg); | ||
523 | } | ||
524 | |||
525 | static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) | ||
526 | { | ||
527 | return inb(uhci->io_addr + reg); | ||
528 | } | ||
529 | |||
530 | static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) | ||
531 | { | ||
532 | outb(val, uhci->io_addr + reg); | ||
533 | } | ||
534 | |||
535 | #else | ||
536 | /* Support non-PCI host controllers */ | ||
537 | #ifdef CONFIG_PCI | ||
538 | /* Support PCI and non-PCI host controllers */ | ||
539 | #define uhci_has_pci_registers(u) ((u)->io_addr != 0) | ||
540 | #else | ||
541 | /* Support non-PCI host controllers only */ | ||
542 | #define uhci_has_pci_registers(u) 0 | ||
543 | #endif | ||
544 | |||
545 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
546 | /* Support (non-PCI) big endian host controllers */ | ||
547 | #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio) | ||
548 | #else | ||
549 | #define uhci_big_endian_mmio(u) 0 | ||
550 | #endif | ||
551 | |||
552 | static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) | ||
553 | { | ||
554 | if (uhci_has_pci_registers(uhci)) | ||
555 | return inl(uhci->io_addr + reg); | ||
556 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
557 | else if (uhci_big_endian_mmio(uhci)) | ||
558 | return readl_be(uhci->regs + reg); | ||
559 | #endif | ||
560 | else | ||
561 | return readl(uhci->regs + reg); | ||
562 | } | ||
563 | |||
564 | static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) | ||
565 | { | ||
566 | if (uhci_has_pci_registers(uhci)) | ||
567 | outl(val, uhci->io_addr + reg); | ||
568 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
569 | else if (uhci_big_endian_mmio(uhci)) | ||
570 | writel_be(val, uhci->regs + reg); | ||
571 | #endif | ||
572 | else | ||
573 | writel(val, uhci->regs + reg); | ||
574 | } | ||
575 | |||
576 | static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) | ||
577 | { | ||
578 | if (uhci_has_pci_registers(uhci)) | ||
579 | return inw(uhci->io_addr + reg); | ||
580 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
581 | else if (uhci_big_endian_mmio(uhci)) | ||
582 | return readw_be(uhci->regs + reg); | ||
583 | #endif | ||
584 | else | ||
585 | return readw(uhci->regs + reg); | ||
586 | } | ||
587 | |||
588 | static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) | ||
589 | { | ||
590 | if (uhci_has_pci_registers(uhci)) | ||
591 | outw(val, uhci->io_addr + reg); | ||
592 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
593 | else if (uhci_big_endian_mmio(uhci)) | ||
594 | writew_be(val, uhci->regs + reg); | ||
595 | #endif | ||
596 | else | ||
597 | writew(val, uhci->regs + reg); | ||
598 | } | ||
599 | |||
600 | static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) | ||
601 | { | ||
602 | if (uhci_has_pci_registers(uhci)) | ||
603 | return inb(uhci->io_addr + reg); | ||
604 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
605 | else if (uhci_big_endian_mmio(uhci)) | ||
606 | return readb_be(uhci->regs + reg); | ||
607 | #endif | ||
608 | else | ||
609 | return readb(uhci->regs + reg); | ||
610 | } | ||
611 | |||
612 | static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) | ||
613 | { | ||
614 | if (uhci_has_pci_registers(uhci)) | ||
615 | outb(val, uhci->io_addr + reg); | ||
616 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | ||
617 | else if (uhci_big_endian_mmio(uhci)) | ||
618 | writeb_be(val, uhci->regs + reg); | ||
619 | #endif | ||
620 | else | ||
621 | writeb(val, uhci->regs + reg); | ||
622 | } | ||
623 | #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ | ||
624 | |||
625 | /* | ||
626 | * The GRLIB GRUSBHC controller can use big endian format for its descriptors. | ||
627 | * | ||
628 | * UHCI controllers accessed through PCI work normally (little-endian | ||
629 | * everywhere), so we don't bother supporting a BE-only mode. | ||
630 | */ | ||
631 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC | ||
632 | #define uhci_big_endian_desc(u) ((u)->big_endian_desc) | ||
633 | |||
634 | /* cpu to uhci */ | ||
635 | static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) | ||
636 | { | ||
637 | return uhci_big_endian_desc(uhci) | ||
638 | ? (__force __hc32)cpu_to_be32(x) | ||
639 | : (__force __hc32)cpu_to_le32(x); | ||
640 | } | ||
641 | |||
642 | /* uhci to cpu */ | ||
643 | static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) | ||
644 | { | ||
645 | return uhci_big_endian_desc(uhci) | ||
646 | ? be32_to_cpu((__force __be32)x) | ||
647 | : le32_to_cpu((__force __le32)x); | ||
648 | } | ||
649 | |||
650 | #else | ||
651 | /* cpu to uhci */ | ||
652 | static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) | ||
653 | { | ||
654 | return cpu_to_le32(x); | ||
655 | } | ||
656 | |||
657 | /* uhci to cpu */ | ||
658 | static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) | ||
659 | { | ||
660 | return le32_to_cpu(x); | ||
661 | } | ||
662 | #endif | ||
663 | |||
470 | #endif | 664 | #endif |
diff --git a/drivers/usb/host/uhci-hub.c b/drivers/usb/host/uhci-hub.c index 6d59c0f77f25..045cde4cbc3d 100644 --- a/drivers/usb/host/uhci-hub.c +++ b/drivers/usb/host/uhci-hub.c | |||
@@ -44,7 +44,7 @@ static int any_ports_active(struct uhci_hcd *uhci) | |||
44 | int port; | 44 | int port; |
45 | 45 | ||
46 | for (port = 0; port < uhci->rh_numports; ++port) { | 46 | for (port = 0; port < uhci->rh_numports; ++port) { |
47 | if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & | 47 | if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & |
48 | (USBPORTSC_CCS | RWC_BITS)) || | 48 | (USBPORTSC_CCS | RWC_BITS)) || |
49 | test_bit(port, &uhci->port_c_suspend)) | 49 | test_bit(port, &uhci->port_c_suspend)) |
50 | return 1; | 50 | return 1; |
@@ -68,7 +68,7 @@ static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf) | |||
68 | 68 | ||
69 | *buf = 0; | 69 | *buf = 0; |
70 | for (port = 0; port < uhci->rh_numports; ++port) { | 70 | for (port = 0; port < uhci->rh_numports; ++port) { |
71 | if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & mask) || | 71 | if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) || |
72 | test_bit(port, &uhci->port_c_suspend)) | 72 | test_bit(port, &uhci->port_c_suspend)) |
73 | *buf |= (1 << (port + 1)); | 73 | *buf |= (1 << (port + 1)); |
74 | } | 74 | } |
@@ -78,17 +78,17 @@ static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf) | |||
78 | #define OK(x) len = (x); break | 78 | #define OK(x) len = (x); break |
79 | 79 | ||
80 | #define CLR_RH_PORTSTAT(x) \ | 80 | #define CLR_RH_PORTSTAT(x) \ |
81 | status = inw(port_addr); \ | 81 | status = uhci_readw(uhci, port_addr); \ |
82 | status &= ~(RWC_BITS|WZ_BITS); \ | 82 | status &= ~(RWC_BITS|WZ_BITS); \ |
83 | status &= ~(x); \ | 83 | status &= ~(x); \ |
84 | status |= RWC_BITS & (x); \ | 84 | status |= RWC_BITS & (x); \ |
85 | outw(status, port_addr) | 85 | uhci_writew(uhci, status, port_addr) |
86 | 86 | ||
87 | #define SET_RH_PORTSTAT(x) \ | 87 | #define SET_RH_PORTSTAT(x) \ |
88 | status = inw(port_addr); \ | 88 | status = uhci_readw(uhci, port_addr); \ |
89 | status |= (x); \ | 89 | status |= (x); \ |
90 | status &= ~(RWC_BITS|WZ_BITS); \ | 90 | status &= ~(RWC_BITS|WZ_BITS); \ |
91 | outw(status, port_addr) | 91 | uhci_writew(uhci, status, port_addr) |
92 | 92 | ||
93 | /* UHCI controllers don't automatically stop resume signalling after 20 msec, | 93 | /* UHCI controllers don't automatically stop resume signalling after 20 msec, |
94 | * so we have to poll and check timeouts in order to take care of it. | 94 | * so we have to poll and check timeouts in order to take care of it. |
@@ -99,7 +99,7 @@ static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, | |||
99 | int status; | 99 | int status; |
100 | int i; | 100 | int i; |
101 | 101 | ||
102 | if (inw(port_addr) & SUSPEND_BITS) { | 102 | if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) { |
103 | CLR_RH_PORTSTAT(SUSPEND_BITS); | 103 | CLR_RH_PORTSTAT(SUSPEND_BITS); |
104 | if (test_bit(port, &uhci->resuming_ports)) | 104 | if (test_bit(port, &uhci->resuming_ports)) |
105 | set_bit(port, &uhci->port_c_suspend); | 105 | set_bit(port, &uhci->port_c_suspend); |
@@ -110,7 +110,7 @@ static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, | |||
110 | * Experiments show that some controllers take longer, so | 110 | * Experiments show that some controllers take longer, so |
111 | * we'll poll for completion. */ | 111 | * we'll poll for completion. */ |
112 | for (i = 0; i < 10; ++i) { | 112 | for (i = 0; i < 10; ++i) { |
113 | if (!(inw(port_addr) & SUSPEND_BITS)) | 113 | if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS)) |
114 | break; | 114 | break; |
115 | udelay(1); | 115 | udelay(1); |
116 | } | 116 | } |
@@ -121,12 +121,12 @@ static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, | |||
121 | /* Wait for the UHCI controller in HP's iLO2 server management chip. | 121 | /* Wait for the UHCI controller in HP's iLO2 server management chip. |
122 | * It can take up to 250 us to finish a reset and set the CSC bit. | 122 | * It can take up to 250 us to finish a reset and set the CSC bit. |
123 | */ | 123 | */ |
124 | static void wait_for_HP(unsigned long port_addr) | 124 | static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr) |
125 | { | 125 | { |
126 | int i; | 126 | int i; |
127 | 127 | ||
128 | for (i = 10; i < 250; i += 10) { | 128 | for (i = 10; i < 250; i += 10) { |
129 | if (inw(port_addr) & USBPORTSC_CSC) | 129 | if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC) |
130 | return; | 130 | return; |
131 | udelay(10); | 131 | udelay(10); |
132 | } | 132 | } |
@@ -140,8 +140,8 @@ static void uhci_check_ports(struct uhci_hcd *uhci) | |||
140 | int status; | 140 | int status; |
141 | 141 | ||
142 | for (port = 0; port < uhci->rh_numports; ++port) { | 142 | for (port = 0; port < uhci->rh_numports; ++port) { |
143 | port_addr = uhci->io_addr + USBPORTSC1 + 2 * port; | 143 | port_addr = USBPORTSC1 + 2 * port; |
144 | status = inw(port_addr); | 144 | status = uhci_readw(uhci, port_addr); |
145 | if (unlikely(status & USBPORTSC_PR)) { | 145 | if (unlikely(status & USBPORTSC_PR)) { |
146 | if (time_after_eq(jiffies, uhci->ports_timeout)) { | 146 | if (time_after_eq(jiffies, uhci->ports_timeout)) { |
147 | CLR_RH_PORTSTAT(USBPORTSC_PR); | 147 | CLR_RH_PORTSTAT(USBPORTSC_PR); |
@@ -149,9 +149,8 @@ static void uhci_check_ports(struct uhci_hcd *uhci) | |||
149 | 149 | ||
150 | /* HP's server management chip requires | 150 | /* HP's server management chip requires |
151 | * a longer delay. */ | 151 | * a longer delay. */ |
152 | if (to_pci_dev(uhci_dev(uhci))->vendor == | 152 | if (uhci->wait_for_hp) |
153 | PCI_VENDOR_ID_HP) | 153 | wait_for_HP(uhci, port_addr); |
154 | wait_for_HP(port_addr); | ||
155 | 154 | ||
156 | /* If the port was enabled before, turning | 155 | /* If the port was enabled before, turning |
157 | * reset on caused a port enable change. | 156 | * reset on caused a port enable change. |
@@ -242,7 +241,7 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
242 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | 241 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); |
243 | int status, lstatus, retval = 0, len = 0; | 242 | int status, lstatus, retval = 0, len = 0; |
244 | unsigned int port = wIndex - 1; | 243 | unsigned int port = wIndex - 1; |
245 | unsigned long port_addr = uhci->io_addr + USBPORTSC1 + 2 * port; | 244 | unsigned long port_addr = USBPORTSC1 + 2 * port; |
246 | u16 wPortChange, wPortStatus; | 245 | u16 wPortChange, wPortStatus; |
247 | unsigned long flags; | 246 | unsigned long flags; |
248 | 247 | ||
@@ -260,14 +259,13 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
260 | goto err; | 259 | goto err; |
261 | 260 | ||
262 | uhci_check_ports(uhci); | 261 | uhci_check_ports(uhci); |
263 | status = inw(port_addr); | 262 | status = uhci_readw(uhci, port_addr); |
264 | 263 | ||
265 | /* Intel controllers report the OverCurrent bit active on. | 264 | /* Intel controllers report the OverCurrent bit active on. |
266 | * VIA controllers report it active off, so we'll adjust the | 265 | * VIA controllers report it active off, so we'll adjust the |
267 | * bit value. (It's not standardized in the UHCI spec.) | 266 | * bit value. (It's not standardized in the UHCI spec.) |
268 | */ | 267 | */ |
269 | if (to_pci_dev(hcd->self.controller)->vendor == | 268 | if (uhci->oc_low) |
270 | PCI_VENDOR_ID_VIA) | ||
271 | status ^= USBPORTSC_OC; | 269 | status ^= USBPORTSC_OC; |
272 | 270 | ||
273 | /* UHCI doesn't support C_RESET (always false) */ | 271 | /* UHCI doesn't support C_RESET (always false) */ |
@@ -358,7 +356,7 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
358 | CLR_RH_PORTSTAT(USBPORTSC_PEC); | 356 | CLR_RH_PORTSTAT(USBPORTSC_PEC); |
359 | OK(0); | 357 | OK(0); |
360 | case USB_PORT_FEAT_SUSPEND: | 358 | case USB_PORT_FEAT_SUSPEND: |
361 | if (!(inw(port_addr) & USBPORTSC_SUSP)) { | 359 | if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) { |
362 | 360 | ||
363 | /* Make certain the port isn't suspended */ | 361 | /* Make certain the port isn't suspended */ |
364 | uhci_finish_suspend(uhci, port, port_addr); | 362 | uhci_finish_suspend(uhci, port, port_addr); |
@@ -370,7 +368,8 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
370 | * if the port is disabled. When this happens | 368 | * if the port is disabled. When this happens |
371 | * just skip the Resume signalling. | 369 | * just skip the Resume signalling. |
372 | */ | 370 | */ |
373 | if (!(inw(port_addr) & USBPORTSC_RD)) | 371 | if (!(uhci_readw(uhci, port_addr) & |
372 | USBPORTSC_RD)) | ||
374 | uhci_finish_suspend(uhci, port, | 373 | uhci_finish_suspend(uhci, port, |
375 | port_addr); | 374 | port_addr); |
376 | else | 375 | else |
diff --git a/drivers/usb/host/uhci-pci.c b/drivers/usb/host/uhci-pci.c new file mode 100644 index 000000000000..c300bd2f7d1c --- /dev/null +++ b/drivers/usb/host/uhci-pci.c | |||
@@ -0,0 +1,301 @@ | |||
1 | /* | ||
2 | * UHCI HCD (Host Controller Driver) PCI Bus Glue. | ||
3 | * | ||
4 | * Extracted from uhci-hcd.c: | ||
5 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | ||
6 | * | ||
7 | * (C) Copyright 1999 Linus Torvalds | ||
8 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | ||
9 | * (C) Copyright 1999 Randy Dunlap | ||
10 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | ||
11 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | ||
12 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | ||
13 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | ||
14 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | ||
15 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | ||
16 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | ||
17 | * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu | ||
18 | */ | ||
19 | |||
20 | #include "pci-quirks.h" | ||
21 | |||
22 | /* | ||
23 | * Make sure the controller is completely inactive, unable to | ||
24 | * generate interrupts or do DMA. | ||
25 | */ | ||
26 | static void uhci_pci_reset_hc(struct uhci_hcd *uhci) | ||
27 | { | ||
28 | uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr); | ||
29 | } | ||
30 | |||
31 | /* | ||
32 | * Initialize a controller that was newly discovered or has just been | ||
33 | * resumed. In either case we can't be sure of its previous state. | ||
34 | * | ||
35 | * Returns: 1 if the controller was reset, 0 otherwise. | ||
36 | */ | ||
37 | static int uhci_pci_check_and_reset_hc(struct uhci_hcd *uhci) | ||
38 | { | ||
39 | return uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), | ||
40 | uhci->io_addr); | ||
41 | } | ||
42 | |||
43 | /* | ||
44 | * Store the basic register settings needed by the controller. | ||
45 | * This function is called at the end of configure_hc in uhci-hcd.c. | ||
46 | */ | ||
47 | static void uhci_pci_configure_hc(struct uhci_hcd *uhci) | ||
48 | { | ||
49 | struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci)); | ||
50 | |||
51 | /* Enable PIRQ */ | ||
52 | pci_write_config_word(pdev, USBLEGSUP, USBLEGSUP_DEFAULT); | ||
53 | |||
54 | /* Disable platform-specific non-PME# wakeup */ | ||
55 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | ||
56 | pci_write_config_byte(pdev, USBRES_INTEL, 0); | ||
57 | } | ||
58 | |||
59 | static int uhci_pci_resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) | ||
60 | { | ||
61 | int port; | ||
62 | |||
63 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { | ||
64 | default: | ||
65 | break; | ||
66 | |||
67 | case PCI_VENDOR_ID_GENESYS: | ||
68 | /* Genesys Logic's GL880S controllers don't generate | ||
69 | * resume-detect interrupts. | ||
70 | */ | ||
71 | return 1; | ||
72 | |||
73 | case PCI_VENDOR_ID_INTEL: | ||
74 | /* Some of Intel's USB controllers have a bug that causes | ||
75 | * resume-detect interrupts if any port has an over-current | ||
76 | * condition. To make matters worse, some motherboards | ||
77 | * hardwire unused USB ports' over-current inputs active! | ||
78 | * To prevent problems, we will not enable resume-detect | ||
79 | * interrupts if any ports are OC. | ||
80 | */ | ||
81 | for (port = 0; port < uhci->rh_numports; ++port) { | ||
82 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | ||
83 | USBPORTSC_OC) | ||
84 | return 1; | ||
85 | } | ||
86 | break; | ||
87 | } | ||
88 | return 0; | ||
89 | } | ||
90 | |||
91 | static int uhci_pci_global_suspend_mode_is_broken(struct uhci_hcd *uhci) | ||
92 | { | ||
93 | int port; | ||
94 | const char *sys_info; | ||
95 | static const char bad_Asus_board[] = "A7V8X"; | ||
96 | |||
97 | /* One of Asus's motherboards has a bug which causes it to | ||
98 | * wake up immediately from suspend-to-RAM if any of the ports | ||
99 | * are connected. In such cases we will not set EGSM. | ||
100 | */ | ||
101 | sys_info = dmi_get_system_info(DMI_BOARD_NAME); | ||
102 | if (sys_info && !strcmp(sys_info, bad_Asus_board)) { | ||
103 | for (port = 0; port < uhci->rh_numports; ++port) { | ||
104 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | ||
105 | USBPORTSC_CCS) | ||
106 | return 1; | ||
107 | } | ||
108 | } | ||
109 | |||
110 | return 0; | ||
111 | } | ||
112 | |||
113 | static int uhci_pci_init(struct usb_hcd *hcd) | ||
114 | { | ||
115 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
116 | |||
117 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | ||
118 | |||
119 | uhci->rh_numports = uhci_count_ports(hcd); | ||
120 | |||
121 | /* Intel controllers report the OverCurrent bit active on. | ||
122 | * VIA controllers report it active off, so we'll adjust the | ||
123 | * bit value. (It's not standardized in the UHCI spec.) | ||
124 | */ | ||
125 | if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_VIA) | ||
126 | uhci->oc_low = 1; | ||
127 | |||
128 | /* HP's server management chip requires a longer port reset delay. */ | ||
129 | if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_HP) | ||
130 | uhci->wait_for_hp = 1; | ||
131 | |||
132 | /* Set up pointers to PCI-specific functions */ | ||
133 | uhci->reset_hc = uhci_pci_reset_hc; | ||
134 | uhci->check_and_reset_hc = uhci_pci_check_and_reset_hc; | ||
135 | uhci->configure_hc = uhci_pci_configure_hc; | ||
136 | uhci->resume_detect_interrupts_are_broken = | ||
137 | uhci_pci_resume_detect_interrupts_are_broken; | ||
138 | uhci->global_suspend_mode_is_broken = | ||
139 | uhci_pci_global_suspend_mode_is_broken; | ||
140 | |||
141 | |||
142 | /* Kick BIOS off this hardware and reset if the controller | ||
143 | * isn't already safely quiescent. | ||
144 | */ | ||
145 | check_and_reset_hc(uhci); | ||
146 | return 0; | ||
147 | } | ||
148 | |||
149 | /* Make sure the controller is quiescent and that we're not using it | ||
150 | * any more. This is mainly for the benefit of programs which, like kexec, | ||
151 | * expect the hardware to be idle: not doing DMA or generating IRQs. | ||
152 | * | ||
153 | * This routine may be called in a damaged or failing kernel. Hence we | ||
154 | * do not acquire the spinlock before shutting down the controller. | ||
155 | */ | ||
156 | static void uhci_shutdown(struct pci_dev *pdev) | ||
157 | { | ||
158 | struct usb_hcd *hcd = pci_get_drvdata(pdev); | ||
159 | |||
160 | uhci_hc_died(hcd_to_uhci(hcd)); | ||
161 | } | ||
162 | |||
163 | #ifdef CONFIG_PM | ||
164 | |||
165 | static int uhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | ||
166 | { | ||
167 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
168 | struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci)); | ||
169 | int rc = 0; | ||
170 | |||
171 | dev_dbg(uhci_dev(uhci), "%s\n", __func__); | ||
172 | |||
173 | spin_lock_irq(&uhci->lock); | ||
174 | if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) | ||
175 | goto done_okay; /* Already suspended or dead */ | ||
176 | |||
177 | if (uhci->rh_state > UHCI_RH_SUSPENDED) { | ||
178 | dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); | ||
179 | rc = -EBUSY; | ||
180 | goto done; | ||
181 | }; | ||
182 | |||
183 | /* All PCI host controllers are required to disable IRQ generation | ||
184 | * at the source, so we must turn off PIRQ. | ||
185 | */ | ||
186 | pci_write_config_word(pdev, USBLEGSUP, 0); | ||
187 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | ||
188 | |||
189 | /* Enable platform-specific non-PME# wakeup */ | ||
190 | if (do_wakeup) { | ||
191 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | ||
192 | pci_write_config_byte(pdev, USBRES_INTEL, | ||
193 | USBPORT1EN | USBPORT2EN); | ||
194 | } | ||
195 | |||
196 | done_okay: | ||
197 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
198 | done: | ||
199 | spin_unlock_irq(&uhci->lock); | ||
200 | return rc; | ||
201 | } | ||
202 | |||
203 | static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | ||
204 | { | ||
205 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | ||
206 | |||
207 | dev_dbg(uhci_dev(uhci), "%s\n", __func__); | ||
208 | |||
209 | /* Since we aren't in D3 any more, it's safe to set this flag | ||
210 | * even if the controller was dead. | ||
211 | */ | ||
212 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
213 | |||
214 | spin_lock_irq(&uhci->lock); | ||
215 | |||
216 | /* Make sure resume from hibernation re-enumerates everything */ | ||
217 | if (hibernated) { | ||
218 | uhci->reset_hc(uhci); | ||
219 | finish_reset(uhci); | ||
220 | } | ||
221 | |||
222 | /* The firmware may have changed the controller settings during | ||
223 | * a system wakeup. Check it and reconfigure to avoid problems. | ||
224 | */ | ||
225 | else { | ||
226 | check_and_reset_hc(uhci); | ||
227 | } | ||
228 | configure_hc(uhci); | ||
229 | |||
230 | /* Tell the core if the controller had to be reset */ | ||
231 | if (uhci->rh_state == UHCI_RH_RESET) | ||
232 | usb_root_hub_lost_power(hcd->self.root_hub); | ||
233 | |||
234 | spin_unlock_irq(&uhci->lock); | ||
235 | |||
236 | /* If interrupts don't work and remote wakeup is enabled then | ||
237 | * the suspended root hub needs to be polled. | ||
238 | */ | ||
239 | if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup) | ||
240 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | ||
241 | |||
242 | /* Does the root hub have a port wakeup pending? */ | ||
243 | usb_hcd_poll_rh_status(hcd); | ||
244 | return 0; | ||
245 | } | ||
246 | |||
247 | #endif | ||
248 | |||
249 | static const struct hc_driver uhci_driver = { | ||
250 | .description = hcd_name, | ||
251 | .product_desc = "UHCI Host Controller", | ||
252 | .hcd_priv_size = sizeof(struct uhci_hcd), | ||
253 | |||
254 | /* Generic hardware linkage */ | ||
255 | .irq = uhci_irq, | ||
256 | .flags = HCD_USB11, | ||
257 | |||
258 | /* Basic lifecycle operations */ | ||
259 | .reset = uhci_pci_init, | ||
260 | .start = uhci_start, | ||
261 | #ifdef CONFIG_PM | ||
262 | .pci_suspend = uhci_pci_suspend, | ||
263 | .pci_resume = uhci_pci_resume, | ||
264 | .bus_suspend = uhci_rh_suspend, | ||
265 | .bus_resume = uhci_rh_resume, | ||
266 | #endif | ||
267 | .stop = uhci_stop, | ||
268 | |||
269 | .urb_enqueue = uhci_urb_enqueue, | ||
270 | .urb_dequeue = uhci_urb_dequeue, | ||
271 | |||
272 | .endpoint_disable = uhci_hcd_endpoint_disable, | ||
273 | .get_frame_number = uhci_hcd_get_frame_number, | ||
274 | |||
275 | .hub_status_data = uhci_hub_status_data, | ||
276 | .hub_control = uhci_hub_control, | ||
277 | }; | ||
278 | |||
279 | static DEFINE_PCI_DEVICE_TABLE(uhci_pci_ids) = { { | ||
280 | /* handle any USB UHCI controller */ | ||
281 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0), | ||
282 | .driver_data = (unsigned long) &uhci_driver, | ||
283 | }, { /* end: all zeroes */ } | ||
284 | }; | ||
285 | |||
286 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | ||
287 | |||
288 | static struct pci_driver uhci_pci_driver = { | ||
289 | .name = (char *)hcd_name, | ||
290 | .id_table = uhci_pci_ids, | ||
291 | |||
292 | .probe = usb_hcd_pci_probe, | ||
293 | .remove = usb_hcd_pci_remove, | ||
294 | .shutdown = uhci_shutdown, | ||
295 | |||
296 | #ifdef CONFIG_PM_SLEEP | ||
297 | .driver = { | ||
298 | .pm = &usb_hcd_pci_pm_ops | ||
299 | }, | ||
300 | #endif | ||
301 | }; | ||
diff --git a/drivers/usb/host/uhci-q.c b/drivers/usb/host/uhci-q.c index d3ade4018487..84ed28b34f93 100644 --- a/drivers/usb/host/uhci-q.c +++ b/drivers/usb/host/uhci-q.c | |||
@@ -29,12 +29,12 @@ static void uhci_set_next_interrupt(struct uhci_hcd *uhci) | |||
29 | { | 29 | { |
30 | if (uhci->is_stopped) | 30 | if (uhci->is_stopped) |
31 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | 31 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); |
32 | uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC); | 32 | uhci->term_td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC); |
33 | } | 33 | } |
34 | 34 | ||
35 | static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci) | 35 | static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci) |
36 | { | 36 | { |
37 | uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC); | 37 | uhci->term_td->status &= ~cpu_to_hc32(uhci, TD_CTRL_IOC); |
38 | } | 38 | } |
39 | 39 | ||
40 | 40 | ||
@@ -53,7 +53,7 @@ static void uhci_fsbr_on(struct uhci_hcd *uhci) | |||
53 | uhci->fsbr_is_on = 1; | 53 | uhci->fsbr_is_on = 1; |
54 | lqh = list_entry(uhci->skel_async_qh->node.prev, | 54 | lqh = list_entry(uhci->skel_async_qh->node.prev, |
55 | struct uhci_qh, node); | 55 | struct uhci_qh, node); |
56 | lqh->link = LINK_TO_QH(uhci->skel_term_qh); | 56 | lqh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); |
57 | } | 57 | } |
58 | 58 | ||
59 | static void uhci_fsbr_off(struct uhci_hcd *uhci) | 59 | static void uhci_fsbr_off(struct uhci_hcd *uhci) |
@@ -65,7 +65,7 @@ static void uhci_fsbr_off(struct uhci_hcd *uhci) | |||
65 | uhci->fsbr_is_on = 0; | 65 | uhci->fsbr_is_on = 0; |
66 | lqh = list_entry(uhci->skel_async_qh->node.prev, | 66 | lqh = list_entry(uhci->skel_async_qh->node.prev, |
67 | struct uhci_qh, node); | 67 | struct uhci_qh, node); |
68 | lqh->link = UHCI_PTR_TERM; | 68 | lqh->link = UHCI_PTR_TERM(uhci); |
69 | } | 69 | } |
70 | 70 | ||
71 | static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb) | 71 | static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb) |
@@ -131,12 +131,12 @@ static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td) | |||
131 | dma_pool_free(uhci->td_pool, td, td->dma_handle); | 131 | dma_pool_free(uhci->td_pool, td, td->dma_handle); |
132 | } | 132 | } |
133 | 133 | ||
134 | static inline void uhci_fill_td(struct uhci_td *td, u32 status, | 134 | static inline void uhci_fill_td(struct uhci_hcd *uhci, struct uhci_td *td, |
135 | u32 token, u32 buffer) | 135 | u32 status, u32 token, u32 buffer) |
136 | { | 136 | { |
137 | td->status = cpu_to_le32(status); | 137 | td->status = cpu_to_hc32(uhci, status); |
138 | td->token = cpu_to_le32(token); | 138 | td->token = cpu_to_hc32(uhci, token); |
139 | td->buffer = cpu_to_le32(buffer); | 139 | td->buffer = cpu_to_hc32(uhci, buffer); |
140 | } | 140 | } |
141 | 141 | ||
142 | static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp) | 142 | static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp) |
@@ -170,11 +170,11 @@ static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci, | |||
170 | 170 | ||
171 | td->link = ltd->link; | 171 | td->link = ltd->link; |
172 | wmb(); | 172 | wmb(); |
173 | ltd->link = LINK_TO_TD(td); | 173 | ltd->link = LINK_TO_TD(uhci, td); |
174 | } else { | 174 | } else { |
175 | td->link = uhci->frame[framenum]; | 175 | td->link = uhci->frame[framenum]; |
176 | wmb(); | 176 | wmb(); |
177 | uhci->frame[framenum] = LINK_TO_TD(td); | 177 | uhci->frame[framenum] = LINK_TO_TD(uhci, td); |
178 | uhci->frame_cpu[framenum] = td; | 178 | uhci->frame_cpu[framenum] = td; |
179 | } | 179 | } |
180 | } | 180 | } |
@@ -195,8 +195,10 @@ static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci, | |||
195 | } else { | 195 | } else { |
196 | struct uhci_td *ntd; | 196 | struct uhci_td *ntd; |
197 | 197 | ||
198 | ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list); | 198 | ntd = list_entry(td->fl_list.next, |
199 | uhci->frame[td->frame] = LINK_TO_TD(ntd); | 199 | struct uhci_td, |
200 | fl_list); | ||
201 | uhci->frame[td->frame] = LINK_TO_TD(uhci, ntd); | ||
200 | uhci->frame_cpu[td->frame] = ntd; | 202 | uhci->frame_cpu[td->frame] = ntd; |
201 | } | 203 | } |
202 | } else { | 204 | } else { |
@@ -253,8 +255,8 @@ static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci, | |||
253 | memset(qh, 0, sizeof(*qh)); | 255 | memset(qh, 0, sizeof(*qh)); |
254 | qh->dma_handle = dma_handle; | 256 | qh->dma_handle = dma_handle; |
255 | 257 | ||
256 | qh->element = UHCI_PTR_TERM; | 258 | qh->element = UHCI_PTR_TERM(uhci); |
257 | qh->link = UHCI_PTR_TERM; | 259 | qh->link = UHCI_PTR_TERM(uhci); |
258 | 260 | ||
259 | INIT_LIST_HEAD(&qh->queue); | 261 | INIT_LIST_HEAD(&qh->queue); |
260 | INIT_LIST_HEAD(&qh->node); | 262 | INIT_LIST_HEAD(&qh->node); |
@@ -346,9 +348,9 @@ static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh, | |||
346 | 348 | ||
347 | /* If the QH element pointer is UHCI_PTR_TERM then then currently | 349 | /* If the QH element pointer is UHCI_PTR_TERM then then currently |
348 | * executing URB has already been unlinked, so this one isn't it. */ | 350 | * executing URB has already been unlinked, so this one isn't it. */ |
349 | if (qh_element(qh) == UHCI_PTR_TERM) | 351 | if (qh_element(qh) == UHCI_PTR_TERM(uhci)) |
350 | goto done; | 352 | goto done; |
351 | qh->element = UHCI_PTR_TERM; | 353 | qh->element = UHCI_PTR_TERM(uhci); |
352 | 354 | ||
353 | /* Control pipes don't have to worry about toggles */ | 355 | /* Control pipes don't have to worry about toggles */ |
354 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) | 356 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) |
@@ -358,7 +360,7 @@ static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh, | |||
358 | WARN_ON(list_empty(&urbp->td_list)); | 360 | WARN_ON(list_empty(&urbp->td_list)); |
359 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | 361 | td = list_entry(urbp->td_list.next, struct uhci_td, list); |
360 | qh->needs_fixup = 1; | 362 | qh->needs_fixup = 1; |
361 | qh->initial_toggle = uhci_toggle(td_token(td)); | 363 | qh->initial_toggle = uhci_toggle(td_token(uhci, td)); |
362 | 364 | ||
363 | done: | 365 | done: |
364 | return ret; | 366 | return ret; |
@@ -368,7 +370,8 @@ done: | |||
368 | * Fix up the data toggles for URBs in a queue, when one of them | 370 | * Fix up the data toggles for URBs in a queue, when one of them |
369 | * terminates early (short transfer, error, or dequeued). | 371 | * terminates early (short transfer, error, or dequeued). |
370 | */ | 372 | */ |
371 | static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first) | 373 | static void uhci_fixup_toggles(struct uhci_hcd *uhci, struct uhci_qh *qh, |
374 | int skip_first) | ||
372 | { | 375 | { |
373 | struct urb_priv *urbp = NULL; | 376 | struct urb_priv *urbp = NULL; |
374 | struct uhci_td *td; | 377 | struct uhci_td *td; |
@@ -382,7 +385,7 @@ static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first) | |||
382 | 385 | ||
383 | /* When starting with the first URB, if the QH element pointer is | 386 | /* When starting with the first URB, if the QH element pointer is |
384 | * still valid then we know the URB's toggles are okay. */ | 387 | * still valid then we know the URB's toggles are okay. */ |
385 | else if (qh_element(qh) != UHCI_PTR_TERM) | 388 | else if (qh_element(qh) != UHCI_PTR_TERM(uhci)) |
386 | toggle = 2; | 389 | toggle = 2; |
387 | 390 | ||
388 | /* Fix up the toggle for the URBs in the queue. Normally this | 391 | /* Fix up the toggle for the URBs in the queue. Normally this |
@@ -394,15 +397,15 @@ static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first) | |||
394 | /* If the first TD has the right toggle value, we don't | 397 | /* If the first TD has the right toggle value, we don't |
395 | * need to change any toggles in this URB */ | 398 | * need to change any toggles in this URB */ |
396 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | 399 | td = list_entry(urbp->td_list.next, struct uhci_td, list); |
397 | if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) { | 400 | if (toggle > 1 || uhci_toggle(td_token(uhci, td)) == toggle) { |
398 | td = list_entry(urbp->td_list.prev, struct uhci_td, | 401 | td = list_entry(urbp->td_list.prev, struct uhci_td, |
399 | list); | 402 | list); |
400 | toggle = uhci_toggle(td_token(td)) ^ 1; | 403 | toggle = uhci_toggle(td_token(uhci, td)) ^ 1; |
401 | 404 | ||
402 | /* Otherwise all the toggles in the URB have to be switched */ | 405 | /* Otherwise all the toggles in the URB have to be switched */ |
403 | } else { | 406 | } else { |
404 | list_for_each_entry(td, &urbp->td_list, list) { | 407 | list_for_each_entry(td, &urbp->td_list, list) { |
405 | td->token ^= cpu_to_le32( | 408 | td->token ^= cpu_to_hc32(uhci, |
406 | TD_TOKEN_TOGGLE); | 409 | TD_TOKEN_TOGGLE); |
407 | toggle ^= 1; | 410 | toggle ^= 1; |
408 | } | 411 | } |
@@ -439,7 +442,7 @@ static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
439 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | 442 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); |
440 | qh->link = pqh->link; | 443 | qh->link = pqh->link; |
441 | wmb(); | 444 | wmb(); |
442 | pqh->link = LINK_TO_QH(qh); | 445 | pqh->link = LINK_TO_QH(uhci, qh); |
443 | } | 446 | } |
444 | 447 | ||
445 | /* | 448 | /* |
@@ -449,7 +452,7 @@ static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
449 | static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh) | 452 | static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh) |
450 | { | 453 | { |
451 | struct uhci_qh *pqh; | 454 | struct uhci_qh *pqh; |
452 | __le32 link_to_new_qh; | 455 | __hc32 link_to_new_qh; |
453 | 456 | ||
454 | /* Find the predecessor QH for our new one and insert it in the list. | 457 | /* Find the predecessor QH for our new one and insert it in the list. |
455 | * The list of QHs is expected to be short, so linear search won't | 458 | * The list of QHs is expected to be short, so linear search won't |
@@ -463,7 +466,7 @@ static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
463 | /* Link it into the schedule */ | 466 | /* Link it into the schedule */ |
464 | qh->link = pqh->link; | 467 | qh->link = pqh->link; |
465 | wmb(); | 468 | wmb(); |
466 | link_to_new_qh = LINK_TO_QH(qh); | 469 | link_to_new_qh = LINK_TO_QH(uhci, qh); |
467 | pqh->link = link_to_new_qh; | 470 | pqh->link = link_to_new_qh; |
468 | 471 | ||
469 | /* If this is now the first FSBR QH, link the terminating skeleton | 472 | /* If this is now the first FSBR QH, link the terminating skeleton |
@@ -481,13 +484,13 @@ static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
481 | 484 | ||
482 | /* Set the element pointer if it isn't set already. | 485 | /* Set the element pointer if it isn't set already. |
483 | * This isn't needed for Isochronous queues, but it doesn't hurt. */ | 486 | * This isn't needed for Isochronous queues, but it doesn't hurt. */ |
484 | if (qh_element(qh) == UHCI_PTR_TERM) { | 487 | if (qh_element(qh) == UHCI_PTR_TERM(uhci)) { |
485 | struct urb_priv *urbp = list_entry(qh->queue.next, | 488 | struct urb_priv *urbp = list_entry(qh->queue.next, |
486 | struct urb_priv, node); | 489 | struct urb_priv, node); |
487 | struct uhci_td *td = list_entry(urbp->td_list.next, | 490 | struct uhci_td *td = list_entry(urbp->td_list.next, |
488 | struct uhci_td, list); | 491 | struct uhci_td, list); |
489 | 492 | ||
490 | qh->element = LINK_TO_TD(td); | 493 | qh->element = LINK_TO_TD(uhci, td); |
491 | } | 494 | } |
492 | 495 | ||
493 | /* Treat the queue as if it has just advanced */ | 496 | /* Treat the queue as if it has just advanced */ |
@@ -531,7 +534,7 @@ static void unlink_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
531 | static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh) | 534 | static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh) |
532 | { | 535 | { |
533 | struct uhci_qh *pqh; | 536 | struct uhci_qh *pqh; |
534 | __le32 link_to_next_qh = qh->link; | 537 | __hc32 link_to_next_qh = qh->link; |
535 | 538 | ||
536 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | 539 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); |
537 | pqh->link = link_to_next_qh; | 540 | pqh->link = link_to_next_qh; |
@@ -728,7 +731,7 @@ static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, | |||
728 | 731 | ||
729 | urbp->urb = urb; | 732 | urbp->urb = urb; |
730 | urb->hcpriv = urbp; | 733 | urb->hcpriv = urbp; |
731 | 734 | ||
732 | INIT_LIST_HEAD(&urbp->node); | 735 | INIT_LIST_HEAD(&urbp->node); |
733 | INIT_LIST_HEAD(&urbp->td_list); | 736 | INIT_LIST_HEAD(&urbp->td_list); |
734 | 737 | ||
@@ -755,8 +758,8 @@ static void uhci_free_urb_priv(struct uhci_hcd *uhci, | |||
755 | /* | 758 | /* |
756 | * Map status to standard result codes | 759 | * Map status to standard result codes |
757 | * | 760 | * |
758 | * <status> is (td_status(td) & 0xF60000), a.k.a. | 761 | * <status> is (td_status(uhci, td) & 0xF60000), a.k.a. |
759 | * uhci_status_bits(td_status(td)). | 762 | * uhci_status_bits(td_status(uhci, td)). |
760 | * Note: <status> does not include the TD_CTRL_NAK bit. | 763 | * Note: <status> does not include the TD_CTRL_NAK bit. |
761 | * <dir_out> is True for output TDs and False for input TDs. | 764 | * <dir_out> is True for output TDs and False for input TDs. |
762 | */ | 765 | */ |
@@ -792,7 +795,7 @@ static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, | |||
792 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); | 795 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
793 | int len = urb->transfer_buffer_length; | 796 | int len = urb->transfer_buffer_length; |
794 | dma_addr_t data = urb->transfer_dma; | 797 | dma_addr_t data = urb->transfer_dma; |
795 | __le32 *plink; | 798 | __hc32 *plink; |
796 | struct urb_priv *urbp = urb->hcpriv; | 799 | struct urb_priv *urbp = urb->hcpriv; |
797 | int skel; | 800 | int skel; |
798 | 801 | ||
@@ -809,7 +812,7 @@ static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, | |||
809 | */ | 812 | */ |
810 | td = qh->dummy_td; | 813 | td = qh->dummy_td; |
811 | uhci_add_td_to_urbp(td, urbp); | 814 | uhci_add_td_to_urbp(td, urbp); |
812 | uhci_fill_td(td, status, destination | uhci_explen(8), | 815 | uhci_fill_td(uhci, td, status, destination | uhci_explen(8), |
813 | urb->setup_dma); | 816 | urb->setup_dma); |
814 | plink = &td->link; | 817 | plink = &td->link; |
815 | status |= TD_CTRL_ACTIVE; | 818 | status |= TD_CTRL_ACTIVE; |
@@ -842,14 +845,14 @@ static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, | |||
842 | td = uhci_alloc_td(uhci); | 845 | td = uhci_alloc_td(uhci); |
843 | if (!td) | 846 | if (!td) |
844 | goto nomem; | 847 | goto nomem; |
845 | *plink = LINK_TO_TD(td); | 848 | *plink = LINK_TO_TD(uhci, td); |
846 | 849 | ||
847 | /* Alternate Data0/1 (start with Data1) */ | 850 | /* Alternate Data0/1 (start with Data1) */ |
848 | destination ^= TD_TOKEN_TOGGLE; | 851 | destination ^= TD_TOKEN_TOGGLE; |
849 | 852 | ||
850 | uhci_add_td_to_urbp(td, urbp); | 853 | uhci_add_td_to_urbp(td, urbp); |
851 | uhci_fill_td(td, status, destination | uhci_explen(pktsze), | 854 | uhci_fill_td(uhci, td, status, |
852 | data); | 855 | destination | uhci_explen(pktsze), data); |
853 | plink = &td->link; | 856 | plink = &td->link; |
854 | 857 | ||
855 | data += pktsze; | 858 | data += pktsze; |
@@ -857,19 +860,19 @@ static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, | |||
857 | } | 860 | } |
858 | 861 | ||
859 | /* | 862 | /* |
860 | * Build the final TD for control status | 863 | * Build the final TD for control status |
861 | */ | 864 | */ |
862 | td = uhci_alloc_td(uhci); | 865 | td = uhci_alloc_td(uhci); |
863 | if (!td) | 866 | if (!td) |
864 | goto nomem; | 867 | goto nomem; |
865 | *plink = LINK_TO_TD(td); | 868 | *plink = LINK_TO_TD(uhci, td); |
866 | 869 | ||
867 | /* Change direction for the status transaction */ | 870 | /* Change direction for the status transaction */ |
868 | destination ^= (USB_PID_IN ^ USB_PID_OUT); | 871 | destination ^= (USB_PID_IN ^ USB_PID_OUT); |
869 | destination |= TD_TOKEN_TOGGLE; /* End in Data1 */ | 872 | destination |= TD_TOKEN_TOGGLE; /* End in Data1 */ |
870 | 873 | ||
871 | uhci_add_td_to_urbp(td, urbp); | 874 | uhci_add_td_to_urbp(td, urbp); |
872 | uhci_fill_td(td, status | TD_CTRL_IOC, | 875 | uhci_fill_td(uhci, td, status | TD_CTRL_IOC, |
873 | destination | uhci_explen(0), 0); | 876 | destination | uhci_explen(0), 0); |
874 | plink = &td->link; | 877 | plink = &td->link; |
875 | 878 | ||
@@ -879,11 +882,11 @@ static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, | |||
879 | td = uhci_alloc_td(uhci); | 882 | td = uhci_alloc_td(uhci); |
880 | if (!td) | 883 | if (!td) |
881 | goto nomem; | 884 | goto nomem; |
882 | *plink = LINK_TO_TD(td); | 885 | *plink = LINK_TO_TD(uhci, td); |
883 | 886 | ||
884 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | 887 | uhci_fill_td(uhci, td, 0, USB_PID_OUT | uhci_explen(0), 0); |
885 | wmb(); | 888 | wmb(); |
886 | qh->dummy_td->status |= cpu_to_le32(TD_CTRL_ACTIVE); | 889 | qh->dummy_td->status |= cpu_to_hc32(uhci, TD_CTRL_ACTIVE); |
887 | qh->dummy_td = td; | 890 | qh->dummy_td = td; |
888 | 891 | ||
889 | /* Low-speed transfers get a different queue, and won't hog the bus. | 892 | /* Low-speed transfers get a different queue, and won't hog the bus. |
@@ -917,10 +920,13 @@ static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, | |||
917 | unsigned long destination, status; | 920 | unsigned long destination, status; |
918 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); | 921 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
919 | int len = urb->transfer_buffer_length; | 922 | int len = urb->transfer_buffer_length; |
920 | dma_addr_t data = urb->transfer_dma; | 923 | int this_sg_len; |
921 | __le32 *plink; | 924 | dma_addr_t data; |
925 | __hc32 *plink; | ||
922 | struct urb_priv *urbp = urb->hcpriv; | 926 | struct urb_priv *urbp = urb->hcpriv; |
923 | unsigned int toggle; | 927 | unsigned int toggle; |
928 | struct scatterlist *sg; | ||
929 | int i; | ||
924 | 930 | ||
925 | if (len < 0) | 931 | if (len < 0) |
926 | return -EINVAL; | 932 | return -EINVAL; |
@@ -937,12 +943,26 @@ static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, | |||
937 | if (usb_pipein(urb->pipe)) | 943 | if (usb_pipein(urb->pipe)) |
938 | status |= TD_CTRL_SPD; | 944 | status |= TD_CTRL_SPD; |
939 | 945 | ||
946 | i = urb->num_sgs; | ||
947 | if (len > 0 && i > 0) { | ||
948 | sg = urb->sg; | ||
949 | data = sg_dma_address(sg); | ||
950 | |||
951 | /* urb->transfer_buffer_length may be smaller than the | ||
952 | * size of the scatterlist (or vice versa) | ||
953 | */ | ||
954 | this_sg_len = min_t(int, sg_dma_len(sg), len); | ||
955 | } else { | ||
956 | sg = NULL; | ||
957 | data = urb->transfer_dma; | ||
958 | this_sg_len = len; | ||
959 | } | ||
940 | /* | 960 | /* |
941 | * Build the DATA TDs | 961 | * Build the DATA TDs |
942 | */ | 962 | */ |
943 | plink = NULL; | 963 | plink = NULL; |
944 | td = qh->dummy_td; | 964 | td = qh->dummy_td; |
945 | do { /* Allow zero length packets */ | 965 | for (;;) { /* Allow zero length packets */ |
946 | int pktsze = maxsze; | 966 | int pktsze = maxsze; |
947 | 967 | ||
948 | if (len <= pktsze) { /* The last packet */ | 968 | if (len <= pktsze) { /* The last packet */ |
@@ -955,20 +975,28 @@ static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, | |||
955 | td = uhci_alloc_td(uhci); | 975 | td = uhci_alloc_td(uhci); |
956 | if (!td) | 976 | if (!td) |
957 | goto nomem; | 977 | goto nomem; |
958 | *plink = LINK_TO_TD(td); | 978 | *plink = LINK_TO_TD(uhci, td); |
959 | } | 979 | } |
960 | uhci_add_td_to_urbp(td, urbp); | 980 | uhci_add_td_to_urbp(td, urbp); |
961 | uhci_fill_td(td, status, | 981 | uhci_fill_td(uhci, td, status, |
962 | destination | uhci_explen(pktsze) | | 982 | destination | uhci_explen(pktsze) | |
963 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | 983 | (toggle << TD_TOKEN_TOGGLE_SHIFT), |
964 | data); | 984 | data); |
965 | plink = &td->link; | 985 | plink = &td->link; |
966 | status |= TD_CTRL_ACTIVE; | 986 | status |= TD_CTRL_ACTIVE; |
967 | 987 | ||
988 | toggle ^= 1; | ||
968 | data += pktsze; | 989 | data += pktsze; |
990 | this_sg_len -= pktsze; | ||
969 | len -= maxsze; | 991 | len -= maxsze; |
970 | toggle ^= 1; | 992 | if (this_sg_len <= 0) { |
971 | } while (len > 0); | 993 | if (--i <= 0 || len <= 0) |
994 | break; | ||
995 | sg = sg_next(sg); | ||
996 | data = sg_dma_address(sg); | ||
997 | this_sg_len = min_t(int, sg_dma_len(sg), len); | ||
998 | } | ||
999 | } | ||
972 | 1000 | ||
973 | /* | 1001 | /* |
974 | * URB_ZERO_PACKET means adding a 0-length packet, if direction | 1002 | * URB_ZERO_PACKET means adding a 0-length packet, if direction |
@@ -983,10 +1011,10 @@ static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, | |||
983 | td = uhci_alloc_td(uhci); | 1011 | td = uhci_alloc_td(uhci); |
984 | if (!td) | 1012 | if (!td) |
985 | goto nomem; | 1013 | goto nomem; |
986 | *plink = LINK_TO_TD(td); | 1014 | *plink = LINK_TO_TD(uhci, td); |
987 | 1015 | ||
988 | uhci_add_td_to_urbp(td, urbp); | 1016 | uhci_add_td_to_urbp(td, urbp); |
989 | uhci_fill_td(td, status, | 1017 | uhci_fill_td(uhci, td, status, |
990 | destination | uhci_explen(0) | | 1018 | destination | uhci_explen(0) | |
991 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | 1019 | (toggle << TD_TOKEN_TOGGLE_SHIFT), |
992 | data); | 1020 | data); |
@@ -1001,7 +1029,7 @@ static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, | |||
1001 | * fast side but not enough to justify delaying an interrupt | 1029 | * fast side but not enough to justify delaying an interrupt |
1002 | * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT | 1030 | * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT |
1003 | * flag setting. */ | 1031 | * flag setting. */ |
1004 | td->status |= cpu_to_le32(TD_CTRL_IOC); | 1032 | td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC); |
1005 | 1033 | ||
1006 | /* | 1034 | /* |
1007 | * Build the new dummy TD and activate the old one | 1035 | * Build the new dummy TD and activate the old one |
@@ -1009,11 +1037,11 @@ static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, | |||
1009 | td = uhci_alloc_td(uhci); | 1037 | td = uhci_alloc_td(uhci); |
1010 | if (!td) | 1038 | if (!td) |
1011 | goto nomem; | 1039 | goto nomem; |
1012 | *plink = LINK_TO_TD(td); | 1040 | *plink = LINK_TO_TD(uhci, td); |
1013 | 1041 | ||
1014 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | 1042 | uhci_fill_td(uhci, td, 0, USB_PID_OUT | uhci_explen(0), 0); |
1015 | wmb(); | 1043 | wmb(); |
1016 | qh->dummy_td->status |= cpu_to_le32(TD_CTRL_ACTIVE); | 1044 | qh->dummy_td->status |= cpu_to_hc32(uhci, TD_CTRL_ACTIVE); |
1017 | qh->dummy_td = td; | 1045 | qh->dummy_td = td; |
1018 | 1046 | ||
1019 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | 1047 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), |
@@ -1106,7 +1134,7 @@ static int uhci_fixup_short_transfer(struct uhci_hcd *uhci, | |||
1106 | * the queue at the status stage transaction, which is | 1134 | * the queue at the status stage transaction, which is |
1107 | * the last TD. */ | 1135 | * the last TD. */ |
1108 | WARN_ON(list_empty(&urbp->td_list)); | 1136 | WARN_ON(list_empty(&urbp->td_list)); |
1109 | qh->element = LINK_TO_TD(td); | 1137 | qh->element = LINK_TO_TD(uhci, td); |
1110 | tmp = td->list.prev; | 1138 | tmp = td->list.prev; |
1111 | ret = -EINPROGRESS; | 1139 | ret = -EINPROGRESS; |
1112 | 1140 | ||
@@ -1115,8 +1143,9 @@ static int uhci_fixup_short_transfer(struct uhci_hcd *uhci, | |||
1115 | /* When a bulk/interrupt transfer is short, we have to | 1143 | /* When a bulk/interrupt transfer is short, we have to |
1116 | * fix up the toggles of the following URBs on the queue | 1144 | * fix up the toggles of the following URBs on the queue |
1117 | * before restarting the queue at the next URB. */ | 1145 | * before restarting the queue at the next URB. */ |
1118 | qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1; | 1146 | qh->initial_toggle = |
1119 | uhci_fixup_toggles(qh, 1); | 1147 | uhci_toggle(td_token(uhci, qh->post_td)) ^ 1; |
1148 | uhci_fixup_toggles(uhci, qh, 1); | ||
1120 | 1149 | ||
1121 | if (list_empty(&urbp->td_list)) | 1150 | if (list_empty(&urbp->td_list)) |
1122 | td = qh->post_td; | 1151 | td = qh->post_td; |
@@ -1151,7 +1180,7 @@ static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb) | |||
1151 | unsigned int ctrlstat; | 1180 | unsigned int ctrlstat; |
1152 | int len; | 1181 | int len; |
1153 | 1182 | ||
1154 | ctrlstat = td_status(td); | 1183 | ctrlstat = td_status(uhci, td); |
1155 | status = uhci_status_bits(ctrlstat); | 1184 | status = uhci_status_bits(ctrlstat); |
1156 | if (status & TD_CTRL_ACTIVE) | 1185 | if (status & TD_CTRL_ACTIVE) |
1157 | return -EINPROGRESS; | 1186 | return -EINPROGRESS; |
@@ -1161,7 +1190,7 @@ static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb) | |||
1161 | 1190 | ||
1162 | if (status) { | 1191 | if (status) { |
1163 | ret = uhci_map_status(status, | 1192 | ret = uhci_map_status(status, |
1164 | uhci_packetout(td_token(td))); | 1193 | uhci_packetout(td_token(uhci, td))); |
1165 | if ((debug == 1 && ret != -EPIPE) || debug > 1) { | 1194 | if ((debug == 1 && ret != -EPIPE) || debug > 1) { |
1166 | /* Some debugging code */ | 1195 | /* Some debugging code */ |
1167 | dev_dbg(&urb->dev->dev, | 1196 | dev_dbg(&urb->dev->dev, |
@@ -1177,7 +1206,7 @@ static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb) | |||
1177 | } | 1206 | } |
1178 | 1207 | ||
1179 | /* Did we receive a short packet? */ | 1208 | /* Did we receive a short packet? */ |
1180 | } else if (len < uhci_expected_length(td_token(td))) { | 1209 | } else if (len < uhci_expected_length(td_token(uhci, td))) { |
1181 | 1210 | ||
1182 | /* For control transfers, go to the status TD if | 1211 | /* For control transfers, go to the status TD if |
1183 | * this isn't already the last data TD */ | 1212 | * this isn't already the last data TD */ |
@@ -1209,10 +1238,10 @@ err: | |||
1209 | if (ret < 0) { | 1238 | if (ret < 0) { |
1210 | /* Note that the queue has stopped and save | 1239 | /* Note that the queue has stopped and save |
1211 | * the next toggle value */ | 1240 | * the next toggle value */ |
1212 | qh->element = UHCI_PTR_TERM; | 1241 | qh->element = UHCI_PTR_TERM(uhci); |
1213 | qh->is_stopped = 1; | 1242 | qh->is_stopped = 1; |
1214 | qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL); | 1243 | qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL); |
1215 | qh->initial_toggle = uhci_toggle(td_token(td)) ^ | 1244 | qh->initial_toggle = uhci_toggle(td_token(uhci, td)) ^ |
1216 | (ret == -EREMOTEIO); | 1245 | (ret == -EREMOTEIO); |
1217 | 1246 | ||
1218 | } else /* Short packet received */ | 1247 | } else /* Short packet received */ |
@@ -1308,14 +1337,14 @@ static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb, | |||
1308 | return -ENOMEM; | 1337 | return -ENOMEM; |
1309 | 1338 | ||
1310 | uhci_add_td_to_urbp(td, urbp); | 1339 | uhci_add_td_to_urbp(td, urbp); |
1311 | uhci_fill_td(td, status, destination | | 1340 | uhci_fill_td(uhci, td, status, destination | |
1312 | uhci_explen(urb->iso_frame_desc[i].length), | 1341 | uhci_explen(urb->iso_frame_desc[i].length), |
1313 | urb->transfer_dma + | 1342 | urb->transfer_dma + |
1314 | urb->iso_frame_desc[i].offset); | 1343 | urb->iso_frame_desc[i].offset); |
1315 | } | 1344 | } |
1316 | 1345 | ||
1317 | /* Set the interrupt-on-completion flag on the last packet. */ | 1346 | /* Set the interrupt-on-completion flag on the last packet. */ |
1318 | td->status |= cpu_to_le32(TD_CTRL_IOC); | 1347 | td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC); |
1319 | 1348 | ||
1320 | /* Add the TDs to the frame list */ | 1349 | /* Add the TDs to the frame list */ |
1321 | frame = urb->start_frame; | 1350 | frame = urb->start_frame; |
@@ -1351,7 +1380,7 @@ static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb) | |||
1351 | 1380 | ||
1352 | uhci_remove_tds_from_frame(uhci, qh->iso_frame); | 1381 | uhci_remove_tds_from_frame(uhci, qh->iso_frame); |
1353 | 1382 | ||
1354 | ctrlstat = td_status(td); | 1383 | ctrlstat = td_status(uhci, td); |
1355 | if (ctrlstat & TD_CTRL_ACTIVE) { | 1384 | if (ctrlstat & TD_CTRL_ACTIVE) { |
1356 | status = -EXDEV; /* TD was added too late? */ | 1385 | status = -EXDEV; /* TD was added too late? */ |
1357 | } else { | 1386 | } else { |
@@ -1602,7 +1631,7 @@ restart: | |||
1602 | * queue, the QH can now be re-activated. */ | 1631 | * queue, the QH can now be re-activated. */ |
1603 | if (!list_empty(&qh->queue)) { | 1632 | if (!list_empty(&qh->queue)) { |
1604 | if (qh->needs_fixup) | 1633 | if (qh->needs_fixup) |
1605 | uhci_fixup_toggles(qh, 0); | 1634 | uhci_fixup_toggles(uhci, qh, 0); |
1606 | 1635 | ||
1607 | /* If the first URB on the queue wants FSBR but its time | 1636 | /* If the first URB on the queue wants FSBR but its time |
1608 | * limit has expired, set the next TD to interrupt on | 1637 | * limit has expired, set the next TD to interrupt on |
@@ -1612,7 +1641,7 @@ restart: | |||
1612 | struct uhci_td *td = list_entry(urbp->td_list.next, | 1641 | struct uhci_td *td = list_entry(urbp->td_list.next, |
1613 | struct uhci_td, list); | 1642 | struct uhci_td, list); |
1614 | 1643 | ||
1615 | td->status |= __cpu_to_le32(TD_CTRL_IOC); | 1644 | td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC); |
1616 | } | 1645 | } |
1617 | 1646 | ||
1618 | uhci_activate_qh(uhci, qh); | 1647 | uhci_activate_qh(uhci, qh); |
@@ -1659,7 +1688,7 @@ static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
1659 | } else { | 1688 | } else { |
1660 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | 1689 | urbp = list_entry(qh->queue.next, struct urb_priv, node); |
1661 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | 1690 | td = list_entry(urbp->td_list.next, struct uhci_td, list); |
1662 | status = td_status(td); | 1691 | status = td_status(uhci, td); |
1663 | if (!(status & TD_CTRL_ACTIVE)) { | 1692 | if (!(status & TD_CTRL_ACTIVE)) { |
1664 | 1693 | ||
1665 | /* We're okay, the queue has advanced */ | 1694 | /* We're okay, the queue has advanced */ |
@@ -1677,7 +1706,8 @@ static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh) | |||
1677 | if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) { | 1706 | if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) { |
1678 | 1707 | ||
1679 | /* Detect the Intel bug and work around it */ | 1708 | /* Detect the Intel bug and work around it */ |
1680 | if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) { | 1709 | if (qh->post_td && qh_element(qh) == |
1710 | LINK_TO_TD(uhci, qh->post_td)) { | ||
1681 | qh->element = qh->post_td->link; | 1711 | qh->element = qh->post_td->link; |
1682 | qh->advance_jiffies = jiffies; | 1712 | qh->advance_jiffies = jiffies; |
1683 | ret = 1; | 1713 | ret = 1; |
diff --git a/drivers/usb/host/whci/Kbuild b/drivers/usb/host/whci/Kbuild index 11e5040b8337..26df0138079e 100644 --- a/drivers/usb/host/whci/Kbuild +++ b/drivers/usb/host/whci/Kbuild | |||
@@ -3,7 +3,7 @@ obj-$(CONFIG_USB_WHCI_HCD) += whci-hcd.o | |||
3 | whci-hcd-y := \ | 3 | whci-hcd-y := \ |
4 | asl.o \ | 4 | asl.o \ |
5 | debug.o \ | 5 | debug.o \ |
6 | hcd.o \ | 6 | hcd.o \ |
7 | hw.o \ | 7 | hw.o \ |
8 | init.o \ | 8 | init.o \ |
9 | int.o \ | 9 | int.o \ |
diff --git a/drivers/usb/host/whci/hcd.c b/drivers/usb/host/whci/hcd.c index 72b6892fda67..9546f6cd01f0 100644 --- a/drivers/usb/host/whci/hcd.c +++ b/drivers/usb/host/whci/hcd.c | |||
@@ -356,7 +356,7 @@ static void __exit whci_hc_driver_exit(void) | |||
356 | module_exit(whci_hc_driver_exit); | 356 | module_exit(whci_hc_driver_exit); |
357 | 357 | ||
358 | /* PCI device ID's that we handle (so it gets loaded) */ | 358 | /* PCI device ID's that we handle (so it gets loaded) */ |
359 | static struct pci_device_id whci_hcd_id_table[] = { | 359 | static struct pci_device_id __used whci_hcd_id_table[] = { |
360 | { PCI_DEVICE_CLASS(PCI_CLASS_WIRELESS_WHCI, ~0) }, | 360 | { PCI_DEVICE_CLASS(PCI_CLASS_WIRELESS_WHCI, ~0) }, |
361 | { /* empty last entry */ } | 361 | { /* empty last entry */ } |
362 | }; | 362 | }; |
diff --git a/drivers/usb/host/whci/qset.c b/drivers/usb/host/whci/qset.c index dc0ab8382f5d..d6e175428618 100644 --- a/drivers/usb/host/whci/qset.c +++ b/drivers/usb/host/whci/qset.c | |||
@@ -739,7 +739,7 @@ static int get_urb_status_from_qtd(struct urb *urb, u32 status) | |||
739 | * process_inactive_qtd - process an inactive (but not halted) qTD. | 739 | * process_inactive_qtd - process an inactive (but not halted) qTD. |
740 | * | 740 | * |
741 | * Update the urb with the transfer bytes from the qTD, if the urb is | 741 | * Update the urb with the transfer bytes from the qTD, if the urb is |
742 | * completely transfered or (in the case of an IN only) the LPF is | 742 | * completely transferred or (in the case of an IN only) the LPF is |
743 | * set, then the transfer is complete and the urb should be returned | 743 | * set, then the transfer is complete and the urb should be returned |
744 | * to the system. | 744 | * to the system. |
745 | */ | 745 | */ |
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c index fcbf4abbf381..1f50b4468e87 100644 --- a/drivers/usb/host/xhci-dbg.c +++ b/drivers/usb/host/xhci-dbg.c | |||
@@ -147,7 +147,7 @@ static void xhci_print_op_regs(struct xhci_hcd *xhci) | |||
147 | 147 | ||
148 | static void xhci_print_ports(struct xhci_hcd *xhci) | 148 | static void xhci_print_ports(struct xhci_hcd *xhci) |
149 | { | 149 | { |
150 | u32 __iomem *addr; | 150 | __le32 __iomem *addr; |
151 | int i, j; | 151 | int i, j; |
152 | int ports; | 152 | int ports; |
153 | char *names[NUM_PORT_REGS] = { | 153 | char *names[NUM_PORT_REGS] = { |
@@ -169,9 +169,10 @@ static void xhci_print_ports(struct xhci_hcd *xhci) | |||
169 | } | 169 | } |
170 | } | 170 | } |
171 | 171 | ||
172 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num) | 172 | void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num) |
173 | { | 173 | { |
174 | void *addr; | 174 | struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num]; |
175 | void __iomem *addr; | ||
175 | u32 temp; | 176 | u32 temp; |
176 | u64 temp_64; | 177 | u64 temp_64; |
177 | 178 | ||
@@ -252,27 +253,27 @@ void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb) | |||
252 | void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) | 253 | void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) |
253 | { | 254 | { |
254 | u64 address; | 255 | u64 address; |
255 | u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK; | 256 | u32 type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK; |
256 | 257 | ||
257 | switch (type) { | 258 | switch (type) { |
258 | case TRB_TYPE(TRB_LINK): | 259 | case TRB_TYPE(TRB_LINK): |
259 | xhci_dbg(xhci, "Link TRB:\n"); | 260 | xhci_dbg(xhci, "Link TRB:\n"); |
260 | xhci_print_trb_offsets(xhci, trb); | 261 | xhci_print_trb_offsets(xhci, trb); |
261 | 262 | ||
262 | address = trb->link.segment_ptr; | 263 | address = le64_to_cpu(trb->link.segment_ptr); |
263 | xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address); | 264 | xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address); |
264 | 265 | ||
265 | xhci_dbg(xhci, "Interrupter target = 0x%x\n", | 266 | xhci_dbg(xhci, "Interrupter target = 0x%x\n", |
266 | GET_INTR_TARGET(trb->link.intr_target)); | 267 | GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target))); |
267 | xhci_dbg(xhci, "Cycle bit = %u\n", | 268 | xhci_dbg(xhci, "Cycle bit = %u\n", |
268 | (unsigned int) (trb->link.control & TRB_CYCLE)); | 269 | (unsigned int) (le32_to_cpu(trb->link.control) & TRB_CYCLE)); |
269 | xhci_dbg(xhci, "Toggle cycle bit = %u\n", | 270 | xhci_dbg(xhci, "Toggle cycle bit = %u\n", |
270 | (unsigned int) (trb->link.control & LINK_TOGGLE)); | 271 | (unsigned int) (le32_to_cpu(trb->link.control) & LINK_TOGGLE)); |
271 | xhci_dbg(xhci, "No Snoop bit = %u\n", | 272 | xhci_dbg(xhci, "No Snoop bit = %u\n", |
272 | (unsigned int) (trb->link.control & TRB_NO_SNOOP)); | 273 | (unsigned int) (le32_to_cpu(trb->link.control) & TRB_NO_SNOOP)); |
273 | break; | 274 | break; |
274 | case TRB_TYPE(TRB_TRANSFER): | 275 | case TRB_TYPE(TRB_TRANSFER): |
275 | address = trb->trans_event.buffer; | 276 | address = le64_to_cpu(trb->trans_event.buffer); |
276 | /* | 277 | /* |
277 | * FIXME: look at flags to figure out if it's an address or if | 278 | * FIXME: look at flags to figure out if it's an address or if |
278 | * the data is directly in the buffer field. | 279 | * the data is directly in the buffer field. |
@@ -280,11 +281,12 @@ void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) | |||
280 | xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address); | 281 | xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address); |
281 | break; | 282 | break; |
282 | case TRB_TYPE(TRB_COMPLETION): | 283 | case TRB_TYPE(TRB_COMPLETION): |
283 | address = trb->event_cmd.cmd_trb; | 284 | address = le64_to_cpu(trb->event_cmd.cmd_trb); |
284 | xhci_dbg(xhci, "Command TRB pointer = %llu\n", address); | 285 | xhci_dbg(xhci, "Command TRB pointer = %llu\n", address); |
285 | xhci_dbg(xhci, "Completion status = %u\n", | 286 | xhci_dbg(xhci, "Completion status = %u\n", |
286 | (unsigned int) GET_COMP_CODE(trb->event_cmd.status)); | 287 | (unsigned int) GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status))); |
287 | xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags); | 288 | xhci_dbg(xhci, "Flags = 0x%x\n", |
289 | (unsigned int) le32_to_cpu(trb->event_cmd.flags)); | ||
288 | break; | 290 | break; |
289 | default: | 291 | default: |
290 | xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n", | 292 | xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n", |
@@ -310,16 +312,16 @@ void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) | |||
310 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg) | 312 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg) |
311 | { | 313 | { |
312 | int i; | 314 | int i; |
313 | u32 addr = (u32) seg->dma; | 315 | u64 addr = seg->dma; |
314 | union xhci_trb *trb = seg->trbs; | 316 | union xhci_trb *trb = seg->trbs; |
315 | 317 | ||
316 | for (i = 0; i < TRBS_PER_SEGMENT; ++i) { | 318 | for (i = 0; i < TRBS_PER_SEGMENT; ++i) { |
317 | trb = &seg->trbs[i]; | 319 | trb = &seg->trbs[i]; |
318 | xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr, | 320 | xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr, |
319 | lower_32_bits(trb->link.segment_ptr), | 321 | (u32)lower_32_bits(le64_to_cpu(trb->link.segment_ptr)), |
320 | upper_32_bits(trb->link.segment_ptr), | 322 | (u32)upper_32_bits(le64_to_cpu(trb->link.segment_ptr)), |
321 | (unsigned int) trb->link.intr_target, | 323 | (unsigned int) le32_to_cpu(trb->link.intr_target), |
322 | (unsigned int) trb->link.control); | 324 | (unsigned int) le32_to_cpu(trb->link.control)); |
323 | addr += sizeof(*trb); | 325 | addr += sizeof(*trb); |
324 | } | 326 | } |
325 | } | 327 | } |
@@ -390,18 +392,18 @@ void xhci_dbg_ep_rings(struct xhci_hcd *xhci, | |||
390 | 392 | ||
391 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) | 393 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) |
392 | { | 394 | { |
393 | u32 addr = (u32) erst->erst_dma_addr; | 395 | u64 addr = erst->erst_dma_addr; |
394 | int i; | 396 | int i; |
395 | struct xhci_erst_entry *entry; | 397 | struct xhci_erst_entry *entry; |
396 | 398 | ||
397 | for (i = 0; i < erst->num_entries; ++i) { | 399 | for (i = 0; i < erst->num_entries; ++i) { |
398 | entry = &erst->entries[i]; | 400 | entry = &erst->entries[i]; |
399 | xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", | 401 | xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", |
400 | (unsigned int) addr, | 402 | addr, |
401 | lower_32_bits(entry->seg_addr), | 403 | lower_32_bits(le64_to_cpu(entry->seg_addr)), |
402 | upper_32_bits(entry->seg_addr), | 404 | upper_32_bits(le64_to_cpu(entry->seg_addr)), |
403 | (unsigned int) entry->seg_size, | 405 | (unsigned int) le32_to_cpu(entry->seg_size), |
404 | (unsigned int) entry->rsvd); | 406 | (unsigned int) le32_to_cpu(entry->rsvd)); |
405 | addr += sizeof(*entry); | 407 | addr += sizeof(*entry); |
406 | } | 408 | } |
407 | } | 409 | } |
@@ -435,21 +437,21 @@ char *xhci_get_slot_state(struct xhci_hcd *xhci, | |||
435 | { | 437 | { |
436 | struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); | 438 | struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); |
437 | 439 | ||
438 | switch (GET_SLOT_STATE(slot_ctx->dev_state)) { | 440 | switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) { |
439 | case 0: | 441 | case SLOT_STATE_ENABLED: |
440 | return "enabled/disabled"; | 442 | return "enabled/disabled"; |
441 | case 1: | 443 | case SLOT_STATE_DEFAULT: |
442 | return "default"; | 444 | return "default"; |
443 | case 2: | 445 | case SLOT_STATE_ADDRESSED: |
444 | return "addressed"; | 446 | return "addressed"; |
445 | case 3: | 447 | case SLOT_STATE_CONFIGURED: |
446 | return "configured"; | 448 | return "configured"; |
447 | default: | 449 | default: |
448 | return "reserved"; | 450 | return "reserved"; |
449 | } | 451 | } |
450 | } | 452 | } |
451 | 453 | ||
452 | void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) | 454 | static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) |
453 | { | 455 | { |
454 | /* Fields are 32 bits wide, DMA addresses are in bytes */ | 456 | /* Fields are 32 bits wide, DMA addresses are in bytes */ |
455 | int field_size = 32 / 8; | 457 | int field_size = 32 / 8; |
@@ -488,7 +490,7 @@ void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) | |||
488 | dbg_rsvd64(xhci, (u64 *)slot_ctx, dma); | 490 | dbg_rsvd64(xhci, (u64 *)slot_ctx, dma); |
489 | } | 491 | } |
490 | 492 | ||
491 | void xhci_dbg_ep_ctx(struct xhci_hcd *xhci, | 493 | static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci, |
492 | struct xhci_container_ctx *ctx, | 494 | struct xhci_container_ctx *ctx, |
493 | unsigned int last_ep) | 495 | unsigned int last_ep) |
494 | { | 496 | { |
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h index 78c4edac1db1..ce5c9e51748e 100644 --- a/drivers/usb/host/xhci-ext-caps.h +++ b/drivers/usb/host/xhci-ext-caps.h | |||
@@ -19,8 +19,8 @@ | |||
19 | * along with this program; if not, write to the Free Software Foundation, | 19 | * along with this program; if not, write to the Free Software Foundation, |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
21 | */ | 21 | */ |
22 | /* Up to 16 microframes to halt an HC - one microframe is 125 microsectonds */ | 22 | /* Up to 16 ms to halt an HC */ |
23 | #define XHCI_MAX_HALT_USEC (16*125) | 23 | #define XHCI_MAX_HALT_USEC (16*1000) |
24 | /* HC not running - set to 1 when run/stop bit is cleared. */ | 24 | /* HC not running - set to 1 when run/stop bit is cleared. */ |
25 | #define XHCI_STS_HALT (1<<0) | 25 | #define XHCI_STS_HALT (1<<0) |
26 | 26 | ||
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index a1a7a9795536..0be788cc2fdb 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c | |||
@@ -24,27 +24,19 @@ | |||
24 | 24 | ||
25 | #include "xhci.h" | 25 | #include "xhci.h" |
26 | 26 | ||
27 | static void xhci_hub_descriptor(struct xhci_hcd *xhci, | 27 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
28 | struct usb_hub_descriptor *desc) | 28 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ |
29 | PORT_RC | PORT_PLC | PORT_PE) | ||
30 | |||
31 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, | ||
32 | struct usb_hub_descriptor *desc, int ports) | ||
29 | { | 33 | { |
30 | int ports; | ||
31 | u16 temp; | 34 | u16 temp; |
32 | 35 | ||
33 | ports = HCS_MAX_PORTS(xhci->hcs_params1); | ||
34 | |||
35 | /* USB 3.0 hubs have a different descriptor, but we fake this for now */ | ||
36 | desc->bDescriptorType = 0x29; | ||
37 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ | 36 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
38 | desc->bHubContrCurrent = 0; | 37 | desc->bHubContrCurrent = 0; |
39 | 38 | ||
40 | desc->bNbrPorts = ports; | 39 | desc->bNbrPorts = ports; |
41 | temp = 1 + (ports / 8); | ||
42 | desc->bDescLength = 7 + 2 * temp; | ||
43 | |||
44 | /* Why does core/hcd.h define bitmap? It's just confusing. */ | ||
45 | memset(&desc->DeviceRemovable[0], 0, temp); | ||
46 | memset(&desc->DeviceRemovable[temp], 0xff, temp); | ||
47 | |||
48 | /* Ugh, these should be #defines, FIXME */ | 40 | /* Ugh, these should be #defines, FIXME */ |
49 | /* Using table 11-13 in USB 2.0 spec. */ | 41 | /* Using table 11-13 in USB 2.0 spec. */ |
50 | temp = 0; | 42 | temp = 0; |
@@ -58,7 +50,103 @@ static void xhci_hub_descriptor(struct xhci_hcd *xhci, | |||
58 | temp |= 0x0008; | 50 | temp |= 0x0008; |
59 | /* Bits 6:5 - no TTs in root ports */ | 51 | /* Bits 6:5 - no TTs in root ports */ |
60 | /* Bit 7 - no port indicators */ | 52 | /* Bit 7 - no port indicators */ |
61 | desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp); | 53 | desc->wHubCharacteristics = cpu_to_le16(temp); |
54 | } | ||
55 | |||
56 | /* Fill in the USB 2.0 roothub descriptor */ | ||
57 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | ||
58 | struct usb_hub_descriptor *desc) | ||
59 | { | ||
60 | int ports; | ||
61 | u16 temp; | ||
62 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | ||
63 | u32 portsc; | ||
64 | unsigned int i; | ||
65 | |||
66 | ports = xhci->num_usb2_ports; | ||
67 | |||
68 | xhci_common_hub_descriptor(xhci, desc, ports); | ||
69 | desc->bDescriptorType = 0x29; | ||
70 | temp = 1 + (ports / 8); | ||
71 | desc->bDescLength = 7 + 2 * temp; | ||
72 | |||
73 | /* The Device Removable bits are reported on a byte granularity. | ||
74 | * If the port doesn't exist within that byte, the bit is set to 0. | ||
75 | */ | ||
76 | memset(port_removable, 0, sizeof(port_removable)); | ||
77 | for (i = 0; i < ports; i++) { | ||
78 | portsc = xhci_readl(xhci, xhci->usb3_ports[i]); | ||
79 | /* If a device is removable, PORTSC reports a 0, same as in the | ||
80 | * hub descriptor DeviceRemovable bits. | ||
81 | */ | ||
82 | if (portsc & PORT_DEV_REMOVE) | ||
83 | /* This math is hairy because bit 0 of DeviceRemovable | ||
84 | * is reserved, and bit 1 is for port 1, etc. | ||
85 | */ | ||
86 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | ||
87 | } | ||
88 | |||
89 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | ||
90 | * ports on it. The USB 2.0 specification says that there are two | ||
91 | * variable length fields at the end of the hub descriptor: | ||
92 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | ||
93 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | ||
94 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | ||
95 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | ||
96 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | ||
97 | * set of ports that actually exist. | ||
98 | */ | ||
99 | memset(desc->u.hs.DeviceRemovable, 0xff, | ||
100 | sizeof(desc->u.hs.DeviceRemovable)); | ||
101 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | ||
102 | sizeof(desc->u.hs.PortPwrCtrlMask)); | ||
103 | |||
104 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | ||
105 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | ||
106 | sizeof(__u8)); | ||
107 | } | ||
108 | |||
109 | /* Fill in the USB 3.0 roothub descriptor */ | ||
110 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | ||
111 | struct usb_hub_descriptor *desc) | ||
112 | { | ||
113 | int ports; | ||
114 | u16 port_removable; | ||
115 | u32 portsc; | ||
116 | unsigned int i; | ||
117 | |||
118 | ports = xhci->num_usb3_ports; | ||
119 | xhci_common_hub_descriptor(xhci, desc, ports); | ||
120 | desc->bDescriptorType = 0x2a; | ||
121 | desc->bDescLength = 12; | ||
122 | |||
123 | /* header decode latency should be zero for roothubs, | ||
124 | * see section 4.23.5.2. | ||
125 | */ | ||
126 | desc->u.ss.bHubHdrDecLat = 0; | ||
127 | desc->u.ss.wHubDelay = 0; | ||
128 | |||
129 | port_removable = 0; | ||
130 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | ||
131 | for (i = 0; i < ports; i++) { | ||
132 | portsc = xhci_readl(xhci, xhci->usb3_ports[i]); | ||
133 | if (portsc & PORT_DEV_REMOVE) | ||
134 | port_removable |= 1 << (i + 1); | ||
135 | } | ||
136 | memset(&desc->u.ss.DeviceRemovable, | ||
137 | (__force __u16) cpu_to_le16(port_removable), | ||
138 | sizeof(__u16)); | ||
139 | } | ||
140 | |||
141 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | ||
142 | struct usb_hub_descriptor *desc) | ||
143 | { | ||
144 | |||
145 | if (hcd->speed == HCD_USB3) | ||
146 | xhci_usb3_hub_descriptor(hcd, xhci, desc); | ||
147 | else | ||
148 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | ||
149 | |||
62 | } | 150 | } |
63 | 151 | ||
64 | static unsigned int xhci_port_speed(unsigned int port_status) | 152 | static unsigned int xhci_port_speed(unsigned int port_status) |
@@ -67,8 +155,6 @@ static unsigned int xhci_port_speed(unsigned int port_status) | |||
67 | return USB_PORT_STAT_LOW_SPEED; | 155 | return USB_PORT_STAT_LOW_SPEED; |
68 | if (DEV_HIGHSPEED(port_status)) | 156 | if (DEV_HIGHSPEED(port_status)) |
69 | return USB_PORT_STAT_HIGH_SPEED; | 157 | return USB_PORT_STAT_HIGH_SPEED; |
70 | if (DEV_SUPERSPEED(port_status)) | ||
71 | return USB_PORT_STAT_SUPER_SPEED; | ||
72 | /* | 158 | /* |
73 | * FIXME: Yes, we should check for full speed, but the core uses that as | 159 | * FIXME: Yes, we should check for full speed, but the core uses that as |
74 | * a default in portspeed() in usb/core/hub.c (which is the only place | 160 | * a default in portspeed() in usb/core/hub.c (which is the only place |
@@ -123,15 +209,120 @@ static unsigned int xhci_port_speed(unsigned int port_status) | |||
123 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | 209 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). |
124 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | 210 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. |
125 | */ | 211 | */ |
126 | static u32 xhci_port_state_to_neutral(u32 state) | 212 | u32 xhci_port_state_to_neutral(u32 state) |
127 | { | 213 | { |
128 | /* Save read-only status and port state */ | 214 | /* Save read-only status and port state */ |
129 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | 215 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); |
130 | } | 216 | } |
131 | 217 | ||
132 | static void xhci_disable_port(struct xhci_hcd *xhci, u16 wIndex, | 218 | /* |
133 | u32 __iomem *addr, u32 port_status) | 219 | * find slot id based on port number. |
220 | * @port: The one-based port number from one of the two split roothubs. | ||
221 | */ | ||
222 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, | ||
223 | u16 port) | ||
224 | { | ||
225 | int slot_id; | ||
226 | int i; | ||
227 | enum usb_device_speed speed; | ||
228 | |||
229 | slot_id = 0; | ||
230 | for (i = 0; i < MAX_HC_SLOTS; i++) { | ||
231 | if (!xhci->devs[i]) | ||
232 | continue; | ||
233 | speed = xhci->devs[i]->udev->speed; | ||
234 | if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) | ||
235 | && xhci->devs[i]->port == port) { | ||
236 | slot_id = i; | ||
237 | break; | ||
238 | } | ||
239 | } | ||
240 | |||
241 | return slot_id; | ||
242 | } | ||
243 | |||
244 | /* | ||
245 | * Stop device | ||
246 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | ||
247 | * to complete. | ||
248 | * suspend will set to 1, if suspend bit need to set in command. | ||
249 | */ | ||
250 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | ||
251 | { | ||
252 | struct xhci_virt_device *virt_dev; | ||
253 | struct xhci_command *cmd; | ||
254 | unsigned long flags; | ||
255 | int timeleft; | ||
256 | int ret; | ||
257 | int i; | ||
258 | |||
259 | ret = 0; | ||
260 | virt_dev = xhci->devs[slot_id]; | ||
261 | cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | ||
262 | if (!cmd) { | ||
263 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | ||
264 | return -ENOMEM; | ||
265 | } | ||
266 | |||
267 | spin_lock_irqsave(&xhci->lock, flags); | ||
268 | for (i = LAST_EP_INDEX; i > 0; i--) { | ||
269 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) | ||
270 | xhci_queue_stop_endpoint(xhci, slot_id, i, suspend); | ||
271 | } | ||
272 | cmd->command_trb = xhci->cmd_ring->enqueue; | ||
273 | list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list); | ||
274 | xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend); | ||
275 | xhci_ring_cmd_db(xhci); | ||
276 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
277 | |||
278 | /* Wait for last stop endpoint command to finish */ | ||
279 | timeleft = wait_for_completion_interruptible_timeout( | ||
280 | cmd->completion, | ||
281 | USB_CTRL_SET_TIMEOUT); | ||
282 | if (timeleft <= 0) { | ||
283 | xhci_warn(xhci, "%s while waiting for stop endpoint command\n", | ||
284 | timeleft == 0 ? "Timeout" : "Signal"); | ||
285 | spin_lock_irqsave(&xhci->lock, flags); | ||
286 | /* The timeout might have raced with the event ring handler, so | ||
287 | * only delete from the list if the item isn't poisoned. | ||
288 | */ | ||
289 | if (cmd->cmd_list.next != LIST_POISON1) | ||
290 | list_del(&cmd->cmd_list); | ||
291 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
292 | ret = -ETIME; | ||
293 | goto command_cleanup; | ||
294 | } | ||
295 | |||
296 | command_cleanup: | ||
297 | xhci_free_command(xhci, cmd); | ||
298 | return ret; | ||
299 | } | ||
300 | |||
301 | /* | ||
302 | * Ring device, it rings the all doorbells unconditionally. | ||
303 | */ | ||
304 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) | ||
305 | { | ||
306 | int i; | ||
307 | |||
308 | for (i = 0; i < LAST_EP_INDEX + 1; i++) | ||
309 | if (xhci->devs[slot_id]->eps[i].ring && | ||
310 | xhci->devs[slot_id]->eps[i].ring->dequeue) | ||
311 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); | ||
312 | |||
313 | return; | ||
314 | } | ||
315 | |||
316 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, | ||
317 | u16 wIndex, __le32 __iomem *addr, u32 port_status) | ||
134 | { | 318 | { |
319 | /* Don't allow the USB core to disable SuperSpeed ports. */ | ||
320 | if (hcd->speed == HCD_USB3) { | ||
321 | xhci_dbg(xhci, "Ignoring request to disable " | ||
322 | "SuperSpeed port.\n"); | ||
323 | return; | ||
324 | } | ||
325 | |||
135 | /* Write 1 to disable the port */ | 326 | /* Write 1 to disable the port */ |
136 | xhci_writel(xhci, port_status | PORT_PE, addr); | 327 | xhci_writel(xhci, port_status | PORT_PE, addr); |
137 | port_status = xhci_readl(xhci, addr); | 328 | port_status = xhci_readl(xhci, addr); |
@@ -140,7 +331,7 @@ static void xhci_disable_port(struct xhci_hcd *xhci, u16 wIndex, | |||
140 | } | 331 | } |
141 | 332 | ||
142 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, | 333 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
143 | u16 wIndex, u32 __iomem *addr, u32 port_status) | 334 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
144 | { | 335 | { |
145 | char *port_change_bit; | 336 | char *port_change_bit; |
146 | u32 status; | 337 | u32 status; |
@@ -150,6 +341,10 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, | |||
150 | status = PORT_RC; | 341 | status = PORT_RC; |
151 | port_change_bit = "reset"; | 342 | port_change_bit = "reset"; |
152 | break; | 343 | break; |
344 | case USB_PORT_FEAT_C_BH_PORT_RESET: | ||
345 | status = PORT_WRC; | ||
346 | port_change_bit = "warm(BH) reset"; | ||
347 | break; | ||
153 | case USB_PORT_FEAT_C_CONNECTION: | 348 | case USB_PORT_FEAT_C_CONNECTION: |
154 | status = PORT_CSC; | 349 | status = PORT_CSC; |
155 | port_change_bit = "connect"; | 350 | port_change_bit = "connect"; |
@@ -162,6 +357,14 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, | |||
162 | status = PORT_PEC; | 357 | status = PORT_PEC; |
163 | port_change_bit = "enable/disable"; | 358 | port_change_bit = "enable/disable"; |
164 | break; | 359 | break; |
360 | case USB_PORT_FEAT_C_SUSPEND: | ||
361 | status = PORT_PLC; | ||
362 | port_change_bit = "suspend/resume"; | ||
363 | break; | ||
364 | case USB_PORT_FEAT_C_PORT_LINK_STATE: | ||
365 | status = PORT_PLC; | ||
366 | port_change_bit = "link state"; | ||
367 | break; | ||
165 | default: | 368 | default: |
166 | /* Should never happen */ | 369 | /* Should never happen */ |
167 | return; | 370 | return; |
@@ -173,17 +376,37 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, | |||
173 | port_change_bit, wIndex, port_status); | 376 | port_change_bit, wIndex, port_status); |
174 | } | 377 | } |
175 | 378 | ||
379 | static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) | ||
380 | { | ||
381 | int max_ports; | ||
382 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | ||
383 | |||
384 | if (hcd->speed == HCD_USB3) { | ||
385 | max_ports = xhci->num_usb3_ports; | ||
386 | *port_array = xhci->usb3_ports; | ||
387 | } else { | ||
388 | max_ports = xhci->num_usb2_ports; | ||
389 | *port_array = xhci->usb2_ports; | ||
390 | } | ||
391 | |||
392 | return max_ports; | ||
393 | } | ||
394 | |||
176 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | 395 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
177 | u16 wIndex, char *buf, u16 wLength) | 396 | u16 wIndex, char *buf, u16 wLength) |
178 | { | 397 | { |
179 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | 398 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
180 | int ports; | 399 | int max_ports; |
181 | unsigned long flags; | 400 | unsigned long flags; |
182 | u32 temp, status; | 401 | u32 temp, temp1, status; |
183 | int retval = 0; | 402 | int retval = 0; |
184 | u32 __iomem *addr; | 403 | __le32 __iomem **port_array; |
404 | int slot_id; | ||
405 | struct xhci_bus_state *bus_state; | ||
406 | u16 link_state = 0; | ||
185 | 407 | ||
186 | ports = HCS_MAX_PORTS(xhci->hcs_params1); | 408 | max_ports = xhci_get_ports(hcd, &port_array); |
409 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | ||
187 | 410 | ||
188 | spin_lock_irqsave(&xhci->lock, flags); | 411 | spin_lock_irqsave(&xhci->lock, flags); |
189 | switch (typeReq) { | 412 | switch (typeReq) { |
@@ -192,15 +415,30 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
192 | memset(buf, 0, 4); | 415 | memset(buf, 0, 4); |
193 | break; | 416 | break; |
194 | case GetHubDescriptor: | 417 | case GetHubDescriptor: |
195 | xhci_hub_descriptor(xhci, (struct usb_hub_descriptor *) buf); | 418 | /* Check to make sure userspace is asking for the USB 3.0 hub |
419 | * descriptor for the USB 3.0 roothub. If not, we stall the | ||
420 | * endpoint, like external hubs do. | ||
421 | */ | ||
422 | if (hcd->speed == HCD_USB3 && | ||
423 | (wLength < USB_DT_SS_HUB_SIZE || | ||
424 | wValue != (USB_DT_SS_HUB << 8))) { | ||
425 | xhci_dbg(xhci, "Wrong hub descriptor type for " | ||
426 | "USB 3.0 roothub.\n"); | ||
427 | goto error; | ||
428 | } | ||
429 | xhci_hub_descriptor(hcd, xhci, | ||
430 | (struct usb_hub_descriptor *) buf); | ||
196 | break; | 431 | break; |
197 | case GetPortStatus: | 432 | case GetPortStatus: |
198 | if (!wIndex || wIndex > ports) | 433 | if (!wIndex || wIndex > max_ports) |
199 | goto error; | 434 | goto error; |
200 | wIndex--; | 435 | wIndex--; |
201 | status = 0; | 436 | status = 0; |
202 | addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff); | 437 | temp = xhci_readl(xhci, port_array[wIndex]); |
203 | temp = xhci_readl(xhci, addr); | 438 | if (temp == 0xffffffff) { |
439 | retval = -ENODEV; | ||
440 | break; | ||
441 | } | ||
204 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); | 442 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); |
205 | 443 | ||
206 | /* wPortChange bits */ | 444 | /* wPortChange bits */ |
@@ -210,10 +448,54 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
210 | status |= USB_PORT_STAT_C_ENABLE << 16; | 448 | status |= USB_PORT_STAT_C_ENABLE << 16; |
211 | if ((temp & PORT_OCC)) | 449 | if ((temp & PORT_OCC)) |
212 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | 450 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; |
213 | /* | 451 | if ((temp & PORT_RC)) |
214 | * FIXME ignoring suspend, reset, and USB 2.1/3.0 specific | 452 | status |= USB_PORT_STAT_C_RESET << 16; |
215 | * changes | 453 | /* USB3.0 only */ |
216 | */ | 454 | if (hcd->speed == HCD_USB3) { |
455 | if ((temp & PORT_PLC)) | ||
456 | status |= USB_PORT_STAT_C_LINK_STATE << 16; | ||
457 | if ((temp & PORT_WRC)) | ||
458 | status |= USB_PORT_STAT_C_BH_RESET << 16; | ||
459 | } | ||
460 | |||
461 | if (hcd->speed != HCD_USB3) { | ||
462 | if ((temp & PORT_PLS_MASK) == XDEV_U3 | ||
463 | && (temp & PORT_POWER)) | ||
464 | status |= USB_PORT_STAT_SUSPEND; | ||
465 | } | ||
466 | if ((temp & PORT_PLS_MASK) == XDEV_RESUME) { | ||
467 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) | ||
468 | goto error; | ||
469 | if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies, | ||
470 | bus_state->resume_done[wIndex])) { | ||
471 | xhci_dbg(xhci, "Resume USB2 port %d\n", | ||
472 | wIndex + 1); | ||
473 | bus_state->resume_done[wIndex] = 0; | ||
474 | temp1 = xhci_port_state_to_neutral(temp); | ||
475 | temp1 &= ~PORT_PLS_MASK; | ||
476 | temp1 |= PORT_LINK_STROBE | XDEV_U0; | ||
477 | xhci_writel(xhci, temp1, port_array[wIndex]); | ||
478 | |||
479 | xhci_dbg(xhci, "set port %d resume\n", | ||
480 | wIndex + 1); | ||
481 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | ||
482 | wIndex + 1); | ||
483 | if (!slot_id) { | ||
484 | xhci_dbg(xhci, "slot_id is zero\n"); | ||
485 | goto error; | ||
486 | } | ||
487 | xhci_ring_device(xhci, slot_id); | ||
488 | bus_state->port_c_suspend |= 1 << wIndex; | ||
489 | bus_state->suspended_ports &= ~(1 << wIndex); | ||
490 | } | ||
491 | } | ||
492 | if ((temp & PORT_PLS_MASK) == XDEV_U0 | ||
493 | && (temp & PORT_POWER) | ||
494 | && (bus_state->suspended_ports & (1 << wIndex))) { | ||
495 | bus_state->suspended_ports &= ~(1 << wIndex); | ||
496 | if (hcd->speed != HCD_USB3) | ||
497 | bus_state->port_c_suspend |= 1 << wIndex; | ||
498 | } | ||
217 | if (temp & PORT_CONNECT) { | 499 | if (temp & PORT_CONNECT) { |
218 | status |= USB_PORT_STAT_CONNECTION; | 500 | status |= USB_PORT_STAT_CONNECTION; |
219 | status |= xhci_port_speed(temp); | 501 | status |= xhci_port_speed(temp); |
@@ -224,20 +506,114 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
224 | status |= USB_PORT_STAT_OVERCURRENT; | 506 | status |= USB_PORT_STAT_OVERCURRENT; |
225 | if (temp & PORT_RESET) | 507 | if (temp & PORT_RESET) |
226 | status |= USB_PORT_STAT_RESET; | 508 | status |= USB_PORT_STAT_RESET; |
227 | if (temp & PORT_POWER) | 509 | if (temp & PORT_POWER) { |
228 | status |= USB_PORT_STAT_POWER; | 510 | if (hcd->speed == HCD_USB3) |
511 | status |= USB_SS_PORT_STAT_POWER; | ||
512 | else | ||
513 | status |= USB_PORT_STAT_POWER; | ||
514 | } | ||
515 | /* Port Link State */ | ||
516 | if (hcd->speed == HCD_USB3) { | ||
517 | /* resume state is a xHCI internal state. | ||
518 | * Do not report it to usb core. | ||
519 | */ | ||
520 | if ((temp & PORT_PLS_MASK) != XDEV_RESUME) | ||
521 | status |= (temp & PORT_PLS_MASK); | ||
522 | } | ||
523 | if (bus_state->port_c_suspend & (1 << wIndex)) | ||
524 | status |= 1 << USB_PORT_FEAT_C_SUSPEND; | ||
229 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); | 525 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); |
230 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | 526 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
231 | break; | 527 | break; |
232 | case SetPortFeature: | 528 | case SetPortFeature: |
529 | if (wValue == USB_PORT_FEAT_LINK_STATE) | ||
530 | link_state = (wIndex & 0xff00) >> 3; | ||
233 | wIndex &= 0xff; | 531 | wIndex &= 0xff; |
234 | if (!wIndex || wIndex > ports) | 532 | if (!wIndex || wIndex > max_ports) |
235 | goto error; | 533 | goto error; |
236 | wIndex--; | 534 | wIndex--; |
237 | addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff); | 535 | temp = xhci_readl(xhci, port_array[wIndex]); |
238 | temp = xhci_readl(xhci, addr); | 536 | if (temp == 0xffffffff) { |
537 | retval = -ENODEV; | ||
538 | break; | ||
539 | } | ||
239 | temp = xhci_port_state_to_neutral(temp); | 540 | temp = xhci_port_state_to_neutral(temp); |
541 | /* FIXME: What new port features do we need to support? */ | ||
240 | switch (wValue) { | 542 | switch (wValue) { |
543 | case USB_PORT_FEAT_SUSPEND: | ||
544 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
545 | /* In spec software should not attempt to suspend | ||
546 | * a port unless the port reports that it is in the | ||
547 | * enabled (PED = ‘1’,PLS < ‘3’) state. | ||
548 | */ | ||
549 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) | ||
550 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | ||
551 | xhci_warn(xhci, "USB core suspending device " | ||
552 | "not in U0/U1/U2.\n"); | ||
553 | goto error; | ||
554 | } | ||
555 | |||
556 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | ||
557 | wIndex + 1); | ||
558 | if (!slot_id) { | ||
559 | xhci_warn(xhci, "slot_id is zero\n"); | ||
560 | goto error; | ||
561 | } | ||
562 | /* unlock to execute stop endpoint commands */ | ||
563 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
564 | xhci_stop_device(xhci, slot_id, 1); | ||
565 | spin_lock_irqsave(&xhci->lock, flags); | ||
566 | |||
567 | temp = xhci_port_state_to_neutral(temp); | ||
568 | temp &= ~PORT_PLS_MASK; | ||
569 | temp |= PORT_LINK_STROBE | XDEV_U3; | ||
570 | xhci_writel(xhci, temp, port_array[wIndex]); | ||
571 | |||
572 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
573 | msleep(10); /* wait device to enter */ | ||
574 | spin_lock_irqsave(&xhci->lock, flags); | ||
575 | |||
576 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
577 | bus_state->suspended_ports |= 1 << wIndex; | ||
578 | break; | ||
579 | case USB_PORT_FEAT_LINK_STATE: | ||
580 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
581 | /* Software should not attempt to set | ||
582 | * port link state above '5' (Rx.Detect) and the port | ||
583 | * must be enabled. | ||
584 | */ | ||
585 | if ((temp & PORT_PE) == 0 || | ||
586 | (link_state > USB_SS_PORT_LS_RX_DETECT)) { | ||
587 | xhci_warn(xhci, "Cannot set link state.\n"); | ||
588 | goto error; | ||
589 | } | ||
590 | |||
591 | if (link_state == USB_SS_PORT_LS_U3) { | ||
592 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | ||
593 | wIndex + 1); | ||
594 | if (slot_id) { | ||
595 | /* unlock to execute stop endpoint | ||
596 | * commands */ | ||
597 | spin_unlock_irqrestore(&xhci->lock, | ||
598 | flags); | ||
599 | xhci_stop_device(xhci, slot_id, 1); | ||
600 | spin_lock_irqsave(&xhci->lock, flags); | ||
601 | } | ||
602 | } | ||
603 | |||
604 | temp = xhci_port_state_to_neutral(temp); | ||
605 | temp &= ~PORT_PLS_MASK; | ||
606 | temp |= PORT_LINK_STROBE | link_state; | ||
607 | xhci_writel(xhci, temp, port_array[wIndex]); | ||
608 | |||
609 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
610 | msleep(20); /* wait device to enter */ | ||
611 | spin_lock_irqsave(&xhci->lock, flags); | ||
612 | |||
613 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
614 | if (link_state == USB_SS_PORT_LS_U3) | ||
615 | bus_state->suspended_ports |= 1 << wIndex; | ||
616 | break; | ||
241 | case USB_PORT_FEAT_POWER: | 617 | case USB_PORT_FEAT_POWER: |
242 | /* | 618 | /* |
243 | * Turn on ports, even if there isn't per-port switching. | 619 | * Turn on ports, even if there isn't per-port switching. |
@@ -245,41 +621,96 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
245 | * However, khubd will ignore the roothub events until | 621 | * However, khubd will ignore the roothub events until |
246 | * the roothub is registered. | 622 | * the roothub is registered. |
247 | */ | 623 | */ |
248 | xhci_writel(xhci, temp | PORT_POWER, addr); | 624 | xhci_writel(xhci, temp | PORT_POWER, |
625 | port_array[wIndex]); | ||
249 | 626 | ||
250 | temp = xhci_readl(xhci, addr); | 627 | temp = xhci_readl(xhci, port_array[wIndex]); |
251 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); | 628 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); |
252 | break; | 629 | break; |
253 | case USB_PORT_FEAT_RESET: | 630 | case USB_PORT_FEAT_RESET: |
254 | temp = (temp | PORT_RESET); | 631 | temp = (temp | PORT_RESET); |
255 | xhci_writel(xhci, temp, addr); | 632 | xhci_writel(xhci, temp, port_array[wIndex]); |
256 | 633 | ||
257 | temp = xhci_readl(xhci, addr); | 634 | temp = xhci_readl(xhci, port_array[wIndex]); |
258 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); | 635 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
259 | break; | 636 | break; |
637 | case USB_PORT_FEAT_BH_PORT_RESET: | ||
638 | temp |= PORT_WR; | ||
639 | xhci_writel(xhci, temp, port_array[wIndex]); | ||
640 | |||
641 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
642 | break; | ||
260 | default: | 643 | default: |
261 | goto error; | 644 | goto error; |
262 | } | 645 | } |
263 | temp = xhci_readl(xhci, addr); /* unblock any posted writes */ | 646 | /* unblock any posted writes */ |
647 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
264 | break; | 648 | break; |
265 | case ClearPortFeature: | 649 | case ClearPortFeature: |
266 | if (!wIndex || wIndex > ports) | 650 | if (!wIndex || wIndex > max_ports) |
267 | goto error; | 651 | goto error; |
268 | wIndex--; | 652 | wIndex--; |
269 | addr = &xhci->op_regs->port_status_base + | 653 | temp = xhci_readl(xhci, port_array[wIndex]); |
270 | NUM_PORT_REGS*(wIndex & 0xff); | 654 | if (temp == 0xffffffff) { |
271 | temp = xhci_readl(xhci, addr); | 655 | retval = -ENODEV; |
656 | break; | ||
657 | } | ||
658 | /* FIXME: What new port features do we need to support? */ | ||
272 | temp = xhci_port_state_to_neutral(temp); | 659 | temp = xhci_port_state_to_neutral(temp); |
273 | switch (wValue) { | 660 | switch (wValue) { |
661 | case USB_PORT_FEAT_SUSPEND: | ||
662 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
663 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); | ||
664 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | ||
665 | if (temp & PORT_RESET) | ||
666 | goto error; | ||
667 | if (temp & XDEV_U3) { | ||
668 | if ((temp & PORT_PE) == 0) | ||
669 | goto error; | ||
670 | |||
671 | temp = xhci_port_state_to_neutral(temp); | ||
672 | temp &= ~PORT_PLS_MASK; | ||
673 | temp |= PORT_LINK_STROBE | XDEV_RESUME; | ||
674 | xhci_writel(xhci, temp, | ||
675 | port_array[wIndex]); | ||
676 | |||
677 | spin_unlock_irqrestore(&xhci->lock, | ||
678 | flags); | ||
679 | msleep(20); | ||
680 | spin_lock_irqsave(&xhci->lock, flags); | ||
681 | |||
682 | temp = xhci_readl(xhci, | ||
683 | port_array[wIndex]); | ||
684 | temp = xhci_port_state_to_neutral(temp); | ||
685 | temp &= ~PORT_PLS_MASK; | ||
686 | temp |= PORT_LINK_STROBE | XDEV_U0; | ||
687 | xhci_writel(xhci, temp, | ||
688 | port_array[wIndex]); | ||
689 | } | ||
690 | bus_state->port_c_suspend |= 1 << wIndex; | ||
691 | |||
692 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | ||
693 | wIndex + 1); | ||
694 | if (!slot_id) { | ||
695 | xhci_dbg(xhci, "slot_id is zero\n"); | ||
696 | goto error; | ||
697 | } | ||
698 | xhci_ring_device(xhci, slot_id); | ||
699 | break; | ||
700 | case USB_PORT_FEAT_C_SUSPEND: | ||
701 | bus_state->port_c_suspend &= ~(1 << wIndex); | ||
274 | case USB_PORT_FEAT_C_RESET: | 702 | case USB_PORT_FEAT_C_RESET: |
703 | case USB_PORT_FEAT_C_BH_PORT_RESET: | ||
275 | case USB_PORT_FEAT_C_CONNECTION: | 704 | case USB_PORT_FEAT_C_CONNECTION: |
276 | case USB_PORT_FEAT_C_OVER_CURRENT: | 705 | case USB_PORT_FEAT_C_OVER_CURRENT: |
277 | case USB_PORT_FEAT_C_ENABLE: | 706 | case USB_PORT_FEAT_C_ENABLE: |
707 | case USB_PORT_FEAT_C_PORT_LINK_STATE: | ||
278 | xhci_clear_port_change_bit(xhci, wValue, wIndex, | 708 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
279 | addr, temp); | 709 | port_array[wIndex], temp); |
280 | break; | 710 | break; |
281 | case USB_PORT_FEAT_ENABLE: | 711 | case USB_PORT_FEAT_ENABLE: |
282 | xhci_disable_port(xhci, wIndex, addr, temp); | 712 | xhci_disable_port(hcd, xhci, wIndex, |
713 | port_array[wIndex], temp); | ||
283 | break; | 714 | break; |
284 | default: | 715 | default: |
285 | goto error; | 716 | goto error; |
@@ -306,25 +737,35 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |||
306 | { | 737 | { |
307 | unsigned long flags; | 738 | unsigned long flags; |
308 | u32 temp, status; | 739 | u32 temp, status; |
740 | u32 mask; | ||
309 | int i, retval; | 741 | int i, retval; |
310 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | 742 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
311 | int ports; | 743 | int max_ports; |
312 | u32 __iomem *addr; | 744 | __le32 __iomem **port_array; |
745 | struct xhci_bus_state *bus_state; | ||
313 | 746 | ||
314 | ports = HCS_MAX_PORTS(xhci->hcs_params1); | 747 | max_ports = xhci_get_ports(hcd, &port_array); |
748 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | ||
315 | 749 | ||
316 | /* Initial status is no changes */ | 750 | /* Initial status is no changes */ |
317 | retval = (ports + 8) / 8; | 751 | retval = (max_ports + 8) / 8; |
318 | memset(buf, 0, retval); | 752 | memset(buf, 0, retval); |
319 | status = 0; | 753 | status = 0; |
320 | 754 | ||
755 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC; | ||
756 | |||
321 | spin_lock_irqsave(&xhci->lock, flags); | 757 | spin_lock_irqsave(&xhci->lock, flags); |
322 | /* For each port, did anything change? If so, set that bit in buf. */ | 758 | /* For each port, did anything change? If so, set that bit in buf. */ |
323 | for (i = 0; i < ports; i++) { | 759 | for (i = 0; i < max_ports; i++) { |
324 | addr = &xhci->op_regs->port_status_base + | 760 | temp = xhci_readl(xhci, port_array[i]); |
325 | NUM_PORT_REGS*i; | 761 | if (temp == 0xffffffff) { |
326 | temp = xhci_readl(xhci, addr); | 762 | retval = -ENODEV; |
327 | if (temp & (PORT_CSC | PORT_PEC | PORT_OCC)) { | 763 | break; |
764 | } | ||
765 | if ((temp & mask) != 0 || | ||
766 | (bus_state->port_c_suspend & 1 << i) || | ||
767 | (bus_state->resume_done[i] && time_after_eq( | ||
768 | jiffies, bus_state->resume_done[i]))) { | ||
328 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; | 769 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
329 | status = 1; | 770 | status = 1; |
330 | } | 771 | } |
@@ -332,3 +773,202 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |||
332 | spin_unlock_irqrestore(&xhci->lock, flags); | 773 | spin_unlock_irqrestore(&xhci->lock, flags); |
333 | return status ? retval : 0; | 774 | return status ? retval : 0; |
334 | } | 775 | } |
776 | |||
777 | #ifdef CONFIG_PM | ||
778 | |||
779 | int xhci_bus_suspend(struct usb_hcd *hcd) | ||
780 | { | ||
781 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | ||
782 | int max_ports, port_index; | ||
783 | __le32 __iomem **port_array; | ||
784 | struct xhci_bus_state *bus_state; | ||
785 | unsigned long flags; | ||
786 | |||
787 | max_ports = xhci_get_ports(hcd, &port_array); | ||
788 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | ||
789 | |||
790 | spin_lock_irqsave(&xhci->lock, flags); | ||
791 | |||
792 | if (hcd->self.root_hub->do_remote_wakeup) { | ||
793 | port_index = max_ports; | ||
794 | while (port_index--) { | ||
795 | if (bus_state->resume_done[port_index] != 0) { | ||
796 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
797 | xhci_dbg(xhci, "suspend failed because " | ||
798 | "port %d is resuming\n", | ||
799 | port_index + 1); | ||
800 | return -EBUSY; | ||
801 | } | ||
802 | } | ||
803 | } | ||
804 | |||
805 | port_index = max_ports; | ||
806 | bus_state->bus_suspended = 0; | ||
807 | while (port_index--) { | ||
808 | /* suspend the port if the port is not suspended */ | ||
809 | u32 t1, t2; | ||
810 | int slot_id; | ||
811 | |||
812 | t1 = xhci_readl(xhci, port_array[port_index]); | ||
813 | t2 = xhci_port_state_to_neutral(t1); | ||
814 | |||
815 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { | ||
816 | xhci_dbg(xhci, "port %d not suspended\n", port_index); | ||
817 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | ||
818 | port_index + 1); | ||
819 | if (slot_id) { | ||
820 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
821 | xhci_stop_device(xhci, slot_id, 1); | ||
822 | spin_lock_irqsave(&xhci->lock, flags); | ||
823 | } | ||
824 | t2 &= ~PORT_PLS_MASK; | ||
825 | t2 |= PORT_LINK_STROBE | XDEV_U3; | ||
826 | set_bit(port_index, &bus_state->bus_suspended); | ||
827 | } | ||
828 | if (hcd->self.root_hub->do_remote_wakeup) { | ||
829 | if (t1 & PORT_CONNECT) { | ||
830 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | ||
831 | t2 &= ~PORT_WKCONN_E; | ||
832 | } else { | ||
833 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | ||
834 | t2 &= ~PORT_WKDISC_E; | ||
835 | } | ||
836 | } else | ||
837 | t2 &= ~PORT_WAKE_BITS; | ||
838 | |||
839 | t1 = xhci_port_state_to_neutral(t1); | ||
840 | if (t1 != t2) | ||
841 | xhci_writel(xhci, t2, port_array[port_index]); | ||
842 | |||
843 | if (hcd->speed != HCD_USB3) { | ||
844 | /* enable remote wake up for USB 2.0 */ | ||
845 | __le32 __iomem *addr; | ||
846 | u32 tmp; | ||
847 | |||
848 | /* Add one to the port status register address to get | ||
849 | * the port power control register address. | ||
850 | */ | ||
851 | addr = port_array[port_index] + 1; | ||
852 | tmp = xhci_readl(xhci, addr); | ||
853 | tmp |= PORT_RWE; | ||
854 | xhci_writel(xhci, tmp, addr); | ||
855 | } | ||
856 | } | ||
857 | hcd->state = HC_STATE_SUSPENDED; | ||
858 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); | ||
859 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
860 | return 0; | ||
861 | } | ||
862 | |||
863 | int xhci_bus_resume(struct usb_hcd *hcd) | ||
864 | { | ||
865 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | ||
866 | int max_ports, port_index; | ||
867 | __le32 __iomem **port_array; | ||
868 | struct xhci_bus_state *bus_state; | ||
869 | u32 temp; | ||
870 | unsigned long flags; | ||
871 | |||
872 | max_ports = xhci_get_ports(hcd, &port_array); | ||
873 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | ||
874 | |||
875 | if (time_before(jiffies, bus_state->next_statechange)) | ||
876 | msleep(5); | ||
877 | |||
878 | spin_lock_irqsave(&xhci->lock, flags); | ||
879 | if (!HCD_HW_ACCESSIBLE(hcd)) { | ||
880 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
881 | return -ESHUTDOWN; | ||
882 | } | ||
883 | |||
884 | /* delay the irqs */ | ||
885 | temp = xhci_readl(xhci, &xhci->op_regs->command); | ||
886 | temp &= ~CMD_EIE; | ||
887 | xhci_writel(xhci, temp, &xhci->op_regs->command); | ||
888 | |||
889 | port_index = max_ports; | ||
890 | while (port_index--) { | ||
891 | /* Check whether need resume ports. If needed | ||
892 | resume port and disable remote wakeup */ | ||
893 | u32 temp; | ||
894 | int slot_id; | ||
895 | |||
896 | temp = xhci_readl(xhci, port_array[port_index]); | ||
897 | if (DEV_SUPERSPEED(temp)) | ||
898 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | ||
899 | else | ||
900 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | ||
901 | if (test_bit(port_index, &bus_state->bus_suspended) && | ||
902 | (temp & PORT_PLS_MASK)) { | ||
903 | if (DEV_SUPERSPEED(temp)) { | ||
904 | temp = xhci_port_state_to_neutral(temp); | ||
905 | temp &= ~PORT_PLS_MASK; | ||
906 | temp |= PORT_LINK_STROBE | XDEV_U0; | ||
907 | xhci_writel(xhci, temp, port_array[port_index]); | ||
908 | } else { | ||
909 | temp = xhci_port_state_to_neutral(temp); | ||
910 | temp &= ~PORT_PLS_MASK; | ||
911 | temp |= PORT_LINK_STROBE | XDEV_RESUME; | ||
912 | xhci_writel(xhci, temp, port_array[port_index]); | ||
913 | |||
914 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
915 | msleep(20); | ||
916 | spin_lock_irqsave(&xhci->lock, flags); | ||
917 | |||
918 | temp = xhci_readl(xhci, port_array[port_index]); | ||
919 | temp = xhci_port_state_to_neutral(temp); | ||
920 | temp &= ~PORT_PLS_MASK; | ||
921 | temp |= PORT_LINK_STROBE | XDEV_U0; | ||
922 | xhci_writel(xhci, temp, port_array[port_index]); | ||
923 | } | ||
924 | /* wait for the port to enter U0 and report port link | ||
925 | * state change. | ||
926 | */ | ||
927 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
928 | msleep(20); | ||
929 | spin_lock_irqsave(&xhci->lock, flags); | ||
930 | |||
931 | /* Clear PLC */ | ||
932 | temp = xhci_readl(xhci, port_array[port_index]); | ||
933 | if (temp & PORT_PLC) { | ||
934 | temp = xhci_port_state_to_neutral(temp); | ||
935 | temp |= PORT_PLC; | ||
936 | xhci_writel(xhci, temp, port_array[port_index]); | ||
937 | } | ||
938 | |||
939 | slot_id = xhci_find_slot_id_by_port(hcd, | ||
940 | xhci, port_index + 1); | ||
941 | if (slot_id) | ||
942 | xhci_ring_device(xhci, slot_id); | ||
943 | } else | ||
944 | xhci_writel(xhci, temp, port_array[port_index]); | ||
945 | |||
946 | if (hcd->speed != HCD_USB3) { | ||
947 | /* disable remote wake up for USB 2.0 */ | ||
948 | __le32 __iomem *addr; | ||
949 | u32 tmp; | ||
950 | |||
951 | /* Add one to the port status register address to get | ||
952 | * the port power control register address. | ||
953 | */ | ||
954 | addr = port_array[port_index] + 1; | ||
955 | tmp = xhci_readl(xhci, addr); | ||
956 | tmp &= ~PORT_RWE; | ||
957 | xhci_writel(xhci, tmp, addr); | ||
958 | } | ||
959 | } | ||
960 | |||
961 | (void) xhci_readl(xhci, &xhci->op_regs->command); | ||
962 | |||
963 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); | ||
964 | /* re-enable irqs */ | ||
965 | temp = xhci_readl(xhci, &xhci->op_regs->command); | ||
966 | temp |= CMD_EIE; | ||
967 | xhci_writel(xhci, temp, &xhci->op_regs->command); | ||
968 | temp = xhci_readl(xhci, &xhci->op_regs->command); | ||
969 | |||
970 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
971 | return 0; | ||
972 | } | ||
973 | |||
974 | #endif /* CONFIG_PM */ | ||
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 4e51343ddffc..fcb7f7efc86d 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c | |||
@@ -89,16 +89,17 @@ static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |||
89 | return; | 89 | return; |
90 | prev->next = next; | 90 | prev->next = next; |
91 | if (link_trbs) { | 91 | if (link_trbs) { |
92 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma; | 92 | prev->trbs[TRBS_PER_SEGMENT-1].link. |
93 | segment_ptr = cpu_to_le64(next->dma); | ||
93 | 94 | ||
94 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | 95 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ |
95 | val = prev->trbs[TRBS_PER_SEGMENT-1].link.control; | 96 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
96 | val &= ~TRB_TYPE_BITMASK; | 97 | val &= ~TRB_TYPE_BITMASK; |
97 | val |= TRB_TYPE(TRB_LINK); | 98 | val |= TRB_TYPE(TRB_LINK); |
98 | /* Always set the chain bit with 0.95 hardware */ | 99 | /* Always set the chain bit with 0.95 hardware */ |
99 | if (xhci_link_trb_quirk(xhci)) | 100 | if (xhci_link_trb_quirk(xhci)) |
100 | val |= TRB_CHAIN; | 101 | val |= TRB_CHAIN; |
101 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = val; | 102 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
102 | } | 103 | } |
103 | xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n", | 104 | xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n", |
104 | (unsigned long long)prev->dma, | 105 | (unsigned long long)prev->dma, |
@@ -186,7 +187,8 @@ static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |||
186 | 187 | ||
187 | if (link_trbs) { | 188 | if (link_trbs) { |
188 | /* See section 4.9.2.1 and 6.4.4.1 */ | 189 | /* See section 4.9.2.1 and 6.4.4.1 */ |
189 | prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE); | 190 | prev->trbs[TRBS_PER_SEGMENT-1].link. |
191 | control |= cpu_to_le32(LINK_TOGGLE); | ||
190 | xhci_dbg(xhci, "Wrote link toggle flag to" | 192 | xhci_dbg(xhci, "Wrote link toggle flag to" |
191 | " segment %p (virtual), 0x%llx (DMA)\n", | 193 | " segment %p (virtual), 0x%llx (DMA)\n", |
192 | prev, (unsigned long long)prev->dma); | 194 | prev, (unsigned long long)prev->dma); |
@@ -207,14 +209,13 @@ void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, | |||
207 | 209 | ||
208 | rings_cached = virt_dev->num_rings_cached; | 210 | rings_cached = virt_dev->num_rings_cached; |
209 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | 211 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { |
210 | virt_dev->num_rings_cached++; | ||
211 | rings_cached = virt_dev->num_rings_cached; | ||
212 | virt_dev->ring_cache[rings_cached] = | 212 | virt_dev->ring_cache[rings_cached] = |
213 | virt_dev->eps[ep_index].ring; | 213 | virt_dev->eps[ep_index].ring; |
214 | virt_dev->num_rings_cached++; | ||
214 | xhci_dbg(xhci, "Cached old ring, " | 215 | xhci_dbg(xhci, "Cached old ring, " |
215 | "%d ring%s cached\n", | 216 | "%d ring%s cached\n", |
216 | rings_cached, | 217 | virt_dev->num_rings_cached, |
217 | (rings_cached > 1) ? "s" : ""); | 218 | (virt_dev->num_rings_cached > 1) ? "s" : ""); |
218 | } else { | 219 | } else { |
219 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | 220 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); |
220 | xhci_dbg(xhci, "Ring cache full (%d rings), " | 221 | xhci_dbg(xhci, "Ring cache full (%d rings), " |
@@ -307,7 +308,7 @@ struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |||
307 | 308 | ||
308 | /***************** Streams structures manipulation *************************/ | 309 | /***************** Streams structures manipulation *************************/ |
309 | 310 | ||
310 | void xhci_free_stream_ctx(struct xhci_hcd *xhci, | 311 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
311 | unsigned int num_stream_ctxs, | 312 | unsigned int num_stream_ctxs, |
312 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | 313 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) |
313 | { | 314 | { |
@@ -335,7 +336,7 @@ void xhci_free_stream_ctx(struct xhci_hcd *xhci, | |||
335 | * The stream context array must be a power of 2, and can be as small as | 336 | * The stream context array must be a power of 2, and can be as small as |
336 | * 64 bytes or as large as 1MB. | 337 | * 64 bytes or as large as 1MB. |
337 | */ | 338 | */ |
338 | struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, | 339 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
339 | unsigned int num_stream_ctxs, dma_addr_t *dma, | 340 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
340 | gfp_t mem_flags) | 341 | gfp_t mem_flags) |
341 | { | 342 | { |
@@ -548,7 +549,8 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |||
548 | addr = cur_ring->first_seg->dma | | 549 | addr = cur_ring->first_seg->dma | |
549 | SCT_FOR_CTX(SCT_PRI_TR) | | 550 | SCT_FOR_CTX(SCT_PRI_TR) | |
550 | cur_ring->cycle_state; | 551 | cur_ring->cycle_state; |
551 | stream_info->stream_ctx_array[cur_stream].stream_ring = addr; | 552 | stream_info->stream_ctx_array[cur_stream]. |
553 | stream_ring = cpu_to_le64(addr); | ||
552 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", | 554 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
553 | cur_stream, (unsigned long long) addr); | 555 | cur_stream, (unsigned long long) addr); |
554 | 556 | ||
@@ -614,10 +616,10 @@ void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |||
614 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | 616 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; |
615 | xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n", | 617 | xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n", |
616 | 1 << (max_primary_streams + 1)); | 618 | 1 << (max_primary_streams + 1)); |
617 | ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK; | 619 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
618 | ep_ctx->ep_info |= EP_MAXPSTREAMS(max_primary_streams); | 620 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) |
619 | ep_ctx->ep_info |= EP_HAS_LSA; | 621 | | EP_HAS_LSA); |
620 | ep_ctx->deq = stream_info->ctx_array_dma; | 622 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); |
621 | } | 623 | } |
622 | 624 | ||
623 | /* | 625 | /* |
@@ -630,10 +632,9 @@ void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, | |||
630 | struct xhci_virt_ep *ep) | 632 | struct xhci_virt_ep *ep) |
631 | { | 633 | { |
632 | dma_addr_t addr; | 634 | dma_addr_t addr; |
633 | ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK; | 635 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
634 | ep_ctx->ep_info &= ~EP_HAS_LSA; | ||
635 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); | 636 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
636 | ep_ctx->deq = addr | ep->ring->cycle_state; | 637 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
637 | } | 638 | } |
638 | 639 | ||
639 | /* Frees all stream contexts associated with the endpoint, | 640 | /* Frees all stream contexts associated with the endpoint, |
@@ -778,13 +779,14 @@ int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, | |||
778 | 779 | ||
779 | init_completion(&dev->cmd_completion); | 780 | init_completion(&dev->cmd_completion); |
780 | INIT_LIST_HEAD(&dev->cmd_list); | 781 | INIT_LIST_HEAD(&dev->cmd_list); |
782 | dev->udev = udev; | ||
781 | 783 | ||
782 | /* Point to output device context in dcbaa. */ | 784 | /* Point to output device context in dcbaa. */ |
783 | xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma; | 785 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
784 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", | 786 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
785 | slot_id, | 787 | slot_id, |
786 | &xhci->dcbaa->dev_context_ptrs[slot_id], | 788 | &xhci->dcbaa->dev_context_ptrs[slot_id], |
787 | (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]); | 789 | (unsigned long long) le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
788 | 790 | ||
789 | return 1; | 791 | return 1; |
790 | fail: | 792 | fail: |
@@ -809,8 +811,58 @@ void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, | |||
809 | * configured device has reset, so all control transfers should have | 811 | * configured device has reset, so all control transfers should have |
810 | * been completed or cancelled before the reset. | 812 | * been completed or cancelled before the reset. |
811 | */ | 813 | */ |
812 | ep0_ctx->deq = xhci_trb_virt_to_dma(ep_ring->enq_seg, ep_ring->enqueue); | 814 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
813 | ep0_ctx->deq |= ep_ring->cycle_state; | 815 | ep_ring->enqueue) |
816 | | ep_ring->cycle_state); | ||
817 | } | ||
818 | |||
819 | /* | ||
820 | * The xHCI roothub may have ports of differing speeds in any order in the port | ||
821 | * status registers. xhci->port_array provides an array of the port speed for | ||
822 | * each offset into the port status registers. | ||
823 | * | ||
824 | * The xHCI hardware wants to know the roothub port number that the USB device | ||
825 | * is attached to (or the roothub port its ancestor hub is attached to). All we | ||
826 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | ||
827 | * roothub, but that doesn't give us the real index into the HW port status | ||
828 | * registers. Scan through the xHCI roothub port array, looking for the Nth | ||
829 | * entry of the correct port speed. Return the port number of that entry. | ||
830 | */ | ||
831 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | ||
832 | struct usb_device *udev) | ||
833 | { | ||
834 | struct usb_device *top_dev; | ||
835 | unsigned int num_similar_speed_ports; | ||
836 | unsigned int faked_port_num; | ||
837 | int i; | ||
838 | |||
839 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | ||
840 | top_dev = top_dev->parent) | ||
841 | /* Found device below root hub */; | ||
842 | faked_port_num = top_dev->portnum; | ||
843 | for (i = 0, num_similar_speed_ports = 0; | ||
844 | i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { | ||
845 | u8 port_speed = xhci->port_array[i]; | ||
846 | |||
847 | /* | ||
848 | * Skip ports that don't have known speeds, or have duplicate | ||
849 | * Extended Capabilities port speed entries. | ||
850 | */ | ||
851 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) | ||
852 | continue; | ||
853 | |||
854 | /* | ||
855 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | ||
856 | * 1.1 ports are under the USB 2.0 hub. If the port speed | ||
857 | * matches the device speed, it's a similar speed port. | ||
858 | */ | ||
859 | if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER)) | ||
860 | num_similar_speed_ports++; | ||
861 | if (num_similar_speed_ports == faked_port_num) | ||
862 | /* Roothub ports are numbered from 1 to N */ | ||
863 | return i+1; | ||
864 | } | ||
865 | return 0; | ||
814 | } | 866 | } |
815 | 867 | ||
816 | /* Setup an xHCI virtual device for a Set Address command */ | 868 | /* Setup an xHCI virtual device for a Set Address command */ |
@@ -818,9 +870,10 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud | |||
818 | { | 870 | { |
819 | struct xhci_virt_device *dev; | 871 | struct xhci_virt_device *dev; |
820 | struct xhci_ep_ctx *ep0_ctx; | 872 | struct xhci_ep_ctx *ep0_ctx; |
821 | struct usb_device *top_dev; | ||
822 | struct xhci_slot_ctx *slot_ctx; | 873 | struct xhci_slot_ctx *slot_ctx; |
823 | struct xhci_input_control_ctx *ctrl_ctx; | 874 | struct xhci_input_control_ctx *ctrl_ctx; |
875 | u32 port_num; | ||
876 | struct usb_device *top_dev; | ||
824 | 877 | ||
825 | dev = xhci->devs[udev->slot_id]; | 878 | dev = xhci->devs[udev->slot_id]; |
826 | /* Slot ID 0 is reserved */ | 879 | /* Slot ID 0 is reserved */ |
@@ -834,24 +887,22 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud | |||
834 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); | 887 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
835 | 888 | ||
836 | /* 2) New slot context and endpoint 0 context are valid*/ | 889 | /* 2) New slot context and endpoint 0 context are valid*/ |
837 | ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG; | 890 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
838 | 891 | ||
839 | /* 3) Only the control endpoint is valid - one endpoint context */ | 892 | /* 3) Only the control endpoint is valid - one endpoint context */ |
840 | slot_ctx->dev_info |= LAST_CTX(1); | 893 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | (u32) udev->route); |
841 | |||
842 | slot_ctx->dev_info |= (u32) udev->route; | ||
843 | switch (udev->speed) { | 894 | switch (udev->speed) { |
844 | case USB_SPEED_SUPER: | 895 | case USB_SPEED_SUPER: |
845 | slot_ctx->dev_info |= (u32) SLOT_SPEED_SS; | 896 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_SS); |
846 | break; | 897 | break; |
847 | case USB_SPEED_HIGH: | 898 | case USB_SPEED_HIGH: |
848 | slot_ctx->dev_info |= (u32) SLOT_SPEED_HS; | 899 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_HS); |
849 | break; | 900 | break; |
850 | case USB_SPEED_FULL: | 901 | case USB_SPEED_FULL: |
851 | slot_ctx->dev_info |= (u32) SLOT_SPEED_FS; | 902 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_FS); |
852 | break; | 903 | break; |
853 | case USB_SPEED_LOW: | 904 | case USB_SPEED_LOW: |
854 | slot_ctx->dev_info |= (u32) SLOT_SPEED_LS; | 905 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_LS); |
855 | break; | 906 | break; |
856 | case USB_SPEED_WIRELESS: | 907 | case USB_SPEED_WIRELESS: |
857 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); | 908 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
@@ -862,40 +913,45 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud | |||
862 | BUG(); | 913 | BUG(); |
863 | } | 914 | } |
864 | /* Find the root hub port this device is under */ | 915 | /* Find the root hub port this device is under */ |
916 | port_num = xhci_find_real_port_number(xhci, udev); | ||
917 | if (!port_num) | ||
918 | return -EINVAL; | ||
919 | slot_ctx->dev_info2 |= cpu_to_le32((u32) ROOT_HUB_PORT(port_num)); | ||
920 | /* Set the port number in the virtual_device to the faked port number */ | ||
865 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | 921 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
866 | top_dev = top_dev->parent) | 922 | top_dev = top_dev->parent) |
867 | /* Found device below root hub */; | 923 | /* Found device below root hub */; |
868 | slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum); | 924 | dev->port = top_dev->portnum; |
869 | xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum); | 925 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
870 | 926 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->port); | |
871 | /* Is this a LS/FS device under a HS hub? */ | 927 | |
872 | if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) && | 928 | /* Is this a LS/FS device under an external HS hub? */ |
873 | udev->tt) { | 929 | if (udev->tt && udev->tt->hub->parent) { |
874 | slot_ctx->tt_info = udev->tt->hub->slot_id; | 930 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
875 | slot_ctx->tt_info |= udev->ttport << 8; | 931 | (udev->ttport << 8)); |
876 | if (udev->tt->multi) | 932 | if (udev->tt->multi) |
877 | slot_ctx->dev_info |= DEV_MTT; | 933 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
878 | } | 934 | } |
879 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); | 935 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
880 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); | 936 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
881 | 937 | ||
882 | /* Step 4 - ring already allocated */ | 938 | /* Step 4 - ring already allocated */ |
883 | /* Step 5 */ | 939 | /* Step 5 */ |
884 | ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP); | 940 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
885 | /* | 941 | /* |
886 | * XXX: Not sure about wireless USB devices. | 942 | * XXX: Not sure about wireless USB devices. |
887 | */ | 943 | */ |
888 | switch (udev->speed) { | 944 | switch (udev->speed) { |
889 | case USB_SPEED_SUPER: | 945 | case USB_SPEED_SUPER: |
890 | ep0_ctx->ep_info2 |= MAX_PACKET(512); | 946 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512)); |
891 | break; | 947 | break; |
892 | case USB_SPEED_HIGH: | 948 | case USB_SPEED_HIGH: |
893 | /* USB core guesses at a 64-byte max packet first for FS devices */ | 949 | /* USB core guesses at a 64-byte max packet first for FS devices */ |
894 | case USB_SPEED_FULL: | 950 | case USB_SPEED_FULL: |
895 | ep0_ctx->ep_info2 |= MAX_PACKET(64); | 951 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64)); |
896 | break; | 952 | break; |
897 | case USB_SPEED_LOW: | 953 | case USB_SPEED_LOW: |
898 | ep0_ctx->ep_info2 |= MAX_PACKET(8); | 954 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8)); |
899 | break; | 955 | break; |
900 | case USB_SPEED_WIRELESS: | 956 | case USB_SPEED_WIRELESS: |
901 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); | 957 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
@@ -906,18 +962,67 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud | |||
906 | BUG(); | 962 | BUG(); |
907 | } | 963 | } |
908 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ | 964 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
909 | ep0_ctx->ep_info2 |= MAX_BURST(0); | 965 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3)); |
910 | ep0_ctx->ep_info2 |= ERROR_COUNT(3); | ||
911 | 966 | ||
912 | ep0_ctx->deq = | 967 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
913 | dev->eps[0].ring->first_seg->dma; | 968 | dev->eps[0].ring->cycle_state); |
914 | ep0_ctx->deq |= dev->eps[0].ring->cycle_state; | ||
915 | 969 | ||
916 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ | 970 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ |
917 | 971 | ||
918 | return 0; | 972 | return 0; |
919 | } | 973 | } |
920 | 974 | ||
975 | /* | ||
976 | * Convert interval expressed as 2^(bInterval - 1) == interval into | ||
977 | * straight exponent value 2^n == interval. | ||
978 | * | ||
979 | */ | ||
980 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | ||
981 | struct usb_host_endpoint *ep) | ||
982 | { | ||
983 | unsigned int interval; | ||
984 | |||
985 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | ||
986 | if (interval != ep->desc.bInterval - 1) | ||
987 | dev_warn(&udev->dev, | ||
988 | "ep %#x - rounding interval to %d %sframes\n", | ||
989 | ep->desc.bEndpointAddress, | ||
990 | 1 << interval, | ||
991 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | ||
992 | |||
993 | if (udev->speed == USB_SPEED_FULL) { | ||
994 | /* | ||
995 | * Full speed isoc endpoints specify interval in frames, | ||
996 | * not microframes. We are using microframes everywhere, | ||
997 | * so adjust accordingly. | ||
998 | */ | ||
999 | interval += 3; /* 1 frame = 2^3 uframes */ | ||
1000 | } | ||
1001 | |||
1002 | return interval; | ||
1003 | } | ||
1004 | |||
1005 | /* | ||
1006 | * Convert bInterval expressed in frames (in 1-255 range) to exponent of | ||
1007 | * microframes, rounded down to nearest power of 2. | ||
1008 | */ | ||
1009 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | ||
1010 | struct usb_host_endpoint *ep) | ||
1011 | { | ||
1012 | unsigned int interval; | ||
1013 | |||
1014 | interval = fls(8 * ep->desc.bInterval) - 1; | ||
1015 | interval = clamp_val(interval, 3, 10); | ||
1016 | if ((1 << interval) != 8 * ep->desc.bInterval) | ||
1017 | dev_warn(&udev->dev, | ||
1018 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", | ||
1019 | ep->desc.bEndpointAddress, | ||
1020 | 1 << interval, | ||
1021 | 8 * ep->desc.bInterval); | ||
1022 | |||
1023 | return interval; | ||
1024 | } | ||
1025 | |||
921 | /* Return the polling or NAK interval. | 1026 | /* Return the polling or NAK interval. |
922 | * | 1027 | * |
923 | * The polling interval is expressed in "microframes". If xHCI's Interval field | 1028 | * The polling interval is expressed in "microframes". If xHCI's Interval field |
@@ -926,7 +1031,7 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud | |||
926 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | 1031 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval |
927 | * is set to 0. | 1032 | * is set to 0. |
928 | */ | 1033 | */ |
929 | static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev, | 1034 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
930 | struct usb_host_endpoint *ep) | 1035 | struct usb_host_endpoint *ep) |
931 | { | 1036 | { |
932 | unsigned int interval = 0; | 1037 | unsigned int interval = 0; |
@@ -935,45 +1040,38 @@ static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev, | |||
935 | case USB_SPEED_HIGH: | 1040 | case USB_SPEED_HIGH: |
936 | /* Max NAK rate */ | 1041 | /* Max NAK rate */ |
937 | if (usb_endpoint_xfer_control(&ep->desc) || | 1042 | if (usb_endpoint_xfer_control(&ep->desc) || |
938 | usb_endpoint_xfer_bulk(&ep->desc)) | 1043 | usb_endpoint_xfer_bulk(&ep->desc)) { |
939 | interval = ep->desc.bInterval; | 1044 | interval = ep->desc.bInterval; |
1045 | break; | ||
1046 | } | ||
940 | /* Fall through - SS and HS isoc/int have same decoding */ | 1047 | /* Fall through - SS and HS isoc/int have same decoding */ |
1048 | |||
941 | case USB_SPEED_SUPER: | 1049 | case USB_SPEED_SUPER: |
942 | if (usb_endpoint_xfer_int(&ep->desc) || | 1050 | if (usb_endpoint_xfer_int(&ep->desc) || |
943 | usb_endpoint_xfer_isoc(&ep->desc)) { | 1051 | usb_endpoint_xfer_isoc(&ep->desc)) { |
944 | if (ep->desc.bInterval == 0) | 1052 | interval = xhci_parse_exponent_interval(udev, ep); |
945 | interval = 0; | ||
946 | else | ||
947 | interval = ep->desc.bInterval - 1; | ||
948 | if (interval > 15) | ||
949 | interval = 15; | ||
950 | if (interval != ep->desc.bInterval + 1) | ||
951 | dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n", | ||
952 | ep->desc.bEndpointAddress, 1 << interval); | ||
953 | } | 1053 | } |
954 | break; | 1054 | break; |
955 | /* Convert bInterval (in 1-255 frames) to microframes and round down to | 1055 | |
956 | * nearest power of 2. | ||
957 | */ | ||
958 | case USB_SPEED_FULL: | 1056 | case USB_SPEED_FULL: |
1057 | if (usb_endpoint_xfer_isoc(&ep->desc)) { | ||
1058 | interval = xhci_parse_exponent_interval(udev, ep); | ||
1059 | break; | ||
1060 | } | ||
1061 | /* | ||
1062 | * Fall through for interrupt endpoint interval decoding | ||
1063 | * since it uses the same rules as low speed interrupt | ||
1064 | * endpoints. | ||
1065 | */ | ||
1066 | |||
959 | case USB_SPEED_LOW: | 1067 | case USB_SPEED_LOW: |
960 | if (usb_endpoint_xfer_int(&ep->desc) || | 1068 | if (usb_endpoint_xfer_int(&ep->desc) || |
961 | usb_endpoint_xfer_isoc(&ep->desc)) { | 1069 | usb_endpoint_xfer_isoc(&ep->desc)) { |
962 | interval = fls(8*ep->desc.bInterval) - 1; | 1070 | |
963 | if (interval > 10) | 1071 | interval = xhci_parse_frame_interval(udev, ep); |
964 | interval = 10; | ||
965 | if (interval < 3) | ||
966 | interval = 3; | ||
967 | if ((1 << interval) != 8*ep->desc.bInterval) | ||
968 | dev_warn(&udev->dev, | ||
969 | "ep %#x - rounding interval" | ||
970 | " to %d microframes, " | ||
971 | "ep desc says %d microframes\n", | ||
972 | ep->desc.bEndpointAddress, | ||
973 | 1 << interval, | ||
974 | 8*ep->desc.bInterval); | ||
975 | } | 1072 | } |
976 | break; | 1073 | break; |
1074 | |||
977 | default: | 1075 | default: |
978 | BUG(); | 1076 | BUG(); |
979 | } | 1077 | } |
@@ -985,7 +1083,7 @@ static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev, | |||
985 | * transaction opportunities per microframe", but that goes in the Max Burst | 1083 | * transaction opportunities per microframe", but that goes in the Max Burst |
986 | * endpoint context field. | 1084 | * endpoint context field. |
987 | */ | 1085 | */ |
988 | static inline u32 xhci_get_endpoint_mult(struct usb_device *udev, | 1086 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
989 | struct usb_host_endpoint *ep) | 1087 | struct usb_host_endpoint *ep) |
990 | { | 1088 | { |
991 | if (udev->speed != USB_SPEED_SUPER || | 1089 | if (udev->speed != USB_SPEED_SUPER || |
@@ -994,7 +1092,7 @@ static inline u32 xhci_get_endpoint_mult(struct usb_device *udev, | |||
994 | return ep->ss_ep_comp.bmAttributes; | 1092 | return ep->ss_ep_comp.bmAttributes; |
995 | } | 1093 | } |
996 | 1094 | ||
997 | static inline u32 xhci_get_endpoint_type(struct usb_device *udev, | 1095 | static u32 xhci_get_endpoint_type(struct usb_device *udev, |
998 | struct usb_host_endpoint *ep) | 1096 | struct usb_host_endpoint *ep) |
999 | { | 1097 | { |
1000 | int in; | 1098 | int in; |
@@ -1028,7 +1126,7 @@ static inline u32 xhci_get_endpoint_type(struct usb_device *udev, | |||
1028 | * Basically, this is the maxpacket size, multiplied by the burst size | 1126 | * Basically, this is the maxpacket size, multiplied by the burst size |
1029 | * and mult size. | 1127 | * and mult size. |
1030 | */ | 1128 | */ |
1031 | static inline u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, | 1129 | static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, |
1032 | struct usb_device *udev, | 1130 | struct usb_device *udev, |
1033 | struct usb_host_endpoint *ep) | 1131 | struct usb_host_endpoint *ep) |
1034 | { | 1132 | { |
@@ -1041,10 +1139,10 @@ static inline u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, | |||
1041 | return 0; | 1139 | return 0; |
1042 | 1140 | ||
1043 | if (udev->speed == USB_SPEED_SUPER) | 1141 | if (udev->speed == USB_SPEED_SUPER) |
1044 | return ep->ss_ep_comp.wBytesPerInterval; | 1142 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
1045 | 1143 | ||
1046 | max_packet = ep->desc.wMaxPacketSize & 0x3ff; | 1144 | max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize)); |
1047 | max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11; | 1145 | max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize) & 0x1800) >> 11; |
1048 | /* A 0 in max burst means 1 transfer per ESIT */ | 1146 | /* A 0 in max burst means 1 transfer per ESIT */ |
1049 | return max_packet * (max_burst + 1); | 1147 | return max_packet * (max_burst + 1); |
1050 | } | 1148 | } |
@@ -1093,33 +1191,31 @@ int xhci_endpoint_init(struct xhci_hcd *xhci, | |||
1093 | } | 1191 | } |
1094 | virt_dev->eps[ep_index].skip = false; | 1192 | virt_dev->eps[ep_index].skip = false; |
1095 | ep_ring = virt_dev->eps[ep_index].new_ring; | 1193 | ep_ring = virt_dev->eps[ep_index].new_ring; |
1096 | ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state; | 1194 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state); |
1097 | 1195 | ||
1098 | ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep); | 1196 | ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep) |
1099 | ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep)); | 1197 | | EP_MULT(xhci_get_endpoint_mult(udev, ep))); |
1100 | 1198 | ||
1101 | /* FIXME dig Mult and streams info out of ep companion desc */ | 1199 | /* FIXME dig Mult and streams info out of ep companion desc */ |
1102 | 1200 | ||
1103 | /* Allow 3 retries for everything but isoc; | 1201 | /* Allow 3 retries for everything but isoc; |
1104 | * error count = 0 means infinite retries. | 1202 | * CErr shall be set to 0 for Isoch endpoints. |
1105 | */ | 1203 | */ |
1106 | if (!usb_endpoint_xfer_isoc(&ep->desc)) | 1204 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
1107 | ep_ctx->ep_info2 = ERROR_COUNT(3); | 1205 | ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3)); |
1108 | else | 1206 | else |
1109 | ep_ctx->ep_info2 = ERROR_COUNT(1); | 1207 | ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0)); |
1110 | 1208 | ||
1111 | ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep); | 1209 | ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep)); |
1112 | 1210 | ||
1113 | /* Set the max packet size and max burst */ | 1211 | /* Set the max packet size and max burst */ |
1114 | switch (udev->speed) { | 1212 | switch (udev->speed) { |
1115 | case USB_SPEED_SUPER: | 1213 | case USB_SPEED_SUPER: |
1116 | max_packet = ep->desc.wMaxPacketSize; | 1214 | max_packet = le16_to_cpu(ep->desc.wMaxPacketSize); |
1117 | ep_ctx->ep_info2 |= MAX_PACKET(max_packet); | 1215 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet)); |
1118 | /* dig out max burst from ep companion desc */ | 1216 | /* dig out max burst from ep companion desc */ |
1119 | max_packet = ep->ss_ep_comp.bMaxBurst; | 1217 | max_packet = ep->ss_ep_comp.bMaxBurst; |
1120 | if (!max_packet) | 1218 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet)); |
1121 | xhci_warn(xhci, "WARN no SS endpoint bMaxBurst\n"); | ||
1122 | ep_ctx->ep_info2 |= MAX_BURST(max_packet); | ||
1123 | break; | 1219 | break; |
1124 | case USB_SPEED_HIGH: | 1220 | case USB_SPEED_HIGH: |
1125 | /* bits 11:12 specify the number of additional transaction | 1221 | /* bits 11:12 specify the number of additional transaction |
@@ -1127,20 +1223,21 @@ int xhci_endpoint_init(struct xhci_hcd *xhci, | |||
1127 | */ | 1223 | */ |
1128 | if (usb_endpoint_xfer_isoc(&ep->desc) || | 1224 | if (usb_endpoint_xfer_isoc(&ep->desc) || |
1129 | usb_endpoint_xfer_int(&ep->desc)) { | 1225 | usb_endpoint_xfer_int(&ep->desc)) { |
1130 | max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11; | 1226 | max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize) |
1131 | ep_ctx->ep_info2 |= MAX_BURST(max_burst); | 1227 | & 0x1800) >> 11; |
1228 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst)); | ||
1132 | } | 1229 | } |
1133 | /* Fall through */ | 1230 | /* Fall through */ |
1134 | case USB_SPEED_FULL: | 1231 | case USB_SPEED_FULL: |
1135 | case USB_SPEED_LOW: | 1232 | case USB_SPEED_LOW: |
1136 | max_packet = ep->desc.wMaxPacketSize & 0x3ff; | 1233 | max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize)); |
1137 | ep_ctx->ep_info2 |= MAX_PACKET(max_packet); | 1234 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet)); |
1138 | break; | 1235 | break; |
1139 | default: | 1236 | default: |
1140 | BUG(); | 1237 | BUG(); |
1141 | } | 1238 | } |
1142 | max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); | 1239 | max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); |
1143 | ep_ctx->tx_info = MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload); | 1240 | ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload)); |
1144 | 1241 | ||
1145 | /* | 1242 | /* |
1146 | * XXX no idea how to calculate the average TRB buffer length for bulk | 1243 | * XXX no idea how to calculate the average TRB buffer length for bulk |
@@ -1156,8 +1253,15 @@ int xhci_endpoint_init(struct xhci_hcd *xhci, | |||
1156 | * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't | 1253 | * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't |
1157 | * use Event Data TRBs, and we don't chain in a link TRB on short | 1254 | * use Event Data TRBs, and we don't chain in a link TRB on short |
1158 | * transfers, we're basically dividing by 1. | 1255 | * transfers, we're basically dividing by 1. |
1256 | * | ||
1257 | * xHCI 1.0 specification indicates that the Average TRB Length should | ||
1258 | * be set to 8 for control endpoints. | ||
1159 | */ | 1259 | */ |
1160 | ep_ctx->tx_info |= AVG_TRB_LENGTH_FOR_EP(max_esit_payload); | 1260 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100) |
1261 | ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8)); | ||
1262 | else | ||
1263 | ep_ctx->tx_info |= | ||
1264 | cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload)); | ||
1161 | 1265 | ||
1162 | /* FIXME Debug endpoint context */ | 1266 | /* FIXME Debug endpoint context */ |
1163 | return 0; | 1267 | return 0; |
@@ -1257,7 +1361,7 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |||
1257 | if (!xhci->scratchpad->sp_dma_buffers) | 1361 | if (!xhci->scratchpad->sp_dma_buffers) |
1258 | goto fail_sp4; | 1362 | goto fail_sp4; |
1259 | 1363 | ||
1260 | xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma; | 1364 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
1261 | for (i = 0; i < num_sp; i++) { | 1365 | for (i = 0; i < num_sp; i++) { |
1262 | dma_addr_t dma; | 1366 | dma_addr_t dma; |
1263 | void *buf = pci_alloc_consistent(to_pci_dev(dev), | 1367 | void *buf = pci_alloc_consistent(to_pci_dev(dev), |
@@ -1441,8 +1545,17 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci) | |||
1441 | xhci->dcbaa = NULL; | 1545 | xhci->dcbaa = NULL; |
1442 | 1546 | ||
1443 | scratchpad_free(xhci); | 1547 | scratchpad_free(xhci); |
1548 | |||
1549 | xhci->num_usb2_ports = 0; | ||
1550 | xhci->num_usb3_ports = 0; | ||
1551 | kfree(xhci->usb2_ports); | ||
1552 | kfree(xhci->usb3_ports); | ||
1553 | kfree(xhci->port_array); | ||
1554 | |||
1444 | xhci->page_size = 0; | 1555 | xhci->page_size = 0; |
1445 | xhci->page_shift = 0; | 1556 | xhci->page_shift = 0; |
1557 | xhci->bus_state[0].bus_suspended = 0; | ||
1558 | xhci->bus_state[1].bus_suspended = 0; | ||
1446 | } | 1559 | } |
1447 | 1560 | ||
1448 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, | 1561 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
@@ -1624,6 +1737,184 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) | |||
1624 | &xhci->ir_set->erst_dequeue); | 1737 | &xhci->ir_set->erst_dequeue); |
1625 | } | 1738 | } |
1626 | 1739 | ||
1740 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, | ||
1741 | __le32 __iomem *addr, u8 major_revision) | ||
1742 | { | ||
1743 | u32 temp, port_offset, port_count; | ||
1744 | int i; | ||
1745 | |||
1746 | if (major_revision > 0x03) { | ||
1747 | xhci_warn(xhci, "Ignoring unknown port speed, " | ||
1748 | "Ext Cap %p, revision = 0x%x\n", | ||
1749 | addr, major_revision); | ||
1750 | /* Ignoring port protocol we can't understand. FIXME */ | ||
1751 | return; | ||
1752 | } | ||
1753 | |||
1754 | /* Port offset and count in the third dword, see section 7.2 */ | ||
1755 | temp = xhci_readl(xhci, addr + 2); | ||
1756 | port_offset = XHCI_EXT_PORT_OFF(temp); | ||
1757 | port_count = XHCI_EXT_PORT_COUNT(temp); | ||
1758 | xhci_dbg(xhci, "Ext Cap %p, port offset = %u, " | ||
1759 | "count = %u, revision = 0x%x\n", | ||
1760 | addr, port_offset, port_count, major_revision); | ||
1761 | /* Port count includes the current port offset */ | ||
1762 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | ||
1763 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | ||
1764 | return; | ||
1765 | port_offset--; | ||
1766 | for (i = port_offset; i < (port_offset + port_count); i++) { | ||
1767 | /* Duplicate entry. Ignore the port if the revisions differ. */ | ||
1768 | if (xhci->port_array[i] != 0) { | ||
1769 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | ||
1770 | " port %u\n", addr, i); | ||
1771 | xhci_warn(xhci, "Port was marked as USB %u, " | ||
1772 | "duplicated as USB %u\n", | ||
1773 | xhci->port_array[i], major_revision); | ||
1774 | /* Only adjust the roothub port counts if we haven't | ||
1775 | * found a similar duplicate. | ||
1776 | */ | ||
1777 | if (xhci->port_array[i] != major_revision && | ||
1778 | xhci->port_array[i] != DUPLICATE_ENTRY) { | ||
1779 | if (xhci->port_array[i] == 0x03) | ||
1780 | xhci->num_usb3_ports--; | ||
1781 | else | ||
1782 | xhci->num_usb2_ports--; | ||
1783 | xhci->port_array[i] = DUPLICATE_ENTRY; | ||
1784 | } | ||
1785 | /* FIXME: Should we disable the port? */ | ||
1786 | continue; | ||
1787 | } | ||
1788 | xhci->port_array[i] = major_revision; | ||
1789 | if (major_revision == 0x03) | ||
1790 | xhci->num_usb3_ports++; | ||
1791 | else | ||
1792 | xhci->num_usb2_ports++; | ||
1793 | } | ||
1794 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | ||
1795 | } | ||
1796 | |||
1797 | /* | ||
1798 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | ||
1799 | * specify what speeds each port is supposed to be. We can't count on the port | ||
1800 | * speed bits in the PORTSC register being correct until a device is connected, | ||
1801 | * but we need to set up the two fake roothubs with the correct number of USB | ||
1802 | * 3.0 and USB 2.0 ports at host controller initialization time. | ||
1803 | */ | ||
1804 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | ||
1805 | { | ||
1806 | __le32 __iomem *addr; | ||
1807 | u32 offset; | ||
1808 | unsigned int num_ports; | ||
1809 | int i, port_index; | ||
1810 | |||
1811 | addr = &xhci->cap_regs->hcc_params; | ||
1812 | offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr)); | ||
1813 | if (offset == 0) { | ||
1814 | xhci_err(xhci, "No Extended Capability registers, " | ||
1815 | "unable to set up roothub.\n"); | ||
1816 | return -ENODEV; | ||
1817 | } | ||
1818 | |||
1819 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | ||
1820 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | ||
1821 | if (!xhci->port_array) | ||
1822 | return -ENOMEM; | ||
1823 | |||
1824 | /* | ||
1825 | * For whatever reason, the first capability offset is from the | ||
1826 | * capability register base, not from the HCCPARAMS register. | ||
1827 | * See section 5.3.6 for offset calculation. | ||
1828 | */ | ||
1829 | addr = &xhci->cap_regs->hc_capbase + offset; | ||
1830 | while (1) { | ||
1831 | u32 cap_id; | ||
1832 | |||
1833 | cap_id = xhci_readl(xhci, addr); | ||
1834 | if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) | ||
1835 | xhci_add_in_port(xhci, num_ports, addr, | ||
1836 | (u8) XHCI_EXT_PORT_MAJOR(cap_id)); | ||
1837 | offset = XHCI_EXT_CAPS_NEXT(cap_id); | ||
1838 | if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports) | ||
1839 | == num_ports) | ||
1840 | break; | ||
1841 | /* | ||
1842 | * Once you're into the Extended Capabilities, the offset is | ||
1843 | * always relative to the register holding the offset. | ||
1844 | */ | ||
1845 | addr += offset; | ||
1846 | } | ||
1847 | |||
1848 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | ||
1849 | xhci_warn(xhci, "No ports on the roothubs?\n"); | ||
1850 | return -ENODEV; | ||
1851 | } | ||
1852 | xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n", | ||
1853 | xhci->num_usb2_ports, xhci->num_usb3_ports); | ||
1854 | |||
1855 | /* Place limits on the number of roothub ports so that the hub | ||
1856 | * descriptors aren't longer than the USB core will allocate. | ||
1857 | */ | ||
1858 | if (xhci->num_usb3_ports > 15) { | ||
1859 | xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n"); | ||
1860 | xhci->num_usb3_ports = 15; | ||
1861 | } | ||
1862 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | ||
1863 | xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n", | ||
1864 | USB_MAXCHILDREN); | ||
1865 | xhci->num_usb2_ports = USB_MAXCHILDREN; | ||
1866 | } | ||
1867 | |||
1868 | /* | ||
1869 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | ||
1870 | * Not sure how the USB core will handle a hub with no ports... | ||
1871 | */ | ||
1872 | if (xhci->num_usb2_ports) { | ||
1873 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | ||
1874 | xhci->num_usb2_ports, flags); | ||
1875 | if (!xhci->usb2_ports) | ||
1876 | return -ENOMEM; | ||
1877 | |||
1878 | port_index = 0; | ||
1879 | for (i = 0; i < num_ports; i++) { | ||
1880 | if (xhci->port_array[i] == 0x03 || | ||
1881 | xhci->port_array[i] == 0 || | ||
1882 | xhci->port_array[i] == DUPLICATE_ENTRY) | ||
1883 | continue; | ||
1884 | |||
1885 | xhci->usb2_ports[port_index] = | ||
1886 | &xhci->op_regs->port_status_base + | ||
1887 | NUM_PORT_REGS*i; | ||
1888 | xhci_dbg(xhci, "USB 2.0 port at index %u, " | ||
1889 | "addr = %p\n", i, | ||
1890 | xhci->usb2_ports[port_index]); | ||
1891 | port_index++; | ||
1892 | if (port_index == xhci->num_usb2_ports) | ||
1893 | break; | ||
1894 | } | ||
1895 | } | ||
1896 | if (xhci->num_usb3_ports) { | ||
1897 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | ||
1898 | xhci->num_usb3_ports, flags); | ||
1899 | if (!xhci->usb3_ports) | ||
1900 | return -ENOMEM; | ||
1901 | |||
1902 | port_index = 0; | ||
1903 | for (i = 0; i < num_ports; i++) | ||
1904 | if (xhci->port_array[i] == 0x03) { | ||
1905 | xhci->usb3_ports[port_index] = | ||
1906 | &xhci->op_regs->port_status_base + | ||
1907 | NUM_PORT_REGS*i; | ||
1908 | xhci_dbg(xhci, "USB 3.0 port at index %u, " | ||
1909 | "addr = %p\n", i, | ||
1910 | xhci->usb3_ports[port_index]); | ||
1911 | port_index++; | ||
1912 | if (port_index == xhci->num_usb3_ports) | ||
1913 | break; | ||
1914 | } | ||
1915 | } | ||
1916 | return 0; | ||
1917 | } | ||
1627 | 1918 | ||
1628 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | 1919 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
1629 | { | 1920 | { |
@@ -1730,11 +2021,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
1730 | val &= DBOFF_MASK; | 2021 | val &= DBOFF_MASK; |
1731 | xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x" | 2022 | xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x" |
1732 | " from cap regs base addr\n", val); | 2023 | " from cap regs base addr\n", val); |
1733 | xhci->dba = (void *) xhci->cap_regs + val; | 2024 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
1734 | xhci_dbg_regs(xhci); | 2025 | xhci_dbg_regs(xhci); |
1735 | xhci_print_run_regs(xhci); | 2026 | xhci_print_run_regs(xhci); |
1736 | /* Set ir_set to interrupt register set 0 */ | 2027 | /* Set ir_set to interrupt register set 0 */ |
1737 | xhci->ir_set = (void *) xhci->run_regs->ir_set; | 2028 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
1738 | 2029 | ||
1739 | /* | 2030 | /* |
1740 | * Event ring setup: Allocate a normal ring, but also setup | 2031 | * Event ring setup: Allocate a normal ring, but also setup |
@@ -1765,8 +2056,8 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
1765 | /* set ring base address and size for each segment table entry */ | 2056 | /* set ring base address and size for each segment table entry */ |
1766 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | 2057 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { |
1767 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | 2058 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; |
1768 | entry->seg_addr = seg->dma; | 2059 | entry->seg_addr = cpu_to_le64(seg->dma); |
1769 | entry->seg_size = TRBS_PER_SEGMENT; | 2060 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); |
1770 | entry->rsvd = 0; | 2061 | entry->rsvd = 0; |
1771 | seg = seg->next; | 2062 | seg = seg->next; |
1772 | } | 2063 | } |
@@ -1791,7 +2082,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
1791 | /* Set the event ring dequeue address */ | 2082 | /* Set the event ring dequeue address */ |
1792 | xhci_set_hc_event_deq(xhci); | 2083 | xhci_set_hc_event_deq(xhci); |
1793 | xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n"); | 2084 | xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n"); |
1794 | xhci_print_ir_set(xhci, xhci->ir_set, 0); | 2085 | xhci_print_ir_set(xhci, 0); |
1795 | 2086 | ||
1796 | /* | 2087 | /* |
1797 | * XXX: Might need to set the Interrupter Moderation Register to | 2088 | * XXX: Might need to set the Interrupter Moderation Register to |
@@ -1801,9 +2092,15 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
1801 | init_completion(&xhci->addr_dev); | 2092 | init_completion(&xhci->addr_dev); |
1802 | for (i = 0; i < MAX_HC_SLOTS; ++i) | 2093 | for (i = 0; i < MAX_HC_SLOTS; ++i) |
1803 | xhci->devs[i] = NULL; | 2094 | xhci->devs[i] = NULL; |
2095 | for (i = 0; i < USB_MAXCHILDREN; ++i) { | ||
2096 | xhci->bus_state[0].resume_done[i] = 0; | ||
2097 | xhci->bus_state[1].resume_done[i] = 0; | ||
2098 | } | ||
1804 | 2099 | ||
1805 | if (scratchpad_alloc(xhci, flags)) | 2100 | if (scratchpad_alloc(xhci, flags)) |
1806 | goto fail; | 2101 | goto fail; |
2102 | if (xhci_setup_port_arrays(xhci, flags)) | ||
2103 | goto fail; | ||
1807 | 2104 | ||
1808 | return 0; | 2105 | return 0; |
1809 | 2106 | ||
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index f7efe025beda..cb16de213f64 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c | |||
@@ -21,6 +21,7 @@ | |||
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include <linux/pci.h> | 23 | #include <linux/pci.h> |
24 | #include <linux/slab.h> | ||
24 | 25 | ||
25 | #include "xhci.h" | 26 | #include "xhci.h" |
26 | 27 | ||
@@ -28,6 +29,9 @@ | |||
28 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | 29 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 |
29 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | 30 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 |
30 | 31 | ||
32 | #define PCI_VENDOR_ID_ETRON 0x1b6f | ||
33 | #define PCI_DEVICE_ID_ASROCK_P67 0x7023 | ||
34 | |||
31 | static const char hcd_name[] = "xhci_hcd"; | 35 | static const char hcd_name[] = "xhci_hcd"; |
32 | 36 | ||
33 | /* called after powerup, by probe or system-pm "wakeup" */ | 37 | /* called after powerup, by probe or system-pm "wakeup" */ |
@@ -50,13 +54,45 @@ static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |||
50 | /* called during probe() after chip reset completes */ | 54 | /* called during probe() after chip reset completes */ |
51 | static int xhci_pci_setup(struct usb_hcd *hcd) | 55 | static int xhci_pci_setup(struct usb_hcd *hcd) |
52 | { | 56 | { |
53 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | 57 | struct xhci_hcd *xhci; |
54 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | 58 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
55 | int retval; | 59 | int retval; |
56 | u32 temp; | 60 | u32 temp; |
57 | 61 | ||
58 | hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2; | 62 | hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2; |
59 | 63 | ||
64 | if (usb_hcd_is_primary_hcd(hcd)) { | ||
65 | xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL); | ||
66 | if (!xhci) | ||
67 | return -ENOMEM; | ||
68 | *((struct xhci_hcd **) hcd->hcd_priv) = xhci; | ||
69 | xhci->main_hcd = hcd; | ||
70 | /* Mark the first roothub as being USB 2.0. | ||
71 | * The xHCI driver will register the USB 3.0 roothub. | ||
72 | */ | ||
73 | hcd->speed = HCD_USB2; | ||
74 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | ||
75 | /* | ||
76 | * USB 2.0 roothub under xHCI has an integrated TT, | ||
77 | * (rate matching hub) as opposed to having an OHCI/UHCI | ||
78 | * companion controller. | ||
79 | */ | ||
80 | hcd->has_tt = 1; | ||
81 | } else { | ||
82 | /* xHCI private pointer was set in xhci_pci_probe for the second | ||
83 | * registered roothub. | ||
84 | */ | ||
85 | xhci = hcd_to_xhci(hcd); | ||
86 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | ||
87 | if (HCC_64BIT_ADDR(temp)) { | ||
88 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); | ||
89 | dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)); | ||
90 | } else { | ||
91 | dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32)); | ||
92 | } | ||
93 | return 0; | ||
94 | } | ||
95 | |||
60 | xhci->cap_regs = hcd->regs; | 96 | xhci->cap_regs = hcd->regs; |
61 | xhci->op_regs = hcd->regs + | 97 | xhci->op_regs = hcd->regs + |
62 | HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase)); | 98 | HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase)); |
@@ -73,25 +109,50 @@ static int xhci_pci_setup(struct usb_hcd *hcd) | |||
73 | 109 | ||
74 | /* Look for vendor-specific quirks */ | 110 | /* Look for vendor-specific quirks */ |
75 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | 111 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
76 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | 112 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) { |
77 | pdev->revision == 0x0) { | 113 | if (pdev->revision == 0x0) { |
78 | xhci->quirks |= XHCI_RESET_EP_QUIRK; | 114 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
79 | xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" | 115 | xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" |
80 | " endpoint cmd after reset endpoint\n"); | 116 | " endpoint cmd after reset endpoint\n"); |
117 | } | ||
118 | /* Fresco Logic confirms: all revisions of this chip do not | ||
119 | * support MSI, even though some of them claim to in their PCI | ||
120 | * capabilities. | ||
121 | */ | ||
122 | xhci->quirks |= XHCI_BROKEN_MSI; | ||
123 | xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " | ||
124 | "has broken MSI implementation\n", | ||
125 | pdev->revision); | ||
81 | } | 126 | } |
127 | |||
82 | if (pdev->vendor == PCI_VENDOR_ID_NEC) | 128 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
83 | xhci->quirks |= XHCI_NEC_HOST; | 129 | xhci->quirks |= XHCI_NEC_HOST; |
84 | 130 | ||
131 | /* AMD PLL quirk */ | ||
132 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | ||
133 | xhci->quirks |= XHCI_AMD_PLL_FIX; | ||
134 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && | ||
135 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | ||
136 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | ||
137 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; | ||
138 | xhci->limit_active_eps = 64; | ||
139 | } | ||
140 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && | ||
141 | pdev->device == PCI_DEVICE_ID_ASROCK_P67) { | ||
142 | xhci->quirks |= XHCI_RESET_ON_RESUME; | ||
143 | xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); | ||
144 | } | ||
145 | |||
85 | /* Make sure the HC is halted. */ | 146 | /* Make sure the HC is halted. */ |
86 | retval = xhci_halt(xhci); | 147 | retval = xhci_halt(xhci); |
87 | if (retval) | 148 | if (retval) |
88 | return retval; | 149 | goto error; |
89 | 150 | ||
90 | xhci_dbg(xhci, "Resetting HCD\n"); | 151 | xhci_dbg(xhci, "Resetting HCD\n"); |
91 | /* Reset the internal HC memory state and registers. */ | 152 | /* Reset the internal HC memory state and registers. */ |
92 | retval = xhci_reset(xhci); | 153 | retval = xhci_reset(xhci); |
93 | if (retval) | 154 | if (retval) |
94 | return retval; | 155 | goto error; |
95 | xhci_dbg(xhci, "Reset complete\n"); | 156 | xhci_dbg(xhci, "Reset complete\n"); |
96 | 157 | ||
97 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | 158 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); |
@@ -106,33 +167,152 @@ static int xhci_pci_setup(struct usb_hcd *hcd) | |||
106 | /* Initialize HCD and host controller data structures. */ | 167 | /* Initialize HCD and host controller data structures. */ |
107 | retval = xhci_init(hcd); | 168 | retval = xhci_init(hcd); |
108 | if (retval) | 169 | if (retval) |
109 | return retval; | 170 | goto error; |
110 | xhci_dbg(xhci, "Called HCD init\n"); | 171 | xhci_dbg(xhci, "Called HCD init\n"); |
111 | 172 | ||
112 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | 173 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); |
113 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); | 174 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); |
114 | 175 | ||
115 | /* Find any debug ports */ | 176 | /* Find any debug ports */ |
116 | return xhci_pci_reinit(xhci, pdev); | 177 | retval = xhci_pci_reinit(xhci, pdev); |
178 | if (!retval) | ||
179 | return retval; | ||
180 | |||
181 | error: | ||
182 | kfree(xhci); | ||
183 | return retval; | ||
117 | } | 184 | } |
118 | 185 | ||
186 | /* | ||
187 | * We need to register our own PCI probe function (instead of the USB core's | ||
188 | * function) in order to create a second roothub under xHCI. | ||
189 | */ | ||
190 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | ||
191 | { | ||
192 | int retval; | ||
193 | struct xhci_hcd *xhci; | ||
194 | struct hc_driver *driver; | ||
195 | struct usb_hcd *hcd; | ||
196 | |||
197 | driver = (struct hc_driver *)id->driver_data; | ||
198 | /* Register the USB 2.0 roothub. | ||
199 | * FIXME: USB core must know to register the USB 2.0 roothub first. | ||
200 | * This is sort of silly, because we could just set the HCD driver flags | ||
201 | * to say USB 2.0, but I'm not sure what the implications would be in | ||
202 | * the other parts of the HCD code. | ||
203 | */ | ||
204 | retval = usb_hcd_pci_probe(dev, id); | ||
205 | |||
206 | if (retval) | ||
207 | return retval; | ||
208 | |||
209 | /* USB 2.0 roothub is stored in the PCI device now. */ | ||
210 | hcd = dev_get_drvdata(&dev->dev); | ||
211 | xhci = hcd_to_xhci(hcd); | ||
212 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | ||
213 | pci_name(dev), hcd); | ||
214 | if (!xhci->shared_hcd) { | ||
215 | retval = -ENOMEM; | ||
216 | goto dealloc_usb2_hcd; | ||
217 | } | ||
218 | |||
219 | /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) | ||
220 | * is called by usb_add_hcd(). | ||
221 | */ | ||
222 | *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; | ||
223 | |||
224 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, | ||
225 | IRQF_DISABLED | IRQF_SHARED); | ||
226 | if (retval) | ||
227 | goto put_usb3_hcd; | ||
228 | /* Roothub already marked as USB 3.0 speed */ | ||
229 | return 0; | ||
230 | |||
231 | put_usb3_hcd: | ||
232 | usb_put_hcd(xhci->shared_hcd); | ||
233 | dealloc_usb2_hcd: | ||
234 | usb_hcd_pci_remove(dev); | ||
235 | return retval; | ||
236 | } | ||
237 | |||
238 | static void xhci_pci_remove(struct pci_dev *dev) | ||
239 | { | ||
240 | struct xhci_hcd *xhci; | ||
241 | |||
242 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | ||
243 | if (xhci->shared_hcd) { | ||
244 | usb_remove_hcd(xhci->shared_hcd); | ||
245 | usb_put_hcd(xhci->shared_hcd); | ||
246 | } | ||
247 | usb_hcd_pci_remove(dev); | ||
248 | kfree(xhci); | ||
249 | } | ||
250 | |||
251 | #ifdef CONFIG_PM | ||
252 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | ||
253 | { | ||
254 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | ||
255 | int retval = 0; | ||
256 | |||
257 | if (hcd->state != HC_STATE_SUSPENDED || | ||
258 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | ||
259 | return -EINVAL; | ||
260 | |||
261 | retval = xhci_suspend(xhci); | ||
262 | |||
263 | return retval; | ||
264 | } | ||
265 | |||
266 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | ||
267 | { | ||
268 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | ||
269 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | ||
270 | int retval = 0; | ||
271 | |||
272 | /* The BIOS on systems with the Intel Panther Point chipset may or may | ||
273 | * not support xHCI natively. That means that during system resume, it | ||
274 | * may switch the ports back to EHCI so that users can use their | ||
275 | * keyboard to select a kernel from GRUB after resume from hibernate. | ||
276 | * | ||
277 | * The BIOS is supposed to remember whether the OS had xHCI ports | ||
278 | * enabled before resume, and switch the ports back to xHCI when the | ||
279 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | ||
280 | * writers. | ||
281 | * | ||
282 | * Unconditionally switch the ports back to xHCI after a system resume. | ||
283 | * We can't tell whether the EHCI or xHCI controller will be resumed | ||
284 | * first, so we have to do the port switchover in both drivers. Writing | ||
285 | * a '1' to the port switchover registers should have no effect if the | ||
286 | * port was already switched over. | ||
287 | */ | ||
288 | if (usb_is_intel_switchable_xhci(pdev)) | ||
289 | usb_enable_xhci_ports(pdev); | ||
290 | |||
291 | retval = xhci_resume(xhci, hibernated); | ||
292 | return retval; | ||
293 | } | ||
294 | #endif /* CONFIG_PM */ | ||
295 | |||
119 | static const struct hc_driver xhci_pci_hc_driver = { | 296 | static const struct hc_driver xhci_pci_hc_driver = { |
120 | .description = hcd_name, | 297 | .description = hcd_name, |
121 | .product_desc = "xHCI Host Controller", | 298 | .product_desc = "xHCI Host Controller", |
122 | .hcd_priv_size = sizeof(struct xhci_hcd), | 299 | .hcd_priv_size = sizeof(struct xhci_hcd *), |
123 | 300 | ||
124 | /* | 301 | /* |
125 | * generic hardware linkage | 302 | * generic hardware linkage |
126 | */ | 303 | */ |
127 | .irq = xhci_irq, | 304 | .irq = xhci_irq, |
128 | .flags = HCD_MEMORY | HCD_USB3, | 305 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, |
129 | 306 | ||
130 | /* | 307 | /* |
131 | * basic lifecycle operations | 308 | * basic lifecycle operations |
132 | */ | 309 | */ |
133 | .reset = xhci_pci_setup, | 310 | .reset = xhci_pci_setup, |
134 | .start = xhci_run, | 311 | .start = xhci_run, |
135 | /* suspend and resume implemented later */ | 312 | #ifdef CONFIG_PM |
313 | .pci_suspend = xhci_pci_suspend, | ||
314 | .pci_resume = xhci_pci_resume, | ||
315 | #endif | ||
136 | .stop = xhci_stop, | 316 | .stop = xhci_stop, |
137 | .shutdown = xhci_shutdown, | 317 | .shutdown = xhci_shutdown, |
138 | 318 | ||
@@ -152,7 +332,7 @@ static const struct hc_driver xhci_pci_hc_driver = { | |||
152 | .reset_bandwidth = xhci_reset_bandwidth, | 332 | .reset_bandwidth = xhci_reset_bandwidth, |
153 | .address_device = xhci_address_device, | 333 | .address_device = xhci_address_device, |
154 | .update_hub_device = xhci_update_hub_device, | 334 | .update_hub_device = xhci_update_hub_device, |
155 | .reset_device = xhci_reset_device, | 335 | .reset_device = xhci_discover_or_reset_device, |
156 | 336 | ||
157 | /* | 337 | /* |
158 | * scheduling support | 338 | * scheduling support |
@@ -162,6 +342,8 @@ static const struct hc_driver xhci_pci_hc_driver = { | |||
162 | /* Root hub support */ | 342 | /* Root hub support */ |
163 | .hub_control = xhci_hub_control, | 343 | .hub_control = xhci_hub_control, |
164 | .hub_status_data = xhci_hub_status_data, | 344 | .hub_status_data = xhci_hub_status_data, |
345 | .bus_suspend = xhci_bus_suspend, | ||
346 | .bus_resume = xhci_bus_resume, | ||
165 | }; | 347 | }; |
166 | 348 | ||
167 | /*-------------------------------------------------------------------------*/ | 349 | /*-------------------------------------------------------------------------*/ |
@@ -181,11 +363,16 @@ static struct pci_driver xhci_pci_driver = { | |||
181 | .name = (char *) hcd_name, | 363 | .name = (char *) hcd_name, |
182 | .id_table = pci_ids, | 364 | .id_table = pci_ids, |
183 | 365 | ||
184 | .probe = usb_hcd_pci_probe, | 366 | .probe = xhci_pci_probe, |
185 | .remove = usb_hcd_pci_remove, | 367 | .remove = xhci_pci_remove, |
186 | /* suspend and resume implemented later */ | 368 | /* suspend and resume implemented later */ |
187 | 369 | ||
188 | .shutdown = usb_hcd_pci_shutdown, | 370 | .shutdown = usb_hcd_pci_shutdown, |
371 | #ifdef CONFIG_PM_SLEEP | ||
372 | .driver = { | ||
373 | .pm = &usb_hcd_pci_pm_ops | ||
374 | }, | ||
375 | #endif | ||
189 | }; | 376 | }; |
190 | 377 | ||
191 | int xhci_register_pci(void) | 378 | int xhci_register_pci(void) |
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 48e60d166ff0..70cacbbe7fb9 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c | |||
@@ -68,6 +68,10 @@ | |||
68 | #include <linux/slab.h> | 68 | #include <linux/slab.h> |
69 | #include "xhci.h" | 69 | #include "xhci.h" |
70 | 70 | ||
71 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | ||
72 | struct xhci_virt_device *virt_dev, | ||
73 | struct xhci_event_cmd *event); | ||
74 | |||
71 | /* | 75 | /* |
72 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | 76 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA |
73 | * address of the TRB. | 77 | * address of the TRB. |
@@ -89,33 +93,35 @@ dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, | |||
89 | /* Does this link TRB point to the first segment in a ring, | 93 | /* Does this link TRB point to the first segment in a ring, |
90 | * or was the previous TRB the last TRB on the last segment in the ERST? | 94 | * or was the previous TRB the last TRB on the last segment in the ERST? |
91 | */ | 95 | */ |
92 | static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, | 96 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
93 | struct xhci_segment *seg, union xhci_trb *trb) | 97 | struct xhci_segment *seg, union xhci_trb *trb) |
94 | { | 98 | { |
95 | if (ring == xhci->event_ring) | 99 | if (ring == xhci->event_ring) |
96 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | 100 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && |
97 | (seg->next == xhci->event_ring->first_seg); | 101 | (seg->next == xhci->event_ring->first_seg); |
98 | else | 102 | else |
99 | return trb->link.control & LINK_TOGGLE; | 103 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
100 | } | 104 | } |
101 | 105 | ||
102 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | 106 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring |
103 | * segment? I.e. would the updated event TRB pointer step off the end of the | 107 | * segment? I.e. would the updated event TRB pointer step off the end of the |
104 | * event seg? | 108 | * event seg? |
105 | */ | 109 | */ |
106 | static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | 110 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
107 | struct xhci_segment *seg, union xhci_trb *trb) | 111 | struct xhci_segment *seg, union xhci_trb *trb) |
108 | { | 112 | { |
109 | if (ring == xhci->event_ring) | 113 | if (ring == xhci->event_ring) |
110 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | 114 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; |
111 | else | 115 | else |
112 | return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); | 116 | return (le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK) |
117 | == TRB_TYPE(TRB_LINK); | ||
113 | } | 118 | } |
114 | 119 | ||
115 | static inline int enqueue_is_link_trb(struct xhci_ring *ring) | 120 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
116 | { | 121 | { |
117 | struct xhci_link_trb *link = &ring->enqueue->link; | 122 | struct xhci_link_trb *link = &ring->enqueue->link; |
118 | return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)); | 123 | return ((le32_to_cpu(link->control) & TRB_TYPE_BITMASK) == |
124 | TRB_TYPE(TRB_LINK)); | ||
119 | } | 125 | } |
120 | 126 | ||
121 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next | 127 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
@@ -161,12 +167,6 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer | |||
161 | next = ring->dequeue; | 167 | next = ring->dequeue; |
162 | } | 168 | } |
163 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); | 169 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
164 | if (ring == xhci->event_ring) | ||
165 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); | ||
166 | else if (ring == xhci->cmd_ring) | ||
167 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); | ||
168 | else | ||
169 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); | ||
170 | } | 170 | } |
171 | 171 | ||
172 | /* | 172 | /* |
@@ -193,7 +193,7 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, | |||
193 | union xhci_trb *next; | 193 | union xhci_trb *next; |
194 | unsigned long long addr; | 194 | unsigned long long addr; |
195 | 195 | ||
196 | chain = ring->enqueue->generic.field[3] & TRB_CHAIN; | 196 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
197 | next = ++(ring->enqueue); | 197 | next = ++(ring->enqueue); |
198 | 198 | ||
199 | ring->enq_updates++; | 199 | ring->enq_updates++; |
@@ -219,12 +219,14 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, | |||
219 | * (which may mean the chain bit is cleared). | 219 | * (which may mean the chain bit is cleared). |
220 | */ | 220 | */ |
221 | if (!xhci_link_trb_quirk(xhci)) { | 221 | if (!xhci_link_trb_quirk(xhci)) { |
222 | next->link.control &= ~TRB_CHAIN; | 222 | next->link.control &= |
223 | next->link.control |= chain; | 223 | cpu_to_le32(~TRB_CHAIN); |
224 | next->link.control |= | ||
225 | cpu_to_le32(chain); | ||
224 | } | 226 | } |
225 | /* Give this link TRB to the hardware */ | 227 | /* Give this link TRB to the hardware */ |
226 | wmb(); | 228 | wmb(); |
227 | next->link.control ^= TRB_CYCLE; | 229 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
228 | } | 230 | } |
229 | /* Toggle the cycle bit after the last ring segment. */ | 231 | /* Toggle the cycle bit after the last ring segment. */ |
230 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | 232 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { |
@@ -240,12 +242,6 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, | |||
240 | next = ring->enqueue; | 242 | next = ring->enqueue; |
241 | } | 243 | } |
242 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); | 244 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
243 | if (ring == xhci->event_ring) | ||
244 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); | ||
245 | else if (ring == xhci->cmd_ring) | ||
246 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); | ||
247 | else | ||
248 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); | ||
249 | } | 245 | } |
250 | 246 | ||
251 | /* | 247 | /* |
@@ -304,40 +300,35 @@ static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, | |||
304 | /* Ring the host controller doorbell after placing a command on the ring */ | 300 | /* Ring the host controller doorbell after placing a command on the ring */ |
305 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) | 301 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
306 | { | 302 | { |
307 | u32 temp; | ||
308 | |||
309 | xhci_dbg(xhci, "// Ding dong!\n"); | 303 | xhci_dbg(xhci, "// Ding dong!\n"); |
310 | temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK; | 304 | xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
311 | xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]); | ||
312 | /* Flush PCI posted writes */ | 305 | /* Flush PCI posted writes */ |
313 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | 306 | xhci_readl(xhci, &xhci->dba->doorbell[0]); |
314 | } | 307 | } |
315 | 308 | ||
316 | static void ring_ep_doorbell(struct xhci_hcd *xhci, | 309 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
317 | unsigned int slot_id, | 310 | unsigned int slot_id, |
318 | unsigned int ep_index, | 311 | unsigned int ep_index, |
319 | unsigned int stream_id) | 312 | unsigned int stream_id) |
320 | { | 313 | { |
321 | struct xhci_virt_ep *ep; | 314 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
322 | unsigned int ep_state; | 315 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
323 | u32 field; | 316 | unsigned int ep_state = ep->ep_state; |
324 | __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; | ||
325 | 317 | ||
326 | ep = &xhci->devs[slot_id]->eps[ep_index]; | ||
327 | ep_state = ep->ep_state; | ||
328 | /* Don't ring the doorbell for this endpoint if there are pending | 318 | /* Don't ring the doorbell for this endpoint if there are pending |
329 | * cancellations because the we don't want to interrupt processing. | 319 | * cancellations because we don't want to interrupt processing. |
330 | * We don't want to restart any stream rings if there's a set dequeue | 320 | * We don't want to restart any stream rings if there's a set dequeue |
331 | * pointer command pending because the device can choose to start any | 321 | * pointer command pending because the device can choose to start any |
332 | * stream once the endpoint is on the HW schedule. | 322 | * stream once the endpoint is on the HW schedule. |
333 | * FIXME - check all the stream rings for pending cancellations. | 323 | * FIXME - check all the stream rings for pending cancellations. |
334 | */ | 324 | */ |
335 | if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING) | 325 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
336 | && !(ep_state & EP_HALTED)) { | 326 | (ep_state & EP_HALTED)) |
337 | field = xhci_readl(xhci, db_addr) & DB_MASK; | 327 | return; |
338 | field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id); | 328 | xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); |
339 | xhci_writel(xhci, field, db_addr); | 329 | /* The CPU has better things to do at this point than wait for a |
340 | } | 330 | * write-posting flush. It'll get there soon enough. |
331 | */ | ||
341 | } | 332 | } |
342 | 333 | ||
343 | /* Ring the doorbell for any rings with pending URBs */ | 334 | /* Ring the doorbell for any rings with pending URBs */ |
@@ -353,7 +344,7 @@ static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |||
353 | /* A ring has pending URBs if its TD list is not empty */ | 344 | /* A ring has pending URBs if its TD list is not empty */ |
354 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | 345 | if (!(ep->ep_state & EP_HAS_STREAMS)) { |
355 | if (!(list_empty(&ep->ring->td_list))) | 346 | if (!(list_empty(&ep->ring->td_list))) |
356 | ring_ep_doorbell(xhci, slot_id, ep_index, 0); | 347 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
357 | return; | 348 | return; |
358 | } | 349 | } |
359 | 350 | ||
@@ -361,7 +352,8 @@ static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |||
361 | stream_id++) { | 352 | stream_id++) { |
362 | struct xhci_stream_info *stream_info = ep->stream_info; | 353 | struct xhci_stream_info *stream_info = ep->stream_info; |
363 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | 354 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) |
364 | ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); | 355 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
356 | stream_id); | ||
365 | } | 357 | } |
366 | } | 358 | } |
367 | 359 | ||
@@ -380,10 +372,8 @@ static struct xhci_segment *find_trb_seg( | |||
380 | while (cur_seg->trbs > trb || | 372 | while (cur_seg->trbs > trb || |
381 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | 373 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { |
382 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | 374 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; |
383 | if ((generic_trb->field[3] & TRB_TYPE_BITMASK) == | 375 | if (le32_to_cpu(generic_trb->field[3]) & LINK_TOGGLE) |
384 | TRB_TYPE(TRB_LINK) && | 376 | *cycle_state ^= 0x1; |
385 | (generic_trb->field[3] & LINK_TOGGLE)) | ||
386 | *cycle_state = ~(*cycle_state) & 0x1; | ||
387 | cur_seg = cur_seg->next; | 377 | cur_seg = cur_seg->next; |
388 | if (cur_seg == start_seg) | 378 | if (cur_seg == start_seg) |
389 | /* Looped over the entire list. Oops! */ | 379 | /* Looped over the entire list. Oops! */ |
@@ -449,6 +439,10 @@ static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |||
449 | * any link TRBs with the toggle cycle bit set. | 439 | * any link TRBs with the toggle cycle bit set. |
450 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | 440 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit |
451 | * if we've moved it past a link TRB with the toggle cycle bit set. | 441 | * if we've moved it past a link TRB with the toggle cycle bit set. |
442 | * | ||
443 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | ||
444 | * with correct __le32 accesses they should work fine. Only users of this are | ||
445 | * in here. | ||
452 | */ | 446 | */ |
453 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, | 447 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
454 | unsigned int slot_id, unsigned int ep_index, | 448 | unsigned int slot_id, unsigned int ep_index, |
@@ -474,36 +468,52 @@ void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, | |||
474 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, | 468 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
475 | dev->eps[ep_index].stopped_trb, | 469 | dev->eps[ep_index].stopped_trb, |
476 | &state->new_cycle_state); | 470 | &state->new_cycle_state); |
477 | if (!state->new_deq_seg) | 471 | if (!state->new_deq_seg) { |
478 | BUG(); | 472 | WARN_ON(1); |
473 | return; | ||
474 | } | ||
475 | |||
479 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ | 476 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
480 | xhci_dbg(xhci, "Finding endpoint context\n"); | 477 | xhci_dbg(xhci, "Finding endpoint context\n"); |
481 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | 478 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
482 | state->new_cycle_state = 0x1 & ep_ctx->deq; | 479 | state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq); |
483 | 480 | ||
484 | state->new_deq_ptr = cur_td->last_trb; | 481 | state->new_deq_ptr = cur_td->last_trb; |
485 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); | 482 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
486 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, | 483 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
487 | state->new_deq_ptr, | 484 | state->new_deq_ptr, |
488 | &state->new_cycle_state); | 485 | &state->new_cycle_state); |
489 | if (!state->new_deq_seg) | 486 | if (!state->new_deq_seg) { |
490 | BUG(); | 487 | WARN_ON(1); |
488 | return; | ||
489 | } | ||
491 | 490 | ||
492 | trb = &state->new_deq_ptr->generic; | 491 | trb = &state->new_deq_ptr->generic; |
493 | if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) && | 492 | if ((le32_to_cpu(trb->field[3]) & TRB_TYPE_BITMASK) == |
494 | (trb->field[3] & LINK_TOGGLE)) | 493 | TRB_TYPE(TRB_LINK) && (le32_to_cpu(trb->field[3]) & LINK_TOGGLE)) |
495 | state->new_cycle_state = ~(state->new_cycle_state) & 0x1; | 494 | state->new_cycle_state ^= 0x1; |
496 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); | 495 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
497 | 496 | ||
497 | /* | ||
498 | * If there is only one segment in a ring, find_trb_seg()'s while loop | ||
499 | * will not run, and it will return before it has a chance to see if it | ||
500 | * needs to toggle the cycle bit. It can't tell if the stalled transfer | ||
501 | * ended just before the link TRB on a one-segment ring, or if the TD | ||
502 | * wrapped around the top of the ring, because it doesn't have the TD in | ||
503 | * question. Look for the one-segment case where stalled TRB's address | ||
504 | * is greater than the new dequeue pointer address. | ||
505 | */ | ||
506 | if (ep_ring->first_seg == ep_ring->first_seg->next && | ||
507 | state->new_deq_ptr < dev->eps[ep_index].stopped_trb) | ||
508 | state->new_cycle_state ^= 0x1; | ||
509 | xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state); | ||
510 | |||
498 | /* Don't update the ring cycle state for the producer (us). */ | 511 | /* Don't update the ring cycle state for the producer (us). */ |
499 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", | 512 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
500 | state->new_deq_seg); | 513 | state->new_deq_seg); |
501 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | 514 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); |
502 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | 515 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", |
503 | (unsigned long long) addr); | 516 | (unsigned long long) addr); |
504 | xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); | ||
505 | ep_ring->dequeue = state->new_deq_ptr; | ||
506 | ep_ring->deq_seg = state->new_deq_seg; | ||
507 | } | 517 | } |
508 | 518 | ||
509 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | 519 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
@@ -515,12 +525,12 @@ static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |||
515 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | 525 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; |
516 | true; | 526 | true; |
517 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | 527 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
518 | if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == | 528 | if ((le32_to_cpu(cur_trb->generic.field[3]) & TRB_TYPE_BITMASK) |
519 | TRB_TYPE(TRB_LINK)) { | 529 | == TRB_TYPE(TRB_LINK)) { |
520 | /* Unchain any chained Link TRBs, but | 530 | /* Unchain any chained Link TRBs, but |
521 | * leave the pointers intact. | 531 | * leave the pointers intact. |
522 | */ | 532 | */ |
523 | cur_trb->generic.field[3] &= ~TRB_CHAIN; | 533 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
524 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); | 534 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); |
525 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " | 535 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
526 | "in seg %p (0x%llx dma)\n", | 536 | "in seg %p (0x%llx dma)\n", |
@@ -533,8 +543,9 @@ static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |||
533 | cur_trb->generic.field[1] = 0; | 543 | cur_trb->generic.field[1] = 0; |
534 | cur_trb->generic.field[2] = 0; | 544 | cur_trb->generic.field[2] = 0; |
535 | /* Preserve only the cycle bit of this TRB */ | 545 | /* Preserve only the cycle bit of this TRB */ |
536 | cur_trb->generic.field[3] &= TRB_CYCLE; | 546 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
537 | cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); | 547 | cur_trb->generic.field[3] |= cpu_to_le32( |
548 | TRB_TYPE(TRB_TR_NOOP)); | ||
538 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " | 549 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
539 | "in seg %p (0x%llx dma)\n", | 550 | "in seg %p (0x%llx dma)\n", |
540 | cur_trb, | 551 | cur_trb, |
@@ -578,7 +589,7 @@ void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |||
578 | ep->ep_state |= SET_DEQ_PENDING; | 589 | ep->ep_state |= SET_DEQ_PENDING; |
579 | } | 590 | } |
580 | 591 | ||
581 | static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, | 592 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
582 | struct xhci_virt_ep *ep) | 593 | struct xhci_virt_ep *ep) |
583 | { | 594 | { |
584 | ep->ep_state &= ~EP_HALT_PENDING; | 595 | ep->ep_state &= ~EP_HALT_PENDING; |
@@ -594,24 +605,30 @@ static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, | |||
594 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | 605 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
595 | struct xhci_td *cur_td, int status, char *adjective) | 606 | struct xhci_td *cur_td, int status, char *adjective) |
596 | { | 607 | { |
597 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | 608 | struct usb_hcd *hcd; |
598 | struct urb *urb; | 609 | struct urb *urb; |
599 | struct urb_priv *urb_priv; | 610 | struct urb_priv *urb_priv; |
600 | 611 | ||
601 | urb = cur_td->urb; | 612 | urb = cur_td->urb; |
602 | urb_priv = urb->hcpriv; | 613 | urb_priv = urb->hcpriv; |
603 | urb_priv->td_cnt++; | 614 | urb_priv->td_cnt++; |
615 | hcd = bus_to_hcd(urb->dev->bus); | ||
604 | 616 | ||
605 | /* Only giveback urb when this is the last td in urb */ | 617 | /* Only giveback urb when this is the last td in urb */ |
606 | if (urb_priv->td_cnt == urb_priv->length) { | 618 | if (urb_priv->td_cnt == urb_priv->length) { |
619 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | ||
620 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | ||
621 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | ||
622 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | ||
623 | usb_amd_quirk_pll_enable(); | ||
624 | } | ||
625 | } | ||
607 | usb_hcd_unlink_urb_from_ep(hcd, urb); | 626 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
608 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb); | ||
609 | 627 | ||
610 | spin_unlock(&xhci->lock); | 628 | spin_unlock(&xhci->lock); |
611 | usb_hcd_giveback_urb(hcd, urb, status); | 629 | usb_hcd_giveback_urb(hcd, urb, status); |
612 | xhci_urb_free_priv(xhci, urb_priv); | 630 | xhci_urb_free_priv(xhci, urb_priv); |
613 | spin_lock(&xhci->lock); | 631 | spin_lock(&xhci->lock); |
614 | xhci_dbg(xhci, "%s URB given back\n", adjective); | ||
615 | } | 632 | } |
616 | } | 633 | } |
617 | 634 | ||
@@ -626,10 +643,11 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |||
626 | * bit cleared) so that the HW will skip over them. | 643 | * bit cleared) so that the HW will skip over them. |
627 | */ | 644 | */ |
628 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | 645 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, |
629 | union xhci_trb *trb) | 646 | union xhci_trb *trb, struct xhci_event_cmd *event) |
630 | { | 647 | { |
631 | unsigned int slot_id; | 648 | unsigned int slot_id; |
632 | unsigned int ep_index; | 649 | unsigned int ep_index; |
650 | struct xhci_virt_device *virt_dev; | ||
633 | struct xhci_ring *ep_ring; | 651 | struct xhci_ring *ep_ring; |
634 | struct xhci_virt_ep *ep; | 652 | struct xhci_virt_ep *ep; |
635 | struct list_head *entry; | 653 | struct list_head *entry; |
@@ -638,13 +656,30 @@ static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |||
638 | 656 | ||
639 | struct xhci_dequeue_state deq_state; | 657 | struct xhci_dequeue_state deq_state; |
640 | 658 | ||
659 | if (unlikely(TRB_TO_SUSPEND_PORT( | ||
660 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) { | ||
661 | slot_id = TRB_TO_SLOT_ID( | ||
662 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); | ||
663 | virt_dev = xhci->devs[slot_id]; | ||
664 | if (virt_dev) | ||
665 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, | ||
666 | event); | ||
667 | else | ||
668 | xhci_warn(xhci, "Stop endpoint command " | ||
669 | "completion for disabled slot %u\n", | ||
670 | slot_id); | ||
671 | return; | ||
672 | } | ||
673 | |||
641 | memset(&deq_state, 0, sizeof(deq_state)); | 674 | memset(&deq_state, 0, sizeof(deq_state)); |
642 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | 675 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
643 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | 676 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
644 | ep = &xhci->devs[slot_id]->eps[ep_index]; | 677 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
645 | 678 | ||
646 | if (list_empty(&ep->cancelled_td_list)) { | 679 | if (list_empty(&ep->cancelled_td_list)) { |
647 | xhci_stop_watchdog_timer_in_irq(xhci, ep); | 680 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
681 | ep->stopped_td = NULL; | ||
682 | ep->stopped_trb = NULL; | ||
648 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | 683 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
649 | return; | 684 | return; |
650 | } | 685 | } |
@@ -803,8 +838,7 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |||
803 | if (ret < 0) { | 838 | if (ret < 0) { |
804 | /* This is bad; the host is not responding to commands and it's | 839 | /* This is bad; the host is not responding to commands and it's |
805 | * not allowing itself to be halted. At least interrupts are | 840 | * not allowing itself to be halted. At least interrupts are |
806 | * disabled, so we can set HC_STATE_HALT and notify the | 841 | * disabled. If we call usb_hc_died(), it will attempt to |
807 | * USB core. But if we call usb_hc_died(), it will attempt to | ||
808 | * disconnect all device drivers under this host. Those | 842 | * disconnect all device drivers under this host. Those |
809 | * disconnect() methods will wait for all URBs to be unlinked, | 843 | * disconnect() methods will wait for all URBs to be unlinked, |
810 | * so we must complete them. | 844 | * so we must complete them. |
@@ -849,9 +883,8 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |||
849 | } | 883 | } |
850 | } | 884 | } |
851 | spin_unlock(&xhci->lock); | 885 | spin_unlock(&xhci->lock); |
852 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | ||
853 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); | 886 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); |
854 | usb_hc_died(xhci_to_hcd(xhci)); | 887 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
855 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | 888 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); |
856 | } | 889 | } |
857 | 890 | ||
@@ -874,9 +907,9 @@ static void handle_set_deq_completion(struct xhci_hcd *xhci, | |||
874 | struct xhci_ep_ctx *ep_ctx; | 907 | struct xhci_ep_ctx *ep_ctx; |
875 | struct xhci_slot_ctx *slot_ctx; | 908 | struct xhci_slot_ctx *slot_ctx; |
876 | 909 | ||
877 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | 910 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
878 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | 911 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
879 | stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]); | 912 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); |
880 | dev = xhci->devs[slot_id]; | 913 | dev = xhci->devs[slot_id]; |
881 | 914 | ||
882 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | 915 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); |
@@ -892,11 +925,11 @@ static void handle_set_deq_completion(struct xhci_hcd *xhci, | |||
892 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | 925 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
893 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | 926 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); |
894 | 927 | ||
895 | if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { | 928 | if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) { |
896 | unsigned int ep_state; | 929 | unsigned int ep_state; |
897 | unsigned int slot_state; | 930 | unsigned int slot_state; |
898 | 931 | ||
899 | switch (GET_COMP_CODE(event->status)) { | 932 | switch (GET_COMP_CODE(le32_to_cpu(event->status))) { |
900 | case COMP_TRB_ERR: | 933 | case COMP_TRB_ERR: |
901 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | 934 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " |
902 | "of stream ID configuration\n"); | 935 | "of stream ID configuration\n"); |
@@ -904,9 +937,9 @@ static void handle_set_deq_completion(struct xhci_hcd *xhci, | |||
904 | case COMP_CTX_STATE: | 937 | case COMP_CTX_STATE: |
905 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | 938 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " |
906 | "to incorrect slot or ep state.\n"); | 939 | "to incorrect slot or ep state.\n"); |
907 | ep_state = ep_ctx->ep_info; | 940 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
908 | ep_state &= EP_STATE_MASK; | 941 | ep_state &= EP_STATE_MASK; |
909 | slot_state = slot_ctx->dev_state; | 942 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
910 | slot_state = GET_SLOT_STATE(slot_state); | 943 | slot_state = GET_SLOT_STATE(slot_state); |
911 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | 944 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", |
912 | slot_state, ep_state); | 945 | slot_state, ep_state); |
@@ -918,7 +951,7 @@ static void handle_set_deq_completion(struct xhci_hcd *xhci, | |||
918 | default: | 951 | default: |
919 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | 952 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " |
920 | "completion code of %u.\n", | 953 | "completion code of %u.\n", |
921 | GET_COMP_CODE(event->status)); | 954 | GET_COMP_CODE(le32_to_cpu(event->status))); |
922 | break; | 955 | break; |
923 | } | 956 | } |
924 | /* OK what do we do now? The endpoint state is hosed, and we | 957 | /* OK what do we do now? The endpoint state is hosed, and we |
@@ -929,10 +962,27 @@ static void handle_set_deq_completion(struct xhci_hcd *xhci, | |||
929 | */ | 962 | */ |
930 | } else { | 963 | } else { |
931 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", | 964 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
932 | ep_ctx->deq); | 965 | le64_to_cpu(ep_ctx->deq)); |
966 | if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg, | ||
967 | dev->eps[ep_index].queued_deq_ptr) == | ||
968 | (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) { | ||
969 | /* Update the ring's dequeue segment and dequeue pointer | ||
970 | * to reflect the new position. | ||
971 | */ | ||
972 | ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg; | ||
973 | ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr; | ||
974 | } else { | ||
975 | xhci_warn(xhci, "Mismatch between completed Set TR Deq " | ||
976 | "Ptr command & xHCI internal state.\n"); | ||
977 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", | ||
978 | dev->eps[ep_index].queued_deq_seg, | ||
979 | dev->eps[ep_index].queued_deq_ptr); | ||
980 | } | ||
933 | } | 981 | } |
934 | 982 | ||
935 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | 983 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
984 | dev->eps[ep_index].queued_deq_seg = NULL; | ||
985 | dev->eps[ep_index].queued_deq_ptr = NULL; | ||
936 | /* Restart any rings with pending URBs */ | 986 | /* Restart any rings with pending URBs */ |
937 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | 987 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
938 | } | 988 | } |
@@ -944,13 +994,13 @@ static void handle_reset_ep_completion(struct xhci_hcd *xhci, | |||
944 | int slot_id; | 994 | int slot_id; |
945 | unsigned int ep_index; | 995 | unsigned int ep_index; |
946 | 996 | ||
947 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | 997 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
948 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | 998 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
949 | /* This command will only fail if the endpoint wasn't halted, | 999 | /* This command will only fail if the endpoint wasn't halted, |
950 | * but we don't care. | 1000 | * but we don't care. |
951 | */ | 1001 | */ |
952 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | 1002 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", |
953 | (unsigned int) GET_COMP_CODE(event->status)); | 1003 | (unsigned int) GET_COMP_CODE(le32_to_cpu(event->status))); |
954 | 1004 | ||
955 | /* HW with the reset endpoint quirk needs to have a configure endpoint | 1005 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
956 | * command complete before the endpoint can be used. Queue that here | 1006 | * command complete before the endpoint can be used. Queue that here |
@@ -987,8 +1037,7 @@ static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |||
987 | if (xhci->cmd_ring->dequeue != command->command_trb) | 1037 | if (xhci->cmd_ring->dequeue != command->command_trb) |
988 | return 0; | 1038 | return 0; |
989 | 1039 | ||
990 | command->status = | 1040 | command->status = GET_COMP_CODE(le32_to_cpu(event->status)); |
991 | GET_COMP_CODE(event->status); | ||
992 | list_del(&command->cmd_list); | 1041 | list_del(&command->cmd_list); |
993 | if (command->completion) | 1042 | if (command->completion) |
994 | complete(command->completion); | 1043 | complete(command->completion); |
@@ -1000,7 +1049,7 @@ static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |||
1000 | static void handle_cmd_completion(struct xhci_hcd *xhci, | 1049 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1001 | struct xhci_event_cmd *event) | 1050 | struct xhci_event_cmd *event) |
1002 | { | 1051 | { |
1003 | int slot_id = TRB_TO_SLOT_ID(event->flags); | 1052 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
1004 | u64 cmd_dma; | 1053 | u64 cmd_dma; |
1005 | dma_addr_t cmd_dequeue_dma; | 1054 | dma_addr_t cmd_dequeue_dma; |
1006 | struct xhci_input_control_ctx *ctrl_ctx; | 1055 | struct xhci_input_control_ctx *ctrl_ctx; |
@@ -1009,7 +1058,7 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, | |||
1009 | struct xhci_ring *ep_ring; | 1058 | struct xhci_ring *ep_ring; |
1010 | unsigned int ep_state; | 1059 | unsigned int ep_state; |
1011 | 1060 | ||
1012 | cmd_dma = event->cmd_trb; | 1061 | cmd_dma = le64_to_cpu(event->cmd_trb); |
1013 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | 1062 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
1014 | xhci->cmd_ring->dequeue); | 1063 | xhci->cmd_ring->dequeue); |
1015 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | 1064 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
@@ -1022,17 +1071,23 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, | |||
1022 | xhci->error_bitmask |= 1 << 5; | 1071 | xhci->error_bitmask |= 1 << 5; |
1023 | return; | 1072 | return; |
1024 | } | 1073 | } |
1025 | switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { | 1074 | switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]) |
1075 | & TRB_TYPE_BITMASK) { | ||
1026 | case TRB_TYPE(TRB_ENABLE_SLOT): | 1076 | case TRB_TYPE(TRB_ENABLE_SLOT): |
1027 | if (GET_COMP_CODE(event->status) == COMP_SUCCESS) | 1077 | if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS) |
1028 | xhci->slot_id = slot_id; | 1078 | xhci->slot_id = slot_id; |
1029 | else | 1079 | else |
1030 | xhci->slot_id = 0; | 1080 | xhci->slot_id = 0; |
1031 | complete(&xhci->addr_dev); | 1081 | complete(&xhci->addr_dev); |
1032 | break; | 1082 | break; |
1033 | case TRB_TYPE(TRB_DISABLE_SLOT): | 1083 | case TRB_TYPE(TRB_DISABLE_SLOT): |
1034 | if (xhci->devs[slot_id]) | 1084 | if (xhci->devs[slot_id]) { |
1085 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | ||
1086 | /* Delete default control endpoint resources */ | ||
1087 | xhci_free_device_endpoint_resources(xhci, | ||
1088 | xhci->devs[slot_id], true); | ||
1035 | xhci_free_virt_device(xhci, slot_id); | 1089 | xhci_free_virt_device(xhci, slot_id); |
1090 | } | ||
1036 | break; | 1091 | break; |
1037 | case TRB_TYPE(TRB_CONFIG_EP): | 1092 | case TRB_TYPE(TRB_CONFIG_EP): |
1038 | virt_dev = xhci->devs[slot_id]; | 1093 | virt_dev = xhci->devs[slot_id]; |
@@ -1049,7 +1104,7 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, | |||
1049 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | 1104 | ctrl_ctx = xhci_get_input_control_ctx(xhci, |
1050 | virt_dev->in_ctx); | 1105 | virt_dev->in_ctx); |
1051 | /* Input ctx add_flags are the endpoint index plus one */ | 1106 | /* Input ctx add_flags are the endpoint index plus one */ |
1052 | ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; | 1107 | ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1; |
1053 | /* A usb_set_interface() call directly after clearing a halted | 1108 | /* A usb_set_interface() call directly after clearing a halted |
1054 | * condition may race on this quirky hardware. Not worth | 1109 | * condition may race on this quirky hardware. Not worth |
1055 | * worrying about, since this is prototype hardware. Not sure | 1110 | * worrying about, since this is prototype hardware. Not sure |
@@ -1058,8 +1113,8 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, | |||
1058 | */ | 1113 | */ |
1059 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | 1114 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
1060 | ep_index != (unsigned int) -1 && | 1115 | ep_index != (unsigned int) -1 && |
1061 | ctrl_ctx->add_flags - SLOT_FLAG == | 1116 | le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG == |
1062 | ctrl_ctx->drop_flags) { | 1117 | le32_to_cpu(ctrl_ctx->drop_flags)) { |
1063 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | 1118 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
1064 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | 1119 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; |
1065 | if (!(ep_state & EP_HALTED)) | 1120 | if (!(ep_state & EP_HALTED)) |
@@ -1076,28 +1131,27 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, | |||
1076 | bandwidth_change: | 1131 | bandwidth_change: |
1077 | xhci_dbg(xhci, "Completed config ep cmd\n"); | 1132 | xhci_dbg(xhci, "Completed config ep cmd\n"); |
1078 | xhci->devs[slot_id]->cmd_status = | 1133 | xhci->devs[slot_id]->cmd_status = |
1079 | GET_COMP_CODE(event->status); | 1134 | GET_COMP_CODE(le32_to_cpu(event->status)); |
1080 | complete(&xhci->devs[slot_id]->cmd_completion); | 1135 | complete(&xhci->devs[slot_id]->cmd_completion); |
1081 | break; | 1136 | break; |
1082 | case TRB_TYPE(TRB_EVAL_CONTEXT): | 1137 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
1083 | virt_dev = xhci->devs[slot_id]; | 1138 | virt_dev = xhci->devs[slot_id]; |
1084 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | 1139 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
1085 | break; | 1140 | break; |
1086 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); | 1141 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
1087 | complete(&xhci->devs[slot_id]->cmd_completion); | 1142 | complete(&xhci->devs[slot_id]->cmd_completion); |
1088 | break; | 1143 | break; |
1089 | case TRB_TYPE(TRB_ADDR_DEV): | 1144 | case TRB_TYPE(TRB_ADDR_DEV): |
1090 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); | 1145 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
1091 | complete(&xhci->addr_dev); | 1146 | complete(&xhci->addr_dev); |
1092 | break; | 1147 | break; |
1093 | case TRB_TYPE(TRB_STOP_RING): | 1148 | case TRB_TYPE(TRB_STOP_RING): |
1094 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue); | 1149 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event); |
1095 | break; | 1150 | break; |
1096 | case TRB_TYPE(TRB_SET_DEQ): | 1151 | case TRB_TYPE(TRB_SET_DEQ): |
1097 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | 1152 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); |
1098 | break; | 1153 | break; |
1099 | case TRB_TYPE(TRB_CMD_NOOP): | 1154 | case TRB_TYPE(TRB_CMD_NOOP): |
1100 | ++xhci->noops_handled; | ||
1101 | break; | 1155 | break; |
1102 | case TRB_TYPE(TRB_RESET_EP): | 1156 | case TRB_TYPE(TRB_RESET_EP): |
1103 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | 1157 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); |
@@ -1105,7 +1159,7 @@ bandwidth_change: | |||
1105 | case TRB_TYPE(TRB_RESET_DEV): | 1159 | case TRB_TYPE(TRB_RESET_DEV): |
1106 | xhci_dbg(xhci, "Completed reset device command.\n"); | 1160 | xhci_dbg(xhci, "Completed reset device command.\n"); |
1107 | slot_id = TRB_TO_SLOT_ID( | 1161 | slot_id = TRB_TO_SLOT_ID( |
1108 | xhci->cmd_ring->dequeue->generic.field[3]); | 1162 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
1109 | virt_dev = xhci->devs[slot_id]; | 1163 | virt_dev = xhci->devs[slot_id]; |
1110 | if (virt_dev) | 1164 | if (virt_dev) |
1111 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | 1165 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); |
@@ -1119,8 +1173,8 @@ bandwidth_change: | |||
1119 | break; | 1173 | break; |
1120 | } | 1174 | } |
1121 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", | 1175 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", |
1122 | NEC_FW_MAJOR(event->status), | 1176 | NEC_FW_MAJOR(le32_to_cpu(event->status)), |
1123 | NEC_FW_MINOR(event->status)); | 1177 | NEC_FW_MINOR(le32_to_cpu(event->status))); |
1124 | break; | 1178 | break; |
1125 | default: | 1179 | default: |
1126 | /* Skip over unknown commands on the event ring */ | 1180 | /* Skip over unknown commands on the event ring */ |
@@ -1135,32 +1189,175 @@ static void handle_vendor_event(struct xhci_hcd *xhci, | |||
1135 | { | 1189 | { |
1136 | u32 trb_type; | 1190 | u32 trb_type; |
1137 | 1191 | ||
1138 | trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]); | 1192 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
1139 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); | 1193 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1140 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | 1194 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) |
1141 | handle_cmd_completion(xhci, &event->event_cmd); | 1195 | handle_cmd_completion(xhci, &event->event_cmd); |
1142 | } | 1196 | } |
1143 | 1197 | ||
1198 | /* @port_id: the one-based port ID from the hardware (indexed from array of all | ||
1199 | * port registers -- USB 3.0 and USB 2.0). | ||
1200 | * | ||
1201 | * Returns a zero-based port number, which is suitable for indexing into each of | ||
1202 | * the split roothubs' port arrays and bus state arrays. | ||
1203 | */ | ||
1204 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | ||
1205 | struct xhci_hcd *xhci, u32 port_id) | ||
1206 | { | ||
1207 | unsigned int i; | ||
1208 | unsigned int num_similar_speed_ports = 0; | ||
1209 | |||
1210 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | ||
1211 | * and usb2_ports are 0-based indexes. Count the number of similar | ||
1212 | * speed ports, up to 1 port before this port. | ||
1213 | */ | ||
1214 | for (i = 0; i < (port_id - 1); i++) { | ||
1215 | u8 port_speed = xhci->port_array[i]; | ||
1216 | |||
1217 | /* | ||
1218 | * Skip ports that don't have known speeds, or have duplicate | ||
1219 | * Extended Capabilities port speed entries. | ||
1220 | */ | ||
1221 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) | ||
1222 | continue; | ||
1223 | |||
1224 | /* | ||
1225 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | ||
1226 | * 1.1 ports are under the USB 2.0 hub. If the port speed | ||
1227 | * matches the device speed, it's a similar speed port. | ||
1228 | */ | ||
1229 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | ||
1230 | num_similar_speed_ports++; | ||
1231 | } | ||
1232 | return num_similar_speed_ports; | ||
1233 | } | ||
1234 | |||
1144 | static void handle_port_status(struct xhci_hcd *xhci, | 1235 | static void handle_port_status(struct xhci_hcd *xhci, |
1145 | union xhci_trb *event) | 1236 | union xhci_trb *event) |
1146 | { | 1237 | { |
1238 | struct usb_hcd *hcd; | ||
1147 | u32 port_id; | 1239 | u32 port_id; |
1240 | u32 temp, temp1; | ||
1241 | int max_ports; | ||
1242 | int slot_id; | ||
1243 | unsigned int faked_port_index; | ||
1244 | u8 major_revision; | ||
1245 | struct xhci_bus_state *bus_state; | ||
1246 | __le32 __iomem **port_array; | ||
1247 | bool bogus_port_status = false; | ||
1148 | 1248 | ||
1149 | /* Port status change events always have a successful completion code */ | 1249 | /* Port status change events always have a successful completion code */ |
1150 | if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { | 1250 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
1151 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); | 1251 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1152 | xhci->error_bitmask |= 1 << 8; | 1252 | xhci->error_bitmask |= 1 << 8; |
1153 | } | 1253 | } |
1154 | /* FIXME: core doesn't care about all port link state changes yet */ | 1254 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
1155 | port_id = GET_PORT_ID(event->generic.field[0]); | ||
1156 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); | 1255 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1157 | 1256 | ||
1257 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); | ||
1258 | if ((port_id <= 0) || (port_id > max_ports)) { | ||
1259 | xhci_warn(xhci, "Invalid port id %d\n", port_id); | ||
1260 | bogus_port_status = true; | ||
1261 | goto cleanup; | ||
1262 | } | ||
1263 | |||
1264 | /* Figure out which usb_hcd this port is attached to: | ||
1265 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | ||
1266 | */ | ||
1267 | major_revision = xhci->port_array[port_id - 1]; | ||
1268 | if (major_revision == 0) { | ||
1269 | xhci_warn(xhci, "Event for port %u not in " | ||
1270 | "Extended Capabilities, ignoring.\n", | ||
1271 | port_id); | ||
1272 | bogus_port_status = true; | ||
1273 | goto cleanup; | ||
1274 | } | ||
1275 | if (major_revision == DUPLICATE_ENTRY) { | ||
1276 | xhci_warn(xhci, "Event for port %u duplicated in" | ||
1277 | "Extended Capabilities, ignoring.\n", | ||
1278 | port_id); | ||
1279 | bogus_port_status = true; | ||
1280 | goto cleanup; | ||
1281 | } | ||
1282 | |||
1283 | /* | ||
1284 | * Hardware port IDs reported by a Port Status Change Event include USB | ||
1285 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | ||
1286 | * resume event, but we first need to translate the hardware port ID | ||
1287 | * into the index into the ports on the correct split roothub, and the | ||
1288 | * correct bus_state structure. | ||
1289 | */ | ||
1290 | /* Find the right roothub. */ | ||
1291 | hcd = xhci_to_hcd(xhci); | ||
1292 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | ||
1293 | hcd = xhci->shared_hcd; | ||
1294 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | ||
1295 | if (hcd->speed == HCD_USB3) | ||
1296 | port_array = xhci->usb3_ports; | ||
1297 | else | ||
1298 | port_array = xhci->usb2_ports; | ||
1299 | /* Find the faked port hub number */ | ||
1300 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | ||
1301 | port_id); | ||
1302 | |||
1303 | temp = xhci_readl(xhci, port_array[faked_port_index]); | ||
1304 | if (hcd->state == HC_STATE_SUSPENDED) { | ||
1305 | xhci_dbg(xhci, "resume root hub\n"); | ||
1306 | usb_hcd_resume_root_hub(hcd); | ||
1307 | } | ||
1308 | |||
1309 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | ||
1310 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | ||
1311 | |||
1312 | temp1 = xhci_readl(xhci, &xhci->op_regs->command); | ||
1313 | if (!(temp1 & CMD_RUN)) { | ||
1314 | xhci_warn(xhci, "xHC is not running.\n"); | ||
1315 | goto cleanup; | ||
1316 | } | ||
1317 | |||
1318 | if (DEV_SUPERSPEED(temp)) { | ||
1319 | xhci_dbg(xhci, "resume SS port %d\n", port_id); | ||
1320 | temp = xhci_port_state_to_neutral(temp); | ||
1321 | temp &= ~PORT_PLS_MASK; | ||
1322 | temp |= PORT_LINK_STROBE | XDEV_U0; | ||
1323 | xhci_writel(xhci, temp, port_array[faked_port_index]); | ||
1324 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | ||
1325 | faked_port_index); | ||
1326 | if (!slot_id) { | ||
1327 | xhci_dbg(xhci, "slot_id is zero\n"); | ||
1328 | goto cleanup; | ||
1329 | } | ||
1330 | xhci_ring_device(xhci, slot_id); | ||
1331 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | ||
1332 | /* Clear PORT_PLC */ | ||
1333 | temp = xhci_readl(xhci, port_array[faked_port_index]); | ||
1334 | temp = xhci_port_state_to_neutral(temp); | ||
1335 | temp |= PORT_PLC; | ||
1336 | xhci_writel(xhci, temp, port_array[faked_port_index]); | ||
1337 | } else { | ||
1338 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | ||
1339 | bus_state->resume_done[faked_port_index] = jiffies + | ||
1340 | msecs_to_jiffies(20); | ||
1341 | mod_timer(&hcd->rh_timer, | ||
1342 | bus_state->resume_done[faked_port_index]); | ||
1343 | /* Do the rest in GetPortStatus */ | ||
1344 | } | ||
1345 | } | ||
1346 | |||
1347 | cleanup: | ||
1158 | /* Update event ring dequeue pointer before dropping the lock */ | 1348 | /* Update event ring dequeue pointer before dropping the lock */ |
1159 | inc_deq(xhci, xhci->event_ring, true); | 1349 | inc_deq(xhci, xhci->event_ring, true); |
1160 | 1350 | ||
1351 | /* Don't make the USB core poll the roothub if we got a bad port status | ||
1352 | * change event. Besides, at that point we can't tell which roothub | ||
1353 | * (USB 2.0 or USB 3.0) to kick. | ||
1354 | */ | ||
1355 | if (bogus_port_status) | ||
1356 | return; | ||
1357 | |||
1161 | spin_unlock(&xhci->lock); | 1358 | spin_unlock(&xhci->lock); |
1162 | /* Pass this up to the core */ | 1359 | /* Pass this up to the core */ |
1163 | usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); | 1360 | usb_hcd_poll_rh_status(hcd); |
1164 | spin_lock(&xhci->lock); | 1361 | spin_lock(&xhci->lock); |
1165 | } | 1362 | } |
1166 | 1363 | ||
@@ -1261,7 +1458,7 @@ static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |||
1261 | * endpoint anyway. Check if a babble halted the | 1458 | * endpoint anyway. Check if a babble halted the |
1262 | * endpoint. | 1459 | * endpoint. |
1263 | */ | 1460 | */ |
1264 | if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED) | 1461 | if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED) |
1265 | return 1; | 1462 | return 1; |
1266 | 1463 | ||
1267 | return 0; | 1464 | return 0; |
@@ -1299,12 +1496,12 @@ static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1299 | struct urb_priv *urb_priv; | 1496 | struct urb_priv *urb_priv; |
1300 | u32 trb_comp_code; | 1497 | u32 trb_comp_code; |
1301 | 1498 | ||
1302 | slot_id = TRB_TO_SLOT_ID(event->flags); | 1499 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
1303 | xdev = xhci->devs[slot_id]; | 1500 | xdev = xhci->devs[slot_id]; |
1304 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | 1501 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1305 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | 1502 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1306 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | 1503 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
1307 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | 1504 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
1308 | 1505 | ||
1309 | if (skip) | 1506 | if (skip) |
1310 | goto td_cleanup; | 1507 | goto td_cleanup; |
@@ -1377,8 +1574,17 @@ td_cleanup: | |||
1377 | 1574 | ||
1378 | urb_priv->td_cnt++; | 1575 | urb_priv->td_cnt++; |
1379 | /* Giveback the urb when all the tds are completed */ | 1576 | /* Giveback the urb when all the tds are completed */ |
1380 | if (urb_priv->td_cnt == urb_priv->length) | 1577 | if (urb_priv->td_cnt == urb_priv->length) { |
1381 | ret = 1; | 1578 | ret = 1; |
1579 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | ||
1580 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | ||
1581 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs | ||
1582 | == 0) { | ||
1583 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | ||
1584 | usb_amd_quirk_pll_enable(); | ||
1585 | } | ||
1586 | } | ||
1587 | } | ||
1382 | } | 1588 | } |
1383 | 1589 | ||
1384 | return ret; | 1590 | return ret; |
@@ -1398,12 +1604,12 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1398 | struct xhci_ep_ctx *ep_ctx; | 1604 | struct xhci_ep_ctx *ep_ctx; |
1399 | u32 trb_comp_code; | 1605 | u32 trb_comp_code; |
1400 | 1606 | ||
1401 | slot_id = TRB_TO_SLOT_ID(event->flags); | 1607 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
1402 | xdev = xhci->devs[slot_id]; | 1608 | xdev = xhci->devs[slot_id]; |
1403 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | 1609 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1404 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | 1610 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1405 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | 1611 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
1406 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | 1612 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
1407 | 1613 | ||
1408 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); | 1614 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); |
1409 | switch (trb_comp_code) { | 1615 | switch (trb_comp_code) { |
@@ -1417,7 +1623,6 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1417 | "without IOC set??\n"); | 1623 | "without IOC set??\n"); |
1418 | *status = -ESHUTDOWN; | 1624 | *status = -ESHUTDOWN; |
1419 | } else { | 1625 | } else { |
1420 | xhci_dbg(xhci, "Successful control transfer!\n"); | ||
1421 | *status = 0; | 1626 | *status = 0; |
1422 | } | 1627 | } |
1423 | break; | 1628 | break; |
@@ -1428,6 +1633,9 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1428 | else | 1633 | else |
1429 | *status = 0; | 1634 | *status = 0; |
1430 | break; | 1635 | break; |
1636 | case COMP_STOP_INVAL: | ||
1637 | case COMP_STOP: | ||
1638 | return finish_td(xhci, td, event_trb, event, ep, status, false); | ||
1431 | default: | 1639 | default: |
1432 | if (!xhci_requires_manual_halt_cleanup(xhci, | 1640 | if (!xhci_requires_manual_halt_cleanup(xhci, |
1433 | ep_ctx, trb_comp_code)) | 1641 | ep_ctx, trb_comp_code)) |
@@ -1442,7 +1650,7 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1442 | event_trb != td->last_trb) | 1650 | event_trb != td->last_trb) |
1443 | td->urb->actual_length = | 1651 | td->urb->actual_length = |
1444 | td->urb->transfer_buffer_length | 1652 | td->urb->transfer_buffer_length |
1445 | - TRB_LEN(event->transfer_len); | 1653 | - TRB_LEN(le32_to_cpu(event->transfer_len)); |
1446 | else | 1654 | else |
1447 | td->urb->actual_length = 0; | 1655 | td->urb->actual_length = 0; |
1448 | 1656 | ||
@@ -1472,15 +1680,12 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1472 | } | 1680 | } |
1473 | } else { | 1681 | } else { |
1474 | /* Maybe the event was for the data stage? */ | 1682 | /* Maybe the event was for the data stage? */ |
1475 | if (trb_comp_code != COMP_STOP_INVAL) { | 1683 | td->urb->actual_length = |
1476 | /* We didn't stop on a link TRB in the middle */ | 1684 | td->urb->transfer_buffer_length - |
1477 | td->urb->actual_length = | 1685 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
1478 | td->urb->transfer_buffer_length - | 1686 | xhci_dbg(xhci, "Waiting for status " |
1479 | TRB_LEN(event->transfer_len); | 1687 | "stage event\n"); |
1480 | xhci_dbg(xhci, "Waiting for status " | 1688 | return 0; |
1481 | "stage event\n"); | ||
1482 | return 0; | ||
1483 | } | ||
1484 | } | 1689 | } |
1485 | } | 1690 | } |
1486 | 1691 | ||
@@ -1498,97 +1703,102 @@ static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1498 | struct urb_priv *urb_priv; | 1703 | struct urb_priv *urb_priv; |
1499 | int idx; | 1704 | int idx; |
1500 | int len = 0; | 1705 | int len = 0; |
1501 | int skip_td = 0; | ||
1502 | union xhci_trb *cur_trb; | 1706 | union xhci_trb *cur_trb; |
1503 | struct xhci_segment *cur_seg; | 1707 | struct xhci_segment *cur_seg; |
1708 | struct usb_iso_packet_descriptor *frame; | ||
1504 | u32 trb_comp_code; | 1709 | u32 trb_comp_code; |
1710 | bool skip_td = false; | ||
1505 | 1711 | ||
1506 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | 1712 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1507 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | 1713 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
1508 | urb_priv = td->urb->hcpriv; | 1714 | urb_priv = td->urb->hcpriv; |
1509 | idx = urb_priv->td_cnt; | 1715 | idx = urb_priv->td_cnt; |
1716 | frame = &td->urb->iso_frame_desc[idx]; | ||
1510 | 1717 | ||
1511 | if (ep->skip) { | 1718 | /* handle completion code */ |
1512 | /* The transfer is partly done */ | 1719 | switch (trb_comp_code) { |
1513 | *status = -EXDEV; | 1720 | case COMP_SUCCESS: |
1514 | td->urb->iso_frame_desc[idx].status = -EXDEV; | 1721 | frame->status = 0; |
1515 | } else { | 1722 | break; |
1516 | /* handle completion code */ | 1723 | case COMP_SHORT_TX: |
1517 | switch (trb_comp_code) { | 1724 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? |
1518 | case COMP_SUCCESS: | 1725 | -EREMOTEIO : 0; |
1519 | td->urb->iso_frame_desc[idx].status = 0; | 1726 | break; |
1520 | xhci_dbg(xhci, "Successful isoc transfer!\n"); | 1727 | case COMP_BW_OVER: |
1521 | break; | 1728 | frame->status = -ECOMM; |
1522 | case COMP_SHORT_TX: | 1729 | skip_td = true; |
1523 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | 1730 | break; |
1524 | td->urb->iso_frame_desc[idx].status = | 1731 | case COMP_BUFF_OVER: |
1525 | -EREMOTEIO; | 1732 | case COMP_BABBLE: |
1526 | else | 1733 | frame->status = -EOVERFLOW; |
1527 | td->urb->iso_frame_desc[idx].status = 0; | 1734 | skip_td = true; |
1528 | break; | 1735 | break; |
1529 | case COMP_BW_OVER: | 1736 | case COMP_DEV_ERR: |
1530 | td->urb->iso_frame_desc[idx].status = -ECOMM; | 1737 | case COMP_STALL: |
1531 | skip_td = 1; | 1738 | frame->status = -EPROTO; |
1532 | break; | 1739 | skip_td = true; |
1533 | case COMP_BUFF_OVER: | 1740 | break; |
1534 | case COMP_BABBLE: | 1741 | case COMP_STOP: |
1535 | td->urb->iso_frame_desc[idx].status = -EOVERFLOW; | 1742 | case COMP_STOP_INVAL: |
1536 | skip_td = 1; | 1743 | break; |
1537 | break; | 1744 | default: |
1538 | case COMP_STALL: | 1745 | frame->status = -1; |
1539 | td->urb->iso_frame_desc[idx].status = -EPROTO; | 1746 | break; |
1540 | skip_td = 1; | ||
1541 | break; | ||
1542 | case COMP_STOP: | ||
1543 | case COMP_STOP_INVAL: | ||
1544 | break; | ||
1545 | default: | ||
1546 | td->urb->iso_frame_desc[idx].status = -1; | ||
1547 | break; | ||
1548 | } | ||
1549 | } | ||
1550 | |||
1551 | /* calc actual length */ | ||
1552 | if (ep->skip) { | ||
1553 | td->urb->iso_frame_desc[idx].actual_length = 0; | ||
1554 | /* Update ring dequeue pointer */ | ||
1555 | while (ep_ring->dequeue != td->last_trb) | ||
1556 | inc_deq(xhci, ep_ring, false); | ||
1557 | inc_deq(xhci, ep_ring, false); | ||
1558 | return finish_td(xhci, td, event_trb, event, ep, status, true); | ||
1559 | } | 1747 | } |
1560 | 1748 | ||
1561 | if (trb_comp_code == COMP_SUCCESS || skip_td == 1) { | 1749 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
1562 | td->urb->iso_frame_desc[idx].actual_length = | 1750 | frame->actual_length = frame->length; |
1563 | td->urb->iso_frame_desc[idx].length; | 1751 | td->urb->actual_length += frame->length; |
1564 | td->urb->actual_length += | ||
1565 | td->urb->iso_frame_desc[idx].length; | ||
1566 | } else { | 1752 | } else { |
1567 | for (cur_trb = ep_ring->dequeue, | 1753 | for (cur_trb = ep_ring->dequeue, |
1568 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | 1754 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; |
1569 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | 1755 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
1570 | if ((cur_trb->generic.field[3] & | 1756 | if ((le32_to_cpu(cur_trb->generic.field[3]) & |
1571 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && | 1757 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && |
1572 | (cur_trb->generic.field[3] & | 1758 | (le32_to_cpu(cur_trb->generic.field[3]) & |
1573 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) | 1759 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) |
1574 | len += | 1760 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
1575 | TRB_LEN(cur_trb->generic.field[2]); | ||
1576 | } | 1761 | } |
1577 | len += TRB_LEN(cur_trb->generic.field[2]) - | 1762 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1578 | TRB_LEN(event->transfer_len); | 1763 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
1579 | 1764 | ||
1580 | if (trb_comp_code != COMP_STOP_INVAL) { | 1765 | if (trb_comp_code != COMP_STOP_INVAL) { |
1581 | td->urb->iso_frame_desc[idx].actual_length = len; | 1766 | frame->actual_length = len; |
1582 | td->urb->actual_length += len; | 1767 | td->urb->actual_length += len; |
1583 | } | 1768 | } |
1584 | } | 1769 | } |
1585 | 1770 | ||
1586 | if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS) | ||
1587 | *status = 0; | ||
1588 | |||
1589 | return finish_td(xhci, td, event_trb, event, ep, status, false); | 1771 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
1590 | } | 1772 | } |
1591 | 1773 | ||
1774 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | ||
1775 | struct xhci_transfer_event *event, | ||
1776 | struct xhci_virt_ep *ep, int *status) | ||
1777 | { | ||
1778 | struct xhci_ring *ep_ring; | ||
1779 | struct urb_priv *urb_priv; | ||
1780 | struct usb_iso_packet_descriptor *frame; | ||
1781 | int idx; | ||
1782 | |||
1783 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | ||
1784 | urb_priv = td->urb->hcpriv; | ||
1785 | idx = urb_priv->td_cnt; | ||
1786 | frame = &td->urb->iso_frame_desc[idx]; | ||
1787 | |||
1788 | /* The transfer is partly done. */ | ||
1789 | frame->status = -EXDEV; | ||
1790 | |||
1791 | /* calc actual length */ | ||
1792 | frame->actual_length = 0; | ||
1793 | |||
1794 | /* Update ring dequeue pointer */ | ||
1795 | while (ep_ring->dequeue != td->last_trb) | ||
1796 | inc_deq(xhci, ep_ring, false); | ||
1797 | inc_deq(xhci, ep_ring, false); | ||
1798 | |||
1799 | return finish_td(xhci, td, NULL, event, ep, status, true); | ||
1800 | } | ||
1801 | |||
1592 | /* | 1802 | /* |
1593 | * Process bulk and interrupt tds, update urb status and actual_length. | 1803 | * Process bulk and interrupt tds, update urb status and actual_length. |
1594 | */ | 1804 | */ |
@@ -1601,8 +1811,8 @@ static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1601 | struct xhci_segment *cur_seg; | 1811 | struct xhci_segment *cur_seg; |
1602 | u32 trb_comp_code; | 1812 | u32 trb_comp_code; |
1603 | 1813 | ||
1604 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | 1814 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1605 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | 1815 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
1606 | 1816 | ||
1607 | switch (trb_comp_code) { | 1817 | switch (trb_comp_code) { |
1608 | case COMP_SUCCESS: | 1818 | case COMP_SUCCESS: |
@@ -1615,12 +1825,6 @@ static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1615 | else | 1825 | else |
1616 | *status = 0; | 1826 | *status = 0; |
1617 | } else { | 1827 | } else { |
1618 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) | ||
1619 | xhci_dbg(xhci, "Successful bulk " | ||
1620 | "transfer!\n"); | ||
1621 | else | ||
1622 | xhci_dbg(xhci, "Successful interrupt " | ||
1623 | "transfer!\n"); | ||
1624 | *status = 0; | 1828 | *status = 0; |
1625 | } | 1829 | } |
1626 | break; | 1830 | break; |
@@ -1634,23 +1838,23 @@ static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1634 | /* Others already handled above */ | 1838 | /* Others already handled above */ |
1635 | break; | 1839 | break; |
1636 | } | 1840 | } |
1637 | dev_dbg(&td->urb->dev->dev, | 1841 | if (trb_comp_code == COMP_SHORT_TX) |
1638 | "ep %#x - asked for %d bytes, " | 1842 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " |
1639 | "%d bytes untransferred\n", | 1843 | "%d bytes untransferred\n", |
1640 | td->urb->ep->desc.bEndpointAddress, | 1844 | td->urb->ep->desc.bEndpointAddress, |
1641 | td->urb->transfer_buffer_length, | 1845 | td->urb->transfer_buffer_length, |
1642 | TRB_LEN(event->transfer_len)); | 1846 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
1643 | /* Fast path - was this the last TRB in the TD for this URB? */ | 1847 | /* Fast path - was this the last TRB in the TD for this URB? */ |
1644 | if (event_trb == td->last_trb) { | 1848 | if (event_trb == td->last_trb) { |
1645 | if (TRB_LEN(event->transfer_len) != 0) { | 1849 | if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
1646 | td->urb->actual_length = | 1850 | td->urb->actual_length = |
1647 | td->urb->transfer_buffer_length - | 1851 | td->urb->transfer_buffer_length - |
1648 | TRB_LEN(event->transfer_len); | 1852 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
1649 | if (td->urb->transfer_buffer_length < | 1853 | if (td->urb->transfer_buffer_length < |
1650 | td->urb->actual_length) { | 1854 | td->urb->actual_length) { |
1651 | xhci_warn(xhci, "HC gave bad length " | 1855 | xhci_warn(xhci, "HC gave bad length " |
1652 | "of %d bytes left\n", | 1856 | "of %d bytes left\n", |
1653 | TRB_LEN(event->transfer_len)); | 1857 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
1654 | td->urb->actual_length = 0; | 1858 | td->urb->actual_length = 0; |
1655 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | 1859 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1656 | *status = -EREMOTEIO; | 1860 | *status = -EREMOTEIO; |
@@ -1681,20 +1885,20 @@ static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |||
1681 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | 1885 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
1682 | cur_trb != event_trb; | 1886 | cur_trb != event_trb; |
1683 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | 1887 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
1684 | if ((cur_trb->generic.field[3] & | 1888 | if ((le32_to_cpu(cur_trb->generic.field[3]) & |
1685 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && | 1889 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && |
1686 | (cur_trb->generic.field[3] & | 1890 | (le32_to_cpu(cur_trb->generic.field[3]) & |
1687 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) | 1891 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) |
1688 | td->urb->actual_length += | 1892 | td->urb->actual_length += |
1689 | TRB_LEN(cur_trb->generic.field[2]); | 1893 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
1690 | } | 1894 | } |
1691 | /* If the ring didn't stop on a Link or No-op TRB, add | 1895 | /* If the ring didn't stop on a Link or No-op TRB, add |
1692 | * in the actual bytes transferred from the Normal TRB | 1896 | * in the actual bytes transferred from the Normal TRB |
1693 | */ | 1897 | */ |
1694 | if (trb_comp_code != COMP_STOP_INVAL) | 1898 | if (trb_comp_code != COMP_STOP_INVAL) |
1695 | td->urb->actual_length += | 1899 | td->urb->actual_length += |
1696 | TRB_LEN(cur_trb->generic.field[2]) - | 1900 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1697 | TRB_LEN(event->transfer_len); | 1901 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
1698 | } | 1902 | } |
1699 | 1903 | ||
1700 | return finish_td(xhci, td, event_trb, event, ep, status, false); | 1904 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
@@ -1724,7 +1928,7 @@ static int handle_tx_event(struct xhci_hcd *xhci, | |||
1724 | u32 trb_comp_code; | 1928 | u32 trb_comp_code; |
1725 | int ret = 0; | 1929 | int ret = 0; |
1726 | 1930 | ||
1727 | slot_id = TRB_TO_SLOT_ID(event->flags); | 1931 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
1728 | xdev = xhci->devs[slot_id]; | 1932 | xdev = xhci->devs[slot_id]; |
1729 | if (!xdev) { | 1933 | if (!xdev) { |
1730 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | 1934 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); |
@@ -1732,20 +1936,20 @@ static int handle_tx_event(struct xhci_hcd *xhci, | |||
1732 | } | 1936 | } |
1733 | 1937 | ||
1734 | /* Endpoint ID is 1 based, our index is zero based */ | 1938 | /* Endpoint ID is 1 based, our index is zero based */ |
1735 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | 1939 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1736 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); | ||
1737 | ep = &xdev->eps[ep_index]; | 1940 | ep = &xdev->eps[ep_index]; |
1738 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | 1941 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1739 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | 1942 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
1740 | if (!ep_ring || | 1943 | if (!ep_ring || |
1741 | (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { | 1944 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
1945 | EP_STATE_DISABLED) { | ||
1742 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " | 1946 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
1743 | "or incorrect stream ring\n"); | 1947 | "or incorrect stream ring\n"); |
1744 | return -ENODEV; | 1948 | return -ENODEV; |
1745 | } | 1949 | } |
1746 | 1950 | ||
1747 | event_dma = event->buffer; | 1951 | event_dma = le64_to_cpu(event->buffer); |
1748 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | 1952 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
1749 | /* Look for common error cases */ | 1953 | /* Look for common error cases */ |
1750 | switch (trb_comp_code) { | 1954 | switch (trb_comp_code) { |
1751 | /* Skip codes that require special handling depending on | 1955 | /* Skip codes that require special handling depending on |
@@ -1798,15 +2002,21 @@ static int handle_tx_event(struct xhci_hcd *xhci, | |||
1798 | if (!list_empty(&ep_ring->td_list)) | 2002 | if (!list_empty(&ep_ring->td_list)) |
1799 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | 2003 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " |
1800 | "still with TDs queued?\n", | 2004 | "still with TDs queued?\n", |
1801 | TRB_TO_SLOT_ID(event->flags), ep_index); | 2005 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2006 | ep_index); | ||
1802 | goto cleanup; | 2007 | goto cleanup; |
1803 | case COMP_OVERRUN: | 2008 | case COMP_OVERRUN: |
1804 | xhci_dbg(xhci, "overrun event on endpoint\n"); | 2009 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
1805 | if (!list_empty(&ep_ring->td_list)) | 2010 | if (!list_empty(&ep_ring->td_list)) |
1806 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | 2011 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " |
1807 | "still with TDs queued?\n", | 2012 | "still with TDs queued?\n", |
1808 | TRB_TO_SLOT_ID(event->flags), ep_index); | 2013 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2014 | ep_index); | ||
1809 | goto cleanup; | 2015 | goto cleanup; |
2016 | case COMP_DEV_ERR: | ||
2017 | xhci_warn(xhci, "WARN: detect an incompatible device"); | ||
2018 | status = -EPROTO; | ||
2019 | break; | ||
1810 | case COMP_MISSED_INT: | 2020 | case COMP_MISSED_INT: |
1811 | /* | 2021 | /* |
1812 | * When encounter missed service error, one or more isoc tds | 2022 | * When encounter missed service error, one or more isoc tds |
@@ -1834,9 +2044,11 @@ static int handle_tx_event(struct xhci_hcd *xhci, | |||
1834 | if (list_empty(&ep_ring->td_list)) { | 2044 | if (list_empty(&ep_ring->td_list)) { |
1835 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " | 2045 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " |
1836 | "with no TDs queued?\n", | 2046 | "with no TDs queued?\n", |
1837 | TRB_TO_SLOT_ID(event->flags), ep_index); | 2047 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2048 | ep_index); | ||
1838 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | 2049 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
1839 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | 2050 | (unsigned int) (le32_to_cpu(event->flags) |
2051 | & TRB_TYPE_BITMASK)>>10); | ||
1840 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | 2052 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); |
1841 | if (ep->skip) { | 2053 | if (ep->skip) { |
1842 | ep->skip = false; | 2054 | ep->skip = false; |
@@ -1848,36 +2060,71 @@ static int handle_tx_event(struct xhci_hcd *xhci, | |||
1848 | } | 2060 | } |
1849 | 2061 | ||
1850 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); | 2062 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
2063 | |||
1851 | /* Is this a TRB in the currently executing TD? */ | 2064 | /* Is this a TRB in the currently executing TD? */ |
1852 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | 2065 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, |
1853 | td->last_trb, event_dma); | 2066 | td->last_trb, event_dma); |
1854 | if (event_seg && ep->skip) { | 2067 | |
1855 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); | 2068 | /* |
1856 | ep->skip = false; | 2069 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE |
2070 | * is not in the current TD pointed by ep_ring->dequeue because | ||
2071 | * that the hardware dequeue pointer still at the previous TRB | ||
2072 | * of the current TD. The previous TRB maybe a Link TD or the | ||
2073 | * last TRB of the previous TD. The command completion handle | ||
2074 | * will take care the rest. | ||
2075 | */ | ||
2076 | if (!event_seg && trb_comp_code == COMP_STOP_INVAL) { | ||
2077 | ret = 0; | ||
2078 | goto cleanup; | ||
1857 | } | 2079 | } |
1858 | if (!event_seg && | 2080 | |
1859 | (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) { | 2081 | if (!event_seg) { |
1860 | /* HC is busted, give up! */ | 2082 | if (!ep->skip || |
1861 | xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not " | 2083 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { |
2084 | /* Some host controllers give a spurious | ||
2085 | * successful event after a short transfer. | ||
2086 | * Ignore it. | ||
2087 | */ | ||
2088 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && | ||
2089 | ep_ring->last_td_was_short) { | ||
2090 | ep_ring->last_td_was_short = false; | ||
2091 | ret = 0; | ||
2092 | goto cleanup; | ||
2093 | } | ||
2094 | /* HC is busted, give up! */ | ||
2095 | xhci_err(xhci, | ||
2096 | "ERROR Transfer event TRB DMA ptr not " | ||
1862 | "part of current TD\n"); | 2097 | "part of current TD\n"); |
1863 | return -ESHUTDOWN; | 2098 | return -ESHUTDOWN; |
2099 | } | ||
2100 | |||
2101 | ret = skip_isoc_td(xhci, td, event, ep, &status); | ||
2102 | goto cleanup; | ||
1864 | } | 2103 | } |
2104 | if (trb_comp_code == COMP_SHORT_TX) | ||
2105 | ep_ring->last_td_was_short = true; | ||
2106 | else | ||
2107 | ep_ring->last_td_was_short = false; | ||
1865 | 2108 | ||
1866 | if (event_seg) { | 2109 | if (ep->skip) { |
1867 | event_trb = &event_seg->trbs[(event_dma - | 2110 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
1868 | event_seg->dma) / sizeof(*event_trb)]; | 2111 | ep->skip = false; |
1869 | /* | 2112 | } |
1870 | * No-op TRB should not trigger interrupts. | 2113 | |
1871 | * If event_trb is a no-op TRB, it means the | 2114 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
1872 | * corresponding TD has been cancelled. Just ignore | 2115 | sizeof(*event_trb)]; |
1873 | * the TD. | 2116 | /* |
1874 | */ | 2117 | * No-op TRB should not trigger interrupts. |
1875 | if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK) | 2118 | * If event_trb is a no-op TRB, it means the |
1876 | == TRB_TYPE(TRB_TR_NOOP)) { | 2119 | * corresponding TD has been cancelled. Just ignore |
1877 | xhci_dbg(xhci, "event_trb is a no-op TRB. " | 2120 | * the TD. |
1878 | "Skip it\n"); | 2121 | */ |
1879 | goto cleanup; | 2122 | if ((le32_to_cpu(event_trb->generic.field[3]) |
1880 | } | 2123 | & TRB_TYPE_BITMASK) |
2124 | == TRB_TYPE(TRB_TR_NOOP)) { | ||
2125 | xhci_dbg(xhci, | ||
2126 | "event_trb is a no-op TRB. Skip it\n"); | ||
2127 | goto cleanup; | ||
1881 | } | 2128 | } |
1882 | 2129 | ||
1883 | /* Now update the urb's actual_length and give back to | 2130 | /* Now update the urb's actual_length and give back to |
@@ -1915,12 +2162,23 @@ cleanup: | |||
1915 | trb_comp_code != COMP_BABBLE)) | 2162 | trb_comp_code != COMP_BABBLE)) |
1916 | xhci_urb_free_priv(xhci, urb_priv); | 2163 | xhci_urb_free_priv(xhci, urb_priv); |
1917 | 2164 | ||
1918 | usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); | 2165 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
1919 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " | 2166 | if ((urb->actual_length != urb->transfer_buffer_length && |
1920 | "status = %d\n", | 2167 | (urb->transfer_flags & |
1921 | urb, urb->actual_length, status); | 2168 | URB_SHORT_NOT_OK)) || |
2169 | status != 0) | ||
2170 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " | ||
2171 | "expected = %x, status = %d\n", | ||
2172 | urb, urb->actual_length, | ||
2173 | urb->transfer_buffer_length, | ||
2174 | status); | ||
1922 | spin_unlock(&xhci->lock); | 2175 | spin_unlock(&xhci->lock); |
1923 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); | 2176 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2177 | * urb->status of an isochronous endpoint to 0. | ||
2178 | */ | ||
2179 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | ||
2180 | status = 0; | ||
2181 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); | ||
1924 | spin_lock(&xhci->lock); | 2182 | spin_lock(&xhci->lock); |
1925 | } | 2183 | } |
1926 | 2184 | ||
@@ -1938,52 +2196,52 @@ cleanup: | |||
1938 | /* | 2196 | /* |
1939 | * This function handles all OS-owned events on the event ring. It may drop | 2197 | * This function handles all OS-owned events on the event ring. It may drop |
1940 | * xhci->lock between event processing (e.g. to pass up port status changes). | 2198 | * xhci->lock between event processing (e.g. to pass up port status changes). |
2199 | * Returns >0 for "possibly more events to process" (caller should call again), | ||
2200 | * otherwise 0 if done. In future, <0 returns should indicate error code. | ||
1941 | */ | 2201 | */ |
1942 | static void xhci_handle_event(struct xhci_hcd *xhci) | 2202 | static int xhci_handle_event(struct xhci_hcd *xhci) |
1943 | { | 2203 | { |
1944 | union xhci_trb *event; | 2204 | union xhci_trb *event; |
1945 | int update_ptrs = 1; | 2205 | int update_ptrs = 1; |
1946 | int ret; | 2206 | int ret; |
1947 | 2207 | ||
1948 | xhci_dbg(xhci, "In %s\n", __func__); | ||
1949 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | 2208 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
1950 | xhci->error_bitmask |= 1 << 1; | 2209 | xhci->error_bitmask |= 1 << 1; |
1951 | return; | 2210 | return 0; |
1952 | } | 2211 | } |
1953 | 2212 | ||
1954 | event = xhci->event_ring->dequeue; | 2213 | event = xhci->event_ring->dequeue; |
1955 | /* Does the HC or OS own the TRB? */ | 2214 | /* Does the HC or OS own the TRB? */ |
1956 | if ((event->event_cmd.flags & TRB_CYCLE) != | 2215 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
1957 | xhci->event_ring->cycle_state) { | 2216 | xhci->event_ring->cycle_state) { |
1958 | xhci->error_bitmask |= 1 << 2; | 2217 | xhci->error_bitmask |= 1 << 2; |
1959 | return; | 2218 | return 0; |
1960 | } | 2219 | } |
1961 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); | ||
1962 | 2220 | ||
2221 | /* | ||
2222 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | ||
2223 | * speculative reads of the event's flags/data below. | ||
2224 | */ | ||
2225 | rmb(); | ||
1963 | /* FIXME: Handle more event types. */ | 2226 | /* FIXME: Handle more event types. */ |
1964 | switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { | 2227 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
1965 | case TRB_TYPE(TRB_COMPLETION): | 2228 | case TRB_TYPE(TRB_COMPLETION): |
1966 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); | ||
1967 | handle_cmd_completion(xhci, &event->event_cmd); | 2229 | handle_cmd_completion(xhci, &event->event_cmd); |
1968 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); | ||
1969 | break; | 2230 | break; |
1970 | case TRB_TYPE(TRB_PORT_STATUS): | 2231 | case TRB_TYPE(TRB_PORT_STATUS): |
1971 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); | ||
1972 | handle_port_status(xhci, event); | 2232 | handle_port_status(xhci, event); |
1973 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); | ||
1974 | update_ptrs = 0; | 2233 | update_ptrs = 0; |
1975 | break; | 2234 | break; |
1976 | case TRB_TYPE(TRB_TRANSFER): | 2235 | case TRB_TYPE(TRB_TRANSFER): |
1977 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); | ||
1978 | ret = handle_tx_event(xhci, &event->trans_event); | 2236 | ret = handle_tx_event(xhci, &event->trans_event); |
1979 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); | ||
1980 | if (ret < 0) | 2237 | if (ret < 0) |
1981 | xhci->error_bitmask |= 1 << 9; | 2238 | xhci->error_bitmask |= 1 << 9; |
1982 | else | 2239 | else |
1983 | update_ptrs = 0; | 2240 | update_ptrs = 0; |
1984 | break; | 2241 | break; |
1985 | default: | 2242 | default: |
1986 | if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48)) | 2243 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2244 | TRB_TYPE(48)) | ||
1987 | handle_vendor_event(xhci, event); | 2245 | handle_vendor_event(xhci, event); |
1988 | else | 2246 | else |
1989 | xhci->error_bitmask |= 1 << 3; | 2247 | xhci->error_bitmask |= 1 << 3; |
@@ -1994,15 +2252,17 @@ static void xhci_handle_event(struct xhci_hcd *xhci) | |||
1994 | if (xhci->xhc_state & XHCI_STATE_DYING) { | 2252 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
1995 | xhci_dbg(xhci, "xHCI host dying, returning from " | 2253 | xhci_dbg(xhci, "xHCI host dying, returning from " |
1996 | "event handler.\n"); | 2254 | "event handler.\n"); |
1997 | return; | 2255 | return 0; |
1998 | } | 2256 | } |
1999 | 2257 | ||
2000 | if (update_ptrs) | 2258 | if (update_ptrs) |
2001 | /* Update SW event ring dequeue pointer */ | 2259 | /* Update SW event ring dequeue pointer */ |
2002 | inc_deq(xhci, xhci->event_ring, true); | 2260 | inc_deq(xhci, xhci->event_ring, true); |
2003 | 2261 | ||
2004 | /* Are there more items on the event ring? */ | 2262 | /* Are there more items on the event ring? Caller will call us again to |
2005 | xhci_handle_event(xhci); | 2263 | * check. |
2264 | */ | ||
2265 | return 1; | ||
2006 | } | 2266 | } |
2007 | 2267 | ||
2008 | /* | 2268 | /* |
@@ -2028,24 +2288,12 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) | |||
2028 | 2288 | ||
2029 | if (!(status & STS_EINT)) { | 2289 | if (!(status & STS_EINT)) { |
2030 | spin_unlock(&xhci->lock); | 2290 | spin_unlock(&xhci->lock); |
2031 | xhci_warn(xhci, "Spurious interrupt.\n"); | ||
2032 | return IRQ_NONE; | 2291 | return IRQ_NONE; |
2033 | } | 2292 | } |
2034 | xhci_dbg(xhci, "op reg status = %08x\n", status); | ||
2035 | xhci_dbg(xhci, "Event ring dequeue ptr:\n"); | ||
2036 | xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n", | ||
2037 | (unsigned long long) | ||
2038 | xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb), | ||
2039 | lower_32_bits(trb->link.segment_ptr), | ||
2040 | upper_32_bits(trb->link.segment_ptr), | ||
2041 | (unsigned int) trb->link.intr_target, | ||
2042 | (unsigned int) trb->link.control); | ||
2043 | |||
2044 | if (status & STS_FATAL) { | 2293 | if (status & STS_FATAL) { |
2045 | xhci_warn(xhci, "WARNING: Host System Error\n"); | 2294 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2046 | xhci_halt(xhci); | 2295 | xhci_halt(xhci); |
2047 | hw_died: | 2296 | hw_died: |
2048 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | ||
2049 | spin_unlock(&xhci->lock); | 2297 | spin_unlock(&xhci->lock); |
2050 | return -ESHUTDOWN; | 2298 | return -ESHUTDOWN; |
2051 | } | 2299 | } |
@@ -2086,7 +2334,7 @@ hw_died: | |||
2086 | /* FIXME this should be a delayed service routine | 2334 | /* FIXME this should be a delayed service routine |
2087 | * that clears the EHB. | 2335 | * that clears the EHB. |
2088 | */ | 2336 | */ |
2089 | xhci_handle_event(xhci); | 2337 | while (xhci_handle_event(xhci) > 0) {} |
2090 | 2338 | ||
2091 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | 2339 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
2092 | /* If necessary, update the HW's version of the event ring deq ptr. */ | 2340 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
@@ -2113,8 +2361,12 @@ hw_died: | |||
2113 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) | 2361 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) |
2114 | { | 2362 | { |
2115 | irqreturn_t ret; | 2363 | irqreturn_t ret; |
2364 | struct xhci_hcd *xhci; | ||
2116 | 2365 | ||
2366 | xhci = hcd_to_xhci(hcd); | ||
2117 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); | 2367 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); |
2368 | if (xhci->shared_hcd) | ||
2369 | set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags); | ||
2118 | 2370 | ||
2119 | ret = xhci_irq(hcd); | 2371 | ret = xhci_irq(hcd); |
2120 | 2372 | ||
@@ -2137,10 +2389,10 @@ static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |||
2137 | struct xhci_generic_trb *trb; | 2389 | struct xhci_generic_trb *trb; |
2138 | 2390 | ||
2139 | trb = &ring->enqueue->generic; | 2391 | trb = &ring->enqueue->generic; |
2140 | trb->field[0] = field1; | 2392 | trb->field[0] = cpu_to_le32(field1); |
2141 | trb->field[1] = field2; | 2393 | trb->field[1] = cpu_to_le32(field2); |
2142 | trb->field[2] = field3; | 2394 | trb->field[2] = cpu_to_le32(field3); |
2143 | trb->field[3] = field4; | 2395 | trb->field[3] = cpu_to_le32(field4); |
2144 | inc_enq(xhci, ring, consumer, more_trbs_coming); | 2396 | inc_enq(xhci, ring, consumer, more_trbs_coming); |
2145 | } | 2397 | } |
2146 | 2398 | ||
@@ -2152,7 +2404,6 @@ static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |||
2152 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) | 2404 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
2153 | { | 2405 | { |
2154 | /* Make sure the endpoint has been added to xHC schedule */ | 2406 | /* Make sure the endpoint has been added to xHC schedule */ |
2155 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); | ||
2156 | switch (ep_state) { | 2407 | switch (ep_state) { |
2157 | case EP_STATE_DISABLED: | 2408 | case EP_STATE_DISABLED: |
2158 | /* | 2409 | /* |
@@ -2189,21 +2440,19 @@ static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |||
2189 | struct xhci_ring *ring = ep_ring; | 2440 | struct xhci_ring *ring = ep_ring; |
2190 | union xhci_trb *next; | 2441 | union xhci_trb *next; |
2191 | 2442 | ||
2192 | xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); | ||
2193 | next = ring->enqueue; | 2443 | next = ring->enqueue; |
2194 | 2444 | ||
2195 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | 2445 | while (last_trb(xhci, ring, ring->enq_seg, next)) { |
2196 | |||
2197 | /* If we're not dealing with 0.95 hardware, | 2446 | /* If we're not dealing with 0.95 hardware, |
2198 | * clear the chain bit. | 2447 | * clear the chain bit. |
2199 | */ | 2448 | */ |
2200 | if (!xhci_link_trb_quirk(xhci)) | 2449 | if (!xhci_link_trb_quirk(xhci)) |
2201 | next->link.control &= ~TRB_CHAIN; | 2450 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
2202 | else | 2451 | else |
2203 | next->link.control |= TRB_CHAIN; | 2452 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
2204 | 2453 | ||
2205 | wmb(); | 2454 | wmb(); |
2206 | next->link.control ^= (u32) TRB_CYCLE; | 2455 | next->link.control ^= cpu_to_le32((u32) TRB_CYCLE); |
2207 | 2456 | ||
2208 | /* Toggle the cycle bit after the last ring segment. */ | 2457 | /* Toggle the cycle bit after the last ring segment. */ |
2209 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | 2458 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { |
@@ -2246,8 +2495,8 @@ static int prepare_transfer(struct xhci_hcd *xhci, | |||
2246 | } | 2495 | } |
2247 | 2496 | ||
2248 | ret = prepare_ring(xhci, ep_ring, | 2497 | ret = prepare_ring(xhci, ep_ring, |
2249 | ep_ctx->ep_info & EP_STATE_MASK, | 2498 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
2250 | num_trbs, mem_flags); | 2499 | num_trbs, mem_flags); |
2251 | if (ret) | 2500 | if (ret) |
2252 | return ret; | 2501 | return ret; |
2253 | 2502 | ||
@@ -2258,7 +2507,7 @@ static int prepare_transfer(struct xhci_hcd *xhci, | |||
2258 | INIT_LIST_HEAD(&td->cancelled_td_list); | 2507 | INIT_LIST_HEAD(&td->cancelled_td_list); |
2259 | 2508 | ||
2260 | if (td_index == 0) { | 2509 | if (td_index == 0) { |
2261 | ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); | 2510 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
2262 | if (unlikely(ret)) { | 2511 | if (unlikely(ret)) { |
2263 | xhci_urb_free_priv(xhci, urb_priv); | 2512 | xhci_urb_free_priv(xhci, urb_priv); |
2264 | urb->hcpriv = NULL; | 2513 | urb->hcpriv = NULL; |
@@ -2294,12 +2543,13 @@ static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) | |||
2294 | 2543 | ||
2295 | /* Scatter gather list entries may cross 64KB boundaries */ | 2544 | /* Scatter gather list entries may cross 64KB boundaries */ |
2296 | running_total = TRB_MAX_BUFF_SIZE - | 2545 | running_total = TRB_MAX_BUFF_SIZE - |
2297 | (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | 2546 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
2547 | running_total &= TRB_MAX_BUFF_SIZE - 1; | ||
2298 | if (running_total != 0) | 2548 | if (running_total != 0) |
2299 | num_trbs++; | 2549 | num_trbs++; |
2300 | 2550 | ||
2301 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | 2551 | /* How many more 64KB chunks to transfer, how many more TRBs? */ |
2302 | while (running_total < sg_dma_len(sg)) { | 2552 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
2303 | num_trbs++; | 2553 | num_trbs++; |
2304 | running_total += TRB_MAX_BUFF_SIZE; | 2554 | running_total += TRB_MAX_BUFF_SIZE; |
2305 | } | 2555 | } |
@@ -2314,7 +2564,8 @@ static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) | |||
2314 | } | 2564 | } |
2315 | xhci_dbg(xhci, "\n"); | 2565 | xhci_dbg(xhci, "\n"); |
2316 | if (!in_interrupt()) | 2566 | if (!in_interrupt()) |
2317 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n", | 2567 | xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, " |
2568 | "num_trbs = %d\n", | ||
2318 | urb->ep->desc.bEndpointAddress, | 2569 | urb->ep->desc.bEndpointAddress, |
2319 | urb->transfer_buffer_length, | 2570 | urb->transfer_buffer_length, |
2320 | num_trbs); | 2571 | num_trbs); |
@@ -2324,11 +2575,11 @@ static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) | |||
2324 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) | 2575 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
2325 | { | 2576 | { |
2326 | if (num_trbs != 0) | 2577 | if (num_trbs != 0) |
2327 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " | 2578 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
2328 | "TRBs, %d left\n", __func__, | 2579 | "TRBs, %d left\n", __func__, |
2329 | urb->ep->desc.bEndpointAddress, num_trbs); | 2580 | urb->ep->desc.bEndpointAddress, num_trbs); |
2330 | if (running_total != urb->transfer_buffer_length) | 2581 | if (running_total != urb->transfer_buffer_length) |
2331 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " | 2582 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
2332 | "queued %#x (%d), asked for %#x (%d)\n", | 2583 | "queued %#x (%d), asked for %#x (%d)\n", |
2333 | __func__, | 2584 | __func__, |
2334 | urb->ep->desc.bEndpointAddress, | 2585 | urb->ep->desc.bEndpointAddress, |
@@ -2339,15 +2590,18 @@ static void check_trb_math(struct urb *urb, int num_trbs, int running_total) | |||
2339 | 2590 | ||
2340 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, | 2591 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
2341 | unsigned int ep_index, unsigned int stream_id, int start_cycle, | 2592 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
2342 | struct xhci_generic_trb *start_trb, struct xhci_td *td) | 2593 | struct xhci_generic_trb *start_trb) |
2343 | { | 2594 | { |
2344 | /* | 2595 | /* |
2345 | * Pass all the TRBs to the hardware at once and make sure this write | 2596 | * Pass all the TRBs to the hardware at once and make sure this write |
2346 | * isn't reordered. | 2597 | * isn't reordered. |
2347 | */ | 2598 | */ |
2348 | wmb(); | 2599 | wmb(); |
2349 | start_trb->field[3] |= start_cycle; | 2600 | if (start_cycle) |
2350 | ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); | 2601 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
2602 | else | ||
2603 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); | ||
2604 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); | ||
2351 | } | 2605 | } |
2352 | 2606 | ||
2353 | /* | 2607 | /* |
@@ -2364,7 +2618,7 @@ int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2364 | int xhci_interval; | 2618 | int xhci_interval; |
2365 | int ep_interval; | 2619 | int ep_interval; |
2366 | 2620 | ||
2367 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | 2621 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
2368 | ep_interval = urb->interval; | 2622 | ep_interval = urb->interval; |
2369 | /* Convert to microframes */ | 2623 | /* Convert to microframes */ |
2370 | if (urb->dev->speed == USB_SPEED_LOW || | 2624 | if (urb->dev->speed == USB_SPEED_LOW || |
@@ -2374,7 +2628,7 @@ int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2374 | * to set the polling interval (once the API is added). | 2628 | * to set the polling interval (once the API is added). |
2375 | */ | 2629 | */ |
2376 | if (xhci_interval != ep_interval) { | 2630 | if (xhci_interval != ep_interval) { |
2377 | if (!printk_ratelimit()) | 2631 | if (printk_ratelimit()) |
2378 | dev_dbg(&urb->dev->dev, "Driver uses different interval" | 2632 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
2379 | " (%d microframe%s) than xHCI " | 2633 | " (%d microframe%s) than xHCI " |
2380 | "(%d microframe%s)\n", | 2634 | "(%d microframe%s)\n", |
@@ -2406,6 +2660,35 @@ static u32 xhci_td_remainder(unsigned int remainder) | |||
2406 | return (remainder >> 10) << 17; | 2660 | return (remainder >> 10) << 17; |
2407 | } | 2661 | } |
2408 | 2662 | ||
2663 | /* | ||
2664 | * For xHCI 1.0 host controllers, TD size is the number of packets remaining in | ||
2665 | * the TD (*not* including this TRB). | ||
2666 | * | ||
2667 | * Total TD packet count = total_packet_count = | ||
2668 | * roundup(TD size in bytes / wMaxPacketSize) | ||
2669 | * | ||
2670 | * Packets transferred up to and including this TRB = packets_transferred = | ||
2671 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | ||
2672 | * | ||
2673 | * TD size = total_packet_count - packets_transferred | ||
2674 | * | ||
2675 | * It must fit in bits 21:17, so it can't be bigger than 31. | ||
2676 | */ | ||
2677 | |||
2678 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, | ||
2679 | unsigned int total_packet_count, struct urb *urb) | ||
2680 | { | ||
2681 | int packets_transferred; | ||
2682 | |||
2683 | /* All the TRB queueing functions don't count the current TRB in | ||
2684 | * running_total. | ||
2685 | */ | ||
2686 | packets_transferred = (running_total + trb_buff_len) / | ||
2687 | le16_to_cpu(urb->ep->desc.wMaxPacketSize); | ||
2688 | |||
2689 | return xhci_td_remainder(total_packet_count - packets_transferred); | ||
2690 | } | ||
2691 | |||
2409 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | 2692 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
2410 | struct urb *urb, int slot_id, unsigned int ep_index) | 2693 | struct urb *urb, int slot_id, unsigned int ep_index) |
2411 | { | 2694 | { |
@@ -2416,6 +2699,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2416 | struct scatterlist *sg; | 2699 | struct scatterlist *sg; |
2417 | int num_sgs; | 2700 | int num_sgs; |
2418 | int trb_buff_len, this_sg_len, running_total; | 2701 | int trb_buff_len, this_sg_len, running_total; |
2702 | unsigned int total_packet_count; | ||
2419 | bool first_trb; | 2703 | bool first_trb; |
2420 | u64 addr; | 2704 | u64 addr; |
2421 | bool more_trbs_coming; | 2705 | bool more_trbs_coming; |
@@ -2429,6 +2713,8 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2429 | 2713 | ||
2430 | num_trbs = count_sg_trbs_needed(xhci, urb); | 2714 | num_trbs = count_sg_trbs_needed(xhci, urb); |
2431 | num_sgs = urb->num_sgs; | 2715 | num_sgs = urb->num_sgs; |
2716 | total_packet_count = roundup(urb->transfer_buffer_length, | ||
2717 | le16_to_cpu(urb->ep->desc.wMaxPacketSize)); | ||
2432 | 2718 | ||
2433 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], | 2719 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
2434 | ep_index, urb->stream_id, | 2720 | ep_index, urb->stream_id, |
@@ -2460,8 +2746,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2460 | sg = urb->sg; | 2746 | sg = urb->sg; |
2461 | addr = (u64) sg_dma_address(sg); | 2747 | addr = (u64) sg_dma_address(sg); |
2462 | this_sg_len = sg_dma_len(sg); | 2748 | this_sg_len = sg_dma_len(sg); |
2463 | trb_buff_len = TRB_MAX_BUFF_SIZE - | 2749 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
2464 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | ||
2465 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | 2750 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
2466 | if (trb_buff_len > urb->transfer_buffer_length) | 2751 | if (trb_buff_len > urb->transfer_buffer_length) |
2467 | trb_buff_len = urb->transfer_buffer_length; | 2752 | trb_buff_len = urb->transfer_buffer_length; |
@@ -2476,9 +2761,11 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2476 | u32 remainder = 0; | 2761 | u32 remainder = 0; |
2477 | 2762 | ||
2478 | /* Don't change the cycle bit of the first TRB until later */ | 2763 | /* Don't change the cycle bit of the first TRB until later */ |
2479 | if (first_trb) | 2764 | if (first_trb) { |
2480 | first_trb = false; | 2765 | first_trb = false; |
2481 | else | 2766 | if (start_cycle == 0) |
2767 | field |= 0x1; | ||
2768 | } else | ||
2482 | field |= ep_ring->cycle_state; | 2769 | field |= ep_ring->cycle_state; |
2483 | 2770 | ||
2484 | /* Chain all the TRBs together; clear the chain bit in the last | 2771 | /* Chain all the TRBs together; clear the chain bit in the last |
@@ -2491,23 +2778,37 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2491 | td->last_trb = ep_ring->enqueue; | 2778 | td->last_trb = ep_ring->enqueue; |
2492 | field |= TRB_IOC; | 2779 | field |= TRB_IOC; |
2493 | } | 2780 | } |
2781 | |||
2782 | /* Only set interrupt on short packet for IN endpoints */ | ||
2783 | if (usb_urb_dir_in(urb)) | ||
2784 | field |= TRB_ISP; | ||
2785 | |||
2494 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " | 2786 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " |
2495 | "64KB boundary at %#x, end dma = %#x\n", | 2787 | "64KB boundary at %#x, end dma = %#x\n", |
2496 | (unsigned int) addr, trb_buff_len, trb_buff_len, | 2788 | (unsigned int) addr, trb_buff_len, trb_buff_len, |
2497 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | 2789 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), |
2498 | (unsigned int) addr + trb_buff_len); | 2790 | (unsigned int) addr + trb_buff_len); |
2499 | if (TRB_MAX_BUFF_SIZE - | 2791 | if (TRB_MAX_BUFF_SIZE - |
2500 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { | 2792 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
2501 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); | 2793 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
2502 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | 2794 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", |
2503 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | 2795 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), |
2504 | (unsigned int) addr + trb_buff_len); | 2796 | (unsigned int) addr + trb_buff_len); |
2505 | } | 2797 | } |
2506 | remainder = xhci_td_remainder(urb->transfer_buffer_length - | 2798 | |
2507 | running_total) ; | 2799 | /* Set the TRB length, TD size, and interrupter fields. */ |
2800 | if (xhci->hci_version < 0x100) { | ||
2801 | remainder = xhci_td_remainder( | ||
2802 | urb->transfer_buffer_length - | ||
2803 | running_total); | ||
2804 | } else { | ||
2805 | remainder = xhci_v1_0_td_remainder(running_total, | ||
2806 | trb_buff_len, total_packet_count, urb); | ||
2807 | } | ||
2508 | length_field = TRB_LEN(trb_buff_len) | | 2808 | length_field = TRB_LEN(trb_buff_len) | |
2509 | remainder | | 2809 | remainder | |
2510 | TRB_INTR_TARGET(0); | 2810 | TRB_INTR_TARGET(0); |
2811 | |||
2511 | if (num_trbs > 1) | 2812 | if (num_trbs > 1) |
2512 | more_trbs_coming = true; | 2813 | more_trbs_coming = true; |
2513 | else | 2814 | else |
@@ -2516,12 +2817,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2516 | lower_32_bits(addr), | 2817 | lower_32_bits(addr), |
2517 | upper_32_bits(addr), | 2818 | upper_32_bits(addr), |
2518 | length_field, | 2819 | length_field, |
2519 | /* We always want to know if the TRB was short, | 2820 | field | TRB_TYPE(TRB_NORMAL)); |
2520 | * or we won't get an event when it completes. | ||
2521 | * (Unless we use event data TRBs, which are a | ||
2522 | * waste of space and HC resources.) | ||
2523 | */ | ||
2524 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | ||
2525 | --num_trbs; | 2821 | --num_trbs; |
2526 | running_total += trb_buff_len; | 2822 | running_total += trb_buff_len; |
2527 | 2823 | ||
@@ -2541,7 +2837,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2541 | } | 2837 | } |
2542 | 2838 | ||
2543 | trb_buff_len = TRB_MAX_BUFF_SIZE - | 2839 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
2544 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | 2840 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
2545 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | 2841 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
2546 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | 2842 | if (running_total + trb_buff_len > urb->transfer_buffer_length) |
2547 | trb_buff_len = | 2843 | trb_buff_len = |
@@ -2550,7 +2846,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2550 | 2846 | ||
2551 | check_trb_math(urb, num_trbs, running_total); | 2847 | check_trb_math(urb, num_trbs, running_total); |
2552 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, | 2848 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
2553 | start_cycle, start_trb, td); | 2849 | start_cycle, start_trb); |
2554 | return 0; | 2850 | return 0; |
2555 | } | 2851 | } |
2556 | 2852 | ||
@@ -2569,6 +2865,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2569 | u32 field, length_field; | 2865 | u32 field, length_field; |
2570 | 2866 | ||
2571 | int running_total, trb_buff_len, ret; | 2867 | int running_total, trb_buff_len, ret; |
2868 | unsigned int total_packet_count; | ||
2572 | u64 addr; | 2869 | u64 addr; |
2573 | 2870 | ||
2574 | if (urb->num_sgs) | 2871 | if (urb->num_sgs) |
@@ -2581,7 +2878,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2581 | num_trbs = 0; | 2878 | num_trbs = 0; |
2582 | /* How much data is (potentially) left before the 64KB boundary? */ | 2879 | /* How much data is (potentially) left before the 64KB boundary? */ |
2583 | running_total = TRB_MAX_BUFF_SIZE - | 2880 | running_total = TRB_MAX_BUFF_SIZE - |
2584 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | 2881 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
2882 | running_total &= TRB_MAX_BUFF_SIZE - 1; | ||
2585 | 2883 | ||
2586 | /* If there's some data on this 64KB chunk, or we have to send a | 2884 | /* If there's some data on this 64KB chunk, or we have to send a |
2587 | * zero-length transfer, we need at least one TRB | 2885 | * zero-length transfer, we need at least one TRB |
@@ -2596,7 +2894,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2596 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | 2894 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ |
2597 | 2895 | ||
2598 | if (!in_interrupt()) | 2896 | if (!in_interrupt()) |
2599 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n", | 2897 | xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), " |
2898 | "addr = %#llx, num_trbs = %d\n", | ||
2600 | urb->ep->desc.bEndpointAddress, | 2899 | urb->ep->desc.bEndpointAddress, |
2601 | urb->transfer_buffer_length, | 2900 | urb->transfer_buffer_length, |
2602 | urb->transfer_buffer_length, | 2901 | urb->transfer_buffer_length, |
@@ -2621,11 +2920,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2621 | start_cycle = ep_ring->cycle_state; | 2920 | start_cycle = ep_ring->cycle_state; |
2622 | 2921 | ||
2623 | running_total = 0; | 2922 | running_total = 0; |
2923 | total_packet_count = roundup(urb->transfer_buffer_length, | ||
2924 | le16_to_cpu(urb->ep->desc.wMaxPacketSize)); | ||
2624 | /* How much data is in the first TRB? */ | 2925 | /* How much data is in the first TRB? */ |
2625 | addr = (u64) urb->transfer_dma; | 2926 | addr = (u64) urb->transfer_dma; |
2626 | trb_buff_len = TRB_MAX_BUFF_SIZE - | 2927 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
2627 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | 2928 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
2628 | if (urb->transfer_buffer_length < trb_buff_len) | 2929 | if (trb_buff_len > urb->transfer_buffer_length) |
2629 | trb_buff_len = urb->transfer_buffer_length; | 2930 | trb_buff_len = urb->transfer_buffer_length; |
2630 | 2931 | ||
2631 | first_trb = true; | 2932 | first_trb = true; |
@@ -2636,9 +2937,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2636 | field = 0; | 2937 | field = 0; |
2637 | 2938 | ||
2638 | /* Don't change the cycle bit of the first TRB until later */ | 2939 | /* Don't change the cycle bit of the first TRB until later */ |
2639 | if (first_trb) | 2940 | if (first_trb) { |
2640 | first_trb = false; | 2941 | first_trb = false; |
2641 | else | 2942 | if (start_cycle == 0) |
2943 | field |= 0x1; | ||
2944 | } else | ||
2642 | field |= ep_ring->cycle_state; | 2945 | field |= ep_ring->cycle_state; |
2643 | 2946 | ||
2644 | /* Chain all the TRBs together; clear the chain bit in the last | 2947 | /* Chain all the TRBs together; clear the chain bit in the last |
@@ -2651,11 +2954,24 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2651 | td->last_trb = ep_ring->enqueue; | 2954 | td->last_trb = ep_ring->enqueue; |
2652 | field |= TRB_IOC; | 2955 | field |= TRB_IOC; |
2653 | } | 2956 | } |
2654 | remainder = xhci_td_remainder(urb->transfer_buffer_length - | 2957 | |
2655 | running_total); | 2958 | /* Only set interrupt on short packet for IN endpoints */ |
2959 | if (usb_urb_dir_in(urb)) | ||
2960 | field |= TRB_ISP; | ||
2961 | |||
2962 | /* Set the TRB length, TD size, and interrupter fields. */ | ||
2963 | if (xhci->hci_version < 0x100) { | ||
2964 | remainder = xhci_td_remainder( | ||
2965 | urb->transfer_buffer_length - | ||
2966 | running_total); | ||
2967 | } else { | ||
2968 | remainder = xhci_v1_0_td_remainder(running_total, | ||
2969 | trb_buff_len, total_packet_count, urb); | ||
2970 | } | ||
2656 | length_field = TRB_LEN(trb_buff_len) | | 2971 | length_field = TRB_LEN(trb_buff_len) | |
2657 | remainder | | 2972 | remainder | |
2658 | TRB_INTR_TARGET(0); | 2973 | TRB_INTR_TARGET(0); |
2974 | |||
2659 | if (num_trbs > 1) | 2975 | if (num_trbs > 1) |
2660 | more_trbs_coming = true; | 2976 | more_trbs_coming = true; |
2661 | else | 2977 | else |
@@ -2664,12 +2980,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2664 | lower_32_bits(addr), | 2980 | lower_32_bits(addr), |
2665 | upper_32_bits(addr), | 2981 | upper_32_bits(addr), |
2666 | length_field, | 2982 | length_field, |
2667 | /* We always want to know if the TRB was short, | 2983 | field | TRB_TYPE(TRB_NORMAL)); |
2668 | * or we won't get an event when it completes. | ||
2669 | * (Unless we use event data TRBs, which are a | ||
2670 | * waste of space and HC resources.) | ||
2671 | */ | ||
2672 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | ||
2673 | --num_trbs; | 2984 | --num_trbs; |
2674 | running_total += trb_buff_len; | 2985 | running_total += trb_buff_len; |
2675 | 2986 | ||
@@ -2682,7 +2993,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2682 | 2993 | ||
2683 | check_trb_math(urb, num_trbs, running_total); | 2994 | check_trb_math(urb, num_trbs, running_total); |
2684 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, | 2995 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
2685 | start_cycle, start_trb, td); | 2996 | start_cycle, start_trb); |
2686 | return 0; | 2997 | return 0; |
2687 | } | 2998 | } |
2688 | 2999 | ||
@@ -2743,16 +3054,35 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2743 | /* Queue setup TRB - see section 6.4.1.2.1 */ | 3054 | /* Queue setup TRB - see section 6.4.1.2.1 */ |
2744 | /* FIXME better way to translate setup_packet into two u32 fields? */ | 3055 | /* FIXME better way to translate setup_packet into two u32 fields? */ |
2745 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | 3056 | setup = (struct usb_ctrlrequest *) urb->setup_packet; |
3057 | field = 0; | ||
3058 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | ||
3059 | if (start_cycle == 0) | ||
3060 | field |= 0x1; | ||
3061 | |||
3062 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ | ||
3063 | if (xhci->hci_version == 0x100) { | ||
3064 | if (urb->transfer_buffer_length > 0) { | ||
3065 | if (setup->bRequestType & USB_DIR_IN) | ||
3066 | field |= TRB_TX_TYPE(TRB_DATA_IN); | ||
3067 | else | ||
3068 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | ||
3069 | } | ||
3070 | } | ||
3071 | |||
2746 | queue_trb(xhci, ep_ring, false, true, | 3072 | queue_trb(xhci, ep_ring, false, true, |
2747 | /* FIXME endianness is probably going to bite my ass here. */ | 3073 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
2748 | setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, | 3074 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, |
2749 | setup->wIndex | setup->wLength << 16, | 3075 | TRB_LEN(8) | TRB_INTR_TARGET(0), |
2750 | TRB_LEN(8) | TRB_INTR_TARGET(0), | 3076 | /* Immediate data in pointer */ |
2751 | /* Immediate data in pointer */ | 3077 | field); |
2752 | TRB_IDT | TRB_TYPE(TRB_SETUP)); | ||
2753 | 3078 | ||
2754 | /* If there's data, queue data TRBs */ | 3079 | /* If there's data, queue data TRBs */ |
2755 | field = 0; | 3080 | /* Only set interrupt on short packet for IN endpoints */ |
3081 | if (usb_urb_dir_in(urb)) | ||
3082 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | ||
3083 | else | ||
3084 | field = TRB_TYPE(TRB_DATA); | ||
3085 | |||
2756 | length_field = TRB_LEN(urb->transfer_buffer_length) | | 3086 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
2757 | xhci_td_remainder(urb->transfer_buffer_length) | | 3087 | xhci_td_remainder(urb->transfer_buffer_length) | |
2758 | TRB_INTR_TARGET(0); | 3088 | TRB_INTR_TARGET(0); |
@@ -2763,8 +3093,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2763 | lower_32_bits(urb->transfer_dma), | 3093 | lower_32_bits(urb->transfer_dma), |
2764 | upper_32_bits(urb->transfer_dma), | 3094 | upper_32_bits(urb->transfer_dma), |
2765 | length_field, | 3095 | length_field, |
2766 | /* Event on short tx */ | 3096 | field | ep_ring->cycle_state); |
2767 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); | ||
2768 | } | 3097 | } |
2769 | 3098 | ||
2770 | /* Save the DMA address of the last TRB in the TD */ | 3099 | /* Save the DMA address of the last TRB in the TD */ |
@@ -2784,7 +3113,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2784 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | 3113 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); |
2785 | 3114 | ||
2786 | giveback_first_trb(xhci, slot_id, ep_index, 0, | 3115 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
2787 | start_cycle, start_trb, td); | 3116 | start_cycle, start_trb); |
2788 | return 0; | 3117 | return 0; |
2789 | } | 3118 | } |
2790 | 3119 | ||
@@ -2797,8 +3126,8 @@ static int count_isoc_trbs_needed(struct xhci_hcd *xhci, | |||
2797 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | 3126 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); |
2798 | td_len = urb->iso_frame_desc[i].length; | 3127 | td_len = urb->iso_frame_desc[i].length; |
2799 | 3128 | ||
2800 | running_total = TRB_MAX_BUFF_SIZE - | 3129 | running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
2801 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | 3130 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
2802 | if (running_total != 0) | 3131 | if (running_total != 0) |
2803 | num_trbs++; | 3132 | num_trbs++; |
2804 | 3133 | ||
@@ -2810,6 +3139,63 @@ static int count_isoc_trbs_needed(struct xhci_hcd *xhci, | |||
2810 | return num_trbs; | 3139 | return num_trbs; |
2811 | } | 3140 | } |
2812 | 3141 | ||
3142 | /* | ||
3143 | * The transfer burst count field of the isochronous TRB defines the number of | ||
3144 | * bursts that are required to move all packets in this TD. Only SuperSpeed | ||
3145 | * devices can burst up to bMaxBurst number of packets per service interval. | ||
3146 | * This field is zero based, meaning a value of zero in the field means one | ||
3147 | * burst. Basically, for everything but SuperSpeed devices, this field will be | ||
3148 | * zero. Only xHCI 1.0 host controllers support this field. | ||
3149 | */ | ||
3150 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | ||
3151 | struct usb_device *udev, | ||
3152 | struct urb *urb, unsigned int total_packet_count) | ||
3153 | { | ||
3154 | unsigned int max_burst; | ||
3155 | |||
3156 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) | ||
3157 | return 0; | ||
3158 | |||
3159 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | ||
3160 | return roundup(total_packet_count, max_burst + 1) - 1; | ||
3161 | } | ||
3162 | |||
3163 | /* | ||
3164 | * Returns the number of packets in the last "burst" of packets. This field is | ||
3165 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | ||
3166 | * the last burst packet count is equal to the total number of packets in the | ||
3167 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | ||
3168 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | ||
3169 | * contain 1 to (bMaxBurst + 1) packets. | ||
3170 | */ | ||
3171 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | ||
3172 | struct usb_device *udev, | ||
3173 | struct urb *urb, unsigned int total_packet_count) | ||
3174 | { | ||
3175 | unsigned int max_burst; | ||
3176 | unsigned int residue; | ||
3177 | |||
3178 | if (xhci->hci_version < 0x100) | ||
3179 | return 0; | ||
3180 | |||
3181 | switch (udev->speed) { | ||
3182 | case USB_SPEED_SUPER: | ||
3183 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ | ||
3184 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | ||
3185 | residue = total_packet_count % (max_burst + 1); | ||
3186 | /* If residue is zero, the last burst contains (max_burst + 1) | ||
3187 | * number of packets, but the TLBPC field is zero-based. | ||
3188 | */ | ||
3189 | if (residue == 0) | ||
3190 | return max_burst; | ||
3191 | return residue - 1; | ||
3192 | default: | ||
3193 | if (total_packet_count == 0) | ||
3194 | return 0; | ||
3195 | return total_packet_count - 1; | ||
3196 | } | ||
3197 | } | ||
3198 | |||
2813 | /* This is for isoc transfer */ | 3199 | /* This is for isoc transfer */ |
2814 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | 3200 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
2815 | struct urb *urb, int slot_id, unsigned int ep_index) | 3201 | struct urb *urb, int slot_id, unsigned int ep_index) |
@@ -2825,6 +3211,7 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2825 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | 3211 | int running_total, trb_buff_len, td_len, td_remain_len, ret; |
2826 | u64 start_addr, addr; | 3212 | u64 start_addr, addr; |
2827 | int i, j; | 3213 | int i, j; |
3214 | bool more_trbs_coming; | ||
2828 | 3215 | ||
2829 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | 3216 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
2830 | 3217 | ||
@@ -2835,7 +3222,7 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2835 | } | 3222 | } |
2836 | 3223 | ||
2837 | if (!in_interrupt()) | 3224 | if (!in_interrupt()) |
2838 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d)," | 3225 | xhci_dbg(xhci, "ep %#x - urb len = %#x (%d)," |
2839 | " addr = %#llx, num_tds = %d\n", | 3226 | " addr = %#llx, num_tds = %d\n", |
2840 | urb->ep->desc.bEndpointAddress, | 3227 | urb->ep->desc.bEndpointAddress, |
2841 | urb->transfer_buffer_length, | 3228 | urb->transfer_buffer_length, |
@@ -2849,12 +3236,22 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2849 | 3236 | ||
2850 | /* Queue the first TRB, even if it's zero-length */ | 3237 | /* Queue the first TRB, even if it's zero-length */ |
2851 | for (i = 0; i < num_tds; i++) { | 3238 | for (i = 0; i < num_tds; i++) { |
2852 | first_trb = true; | 3239 | unsigned int total_packet_count; |
3240 | unsigned int burst_count; | ||
3241 | unsigned int residue; | ||
2853 | 3242 | ||
3243 | first_trb = true; | ||
2854 | running_total = 0; | 3244 | running_total = 0; |
2855 | addr = start_addr + urb->iso_frame_desc[i].offset; | 3245 | addr = start_addr + urb->iso_frame_desc[i].offset; |
2856 | td_len = urb->iso_frame_desc[i].length; | 3246 | td_len = urb->iso_frame_desc[i].length; |
2857 | td_remain_len = td_len; | 3247 | td_remain_len = td_len; |
3248 | /* FIXME: Ignoring zero-length packets, can those happen? */ | ||
3249 | total_packet_count = roundup(td_len, | ||
3250 | le16_to_cpu(urb->ep->desc.wMaxPacketSize)); | ||
3251 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, | ||
3252 | total_packet_count); | ||
3253 | residue = xhci_get_last_burst_packet_count(xhci, | ||
3254 | urb->dev, urb, total_packet_count); | ||
2858 | 3255 | ||
2859 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | 3256 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); |
2860 | 3257 | ||
@@ -2868,14 +3265,17 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2868 | 3265 | ||
2869 | for (j = 0; j < trbs_per_td; j++) { | 3266 | for (j = 0; j < trbs_per_td; j++) { |
2870 | u32 remainder = 0; | 3267 | u32 remainder = 0; |
2871 | field = 0; | 3268 | field = TRB_TBC(burst_count) | TRB_TLBPC(residue); |
2872 | 3269 | ||
2873 | if (first_trb) { | 3270 | if (first_trb) { |
2874 | /* Queue the isoc TRB */ | 3271 | /* Queue the isoc TRB */ |
2875 | field |= TRB_TYPE(TRB_ISOC); | 3272 | field |= TRB_TYPE(TRB_ISOC); |
2876 | /* Assume URB_ISO_ASAP is set */ | 3273 | /* Assume URB_ISO_ASAP is set */ |
2877 | field |= TRB_SIA; | 3274 | field |= TRB_SIA; |
2878 | if (i > 0) | 3275 | if (i == 0) { |
3276 | if (start_cycle == 0) | ||
3277 | field |= 0x1; | ||
3278 | } else | ||
2879 | field |= ep_ring->cycle_state; | 3279 | field |= ep_ring->cycle_state; |
2880 | first_trb = false; | 3280 | first_trb = false; |
2881 | } else { | 3281 | } else { |
@@ -2884,15 +3284,26 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2884 | field |= ep_ring->cycle_state; | 3284 | field |= ep_ring->cycle_state; |
2885 | } | 3285 | } |
2886 | 3286 | ||
3287 | /* Only set interrupt on short packet for IN EPs */ | ||
3288 | if (usb_urb_dir_in(urb)) | ||
3289 | field |= TRB_ISP; | ||
3290 | |||
2887 | /* Chain all the TRBs together; clear the chain bit in | 3291 | /* Chain all the TRBs together; clear the chain bit in |
2888 | * the last TRB to indicate it's the last TRB in the | 3292 | * the last TRB to indicate it's the last TRB in the |
2889 | * chain. | 3293 | * chain. |
2890 | */ | 3294 | */ |
2891 | if (j < trbs_per_td - 1) { | 3295 | if (j < trbs_per_td - 1) { |
2892 | field |= TRB_CHAIN; | 3296 | field |= TRB_CHAIN; |
3297 | more_trbs_coming = true; | ||
2893 | } else { | 3298 | } else { |
2894 | td->last_trb = ep_ring->enqueue; | 3299 | td->last_trb = ep_ring->enqueue; |
2895 | field |= TRB_IOC; | 3300 | field |= TRB_IOC; |
3301 | if (xhci->hci_version == 0x100) { | ||
3302 | /* Set BEI bit except for the last td */ | ||
3303 | if (i < num_tds - 1) | ||
3304 | field |= TRB_BEI; | ||
3305 | } | ||
3306 | more_trbs_coming = false; | ||
2896 | } | 3307 | } |
2897 | 3308 | ||
2898 | /* Calculate TRB length */ | 3309 | /* Calculate TRB length */ |
@@ -2901,20 +3312,24 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2901 | if (trb_buff_len > td_remain_len) | 3312 | if (trb_buff_len > td_remain_len) |
2902 | trb_buff_len = td_remain_len; | 3313 | trb_buff_len = td_remain_len; |
2903 | 3314 | ||
2904 | remainder = xhci_td_remainder(td_len - running_total); | 3315 | /* Set the TRB length, TD size, & interrupter fields. */ |
3316 | if (xhci->hci_version < 0x100) { | ||
3317 | remainder = xhci_td_remainder( | ||
3318 | td_len - running_total); | ||
3319 | } else { | ||
3320 | remainder = xhci_v1_0_td_remainder( | ||
3321 | running_total, trb_buff_len, | ||
3322 | total_packet_count, urb); | ||
3323 | } | ||
2905 | length_field = TRB_LEN(trb_buff_len) | | 3324 | length_field = TRB_LEN(trb_buff_len) | |
2906 | remainder | | 3325 | remainder | |
2907 | TRB_INTR_TARGET(0); | 3326 | TRB_INTR_TARGET(0); |
2908 | queue_trb(xhci, ep_ring, false, false, | 3327 | |
3328 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | ||
2909 | lower_32_bits(addr), | 3329 | lower_32_bits(addr), |
2910 | upper_32_bits(addr), | 3330 | upper_32_bits(addr), |
2911 | length_field, | 3331 | length_field, |
2912 | /* We always want to know if the TRB was short, | 3332 | field); |
2913 | * or we won't get an event when it completes. | ||
2914 | * (Unless we use event data TRBs, which are a | ||
2915 | * waste of space and HC resources.) | ||
2916 | */ | ||
2917 | field | TRB_ISP); | ||
2918 | running_total += trb_buff_len; | 3333 | running_total += trb_buff_len; |
2919 | 3334 | ||
2920 | addr += trb_buff_len; | 3335 | addr += trb_buff_len; |
@@ -2928,10 +3343,14 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2928 | } | 3343 | } |
2929 | } | 3344 | } |
2930 | 3345 | ||
2931 | wmb(); | 3346 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
2932 | start_trb->field[3] |= start_cycle; | 3347 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
3348 | usb_amd_quirk_pll_disable(); | ||
3349 | } | ||
3350 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | ||
2933 | 3351 | ||
2934 | ring_ep_doorbell(xhci, slot_id, ep_index, urb->stream_id); | 3352 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3353 | start_cycle, start_trb); | ||
2935 | return 0; | 3354 | return 0; |
2936 | } | 3355 | } |
2937 | 3356 | ||
@@ -2966,8 +3385,8 @@ int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2966 | /* Check the ring to guarantee there is enough room for the whole urb. | 3385 | /* Check the ring to guarantee there is enough room for the whole urb. |
2967 | * Do not insert any td of the urb to the ring if the check failed. | 3386 | * Do not insert any td of the urb to the ring if the check failed. |
2968 | */ | 3387 | */ |
2969 | ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK, | 3388 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
2970 | num_trbs, mem_flags); | 3389 | num_trbs, mem_flags); |
2971 | if (ret) | 3390 | if (ret) |
2972 | return ret; | 3391 | return ret; |
2973 | 3392 | ||
@@ -2979,7 +3398,7 @@ int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2979 | urb->dev->speed == USB_SPEED_FULL) | 3398 | urb->dev->speed == USB_SPEED_FULL) |
2980 | urb->start_frame >>= 3; | 3399 | urb->start_frame >>= 3; |
2981 | 3400 | ||
2982 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | 3401 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
2983 | ep_interval = urb->interval; | 3402 | ep_interval = urb->interval; |
2984 | /* Convert to microframes */ | 3403 | /* Convert to microframes */ |
2985 | if (urb->dev->speed == USB_SPEED_LOW || | 3404 | if (urb->dev->speed == USB_SPEED_LOW || |
@@ -2989,7 +3408,7 @@ int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |||
2989 | * to set the polling interval (once the API is added). | 3408 | * to set the polling interval (once the API is added). |
2990 | */ | 3409 | */ |
2991 | if (xhci_interval != ep_interval) { | 3410 | if (xhci_interval != ep_interval) { |
2992 | if (!printk_ratelimit()) | 3411 | if (printk_ratelimit()) |
2993 | dev_dbg(&urb->dev->dev, "Driver uses different interval" | 3412 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
2994 | " (%d microframe%s) than xHCI " | 3413 | " (%d microframe%s) than xHCI " |
2995 | "(%d microframe%s)\n", | 3414 | "(%d microframe%s)\n", |
@@ -3039,24 +3458,6 @@ static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |||
3039 | return 0; | 3458 | return 0; |
3040 | } | 3459 | } |
3041 | 3460 | ||
3042 | /* Queue a no-op command on the command ring */ | ||
3043 | static int queue_cmd_noop(struct xhci_hcd *xhci) | ||
3044 | { | ||
3045 | return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false); | ||
3046 | } | ||
3047 | |||
3048 | /* | ||
3049 | * Place a no-op command on the command ring to test the command and | ||
3050 | * event ring. | ||
3051 | */ | ||
3052 | void *xhci_setup_one_noop(struct xhci_hcd *xhci) | ||
3053 | { | ||
3054 | if (queue_cmd_noop(xhci) < 0) | ||
3055 | return NULL; | ||
3056 | xhci->noops_submitted++; | ||
3057 | return xhci_ring_cmd_db; | ||
3058 | } | ||
3059 | |||
3060 | /* Queue a slot enable or disable request on the command ring */ | 3461 | /* Queue a slot enable or disable request on the command ring */ |
3061 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) | 3462 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3062 | { | 3463 | { |
@@ -3108,15 +3509,20 @@ int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |||
3108 | false); | 3509 | false); |
3109 | } | 3510 | } |
3110 | 3511 | ||
3512 | /* | ||
3513 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | ||
3514 | * activity on an endpoint that is about to be suspended. | ||
3515 | */ | ||
3111 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, | 3516 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
3112 | unsigned int ep_index) | 3517 | unsigned int ep_index, int suspend) |
3113 | { | 3518 | { |
3114 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | 3519 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
3115 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | 3520 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
3116 | u32 type = TRB_TYPE(TRB_STOP_RING); | 3521 | u32 type = TRB_TYPE(TRB_STOP_RING); |
3522 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); | ||
3117 | 3523 | ||
3118 | return queue_command(xhci, 0, 0, 0, | 3524 | return queue_command(xhci, 0, 0, 0, |
3119 | trb_slot_id | trb_ep_index | type, false); | 3525 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
3120 | } | 3526 | } |
3121 | 3527 | ||
3122 | /* Set Transfer Ring Dequeue Pointer command. | 3528 | /* Set Transfer Ring Dequeue Pointer command. |
@@ -3132,6 +3538,7 @@ static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |||
3132 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | 3538 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
3133 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); | 3539 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
3134 | u32 type = TRB_TYPE(TRB_SET_DEQ); | 3540 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
3541 | struct xhci_virt_ep *ep; | ||
3135 | 3542 | ||
3136 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); | 3543 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
3137 | if (addr == 0) { | 3544 | if (addr == 0) { |
@@ -3140,6 +3547,14 @@ static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |||
3140 | deq_seg, deq_ptr); | 3547 | deq_seg, deq_ptr); |
3141 | return 0; | 3548 | return 0; |
3142 | } | 3549 | } |
3550 | ep = &xhci->devs[slot_id]->eps[ep_index]; | ||
3551 | if ((ep->ep_state & SET_DEQ_PENDING)) { | ||
3552 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | ||
3553 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | ||
3554 | return 0; | ||
3555 | } | ||
3556 | ep->queued_deq_seg = deq_seg; | ||
3557 | ep->queued_deq_ptr = deq_ptr; | ||
3143 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, | 3558 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
3144 | upper_32_bits(addr), trb_stream_id, | 3559 | upper_32_bits(addr), trb_stream_id, |
3145 | trb_slot_id | trb_ep_index | type, false); | 3560 | trb_slot_id | trb_ep_index | type, false); |
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index d5c550ea3e68..f5fe1ac301ab 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c | |||
@@ -93,23 +93,26 @@ void xhci_quiesce(struct xhci_hcd *xhci) | |||
93 | * | 93 | * |
94 | * Disable any IRQs and clear the run/stop bit. | 94 | * Disable any IRQs and clear the run/stop bit. |
95 | * HC will complete any current and actively pipelined transactions, and | 95 | * HC will complete any current and actively pipelined transactions, and |
96 | * should halt within 16 microframes of the run/stop bit being cleared. | 96 | * should halt within 16 ms of the run/stop bit being cleared. |
97 | * Read HC Halted bit in the status register to see when the HC is finished. | 97 | * Read HC Halted bit in the status register to see when the HC is finished. |
98 | * XXX: shouldn't we set HC_STATE_HALT here somewhere? | ||
99 | */ | 98 | */ |
100 | int xhci_halt(struct xhci_hcd *xhci) | 99 | int xhci_halt(struct xhci_hcd *xhci) |
101 | { | 100 | { |
101 | int ret; | ||
102 | xhci_dbg(xhci, "// Halt the HC\n"); | 102 | xhci_dbg(xhci, "// Halt the HC\n"); |
103 | xhci_quiesce(xhci); | 103 | xhci_quiesce(xhci); |
104 | 104 | ||
105 | return handshake(xhci, &xhci->op_regs->status, | 105 | ret = handshake(xhci, &xhci->op_regs->status, |
106 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); | 106 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
107 | if (!ret) | ||
108 | xhci->xhc_state |= XHCI_STATE_HALTED; | ||
109 | return ret; | ||
107 | } | 110 | } |
108 | 111 | ||
109 | /* | 112 | /* |
110 | * Set the run bit and wait for the host to be running. | 113 | * Set the run bit and wait for the host to be running. |
111 | */ | 114 | */ |
112 | int xhci_start(struct xhci_hcd *xhci) | 115 | static int xhci_start(struct xhci_hcd *xhci) |
113 | { | 116 | { |
114 | u32 temp; | 117 | u32 temp; |
115 | int ret; | 118 | int ret; |
@@ -130,11 +133,13 @@ int xhci_start(struct xhci_hcd *xhci) | |||
130 | xhci_err(xhci, "Host took too long to start, " | 133 | xhci_err(xhci, "Host took too long to start, " |
131 | "waited %u microseconds.\n", | 134 | "waited %u microseconds.\n", |
132 | XHCI_MAX_HALT_USEC); | 135 | XHCI_MAX_HALT_USEC); |
136 | if (!ret) | ||
137 | xhci->xhc_state &= ~XHCI_STATE_HALTED; | ||
133 | return ret; | 138 | return ret; |
134 | } | 139 | } |
135 | 140 | ||
136 | /* | 141 | /* |
137 | * Reset a halted HC, and set the internal HC state to HC_STATE_HALT. | 142 | * Reset a halted HC. |
138 | * | 143 | * |
139 | * This resets pipelines, timers, counters, state machines, etc. | 144 | * This resets pipelines, timers, counters, state machines, etc. |
140 | * Transactions will be terminated immediately, and operational registers | 145 | * Transactions will be terminated immediately, and operational registers |
@@ -156,8 +161,6 @@ int xhci_reset(struct xhci_hcd *xhci) | |||
156 | command = xhci_readl(xhci, &xhci->op_regs->command); | 161 | command = xhci_readl(xhci, &xhci->op_regs->command); |
157 | command |= CMD_RESET; | 162 | command |= CMD_RESET; |
158 | xhci_writel(xhci, command, &xhci->op_regs->command); | 163 | xhci_writel(xhci, command, &xhci->op_regs->command); |
159 | /* XXX: Why does EHCI set this here? Shouldn't other code do this? */ | ||
160 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | ||
161 | 164 | ||
162 | ret = handshake(xhci, &xhci->op_regs->command, | 165 | ret = handshake(xhci, &xhci->op_regs->command, |
163 | CMD_RESET, 0, 250 * 1000); | 166 | CMD_RESET, 0, 250 * 1000); |
@@ -226,7 +229,8 @@ static int xhci_setup_msi(struct xhci_hcd *xhci) | |||
226 | static int xhci_setup_msix(struct xhci_hcd *xhci) | 229 | static int xhci_setup_msix(struct xhci_hcd *xhci) |
227 | { | 230 | { |
228 | int i, ret = 0; | 231 | int i, ret = 0; |
229 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | 232 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
233 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | ||
230 | 234 | ||
231 | /* | 235 | /* |
232 | * calculate number of msi-x vectors supported. | 236 | * calculate number of msi-x vectors supported. |
@@ -265,6 +269,7 @@ static int xhci_setup_msix(struct xhci_hcd *xhci) | |||
265 | goto disable_msix; | 269 | goto disable_msix; |
266 | } | 270 | } |
267 | 271 | ||
272 | hcd->msix_enabled = 1; | ||
268 | return ret; | 273 | return ret; |
269 | 274 | ||
270 | disable_msix: | 275 | disable_msix: |
@@ -280,7 +285,8 @@ free_entries: | |||
280 | /* Free any IRQs and disable MSI-X */ | 285 | /* Free any IRQs and disable MSI-X */ |
281 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | 286 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) |
282 | { | 287 | { |
283 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | 288 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
289 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | ||
284 | 290 | ||
285 | xhci_free_irq(xhci); | 291 | xhci_free_irq(xhci); |
286 | 292 | ||
@@ -292,6 +298,7 @@ static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |||
292 | pci_disable_msi(pdev); | 298 | pci_disable_msi(pdev); |
293 | } | 299 | } |
294 | 300 | ||
301 | hcd->msix_enabled = 0; | ||
295 | return; | 302 | return; |
296 | } | 303 | } |
297 | 304 | ||
@@ -325,7 +332,7 @@ int xhci_init(struct usb_hcd *hcd) | |||
325 | 332 | ||
326 | 333 | ||
327 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | 334 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
328 | void xhci_event_ring_work(unsigned long arg) | 335 | static void xhci_event_ring_work(unsigned long arg) |
329 | { | 336 | { |
330 | unsigned long flags; | 337 | unsigned long flags; |
331 | int temp; | 338 | int temp; |
@@ -346,7 +353,6 @@ void xhci_event_ring_work(unsigned long arg) | |||
346 | 353 | ||
347 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | 354 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
348 | xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp); | 355 | xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp); |
349 | xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled); | ||
350 | xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask); | 356 | xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask); |
351 | xhci->error_bitmask = 0; | 357 | xhci->error_bitmask = 0; |
352 | xhci_dbg(xhci, "Event ring:\n"); | 358 | xhci_dbg(xhci, "Event ring:\n"); |
@@ -366,10 +372,6 @@ void xhci_event_ring_work(unsigned long arg) | |||
366 | xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]); | 372 | xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]); |
367 | } | 373 | } |
368 | } | 374 | } |
369 | |||
370 | if (xhci->noops_submitted != NUM_TEST_NOOPS) | ||
371 | if (xhci_setup_one_noop(xhci)) | ||
372 | xhci_ring_cmd_db(xhci); | ||
373 | spin_unlock_irqrestore(&xhci->lock, flags); | 375 | spin_unlock_irqrestore(&xhci->lock, flags); |
374 | 376 | ||
375 | if (!xhci->zombie) | 377 | if (!xhci->zombie) |
@@ -379,6 +381,21 @@ void xhci_event_ring_work(unsigned long arg) | |||
379 | } | 381 | } |
380 | #endif | 382 | #endif |
381 | 383 | ||
384 | static int xhci_run_finished(struct xhci_hcd *xhci) | ||
385 | { | ||
386 | if (xhci_start(xhci)) { | ||
387 | xhci_halt(xhci); | ||
388 | return -ENODEV; | ||
389 | } | ||
390 | xhci->shared_hcd->state = HC_STATE_RUNNING; | ||
391 | |||
392 | if (xhci->quirks & XHCI_NEC_HOST) | ||
393 | xhci_ring_cmd_db(xhci); | ||
394 | |||
395 | xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n"); | ||
396 | return 0; | ||
397 | } | ||
398 | |||
382 | /* | 399 | /* |
383 | * Start the HC after it was halted. | 400 | * Start the HC after it was halted. |
384 | * | 401 | * |
@@ -398,9 +415,14 @@ int xhci_run(struct usb_hcd *hcd) | |||
398 | u32 ret; | 415 | u32 ret; |
399 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | 416 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
400 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | 417 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
401 | void (*doorbell)(struct xhci_hcd *) = NULL; | 418 | |
419 | /* Start the xHCI host controller running only after the USB 2.0 roothub | ||
420 | * is setup. | ||
421 | */ | ||
402 | 422 | ||
403 | hcd->uses_new_polling = 1; | 423 | hcd->uses_new_polling = 1; |
424 | if (!usb_hcd_is_primary_hcd(hcd)) | ||
425 | return xhci_run_finished(xhci); | ||
404 | 426 | ||
405 | xhci_dbg(xhci, "xhci_run\n"); | 427 | xhci_dbg(xhci, "xhci_run\n"); |
406 | /* unregister the legacy interrupt */ | 428 | /* unregister the legacy interrupt */ |
@@ -408,12 +430,19 @@ int xhci_run(struct usb_hcd *hcd) | |||
408 | free_irq(hcd->irq, hcd); | 430 | free_irq(hcd->irq, hcd); |
409 | hcd->irq = -1; | 431 | hcd->irq = -1; |
410 | 432 | ||
433 | /* Some Fresco Logic host controllers advertise MSI, but fail to | ||
434 | * generate interrupts. Don't even try to enable MSI. | ||
435 | */ | ||
436 | if (xhci->quirks & XHCI_BROKEN_MSI) | ||
437 | goto legacy_irq; | ||
438 | |||
411 | ret = xhci_setup_msix(xhci); | 439 | ret = xhci_setup_msix(xhci); |
412 | if (ret) | 440 | if (ret) |
413 | /* fall back to msi*/ | 441 | /* fall back to msi*/ |
414 | ret = xhci_setup_msi(xhci); | 442 | ret = xhci_setup_msi(xhci); |
415 | 443 | ||
416 | if (ret) { | 444 | if (ret) { |
445 | legacy_irq: | ||
417 | /* fall back to legacy interrupt*/ | 446 | /* fall back to legacy interrupt*/ |
418 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | 447 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, |
419 | hcd->irq_descr, hcd); | 448 | hcd->irq_descr, hcd); |
@@ -457,7 +486,6 @@ int xhci_run(struct usb_hcd *hcd) | |||
457 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); | 486 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); |
458 | 487 | ||
459 | /* Set the HCD state before we enable the irqs */ | 488 | /* Set the HCD state before we enable the irqs */ |
460 | hcd->state = HC_STATE_RUNNING; | ||
461 | temp = xhci_readl(xhci, &xhci->op_regs->command); | 489 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
462 | temp |= (CMD_EIE); | 490 | temp |= (CMD_EIE); |
463 | xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n", | 491 | xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n", |
@@ -469,26 +497,29 @@ int xhci_run(struct usb_hcd *hcd) | |||
469 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); | 497 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
470 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), | 498 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), |
471 | &xhci->ir_set->irq_pending); | 499 | &xhci->ir_set->irq_pending); |
472 | xhci_print_ir_set(xhci, xhci->ir_set, 0); | 500 | xhci_print_ir_set(xhci, 0); |
473 | 501 | ||
474 | if (NUM_TEST_NOOPS > 0) | ||
475 | doorbell = xhci_setup_one_noop(xhci); | ||
476 | if (xhci->quirks & XHCI_NEC_HOST) | 502 | if (xhci->quirks & XHCI_NEC_HOST) |
477 | xhci_queue_vendor_command(xhci, 0, 0, 0, | 503 | xhci_queue_vendor_command(xhci, 0, 0, 0, |
478 | TRB_TYPE(TRB_NEC_GET_FW)); | 504 | TRB_TYPE(TRB_NEC_GET_FW)); |
479 | 505 | ||
480 | if (xhci_start(xhci)) { | 506 | xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n"); |
481 | xhci_halt(xhci); | 507 | return 0; |
482 | return -ENODEV; | 508 | } |
483 | } | ||
484 | 509 | ||
485 | if (doorbell) | 510 | static void xhci_only_stop_hcd(struct usb_hcd *hcd) |
486 | (*doorbell)(xhci); | 511 | { |
487 | if (xhci->quirks & XHCI_NEC_HOST) | 512 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
488 | xhci_ring_cmd_db(xhci); | ||
489 | 513 | ||
490 | xhci_dbg(xhci, "Finished xhci_run\n"); | 514 | spin_lock_irq(&xhci->lock); |
491 | return 0; | 515 | xhci_halt(xhci); |
516 | |||
517 | /* The shared_hcd is going to be deallocated shortly (the USB core only | ||
518 | * calls this function when allocation fails in usb_add_hcd(), or | ||
519 | * usb_remove_hcd() is called). So we need to unset xHCI's pointer. | ||
520 | */ | ||
521 | xhci->shared_hcd = NULL; | ||
522 | spin_unlock_irq(&xhci->lock); | ||
492 | } | 523 | } |
493 | 524 | ||
494 | /* | 525 | /* |
@@ -505,25 +536,37 @@ void xhci_stop(struct usb_hcd *hcd) | |||
505 | u32 temp; | 536 | u32 temp; |
506 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | 537 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
507 | 538 | ||
539 | if (!usb_hcd_is_primary_hcd(hcd)) { | ||
540 | xhci_only_stop_hcd(xhci->shared_hcd); | ||
541 | return; | ||
542 | } | ||
543 | |||
508 | spin_lock_irq(&xhci->lock); | 544 | spin_lock_irq(&xhci->lock); |
545 | /* Make sure the xHC is halted for a USB3 roothub | ||
546 | * (xhci_stop() could be called as part of failed init). | ||
547 | */ | ||
509 | xhci_halt(xhci); | 548 | xhci_halt(xhci); |
510 | xhci_reset(xhci); | 549 | xhci_reset(xhci); |
511 | xhci_cleanup_msix(xhci); | ||
512 | spin_unlock_irq(&xhci->lock); | 550 | spin_unlock_irq(&xhci->lock); |
513 | 551 | ||
552 | xhci_cleanup_msix(xhci); | ||
553 | |||
514 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | 554 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
515 | /* Tell the event ring poll function not to reschedule */ | 555 | /* Tell the event ring poll function not to reschedule */ |
516 | xhci->zombie = 1; | 556 | xhci->zombie = 1; |
517 | del_timer_sync(&xhci->event_ring_timer); | 557 | del_timer_sync(&xhci->event_ring_timer); |
518 | #endif | 558 | #endif |
519 | 559 | ||
560 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | ||
561 | usb_amd_dev_put(); | ||
562 | |||
520 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); | 563 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
521 | temp = xhci_readl(xhci, &xhci->op_regs->status); | 564 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
522 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | 565 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); |
523 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | 566 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
524 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | 567 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), |
525 | &xhci->ir_set->irq_pending); | 568 | &xhci->ir_set->irq_pending); |
526 | xhci_print_ir_set(xhci, xhci->ir_set, 0); | 569 | xhci_print_ir_set(xhci, 0); |
527 | 570 | ||
528 | xhci_dbg(xhci, "cleaning up memory\n"); | 571 | xhci_dbg(xhci, "cleaning up memory\n"); |
529 | xhci_mem_cleanup(xhci); | 572 | xhci_mem_cleanup(xhci); |
@@ -537,6 +580,8 @@ void xhci_stop(struct usb_hcd *hcd) | |||
537 | * This is called when the machine is rebooting or halting. We assume that the | 580 | * This is called when the machine is rebooting or halting. We assume that the |
538 | * machine will be powered off, and the HC's internal state will be reset. | 581 | * machine will be powered off, and the HC's internal state will be reset. |
539 | * Don't bother to free memory. | 582 | * Don't bother to free memory. |
583 | * | ||
584 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | ||
540 | */ | 585 | */ |
541 | void xhci_shutdown(struct usb_hcd *hcd) | 586 | void xhci_shutdown(struct usb_hcd *hcd) |
542 | { | 587 | { |
@@ -544,13 +589,284 @@ void xhci_shutdown(struct usb_hcd *hcd) | |||
544 | 589 | ||
545 | spin_lock_irq(&xhci->lock); | 590 | spin_lock_irq(&xhci->lock); |
546 | xhci_halt(xhci); | 591 | xhci_halt(xhci); |
547 | xhci_cleanup_msix(xhci); | ||
548 | spin_unlock_irq(&xhci->lock); | 592 | spin_unlock_irq(&xhci->lock); |
549 | 593 | ||
594 | xhci_cleanup_msix(xhci); | ||
595 | |||
550 | xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n", | 596 | xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n", |
551 | xhci_readl(xhci, &xhci->op_regs->status)); | 597 | xhci_readl(xhci, &xhci->op_regs->status)); |
552 | } | 598 | } |
553 | 599 | ||
600 | #ifdef CONFIG_PM | ||
601 | static void xhci_save_registers(struct xhci_hcd *xhci) | ||
602 | { | ||
603 | xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command); | ||
604 | xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification); | ||
605 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); | ||
606 | xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg); | ||
607 | xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); | ||
608 | xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control); | ||
609 | xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size); | ||
610 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); | ||
611 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | ||
612 | } | ||
613 | |||
614 | static void xhci_restore_registers(struct xhci_hcd *xhci) | ||
615 | { | ||
616 | xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command); | ||
617 | xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | ||
618 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); | ||
619 | xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg); | ||
620 | xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending); | ||
621 | xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control); | ||
622 | xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size); | ||
623 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); | ||
624 | } | ||
625 | |||
626 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) | ||
627 | { | ||
628 | u64 val_64; | ||
629 | |||
630 | /* step 2: initialize command ring buffer */ | ||
631 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | ||
632 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | ||
633 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | ||
634 | xhci->cmd_ring->dequeue) & | ||
635 | (u64) ~CMD_RING_RSVD_BITS) | | ||
636 | xhci->cmd_ring->cycle_state; | ||
637 | xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n", | ||
638 | (long unsigned long) val_64); | ||
639 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | ||
640 | } | ||
641 | |||
642 | /* | ||
643 | * The whole command ring must be cleared to zero when we suspend the host. | ||
644 | * | ||
645 | * The host doesn't save the command ring pointer in the suspend well, so we | ||
646 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | ||
647 | * aligned, because of the reserved bits in the command ring dequeue pointer | ||
648 | * register. Therefore, we can't just set the dequeue pointer back in the | ||
649 | * middle of the ring (TRBs are 16-byte aligned). | ||
650 | */ | ||
651 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | ||
652 | { | ||
653 | struct xhci_ring *ring; | ||
654 | struct xhci_segment *seg; | ||
655 | |||
656 | ring = xhci->cmd_ring; | ||
657 | seg = ring->deq_seg; | ||
658 | do { | ||
659 | memset(seg->trbs, 0, SEGMENT_SIZE); | ||
660 | seg = seg->next; | ||
661 | } while (seg != ring->deq_seg); | ||
662 | |||
663 | /* Reset the software enqueue and dequeue pointers */ | ||
664 | ring->deq_seg = ring->first_seg; | ||
665 | ring->dequeue = ring->first_seg->trbs; | ||
666 | ring->enq_seg = ring->deq_seg; | ||
667 | ring->enqueue = ring->dequeue; | ||
668 | |||
669 | /* | ||
670 | * Ring is now zeroed, so the HW should look for change of ownership | ||
671 | * when the cycle bit is set to 1. | ||
672 | */ | ||
673 | ring->cycle_state = 1; | ||
674 | |||
675 | /* | ||
676 | * Reset the hardware dequeue pointer. | ||
677 | * Yes, this will need to be re-written after resume, but we're paranoid | ||
678 | * and want to make sure the hardware doesn't access bogus memory | ||
679 | * because, say, the BIOS or an SMI started the host without changing | ||
680 | * the command ring pointers. | ||
681 | */ | ||
682 | xhci_set_cmd_ring_deq(xhci); | ||
683 | } | ||
684 | |||
685 | /* | ||
686 | * Stop HC (not bus-specific) | ||
687 | * | ||
688 | * This is called when the machine transition into S3/S4 mode. | ||
689 | * | ||
690 | */ | ||
691 | int xhci_suspend(struct xhci_hcd *xhci) | ||
692 | { | ||
693 | int rc = 0; | ||
694 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | ||
695 | u32 command; | ||
696 | int i; | ||
697 | |||
698 | spin_lock_irq(&xhci->lock); | ||
699 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
700 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | ||
701 | /* step 1: stop endpoint */ | ||
702 | /* skipped assuming that port suspend has done */ | ||
703 | |||
704 | /* step 2: clear Run/Stop bit */ | ||
705 | command = xhci_readl(xhci, &xhci->op_regs->command); | ||
706 | command &= ~CMD_RUN; | ||
707 | xhci_writel(xhci, command, &xhci->op_regs->command); | ||
708 | if (handshake(xhci, &xhci->op_regs->status, | ||
709 | STS_HALT, STS_HALT, 100*100)) { | ||
710 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); | ||
711 | spin_unlock_irq(&xhci->lock); | ||
712 | return -ETIMEDOUT; | ||
713 | } | ||
714 | xhci_clear_command_ring(xhci); | ||
715 | |||
716 | /* step 3: save registers */ | ||
717 | xhci_save_registers(xhci); | ||
718 | |||
719 | /* step 4: set CSS flag */ | ||
720 | command = xhci_readl(xhci, &xhci->op_regs->command); | ||
721 | command |= CMD_CSS; | ||
722 | xhci_writel(xhci, command, &xhci->op_regs->command); | ||
723 | if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) { | ||
724 | xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n"); | ||
725 | spin_unlock_irq(&xhci->lock); | ||
726 | return -ETIMEDOUT; | ||
727 | } | ||
728 | spin_unlock_irq(&xhci->lock); | ||
729 | |||
730 | /* step 5: remove core well power */ | ||
731 | /* synchronize irq when using MSI-X */ | ||
732 | if (xhci->msix_entries) { | ||
733 | for (i = 0; i < xhci->msix_count; i++) | ||
734 | synchronize_irq(xhci->msix_entries[i].vector); | ||
735 | } | ||
736 | |||
737 | return rc; | ||
738 | } | ||
739 | |||
740 | /* | ||
741 | * start xHC (not bus-specific) | ||
742 | * | ||
743 | * This is called when the machine transition from S3/S4 mode. | ||
744 | * | ||
745 | */ | ||
746 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | ||
747 | { | ||
748 | u32 command, temp = 0; | ||
749 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | ||
750 | struct usb_hcd *secondary_hcd; | ||
751 | int retval; | ||
752 | |||
753 | /* Wait a bit if either of the roothubs need to settle from the | ||
754 | * transition into bus suspend. | ||
755 | */ | ||
756 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || | ||
757 | time_before(jiffies, | ||
758 | xhci->bus_state[1].next_statechange)) | ||
759 | msleep(100); | ||
760 | |||
761 | spin_lock_irq(&xhci->lock); | ||
762 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | ||
763 | hibernated = true; | ||
764 | |||
765 | if (!hibernated) { | ||
766 | /* step 1: restore register */ | ||
767 | xhci_restore_registers(xhci); | ||
768 | /* step 2: initialize command ring buffer */ | ||
769 | xhci_set_cmd_ring_deq(xhci); | ||
770 | /* step 3: restore state and start state*/ | ||
771 | /* step 3: set CRS flag */ | ||
772 | command = xhci_readl(xhci, &xhci->op_regs->command); | ||
773 | command |= CMD_CRS; | ||
774 | xhci_writel(xhci, command, &xhci->op_regs->command); | ||
775 | if (handshake(xhci, &xhci->op_regs->status, | ||
776 | STS_RESTORE, 0, 10*100)) { | ||
777 | xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n"); | ||
778 | spin_unlock_irq(&xhci->lock); | ||
779 | return -ETIMEDOUT; | ||
780 | } | ||
781 | temp = xhci_readl(xhci, &xhci->op_regs->status); | ||
782 | } | ||
783 | |||
784 | /* If restore operation fails, re-initialize the HC during resume */ | ||
785 | if ((temp & STS_SRE) || hibernated) { | ||
786 | /* Let the USB core know _both_ roothubs lost power. */ | ||
787 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | ||
788 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | ||
789 | |||
790 | xhci_dbg(xhci, "Stop HCD\n"); | ||
791 | xhci_halt(xhci); | ||
792 | xhci_reset(xhci); | ||
793 | spin_unlock_irq(&xhci->lock); | ||
794 | xhci_cleanup_msix(xhci); | ||
795 | |||
796 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | ||
797 | /* Tell the event ring poll function not to reschedule */ | ||
798 | xhci->zombie = 1; | ||
799 | del_timer_sync(&xhci->event_ring_timer); | ||
800 | #endif | ||
801 | |||
802 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); | ||
803 | temp = xhci_readl(xhci, &xhci->op_regs->status); | ||
804 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | ||
805 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | ||
806 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | ||
807 | &xhci->ir_set->irq_pending); | ||
808 | xhci_print_ir_set(xhci, 0); | ||
809 | |||
810 | xhci_dbg(xhci, "cleaning up memory\n"); | ||
811 | xhci_mem_cleanup(xhci); | ||
812 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | ||
813 | xhci_readl(xhci, &xhci->op_regs->status)); | ||
814 | |||
815 | /* USB core calls the PCI reinit and start functions twice: | ||
816 | * first with the primary HCD, and then with the secondary HCD. | ||
817 | * If we don't do the same, the host will never be started. | ||
818 | */ | ||
819 | if (!usb_hcd_is_primary_hcd(hcd)) | ||
820 | secondary_hcd = hcd; | ||
821 | else | ||
822 | secondary_hcd = xhci->shared_hcd; | ||
823 | |||
824 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | ||
825 | retval = xhci_init(hcd->primary_hcd); | ||
826 | if (retval) | ||
827 | return retval; | ||
828 | xhci_dbg(xhci, "Start the primary HCD\n"); | ||
829 | retval = xhci_run(hcd->primary_hcd); | ||
830 | if (retval) | ||
831 | goto failed_restart; | ||
832 | |||
833 | xhci_dbg(xhci, "Start the secondary HCD\n"); | ||
834 | retval = xhci_run(secondary_hcd); | ||
835 | if (!retval) { | ||
836 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
837 | set_bit(HCD_FLAG_HW_ACCESSIBLE, | ||
838 | &xhci->shared_hcd->flags); | ||
839 | } | ||
840 | failed_restart: | ||
841 | hcd->state = HC_STATE_SUSPENDED; | ||
842 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; | ||
843 | return retval; | ||
844 | } | ||
845 | |||
846 | /* step 4: set Run/Stop bit */ | ||
847 | command = xhci_readl(xhci, &xhci->op_regs->command); | ||
848 | command |= CMD_RUN; | ||
849 | xhci_writel(xhci, command, &xhci->op_regs->command); | ||
850 | handshake(xhci, &xhci->op_regs->status, STS_HALT, | ||
851 | 0, 250 * 1000); | ||
852 | |||
853 | /* step 5: walk topology and initialize portsc, | ||
854 | * portpmsc and portli | ||
855 | */ | ||
856 | /* this is done in bus_resume */ | ||
857 | |||
858 | /* step 6: restart each of the previously | ||
859 | * Running endpoints by ringing their doorbells | ||
860 | */ | ||
861 | |||
862 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | ||
863 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | ||
864 | |||
865 | spin_unlock_irq(&xhci->lock); | ||
866 | return 0; | ||
867 | } | ||
868 | #endif /* CONFIG_PM */ | ||
869 | |||
554 | /*-------------------------------------------------------------------------*/ | 870 | /*-------------------------------------------------------------------------*/ |
555 | 871 | ||
556 | /** | 872 | /** |
@@ -606,8 +922,12 @@ unsigned int xhci_last_valid_endpoint(u32 added_ctxs) | |||
606 | /* Returns 1 if the arguments are OK; | 922 | /* Returns 1 if the arguments are OK; |
607 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | 923 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. |
608 | */ | 924 | */ |
609 | int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, | 925 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
610 | struct usb_host_endpoint *ep, int check_ep, const char *func) { | 926 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
927 | const char *func) { | ||
928 | struct xhci_hcd *xhci; | ||
929 | struct xhci_virt_device *virt_dev; | ||
930 | |||
611 | if (!hcd || (check_ep && !ep) || !udev) { | 931 | if (!hcd || (check_ep && !ep) || !udev) { |
612 | printk(KERN_DEBUG "xHCI %s called with invalid args\n", | 932 | printk(KERN_DEBUG "xHCI %s called with invalid args\n", |
613 | func); | 933 | func); |
@@ -618,11 +938,24 @@ int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, | |||
618 | func); | 938 | func); |
619 | return 0; | 939 | return 0; |
620 | } | 940 | } |
621 | if (!udev->slot_id) { | 941 | |
622 | printk(KERN_DEBUG "xHCI %s called with unaddressed device\n", | 942 | if (check_virt_dev) { |
623 | func); | 943 | xhci = hcd_to_xhci(hcd); |
624 | return -EINVAL; | 944 | if (!udev->slot_id || !xhci->devs |
945 | || !xhci->devs[udev->slot_id]) { | ||
946 | printk(KERN_DEBUG "xHCI %s called with unaddressed " | ||
947 | "device\n", func); | ||
948 | return -EINVAL; | ||
949 | } | ||
950 | |||
951 | virt_dev = xhci->devs[udev->slot_id]; | ||
952 | if (virt_dev->udev != udev) { | ||
953 | printk(KERN_DEBUG "xHCI %s called with udev and " | ||
954 | "virt_dev does not match\n", func); | ||
955 | return -EINVAL; | ||
956 | } | ||
625 | } | 957 | } |
958 | |||
626 | return 1; | 959 | return 1; |
627 | } | 960 | } |
628 | 961 | ||
@@ -649,8 +982,8 @@ static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |||
649 | 982 | ||
650 | out_ctx = xhci->devs[slot_id]->out_ctx; | 983 | out_ctx = xhci->devs[slot_id]->out_ctx; |
651 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | 984 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
652 | hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2); | 985 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
653 | max_packet_size = urb->dev->ep0.desc.wMaxPacketSize; | 986 | max_packet_size = le16_to_cpu(urb->dev->ep0.desc.wMaxPacketSize); |
654 | if (hw_max_packet_size != max_packet_size) { | 987 | if (hw_max_packet_size != max_packet_size) { |
655 | xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n"); | 988 | xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n"); |
656 | xhci_dbg(xhci, "Max packet size in usb_device = %d\n", | 989 | xhci_dbg(xhci, "Max packet size in usb_device = %d\n", |
@@ -664,15 +997,15 @@ static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |||
664 | xhci->devs[slot_id]->out_ctx, ep_index); | 997 | xhci->devs[slot_id]->out_ctx, ep_index); |
665 | in_ctx = xhci->devs[slot_id]->in_ctx; | 998 | in_ctx = xhci->devs[slot_id]->in_ctx; |
666 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | 999 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
667 | ep_ctx->ep_info2 &= ~MAX_PACKET_MASK; | 1000 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
668 | ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size); | 1001 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); |
669 | 1002 | ||
670 | /* Set up the input context flags for the command */ | 1003 | /* Set up the input context flags for the command */ |
671 | /* FIXME: This won't work if a non-default control endpoint | 1004 | /* FIXME: This won't work if a non-default control endpoint |
672 | * changes max packet sizes. | 1005 | * changes max packet sizes. |
673 | */ | 1006 | */ |
674 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | 1007 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
675 | ctrl_ctx->add_flags = EP0_FLAG; | 1008 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
676 | ctrl_ctx->drop_flags = 0; | 1009 | ctrl_ctx->drop_flags = 0; |
677 | 1010 | ||
678 | xhci_dbg(xhci, "Slot %d input context\n", slot_id); | 1011 | xhci_dbg(xhci, "Slot %d input context\n", slot_id); |
@@ -686,7 +1019,7 @@ static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |||
686 | /* Clean up the input context for later use by bandwidth | 1019 | /* Clean up the input context for later use by bandwidth |
687 | * functions. | 1020 | * functions. |
688 | */ | 1021 | */ |
689 | ctrl_ctx->add_flags = SLOT_FLAG; | 1022 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
690 | } | 1023 | } |
691 | return ret; | 1024 | return ret; |
692 | } | 1025 | } |
@@ -704,18 +1037,13 @@ int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) | |||
704 | struct urb_priv *urb_priv; | 1037 | struct urb_priv *urb_priv; |
705 | int size, i; | 1038 | int size, i; |
706 | 1039 | ||
707 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0) | 1040 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1041 | true, true, __func__) <= 0) | ||
708 | return -EINVAL; | 1042 | return -EINVAL; |
709 | 1043 | ||
710 | slot_id = urb->dev->slot_id; | 1044 | slot_id = urb->dev->slot_id; |
711 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | 1045 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); |
712 | 1046 | ||
713 | if (!xhci->devs || !xhci->devs[slot_id]) { | ||
714 | if (!in_interrupt()) | ||
715 | dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n"); | ||
716 | ret = -EINVAL; | ||
717 | goto exit; | ||
718 | } | ||
719 | if (!HCD_HW_ACCESSIBLE(hcd)) { | 1047 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
720 | if (!in_interrupt()) | 1048 | if (!in_interrupt()) |
721 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | 1049 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); |
@@ -904,13 +1232,13 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |||
904 | if (ret || !urb->hcpriv) | 1232 | if (ret || !urb->hcpriv) |
905 | goto done; | 1233 | goto done; |
906 | temp = xhci_readl(xhci, &xhci->op_regs->status); | 1234 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
907 | if (temp == 0xffffffff) { | 1235 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { |
908 | xhci_dbg(xhci, "HW died, freeing TD.\n"); | 1236 | xhci_dbg(xhci, "HW died, freeing TD.\n"); |
909 | urb_priv = urb->hcpriv; | 1237 | urb_priv = urb->hcpriv; |
910 | 1238 | ||
911 | usb_hcd_unlink_urb_from_ep(hcd, urb); | 1239 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
912 | spin_unlock_irqrestore(&xhci->lock, flags); | 1240 | spin_unlock_irqrestore(&xhci->lock, flags); |
913 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN); | 1241 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); |
914 | xhci_urb_free_priv(xhci, urb_priv); | 1242 | xhci_urb_free_priv(xhci, urb_priv); |
915 | return ret; | 1243 | return ret; |
916 | } | 1244 | } |
@@ -956,7 +1284,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |||
956 | ep->stop_cmd_timer.expires = jiffies + | 1284 | ep->stop_cmd_timer.expires = jiffies + |
957 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | 1285 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; |
958 | add_timer(&ep->stop_cmd_timer); | 1286 | add_timer(&ep->stop_cmd_timer); |
959 | xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index); | 1287 | xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0); |
960 | xhci_ring_cmd_db(xhci); | 1288 | xhci_ring_cmd_db(xhci); |
961 | } | 1289 | } |
962 | done: | 1290 | done: |
@@ -991,12 +1319,14 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
991 | u32 new_add_flags, new_drop_flags, new_slot_info; | 1319 | u32 new_add_flags, new_drop_flags, new_slot_info; |
992 | int ret; | 1320 | int ret; |
993 | 1321 | ||
994 | ret = xhci_check_args(hcd, udev, ep, 1, __func__); | 1322 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
995 | if (ret <= 0) | 1323 | if (ret <= 0) |
996 | return ret; | 1324 | return ret; |
997 | xhci = hcd_to_xhci(hcd); | 1325 | xhci = hcd_to_xhci(hcd); |
998 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); | 1326 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1327 | return -ENODEV; | ||
999 | 1328 | ||
1329 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); | ||
1000 | drop_flag = xhci_get_endpoint_flag(&ep->desc); | 1330 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1001 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | 1331 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { |
1002 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | 1332 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", |
@@ -1004,12 +1334,6 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
1004 | return 0; | 1334 | return 0; |
1005 | } | 1335 | } |
1006 | 1336 | ||
1007 | if (!xhci->devs || !xhci->devs[udev->slot_id]) { | ||
1008 | xhci_warn(xhci, "xHCI %s called with unaddressed device\n", | ||
1009 | __func__); | ||
1010 | return -EINVAL; | ||
1011 | } | ||
1012 | |||
1013 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; | 1337 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
1014 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; | 1338 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
1015 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | 1339 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
@@ -1018,27 +1342,30 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
1018 | /* If the HC already knows the endpoint is disabled, | 1342 | /* If the HC already knows the endpoint is disabled, |
1019 | * or the HCD has noted it is disabled, ignore this request | 1343 | * or the HCD has noted it is disabled, ignore this request |
1020 | */ | 1344 | */ |
1021 | if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED || | 1345 | if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
1022 | ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) { | 1346 | EP_STATE_DISABLED || |
1347 | le32_to_cpu(ctrl_ctx->drop_flags) & | ||
1348 | xhci_get_endpoint_flag(&ep->desc)) { | ||
1023 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", | 1349 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", |
1024 | __func__, ep); | 1350 | __func__, ep); |
1025 | return 0; | 1351 | return 0; |
1026 | } | 1352 | } |
1027 | 1353 | ||
1028 | ctrl_ctx->drop_flags |= drop_flag; | 1354 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1029 | new_drop_flags = ctrl_ctx->drop_flags; | 1355 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
1030 | 1356 | ||
1031 | ctrl_ctx->add_flags &= ~drop_flag; | 1357 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1032 | new_add_flags = ctrl_ctx->add_flags; | 1358 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); |
1033 | 1359 | ||
1034 | last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags); | 1360 | last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)); |
1035 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); | 1361 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1036 | /* Update the last valid endpoint context, if we deleted the last one */ | 1362 | /* Update the last valid endpoint context, if we deleted the last one */ |
1037 | if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) { | 1363 | if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) > |
1038 | slot_ctx->dev_info &= ~LAST_CTX_MASK; | 1364 | LAST_CTX(last_ctx)) { |
1039 | slot_ctx->dev_info |= LAST_CTX(last_ctx); | 1365 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
1366 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx)); | ||
1040 | } | 1367 | } |
1041 | new_slot_info = slot_ctx->dev_info; | 1368 | new_slot_info = le32_to_cpu(slot_ctx->dev_info); |
1042 | 1369 | ||
1043 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); | 1370 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); |
1044 | 1371 | ||
@@ -1076,15 +1403,18 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
1076 | u32 added_ctxs; | 1403 | u32 added_ctxs; |
1077 | unsigned int last_ctx; | 1404 | unsigned int last_ctx; |
1078 | u32 new_add_flags, new_drop_flags, new_slot_info; | 1405 | u32 new_add_flags, new_drop_flags, new_slot_info; |
1406 | struct xhci_virt_device *virt_dev; | ||
1079 | int ret = 0; | 1407 | int ret = 0; |
1080 | 1408 | ||
1081 | ret = xhci_check_args(hcd, udev, ep, 1, __func__); | 1409 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
1082 | if (ret <= 0) { | 1410 | if (ret <= 0) { |
1083 | /* So we won't queue a reset ep command for a root hub */ | 1411 | /* So we won't queue a reset ep command for a root hub */ |
1084 | ep->hcpriv = NULL; | 1412 | ep->hcpriv = NULL; |
1085 | return ret; | 1413 | return ret; |
1086 | } | 1414 | } |
1087 | xhci = hcd_to_xhci(hcd); | 1415 | xhci = hcd_to_xhci(hcd); |
1416 | if (xhci->xhc_state & XHCI_STATE_DYING) | ||
1417 | return -ENODEV; | ||
1088 | 1418 | ||
1089 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | 1419 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); |
1090 | last_ctx = xhci_last_valid_endpoint(added_ctxs); | 1420 | last_ctx = xhci_last_valid_endpoint(added_ctxs); |
@@ -1098,21 +1428,30 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
1098 | return 0; | 1428 | return 0; |
1099 | } | 1429 | } |
1100 | 1430 | ||
1101 | if (!xhci->devs || !xhci->devs[udev->slot_id]) { | 1431 | virt_dev = xhci->devs[udev->slot_id]; |
1102 | xhci_warn(xhci, "xHCI %s called with unaddressed device\n", | 1432 | in_ctx = virt_dev->in_ctx; |
1103 | __func__); | 1433 | out_ctx = virt_dev->out_ctx; |
1104 | return -EINVAL; | ||
1105 | } | ||
1106 | |||
1107 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; | ||
1108 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; | ||
1109 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | 1434 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
1110 | ep_index = xhci_get_endpoint_index(&ep->desc); | 1435 | ep_index = xhci_get_endpoint_index(&ep->desc); |
1111 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | 1436 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1437 | |||
1438 | /* If this endpoint is already in use, and the upper layers are trying | ||
1439 | * to add it again without dropping it, reject the addition. | ||
1440 | */ | ||
1441 | if (virt_dev->eps[ep_index].ring && | ||
1442 | !(le32_to_cpu(ctrl_ctx->drop_flags) & | ||
1443 | xhci_get_endpoint_flag(&ep->desc))) { | ||
1444 | xhci_warn(xhci, "Trying to add endpoint 0x%x " | ||
1445 | "without dropping it.\n", | ||
1446 | (unsigned int) ep->desc.bEndpointAddress); | ||
1447 | return -EINVAL; | ||
1448 | } | ||
1449 | |||
1112 | /* If the HCD has already noted the endpoint is enabled, | 1450 | /* If the HCD has already noted the endpoint is enabled, |
1113 | * ignore this request. | 1451 | * ignore this request. |
1114 | */ | 1452 | */ |
1115 | if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) { | 1453 | if (le32_to_cpu(ctrl_ctx->add_flags) & |
1454 | xhci_get_endpoint_flag(&ep->desc)) { | ||
1116 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", | 1455 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1117 | __func__, ep); | 1456 | __func__, ep); |
1118 | return 0; | 1457 | return 0; |
@@ -1123,15 +1462,14 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
1123 | * process context, not interrupt context (or so documenation | 1462 | * process context, not interrupt context (or so documenation |
1124 | * for usb_set_interface() and usb_set_configuration() claim). | 1463 | * for usb_set_interface() and usb_set_configuration() claim). |
1125 | */ | 1464 | */ |
1126 | if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id], | 1465 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
1127 | udev, ep, GFP_NOIO) < 0) { | ||
1128 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", | 1466 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1129 | __func__, ep->desc.bEndpointAddress); | 1467 | __func__, ep->desc.bEndpointAddress); |
1130 | return -ENOMEM; | 1468 | return -ENOMEM; |
1131 | } | 1469 | } |
1132 | 1470 | ||
1133 | ctrl_ctx->add_flags |= added_ctxs; | 1471 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1134 | new_add_flags = ctrl_ctx->add_flags; | 1472 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); |
1135 | 1473 | ||
1136 | /* If xhci_endpoint_disable() was called for this endpoint, but the | 1474 | /* If xhci_endpoint_disable() was called for this endpoint, but the |
1137 | * xHC hasn't been notified yet through the check_bandwidth() call, | 1475 | * xHC hasn't been notified yet through the check_bandwidth() call, |
@@ -1139,15 +1477,16 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |||
1139 | * descriptors. We must drop and re-add this endpoint, so we leave the | 1477 | * descriptors. We must drop and re-add this endpoint, so we leave the |
1140 | * drop flags alone. | 1478 | * drop flags alone. |
1141 | */ | 1479 | */ |
1142 | new_drop_flags = ctrl_ctx->drop_flags; | 1480 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
1143 | 1481 | ||
1144 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); | 1482 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1145 | /* Update the last valid endpoint context, if we just added one past */ | 1483 | /* Update the last valid endpoint context, if we just added one past */ |
1146 | if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) { | 1484 | if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) < |
1147 | slot_ctx->dev_info &= ~LAST_CTX_MASK; | 1485 | LAST_CTX(last_ctx)) { |
1148 | slot_ctx->dev_info |= LAST_CTX(last_ctx); | 1486 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
1487 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx)); | ||
1149 | } | 1488 | } |
1150 | new_slot_info = slot_ctx->dev_info; | 1489 | new_slot_info = le32_to_cpu(slot_ctx->dev_info); |
1151 | 1490 | ||
1152 | /* Store the usb_device pointer for later use */ | 1491 | /* Store the usb_device pointer for later use */ |
1153 | ep->hcpriv = udev; | 1492 | ep->hcpriv = udev; |
@@ -1177,9 +1516,9 @@ static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *vir | |||
1177 | ctrl_ctx->drop_flags = 0; | 1516 | ctrl_ctx->drop_flags = 0; |
1178 | ctrl_ctx->add_flags = 0; | 1517 | ctrl_ctx->add_flags = 0; |
1179 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | 1518 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
1180 | slot_ctx->dev_info &= ~LAST_CTX_MASK; | 1519 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
1181 | /* Endpoint 0 is always valid */ | 1520 | /* Endpoint 0 is always valid */ |
1182 | slot_ctx->dev_info |= LAST_CTX(1); | 1521 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
1183 | for (i = 1; i < 31; ++i) { | 1522 | for (i = 1; i < 31; ++i) { |
1184 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); | 1523 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
1185 | ep_ctx->ep_info = 0; | 1524 | ep_ctx->ep_info = 0; |
@@ -1190,7 +1529,7 @@ static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *vir | |||
1190 | } | 1529 | } |
1191 | 1530 | ||
1192 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, | 1531 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
1193 | struct usb_device *udev, int *cmd_status) | 1532 | struct usb_device *udev, u32 *cmd_status) |
1194 | { | 1533 | { |
1195 | int ret; | 1534 | int ret; |
1196 | 1535 | ||
@@ -1214,6 +1553,11 @@ static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, | |||
1214 | "and endpoint is not disabled.\n"); | 1553 | "and endpoint is not disabled.\n"); |
1215 | ret = -EINVAL; | 1554 | ret = -EINVAL; |
1216 | break; | 1555 | break; |
1556 | case COMP_DEV_ERR: | ||
1557 | dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint " | ||
1558 | "configure command.\n"); | ||
1559 | ret = -ENODEV; | ||
1560 | break; | ||
1217 | case COMP_SUCCESS: | 1561 | case COMP_SUCCESS: |
1218 | dev_dbg(&udev->dev, "Successful Endpoint Configure command\n"); | 1562 | dev_dbg(&udev->dev, "Successful Endpoint Configure command\n"); |
1219 | ret = 0; | 1563 | ret = 0; |
@@ -1228,7 +1572,7 @@ static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, | |||
1228 | } | 1572 | } |
1229 | 1573 | ||
1230 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | 1574 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, |
1231 | struct usb_device *udev, int *cmd_status) | 1575 | struct usb_device *udev, u32 *cmd_status) |
1232 | { | 1576 | { |
1233 | int ret; | 1577 | int ret; |
1234 | struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; | 1578 | struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; |
@@ -1248,6 +1592,16 @@ static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |||
1248 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); | 1592 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); |
1249 | ret = -EINVAL; | 1593 | ret = -EINVAL; |
1250 | break; | 1594 | break; |
1595 | case COMP_DEV_ERR: | ||
1596 | dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate " | ||
1597 | "context command.\n"); | ||
1598 | ret = -ENODEV; | ||
1599 | break; | ||
1600 | case COMP_MEL_ERR: | ||
1601 | /* Max Exit Latency too large error */ | ||
1602 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | ||
1603 | ret = -EINVAL; | ||
1604 | break; | ||
1251 | case COMP_SUCCESS: | 1605 | case COMP_SUCCESS: |
1252 | dev_dbg(&udev->dev, "Successful evaluate context command\n"); | 1606 | dev_dbg(&udev->dev, "Successful evaluate context command\n"); |
1253 | ret = 0; | 1607 | ret = 0; |
@@ -1261,6 +1615,113 @@ static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |||
1261 | return ret; | 1615 | return ret; |
1262 | } | 1616 | } |
1263 | 1617 | ||
1618 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, | ||
1619 | struct xhci_container_ctx *in_ctx) | ||
1620 | { | ||
1621 | struct xhci_input_control_ctx *ctrl_ctx; | ||
1622 | u32 valid_add_flags; | ||
1623 | u32 valid_drop_flags; | ||
1624 | |||
1625 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | ||
1626 | /* Ignore the slot flag (bit 0), and the default control endpoint flag | ||
1627 | * (bit 1). The default control endpoint is added during the Address | ||
1628 | * Device command and is never removed until the slot is disabled. | ||
1629 | */ | ||
1630 | valid_add_flags = ctrl_ctx->add_flags >> 2; | ||
1631 | valid_drop_flags = ctrl_ctx->drop_flags >> 2; | ||
1632 | |||
1633 | /* Use hweight32 to count the number of ones in the add flags, or | ||
1634 | * number of endpoints added. Don't count endpoints that are changed | ||
1635 | * (both added and dropped). | ||
1636 | */ | ||
1637 | return hweight32(valid_add_flags) - | ||
1638 | hweight32(valid_add_flags & valid_drop_flags); | ||
1639 | } | ||
1640 | |||
1641 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | ||
1642 | struct xhci_container_ctx *in_ctx) | ||
1643 | { | ||
1644 | struct xhci_input_control_ctx *ctrl_ctx; | ||
1645 | u32 valid_add_flags; | ||
1646 | u32 valid_drop_flags; | ||
1647 | |||
1648 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | ||
1649 | valid_add_flags = ctrl_ctx->add_flags >> 2; | ||
1650 | valid_drop_flags = ctrl_ctx->drop_flags >> 2; | ||
1651 | |||
1652 | return hweight32(valid_drop_flags) - | ||
1653 | hweight32(valid_add_flags & valid_drop_flags); | ||
1654 | } | ||
1655 | |||
1656 | /* | ||
1657 | * We need to reserve the new number of endpoints before the configure endpoint | ||
1658 | * command completes. We can't subtract the dropped endpoints from the number | ||
1659 | * of active endpoints until the command completes because we can oversubscribe | ||
1660 | * the host in this case: | ||
1661 | * | ||
1662 | * - the first configure endpoint command drops more endpoints than it adds | ||
1663 | * - a second configure endpoint command that adds more endpoints is queued | ||
1664 | * - the first configure endpoint command fails, so the config is unchanged | ||
1665 | * - the second command may succeed, even though there isn't enough resources | ||
1666 | * | ||
1667 | * Must be called with xhci->lock held. | ||
1668 | */ | ||
1669 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | ||
1670 | struct xhci_container_ctx *in_ctx) | ||
1671 | { | ||
1672 | u32 added_eps; | ||
1673 | |||
1674 | added_eps = xhci_count_num_new_endpoints(xhci, in_ctx); | ||
1675 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { | ||
1676 | xhci_dbg(xhci, "Not enough ep ctxs: " | ||
1677 | "%u active, need to add %u, limit is %u.\n", | ||
1678 | xhci->num_active_eps, added_eps, | ||
1679 | xhci->limit_active_eps); | ||
1680 | return -ENOMEM; | ||
1681 | } | ||
1682 | xhci->num_active_eps += added_eps; | ||
1683 | xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps, | ||
1684 | xhci->num_active_eps); | ||
1685 | return 0; | ||
1686 | } | ||
1687 | |||
1688 | /* | ||
1689 | * The configure endpoint was failed by the xHC for some other reason, so we | ||
1690 | * need to revert the resources that failed configuration would have used. | ||
1691 | * | ||
1692 | * Must be called with xhci->lock held. | ||
1693 | */ | ||
1694 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | ||
1695 | struct xhci_container_ctx *in_ctx) | ||
1696 | { | ||
1697 | u32 num_failed_eps; | ||
1698 | |||
1699 | num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx); | ||
1700 | xhci->num_active_eps -= num_failed_eps; | ||
1701 | xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n", | ||
1702 | num_failed_eps, | ||
1703 | xhci->num_active_eps); | ||
1704 | } | ||
1705 | |||
1706 | /* | ||
1707 | * Now that the command has completed, clean up the active endpoint count by | ||
1708 | * subtracting out the endpoints that were dropped (but not changed). | ||
1709 | * | ||
1710 | * Must be called with xhci->lock held. | ||
1711 | */ | ||
1712 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | ||
1713 | struct xhci_container_ctx *in_ctx) | ||
1714 | { | ||
1715 | u32 num_dropped_eps; | ||
1716 | |||
1717 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx); | ||
1718 | xhci->num_active_eps -= num_dropped_eps; | ||
1719 | if (num_dropped_eps) | ||
1720 | xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n", | ||
1721 | num_dropped_eps, | ||
1722 | xhci->num_active_eps); | ||
1723 | } | ||
1724 | |||
1264 | /* Issue a configure endpoint command or evaluate context command | 1725 | /* Issue a configure endpoint command or evaluate context command |
1265 | * and wait for it to finish. | 1726 | * and wait for it to finish. |
1266 | */ | 1727 | */ |
@@ -1274,19 +1735,45 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |||
1274 | unsigned long flags; | 1735 | unsigned long flags; |
1275 | struct xhci_container_ctx *in_ctx; | 1736 | struct xhci_container_ctx *in_ctx; |
1276 | struct completion *cmd_completion; | 1737 | struct completion *cmd_completion; |
1277 | int *cmd_status; | 1738 | u32 *cmd_status; |
1278 | struct xhci_virt_device *virt_dev; | 1739 | struct xhci_virt_device *virt_dev; |
1279 | 1740 | ||
1280 | spin_lock_irqsave(&xhci->lock, flags); | 1741 | spin_lock_irqsave(&xhci->lock, flags); |
1281 | virt_dev = xhci->devs[udev->slot_id]; | 1742 | virt_dev = xhci->devs[udev->slot_id]; |
1282 | if (command) { | 1743 | if (command) { |
1283 | in_ctx = command->in_ctx; | 1744 | in_ctx = command->in_ctx; |
1745 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && | ||
1746 | xhci_reserve_host_resources(xhci, in_ctx)) { | ||
1747 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
1748 | xhci_warn(xhci, "Not enough host resources, " | ||
1749 | "active endpoint contexts = %u\n", | ||
1750 | xhci->num_active_eps); | ||
1751 | return -ENOMEM; | ||
1752 | } | ||
1753 | |||
1284 | cmd_completion = command->completion; | 1754 | cmd_completion = command->completion; |
1285 | cmd_status = &command->status; | 1755 | cmd_status = &command->status; |
1286 | command->command_trb = xhci->cmd_ring->enqueue; | 1756 | command->command_trb = xhci->cmd_ring->enqueue; |
1757 | |||
1758 | /* Enqueue pointer can be left pointing to the link TRB, | ||
1759 | * we must handle that | ||
1760 | */ | ||
1761 | if ((le32_to_cpu(command->command_trb->link.control) | ||
1762 | & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) | ||
1763 | command->command_trb = | ||
1764 | xhci->cmd_ring->enq_seg->next->trbs; | ||
1765 | |||
1287 | list_add_tail(&command->cmd_list, &virt_dev->cmd_list); | 1766 | list_add_tail(&command->cmd_list, &virt_dev->cmd_list); |
1288 | } else { | 1767 | } else { |
1289 | in_ctx = virt_dev->in_ctx; | 1768 | in_ctx = virt_dev->in_ctx; |
1769 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && | ||
1770 | xhci_reserve_host_resources(xhci, in_ctx)) { | ||
1771 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
1772 | xhci_warn(xhci, "Not enough host resources, " | ||
1773 | "active endpoint contexts = %u\n", | ||
1774 | xhci->num_active_eps); | ||
1775 | return -ENOMEM; | ||
1776 | } | ||
1290 | cmd_completion = &virt_dev->cmd_completion; | 1777 | cmd_completion = &virt_dev->cmd_completion; |
1291 | cmd_status = &virt_dev->cmd_status; | 1778 | cmd_status = &virt_dev->cmd_status; |
1292 | } | 1779 | } |
@@ -1301,6 +1788,8 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |||
1301 | if (ret < 0) { | 1788 | if (ret < 0) { |
1302 | if (command) | 1789 | if (command) |
1303 | list_del(&command->cmd_list); | 1790 | list_del(&command->cmd_list); |
1791 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) | ||
1792 | xhci_free_host_resources(xhci, in_ctx); | ||
1304 | spin_unlock_irqrestore(&xhci->lock, flags); | 1793 | spin_unlock_irqrestore(&xhci->lock, flags); |
1305 | xhci_dbg(xhci, "FIXME allocate a new ring segment\n"); | 1794 | xhci_dbg(xhci, "FIXME allocate a new ring segment\n"); |
1306 | return -ENOMEM; | 1795 | return -ENOMEM; |
@@ -1323,8 +1812,22 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |||
1323 | } | 1812 | } |
1324 | 1813 | ||
1325 | if (!ctx_change) | 1814 | if (!ctx_change) |
1326 | return xhci_configure_endpoint_result(xhci, udev, cmd_status); | 1815 | ret = xhci_configure_endpoint_result(xhci, udev, cmd_status); |
1327 | return xhci_evaluate_context_result(xhci, udev, cmd_status); | 1816 | else |
1817 | ret = xhci_evaluate_context_result(xhci, udev, cmd_status); | ||
1818 | |||
1819 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | ||
1820 | spin_lock_irqsave(&xhci->lock, flags); | ||
1821 | /* If the command failed, remove the reserved resources. | ||
1822 | * Otherwise, clean up the estimate to include dropped eps. | ||
1823 | */ | ||
1824 | if (ret) | ||
1825 | xhci_free_host_resources(xhci, in_ctx); | ||
1826 | else | ||
1827 | xhci_finish_resource_reservation(xhci, in_ctx); | ||
1828 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
1829 | } | ||
1830 | return ret; | ||
1328 | } | 1831 | } |
1329 | 1832 | ||
1330 | /* Called after one or more calls to xhci_add_endpoint() or | 1833 | /* Called after one or more calls to xhci_add_endpoint() or |
@@ -1346,29 +1849,25 @@ int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |||
1346 | struct xhci_input_control_ctx *ctrl_ctx; | 1849 | struct xhci_input_control_ctx *ctrl_ctx; |
1347 | struct xhci_slot_ctx *slot_ctx; | 1850 | struct xhci_slot_ctx *slot_ctx; |
1348 | 1851 | ||
1349 | ret = xhci_check_args(hcd, udev, NULL, 0, __func__); | 1852 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
1350 | if (ret <= 0) | 1853 | if (ret <= 0) |
1351 | return ret; | 1854 | return ret; |
1352 | xhci = hcd_to_xhci(hcd); | 1855 | xhci = hcd_to_xhci(hcd); |
1856 | if (xhci->xhc_state & XHCI_STATE_DYING) | ||
1857 | return -ENODEV; | ||
1353 | 1858 | ||
1354 | if (!udev->slot_id || !xhci->devs || !xhci->devs[udev->slot_id]) { | ||
1355 | xhci_warn(xhci, "xHCI %s called with unaddressed device\n", | ||
1356 | __func__); | ||
1357 | return -EINVAL; | ||
1358 | } | ||
1359 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); | 1859 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
1360 | virt_dev = xhci->devs[udev->slot_id]; | 1860 | virt_dev = xhci->devs[udev->slot_id]; |
1361 | 1861 | ||
1362 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ | 1862 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ |
1363 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); | 1863 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
1364 | ctrl_ctx->add_flags |= SLOT_FLAG; | 1864 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
1365 | ctrl_ctx->add_flags &= ~EP0_FLAG; | 1865 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); |
1366 | ctrl_ctx->drop_flags &= ~SLOT_FLAG; | 1866 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); |
1367 | ctrl_ctx->drop_flags &= ~EP0_FLAG; | ||
1368 | xhci_dbg(xhci, "New Input Control Context:\n"); | 1867 | xhci_dbg(xhci, "New Input Control Context:\n"); |
1369 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | 1868 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
1370 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, | 1869 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, |
1371 | LAST_CTX_TO_EP_NUM(slot_ctx->dev_info)); | 1870 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
1372 | 1871 | ||
1373 | ret = xhci_configure_endpoint(xhci, udev, NULL, | 1872 | ret = xhci_configure_endpoint(xhci, udev, NULL, |
1374 | false, false); | 1873 | false, false); |
@@ -1379,10 +1878,19 @@ int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |||
1379 | 1878 | ||
1380 | xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); | 1879 | xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); |
1381 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, | 1880 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, |
1382 | LAST_CTX_TO_EP_NUM(slot_ctx->dev_info)); | 1881 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
1383 | 1882 | ||
1883 | /* Free any rings that were dropped, but not changed. */ | ||
1884 | for (i = 1; i < 31; ++i) { | ||
1885 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && | ||
1886 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) | ||
1887 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | ||
1888 | } | ||
1384 | xhci_zero_in_ctx(xhci, virt_dev); | 1889 | xhci_zero_in_ctx(xhci, virt_dev); |
1385 | /* Install new rings and free or cache any old rings */ | 1890 | /* |
1891 | * Install any rings for completely new endpoints or changed endpoints, | ||
1892 | * and free or cache any old rings from changed endpoints. | ||
1893 | */ | ||
1386 | for (i = 1; i < 31; ++i) { | 1894 | for (i = 1; i < 31; ++i) { |
1387 | if (!virt_dev->eps[i].new_ring) | 1895 | if (!virt_dev->eps[i].new_ring) |
1388 | continue; | 1896 | continue; |
@@ -1405,16 +1913,11 @@ void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |||
1405 | struct xhci_virt_device *virt_dev; | 1913 | struct xhci_virt_device *virt_dev; |
1406 | int i, ret; | 1914 | int i, ret; |
1407 | 1915 | ||
1408 | ret = xhci_check_args(hcd, udev, NULL, 0, __func__); | 1916 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
1409 | if (ret <= 0) | 1917 | if (ret <= 0) |
1410 | return; | 1918 | return; |
1411 | xhci = hcd_to_xhci(hcd); | 1919 | xhci = hcd_to_xhci(hcd); |
1412 | 1920 | ||
1413 | if (!xhci->devs || !xhci->devs[udev->slot_id]) { | ||
1414 | xhci_warn(xhci, "xHCI %s called with unaddressed device\n", | ||
1415 | __func__); | ||
1416 | return; | ||
1417 | } | ||
1418 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); | 1921 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
1419 | virt_dev = xhci->devs[udev->slot_id]; | 1922 | virt_dev = xhci->devs[udev->slot_id]; |
1420 | /* Free any rings allocated for added endpoints */ | 1923 | /* Free any rings allocated for added endpoints */ |
@@ -1434,16 +1937,16 @@ static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, | |||
1434 | { | 1937 | { |
1435 | struct xhci_input_control_ctx *ctrl_ctx; | 1938 | struct xhci_input_control_ctx *ctrl_ctx; |
1436 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | 1939 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
1437 | ctrl_ctx->add_flags = add_flags; | 1940 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
1438 | ctrl_ctx->drop_flags = drop_flags; | 1941 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); |
1439 | xhci_slot_copy(xhci, in_ctx, out_ctx); | 1942 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
1440 | ctrl_ctx->add_flags |= SLOT_FLAG; | 1943 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
1441 | 1944 | ||
1442 | xhci_dbg(xhci, "Input Context:\n"); | 1945 | xhci_dbg(xhci, "Input Context:\n"); |
1443 | xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); | 1946 | xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); |
1444 | } | 1947 | } |
1445 | 1948 | ||
1446 | void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, | 1949 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
1447 | unsigned int slot_id, unsigned int ep_index, | 1950 | unsigned int slot_id, unsigned int ep_index, |
1448 | struct xhci_dequeue_state *deq_state) | 1951 | struct xhci_dequeue_state *deq_state) |
1449 | { | 1952 | { |
@@ -1466,7 +1969,7 @@ void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, | |||
1466 | deq_state->new_deq_ptr); | 1969 | deq_state->new_deq_ptr); |
1467 | return; | 1970 | return; |
1468 | } | 1971 | } |
1469 | ep_ctx->deq = addr | deq_state->new_cycle_state; | 1972 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
1470 | 1973 | ||
1471 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); | 1974 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
1472 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, | 1975 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
@@ -1575,7 +2078,7 @@ static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, | |||
1575 | 2078 | ||
1576 | if (!ep) | 2079 | if (!ep) |
1577 | return -EINVAL; | 2080 | return -EINVAL; |
1578 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, __func__); | 2081 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
1579 | if (ret <= 0) | 2082 | if (ret <= 0) |
1580 | return -EINVAL; | 2083 | return -EINVAL; |
1581 | if (ep->ss_ep_comp.bmAttributes == 0) { | 2084 | if (ep->ss_ep_comp.bmAttributes == 0) { |
@@ -1771,7 +2274,7 @@ int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, | |||
1771 | return -EINVAL; | 2274 | return -EINVAL; |
1772 | } | 2275 | } |
1773 | vdev = xhci->devs[udev->slot_id]; | 2276 | vdev = xhci->devs[udev->slot_id]; |
1774 | /* Mark each endpoint as being in transistion, so | 2277 | /* Mark each endpoint as being in transition, so |
1775 | * xhci_urb_enqueue() will reject all URBs. | 2278 | * xhci_urb_enqueue() will reject all URBs. |
1776 | */ | 2279 | */ |
1777 | for (i = 0; i < num_eps; i++) { | 2280 | for (i = 0; i < num_eps; i++) { |
@@ -1942,6 +2445,34 @@ int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |||
1942 | } | 2445 | } |
1943 | 2446 | ||
1944 | /* | 2447 | /* |
2448 | * Deletes endpoint resources for endpoints that were active before a Reset | ||
2449 | * Device command, or a Disable Slot command. The Reset Device command leaves | ||
2450 | * the control endpoint intact, whereas the Disable Slot command deletes it. | ||
2451 | * | ||
2452 | * Must be called with xhci->lock held. | ||
2453 | */ | ||
2454 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | ||
2455 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | ||
2456 | { | ||
2457 | int i; | ||
2458 | unsigned int num_dropped_eps = 0; | ||
2459 | unsigned int drop_flags = 0; | ||
2460 | |||
2461 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | ||
2462 | if (virt_dev->eps[i].ring) { | ||
2463 | drop_flags |= 1 << i; | ||
2464 | num_dropped_eps++; | ||
2465 | } | ||
2466 | } | ||
2467 | xhci->num_active_eps -= num_dropped_eps; | ||
2468 | if (num_dropped_eps) | ||
2469 | xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, " | ||
2470 | "%u now active.\n", | ||
2471 | num_dropped_eps, drop_flags, | ||
2472 | xhci->num_active_eps); | ||
2473 | } | ||
2474 | |||
2475 | /* | ||
1945 | * This submits a Reset Device Command, which will set the device state to 0, | 2476 | * This submits a Reset Device Command, which will set the device state to 0, |
1946 | * set the device address to 0, and disable all the endpoints except the default | 2477 | * set the device address to 0, and disable all the endpoints except the default |
1947 | * control endpoint. The USB core should come back and call | 2478 | * control endpoint. The USB core should come back and call |
@@ -1953,8 +2484,13 @@ int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |||
1953 | * Wait for the Reset Device command to finish. Remove all structures | 2484 | * Wait for the Reset Device command to finish. Remove all structures |
1954 | * associated with the endpoints that were disabled. Clear the input device | 2485 | * associated with the endpoints that were disabled. Clear the input device |
1955 | * structure? Cache the rings? Reset the control endpoint 0 max packet size? | 2486 | * structure? Cache the rings? Reset the control endpoint 0 max packet size? |
2487 | * | ||
2488 | * If the virt_dev to be reset does not exist or does not match the udev, | ||
2489 | * it means the device is lost, possibly due to the xHC restore error and | ||
2490 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | ||
2491 | * re-allocate the device. | ||
1956 | */ | 2492 | */ |
1957 | int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev) | 2493 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) |
1958 | { | 2494 | { |
1959 | int ret, i; | 2495 | int ret, i; |
1960 | unsigned long flags; | 2496 | unsigned long flags; |
@@ -1964,19 +2500,45 @@ int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
1964 | struct xhci_command *reset_device_cmd; | 2500 | struct xhci_command *reset_device_cmd; |
1965 | int timeleft; | 2501 | int timeleft; |
1966 | int last_freed_endpoint; | 2502 | int last_freed_endpoint; |
2503 | struct xhci_slot_ctx *slot_ctx; | ||
1967 | 2504 | ||
1968 | ret = xhci_check_args(hcd, udev, NULL, 0, __func__); | 2505 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
1969 | if (ret <= 0) | 2506 | if (ret <= 0) |
1970 | return ret; | 2507 | return ret; |
1971 | xhci = hcd_to_xhci(hcd); | 2508 | xhci = hcd_to_xhci(hcd); |
1972 | slot_id = udev->slot_id; | 2509 | slot_id = udev->slot_id; |
1973 | virt_dev = xhci->devs[slot_id]; | 2510 | virt_dev = xhci->devs[slot_id]; |
1974 | if (!virt_dev) { | 2511 | if (!virt_dev) { |
1975 | xhci_dbg(xhci, "%s called with invalid slot ID %u\n", | 2512 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " |
1976 | __func__, slot_id); | 2513 | "not exist. Re-allocate the device\n", slot_id); |
1977 | return -EINVAL; | 2514 | ret = xhci_alloc_dev(hcd, udev); |
2515 | if (ret == 1) | ||
2516 | return 0; | ||
2517 | else | ||
2518 | return -EINVAL; | ||
1978 | } | 2519 | } |
1979 | 2520 | ||
2521 | if (virt_dev->udev != udev) { | ||
2522 | /* If the virt_dev and the udev does not match, this virt_dev | ||
2523 | * may belong to another udev. | ||
2524 | * Re-allocate the device. | ||
2525 | */ | ||
2526 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | ||
2527 | "not match the udev. Re-allocate the device\n", | ||
2528 | slot_id); | ||
2529 | ret = xhci_alloc_dev(hcd, udev); | ||
2530 | if (ret == 1) | ||
2531 | return 0; | ||
2532 | else | ||
2533 | return -EINVAL; | ||
2534 | } | ||
2535 | |||
2536 | /* If device is not setup, there is no point in resetting it */ | ||
2537 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | ||
2538 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | ||
2539 | SLOT_STATE_DISABLED) | ||
2540 | return 0; | ||
2541 | |||
1980 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); | 2542 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
1981 | /* Allocate the command structure that holds the struct completion. | 2543 | /* Allocate the command structure that holds the struct completion. |
1982 | * Assume we're in process context, since the normal device reset | 2544 | * Assume we're in process context, since the normal device reset |
@@ -1993,6 +2555,15 @@ int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
1993 | /* Attempt to submit the Reset Device command to the command ring */ | 2555 | /* Attempt to submit the Reset Device command to the command ring */ |
1994 | spin_lock_irqsave(&xhci->lock, flags); | 2556 | spin_lock_irqsave(&xhci->lock, flags); |
1995 | reset_device_cmd->command_trb = xhci->cmd_ring->enqueue; | 2557 | reset_device_cmd->command_trb = xhci->cmd_ring->enqueue; |
2558 | |||
2559 | /* Enqueue pointer can be left pointing to the link TRB, | ||
2560 | * we must handle that | ||
2561 | */ | ||
2562 | if ((le32_to_cpu(reset_device_cmd->command_trb->link.control) | ||
2563 | & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) | ||
2564 | reset_device_cmd->command_trb = | ||
2565 | xhci->cmd_ring->enq_seg->next->trbs; | ||
2566 | |||
1996 | list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list); | 2567 | list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list); |
1997 | ret = xhci_queue_reset_device(xhci, slot_id); | 2568 | ret = xhci_queue_reset_device(xhci, slot_id); |
1998 | if (ret) { | 2569 | if (ret) { |
@@ -2049,13 +2620,29 @@ int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
2049 | goto command_cleanup; | 2620 | goto command_cleanup; |
2050 | } | 2621 | } |
2051 | 2622 | ||
2623 | /* Free up host controller endpoint resources */ | ||
2624 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | ||
2625 | spin_lock_irqsave(&xhci->lock, flags); | ||
2626 | /* Don't delete the default control endpoint resources */ | ||
2627 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | ||
2628 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
2629 | } | ||
2630 | |||
2052 | /* Everything but endpoint 0 is disabled, so free or cache the rings. */ | 2631 | /* Everything but endpoint 0 is disabled, so free or cache the rings. */ |
2053 | last_freed_endpoint = 1; | 2632 | last_freed_endpoint = 1; |
2054 | for (i = 1; i < 31; ++i) { | 2633 | for (i = 1; i < 31; ++i) { |
2055 | if (!virt_dev->eps[i].ring) | 2634 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
2056 | continue; | 2635 | |
2057 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | 2636 | if (ep->ep_state & EP_HAS_STREAMS) { |
2058 | last_freed_endpoint = i; | 2637 | xhci_free_stream_info(xhci, ep->stream_info); |
2638 | ep->stream_info = NULL; | ||
2639 | ep->ep_state &= ~EP_HAS_STREAMS; | ||
2640 | } | ||
2641 | |||
2642 | if (ep->ring) { | ||
2643 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | ||
2644 | last_freed_endpoint = i; | ||
2645 | } | ||
2059 | } | 2646 | } |
2060 | xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); | 2647 | xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); |
2061 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); | 2648 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); |
@@ -2077,13 +2664,13 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |||
2077 | struct xhci_virt_device *virt_dev; | 2664 | struct xhci_virt_device *virt_dev; |
2078 | unsigned long flags; | 2665 | unsigned long flags; |
2079 | u32 state; | 2666 | u32 state; |
2080 | int i; | 2667 | int i, ret; |
2081 | 2668 | ||
2082 | if (udev->slot_id == 0) | 2669 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
2670 | if (ret <= 0) | ||
2083 | return; | 2671 | return; |
2672 | |||
2084 | virt_dev = xhci->devs[udev->slot_id]; | 2673 | virt_dev = xhci->devs[udev->slot_id]; |
2085 | if (!virt_dev) | ||
2086 | return; | ||
2087 | 2674 | ||
2088 | /* Stop any wayward timer functions (which may grab the lock) */ | 2675 | /* Stop any wayward timer functions (which may grab the lock) */ |
2089 | for (i = 0; i < 31; ++i) { | 2676 | for (i = 0; i < 31; ++i) { |
@@ -2114,6 +2701,27 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |||
2114 | } | 2701 | } |
2115 | 2702 | ||
2116 | /* | 2703 | /* |
2704 | * Checks if we have enough host controller resources for the default control | ||
2705 | * endpoint. | ||
2706 | * | ||
2707 | * Must be called with xhci->lock held. | ||
2708 | */ | ||
2709 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | ||
2710 | { | ||
2711 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | ||
2712 | xhci_dbg(xhci, "Not enough ep ctxs: " | ||
2713 | "%u active, need to add 1, limit is %u.\n", | ||
2714 | xhci->num_active_eps, xhci->limit_active_eps); | ||
2715 | return -ENOMEM; | ||
2716 | } | ||
2717 | xhci->num_active_eps += 1; | ||
2718 | xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n", | ||
2719 | xhci->num_active_eps); | ||
2720 | return 0; | ||
2721 | } | ||
2722 | |||
2723 | |||
2724 | /* | ||
2117 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | 2725 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command |
2118 | * timed out, or allocating memory failed. Returns 1 on success. | 2726 | * timed out, or allocating memory failed. Returns 1 on success. |
2119 | */ | 2727 | */ |
@@ -2148,20 +2756,39 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |||
2148 | xhci_err(xhci, "Error while assigning device slot ID\n"); | 2756 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
2149 | return 0; | 2757 | return 0; |
2150 | } | 2758 | } |
2151 | /* xhci_alloc_virt_device() does not touch rings; no need to lock */ | 2759 | |
2152 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) { | 2760 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { |
2153 | /* Disable slot, if we can do it without mem alloc */ | ||
2154 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); | ||
2155 | spin_lock_irqsave(&xhci->lock, flags); | 2761 | spin_lock_irqsave(&xhci->lock, flags); |
2156 | if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) | 2762 | ret = xhci_reserve_host_control_ep_resources(xhci); |
2157 | xhci_ring_cmd_db(xhci); | 2763 | if (ret) { |
2764 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
2765 | xhci_warn(xhci, "Not enough host resources, " | ||
2766 | "active endpoint contexts = %u\n", | ||
2767 | xhci->num_active_eps); | ||
2768 | goto disable_slot; | ||
2769 | } | ||
2158 | spin_unlock_irqrestore(&xhci->lock, flags); | 2770 | spin_unlock_irqrestore(&xhci->lock, flags); |
2159 | return 0; | 2771 | } |
2772 | /* Use GFP_NOIO, since this function can be called from | ||
2773 | * xhci_discover_or_reset_device(), which may be called as part of | ||
2774 | * mass storage driver error handling. | ||
2775 | */ | ||
2776 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) { | ||
2777 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); | ||
2778 | goto disable_slot; | ||
2160 | } | 2779 | } |
2161 | udev->slot_id = xhci->slot_id; | 2780 | udev->slot_id = xhci->slot_id; |
2162 | /* Is this a LS or FS device under a HS hub? */ | 2781 | /* Is this a LS or FS device under a HS hub? */ |
2163 | /* Hub or peripherial? */ | 2782 | /* Hub or peripherial? */ |
2164 | return 1; | 2783 | return 1; |
2784 | |||
2785 | disable_slot: | ||
2786 | /* Disable slot, if we can do it without mem alloc */ | ||
2787 | spin_lock_irqsave(&xhci->lock, flags); | ||
2788 | if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) | ||
2789 | xhci_ring_cmd_db(xhci); | ||
2790 | spin_unlock_irqrestore(&xhci->lock, flags); | ||
2791 | return 0; | ||
2165 | } | 2792 | } |
2166 | 2793 | ||
2167 | /* | 2794 | /* |
@@ -2191,12 +2818,28 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
2191 | 2818 | ||
2192 | virt_dev = xhci->devs[udev->slot_id]; | 2819 | virt_dev = xhci->devs[udev->slot_id]; |
2193 | 2820 | ||
2194 | /* If this is a Set Address to an unconfigured device, setup ep 0 */ | 2821 | if (WARN_ON(!virt_dev)) { |
2195 | if (!udev->config) | 2822 | /* |
2823 | * In plug/unplug torture test with an NEC controller, | ||
2824 | * a zero-dereference was observed once due to virt_dev = 0. | ||
2825 | * Print useful debug rather than crash if it is observed again! | ||
2826 | */ | ||
2827 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | ||
2828 | udev->slot_id); | ||
2829 | return -EINVAL; | ||
2830 | } | ||
2831 | |||
2832 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | ||
2833 | /* | ||
2834 | * If this is the first Set Address since device plug-in or | ||
2835 | * virt_device realloaction after a resume with an xHCI power loss, | ||
2836 | * then set up the slot context. | ||
2837 | */ | ||
2838 | if (!slot_ctx->dev_info) | ||
2196 | xhci_setup_addressable_virt_dev(xhci, udev); | 2839 | xhci_setup_addressable_virt_dev(xhci, udev); |
2840 | /* Otherwise, update the control endpoint ring enqueue pointer. */ | ||
2197 | else | 2841 | else |
2198 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | 2842 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); |
2199 | /* Otherwise, assume the core has the device configured how it wants */ | ||
2200 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); | 2843 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
2201 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); | 2844 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
2202 | 2845 | ||
@@ -2236,6 +2879,11 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
2236 | dev_warn(&udev->dev, "Device not responding to set address.\n"); | 2879 | dev_warn(&udev->dev, "Device not responding to set address.\n"); |
2237 | ret = -EPROTO; | 2880 | ret = -EPROTO; |
2238 | break; | 2881 | break; |
2882 | case COMP_DEV_ERR: | ||
2883 | dev_warn(&udev->dev, "ERROR: Incompatible device for address " | ||
2884 | "device command.\n"); | ||
2885 | ret = -ENODEV; | ||
2886 | break; | ||
2239 | case COMP_SUCCESS: | 2887 | case COMP_SUCCESS: |
2240 | xhci_dbg(xhci, "Successful Address Device command\n"); | 2888 | xhci_dbg(xhci, "Successful Address Device command\n"); |
2241 | break; | 2889 | break; |
@@ -2253,10 +2901,10 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
2253 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); | 2901 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
2254 | xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64); | 2902 | xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64); |
2255 | xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n", | 2903 | xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n", |
2256 | udev->slot_id, | 2904 | udev->slot_id, |
2257 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | 2905 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], |
2258 | (unsigned long long) | 2906 | (unsigned long long) |
2259 | xhci->dcbaa->dev_context_ptrs[udev->slot_id]); | 2907 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); |
2260 | xhci_dbg(xhci, "Output Context DMA address = %#08llx\n", | 2908 | xhci_dbg(xhci, "Output Context DMA address = %#08llx\n", |
2261 | (unsigned long long)virt_dev->out_ctx->dma); | 2909 | (unsigned long long)virt_dev->out_ctx->dma); |
2262 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); | 2910 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
@@ -2268,15 +2916,16 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
2268 | * address given back to us by the HC. | 2916 | * address given back to us by the HC. |
2269 | */ | 2917 | */ |
2270 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | 2918 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
2271 | udev->devnum = (slot_ctx->dev_state & DEV_ADDR_MASK) + 1; | 2919 | /* Use kernel assigned address for devices; store xHC assigned |
2920 | * address locally. */ | ||
2921 | virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK) | ||
2922 | + 1; | ||
2272 | /* Zero the input context control for later use */ | 2923 | /* Zero the input context control for later use */ |
2273 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); | 2924 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
2274 | ctrl_ctx->add_flags = 0; | 2925 | ctrl_ctx->add_flags = 0; |
2275 | ctrl_ctx->drop_flags = 0; | 2926 | ctrl_ctx->drop_flags = 0; |
2276 | 2927 | ||
2277 | xhci_dbg(xhci, "Device address = %d\n", udev->devnum); | 2928 | xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address); |
2278 | /* XXX Meh, not sure if anyone else but choose_address uses this. */ | ||
2279 | set_bit(udev->devnum, udev->bus->devmap.devicemap); | ||
2280 | 2929 | ||
2281 | return 0; | 2930 | return 0; |
2282 | } | 2931 | } |
@@ -2314,24 +2963,29 @@ int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, | |||
2314 | spin_lock_irqsave(&xhci->lock, flags); | 2963 | spin_lock_irqsave(&xhci->lock, flags); |
2315 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); | 2964 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
2316 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); | 2965 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
2317 | ctrl_ctx->add_flags |= SLOT_FLAG; | 2966 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2318 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); | 2967 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
2319 | slot_ctx->dev_info |= DEV_HUB; | 2968 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
2320 | if (tt->multi) | 2969 | if (tt->multi) |
2321 | slot_ctx->dev_info |= DEV_MTT; | 2970 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
2322 | if (xhci->hci_version > 0x95) { | 2971 | if (xhci->hci_version > 0x95) { |
2323 | xhci_dbg(xhci, "xHCI version %x needs hub " | 2972 | xhci_dbg(xhci, "xHCI version %x needs hub " |
2324 | "TT think time and number of ports\n", | 2973 | "TT think time and number of ports\n", |
2325 | (unsigned int) xhci->hci_version); | 2974 | (unsigned int) xhci->hci_version); |
2326 | slot_ctx->dev_info2 |= XHCI_MAX_PORTS(hdev->maxchild); | 2975 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
2327 | /* Set TT think time - convert from ns to FS bit times. | 2976 | /* Set TT think time - convert from ns to FS bit times. |
2328 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | 2977 | * 0 = 8 FS bit times, 1 = 16 FS bit times, |
2329 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | 2978 | * 2 = 24 FS bit times, 3 = 32 FS bit times. |
2979 | * | ||
2980 | * xHCI 1.0: this field shall be 0 if the device is not a | ||
2981 | * High-spped hub. | ||
2330 | */ | 2982 | */ |
2331 | think_time = tt->think_time; | 2983 | think_time = tt->think_time; |
2332 | if (think_time != 0) | 2984 | if (think_time != 0) |
2333 | think_time = (think_time / 666) - 1; | 2985 | think_time = (think_time / 666) - 1; |
2334 | slot_ctx->tt_info |= TT_THINK_TIME(think_time); | 2986 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
2987 | slot_ctx->tt_info |= | ||
2988 | cpu_to_le32(TT_THINK_TIME(think_time)); | ||
2335 | } else { | 2989 | } else { |
2336 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | 2990 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " |
2337 | "TT think time or number of ports\n", | 2991 | "TT think time or number of ports\n", |
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 34a60d9f056a..d8bbf5ccb10d 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h | |||
@@ -30,6 +30,7 @@ | |||
30 | 30 | ||
31 | /* Code sharing between pci-quirks and xhci hcd */ | 31 | /* Code sharing between pci-quirks and xhci hcd */ |
32 | #include "xhci-ext-caps.h" | 32 | #include "xhci-ext-caps.h" |
33 | #include "pci-quirks.h" | ||
33 | 34 | ||
34 | /* xHCI PCI Configuration Registers */ | 35 | /* xHCI PCI Configuration Registers */ |
35 | #define XHCI_SBRN_OFFSET (0x60) | 36 | #define XHCI_SBRN_OFFSET (0x60) |
@@ -56,13 +57,13 @@ | |||
56 | * @run_regs_off: RTSOFF - Runtime register space offset | 57 | * @run_regs_off: RTSOFF - Runtime register space offset |
57 | */ | 58 | */ |
58 | struct xhci_cap_regs { | 59 | struct xhci_cap_regs { |
59 | u32 hc_capbase; | 60 | __le32 hc_capbase; |
60 | u32 hcs_params1; | 61 | __le32 hcs_params1; |
61 | u32 hcs_params2; | 62 | __le32 hcs_params2; |
62 | u32 hcs_params3; | 63 | __le32 hcs_params3; |
63 | u32 hcc_params; | 64 | __le32 hcc_params; |
64 | u32 db_off; | 65 | __le32 db_off; |
65 | u32 run_regs_off; | 66 | __le32 run_regs_off; |
66 | /* Reserved up to (CAPLENGTH - 0x1C) */ | 67 | /* Reserved up to (CAPLENGTH - 0x1C) */ |
67 | }; | 68 | }; |
68 | 69 | ||
@@ -154,26 +155,26 @@ struct xhci_cap_regs { | |||
154 | * devices. | 155 | * devices. |
155 | */ | 156 | */ |
156 | struct xhci_op_regs { | 157 | struct xhci_op_regs { |
157 | u32 command; | 158 | __le32 command; |
158 | u32 status; | 159 | __le32 status; |
159 | u32 page_size; | 160 | __le32 page_size; |
160 | u32 reserved1; | 161 | __le32 reserved1; |
161 | u32 reserved2; | 162 | __le32 reserved2; |
162 | u32 dev_notification; | 163 | __le32 dev_notification; |
163 | u64 cmd_ring; | 164 | __le64 cmd_ring; |
164 | /* rsvd: offset 0x20-2F */ | 165 | /* rsvd: offset 0x20-2F */ |
165 | u32 reserved3[4]; | 166 | __le32 reserved3[4]; |
166 | u64 dcbaa_ptr; | 167 | __le64 dcbaa_ptr; |
167 | u32 config_reg; | 168 | __le32 config_reg; |
168 | /* rsvd: offset 0x3C-3FF */ | 169 | /* rsvd: offset 0x3C-3FF */ |
169 | u32 reserved4[241]; | 170 | __le32 reserved4[241]; |
170 | /* port 1 registers, which serve as a base address for other ports */ | 171 | /* port 1 registers, which serve as a base address for other ports */ |
171 | u32 port_status_base; | 172 | __le32 port_status_base; |
172 | u32 port_power_base; | 173 | __le32 port_power_base; |
173 | u32 port_link_base; | 174 | __le32 port_link_base; |
174 | u32 reserved5; | 175 | __le32 reserved5; |
175 | /* registers for ports 2-255 */ | 176 | /* registers for ports 2-255 */ |
176 | u32 reserved6[NUM_PORT_REGS*254]; | 177 | __le32 reserved6[NUM_PORT_REGS*254]; |
177 | }; | 178 | }; |
178 | 179 | ||
179 | /* USBCMD - USB command - command bitmasks */ | 180 | /* USBCMD - USB command - command bitmasks */ |
@@ -191,7 +192,7 @@ struct xhci_op_regs { | |||
191 | /* bits 4:6 are reserved (and should be preserved on writes). */ | 192 | /* bits 4:6 are reserved (and should be preserved on writes). */ |
192 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ | 193 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ |
193 | #define CMD_LRESET (1 << 7) | 194 | #define CMD_LRESET (1 << 7) |
194 | /* FIXME: ignoring host controller save/restore state for now. */ | 195 | /* host controller save/restore state. */ |
195 | #define CMD_CSS (1 << 8) | 196 | #define CMD_CSS (1 << 8) |
196 | #define CMD_CRS (1 << 9) | 197 | #define CMD_CRS (1 << 9) |
197 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ | 198 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ |
@@ -232,7 +233,7 @@ struct xhci_op_regs { | |||
232 | * notification type that matches a bit set in this bit field. | 233 | * notification type that matches a bit set in this bit field. |
233 | */ | 234 | */ |
234 | #define DEV_NOTE_MASK (0xffff) | 235 | #define DEV_NOTE_MASK (0xffff) |
235 | #define ENABLE_DEV_NOTE(x) (1 << x) | 236 | #define ENABLE_DEV_NOTE(x) (1 << (x)) |
236 | /* Most of the device notification types should only be used for debug. | 237 | /* Most of the device notification types should only be used for debug. |
237 | * SW does need to pay attention to function wake notifications. | 238 | * SW does need to pay attention to function wake notifications. |
238 | */ | 239 | */ |
@@ -269,6 +270,10 @@ struct xhci_op_regs { | |||
269 | * A read gives the current link PM state of the port, | 270 | * A read gives the current link PM state of the port, |
270 | * a write with Link State Write Strobe set sets the link state. | 271 | * a write with Link State Write Strobe set sets the link state. |
271 | */ | 272 | */ |
273 | #define PORT_PLS_MASK (0xf << 5) | ||
274 | #define XDEV_U0 (0x0 << 5) | ||
275 | #define XDEV_U3 (0x3 << 5) | ||
276 | #define XDEV_RESUME (0xf << 5) | ||
272 | /* true: port has power (see HCC_PPC) */ | 277 | /* true: port has power (see HCC_PPC) */ |
273 | #define PORT_POWER (1 << 9) | 278 | #define PORT_POWER (1 << 9) |
274 | /* bits 10:13 indicate device speed: | 279 | /* bits 10:13 indicate device speed: |
@@ -344,6 +349,9 @@ struct xhci_op_regs { | |||
344 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ | 349 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ |
345 | #define PORT_WR (1 << 31) | 350 | #define PORT_WR (1 << 31) |
346 | 351 | ||
352 | /* We mark duplicate entries with -1 */ | ||
353 | #define DUPLICATE_ENTRY ((u8)(-1)) | ||
354 | |||
347 | /* Port Power Management Status and Control - port_power_base bitmasks */ | 355 | /* Port Power Management Status and Control - port_power_base bitmasks */ |
348 | /* Inactivity timer value for transitions into U1, in microseconds. | 356 | /* Inactivity timer value for transitions into U1, in microseconds. |
349 | * Timeout can be up to 127us. 0xFF means an infinite timeout. | 357 | * Timeout can be up to 127us. 0xFF means an infinite timeout. |
@@ -353,6 +361,8 @@ struct xhci_op_regs { | |||
353 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) | 361 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) |
354 | /* Bits 24:31 for port testing */ | 362 | /* Bits 24:31 for port testing */ |
355 | 363 | ||
364 | /* USB2 Protocol PORTSPMSC */ | ||
365 | #define PORT_RWE (1 << 0x3) | ||
356 | 366 | ||
357 | /** | 367 | /** |
358 | * struct xhci_intr_reg - Interrupt Register Set | 368 | * struct xhci_intr_reg - Interrupt Register Set |
@@ -372,12 +382,12 @@ struct xhci_op_regs { | |||
372 | * updates the dequeue pointer. | 382 | * updates the dequeue pointer. |
373 | */ | 383 | */ |
374 | struct xhci_intr_reg { | 384 | struct xhci_intr_reg { |
375 | u32 irq_pending; | 385 | __le32 irq_pending; |
376 | u32 irq_control; | 386 | __le32 irq_control; |
377 | u32 erst_size; | 387 | __le32 erst_size; |
378 | u32 rsvd; | 388 | __le32 rsvd; |
379 | u64 erst_base; | 389 | __le64 erst_base; |
380 | u64 erst_dequeue; | 390 | __le64 erst_dequeue; |
381 | }; | 391 | }; |
382 | 392 | ||
383 | /* irq_pending bitmasks */ | 393 | /* irq_pending bitmasks */ |
@@ -422,30 +432,44 @@ struct xhci_intr_reg { | |||
422 | * or larger accesses" | 432 | * or larger accesses" |
423 | */ | 433 | */ |
424 | struct xhci_run_regs { | 434 | struct xhci_run_regs { |
425 | u32 microframe_index; | 435 | __le32 microframe_index; |
426 | u32 rsvd[7]; | 436 | __le32 rsvd[7]; |
427 | struct xhci_intr_reg ir_set[128]; | 437 | struct xhci_intr_reg ir_set[128]; |
428 | }; | 438 | }; |
429 | 439 | ||
430 | /** | 440 | /** |
431 | * struct doorbell_array | 441 | * struct doorbell_array |
432 | * | 442 | * |
443 | * Bits 0 - 7: Endpoint target | ||
444 | * Bits 8 - 15: RsvdZ | ||
445 | * Bits 16 - 31: Stream ID | ||
446 | * | ||
433 | * Section 5.6 | 447 | * Section 5.6 |
434 | */ | 448 | */ |
435 | struct xhci_doorbell_array { | 449 | struct xhci_doorbell_array { |
436 | u32 doorbell[256]; | 450 | __le32 doorbell[256]; |
437 | }; | 451 | }; |
438 | 452 | ||
439 | #define DB_TARGET_MASK 0xFFFFFF00 | 453 | #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) |
440 | #define DB_STREAM_ID_MASK 0x0000FFFF | 454 | #define DB_VALUE_HOST 0x00000000 |
441 | #define DB_TARGET_HOST 0x0 | ||
442 | #define DB_STREAM_ID_HOST 0x0 | ||
443 | #define DB_MASK (0xff << 8) | ||
444 | 455 | ||
445 | /* Endpoint Target - bits 0:7 */ | 456 | /** |
446 | #define EPI_TO_DB(p) (((p) + 1) & 0xff) | 457 | * struct xhci_protocol_caps |
447 | #define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16) | 458 | * @revision: major revision, minor revision, capability ID, |
459 | * and next capability pointer. | ||
460 | * @name_string: Four ASCII characters to say which spec this xHC | ||
461 | * follows, typically "USB ". | ||
462 | * @port_info: Port offset, count, and protocol-defined information. | ||
463 | */ | ||
464 | struct xhci_protocol_caps { | ||
465 | u32 revision; | ||
466 | u32 name_string; | ||
467 | u32 port_info; | ||
468 | }; | ||
448 | 469 | ||
470 | #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) | ||
471 | #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) | ||
472 | #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) | ||
449 | 473 | ||
450 | /** | 474 | /** |
451 | * struct xhci_container_ctx | 475 | * struct xhci_container_ctx |
@@ -480,12 +504,12 @@ struct xhci_container_ctx { | |||
480 | * reserved at the end of the slot context for HC internal use. | 504 | * reserved at the end of the slot context for HC internal use. |
481 | */ | 505 | */ |
482 | struct xhci_slot_ctx { | 506 | struct xhci_slot_ctx { |
483 | u32 dev_info; | 507 | __le32 dev_info; |
484 | u32 dev_info2; | 508 | __le32 dev_info2; |
485 | u32 tt_info; | 509 | __le32 tt_info; |
486 | u32 dev_state; | 510 | __le32 dev_state; |
487 | /* offset 0x10 to 0x1f reserved for HC internal use */ | 511 | /* offset 0x10 to 0x1f reserved for HC internal use */ |
488 | u32 reserved[4]; | 512 | __le32 reserved[4]; |
489 | }; | 513 | }; |
490 | 514 | ||
491 | /* dev_info bitmasks */ | 515 | /* dev_info bitmasks */ |
@@ -510,6 +534,7 @@ struct xhci_slot_ctx { | |||
510 | #define MAX_EXIT (0xffff) | 534 | #define MAX_EXIT (0xffff) |
511 | /* Root hub port number that is needed to access the USB device */ | 535 | /* Root hub port number that is needed to access the USB device */ |
512 | #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) | 536 | #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) |
537 | #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) | ||
513 | /* Maximum number of ports under a hub device */ | 538 | /* Maximum number of ports under a hub device */ |
514 | #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) | 539 | #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) |
515 | 540 | ||
@@ -535,6 +560,11 @@ struct xhci_slot_ctx { | |||
535 | #define SLOT_STATE (0x1f << 27) | 560 | #define SLOT_STATE (0x1f << 27) |
536 | #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) | 561 | #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) |
537 | 562 | ||
563 | #define SLOT_STATE_DISABLED 0 | ||
564 | #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED | ||
565 | #define SLOT_STATE_DEFAULT 1 | ||
566 | #define SLOT_STATE_ADDRESSED 2 | ||
567 | #define SLOT_STATE_CONFIGURED 3 | ||
538 | 568 | ||
539 | /** | 569 | /** |
540 | * struct xhci_ep_ctx | 570 | * struct xhci_ep_ctx |
@@ -555,12 +585,12 @@ struct xhci_slot_ctx { | |||
555 | * reserved at the end of the endpoint context for HC internal use. | 585 | * reserved at the end of the endpoint context for HC internal use. |
556 | */ | 586 | */ |
557 | struct xhci_ep_ctx { | 587 | struct xhci_ep_ctx { |
558 | u32 ep_info; | 588 | __le32 ep_info; |
559 | u32 ep_info2; | 589 | __le32 ep_info2; |
560 | u64 deq; | 590 | __le64 deq; |
561 | u32 tx_info; | 591 | __le32 tx_info; |
562 | /* offset 0x14 - 0x1f reserved for HC internal use */ | 592 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
563 | u32 reserved[3]; | 593 | __le32 reserved[3]; |
564 | }; | 594 | }; |
565 | 595 | ||
566 | /* ep_info bitmasks */ | 596 | /* ep_info bitmasks */ |
@@ -580,11 +610,11 @@ struct xhci_ep_ctx { | |||
580 | #define EP_STATE_STOPPED 3 | 610 | #define EP_STATE_STOPPED 3 |
581 | #define EP_STATE_ERROR 4 | 611 | #define EP_STATE_ERROR 4 |
582 | /* Mult - Max number of burtst within an interval, in EP companion desc. */ | 612 | /* Mult - Max number of burtst within an interval, in EP companion desc. */ |
583 | #define EP_MULT(p) ((p & 0x3) << 8) | 613 | #define EP_MULT(p) (((p) & 0x3) << 8) |
584 | /* bits 10:14 are Max Primary Streams */ | 614 | /* bits 10:14 are Max Primary Streams */ |
585 | /* bit 15 is Linear Stream Array */ | 615 | /* bit 15 is Linear Stream Array */ |
586 | /* Interval - period between requests to an endpoint - 125u increments. */ | 616 | /* Interval - period between requests to an endpoint - 125u increments. */ |
587 | #define EP_INTERVAL(p) ((p & 0xff) << 16) | 617 | #define EP_INTERVAL(p) (((p) & 0xff) << 16) |
588 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) | 618 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) |
589 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) | 619 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) |
590 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) | 620 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) |
@@ -614,10 +644,18 @@ struct xhci_ep_ctx { | |||
614 | #define MAX_PACKET_MASK (0xffff << 16) | 644 | #define MAX_PACKET_MASK (0xffff << 16) |
615 | #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) | 645 | #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) |
616 | 646 | ||
647 | /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. | ||
648 | * USB2.0 spec 9.6.6. | ||
649 | */ | ||
650 | #define GET_MAX_PACKET(p) ((p) & 0x7ff) | ||
651 | |||
617 | /* tx_info bitmasks */ | 652 | /* tx_info bitmasks */ |
618 | #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) | 653 | #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) |
619 | #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) | 654 | #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) |
620 | 655 | ||
656 | /* deq bitmasks */ | ||
657 | #define EP_CTX_CYCLE_MASK (1 << 0) | ||
658 | |||
621 | 659 | ||
622 | /** | 660 | /** |
623 | * struct xhci_input_control_context | 661 | * struct xhci_input_control_context |
@@ -627,9 +665,9 @@ struct xhci_ep_ctx { | |||
627 | * @add_context: set the bit of the endpoint context you want to enable | 665 | * @add_context: set the bit of the endpoint context you want to enable |
628 | */ | 666 | */ |
629 | struct xhci_input_control_ctx { | 667 | struct xhci_input_control_ctx { |
630 | u32 drop_flags; | 668 | __le32 drop_flags; |
631 | u32 add_flags; | 669 | __le32 add_flags; |
632 | u32 rsvd2[6]; | 670 | __le32 rsvd2[6]; |
633 | }; | 671 | }; |
634 | 672 | ||
635 | /* Represents everything that is needed to issue a command on the command ring. | 673 | /* Represents everything that is needed to issue a command on the command ring. |
@@ -655,9 +693,9 @@ struct xhci_command { | |||
655 | 693 | ||
656 | struct xhci_stream_ctx { | 694 | struct xhci_stream_ctx { |
657 | /* 64-bit stream ring address, cycle state, and stream type */ | 695 | /* 64-bit stream ring address, cycle state, and stream type */ |
658 | u64 stream_ring; | 696 | __le64 stream_ring; |
659 | /* offset 0x14 - 0x1f reserved for HC internal use */ | 697 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
660 | u32 reserved[2]; | 698 | __le32 reserved[2]; |
661 | }; | 699 | }; |
662 | 700 | ||
663 | /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ | 701 | /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ |
@@ -720,6 +758,12 @@ struct xhci_virt_ep { | |||
720 | struct timer_list stop_cmd_timer; | 758 | struct timer_list stop_cmd_timer; |
721 | int stop_cmds_pending; | 759 | int stop_cmds_pending; |
722 | struct xhci_hcd *xhci; | 760 | struct xhci_hcd *xhci; |
761 | /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue | ||
762 | * command. We'll need to update the ring's dequeue segment and dequeue | ||
763 | * pointer after the command completes. | ||
764 | */ | ||
765 | struct xhci_segment *queued_deq_seg; | ||
766 | union xhci_trb *queued_deq_ptr; | ||
723 | /* | 767 | /* |
724 | * Sometimes the xHC can not process isochronous endpoint ring quickly | 768 | * Sometimes the xHC can not process isochronous endpoint ring quickly |
725 | * enough, and it will miss some isoc tds on the ring and generate | 769 | * enough, and it will miss some isoc tds on the ring and generate |
@@ -731,6 +775,7 @@ struct xhci_virt_ep { | |||
731 | }; | 775 | }; |
732 | 776 | ||
733 | struct xhci_virt_device { | 777 | struct xhci_virt_device { |
778 | struct usb_device *udev; | ||
734 | /* | 779 | /* |
735 | * Commands to the hardware are passed an "input context" that | 780 | * Commands to the hardware are passed an "input context" that |
736 | * tells the hardware what to change in its data structures. | 781 | * tells the hardware what to change in its data structures. |
@@ -745,12 +790,15 @@ struct xhci_virt_device { | |||
745 | /* Rings saved to ensure old alt settings can be re-instated */ | 790 | /* Rings saved to ensure old alt settings can be re-instated */ |
746 | struct xhci_ring **ring_cache; | 791 | struct xhci_ring **ring_cache; |
747 | int num_rings_cached; | 792 | int num_rings_cached; |
793 | /* Store xHC assigned device address */ | ||
794 | int address; | ||
748 | #define XHCI_MAX_RINGS_CACHED 31 | 795 | #define XHCI_MAX_RINGS_CACHED 31 |
749 | struct xhci_virt_ep eps[31]; | 796 | struct xhci_virt_ep eps[31]; |
750 | struct completion cmd_completion; | 797 | struct completion cmd_completion; |
751 | /* Status of the last command issued for this device */ | 798 | /* Status of the last command issued for this device */ |
752 | u32 cmd_status; | 799 | u32 cmd_status; |
753 | struct list_head cmd_list; | 800 | struct list_head cmd_list; |
801 | u8 port; | ||
754 | }; | 802 | }; |
755 | 803 | ||
756 | 804 | ||
@@ -760,7 +808,7 @@ struct xhci_virt_device { | |||
760 | */ | 808 | */ |
761 | struct xhci_device_context_array { | 809 | struct xhci_device_context_array { |
762 | /* 64-bit device addresses; we only write 32-bit addresses */ | 810 | /* 64-bit device addresses; we only write 32-bit addresses */ |
763 | u64 dev_context_ptrs[MAX_HC_SLOTS]; | 811 | __le64 dev_context_ptrs[MAX_HC_SLOTS]; |
764 | /* private xHCD pointers */ | 812 | /* private xHCD pointers */ |
765 | dma_addr_t dma; | 813 | dma_addr_t dma; |
766 | }; | 814 | }; |
@@ -773,10 +821,10 @@ struct xhci_device_context_array { | |||
773 | 821 | ||
774 | struct xhci_transfer_event { | 822 | struct xhci_transfer_event { |
775 | /* 64-bit buffer address, or immediate data */ | 823 | /* 64-bit buffer address, or immediate data */ |
776 | u64 buffer; | 824 | __le64 buffer; |
777 | u32 transfer_len; | 825 | __le32 transfer_len; |
778 | /* This field is interpreted differently based on the type of TRB */ | 826 | /* This field is interpreted differently based on the type of TRB */ |
779 | u32 flags; | 827 | __le32 flags; |
780 | }; | 828 | }; |
781 | 829 | ||
782 | /** Transfer Event bit fields **/ | 830 | /** Transfer Event bit fields **/ |
@@ -826,6 +874,8 @@ struct xhci_transfer_event { | |||
826 | #define COMP_PING_ERR 20 | 874 | #define COMP_PING_ERR 20 |
827 | /* Event Ring is full */ | 875 | /* Event Ring is full */ |
828 | #define COMP_ER_FULL 21 | 876 | #define COMP_ER_FULL 21 |
877 | /* Incompatible Device Error */ | ||
878 | #define COMP_DEV_ERR 22 | ||
829 | /* Missed Service Error - HC couldn't service an isoc ep within interval */ | 879 | /* Missed Service Error - HC couldn't service an isoc ep within interval */ |
830 | #define COMP_MISSED_INT 23 | 880 | #define COMP_MISSED_INT 23 |
831 | /* Successfully stopped command ring */ | 881 | /* Successfully stopped command ring */ |
@@ -834,11 +884,13 @@ struct xhci_transfer_event { | |||
834 | #define COMP_CMD_ABORT 25 | 884 | #define COMP_CMD_ABORT 25 |
835 | /* Stopped - transfer was terminated by a stop endpoint command */ | 885 | /* Stopped - transfer was terminated by a stop endpoint command */ |
836 | #define COMP_STOP 26 | 886 | #define COMP_STOP 26 |
837 | /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ | 887 | /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ |
838 | #define COMP_STOP_INVAL 27 | 888 | #define COMP_STOP_INVAL 27 |
839 | /* Control Abort Error - Debug Capability - control pipe aborted */ | 889 | /* Control Abort Error - Debug Capability - control pipe aborted */ |
840 | #define COMP_DBG_ABORT 28 | 890 | #define COMP_DBG_ABORT 28 |
841 | /* TRB type 29 and 30 reserved */ | 891 | /* Max Exit Latency Too Large Error */ |
892 | #define COMP_MEL_ERR 29 | ||
893 | /* TRB type 30 reserved */ | ||
842 | /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ | 894 | /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ |
843 | #define COMP_BUFF_OVER 31 | 895 | #define COMP_BUFF_OVER 31 |
844 | /* Event Lost Error - xHC has an "internal event overrun condition" */ | 896 | /* Event Lost Error - xHC has an "internal event overrun condition" */ |
@@ -855,9 +907,9 @@ struct xhci_transfer_event { | |||
855 | 907 | ||
856 | struct xhci_link_trb { | 908 | struct xhci_link_trb { |
857 | /* 64-bit segment pointer*/ | 909 | /* 64-bit segment pointer*/ |
858 | u64 segment_ptr; | 910 | __le64 segment_ptr; |
859 | u32 intr_target; | 911 | __le32 intr_target; |
860 | u32 control; | 912 | __le32 control; |
861 | }; | 913 | }; |
862 | 914 | ||
863 | /* control bitfields */ | 915 | /* control bitfields */ |
@@ -866,9 +918,9 @@ struct xhci_link_trb { | |||
866 | /* Command completion event TRB */ | 918 | /* Command completion event TRB */ |
867 | struct xhci_event_cmd { | 919 | struct xhci_event_cmd { |
868 | /* Pointer to command TRB, or the value passed by the event data trb */ | 920 | /* Pointer to command TRB, or the value passed by the event data trb */ |
869 | u64 cmd_trb; | 921 | __le64 cmd_trb; |
870 | u32 status; | 922 | __le32 status; |
871 | u32 flags; | 923 | __le32 flags; |
872 | }; | 924 | }; |
873 | 925 | ||
874 | /* flags bitmasks */ | 926 | /* flags bitmasks */ |
@@ -881,6 +933,10 @@ struct xhci_event_cmd { | |||
881 | #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) | 933 | #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) |
882 | #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) | 934 | #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) |
883 | 935 | ||
936 | #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) | ||
937 | #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) | ||
938 | #define LAST_EP_INDEX 30 | ||
939 | |||
884 | /* Set TR Dequeue Pointer command TRB fields */ | 940 | /* Set TR Dequeue Pointer command TRB fields */ |
885 | #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) | 941 | #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) |
886 | #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) | 942 | #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) |
@@ -896,6 +952,8 @@ struct xhci_event_cmd { | |||
896 | /* Interrupter Target - which MSI-X vector to target the completion event at */ | 952 | /* Interrupter Target - which MSI-X vector to target the completion event at */ |
897 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) | 953 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) |
898 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) | 954 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) |
955 | #define TRB_TBC(p) (((p) & 0x3) << 7) | ||
956 | #define TRB_TLBPC(p) (((p) & 0xf) << 16) | ||
899 | 957 | ||
900 | /* Cycle bit - indicates TRB ownership by HC or HCD */ | 958 | /* Cycle bit - indicates TRB ownership by HC or HCD */ |
901 | #define TRB_CYCLE (1<<0) | 959 | #define TRB_CYCLE (1<<0) |
@@ -915,15 +973,20 @@ struct xhci_event_cmd { | |||
915 | /* The buffer pointer contains immediate data */ | 973 | /* The buffer pointer contains immediate data */ |
916 | #define TRB_IDT (1<<6) | 974 | #define TRB_IDT (1<<6) |
917 | 975 | ||
976 | /* Block Event Interrupt */ | ||
977 | #define TRB_BEI (1<<9) | ||
918 | 978 | ||
919 | /* Control transfer TRB specific fields */ | 979 | /* Control transfer TRB specific fields */ |
920 | #define TRB_DIR_IN (1<<16) | 980 | #define TRB_DIR_IN (1<<16) |
981 | #define TRB_TX_TYPE(p) ((p) << 16) | ||
982 | #define TRB_DATA_OUT 2 | ||
983 | #define TRB_DATA_IN 3 | ||
921 | 984 | ||
922 | /* Isochronous TRB specific fields */ | 985 | /* Isochronous TRB specific fields */ |
923 | #define TRB_SIA (1<<31) | 986 | #define TRB_SIA (1<<31) |
924 | 987 | ||
925 | struct xhci_generic_trb { | 988 | struct xhci_generic_trb { |
926 | u32 field[4]; | 989 | __le32 field[4]; |
927 | }; | 990 | }; |
928 | 991 | ||
929 | union xhci_trb { | 992 | union xhci_trb { |
@@ -1067,14 +1130,15 @@ struct xhci_ring { | |||
1067 | */ | 1130 | */ |
1068 | u32 cycle_state; | 1131 | u32 cycle_state; |
1069 | unsigned int stream_id; | 1132 | unsigned int stream_id; |
1133 | bool last_td_was_short; | ||
1070 | }; | 1134 | }; |
1071 | 1135 | ||
1072 | struct xhci_erst_entry { | 1136 | struct xhci_erst_entry { |
1073 | /* 64-bit event ring segment address */ | 1137 | /* 64-bit event ring segment address */ |
1074 | u64 seg_addr; | 1138 | __le64 seg_addr; |
1075 | u32 seg_size; | 1139 | __le32 seg_size; |
1076 | /* Set to zero */ | 1140 | /* Set to zero */ |
1077 | u32 rsvd; | 1141 | __le32 rsvd; |
1078 | }; | 1142 | }; |
1079 | 1143 | ||
1080 | struct xhci_erst { | 1144 | struct xhci_erst { |
@@ -1115,9 +1179,41 @@ struct urb_priv { | |||
1115 | #define XHCI_STOP_EP_CMD_TIMEOUT 5 | 1179 | #define XHCI_STOP_EP_CMD_TIMEOUT 5 |
1116 | /* XXX: Make these module parameters */ | 1180 | /* XXX: Make these module parameters */ |
1117 | 1181 | ||
1182 | struct s3_save { | ||
1183 | u32 command; | ||
1184 | u32 dev_nt; | ||
1185 | u64 dcbaa_ptr; | ||
1186 | u32 config_reg; | ||
1187 | u32 irq_pending; | ||
1188 | u32 irq_control; | ||
1189 | u32 erst_size; | ||
1190 | u64 erst_base; | ||
1191 | u64 erst_dequeue; | ||
1192 | }; | ||
1193 | |||
1194 | struct xhci_bus_state { | ||
1195 | unsigned long bus_suspended; | ||
1196 | unsigned long next_statechange; | ||
1197 | |||
1198 | /* Port suspend arrays are indexed by the portnum of the fake roothub */ | ||
1199 | /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ | ||
1200 | u32 port_c_suspend; | ||
1201 | u32 suspended_ports; | ||
1202 | unsigned long resume_done[USB_MAXCHILDREN]; | ||
1203 | }; | ||
1204 | |||
1205 | static inline unsigned int hcd_index(struct usb_hcd *hcd) | ||
1206 | { | ||
1207 | if (hcd->speed == HCD_USB3) | ||
1208 | return 0; | ||
1209 | else | ||
1210 | return 1; | ||
1211 | } | ||
1118 | 1212 | ||
1119 | /* There is one ehci_hci structure per controller */ | 1213 | /* There is one ehci_hci structure per controller */ |
1120 | struct xhci_hcd { | 1214 | struct xhci_hcd { |
1215 | struct usb_hcd *main_hcd; | ||
1216 | struct usb_hcd *shared_hcd; | ||
1121 | /* glue to PCI and HCD framework */ | 1217 | /* glue to PCI and HCD framework */ |
1122 | struct xhci_cap_regs __iomem *cap_regs; | 1218 | struct xhci_cap_regs __iomem *cap_regs; |
1123 | struct xhci_op_regs __iomem *op_regs; | 1219 | struct xhci_op_regs __iomem *op_regs; |
@@ -1178,6 +1274,9 @@ struct xhci_hcd { | |||
1178 | #endif | 1274 | #endif |
1179 | /* Host controller watchdog timer structures */ | 1275 | /* Host controller watchdog timer structures */ |
1180 | unsigned int xhc_state; | 1276 | unsigned int xhc_state; |
1277 | |||
1278 | u32 command; | ||
1279 | struct s3_save s3; | ||
1181 | /* Host controller is dying - not responding to commands. "I'm not dead yet!" | 1280 | /* Host controller is dying - not responding to commands. "I'm not dead yet!" |
1182 | * | 1281 | * |
1183 | * xHC interrupts have been disabled and a watchdog timer will (or has already) | 1282 | * xHC interrupts have been disabled and a watchdog timer will (or has already) |
@@ -1191,28 +1290,50 @@ struct xhci_hcd { | |||
1191 | * There are no reports of xHCI host controllers that display this issue. | 1290 | * There are no reports of xHCI host controllers that display this issue. |
1192 | */ | 1291 | */ |
1193 | #define XHCI_STATE_DYING (1 << 0) | 1292 | #define XHCI_STATE_DYING (1 << 0) |
1293 | #define XHCI_STATE_HALTED (1 << 1) | ||
1194 | /* Statistics */ | 1294 | /* Statistics */ |
1195 | int noops_submitted; | ||
1196 | int noops_handled; | ||
1197 | int error_bitmask; | 1295 | int error_bitmask; |
1198 | unsigned int quirks; | 1296 | unsigned int quirks; |
1199 | #define XHCI_LINK_TRB_QUIRK (1 << 0) | 1297 | #define XHCI_LINK_TRB_QUIRK (1 << 0) |
1200 | #define XHCI_RESET_EP_QUIRK (1 << 1) | 1298 | #define XHCI_RESET_EP_QUIRK (1 << 1) |
1201 | #define XHCI_NEC_HOST (1 << 2) | 1299 | #define XHCI_NEC_HOST (1 << 2) |
1300 | #define XHCI_AMD_PLL_FIX (1 << 3) | ||
1301 | #define XHCI_SPURIOUS_SUCCESS (1 << 4) | ||
1302 | /* | ||
1303 | * Certain Intel host controllers have a limit to the number of endpoint | ||
1304 | * contexts they can handle. Ideally, they would signal that they can't handle | ||
1305 | * anymore endpoint contexts by returning a Resource Error for the Configure | ||
1306 | * Endpoint command, but they don't. Instead they expect software to keep track | ||
1307 | * of the number of active endpoints for them, across configure endpoint | ||
1308 | * commands, reset device commands, disable slot commands, and address device | ||
1309 | * commands. | ||
1310 | */ | ||
1311 | #define XHCI_EP_LIMIT_QUIRK (1 << 5) | ||
1312 | #define XHCI_BROKEN_MSI (1 << 6) | ||
1313 | #define XHCI_RESET_ON_RESUME (1 << 7) | ||
1314 | unsigned int num_active_eps; | ||
1315 | unsigned int limit_active_eps; | ||
1316 | /* There are two roothubs to keep track of bus suspend info for */ | ||
1317 | struct xhci_bus_state bus_state[2]; | ||
1318 | /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ | ||
1319 | u8 *port_array; | ||
1320 | /* Array of pointers to USB 3.0 PORTSC registers */ | ||
1321 | __le32 __iomem **usb3_ports; | ||
1322 | unsigned int num_usb3_ports; | ||
1323 | /* Array of pointers to USB 2.0 PORTSC registers */ | ||
1324 | __le32 __iomem **usb2_ports; | ||
1325 | unsigned int num_usb2_ports; | ||
1202 | }; | 1326 | }; |
1203 | 1327 | ||
1204 | /* For testing purposes */ | ||
1205 | #define NUM_TEST_NOOPS 0 | ||
1206 | |||
1207 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ | 1328 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1208 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) | 1329 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) |
1209 | { | 1330 | { |
1210 | return (struct xhci_hcd *) (hcd->hcd_priv); | 1331 | return *((struct xhci_hcd **) (hcd->hcd_priv)); |
1211 | } | 1332 | } |
1212 | 1333 | ||
1213 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | 1334 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) |
1214 | { | 1335 | { |
1215 | return container_of((void *) xhci, struct usb_hcd, hcd_priv); | 1336 | return xhci->main_hcd; |
1216 | } | 1337 | } |
1217 | 1338 | ||
1218 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | 1339 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
@@ -1233,16 +1354,13 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | |||
1233 | /* TODO: copied from ehci.h - can be refactored? */ | 1354 | /* TODO: copied from ehci.h - can be refactored? */ |
1234 | /* xHCI spec says all registers are little endian */ | 1355 | /* xHCI spec says all registers are little endian */ |
1235 | static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, | 1356 | static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, |
1236 | __u32 __iomem *regs) | 1357 | __le32 __iomem *regs) |
1237 | { | 1358 | { |
1238 | return readl(regs); | 1359 | return readl(regs); |
1239 | } | 1360 | } |
1240 | static inline void xhci_writel(struct xhci_hcd *xhci, | 1361 | static inline void xhci_writel(struct xhci_hcd *xhci, |
1241 | const unsigned int val, __u32 __iomem *regs) | 1362 | const unsigned int val, __le32 __iomem *regs) |
1242 | { | 1363 | { |
1243 | xhci_dbg(xhci, | ||
1244 | "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", | ||
1245 | regs, val); | ||
1246 | writel(val, regs); | 1364 | writel(val, regs); |
1247 | } | 1365 | } |
1248 | 1366 | ||
@@ -1256,7 +1374,7 @@ static inline void xhci_writel(struct xhci_hcd *xhci, | |||
1256 | * the high dword, and write order is irrelevant. | 1374 | * the high dword, and write order is irrelevant. |
1257 | */ | 1375 | */ |
1258 | static inline u64 xhci_read_64(const struct xhci_hcd *xhci, | 1376 | static inline u64 xhci_read_64(const struct xhci_hcd *xhci, |
1259 | __u64 __iomem *regs) | 1377 | __le64 __iomem *regs) |
1260 | { | 1378 | { |
1261 | __u32 __iomem *ptr = (__u32 __iomem *) regs; | 1379 | __u32 __iomem *ptr = (__u32 __iomem *) regs; |
1262 | u64 val_lo = readl(ptr); | 1380 | u64 val_lo = readl(ptr); |
@@ -1264,15 +1382,12 @@ static inline u64 xhci_read_64(const struct xhci_hcd *xhci, | |||
1264 | return val_lo + (val_hi << 32); | 1382 | return val_lo + (val_hi << 32); |
1265 | } | 1383 | } |
1266 | static inline void xhci_write_64(struct xhci_hcd *xhci, | 1384 | static inline void xhci_write_64(struct xhci_hcd *xhci, |
1267 | const u64 val, __u64 __iomem *regs) | 1385 | const u64 val, __le64 __iomem *regs) |
1268 | { | 1386 | { |
1269 | __u32 __iomem *ptr = (__u32 __iomem *) regs; | 1387 | __u32 __iomem *ptr = (__u32 __iomem *) regs; |
1270 | u32 val_lo = lower_32_bits(val); | 1388 | u32 val_lo = lower_32_bits(val); |
1271 | u32 val_hi = upper_32_bits(val); | 1389 | u32 val_hi = upper_32_bits(val); |
1272 | 1390 | ||
1273 | xhci_dbg(xhci, | ||
1274 | "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", | ||
1275 | regs, (long unsigned int) val); | ||
1276 | writel(val_lo, ptr); | 1391 | writel(val_lo, ptr); |
1277 | writel(val_hi, ptr + 1); | 1392 | writel(val_hi, ptr + 1); |
1278 | } | 1393 | } |
@@ -1285,7 +1400,7 @@ static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) | |||
1285 | } | 1400 | } |
1286 | 1401 | ||
1287 | /* xHCI debugging */ | 1402 | /* xHCI debugging */ |
1288 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); | 1403 | void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); |
1289 | void xhci_print_registers(struct xhci_hcd *xhci); | 1404 | void xhci_print_registers(struct xhci_hcd *xhci); |
1290 | void xhci_dbg_regs(struct xhci_hcd *xhci); | 1405 | void xhci_dbg_regs(struct xhci_hcd *xhci); |
1291 | void xhci_print_run_regs(struct xhci_hcd *xhci); | 1406 | void xhci_print_run_regs(struct xhci_hcd *xhci); |
@@ -1341,6 +1456,8 @@ void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |||
1341 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, | 1456 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, |
1342 | struct xhci_ep_ctx *ep_ctx, | 1457 | struct xhci_ep_ctx *ep_ctx, |
1343 | struct xhci_virt_ep *ep); | 1458 | struct xhci_virt_ep *ep); |
1459 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | ||
1460 | struct xhci_virt_device *virt_dev, bool drop_control_ep); | ||
1344 | struct xhci_ring *xhci_dma_to_transfer_ring( | 1461 | struct xhci_ring *xhci_dma_to_transfer_ring( |
1345 | struct xhci_virt_ep *ep, | 1462 | struct xhci_virt_ep *ep, |
1346 | u64 address); | 1463 | u64 address); |
@@ -1369,6 +1486,15 @@ int xhci_init(struct usb_hcd *hcd); | |||
1369 | int xhci_run(struct usb_hcd *hcd); | 1486 | int xhci_run(struct usb_hcd *hcd); |
1370 | void xhci_stop(struct usb_hcd *hcd); | 1487 | void xhci_stop(struct usb_hcd *hcd); |
1371 | void xhci_shutdown(struct usb_hcd *hcd); | 1488 | void xhci_shutdown(struct usb_hcd *hcd); |
1489 | |||
1490 | #ifdef CONFIG_PM | ||
1491 | int xhci_suspend(struct xhci_hcd *xhci); | ||
1492 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated); | ||
1493 | #else | ||
1494 | #define xhci_suspend NULL | ||
1495 | #define xhci_resume NULL | ||
1496 | #endif | ||
1497 | |||
1372 | int xhci_get_frame(struct usb_hcd *hcd); | 1498 | int xhci_get_frame(struct usb_hcd *hcd); |
1373 | irqreturn_t xhci_irq(struct usb_hcd *hcd); | 1499 | irqreturn_t xhci_irq(struct usb_hcd *hcd); |
1374 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); | 1500 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); |
@@ -1388,7 +1514,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); | |||
1388 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); | 1514 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); |
1389 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); | 1515 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); |
1390 | void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); | 1516 | void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); |
1391 | int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev); | 1517 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); |
1392 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); | 1518 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
1393 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); | 1519 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
1394 | 1520 | ||
@@ -1399,14 +1525,13 @@ struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, | |||
1399 | dma_addr_t suspect_dma); | 1525 | dma_addr_t suspect_dma); |
1400 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); | 1526 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); |
1401 | void xhci_ring_cmd_db(struct xhci_hcd *xhci); | 1527 | void xhci_ring_cmd_db(struct xhci_hcd *xhci); |
1402 | void *xhci_setup_one_noop(struct xhci_hcd *xhci); | ||
1403 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); | 1528 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); |
1404 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | 1529 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
1405 | u32 slot_id); | 1530 | u32 slot_id); |
1406 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, | 1531 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
1407 | u32 field1, u32 field2, u32 field3, u32 field4); | 1532 | u32 field1, u32 field2, u32 field3, u32 field4); |
1408 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, | 1533 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
1409 | unsigned int ep_index); | 1534 | unsigned int ep_index, int suspend); |
1410 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, | 1535 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
1411 | int slot_id, unsigned int ep_index); | 1536 | int slot_id, unsigned int ep_index); |
1412 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, | 1537 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
@@ -1436,12 +1561,27 @@ void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, | |||
1436 | unsigned int slot_id, unsigned int ep_index, | 1561 | unsigned int slot_id, unsigned int ep_index, |
1437 | struct xhci_dequeue_state *deq_state); | 1562 | struct xhci_dequeue_state *deq_state); |
1438 | void xhci_stop_endpoint_command_watchdog(unsigned long arg); | 1563 | void xhci_stop_endpoint_command_watchdog(unsigned long arg); |
1564 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, | ||
1565 | unsigned int ep_index, unsigned int stream_id); | ||
1439 | 1566 | ||
1440 | /* xHCI roothub code */ | 1567 | /* xHCI roothub code */ |
1441 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, | 1568 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, |
1442 | char *buf, u16 wLength); | 1569 | char *buf, u16 wLength); |
1443 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); | 1570 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); |
1444 | 1571 | ||
1572 | #ifdef CONFIG_PM | ||
1573 | int xhci_bus_suspend(struct usb_hcd *hcd); | ||
1574 | int xhci_bus_resume(struct usb_hcd *hcd); | ||
1575 | #else | ||
1576 | #define xhci_bus_suspend NULL | ||
1577 | #define xhci_bus_resume NULL | ||
1578 | #endif /* CONFIG_PM */ | ||
1579 | |||
1580 | u32 xhci_port_state_to_neutral(u32 state); | ||
1581 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, | ||
1582 | u16 port); | ||
1583 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); | ||
1584 | |||
1445 | /* xHCI contexts */ | 1585 | /* xHCI contexts */ |
1446 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); | 1586 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); |
1447 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); | 1587 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); |