1 files changed, 77 insertions, 68 deletions

diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index ba1be6b7cc6d..e12db7cfb9bb 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -57,13 +57,13 @@
  * @run_regs_off:       RTSOFF - Runtime register space offset
  */
 struct xhci_cap_regs {
-        u32     hc_capbase;
-        u32     hcs_params1;
-        u32     hcs_params2;
-        u32     hcs_params3;
-        u32     hcc_params;
-        u32     db_off;
-        u32     run_regs_off;
+        __le32  hc_capbase;
+        __le32  hcs_params1;
+        __le32  hcs_params2;
+        __le32  hcs_params3;
+        __le32  hcc_params;
+        __le32  db_off;
+        __le32  run_regs_off;
         /* Reserved up to (CAPLENGTH - 0x1C) */
 };
 
@@ -155,26 +155,26 @@ struct xhci_cap_regs {
  *                      devices.
  */
 struct xhci_op_regs {
-        u32     command;
-        u32     status;
-        u32     page_size;
-        u32     reserved1;
-        u32     reserved2;
-        u32     dev_notification;
-        u64     cmd_ring;
+        __le32  command;
+        __le32  status;
+        __le32  page_size;
+        __le32  reserved1;
+        __le32  reserved2;
+        __le32  dev_notification;
+        __le64  cmd_ring;
         /* rsvd: offset 0x20-2F */
-        u32     reserved3[4];
-        u64     dcbaa_ptr;
-        u32     config_reg;
+        __le32  reserved3[4];
+        __le64  dcbaa_ptr;
+        __le32  config_reg;
         /* rsvd: offset 0x3C-3FF */
-        u32     reserved4[241];
+        __le32  reserved4[241];
         /* port 1 registers, which serve as a base address for other ports */
-        u32     port_status_base;
-        u32     port_power_base;
-        u32     port_link_base;
-        u32     reserved5;
+        __le32  port_status_base;
+        __le32  port_power_base;
+        __le32  port_link_base;
+        __le32  reserved5;
         /* registers for ports 2-255 */
-        u32     reserved6[NUM_PORT_REGS*254];
+        __le32  reserved6[NUM_PORT_REGS*254];
 };
 
 /* USBCMD - USB command - command bitmasks */
@@ -382,12 +382,12 @@ struct xhci_op_regs {
  * updates the dequeue pointer.
  */
 struct xhci_intr_reg {
-        u32     irq_pending;
-        u32     irq_control;
-        u32     erst_size;
-        u32     rsvd;
-        u64     erst_base;
-        u64     erst_dequeue;
+        __le32  irq_pending;
+        __le32  irq_control;
+        __le32  erst_size;
+        __le32  rsvd;
+        __le64  erst_base;
+        __le64  erst_dequeue;
 };
 
 /* irq_pending bitmasks */
@@ -432,8 +432,8 @@ struct xhci_intr_reg {
  * or larger accesses"
  */
 struct xhci_run_regs {
-        u32                     microframe_index;
-        u32                     rsvd[7];
+        __le32                  microframe_index;
+        __le32                  rsvd[7];
         struct xhci_intr_reg    ir_set[128];
 };
 
@@ -447,7 +447,7 @@ struct xhci_run_regs {
  * Section 5.6
  */
 struct xhci_doorbell_array {
-        u32     doorbell[256];
+        __le32  doorbell[256];
 };
 
 #define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
@@ -504,12 +504,12 @@ struct xhci_container_ctx {
  * reserved at the end of the slot context for HC internal use.
  */
 struct xhci_slot_ctx {
-        u32     dev_info;
-        u32     dev_info2;
-        u32     tt_info;
-        u32     dev_state;
+        __le32  dev_info;
+        __le32  dev_info2;
+        __le32  tt_info;
+        __le32  dev_state;
         /* offset 0x10 to 0x1f reserved for HC internal use */
-        u32     reserved[4];
+        __le32  reserved[4];
 };
 
 /* dev_info bitmasks */
@@ -580,12 +580,12 @@ struct xhci_slot_ctx {
  * reserved at the end of the endpoint context for HC internal use.
  */
 struct xhci_ep_ctx {
-        u32     ep_info;
-        u32     ep_info2;
-        u64     deq;
-        u32     tx_info;
+        __le32  ep_info;
+        __le32  ep_info2;
+        __le64  deq;
+        __le32  tx_info;
         /* offset 0x14 - 0x1f reserved for HC internal use */
-        u32     reserved[3];
+        __le32  reserved[3];
 };
 
 /* ep_info bitmasks */
@@ -660,9 +660,9 @@ struct xhci_ep_ctx {
  * @add_context:        set the bit of the endpoint context you want to enable
  */
 struct xhci_input_control_ctx {
-        u32     drop_flags;
-        u32     add_flags;
-        u32     rsvd2[6];
+        __le32  drop_flags;
+        __le32  add_flags;
+        __le32  rsvd2[6];
 };
 
 /* Represents everything that is needed to issue a command on the command ring.
@@ -688,9 +688,9 @@ struct xhci_command {
 
 struct xhci_stream_ctx {
         /* 64-bit stream ring address, cycle state, and stream type */
-        u64     stream_ring;
+        __le64  stream_ring;
         /* offset 0x14 - 0x1f reserved for HC internal use */
-        u32     reserved[2];
+        __le32  reserved[2];
 };
 
 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
@@ -803,7 +803,7 @@ struct xhci_virt_device {
  */
 struct xhci_device_context_array {
         /* 64-bit device addresses; we only write 32-bit addresses */
-        u64                     dev_context_ptrs[MAX_HC_SLOTS];
+        __le64                  dev_context_ptrs[MAX_HC_SLOTS];
         /* private xHCD pointers */
         dma_addr_t      dma;
 };
@@ -816,10 +816,10 @@ struct xhci_device_context_array {
 
 struct xhci_transfer_event {
         /* 64-bit buffer address, or immediate data */
-        u64     buffer;
-        u32     transfer_len;
+        __le64  buffer;
+        __le32  transfer_len;
         /* This field is interpreted differently based on the type of TRB */
-        u32     flags;
+        __le32  flags;
 };
 
 /** Transfer Event bit fields **/
@@ -881,7 +881,9 @@ struct xhci_transfer_event {
 #define COMP_STOP_INVAL 27
 /* Control Abort Error - Debug Capability - control pipe aborted */
 #define COMP_DBG_ABORT  28
-/* TRB type 29 and 30 reserved */
+/* Max Exit Latency Too Large Error */
+#define COMP_MEL_ERR    29
+/* TRB type 30 reserved */
 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
 #define COMP_BUFF_OVER  31
 /* Event Lost Error - xHC has an "internal event overrun condition" */
@@ -898,9 +900,9 @@ struct xhci_transfer_event {
 
 struct xhci_link_trb {
         /* 64-bit segment pointer*/
-        u64 segment_ptr;
-        u32 intr_target;
-        u32 control;
+        __le64 segment_ptr;
+        __le32 intr_target;
+        __le32 control;
 };
 
 /* control bitfields */
@@ -909,9 +911,9 @@ struct xhci_link_trb {
 /* Command completion event TRB */
 struct xhci_event_cmd {
         /* Pointer to command TRB, or the value passed by the event data trb */
-        u64 cmd_trb;
-        u32 status;
-        u32 flags;
+        __le64 cmd_trb;
+        __le32 status;
+        __le32 flags;
 };
 
 /* flags bitmasks */
@@ -943,6 +945,8 @@ struct xhci_event_cmd {
 /* Interrupter Target - which MSI-X vector to target the completion event at */
 #define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
 #define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
+#define TRB_TBC(p)              (((p) & 0x3) << 7)
+#define TRB_TLBPC(p)            (((p) & 0xf) << 16)
 
 /* Cycle bit - indicates TRB ownership by HC or HCD */
 #define TRB_CYCLE               (1<<0)
@@ -962,15 +966,20 @@ struct xhci_event_cmd {
 /* The buffer pointer contains immediate data */
 #define TRB_IDT                 (1<<6)
 
+/* Block Event Interrupt */
+#define TRB_BEI                 (1<<9)
 
 /* Control transfer TRB specific fields */
 #define TRB_DIR_IN              (1<<16)
+#define TRB_TX_TYPE(p)          ((p) << 16)
+#define TRB_DATA_OUT            2
+#define TRB_DATA_IN             3
 
 /* Isochronous TRB specific fields */
 #define TRB_SIA                 (1<<31)
 
 struct xhci_generic_trb {
-        u32 field[4];
+        __le32 field[4];
 };
 
 union xhci_trb {
@@ -1118,10 +1127,10 @@ struct xhci_ring {
 
 struct xhci_erst_entry {
         /* 64-bit event ring segment address */
-        u64     seg_addr;
-        u32     seg_size;
+        __le64  seg_addr;
+        __le32  seg_size;
         /* Set to zero */
-        u32     rsvd;
+        __le32  rsvd;
 };
 
 struct xhci_erst {
@@ -1286,10 +1295,10 @@ struct xhci_hcd {
         /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
         u8                      *port_array;
         /* Array of pointers to USB 3.0 PORTSC registers */
-        u32 __iomem             **usb3_ports;
+        __le32 __iomem          **usb3_ports;
         unsigned int            num_usb3_ports;
         /* Array of pointers to USB 2.0 PORTSC registers */
-        u32 __iomem             **usb2_ports;
+        __le32 __iomem          **usb2_ports;
         unsigned int            num_usb2_ports;
 };
 
@@ -1322,12 +1331,12 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
 /* TODO: copied from ehci.h - can be refactored? */
 /* xHCI spec says all registers are little endian */
 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
-                __u32 __iomem *regs)
+                __le32 __iomem *regs)
 {
         return readl(regs);
 }
 static inline void xhci_writel(struct xhci_hcd *xhci,
-                const unsigned int val, __u32 __iomem *regs)
+                const unsigned int val, __le32 __iomem *regs)
 {
         xhci_dbg(xhci,
                         "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
@@ -1345,7 +1354,7 @@ static inline void xhci_writel(struct xhci_hcd *xhci,
  * the high dword, and write order is irrelevant.
  */
 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
-                __u64 __iomem *regs)
+                __le64 __iomem *regs)
 {
         __u32 __iomem *ptr = (__u32 __iomem *) regs;
         u64 val_lo = readl(ptr);
@@ -1353,7 +1362,7 @@ static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
         return val_lo + (val_hi << 32);
 }
 static inline void xhci_write_64(struct xhci_hcd *xhci,
-                const u64 val, __u64 __iomem *regs)
+                                 const u64 val, __le64 __iomem *regs)
 {
         __u32 __iomem *ptr = (__u32 __iomem *) regs;
         u32 val_lo = lower_32_bits(val);