diff options
Diffstat (limited to 'drivers/usb/host/xhci.c')
-rw-r--r-- | drivers/usb/host/xhci.c | 91 |
1 files changed, 81 insertions, 10 deletions
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 5d7d4e951ea4..45e4a3108cc3 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c | |||
@@ -577,6 +577,65 @@ static void xhci_restore_registers(struct xhci_hcd *xhci) | |||
577 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); | 577 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
578 | } | 578 | } |
579 | 579 | ||
580 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) | ||
581 | { | ||
582 | u64 val_64; | ||
583 | |||
584 | /* step 2: initialize command ring buffer */ | ||
585 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | ||
586 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | ||
587 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | ||
588 | xhci->cmd_ring->dequeue) & | ||
589 | (u64) ~CMD_RING_RSVD_BITS) | | ||
590 | xhci->cmd_ring->cycle_state; | ||
591 | xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n", | ||
592 | (long unsigned long) val_64); | ||
593 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | * The whole command ring must be cleared to zero when we suspend the host. | ||
598 | * | ||
599 | * The host doesn't save the command ring pointer in the suspend well, so we | ||
600 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | ||
601 | * aligned, because of the reserved bits in the command ring dequeue pointer | ||
602 | * register. Therefore, we can't just set the dequeue pointer back in the | ||
603 | * middle of the ring (TRBs are 16-byte aligned). | ||
604 | */ | ||
605 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | ||
606 | { | ||
607 | struct xhci_ring *ring; | ||
608 | struct xhci_segment *seg; | ||
609 | |||
610 | ring = xhci->cmd_ring; | ||
611 | seg = ring->deq_seg; | ||
612 | do { | ||
613 | memset(seg->trbs, 0, SEGMENT_SIZE); | ||
614 | seg = seg->next; | ||
615 | } while (seg != ring->deq_seg); | ||
616 | |||
617 | /* Reset the software enqueue and dequeue pointers */ | ||
618 | ring->deq_seg = ring->first_seg; | ||
619 | ring->dequeue = ring->first_seg->trbs; | ||
620 | ring->enq_seg = ring->deq_seg; | ||
621 | ring->enqueue = ring->dequeue; | ||
622 | |||
623 | /* | ||
624 | * Ring is now zeroed, so the HW should look for change of ownership | ||
625 | * when the cycle bit is set to 1. | ||
626 | */ | ||
627 | ring->cycle_state = 1; | ||
628 | |||
629 | /* | ||
630 | * Reset the hardware dequeue pointer. | ||
631 | * Yes, this will need to be re-written after resume, but we're paranoid | ||
632 | * and want to make sure the hardware doesn't access bogus memory | ||
633 | * because, say, the BIOS or an SMI started the host without changing | ||
634 | * the command ring pointers. | ||
635 | */ | ||
636 | xhci_set_cmd_ring_deq(xhci); | ||
637 | } | ||
638 | |||
580 | /* | 639 | /* |
581 | * Stop HC (not bus-specific) | 640 | * Stop HC (not bus-specific) |
582 | * | 641 | * |
@@ -604,6 +663,7 @@ int xhci_suspend(struct xhci_hcd *xhci) | |||
604 | spin_unlock_irq(&xhci->lock); | 663 | spin_unlock_irq(&xhci->lock); |
605 | return -ETIMEDOUT; | 664 | return -ETIMEDOUT; |
606 | } | 665 | } |
666 | xhci_clear_command_ring(xhci); | ||
607 | 667 | ||
608 | /* step 3: save registers */ | 668 | /* step 3: save registers */ |
609 | xhci_save_registers(xhci); | 669 | xhci_save_registers(xhci); |
@@ -635,7 +695,6 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
635 | u32 command, temp = 0; | 695 | u32 command, temp = 0; |
636 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | 696 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
637 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | 697 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
638 | u64 val_64; | ||
639 | int old_state, retval; | 698 | int old_state, retval; |
640 | 699 | ||
641 | old_state = hcd->state; | 700 | old_state = hcd->state; |
@@ -648,15 +707,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
648 | /* step 1: restore register */ | 707 | /* step 1: restore register */ |
649 | xhci_restore_registers(xhci); | 708 | xhci_restore_registers(xhci); |
650 | /* step 2: initialize command ring buffer */ | 709 | /* step 2: initialize command ring buffer */ |
651 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | 710 | xhci_set_cmd_ring_deq(xhci); |
652 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | ||
653 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | ||
654 | xhci->cmd_ring->dequeue) & | ||
655 | (u64) ~CMD_RING_RSVD_BITS) | | ||
656 | xhci->cmd_ring->cycle_state; | ||
657 | xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n", | ||
658 | (long unsigned long) val_64); | ||
659 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | ||
660 | /* step 3: restore state and start state*/ | 711 | /* step 3: restore state and start state*/ |
661 | /* step 3: set CRS flag */ | 712 | /* step 3: set CRS flag */ |
662 | command = xhci_readl(xhci, &xhci->op_regs->command); | 713 | command = xhci_readl(xhci, &xhci->op_regs->command); |
@@ -714,6 +765,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
714 | return retval; | 765 | return retval; |
715 | } | 766 | } |
716 | 767 | ||
768 | spin_unlock_irq(&xhci->lock); | ||
717 | /* Re-setup MSI-X */ | 769 | /* Re-setup MSI-X */ |
718 | if (hcd->irq) | 770 | if (hcd->irq) |
719 | free_irq(hcd->irq, hcd); | 771 | free_irq(hcd->irq, hcd); |
@@ -736,6 +788,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
736 | hcd->irq = pdev->irq; | 788 | hcd->irq = pdev->irq; |
737 | } | 789 | } |
738 | 790 | ||
791 | spin_lock_irq(&xhci->lock); | ||
739 | /* step 4: set Run/Stop bit */ | 792 | /* step 4: set Run/Stop bit */ |
740 | command = xhci_readl(xhci, &xhci->op_regs->command); | 793 | command = xhci_readl(xhci, &xhci->op_regs->command); |
741 | command |= CMD_RUN; | 794 | command |= CMD_RUN; |
@@ -1496,6 +1549,15 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |||
1496 | cmd_completion = command->completion; | 1549 | cmd_completion = command->completion; |
1497 | cmd_status = &command->status; | 1550 | cmd_status = &command->status; |
1498 | command->command_trb = xhci->cmd_ring->enqueue; | 1551 | command->command_trb = xhci->cmd_ring->enqueue; |
1552 | |||
1553 | /* Enqueue pointer can be left pointing to the link TRB, | ||
1554 | * we must handle that | ||
1555 | */ | ||
1556 | if ((command->command_trb->link.control & TRB_TYPE_BITMASK) | ||
1557 | == TRB_TYPE(TRB_LINK)) | ||
1558 | command->command_trb = | ||
1559 | xhci->cmd_ring->enq_seg->next->trbs; | ||
1560 | |||
1499 | list_add_tail(&command->cmd_list, &virt_dev->cmd_list); | 1561 | list_add_tail(&command->cmd_list, &virt_dev->cmd_list); |
1500 | } else { | 1562 | } else { |
1501 | in_ctx = virt_dev->in_ctx; | 1563 | in_ctx = virt_dev->in_ctx; |
@@ -2219,6 +2281,15 @@ int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
2219 | /* Attempt to submit the Reset Device command to the command ring */ | 2281 | /* Attempt to submit the Reset Device command to the command ring */ |
2220 | spin_lock_irqsave(&xhci->lock, flags); | 2282 | spin_lock_irqsave(&xhci->lock, flags); |
2221 | reset_device_cmd->command_trb = xhci->cmd_ring->enqueue; | 2283 | reset_device_cmd->command_trb = xhci->cmd_ring->enqueue; |
2284 | |||
2285 | /* Enqueue pointer can be left pointing to the link TRB, | ||
2286 | * we must handle that | ||
2287 | */ | ||
2288 | if ((reset_device_cmd->command_trb->link.control & TRB_TYPE_BITMASK) | ||
2289 | == TRB_TYPE(TRB_LINK)) | ||
2290 | reset_device_cmd->command_trb = | ||
2291 | xhci->cmd_ring->enq_seg->next->trbs; | ||
2292 | |||
2222 | list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list); | 2293 | list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list); |
2223 | ret = xhci_queue_reset_device(xhci, slot_id); | 2294 | ret = xhci_queue_reset_device(xhci, slot_id); |
2224 | if (ret) { | 2295 | if (ret) { |