diff options
Diffstat (limited to 'drivers/usb/host/xhci-hub.c')
-rw-r--r-- | drivers/usb/host/xhci-hub.c | 106 |
1 files changed, 51 insertions, 55 deletions
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index 805f2348eeba..9992fbfec85f 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c | |||
@@ -94,7 +94,7 @@ static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |||
94 | */ | 94 | */ |
95 | memset(port_removable, 0, sizeof(port_removable)); | 95 | memset(port_removable, 0, sizeof(port_removable)); |
96 | for (i = 0; i < ports; i++) { | 96 | for (i = 0; i < ports; i++) { |
97 | portsc = xhci_readl(xhci, xhci->usb2_ports[i]); | 97 | portsc = readl(xhci->usb2_ports[i]); |
98 | /* If a device is removable, PORTSC reports a 0, same as in the | 98 | /* If a device is removable, PORTSC reports a 0, same as in the |
99 | * hub descriptor DeviceRemovable bits. | 99 | * hub descriptor DeviceRemovable bits. |
100 | */ | 100 | */ |
@@ -148,7 +148,7 @@ static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |||
148 | port_removable = 0; | 148 | port_removable = 0; |
149 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | 149 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ |
150 | for (i = 0; i < ports; i++) { | 150 | for (i = 0; i < ports; i++) { |
151 | portsc = xhci_readl(xhci, xhci->usb3_ports[i]); | 151 | portsc = readl(xhci->usb3_ports[i]); |
152 | if (portsc & PORT_DEV_REMOVE) | 152 | if (portsc & PORT_DEV_REMOVE) |
153 | port_removable |= 1 << (i + 1); | 153 | port_removable |= 1 << (i + 1); |
154 | } | 154 | } |
@@ -342,8 +342,8 @@ static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |||
342 | } | 342 | } |
343 | 343 | ||
344 | /* Write 1 to disable the port */ | 344 | /* Write 1 to disable the port */ |
345 | xhci_writel(xhci, port_status | PORT_PE, addr); | 345 | writel(port_status | PORT_PE, addr); |
346 | port_status = xhci_readl(xhci, addr); | 346 | port_status = readl(addr); |
347 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", | 347 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", |
348 | wIndex, port_status); | 348 | wIndex, port_status); |
349 | } | 349 | } |
@@ -388,8 +388,8 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, | |||
388 | return; | 388 | return; |
389 | } | 389 | } |
390 | /* Change bits are all write 1 to clear */ | 390 | /* Change bits are all write 1 to clear */ |
391 | xhci_writel(xhci, port_status | status, addr); | 391 | writel(port_status | status, addr); |
392 | port_status = xhci_readl(xhci, addr); | 392 | port_status = readl(addr); |
393 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", | 393 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", |
394 | port_change_bit, wIndex, port_status); | 394 | port_change_bit, wIndex, port_status); |
395 | } | 395 | } |
@@ -415,11 +415,11 @@ void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |||
415 | { | 415 | { |
416 | u32 temp; | 416 | u32 temp; |
417 | 417 | ||
418 | temp = xhci_readl(xhci, port_array[port_id]); | 418 | temp = readl(port_array[port_id]); |
419 | temp = xhci_port_state_to_neutral(temp); | 419 | temp = xhci_port_state_to_neutral(temp); |
420 | temp &= ~PORT_PLS_MASK; | 420 | temp &= ~PORT_PLS_MASK; |
421 | temp |= PORT_LINK_STROBE | link_state; | 421 | temp |= PORT_LINK_STROBE | link_state; |
422 | xhci_writel(xhci, temp, port_array[port_id]); | 422 | writel(temp, port_array[port_id]); |
423 | } | 423 | } |
424 | 424 | ||
425 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, | 425 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
@@ -427,7 +427,7 @@ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, | |||
427 | { | 427 | { |
428 | u32 temp; | 428 | u32 temp; |
429 | 429 | ||
430 | temp = xhci_readl(xhci, port_array[port_id]); | 430 | temp = readl(port_array[port_id]); |
431 | temp = xhci_port_state_to_neutral(temp); | 431 | temp = xhci_port_state_to_neutral(temp); |
432 | 432 | ||
433 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | 433 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) |
@@ -445,7 +445,7 @@ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, | |||
445 | else | 445 | else |
446 | temp &= ~PORT_WKOC_E; | 446 | temp &= ~PORT_WKOC_E; |
447 | 447 | ||
448 | xhci_writel(xhci, temp, port_array[port_id]); | 448 | writel(temp, port_array[port_id]); |
449 | } | 449 | } |
450 | 450 | ||
451 | /* Test and clear port RWC bit */ | 451 | /* Test and clear port RWC bit */ |
@@ -454,11 +454,11 @@ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |||
454 | { | 454 | { |
455 | u32 temp; | 455 | u32 temp; |
456 | 456 | ||
457 | temp = xhci_readl(xhci, port_array[port_id]); | 457 | temp = readl(port_array[port_id]); |
458 | if (temp & port_bit) { | 458 | if (temp & port_bit) { |
459 | temp = xhci_port_state_to_neutral(temp); | 459 | temp = xhci_port_state_to_neutral(temp); |
460 | temp |= port_bit; | 460 | temp |= port_bit; |
461 | xhci_writel(xhci, temp, port_array[port_id]); | 461 | writel(temp, port_array[port_id]); |
462 | } | 462 | } |
463 | } | 463 | } |
464 | 464 | ||
@@ -623,8 +623,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd, | |||
623 | } | 623 | } |
624 | xhci_ring_device(xhci, slot_id); | 624 | xhci_ring_device(xhci, slot_id); |
625 | } else { | 625 | } else { |
626 | int port_status = xhci_readl(xhci, | 626 | int port_status = readl(port_array[wIndex]); |
627 | port_array[wIndex]); | ||
628 | xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", | 627 | xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", |
629 | XHCI_MAX_REXIT_TIMEOUT, | 628 | XHCI_MAX_REXIT_TIMEOUT, |
630 | port_status); | 629 | port_status); |
@@ -733,12 +732,12 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
733 | /* Set the U1 and U2 exit latencies. */ | 732 | /* Set the U1 and U2 exit latencies. */ |
734 | memcpy(buf, &usb_bos_descriptor, | 733 | memcpy(buf, &usb_bos_descriptor, |
735 | USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); | 734 | USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); |
736 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); | 735 | temp = readl(&xhci->cap_regs->hcs_params3); |
737 | buf[12] = HCS_U1_LATENCY(temp); | 736 | buf[12] = HCS_U1_LATENCY(temp); |
738 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | 737 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); |
739 | 738 | ||
740 | /* Indicate whether the host has LTM support. */ | 739 | /* Indicate whether the host has LTM support. */ |
741 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | 740 | temp = readl(&xhci->cap_regs->hcc_params); |
742 | if (HCC_LTC(temp)) | 741 | if (HCC_LTC(temp)) |
743 | buf[8] |= USB_LTM_SUPPORT; | 742 | buf[8] |= USB_LTM_SUPPORT; |
744 | 743 | ||
@@ -748,7 +747,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
748 | if (!wIndex || wIndex > max_ports) | 747 | if (!wIndex || wIndex > max_ports) |
749 | goto error; | 748 | goto error; |
750 | wIndex--; | 749 | wIndex--; |
751 | temp = xhci_readl(xhci, port_array[wIndex]); | 750 | temp = readl(port_array[wIndex]); |
752 | if (temp == 0xffffffff) { | 751 | if (temp == 0xffffffff) { |
753 | retval = -ENODEV; | 752 | retval = -ENODEV; |
754 | break; | 753 | break; |
@@ -775,7 +774,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
775 | if (!wIndex || wIndex > max_ports) | 774 | if (!wIndex || wIndex > max_ports) |
776 | goto error; | 775 | goto error; |
777 | wIndex--; | 776 | wIndex--; |
778 | temp = xhci_readl(xhci, port_array[wIndex]); | 777 | temp = readl(port_array[wIndex]); |
779 | if (temp == 0xffffffff) { | 778 | if (temp == 0xffffffff) { |
780 | retval = -ENODEV; | 779 | retval = -ENODEV; |
781 | break; | 780 | break; |
@@ -784,7 +783,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
784 | /* FIXME: What new port features do we need to support? */ | 783 | /* FIXME: What new port features do we need to support? */ |
785 | switch (wValue) { | 784 | switch (wValue) { |
786 | case USB_PORT_FEAT_SUSPEND: | 785 | case USB_PORT_FEAT_SUSPEND: |
787 | temp = xhci_readl(xhci, port_array[wIndex]); | 786 | temp = readl(port_array[wIndex]); |
788 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { | 787 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
789 | /* Resume the port to U0 first */ | 788 | /* Resume the port to U0 first */ |
790 | xhci_set_link_state(xhci, port_array, wIndex, | 789 | xhci_set_link_state(xhci, port_array, wIndex, |
@@ -797,7 +796,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
797 | * a port unless the port reports that it is in the | 796 | * a port unless the port reports that it is in the |
798 | * enabled (PED = ‘1’,PLS < ‘3’) state. | 797 | * enabled (PED = ‘1’,PLS < ‘3’) state. |
799 | */ | 798 | */ |
800 | temp = xhci_readl(xhci, port_array[wIndex]); | 799 | temp = readl(port_array[wIndex]); |
801 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) | 800 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
802 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | 801 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { |
803 | xhci_warn(xhci, "USB core suspending device " | 802 | xhci_warn(xhci, "USB core suspending device " |
@@ -822,11 +821,11 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
822 | msleep(10); /* wait device to enter */ | 821 | msleep(10); /* wait device to enter */ |
823 | spin_lock_irqsave(&xhci->lock, flags); | 822 | spin_lock_irqsave(&xhci->lock, flags); |
824 | 823 | ||
825 | temp = xhci_readl(xhci, port_array[wIndex]); | 824 | temp = readl(port_array[wIndex]); |
826 | bus_state->suspended_ports |= 1 << wIndex; | 825 | bus_state->suspended_ports |= 1 << wIndex; |
827 | break; | 826 | break; |
828 | case USB_PORT_FEAT_LINK_STATE: | 827 | case USB_PORT_FEAT_LINK_STATE: |
829 | temp = xhci_readl(xhci, port_array[wIndex]); | 828 | temp = readl(port_array[wIndex]); |
830 | 829 | ||
831 | /* Disable port */ | 830 | /* Disable port */ |
832 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | 831 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { |
@@ -839,9 +838,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
839 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | 838 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | |
840 | PORT_OCC | PORT_RC | PORT_PLC | | 839 | PORT_OCC | PORT_RC | PORT_PLC | |
841 | PORT_CEC; | 840 | PORT_CEC; |
842 | xhci_writel(xhci, temp | PORT_PE, | 841 | writel(temp | PORT_PE, port_array[wIndex]); |
843 | port_array[wIndex]); | 842 | temp = readl(port_array[wIndex]); |
844 | temp = xhci_readl(xhci, port_array[wIndex]); | ||
845 | break; | 843 | break; |
846 | } | 844 | } |
847 | 845 | ||
@@ -850,7 +848,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
850 | xhci_dbg(xhci, "Enable port %d\n", wIndex); | 848 | xhci_dbg(xhci, "Enable port %d\n", wIndex); |
851 | xhci_set_link_state(xhci, port_array, wIndex, | 849 | xhci_set_link_state(xhci, port_array, wIndex, |
852 | link_state); | 850 | link_state); |
853 | temp = xhci_readl(xhci, port_array[wIndex]); | 851 | temp = readl(port_array[wIndex]); |
854 | break; | 852 | break; |
855 | } | 853 | } |
856 | 854 | ||
@@ -884,7 +882,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
884 | msleep(20); /* wait device to enter */ | 882 | msleep(20); /* wait device to enter */ |
885 | spin_lock_irqsave(&xhci->lock, flags); | 883 | spin_lock_irqsave(&xhci->lock, flags); |
886 | 884 | ||
887 | temp = xhci_readl(xhci, port_array[wIndex]); | 885 | temp = readl(port_array[wIndex]); |
888 | if (link_state == USB_SS_PORT_LS_U3) | 886 | if (link_state == USB_SS_PORT_LS_U3) |
889 | bus_state->suspended_ports |= 1 << wIndex; | 887 | bus_state->suspended_ports |= 1 << wIndex; |
890 | break; | 888 | break; |
@@ -895,10 +893,9 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
895 | * However, khubd will ignore the roothub events until | 893 | * However, khubd will ignore the roothub events until |
896 | * the roothub is registered. | 894 | * the roothub is registered. |
897 | */ | 895 | */ |
898 | xhci_writel(xhci, temp | PORT_POWER, | 896 | writel(temp | PORT_POWER, port_array[wIndex]); |
899 | port_array[wIndex]); | ||
900 | 897 | ||
901 | temp = xhci_readl(xhci, port_array[wIndex]); | 898 | temp = readl(port_array[wIndex]); |
902 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); | 899 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); |
903 | 900 | ||
904 | spin_unlock_irqrestore(&xhci->lock, flags); | 901 | spin_unlock_irqrestore(&xhci->lock, flags); |
@@ -911,52 +908,52 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
911 | break; | 908 | break; |
912 | case USB_PORT_FEAT_RESET: | 909 | case USB_PORT_FEAT_RESET: |
913 | temp = (temp | PORT_RESET); | 910 | temp = (temp | PORT_RESET); |
914 | xhci_writel(xhci, temp, port_array[wIndex]); | 911 | writel(temp, port_array[wIndex]); |
915 | 912 | ||
916 | temp = xhci_readl(xhci, port_array[wIndex]); | 913 | temp = readl(port_array[wIndex]); |
917 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); | 914 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
918 | break; | 915 | break; |
919 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: | 916 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
920 | xhci_set_remote_wake_mask(xhci, port_array, | 917 | xhci_set_remote_wake_mask(xhci, port_array, |
921 | wIndex, wake_mask); | 918 | wIndex, wake_mask); |
922 | temp = xhci_readl(xhci, port_array[wIndex]); | 919 | temp = readl(port_array[wIndex]); |
923 | xhci_dbg(xhci, "set port remote wake mask, " | 920 | xhci_dbg(xhci, "set port remote wake mask, " |
924 | "actual port %d status = 0x%x\n", | 921 | "actual port %d status = 0x%x\n", |
925 | wIndex, temp); | 922 | wIndex, temp); |
926 | break; | 923 | break; |
927 | case USB_PORT_FEAT_BH_PORT_RESET: | 924 | case USB_PORT_FEAT_BH_PORT_RESET: |
928 | temp |= PORT_WR; | 925 | temp |= PORT_WR; |
929 | xhci_writel(xhci, temp, port_array[wIndex]); | 926 | writel(temp, port_array[wIndex]); |
930 | 927 | ||
931 | temp = xhci_readl(xhci, port_array[wIndex]); | 928 | temp = readl(port_array[wIndex]); |
932 | break; | 929 | break; |
933 | case USB_PORT_FEAT_U1_TIMEOUT: | 930 | case USB_PORT_FEAT_U1_TIMEOUT: |
934 | if (hcd->speed != HCD_USB3) | 931 | if (hcd->speed != HCD_USB3) |
935 | goto error; | 932 | goto error; |
936 | temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC); | 933 | temp = readl(port_array[wIndex] + PORTPMSC); |
937 | temp &= ~PORT_U1_TIMEOUT_MASK; | 934 | temp &= ~PORT_U1_TIMEOUT_MASK; |
938 | temp |= PORT_U1_TIMEOUT(timeout); | 935 | temp |= PORT_U1_TIMEOUT(timeout); |
939 | xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); | 936 | writel(temp, port_array[wIndex] + PORTPMSC); |
940 | break; | 937 | break; |
941 | case USB_PORT_FEAT_U2_TIMEOUT: | 938 | case USB_PORT_FEAT_U2_TIMEOUT: |
942 | if (hcd->speed != HCD_USB3) | 939 | if (hcd->speed != HCD_USB3) |
943 | goto error; | 940 | goto error; |
944 | temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC); | 941 | temp = readl(port_array[wIndex] + PORTPMSC); |
945 | temp &= ~PORT_U2_TIMEOUT_MASK; | 942 | temp &= ~PORT_U2_TIMEOUT_MASK; |
946 | temp |= PORT_U2_TIMEOUT(timeout); | 943 | temp |= PORT_U2_TIMEOUT(timeout); |
947 | xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); | 944 | writel(temp, port_array[wIndex] + PORTPMSC); |
948 | break; | 945 | break; |
949 | default: | 946 | default: |
950 | goto error; | 947 | goto error; |
951 | } | 948 | } |
952 | /* unblock any posted writes */ | 949 | /* unblock any posted writes */ |
953 | temp = xhci_readl(xhci, port_array[wIndex]); | 950 | temp = readl(port_array[wIndex]); |
954 | break; | 951 | break; |
955 | case ClearPortFeature: | 952 | case ClearPortFeature: |
956 | if (!wIndex || wIndex > max_ports) | 953 | if (!wIndex || wIndex > max_ports) |
957 | goto error; | 954 | goto error; |
958 | wIndex--; | 955 | wIndex--; |
959 | temp = xhci_readl(xhci, port_array[wIndex]); | 956 | temp = readl(port_array[wIndex]); |
960 | if (temp == 0xffffffff) { | 957 | if (temp == 0xffffffff) { |
961 | retval = -ENODEV; | 958 | retval = -ENODEV; |
962 | break; | 959 | break; |
@@ -965,7 +962,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
965 | temp = xhci_port_state_to_neutral(temp); | 962 | temp = xhci_port_state_to_neutral(temp); |
966 | switch (wValue) { | 963 | switch (wValue) { |
967 | case USB_PORT_FEAT_SUSPEND: | 964 | case USB_PORT_FEAT_SUSPEND: |
968 | temp = xhci_readl(xhci, port_array[wIndex]); | 965 | temp = readl(port_array[wIndex]); |
969 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); | 966 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
970 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | 967 | xhci_dbg(xhci, "PORTSC %04x\n", temp); |
971 | if (temp & PORT_RESET) | 968 | if (temp & PORT_RESET) |
@@ -1008,8 +1005,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
1008 | port_array[wIndex], temp); | 1005 | port_array[wIndex], temp); |
1009 | break; | 1006 | break; |
1010 | case USB_PORT_FEAT_POWER: | 1007 | case USB_PORT_FEAT_POWER: |
1011 | xhci_writel(xhci, temp & ~PORT_POWER, | 1008 | writel(temp & ~PORT_POWER, port_array[wIndex]); |
1012 | port_array[wIndex]); | ||
1013 | 1009 | ||
1014 | spin_unlock_irqrestore(&xhci->lock, flags); | 1010 | spin_unlock_irqrestore(&xhci->lock, flags); |
1015 | temp = usb_acpi_power_manageable(hcd->self.root_hub, | 1011 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
@@ -1070,7 +1066,7 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |||
1070 | spin_lock_irqsave(&xhci->lock, flags); | 1066 | spin_lock_irqsave(&xhci->lock, flags); |
1071 | /* For each port, did anything change? If so, set that bit in buf. */ | 1067 | /* For each port, did anything change? If so, set that bit in buf. */ |
1072 | for (i = 0; i < max_ports; i++) { | 1068 | for (i = 0; i < max_ports; i++) { |
1073 | temp = xhci_readl(xhci, port_array[i]); | 1069 | temp = readl(port_array[i]); |
1074 | if (temp == 0xffffffff) { | 1070 | if (temp == 0xffffffff) { |
1075 | retval = -ENODEV; | 1071 | retval = -ENODEV; |
1076 | break; | 1072 | break; |
@@ -1124,7 +1120,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd) | |||
1124 | u32 t1, t2; | 1120 | u32 t1, t2; |
1125 | int slot_id; | 1121 | int slot_id; |
1126 | 1122 | ||
1127 | t1 = xhci_readl(xhci, port_array[port_index]); | 1123 | t1 = readl(port_array[port_index]); |
1128 | t2 = xhci_port_state_to_neutral(t1); | 1124 | t2 = xhci_port_state_to_neutral(t1); |
1129 | 1125 | ||
1130 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { | 1126 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { |
@@ -1157,7 +1153,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd) | |||
1157 | 1153 | ||
1158 | t1 = xhci_port_state_to_neutral(t1); | 1154 | t1 = xhci_port_state_to_neutral(t1); |
1159 | if (t1 != t2) | 1155 | if (t1 != t2) |
1160 | xhci_writel(xhci, t2, port_array[port_index]); | 1156 | writel(t2, port_array[port_index]); |
1161 | } | 1157 | } |
1162 | hcd->state = HC_STATE_SUSPENDED; | 1158 | hcd->state = HC_STATE_SUSPENDED; |
1163 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); | 1159 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
@@ -1187,9 +1183,9 @@ int xhci_bus_resume(struct usb_hcd *hcd) | |||
1187 | } | 1183 | } |
1188 | 1184 | ||
1189 | /* delay the irqs */ | 1185 | /* delay the irqs */ |
1190 | temp = xhci_readl(xhci, &xhci->op_regs->command); | 1186 | temp = readl(&xhci->op_regs->command); |
1191 | temp &= ~CMD_EIE; | 1187 | temp &= ~CMD_EIE; |
1192 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 1188 | writel(temp, &xhci->op_regs->command); |
1193 | 1189 | ||
1194 | port_index = max_ports; | 1190 | port_index = max_ports; |
1195 | while (port_index--) { | 1191 | while (port_index--) { |
@@ -1198,7 +1194,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) | |||
1198 | u32 temp; | 1194 | u32 temp; |
1199 | int slot_id; | 1195 | int slot_id; |
1200 | 1196 | ||
1201 | temp = xhci_readl(xhci, port_array[port_index]); | 1197 | temp = readl(port_array[port_index]); |
1202 | if (DEV_SUPERSPEED(temp)) | 1198 | if (DEV_SUPERSPEED(temp)) |
1203 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | 1199 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); |
1204 | else | 1200 | else |
@@ -1235,17 +1231,17 @@ int xhci_bus_resume(struct usb_hcd *hcd) | |||
1235 | if (slot_id) | 1231 | if (slot_id) |
1236 | xhci_ring_device(xhci, slot_id); | 1232 | xhci_ring_device(xhci, slot_id); |
1237 | } else | 1233 | } else |
1238 | xhci_writel(xhci, temp, port_array[port_index]); | 1234 | writel(temp, port_array[port_index]); |
1239 | } | 1235 | } |
1240 | 1236 | ||
1241 | (void) xhci_readl(xhci, &xhci->op_regs->command); | 1237 | (void) readl(&xhci->op_regs->command); |
1242 | 1238 | ||
1243 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); | 1239 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
1244 | /* re-enable irqs */ | 1240 | /* re-enable irqs */ |
1245 | temp = xhci_readl(xhci, &xhci->op_regs->command); | 1241 | temp = readl(&xhci->op_regs->command); |
1246 | temp |= CMD_EIE; | 1242 | temp |= CMD_EIE; |
1247 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 1243 | writel(temp, &xhci->op_regs->command); |
1248 | temp = xhci_readl(xhci, &xhci->op_regs->command); | 1244 | temp = readl(&xhci->op_regs->command); |
1249 | 1245 | ||
1250 | spin_unlock_irqrestore(&xhci->lock, flags); | 1246 | spin_unlock_irqrestore(&xhci->lock, flags); |
1251 | return 0; | 1247 | return 0; |