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path: root/drivers/usb/host/pci-quirks.c
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Diffstat (limited to 'drivers/usb/host/pci-quirks.c')
-rw-r--r--drivers/usb/host/pci-quirks.c260
1 files changed, 0 insertions, 260 deletions
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 344b25a790e1..4c502c890ebd 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -52,266 +52,6 @@
52#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 52#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
53#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 53#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
54 54
55/* AMD quirk use */
56#define AB_REG_BAR_LOW 0xe0
57#define AB_REG_BAR_HIGH 0xe1
58#define AB_REG_BAR_SB700 0xf0
59#define AB_INDX(addr) ((addr) + 0x00)
60#define AB_DATA(addr) ((addr) + 0x04)
61#define AX_INDXC 0x30
62#define AX_DATAC 0x34
63
64#define NB_PCIE_INDX_ADDR 0xe0
65#define NB_PCIE_INDX_DATA 0xe4
66#define PCIE_P_CNTL 0x10040
67#define BIF_NB 0x10002
68#define NB_PIF0_PWRDOWN_0 0x01100012
69#define NB_PIF0_PWRDOWN_1 0x01100013
70
71static struct amd_chipset_info {
72 struct pci_dev *nb_dev;
73 struct pci_dev *smbus_dev;
74 int nb_type;
75 int sb_type;
76 int isoc_reqs;
77 int probe_count;
78 int probe_result;
79} amd_chipset;
80
81static DEFINE_SPINLOCK(amd_lock);
82
83int usb_amd_find_chipset_info(void)
84{
85 u8 rev = 0;
86 unsigned long flags;
87
88 spin_lock_irqsave(&amd_lock, flags);
89
90 amd_chipset.probe_count++;
91 /* probe only once */
92 if (amd_chipset.probe_count > 1) {
93 spin_unlock_irqrestore(&amd_lock, flags);
94 return amd_chipset.probe_result;
95 }
96
97 amd_chipset.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
98 if (amd_chipset.smbus_dev) {
99 pci_read_config_byte(amd_chipset.smbus_dev,
100 PCI_REVISION_ID, &rev);
101 if (rev >= 0x40)
102 amd_chipset.sb_type = 1;
103 else if (rev >= 0x30 && rev <= 0x3b)
104 amd_chipset.sb_type = 3;
105 } else {
106 amd_chipset.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
107 0x780b, NULL);
108 if (!amd_chipset.smbus_dev) {
109 spin_unlock_irqrestore(&amd_lock, flags);
110 return 0;
111 }
112 pci_read_config_byte(amd_chipset.smbus_dev,
113 PCI_REVISION_ID, &rev);
114 if (rev >= 0x11 && rev <= 0x18)
115 amd_chipset.sb_type = 2;
116 }
117
118 if (amd_chipset.sb_type == 0) {
119 if (amd_chipset.smbus_dev) {
120 pci_dev_put(amd_chipset.smbus_dev);
121 amd_chipset.smbus_dev = NULL;
122 }
123 spin_unlock_irqrestore(&amd_lock, flags);
124 return 0;
125 }
126
127 amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
128 if (amd_chipset.nb_dev) {
129 amd_chipset.nb_type = 1;
130 } else {
131 amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
132 0x1510, NULL);
133 if (amd_chipset.nb_dev) {
134 amd_chipset.nb_type = 2;
135 } else {
136 amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
137 0x9600, NULL);
138 if (amd_chipset.nb_dev)
139 amd_chipset.nb_type = 3;
140 }
141 }
142
143 amd_chipset.probe_result = 1;
144 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
145
146 spin_unlock_irqrestore(&amd_lock, flags);
147 return amd_chipset.probe_result;
148}
149EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
150
151/*
152 * The hardware normally enables the A-link power management feature, which
153 * lets the system lower the power consumption in idle states.
154 *
155 * This USB quirk prevents the link going into that lower power state
156 * during isochronous transfers.
157 *
158 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
159 * some AMD platforms may stutter or have breaks occasionally.
160 */
161static void usb_amd_quirk_pll(int disable)
162{
163 u32 addr, addr_low, addr_high, val;
164 u32 bit = disable ? 0 : 1;
165 unsigned long flags;
166
167 spin_lock_irqsave(&amd_lock, flags);
168
169 if (disable) {
170 amd_chipset.isoc_reqs++;
171 if (amd_chipset.isoc_reqs > 1) {
172 spin_unlock_irqrestore(&amd_lock, flags);
173 return;
174 }
175 } else {
176 amd_chipset.isoc_reqs--;
177 if (amd_chipset.isoc_reqs > 0) {
178 spin_unlock_irqrestore(&amd_lock, flags);
179 return;
180 }
181 }
182
183 if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
184 outb_p(AB_REG_BAR_LOW, 0xcd6);
185 addr_low = inb_p(0xcd7);
186 outb_p(AB_REG_BAR_HIGH, 0xcd6);
187 addr_high = inb_p(0xcd7);
188 addr = addr_high << 8 | addr_low;
189
190 outl_p(0x30, AB_INDX(addr));
191 outl_p(0x40, AB_DATA(addr));
192 outl_p(0x34, AB_INDX(addr));
193 val = inl_p(AB_DATA(addr));
194 } else if (amd_chipset.sb_type == 3) {
195 pci_read_config_dword(amd_chipset.smbus_dev,
196 AB_REG_BAR_SB700, &addr);
197 outl(AX_INDXC, AB_INDX(addr));
198 outl(0x40, AB_DATA(addr));
199 outl(AX_DATAC, AB_INDX(addr));
200 val = inl(AB_DATA(addr));
201 } else {
202 spin_unlock_irqrestore(&amd_lock, flags);
203 return;
204 }
205
206 if (disable) {
207 val &= ~0x08;
208 val |= (1 << 4) | (1 << 9);
209 } else {
210 val |= 0x08;
211 val &= ~((1 << 4) | (1 << 9));
212 }
213 outl_p(val, AB_DATA(addr));
214
215 if (!amd_chipset.nb_dev) {
216 spin_unlock_irqrestore(&amd_lock, flags);
217 return;
218 }
219
220 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
221 addr = PCIE_P_CNTL;
222 pci_write_config_dword(amd_chipset.nb_dev,
223 NB_PCIE_INDX_ADDR, addr);
224 pci_read_config_dword(amd_chipset.nb_dev,
225 NB_PCIE_INDX_DATA, &val);
226
227 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
228 val |= bit | (bit << 3) | (bit << 12);
229 val |= ((!bit) << 4) | ((!bit) << 9);
230 pci_write_config_dword(amd_chipset.nb_dev,
231 NB_PCIE_INDX_DATA, val);
232
233 addr = BIF_NB;
234 pci_write_config_dword(amd_chipset.nb_dev,
235 NB_PCIE_INDX_ADDR, addr);
236 pci_read_config_dword(amd_chipset.nb_dev,
237 NB_PCIE_INDX_DATA, &val);
238 val &= ~(1 << 8);
239 val |= bit << 8;
240
241 pci_write_config_dword(amd_chipset.nb_dev,
242 NB_PCIE_INDX_DATA, val);
243 } else if (amd_chipset.nb_type == 2) {
244 addr = NB_PIF0_PWRDOWN_0;
245 pci_write_config_dword(amd_chipset.nb_dev,
246 NB_PCIE_INDX_ADDR, addr);
247 pci_read_config_dword(amd_chipset.nb_dev,
248 NB_PCIE_INDX_DATA, &val);
249 if (disable)
250 val &= ~(0x3f << 7);
251 else
252 val |= 0x3f << 7;
253
254 pci_write_config_dword(amd_chipset.nb_dev,
255 NB_PCIE_INDX_DATA, val);
256
257 addr = NB_PIF0_PWRDOWN_1;
258 pci_write_config_dword(amd_chipset.nb_dev,
259 NB_PCIE_INDX_ADDR, addr);
260 pci_read_config_dword(amd_chipset.nb_dev,
261 NB_PCIE_INDX_DATA, &val);
262 if (disable)
263 val &= ~(0x3f << 7);
264 else
265 val |= 0x3f << 7;
266
267 pci_write_config_dword(amd_chipset.nb_dev,
268 NB_PCIE_INDX_DATA, val);
269 }
270
271 spin_unlock_irqrestore(&amd_lock, flags);
272 return;
273}
274
275void usb_amd_quirk_pll_disable(void)
276{
277 usb_amd_quirk_pll(1);
278}
279EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
280
281void usb_amd_quirk_pll_enable(void)
282{
283 usb_amd_quirk_pll(0);
284}
285EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
286
287void usb_amd_dev_put(void)
288{
289 unsigned long flags;
290
291 spin_lock_irqsave(&amd_lock, flags);
292
293 amd_chipset.probe_count--;
294 if (amd_chipset.probe_count > 0) {
295 spin_unlock_irqrestore(&amd_lock, flags);
296 return;
297 }
298
299 if (amd_chipset.nb_dev) {
300 pci_dev_put(amd_chipset.nb_dev);
301 amd_chipset.nb_dev = NULL;
302 }
303 if (amd_chipset.smbus_dev) {
304 pci_dev_put(amd_chipset.smbus_dev);
305 amd_chipset.smbus_dev = NULL;
306 }
307 amd_chipset.nb_type = 0;
308 amd_chipset.sb_type = 0;
309 amd_chipset.isoc_reqs = 0;
310 amd_chipset.probe_result = 0;
311
312 spin_unlock_irqrestore(&amd_lock, flags);
313}
314EXPORT_SYMBOL_GPL(usb_amd_dev_put);
315 55
316/* 56/*
317 * Make sure the controller is completely inactive, unable to 57 * Make sure the controller is completely inactive, unable to
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 22:52:12 -0400