1 files changed, 583 insertions, 0 deletions
diff --git a/drivers/usb/host/isp116x.h b/drivers/usb/host/isp116x.h
new file mode 100644
index 000000000000..58873470dcf5
--- /dev/null
+++ b/drivers/usb/host/isp116x.h
@@ -0,0 +1,583 @@
+/*
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ */
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT         850
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED     832
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED      64
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED     1
+#define BYTE_TIME_LOWSPEED      20
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE        4096
+#define ISP116x_ITL_BUFSIZE     0
+#define ISP116x_ATL_BUFSIZE     ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+#define ISP116x_WRITE_OFFSET    0x80
+/*------------ ISP116x registers/bits ------------*/
+#define HCREVISION      0x00
+#define HCCONTROL       0x01
+#define         HCCONTROL_HCFS  (3 << 6)        /* host controller
+                                                   functional state */
+#define         HCCONTROL_USB_RESET     (0 << 6)
+#define         HCCONTROL_USB_RESUME    (1 << 6)
+#define         HCCONTROL_USB_OPER      (2 << 6)
+#define         HCCONTROL_USB_SUSPEND   (3 << 6)
+#define         HCCONTROL_RWC   (1 << 9)        /* remote wakeup connected */
+#define         HCCONTROL_RWE   (1 << 10)       /* remote wakeup enable */
+#define HCCMDSTAT       0x02
+#define         HCCMDSTAT_HCR   (1 << 0)        /* host controller reset */
+#define         HCCMDSTAT_SOC   (3 << 16)       /* scheduling overrun count */
+#define HCINTSTAT       0x03
+#define         HCINT_SO        (1 << 0)        /* scheduling overrun */
+#define         HCINT_WDH       (1 << 1)        /* writeback of done_head */
+#define         HCINT_SF        (1 << 2)        /* start frame */
+#define         HCINT_RD        (1 << 3)        /* resume detect */
+#define         HCINT_UE        (1 << 4)        /* unrecoverable error */
+#define         HCINT_FNO       (1 << 5)        /* frame number overflow */
+#define         HCINT_RHSC      (1 << 6)        /* root hub status change */
+#define         HCINT_OC        (1 << 30)       /* ownership change */
+#define         HCINT_MIE       (1 << 31)       /* master interrupt enable */
+#define HCINTENB        0x04
+#define HCINTDIS        0x05
+#define HCFMINTVL       0x0d
+#define HCFMREM         0x0e
+#define HCFMNUM         0x0f
+#define HCLSTHRESH      0x11
+#define HCRHDESCA       0x12
+#define         RH_A_NDP        (0x3 << 0)      /* # downstream ports */
+#define         RH_A_PSM        (1 << 8)        /* power switching mode */
+#define         RH_A_NPS        (1 << 9)        /* no power switching */
+#define         RH_A_DT         (1 << 10)       /* device type (mbz) */
+#define         RH_A_OCPM       (1 << 11)       /* overcurrent protection
+                                                   mode */
+#define         RH_A_NOCP       (1 << 12)       /* no overcurrent protection */
+#define         RH_A_POTPGT     (0xff << 24)    /* power on -> power good
+                                                   time */
+#define HCRHDESCB       0x13
+#define         RH_B_DR         (0xffff << 0)   /* device removable flags */
+#define         RH_B_PPCM       (0xffff << 16)  /* port power control mask */
+#define HCRHSTATUS      0x14
+#define         RH_HS_LPS       (1 << 0)        /* local power status */
+#define         RH_HS_OCI       (1 << 1)        /* over current indicator */
+#define         RH_HS_DRWE      (1 << 15)       /* device remote wakeup
+                                                   enable */
+#define         RH_HS_LPSC      (1 << 16)       /* local power status change */
+#define         RH_HS_OCIC      (1 << 17)       /* over current indicator
+                                                   change */
+#define         RH_HS_CRWE      (1 << 31)       /* clear remote wakeup
+                                                   enable */
+#define HCRHPORT1       0x15
+#define         RH_PS_CCS       (1 << 0)        /* current connect status */
+#define         RH_PS_PES       (1 << 1)        /* port enable status */
+#define         RH_PS_PSS       (1 << 2)        /* port suspend status */
+#define         RH_PS_POCI      (1 << 3)        /* port over current
+                                                   indicator */
+#define         RH_PS_PRS       (1 << 4)        /* port reset status */
+#define         RH_PS_PPS       (1 << 8)        /* port power status */
+#define         RH_PS_LSDA      (1 << 9)        /* low speed device attached */
+#define         RH_PS_CSC       (1 << 16)       /* connect status change */
+#define         RH_PS_PESC      (1 << 17)       /* port enable status change */
+#define         RH_PS_PSSC      (1 << 18)       /* port suspend status
+                                                   change */
+#define         RH_PS_OCIC      (1 << 19)       /* over current indicator
+                                                   change */
+#define         RH_PS_PRSC      (1 << 20)       /* port reset status change */
+#define         HCRHPORT_CLRMASK        (0x1f << 16)
+#define HCRHPORT2       0x16
+#define HCHWCFG         0x20
+#define         HCHWCFG_15KRSEL         (1 << 12)
+#define         HCHWCFG_CLKNOTSTOP      (1 << 11)
+#define         HCHWCFG_ANALOG_OC       (1 << 10)
+#define         HCHWCFG_DACK_MODE       (1 << 8)
+#define         HCHWCFG_EOT_POL         (1 << 7)
+#define         HCHWCFG_DACK_POL        (1 << 6)
+#define         HCHWCFG_DREQ_POL        (1 << 5)
+#define         HCHWCFG_DBWIDTH_MASK    (0x03 << 3)
+#define         HCHWCFG_DBWIDTH(n)      (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define         HCHWCFG_INT_POL         (1 << 2)
+#define         HCHWCFG_INT_TRIGGER     (1 << 1)
+#define         HCHWCFG_INT_ENABLE      (1 << 0)
+#define HCDMACFG        0x21
+#define         HCDMACFG_BURST_LEN_MASK (0x03 << 5)
+#define         HCDMACFG_BURST_LEN(n)   (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define         HCDMACFG_BURST_LEN_1    HCDMACFG_BURST_LEN(0)
+#define         HCDMACFG_BURST_LEN_4    HCDMACFG_BURST_LEN(1)
+#define         HCDMACFG_BURST_LEN_8    HCDMACFG_BURST_LEN(2)
+#define         HCDMACFG_DMA_ENABLE     (1 << 4)
+#define         HCDMACFG_BUF_TYPE_MASK  (0x07 << 1)
+#define         HCDMACFG_CTR_SEL        (1 << 2)
+#define         HCDMACFG_ITLATL_SEL     (1 << 1)
+#define         HCDMACFG_DMA_RW_SELECT  (1 << 0)
+#define HCXFERCTR       0x22
+#define HCuPINT         0x24
+#define         HCuPINT_SOF             (1 << 0)
+#define         HCuPINT_ATL             (1 << 1)
+#define         HCuPINT_AIIEOT          (1 << 2)
+#define         HCuPINT_OPR             (1 << 4)
+#define         HCuPINT_SUSP            (1 << 5)
+#define         HCuPINT_CLKRDY          (1 << 6)
+#define HCuPINTENB      0x25
+#define HCCHIPID        0x27
+#define         HCCHIPID_MASK           0xff00
+#define         HCCHIPID_MAGIC          0x6100
+#define HCSCRATCH       0x28
+#define HCSWRES         0x29
+#define         HCSWRES_MAGIC           0x00f6
+#define HCITLBUFLEN     0x2a
+#define HCATLBUFLEN     0x2b
+#define HCBUFSTAT       0x2c
+#define         HCBUFSTAT_ITL0_FULL     (1 << 0)
+#define         HCBUFSTAT_ITL1_FULL     (1 << 1)
+#define         HCBUFSTAT_ATL_FULL      (1 << 2)
+#define         HCBUFSTAT_ITL0_DONE     (1 << 3)
+#define         HCBUFSTAT_ITL1_DONE     (1 << 4)
+#define         HCBUFSTAT_ATL_DONE      (1 << 5)
+#define HCRDITL0LEN     0x2d
+#define HCRDITL1LEN     0x2e
+#define HCITLPORT       0x40
+#define HCATLPORT       0x41
+/* Philips transfer descriptor */
+struct ptd {
+        u16 count;
+#define PTD_COUNT_MSK   (0x3ff << 0)
+#define PTD_TOGGLE_MSK  (1 << 10)
+#define PTD_ACTIVE_MSK  (1 << 11)
+#define PTD_CC_MSK      (0xf << 12)
+        u16 mps;
+#define PTD_MPS_MSK     (0x3ff << 0)
+#define PTD_SPD_MSK     (1 << 10)
+#define PTD_LAST_MSK    (1 << 11)
+#define PTD_EP_MSK      (0xf << 12)
+        u16 len;
+#define PTD_LEN_MSK     (0x3ff << 0)
+#define PTD_DIR_MSK     (3 << 10)
+#define PTD_DIR_SETUP   (0)
+#define PTD_DIR_OUT     (1)
+#define PTD_DIR_IN      (2)
+#define PTD_B5_5_MSK    (1 << 13)
+        u16 faddr;
+#define PTD_FA_MSK      (0x7f << 0)
+#define PTD_FMT_MSK     (1 << 7)
+} __attribute__ ((packed, aligned(2)));
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)        (((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)            (((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)       (((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)           (((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)       (((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)           (((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)           (((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)               (((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)          (((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)              (((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)          (((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)              (((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)         (((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)             (((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)           (((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)               (((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)          (((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)              (((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)          (((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)              (((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)         (((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)             (((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)           (((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)               (((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)          (((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)              (((v) << 7) & PTD_FMT_MSK)
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+/* map PTD status codes (CC) to errno values */
+static const int cc_to_error[16] = {
+        /* No  Error  */ 0,
+        /* CRC Error  */ -EILSEQ,
+        /* Bit Stuff  */ -EPROTO,
+        /* Data Togg  */ -EILSEQ,
+        /* Stall      */ -EPIPE,
+        /* DevNotResp */ -ETIMEDOUT,
+        /* PIDCheck   */ -EPROTO,
+        /* UnExpPID   */ -EPROTO,
+        /* DataOver   */ -EOVERFLOW,
+        /* DataUnder  */ -EREMOTEIO,
+        /* (for hw)   */ -EIO,
+        /* (for hw)   */ -EIO,
+        /* BufferOver */ -ECOMM,
+        /* BuffUnder  */ -ENOSR,
+        /* (for HCD)  */ -EALREADY,
+        /* (for HCD)  */ -EALREADY
+};
+/*--------------------------------------------------------------*/
+#define LOG2_PERIODIC_SIZE      5       /* arbitrary; this matches OHCI */
+#define PERIODIC_SIZE           (1 << LOG2_PERIODIC_SIZE)
+struct isp116x {
+        spinlock_t lock;
+        struct work_struct rh_resume;
+        void __iomem *addr_reg;
+        void __iomem *data_reg;
+        struct isp116x_platform_data *board;
+        struct proc_dir_entry *pde;
+        unsigned long stat1, stat2, stat4, stat8, stat16;
+        /* HC registers */
+        u32 intenb;             /* "OHCI" interrupts */
+        u16 irqenb;             /* uP interrupts */
+        /* Root hub registers */
+        u32 rhdesca;
+        u32 rhdescb;
+        u32 rhstatus;
+        u32 rhport[2];
+        /* async schedule: control, bulk */
+        struct list_head async;
+        /* periodic schedule: int */
+        u16 load[PERIODIC_SIZE];
+        struct isp116x_ep *periodic[PERIODIC_SIZE];
+        unsigned periodic_count;
+        u16 fmindex;
+        /* Schedule for the current frame */
+        struct isp116x_ep *atl_active;
+        int atl_buflen;
+        int atl_bufshrt;
+        int atl_last_dir;
+        atomic_t atl_finishing;
+};
+static inline struct isp116x *hcd_to_isp116x(struct usb_hcd *hcd)
+{
+        return (struct isp116x *)(hcd->hcd_priv);
+}
+static inline struct usb_hcd *isp116x_to_hcd(struct isp116x *isp116x)
+{
+        return container_of((void *)isp116x, struct usb_hcd, hcd_priv);
+}
+struct isp116x_ep {
+        struct usb_host_endpoint *hep;
+        struct usb_device *udev;
+        struct ptd ptd;
+        u8 maxpacket;
+        u8 epnum;
+        u8 nextpid;
+        u16 error_count;
+        u16 length;             /* of current packet */
+        unsigned char *data;    /* to databuf */
+        /* queue of active EP's (the ones scheduled for the
+           current frame) */
+        struct isp116x_ep *active;
+        /* periodic schedule */
+        u16 period;
+        u16 branch;
+        u16 load;
+        struct isp116x_ep *next;
+        /* async schedule */
+        struct list_head schedule;
+};
+/*-------------------------------------------------------------------------*/
+#ifdef DEBUG
+#define DBG(stuff...)           printk(KERN_DEBUG "116x: " stuff)
+#else
+#define DBG(stuff...)           do{}while(0)
+#endif
+#ifdef VERBOSE
+#    define VDBG                DBG
+#else
+#    define VDBG(stuff...)      do{}while(0)
+#endif
+#define ERR(stuff...)           printk(KERN_ERR "116x: " stuff)
+#define WARN(stuff...)          printk(KERN_WARNING "116x: " stuff)
+#define INFO(stuff...)          printk(KERN_INFO "116x: " stuff)
+/* ------------------------------------------------- */
+#if defined(USE_PLATFORM_DELAY)
+#if defined(USE_NDELAY)
+#error USE_PLATFORM_DELAY and USE_NDELAY simultaneously defined.
+#endif
+#define isp116x_delay(h,d)      (h)->board->delay(      \
+                                isp116x_to_hcd(h)->self.controller,d)
+#define isp116x_check_platform_delay(h) ((h)->board->delay == NULL)
+#elif defined(USE_NDELAY)
+#define isp116x_delay(h,d)      ndelay(d)
+#define isp116x_check_platform_delay(h) 0
+#else
+#define isp116x_delay(h,d)      do{}while(0)
+#define isp116x_check_platform_delay(h) 0
+#endif
+#if defined(DEBUG)
+#define IRQ_TEST()      BUG_ON(!irqs_disabled())
+#else
+#define IRQ_TEST()      do{}while(0)
+#endif
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+        IRQ_TEST();
+        writew(reg & 0xff, isp116x->addr_reg);
+        isp116x_delay(isp116x, 300);
+}
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+        writew(val, isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+}
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+        __raw_writew(val, isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+}
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+        u16 val;
+        val = readw(isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+        return val;
+}
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+        u16 val;
+        val = __raw_readw(isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+        return val;
+}
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+        writew(val & 0xffff, isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+        writew(val >> 16, isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+}
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+        u32 val;
+        val = (u32) readw(isp116x->data_reg);
+        isp116x_delay(isp116x, 150);
+        val |= ((u32) readw(isp116x->data_reg)) << 16;
+        isp116x_delay(isp116x, 150);
+        return val;
+}
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+        isp116x_write_addr(isp116x, reg);
+        return isp116x_read_data16(isp116x);
+}
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+        isp116x_write_addr(isp116x, reg);
+        return isp116x_read_data32(isp116x);
+}
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+                                unsigned val)
+{
+        isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+        isp116x_write_data16(isp116x, (u16) (val & 0xffff));
+}
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+                                unsigned val)
+{
+        isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+        isp116x_write_data32(isp116x, (u32) val);
+}
+#define isp116x_show_reg(d,r) {                                 \
+        if ((r) < 0x20) {                                       \
+                DBG("%-12s[%02x]: %08x\n", #r,                  \
+                        r, isp116x_read_reg32(d, r));           \
+        } else {                                                \
+                DBG("%-12s[%02x]:     %04x\n", #r,              \
+                        r, isp116x_read_reg16(d, r));           \
+        }                                                       \
+}
+static inline void isp116x_show_regs(struct isp116x *isp116x)
+{
+        isp116x_show_reg(isp116x, HCREVISION);
+        isp116x_show_reg(isp116x, HCCONTROL);
+        isp116x_show_reg(isp116x, HCCMDSTAT);
+        isp116x_show_reg(isp116x, HCINTSTAT);
+        isp116x_show_reg(isp116x, HCINTENB);
+        isp116x_show_reg(isp116x, HCFMINTVL);
+        isp116x_show_reg(isp116x, HCFMREM);
+        isp116x_show_reg(isp116x, HCFMNUM);
+        isp116x_show_reg(isp116x, HCLSTHRESH);
+        isp116x_show_reg(isp116x, HCRHDESCA);
+        isp116x_show_reg(isp116x, HCRHDESCB);
+        isp116x_show_reg(isp116x, HCRHSTATUS);
+        isp116x_show_reg(isp116x, HCRHPORT1);
+        isp116x_show_reg(isp116x, HCRHPORT2);
+        isp116x_show_reg(isp116x, HCHWCFG);
+        isp116x_show_reg(isp116x, HCDMACFG);
+        isp116x_show_reg(isp116x, HCXFERCTR);
+        isp116x_show_reg(isp116x, HCuPINT);
+        isp116x_show_reg(isp116x, HCuPINTENB);
+        isp116x_show_reg(isp116x, HCCHIPID);
+        isp116x_show_reg(isp116x, HCSCRATCH);
+        isp116x_show_reg(isp116x, HCITLBUFLEN);
+        isp116x_show_reg(isp116x, HCATLBUFLEN);
+        isp116x_show_reg(isp116x, HCBUFSTAT);
+        isp116x_show_reg(isp116x, HCRDITL0LEN);
+        isp116x_show_reg(isp116x, HCRDITL1LEN);
+}
+#if defined(URB_TRACE)
+#define PIPETYPE(pipe)  ({ char *__s;                   \
+        if (usb_pipecontrol(pipe))      __s = "ctrl";   \
+        else if (usb_pipeint(pipe))     __s = "int";    \
+        else if (usb_pipebulk(pipe))    __s = "bulk";   \
+        else                            __s = "iso";    \
+        __s;})
+#define PIPEDIR(pipe)   ({ usb_pipein(pipe) ? "in" : "out"; })
+#define URB_NOTSHORT(urb) ({ (urb)->transfer_flags & URB_SHORT_NOT_OK ? \
+        "short_not_ok" : ""; })
+/* print debug info about the URB */
+static void urb_dbg(struct urb *urb, char *msg)
+{
+        unsigned int pipe;
+        if (!urb) {
+                DBG("%s: zero urb\n", msg);
+                return;
+        }
+        pipe = urb->pipe;
+        DBG("%s: FA %d ep%d%s %s: len %d/%d %s\n", msg,
+            usb_pipedevice(pipe), usb_pipeendpoint(pipe),
+            PIPEDIR(pipe), PIPETYPE(pipe),
+            urb->transfer_buffer_length, urb->actual_length, URB_NOTSHORT(urb));
+}
+#else
+#define  urb_dbg(urb,msg)   do{}while(0)
+#endif                          /* ! defined(URB_TRACE) */
+#if defined(PTD_TRACE)
+#define PTD_DIR_STR(ptd)  ({char __c;           \
+        switch(PTD_GET_DIR(ptd)){               \
+        case 0:  __c = 's'; break;              \
+        case 1:  __c = 'o'; break;              \
+        default: __c = 'i'; break;              \
+        }; __c;})
+/*
+  Dump PTD info. The code documents the format
+  perfectly, right :)
+*/
+static inline void dump_ptd(struct ptd *ptd)
+{
+        printk("td: %x %d%c%d %d,%d,%d  %x %x%x%x\n",
+               PTD_GET_CC(ptd), PTD_GET_FA(ptd),
+               PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
+               PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
+               PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd),
+               PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
+}
+static inline void dump_ptd_out_data(struct ptd *ptd, u8 * buf)
+{
+        int k;
+        if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
+                printk("-> ");
+                for (k = 0; k < PTD_GET_LEN(ptd); ++k)
+                        printk("%02x ", ((u8 *) buf)[k]);
+                printk("\n");
+        }
+}
+static inline void dump_ptd_in_data(struct ptd *ptd, u8 * buf)
+{
+        int k;
+        if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
+                printk("<- ");
+                for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
+                        printk("%02x ", ((u8 *) buf)[k]);
+                printk("\n");
+        }
+        if (PTD_GET_LAST(ptd))
+                printk("-\n");
+}
+#else
+#define dump_ptd(ptd)               do{}while(0)
+#define dump_ptd_in_data(ptd,buf)   do{}while(0)
+#define dump_ptd_out_data(ptd,buf)  do{}while(0)
+#endif                          /* ! defined(PTD_TRACE) */

diff --git a/drivers/usb/host/isp116x.h b/drivers/usb/host/isp116x.h new file mode 100644 index 000000000000..58873470dcf5 --- /dev/null +++ b/drivers/usb/host/isp116x.h
@@ -0,0 +1,583 @@
	1	/*
	2	* ISP116x register declarations and HCD data structures
	3	*
	4	* Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
	5	* Portions:
	6	* Copyright (C) 2004 Lothar Wassmann
	7	* Copyright (C) 2004 Psion Teklogix
	8	* Copyright (C) 2004 David Brownell
	9	*/
	10
	11	/* us of 1ms frame */
	12	#define MAX_LOAD_LIMIT 850
	13
	14	/* Full speed: max # of bytes to transfer for a single urb
	15	at a time must be < 1024 && must be multiple of 64.
	16	832 allows transfering 4kiB within 5 frames. */
	17	#define MAX_TRANSFER_SIZE_FULLSPEED 832
	18
	19	/* Low speed: there is no reason to schedule in very big
	20	chunks; often the requested long transfers are for
	21	string descriptors containing short strings. */
	22	#define MAX_TRANSFER_SIZE_LOWSPEED 64
	23
	24	/* Bytetime (us), a rough indication of how much time it
	25	would take to transfer a byte of useful data over USB */
	26	#define BYTE_TIME_FULLSPEED 1
	27	#define BYTE_TIME_LOWSPEED 20
	28
	29	/* Buffer sizes */
	30	#define ISP116x_BUF_SIZE 4096
	31	#define ISP116x_ITL_BUFSIZE 0
	32	#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
	33
	34	#define ISP116x_WRITE_OFFSET 0x80
	35
	36	/------------ ISP116x registers/bits ------------/
	37	#define HCREVISION 0x00
	38	#define HCCONTROL 0x01
	39	#define HCCONTROL_HCFS (3 << 6) /* host controller
	40	functional state */
	41	#define HCCONTROL_USB_RESET (0 << 6)
	42	#define HCCONTROL_USB_RESUME (1 << 6)
	43	#define HCCONTROL_USB_OPER (2 << 6)
	44	#define HCCONTROL_USB_SUSPEND (3 << 6)
	45	#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
	46	#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
	47	#define HCCMDSTAT 0x02
	48	#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
	49	#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
	50	#define HCINTSTAT 0x03
	51	#define HCINT_SO (1 << 0) /* scheduling overrun */
	52	#define HCINT_WDH (1 << 1) /* writeback of done_head */
	53	#define HCINT_SF (1 << 2) /* start frame */
	54	#define HCINT_RD (1 << 3) /* resume detect */
	55	#define HCINT_UE (1 << 4) /* unrecoverable error */
	56	#define HCINT_FNO (1 << 5) /* frame number overflow */
	57	#define HCINT_RHSC (1 << 6) /* root hub status change */
	58	#define HCINT_OC (1 << 30) /* ownership change */
	59	#define HCINT_MIE (1 << 31) /* master interrupt enable */
	60	#define HCINTENB 0x04
	61	#define HCINTDIS 0x05
	62	#define HCFMINTVL 0x0d
	63	#define HCFMREM 0x0e
	64	#define HCFMNUM 0x0f
	65	#define HCLSTHRESH 0x11
	66	#define HCRHDESCA 0x12
	67	#define RH_A_NDP (0x3 << 0) /* # downstream ports */
	68	#define RH_A_PSM (1 << 8) /* power switching mode */
	69	#define RH_A_NPS (1 << 9) /* no power switching */
	70	#define RH_A_DT (1 << 10) /* device type (mbz) */
	71	#define RH_A_OCPM (1 << 11) /* overcurrent protection
	72	mode */
	73	#define RH_A_NOCP (1 << 12) /* no overcurrent protection */
	74	#define RH_A_POTPGT (0xff << 24) /* power on -> power good
	75	time */
	76	#define HCRHDESCB 0x13
	77	#define RH_B_DR (0xffff << 0) /* device removable flags */
	78	#define RH_B_PPCM (0xffff << 16) /* port power control mask */
	79	#define HCRHSTATUS 0x14
	80	#define RH_HS_LPS (1 << 0) /* local power status */
	81	#define RH_HS_OCI (1 << 1) /* over current indicator */
	82	#define RH_HS_DRWE (1 << 15) /* device remote wakeup
	83	enable */
	84	#define RH_HS_LPSC (1 << 16) /* local power status change */
	85	#define RH_HS_OCIC (1 << 17) /* over current indicator
	86	change */
	87	#define RH_HS_CRWE (1 << 31) /* clear remote wakeup
	88	enable */
	89	#define HCRHPORT1 0x15
	90	#define RH_PS_CCS (1 << 0) /* current connect status */
	91	#define RH_PS_PES (1 << 1) /* port enable status */
	92	#define RH_PS_PSS (1 << 2) /* port suspend status */
	93	#define RH_PS_POCI (1 << 3) /* port over current
	94	indicator */
	95	#define RH_PS_PRS (1 << 4) /* port reset status */
	96	#define RH_PS_PPS (1 << 8) /* port power status */
	97	#define RH_PS_LSDA (1 << 9) /* low speed device attached */
	98	#define RH_PS_CSC (1 << 16) /* connect status change */
	99	#define RH_PS_PESC (1 << 17) /* port enable status change */
	100	#define RH_PS_PSSC (1 << 18) /* port suspend status
	101	change */
	102	#define RH_PS_OCIC (1 << 19) /* over current indicator
	103	change */
	104	#define RH_PS_PRSC (1 << 20) /* port reset status change */
	105	#define HCRHPORT_CLRMASK (0x1f << 16)
	106	#define HCRHPORT2 0x16
	107	#define HCHWCFG 0x20
	108	#define HCHWCFG_15KRSEL (1 << 12)
	109	#define HCHWCFG_CLKNOTSTOP (1 << 11)
	110	#define HCHWCFG_ANALOG_OC (1 << 10)
	111	#define HCHWCFG_DACK_MODE (1 << 8)
	112	#define HCHWCFG_EOT_POL (1 << 7)
	113	#define HCHWCFG_DACK_POL (1 << 6)
	114	#define HCHWCFG_DREQ_POL (1 << 5)
	115	#define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
	116	#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
	117	#define HCHWCFG_INT_POL (1 << 2)
	118	#define HCHWCFG_INT_TRIGGER (1 << 1)
	119	#define HCHWCFG_INT_ENABLE (1 << 0)
	120	#define HCDMACFG 0x21
	121	#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
	122	#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
	123	#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
	124	#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
	125	#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
	126	#define HCDMACFG_DMA_ENABLE (1 << 4)
	127	#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
	128	#define HCDMACFG_CTR_SEL (1 << 2)
	129	#define HCDMACFG_ITLATL_SEL (1 << 1)
	130	#define HCDMACFG_DMA_RW_SELECT (1 << 0)
	131	#define HCXFERCTR 0x22
	132	#define HCuPINT 0x24
	133	#define HCuPINT_SOF (1 << 0)
	134	#define HCuPINT_ATL (1 << 1)
	135	#define HCuPINT_AIIEOT (1 << 2)
	136	#define HCuPINT_OPR (1 << 4)
	137	#define HCuPINT_SUSP (1 << 5)
	138	#define HCuPINT_CLKRDY (1 << 6)
	139	#define HCuPINTENB 0x25
	140	#define HCCHIPID 0x27
	141	#define HCCHIPID_MASK 0xff00
	142	#define HCCHIPID_MAGIC 0x6100
	143	#define HCSCRATCH 0x28
	144	#define HCSWRES 0x29
	145	#define HCSWRES_MAGIC 0x00f6
	146	#define HCITLBUFLEN 0x2a
	147	#define HCATLBUFLEN 0x2b
	148	#define HCBUFSTAT 0x2c
	149	#define HCBUFSTAT_ITL0_FULL (1 << 0)
	150	#define HCBUFSTAT_ITL1_FULL (1 << 1)
	151	#define HCBUFSTAT_ATL_FULL (1 << 2)
	152	#define HCBUFSTAT_ITL0_DONE (1 << 3)
	153	#define HCBUFSTAT_ITL1_DONE (1 << 4)
	154	#define HCBUFSTAT_ATL_DONE (1 << 5)
	155	#define HCRDITL0LEN 0x2d
	156	#define HCRDITL1LEN 0x2e
	157	#define HCITLPORT 0x40
	158	#define HCATLPORT 0x41
	159
	160	/* Philips transfer descriptor */
	161	struct ptd {
	162	u16 count;
	163	#define PTD_COUNT_MSK (0x3ff << 0)
	164	#define PTD_TOGGLE_MSK (1 << 10)
	165	#define PTD_ACTIVE_MSK (1 << 11)
	166	#define PTD_CC_MSK (0xf << 12)
	167	u16 mps;
	168	#define PTD_MPS_MSK (0x3ff << 0)
	169	#define PTD_SPD_MSK (1 << 10)
	170	#define PTD_LAST_MSK (1 << 11)
	171	#define PTD_EP_MSK (0xf << 12)
	172	u16 len;
	173	#define PTD_LEN_MSK (0x3ff << 0)
	174	#define PTD_DIR_MSK (3 << 10)
	175	#define PTD_DIR_SETUP (0)
	176	#define PTD_DIR_OUT (1)
	177	#define PTD_DIR_IN (2)
	178	#define PTD_B5_5_MSK (1 << 13)
	179	u16 faddr;
	180	#define PTD_FA_MSK (0x7f << 0)
	181	#define PTD_FMT_MSK (1 << 7)
	182	} __attribute__ ((packed, aligned(2)));
	183
	184	/* PTD accessor macros. */
	185	#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
	186	#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
	187	#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
	188	#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
	189	#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
	190	#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
	191	#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
	192	#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
	193	#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
	194	#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
	195	#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
	196	#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
	197	#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
	198	#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
	199	#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
	200	#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
	201	#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
	202	#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
	203	#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
	204	#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
	205	#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
	206	#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
	207	#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
	208	#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
	209	#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
	210	#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
	211
	212	/* Hardware transfer status codes -- CC from ptd->count */
	213	#define TD_CC_NOERROR 0x00
	214	#define TD_CC_CRC 0x01
	215	#define TD_CC_BITSTUFFING 0x02
	216	#define TD_CC_DATATOGGLEM 0x03
	217	#define TD_CC_STALL 0x04
	218	#define TD_DEVNOTRESP 0x05
	219	#define TD_PIDCHECKFAIL 0x06
	220	#define TD_UNEXPECTEDPID 0x07
	221	#define TD_DATAOVERRUN 0x08
	222	#define TD_DATAUNDERRUN 0x09
	223	/* 0x0A, 0x0B reserved for hardware */
	224	#define TD_BUFFEROVERRUN 0x0C
	225	#define TD_BUFFERUNDERRUN 0x0D
	226	/* 0x0E, 0x0F reserved for HCD */
	227	#define TD_NOTACCESSED 0x0F
	228
	229	/* map PTD status codes (CC) to errno values */
	230	static const int cc_to_error[16] = {
	231	/* No Error */ 0,
	232	/* CRC Error */ -EILSEQ,
	233	/* Bit Stuff */ -EPROTO,
	234	/* Data Togg */ -EILSEQ,
	235	/* Stall */ -EPIPE,
	236	/* DevNotResp */ -ETIMEDOUT,
	237	/* PIDCheck */ -EPROTO,
	238	/* UnExpPID */ -EPROTO,
	239	/* DataOver */ -EOVERFLOW,
	240	/* DataUnder */ -EREMOTEIO,
	241	/* (for hw) */ -EIO,
	242	/* (for hw) */ -EIO,
	243	/* BufferOver */ -ECOMM,
	244	/* BuffUnder */ -ENOSR,
	245	/* (for HCD) */ -EALREADY,
	246	/* (for HCD) */ -EALREADY
	247	};
	248
	249	/--------------------------------------------------------------/
	250
	251	#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
	252	#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
	253
	254	struct isp116x {
	255	spinlock_t lock;
	256	struct work_struct rh_resume;
	257
	258	void __iomem *addr_reg;
	259	void __iomem *data_reg;
	260
	261	struct isp116x_platform_data *board;
	262
	263	struct proc_dir_entry *pde;
	264	unsigned long stat1, stat2, stat4, stat8, stat16;
	265
	266	/* HC registers */
	267	u32 intenb; /* "OHCI" interrupts */
	268	u16 irqenb; /* uP interrupts */
	269
	270	/* Root hub registers */
	271	u32 rhdesca;
	272	u32 rhdescb;
	273	u32 rhstatus;
	274	u32 rhport[2];
	275
	276	/* async schedule: control, bulk */
	277	struct list_head async;
	278
	279	/* periodic schedule: int */
	280	u16 load[PERIODIC_SIZE];
	281	struct isp116x_ep *periodic[PERIODIC_SIZE];
	282	unsigned periodic_count;
	283	u16 fmindex;
	284
	285	/* Schedule for the current frame */
	286	struct isp116x_ep *atl_active;
	287	int atl_buflen;
	288	int atl_bufshrt;
	289	int atl_last_dir;
	290	atomic_t atl_finishing;
	291	};
	292
	293	static inline struct isp116x hcd_to_isp116x(struct usb_hcd hcd)
	294	{
	295	return (struct isp116x *)(hcd->hcd_priv);
	296	}
	297
	298	static inline struct usb_hcd isp116x_to_hcd(struct isp116x isp116x)
	299	{
	300	return container_of((void *)isp116x, struct usb_hcd, hcd_priv);
	301	}
	302
	303	struct isp116x_ep {
	304	struct usb_host_endpoint *hep;
	305	struct usb_device *udev;
	306	struct ptd ptd;
	307
	308	u8 maxpacket;
	309	u8 epnum;
	310	u8 nextpid;
	311	u16 error_count;
	312	u16 length; /* of current packet */
	313	unsigned char data; / to databuf */
	314	/* queue of active EP's (the ones scheduled for the
	315	current frame) */
	316	struct isp116x_ep *active;
	317
	318	/* periodic schedule */
	319	u16 period;
	320	u16 branch;
	321	u16 load;
	322	struct isp116x_ep *next;
	323
	324	/* async schedule */
	325	struct list_head schedule;
	326	};
	327
	328	/-------------------------------------------------------------------------/
	329
	330	#ifdef DEBUG
	331	#define DBG(stuff...) printk(KERN_DEBUG "116x: " stuff)
	332	#else
	333	#define DBG(stuff...) do{}while(0)
	334	#endif
	335
	336	#ifdef VERBOSE
	337	# define VDBG DBG
	338	#else
	339	# define VDBG(stuff...) do{}while(0)
	340	#endif
	341
	342	#define ERR(stuff...) printk(KERN_ERR "116x: " stuff)
	343	#define WARN(stuff...) printk(KERN_WARNING "116x: " stuff)
	344	#define INFO(stuff...) printk(KERN_INFO "116x: " stuff)
	345
	346	/* ------------------------------------------------- */
	347
	348	#if defined(USE_PLATFORM_DELAY)
	349	#if defined(USE_NDELAY)
	350	#error USE_PLATFORM_DELAY and USE_NDELAY simultaneously defined.
	351	#endif
	352	#define isp116x_delay(h,d) (h)->board->delay( \
	353	isp116x_to_hcd(h)->self.controller,d)
	354	#define isp116x_check_platform_delay(h) ((h)->board->delay == NULL)
	355	#elif defined(USE_NDELAY)
	356	#define isp116x_delay(h,d) ndelay(d)
	357	#define isp116x_check_platform_delay(h) 0
	358	#else
	359	#define isp116x_delay(h,d) do{}while(0)
	360	#define isp116x_check_platform_delay(h) 0
	361	#endif
	362
	363	#if defined(DEBUG)
	364	#define IRQ_TEST() BUG_ON(!irqs_disabled())
	365	#else
	366	#define IRQ_TEST() do{}while(0)
	367	#endif
	368
	369	static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
	370	{
	371	IRQ_TEST();
	372	writew(reg & 0xff, isp116x->addr_reg);
	373	isp116x_delay(isp116x, 300);
	374	}
	375
	376	static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
	377	{
	378	writew(val, isp116x->data_reg);
	379	isp116x_delay(isp116x, 150);
	380	}
	381
	382	static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
	383	{
	384	__raw_writew(val, isp116x->data_reg);
	385	isp116x_delay(isp116x, 150);
	386	}
	387
	388	static inline u16 isp116x_read_data16(struct isp116x *isp116x)
	389	{
	390	u16 val;
	391
	392	val = readw(isp116x->data_reg);
	393	isp116x_delay(isp116x, 150);
	394	return val;
	395	}
	396
	397	static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
	398	{
	399	u16 val;
	400
	401	val = __raw_readw(isp116x->data_reg);
	402	isp116x_delay(isp116x, 150);
	403	return val;
	404	}
	405
	406	static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
	407	{
	408	writew(val & 0xffff, isp116x->data_reg);
	409	isp116x_delay(isp116x, 150);
	410	writew(val >> 16, isp116x->data_reg);
	411	isp116x_delay(isp116x, 150);
	412	}
	413
	414	static inline u32 isp116x_read_data32(struct isp116x *isp116x)
	415	{
	416	u32 val;
	417
	418	val = (u32) readw(isp116x->data_reg);
	419	isp116x_delay(isp116x, 150);
	420	val \|= ((u32) readw(isp116x->data_reg)) << 16;
	421	isp116x_delay(isp116x, 150);
	422	return val;
	423	}
	424
	425	/* Let's keep register access functions out of line. Hint:
	426	we wait at least 150 ns at every access.
	427	*/
	428	static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
	429	{
	430	isp116x_write_addr(isp116x, reg);
	431	return isp116x_read_data16(isp116x);
	432	}
	433
	434	static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
	435	{
	436	isp116x_write_addr(isp116x, reg);
	437	return isp116x_read_data32(isp116x);
	438	}
	439
	440	static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
	441	unsigned val)
	442	{
	443	isp116x_write_addr(isp116x, reg \| ISP116x_WRITE_OFFSET);
	444	isp116x_write_data16(isp116x, (u16) (val & 0xffff));
	445	}
	446
	447	static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
	448	unsigned val)
	449	{
	450	isp116x_write_addr(isp116x, reg \| ISP116x_WRITE_OFFSET);
	451	isp116x_write_data32(isp116x, (u32) val);
	452	}
	453
	454	#define isp116x_show_reg(d,r) { \
	455	if ((r) < 0x20) { \
	456	DBG("%-12s[%02x]: %08x\n", #r, \
	457	r, isp116x_read_reg32(d, r)); \
	458	} else { \
	459	DBG("%-12s[%02x]: %04x\n", #r, \
	460	r, isp116x_read_reg16(d, r)); \
	461	} \
	462	}
	463
	464	static inline void isp116x_show_regs(struct isp116x *isp116x)
	465	{
	466	isp116x_show_reg(isp116x, HCREVISION);
	467	isp116x_show_reg(isp116x, HCCONTROL);
	468	isp116x_show_reg(isp116x, HCCMDSTAT);
	469	isp116x_show_reg(isp116x, HCINTSTAT);
	470	isp116x_show_reg(isp116x, HCINTENB);
	471	isp116x_show_reg(isp116x, HCFMINTVL);
	472	isp116x_show_reg(isp116x, HCFMREM);
	473	isp116x_show_reg(isp116x, HCFMNUM);
	474	isp116x_show_reg(isp116x, HCLSTHRESH);
	475	isp116x_show_reg(isp116x, HCRHDESCA);
	476	isp116x_show_reg(isp116x, HCRHDESCB);
	477	isp116x_show_reg(isp116x, HCRHSTATUS);
	478	isp116x_show_reg(isp116x, HCRHPORT1);
	479	isp116x_show_reg(isp116x, HCRHPORT2);
	480	isp116x_show_reg(isp116x, HCHWCFG);
	481	isp116x_show_reg(isp116x, HCDMACFG);
	482	isp116x_show_reg(isp116x, HCXFERCTR);
	483	isp116x_show_reg(isp116x, HCuPINT);
	484	isp116x_show_reg(isp116x, HCuPINTENB);
	485	isp116x_show_reg(isp116x, HCCHIPID);
	486	isp116x_show_reg(isp116x, HCSCRATCH);
	487	isp116x_show_reg(isp116x, HCITLBUFLEN);
	488	isp116x_show_reg(isp116x, HCATLBUFLEN);
	489	isp116x_show_reg(isp116x, HCBUFSTAT);
	490	isp116x_show_reg(isp116x, HCRDITL0LEN);
	491	isp116x_show_reg(isp116x, HCRDITL1LEN);
	492	}
	493
	494	#if defined(URB_TRACE)
	495
	496	#define PIPETYPE(pipe) ({ char *__s; \
	497	if (usb_pipecontrol(pipe)) __s = "ctrl"; \
	498	else if (usb_pipeint(pipe)) __s = "int"; \
	499	else if (usb_pipebulk(pipe)) __s = "bulk"; \
	500	else __s = "iso"; \
	501	__s;})
	502	#define PIPEDIR(pipe) ({ usb_pipein(pipe) ? "in" : "out"; })
	503	#define URB_NOTSHORT(urb) ({ (urb)->transfer_flags & URB_SHORT_NOT_OK ? \
	504	"short_not_ok" : ""; })
	505
	506	/* print debug info about the URB */
	507	static void urb_dbg(struct urb urb, char msg)
	508	{
	509	unsigned int pipe;
	510
	511	if (!urb) {
	512	DBG("%s: zero urb\n", msg);
	513	return;
	514	}
	515	pipe = urb->pipe;
	516	DBG("%s: FA %d ep%d%s %s: len %d/%d %s\n", msg,
	517	usb_pipedevice(pipe), usb_pipeendpoint(pipe),
	518	PIPEDIR(pipe), PIPETYPE(pipe),
	519	urb->transfer_buffer_length, urb->actual_length, URB_NOTSHORT(urb));
	520	}
	521
	522	#else
	523
	524	#define urb_dbg(urb,msg) do{}while(0)
	525
	526	#endif /* ! defined(URB_TRACE) */
	527
	528	#if defined(PTD_TRACE)
	529
	530	#define PTD_DIR_STR(ptd) ({char __c; \
	531	switch(PTD_GET_DIR(ptd)){ \
	532	case 0: __c = 's'; break; \
	533	case 1: __c = 'o'; break; \
	534	default: __c = 'i'; break; \
	535	}; __c;})
	536
	537	/*
	538	Dump PTD info. The code documents the format
	539	perfectly, right :)
	540	*/
	541	static inline void dump_ptd(struct ptd *ptd)
	542	{
	543	printk("td: %x %d%c%d %d,%d,%d %x %x%x%x\n",
	544	PTD_GET_CC(ptd), PTD_GET_FA(ptd),
	545	PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
	546	PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
	547	PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd),
	548	PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
	549	}
	550
	551	static inline void dump_ptd_out_data(struct ptd ptd, u8 buf)
	552	{
	553	int k;
	554
	555	if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
	556	printk("-> ");
	557	for (k = 0; k < PTD_GET_LEN(ptd); ++k)
	558	printk("%02x ", ((u8 *) buf)[k]);
	559	printk("\n");
	560	}
	561	}
	562
	563	static inline void dump_ptd_in_data(struct ptd ptd, u8 buf)
	564	{
	565	int k;
	566
	567	if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
	568	printk("<- ");
	569	for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
	570	printk("%02x ", ((u8 *) buf)[k]);
	571	printk("\n");
	572	}
	573	if (PTD_GET_LAST(ptd))
	574	printk("-\n");
	575	}
	576
	577	#else
	578
	579	#define dump_ptd(ptd) do{}while(0)
	580	#define dump_ptd_in_data(ptd,buf) do{}while(0)
	581	#define dump_ptd_out_data(ptd,buf) do{}while(0)
	582
	583	#endif /* ! defined(PTD_TRACE) */