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-rw-r--r--drivers/usb/gadget/Kconfig14
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/at91_udc.c4
-rw-r--r--drivers/usb/gadget/ci13xxx_udc.c344
-rw-r--r--drivers/usb/gadget/ci13xxx_udc.h9
-rw-r--r--drivers/usb/gadget/composite.c14
-rw-r--r--drivers/usb/gadget/dummy_hcd.c4
-rw-r--r--drivers/usb/gadget/epautoconf.c7
-rw-r--r--drivers/usb/gadget/f_fs.c8
-rw-r--r--drivers/usb/gadget/fsl_mxc_udc.c21
-rw-r--r--drivers/usb/gadget/fsl_udc_core.c2
-rw-r--r--drivers/usb/gadget/fusb300_udc.c1744
-rw-r--r--drivers/usb/gadget/fusb300_udc.h687
-rw-r--r--drivers/usb/gadget/m66592-udc.c2
-rw-r--r--drivers/usb/gadget/pch_udc.c178
-rw-r--r--drivers/usb/gadget/s3c2410_udc.c76
-rw-r--r--drivers/usb/gadget/u_ether.c2
17 files changed, 2904 insertions, 213 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index d50099675f28..bfde50e20b30 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -176,6 +176,18 @@ config USB_FSL_USB2
176 default USB_GADGET 176 default USB_GADGET
177 select USB_GADGET_SELECTED 177 select USB_GADGET_SELECTED
178 178
179config USB_GADGET_FUSB300
180 boolean "Faraday FUSB300 USB Peripheral Controller"
181 select USB_GADGET_DUALSPEED
182 help
183 Faraday usb device controller FUSB300 driver
184
185config USB_FUSB300
186 tristate
187 depends on USB_GADGET_FUSB300
188 default USB_GADGET
189 select USB_GADGET_SELECTED
190
179config USB_GADGET_LH7A40X 191config USB_GADGET_LH7A40X
180 boolean "LH7A40X" 192 boolean "LH7A40X"
181 depends on ARCH_LH7A40X 193 depends on ARCH_LH7A40X
@@ -540,7 +552,7 @@ config USB_GADGET_CI13XXX_MSM
540 boolean "MIPS USB CI13xxx for MSM" 552 boolean "MIPS USB CI13xxx for MSM"
541 depends on ARCH_MSM 553 depends on ARCH_MSM
542 select USB_GADGET_DUALSPEED 554 select USB_GADGET_DUALSPEED
543 select USB_MSM_OTG_72K 555 select USB_MSM_OTG
544 help 556 help
545 MSM SoC has chipidea USB controller. This driver uses 557 MSM SoC has chipidea USB controller. This driver uses
546 ci13xxx_udc core. 558 ci13xxx_udc core.
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 55f5e8ae5924..305286e181d5 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_USB_EG20T) += pch_udc.o
28obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o 28obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
29mv_udc-y := mv_udc_core.o mv_udc_phy.o 29mv_udc-y := mv_udc_core.o mv_udc_phy.o
30obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o 30obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
31obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
31 32
32# 33#
33# USB gadget drivers 34# USB gadget drivers
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index bdec36acd0fa..bb8ddf0469f9 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -1798,8 +1798,10 @@ static int __init at91udc_probe(struct platform_device *pdev)
1798 } 1798 }
1799 1799
1800 retval = device_register(&udc->gadget.dev); 1800 retval = device_register(&udc->gadget.dev);
1801 if (retval < 0) 1801 if (retval < 0) {
1802 put_device(&udc->gadget.dev);
1802 goto fail0b; 1803 goto fail0b;
1804 }
1803 1805
1804 /* don't do anything until we have both gadget driver and VBUS */ 1806 /* don't do anything until we have both gadget driver and VBUS */
1805 clk_enable(udc->iclk); 1807 clk_enable(udc->iclk);
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index a1c67ae1572a..e09178bc1450 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -435,20 +435,6 @@ static int hw_ep_get_halt(int num, int dir)
435} 435}
436 436
437/** 437/**
438 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
439 * @num: endpoint number
440 * @dir: endpoint direction
441 *
442 * This function returns true if endpoint primed
443 */
444static int hw_ep_is_primed(int num, int dir)
445{
446 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
447
448 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
449}
450
451/**
452 * hw_test_and_clear_setup_status: test & clear setup status (execute without 438 * hw_test_and_clear_setup_status: test & clear setup status (execute without
453 * interruption) 439 * interruption)
454 * @n: bit number (endpoint) 440 * @n: bit number (endpoint)
@@ -472,10 +458,6 @@ static int hw_ep_prime(int num, int dir, int is_ctrl)
472{ 458{
473 int n = hw_ep_bit(num, dir); 459 int n = hw_ep_bit(num, dir);
474 460
475 /* the caller should flush first */
476 if (hw_ep_is_primed(num, dir))
477 return -EBUSY;
478
479 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num))) 461 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
480 return -EAGAIN; 462 return -EAGAIN;
481 463
@@ -1434,6 +1416,8 @@ static inline u8 _usb_addr(struct ci13xxx_ep *ep)
1434static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) 1416static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1435{ 1417{
1436 unsigned i; 1418 unsigned i;
1419 int ret = 0;
1420 unsigned length = mReq->req.length;
1437 1421
1438 trace("%p, %p", mEp, mReq); 1422 trace("%p, %p", mEp, mReq);
1439 1423
@@ -1441,53 +1425,91 @@ static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1441 if (mReq->req.status == -EALREADY) 1425 if (mReq->req.status == -EALREADY)
1442 return -EALREADY; 1426 return -EALREADY;
1443 1427
1444 if (hw_ep_is_primed(mEp->num, mEp->dir))
1445 return -EBUSY;
1446
1447 mReq->req.status = -EALREADY; 1428 mReq->req.status = -EALREADY;
1448 1429 if (length && !mReq->req.dma) {
1449 if (mReq->req.length && !mReq->req.dma) {
1450 mReq->req.dma = \ 1430 mReq->req.dma = \
1451 dma_map_single(mEp->device, mReq->req.buf, 1431 dma_map_single(mEp->device, mReq->req.buf,
1452 mReq->req.length, mEp->dir ? 1432 length, mEp->dir ? DMA_TO_DEVICE :
1453 DMA_TO_DEVICE : DMA_FROM_DEVICE); 1433 DMA_FROM_DEVICE);
1454 if (mReq->req.dma == 0) 1434 if (mReq->req.dma == 0)
1455 return -ENOMEM; 1435 return -ENOMEM;
1456 1436
1457 mReq->map = 1; 1437 mReq->map = 1;
1458 } 1438 }
1459 1439
1440 if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
1441 mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
1442 &mReq->zdma);
1443 if (mReq->zptr == NULL) {
1444 if (mReq->map) {
1445 dma_unmap_single(mEp->device, mReq->req.dma,
1446 length, mEp->dir ? DMA_TO_DEVICE :
1447 DMA_FROM_DEVICE);
1448 mReq->req.dma = 0;
1449 mReq->map = 0;
1450 }
1451 return -ENOMEM;
1452 }
1453 memset(mReq->zptr, 0, sizeof(*mReq->zptr));
1454 mReq->zptr->next = TD_TERMINATE;
1455 mReq->zptr->token = TD_STATUS_ACTIVE;
1456 if (!mReq->req.no_interrupt)
1457 mReq->zptr->token |= TD_IOC;
1458 }
1460 /* 1459 /*
1461 * TD configuration 1460 * TD configuration
1462 * TODO - handle requests which spawns into several TDs 1461 * TODO - handle requests which spawns into several TDs
1463 */ 1462 */
1464 memset(mReq->ptr, 0, sizeof(*mReq->ptr)); 1463 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
1465 mReq->ptr->next |= TD_TERMINATE; 1464 mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
1466 mReq->ptr->token = mReq->req.length << ffs_nr(TD_TOTAL_BYTES);
1467 mReq->ptr->token &= TD_TOTAL_BYTES; 1465 mReq->ptr->token &= TD_TOTAL_BYTES;
1468 mReq->ptr->token |= TD_IOC;
1469 mReq->ptr->token |= TD_STATUS_ACTIVE; 1466 mReq->ptr->token |= TD_STATUS_ACTIVE;
1467 if (mReq->zptr) {
1468 mReq->ptr->next = mReq->zdma;
1469 } else {
1470 mReq->ptr->next = TD_TERMINATE;
1471 if (!mReq->req.no_interrupt)
1472 mReq->ptr->token |= TD_IOC;
1473 }
1470 mReq->ptr->page[0] = mReq->req.dma; 1474 mReq->ptr->page[0] = mReq->req.dma;
1471 for (i = 1; i < 5; i++) 1475 for (i = 1; i < 5; i++)
1472 mReq->ptr->page[i] = 1476 mReq->ptr->page[i] =
1473 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK; 1477 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
1474 1478
1475 /* 1479 if (!list_empty(&mEp->qh.queue)) {
1476 * QH configuration 1480 struct ci13xxx_req *mReqPrev;
1477 * At this point it's guaranteed exclusive access to qhead 1481 int n = hw_ep_bit(mEp->num, mEp->dir);
1478 * (endpt is not primed) so it's no need to use tripwire 1482 int tmp_stat;
1479 */ 1483
1484 mReqPrev = list_entry(mEp->qh.queue.prev,
1485 struct ci13xxx_req, queue);
1486 if (mReqPrev->zptr)
1487 mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
1488 else
1489 mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
1490 wmb();
1491 if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
1492 goto done;
1493 do {
1494 hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
1495 tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
1496 } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
1497 hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
1498 if (tmp_stat)
1499 goto done;
1500 }
1501
1502 /* QH configuration */
1480 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */ 1503 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
1481 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */ 1504 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
1482 if (mReq->req.zero == 0) 1505 mEp->qh.ptr->cap |= QH_ZLT;
1483 mEp->qh.ptr->cap |= QH_ZLT;
1484 else
1485 mEp->qh.ptr->cap &= ~QH_ZLT;
1486 1506
1487 wmb(); /* synchronize before ep prime */ 1507 wmb(); /* synchronize before ep prime */
1488 1508
1489 return hw_ep_prime(mEp->num, mEp->dir, 1509 ret = hw_ep_prime(mEp->num, mEp->dir,
1490 mEp->type == USB_ENDPOINT_XFER_CONTROL); 1510 mEp->type == USB_ENDPOINT_XFER_CONTROL);
1511done:
1512 return ret;
1491} 1513}
1492 1514
1493/** 1515/**
@@ -1504,8 +1526,15 @@ static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1504 if (mReq->req.status != -EALREADY) 1526 if (mReq->req.status != -EALREADY)
1505 return -EINVAL; 1527 return -EINVAL;
1506 1528
1507 if (hw_ep_is_primed(mEp->num, mEp->dir)) 1529 if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
1508 hw_ep_flush(mEp->num, mEp->dir); 1530 return -EBUSY;
1531
1532 if (mReq->zptr) {
1533 if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
1534 return -EBUSY;
1535 dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
1536 mReq->zptr = NULL;
1537 }
1509 1538
1510 mReq->req.status = 0; 1539 mReq->req.status = 0;
1511 1540
@@ -1517,9 +1546,7 @@ static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1517 } 1546 }
1518 1547
1519 mReq->req.status = mReq->ptr->token & TD_STATUS; 1548 mReq->req.status = mReq->ptr->token & TD_STATUS;
1520 if ((TD_STATUS_ACTIVE & mReq->req.status) != 0) 1549 if ((TD_STATUS_HALTED & mReq->req.status) != 0)
1521 mReq->req.status = -ECONNRESET;
1522 else if ((TD_STATUS_HALTED & mReq->req.status) != 0)
1523 mReq->req.status = -1; 1550 mReq->req.status = -1;
1524 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0) 1551 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
1525 mReq->req.status = -1; 1552 mReq->req.status = -1;
@@ -1581,12 +1608,19 @@ static int _gadget_stop_activity(struct usb_gadget *gadget)
1581{ 1608{
1582 struct usb_ep *ep; 1609 struct usb_ep *ep;
1583 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget); 1610 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1611 unsigned long flags;
1584 1612
1585 trace("%p", gadget); 1613 trace("%p", gadget);
1586 1614
1587 if (gadget == NULL) 1615 if (gadget == NULL)
1588 return -EINVAL; 1616 return -EINVAL;
1589 1617
1618 spin_lock_irqsave(udc->lock, flags);
1619 udc->gadget.speed = USB_SPEED_UNKNOWN;
1620 udc->remote_wakeup = 0;
1621 udc->suspended = 0;
1622 spin_unlock_irqrestore(udc->lock, flags);
1623
1590 /* flush all endpoints */ 1624 /* flush all endpoints */
1591 gadget_for_each_ep(ep, gadget) { 1625 gadget_for_each_ep(ep, gadget) {
1592 usb_ep_fifo_flush(ep); 1626 usb_ep_fifo_flush(ep);
@@ -1720,7 +1754,8 @@ __acquires(mEp->lock)
1720 } 1754 }
1721 1755
1722 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) { 1756 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1723 /* TODO: D1 - Remote Wakeup; D0 - Self Powered */ 1757 /* Assume that device is bus powered for now. */
1758 *((u16 *)req->buf) = _udc->remote_wakeup << 1;
1724 retval = 0; 1759 retval = 0;
1725 } else if ((setup->bRequestType & USB_RECIP_MASK) \ 1760 } else if ((setup->bRequestType & USB_RECIP_MASK) \
1726 == USB_RECIP_ENDPOINT) { 1761 == USB_RECIP_ENDPOINT) {
@@ -1749,6 +1784,28 @@ __acquires(mEp->lock)
1749} 1784}
1750 1785
1751/** 1786/**
1787 * isr_setup_status_complete: setup_status request complete function
1788 * @ep: endpoint
1789 * @req: request handled
1790 *
1791 * Caller must release lock. Put the port in test mode if test mode
1792 * feature is selected.
1793 */
1794static void
1795isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
1796{
1797 struct ci13xxx *udc = req->context;
1798 unsigned long flags;
1799
1800 trace("%p, %p", ep, req);
1801
1802 spin_lock_irqsave(udc->lock, flags);
1803 if (udc->test_mode)
1804 hw_port_test_set(udc->test_mode);
1805 spin_unlock_irqrestore(udc->lock, flags);
1806}
1807
1808/**
1752 * isr_setup_status_phase: queues the status phase of a setup transation 1809 * isr_setup_status_phase: queues the status phase of a setup transation
1753 * @udc: udc struct 1810 * @udc: udc struct
1754 * 1811 *
@@ -1764,6 +1821,8 @@ __acquires(mEp->lock)
1764 trace("%p", udc); 1821 trace("%p", udc);
1765 1822
1766 mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in; 1823 mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
1824 udc->status->context = udc;
1825 udc->status->complete = isr_setup_status_complete;
1767 1826
1768 spin_unlock(mEp->lock); 1827 spin_unlock(mEp->lock);
1769 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC); 1828 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
@@ -1783,7 +1842,7 @@ static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
1783__releases(mEp->lock) 1842__releases(mEp->lock)
1784__acquires(mEp->lock) 1843__acquires(mEp->lock)
1785{ 1844{
1786 struct ci13xxx_req *mReq; 1845 struct ci13xxx_req *mReq, *mReqTemp;
1787 int retval; 1846 int retval;
1788 1847
1789 trace("%p", mEp); 1848 trace("%p", mEp);
@@ -1791,34 +1850,25 @@ __acquires(mEp->lock)
1791 if (list_empty(&mEp->qh.queue)) 1850 if (list_empty(&mEp->qh.queue))
1792 return -EINVAL; 1851 return -EINVAL;
1793 1852
1794 /* pop oldest request */ 1853 list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
1795 mReq = list_entry(mEp->qh.queue.next, 1854 queue) {
1796 struct ci13xxx_req, queue); 1855 retval = _hardware_dequeue(mEp, mReq);
1797 list_del_init(&mReq->queue); 1856 if (retval < 0)
1798 1857 break;
1799 retval = _hardware_dequeue(mEp, mReq); 1858 list_del_init(&mReq->queue);
1800 if (retval < 0) { 1859 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
1801 dbg_event(_usb_addr(mEp), "DONE", retval); 1860 if (mReq->req.complete != NULL) {
1802 goto done; 1861 spin_unlock(mEp->lock);
1803 } 1862 mReq->req.complete(&mEp->ep, &mReq->req);
1804 1863 spin_lock(mEp->lock);
1805 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval); 1864 }
1806
1807 if (!list_empty(&mEp->qh.queue)) {
1808 struct ci13xxx_req* mReqEnq;
1809
1810 mReqEnq = list_entry(mEp->qh.queue.next,
1811 struct ci13xxx_req, queue);
1812 _hardware_enqueue(mEp, mReqEnq);
1813 } 1865 }
1814 1866
1815 if (mReq->req.complete != NULL) { 1867 if (retval == EBUSY)
1816 spin_unlock(mEp->lock); 1868 retval = 0;
1817 mReq->req.complete(&mEp->ep, &mReq->req); 1869 if (retval < 0)
1818 spin_lock(mEp->lock); 1870 dbg_event(_usb_addr(mEp), "DONE", retval);
1819 }
1820 1871
1821 done:
1822 return retval; 1872 return retval;
1823} 1873}
1824 1874
@@ -1833,6 +1883,7 @@ __releases(udc->lock)
1833__acquires(udc->lock) 1883__acquires(udc->lock)
1834{ 1884{
1835 unsigned i; 1885 unsigned i;
1886 u8 tmode = 0;
1836 1887
1837 trace("%p", udc); 1888 trace("%p", udc);
1838 1889
@@ -1895,22 +1946,32 @@ __acquires(udc->lock)
1895 1946
1896 switch (req.bRequest) { 1947 switch (req.bRequest) {
1897 case USB_REQ_CLEAR_FEATURE: 1948 case USB_REQ_CLEAR_FEATURE:
1898 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) && 1949 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1899 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT) 1950 le16_to_cpu(req.wValue) ==
1900 goto delegate; 1951 USB_ENDPOINT_HALT) {
1901 if (req.wLength != 0) 1952 if (req.wLength != 0)
1902 break;
1903 num = le16_to_cpu(req.wIndex);
1904 num &= USB_ENDPOINT_NUMBER_MASK;
1905 if (!udc->ci13xxx_ep[num].wedge) {
1906 spin_unlock(udc->lock);
1907 err = usb_ep_clear_halt(
1908 &udc->ci13xxx_ep[num].ep);
1909 spin_lock(udc->lock);
1910 if (err)
1911 break; 1953 break;
1954 num = le16_to_cpu(req.wIndex);
1955 num &= USB_ENDPOINT_NUMBER_MASK;
1956 if (!udc->ci13xxx_ep[num].wedge) {
1957 spin_unlock(udc->lock);
1958 err = usb_ep_clear_halt(
1959 &udc->ci13xxx_ep[num].ep);
1960 spin_lock(udc->lock);
1961 if (err)
1962 break;
1963 }
1964 err = isr_setup_status_phase(udc);
1965 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
1966 le16_to_cpu(req.wValue) ==
1967 USB_DEVICE_REMOTE_WAKEUP) {
1968 if (req.wLength != 0)
1969 break;
1970 udc->remote_wakeup = 0;
1971 err = isr_setup_status_phase(udc);
1972 } else {
1973 goto delegate;
1912 } 1974 }
1913 err = isr_setup_status_phase(udc);
1914 break; 1975 break;
1915 case USB_REQ_GET_STATUS: 1976 case USB_REQ_GET_STATUS:
1916 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) && 1977 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
@@ -1934,20 +1995,48 @@ __acquires(udc->lock)
1934 err = isr_setup_status_phase(udc); 1995 err = isr_setup_status_phase(udc);
1935 break; 1996 break;
1936 case USB_REQ_SET_FEATURE: 1997 case USB_REQ_SET_FEATURE:
1937 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) && 1998 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1938 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT) 1999 le16_to_cpu(req.wValue) ==
1939 goto delegate; 2000 USB_ENDPOINT_HALT) {
1940 if (req.wLength != 0) 2001 if (req.wLength != 0)
1941 break; 2002 break;
1942 num = le16_to_cpu(req.wIndex); 2003 num = le16_to_cpu(req.wIndex);
1943 num &= USB_ENDPOINT_NUMBER_MASK; 2004 num &= USB_ENDPOINT_NUMBER_MASK;
1944 2005
1945 spin_unlock(udc->lock); 2006 spin_unlock(udc->lock);
1946 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep); 2007 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
1947 spin_lock(udc->lock); 2008 spin_lock(udc->lock);
1948 if (err) 2009 if (!err)
1949 break; 2010 isr_setup_status_phase(udc);
1950 err = isr_setup_status_phase(udc); 2011 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
2012 if (req.wLength != 0)
2013 break;
2014 switch (le16_to_cpu(req.wValue)) {
2015 case USB_DEVICE_REMOTE_WAKEUP:
2016 udc->remote_wakeup = 1;
2017 err = isr_setup_status_phase(udc);
2018 break;
2019 case USB_DEVICE_TEST_MODE:
2020 tmode = le16_to_cpu(req.wIndex) >> 8;
2021 switch (tmode) {
2022 case TEST_J:
2023 case TEST_K:
2024 case TEST_SE0_NAK:
2025 case TEST_PACKET:
2026 case TEST_FORCE_EN:
2027 udc->test_mode = tmode;
2028 err = isr_setup_status_phase(
2029 udc);
2030 break;
2031 default:
2032 break;
2033 }
2034 default:
2035 goto delegate;
2036 }
2037 } else {
2038 goto delegate;
2039 }
1951 break; 2040 break;
1952 default: 2041 default:
1953delegate: 2042delegate:
@@ -2178,15 +2267,15 @@ static int ep_queue(struct usb_ep *ep, struct usb_request *req,
2178 /* push request */ 2267 /* push request */
2179 mReq->req.status = -EINPROGRESS; 2268 mReq->req.status = -EINPROGRESS;
2180 mReq->req.actual = 0; 2269 mReq->req.actual = 0;
2181 list_add_tail(&mReq->queue, &mEp->qh.queue);
2182 2270
2183 if (list_is_singular(&mEp->qh.queue)) 2271 retval = _hardware_enqueue(mEp, mReq);
2184 retval = _hardware_enqueue(mEp, mReq);
2185 2272
2186 if (retval == -EALREADY) { 2273 if (retval == -EALREADY) {
2187 dbg_event(_usb_addr(mEp), "QUEUE", retval); 2274 dbg_event(_usb_addr(mEp), "QUEUE", retval);
2188 retval = 0; 2275 retval = 0;
2189 } 2276 }
2277 if (!retval)
2278 list_add_tail(&mReq->queue, &mEp->qh.queue);
2190 2279
2191 done: 2280 done:
2192 spin_unlock_irqrestore(mEp->lock, flags); 2281 spin_unlock_irqrestore(mEp->lock, flags);
@@ -2206,19 +2295,25 @@ static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2206 2295
2207 trace("%p, %p", ep, req); 2296 trace("%p, %p", ep, req);
2208 2297
2209 if (ep == NULL || req == NULL || mEp->desc == NULL || 2298 if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
2210 list_empty(&mReq->queue) || list_empty(&mEp->qh.queue)) 2299 mEp->desc == NULL || list_empty(&mReq->queue) ||
2300 list_empty(&mEp->qh.queue))
2211 return -EINVAL; 2301 return -EINVAL;
2212 2302
2213 spin_lock_irqsave(mEp->lock, flags); 2303 spin_lock_irqsave(mEp->lock, flags);
2214 2304
2215 dbg_event(_usb_addr(mEp), "DEQUEUE", 0); 2305 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
2216 2306
2217 if (mReq->req.status == -EALREADY) 2307 hw_ep_flush(mEp->num, mEp->dir);
2218 _hardware_dequeue(mEp, mReq);
2219 2308
2220 /* pop request */ 2309 /* pop request */
2221 list_del_init(&mReq->queue); 2310 list_del_init(&mReq->queue);
2311 if (mReq->map) {
2312 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
2313 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
2314 mReq->req.dma = 0;
2315 mReq->map = 0;
2316 }
2222 req->status = -ECONNRESET; 2317 req->status = -ECONNRESET;
2223 2318
2224 if (mReq->req.complete != NULL) { 2319 if (mReq->req.complete != NULL) {
@@ -2377,6 +2472,31 @@ static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
2377 return 0; 2472 return 0;
2378} 2473}
2379 2474
2475static int ci13xxx_wakeup(struct usb_gadget *_gadget)
2476{
2477 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2478 unsigned long flags;
2479 int ret = 0;
2480
2481 trace();
2482
2483 spin_lock_irqsave(udc->lock, flags);
2484 if (!udc->remote_wakeup) {
2485 ret = -EOPNOTSUPP;
2486 dbg_trace("remote wakeup feature is not enabled\n");
2487 goto out;
2488 }
2489 if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
2490 ret = -EINVAL;
2491 dbg_trace("port is not suspended\n");
2492 goto out;
2493 }
2494 hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
2495out:
2496 spin_unlock_irqrestore(udc->lock, flags);
2497 return ret;
2498}
2499
2380/** 2500/**
2381 * Device operations part of the API to the USB controller hardware, 2501 * Device operations part of the API to the USB controller hardware,
2382 * which don't involve endpoints (or i/o) 2502 * which don't involve endpoints (or i/o)
@@ -2384,6 +2504,7 @@ static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
2384 */ 2504 */
2385static const struct usb_gadget_ops usb_gadget_ops = { 2505static const struct usb_gadget_ops usb_gadget_ops = {
2386 .vbus_session = ci13xxx_vbus_session, 2506 .vbus_session = ci13xxx_vbus_session,
2507 .wakeup = ci13xxx_wakeup,
2387}; 2508};
2388 2509
2389/** 2510/**
@@ -2626,6 +2747,12 @@ static irqreturn_t udc_irq(void)
2626 isr_statistics.pci++; 2747 isr_statistics.pci++;
2627 udc->gadget.speed = hw_port_is_high_speed() ? 2748 udc->gadget.speed = hw_port_is_high_speed() ?
2628 USB_SPEED_HIGH : USB_SPEED_FULL; 2749 USB_SPEED_HIGH : USB_SPEED_FULL;
2750 if (udc->suspended) {
2751 spin_unlock(udc->lock);
2752 udc->driver->resume(&udc->gadget);
2753 spin_lock(udc->lock);
2754 udc->suspended = 0;
2755 }
2629 } 2756 }
2630 if (USBi_UEI & intr) 2757 if (USBi_UEI & intr)
2631 isr_statistics.uei++; 2758 isr_statistics.uei++;
@@ -2633,8 +2760,15 @@ static irqreturn_t udc_irq(void)
2633 isr_statistics.ui++; 2760 isr_statistics.ui++;
2634 isr_tr_complete_handler(udc); 2761 isr_tr_complete_handler(udc);
2635 } 2762 }
2636 if (USBi_SLI & intr) 2763 if (USBi_SLI & intr) {
2764 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
2765 udc->suspended = 1;
2766 spin_unlock(udc->lock);
2767 udc->driver->suspend(&udc->gadget);
2768 spin_lock(udc->lock);
2769 }
2637 isr_statistics.sli++; 2770 isr_statistics.sli++;
2771 }
2638 retval = IRQ_HANDLED; 2772 retval = IRQ_HANDLED;
2639 } else { 2773 } else {
2640 isr_statistics.none++; 2774 isr_statistics.none++;
diff --git a/drivers/usb/gadget/ci13xxx_udc.h b/drivers/usb/gadget/ci13xxx_udc.h
index a2492b65f98c..23707775cb43 100644
--- a/drivers/usb/gadget/ci13xxx_udc.h
+++ b/drivers/usb/gadget/ci13xxx_udc.h
@@ -33,6 +33,7 @@ struct ci13xxx_td {
33 /* 0 */ 33 /* 0 */
34 u32 next; 34 u32 next;
35#define TD_TERMINATE BIT(0) 35#define TD_TERMINATE BIT(0)
36#define TD_ADDR_MASK (0xFFFFFFEUL << 5)
36 /* 1 */ 37 /* 1 */
37 u32 token; 38 u32 token;
38#define TD_STATUS (0x00FFUL << 0) 39#define TD_STATUS (0x00FFUL << 0)
@@ -74,6 +75,8 @@ struct ci13xxx_req {
74 struct list_head queue; 75 struct list_head queue;
75 struct ci13xxx_td *ptr; 76 struct ci13xxx_td *ptr;
76 dma_addr_t dma; 77 dma_addr_t dma;
78 struct ci13xxx_td *zptr;
79 dma_addr_t zdma;
77}; 80};
78 81
79/* Extension of usb_ep */ 82/* Extension of usb_ep */
@@ -125,6 +128,10 @@ struct ci13xxx {
125 u32 ep0_dir; /* ep0 direction */ 128 u32 ep0_dir; /* ep0 direction */
126#define ep0out ci13xxx_ep[0] 129#define ep0out ci13xxx_ep[0]
127#define ep0in ci13xxx_ep[16] 130#define ep0in ci13xxx_ep[16]
131 u8 remote_wakeup; /* Is remote wakeup feature
132 enabled by the host? */
133 u8 suspended; /* suspended by the host */
134 u8 test_mode; /* the selected test mode */
128 135
129 struct usb_gadget_driver *driver; /* 3rd party gadget driver */ 136 struct usb_gadget_driver *driver; /* 3rd party gadget driver */
130 struct ci13xxx_udc_driver *udc_driver; /* device controller driver */ 137 struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
@@ -152,6 +159,7 @@ struct ci13xxx {
152#define USBCMD_RS BIT(0) 159#define USBCMD_RS BIT(0)
153#define USBCMD_RST BIT(1) 160#define USBCMD_RST BIT(1)
154#define USBCMD_SUTW BIT(13) 161#define USBCMD_SUTW BIT(13)
162#define USBCMD_ATDTW BIT(14)
155 163
156/* USBSTS & USBINTR */ 164/* USBSTS & USBINTR */
157#define USBi_UI BIT(0) 165#define USBi_UI BIT(0)
@@ -165,6 +173,7 @@ struct ci13xxx {
165#define DEVICEADDR_USBADR (0x7FUL << 25) 173#define DEVICEADDR_USBADR (0x7FUL << 25)
166 174
167/* PORTSC */ 175/* PORTSC */
176#define PORTSC_FPR BIT(6)
168#define PORTSC_SUSP BIT(7) 177#define PORTSC_SUSP BIT(7)
169#define PORTSC_HSP BIT(9) 178#define PORTSC_HSP BIT(9)
170#define PORTSC_PTC (0x0FUL << 16) 179#define PORTSC_PTC (0x0FUL << 16)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 1ba4befe336b..c2251c40a205 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -813,7 +813,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
813 */ 813 */
814 req->zero = 0; 814 req->zero = 0;
815 req->complete = composite_setup_complete; 815 req->complete = composite_setup_complete;
816 req->length = USB_BUFSIZ; 816 req->length = 0;
817 gadget->ep0->driver_data = cdev; 817 gadget->ep0->driver_data = cdev;
818 818
819 switch (ctrl->bRequest) { 819 switch (ctrl->bRequest) {
@@ -887,7 +887,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
887 case USB_REQ_SET_INTERFACE: 887 case USB_REQ_SET_INTERFACE:
888 if (ctrl->bRequestType != USB_RECIP_INTERFACE) 888 if (ctrl->bRequestType != USB_RECIP_INTERFACE)
889 goto unknown; 889 goto unknown;
890 if (!cdev->config || w_index >= MAX_CONFIG_INTERFACES) 890 if (!cdev->config || intf >= MAX_CONFIG_INTERFACES)
891 break; 891 break;
892 f = cdev->config->interface[intf]; 892 f = cdev->config->interface[intf];
893 if (!f) 893 if (!f)
@@ -899,7 +899,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
899 case USB_REQ_GET_INTERFACE: 899 case USB_REQ_GET_INTERFACE:
900 if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) 900 if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
901 goto unknown; 901 goto unknown;
902 if (!cdev->config || w_index >= MAX_CONFIG_INTERFACES) 902 if (!cdev->config || intf >= MAX_CONFIG_INTERFACES)
903 break; 903 break;
904 f = cdev->config->interface[intf]; 904 f = cdev->config->interface[intf];
905 if (!f) 905 if (!f)
@@ -928,7 +928,7 @@ unknown:
928 */ 928 */
929 switch (ctrl->bRequestType & USB_RECIP_MASK) { 929 switch (ctrl->bRequestType & USB_RECIP_MASK) {
930 case USB_RECIP_INTERFACE: 930 case USB_RECIP_INTERFACE:
931 if (!cdev->config || w_index >= MAX_CONFIG_INTERFACES) 931 if (!cdev->config || intf >= MAX_CONFIG_INTERFACES)
932 break; 932 break;
933 f = cdev->config->interface[intf]; 933 f = cdev->config->interface[intf];
934 break; 934 break;
@@ -1258,16 +1258,16 @@ static struct usb_gadget_driver composite_driver = {
1258 * while it was binding. That would usually be done in order to wait for 1258 * while it was binding. That would usually be done in order to wait for
1259 * some userspace participation. 1259 * some userspace participation.
1260 */ 1260 */
1261extern int usb_composite_probe(struct usb_composite_driver *driver, 1261int usb_composite_probe(struct usb_composite_driver *driver,
1262 int (*bind)(struct usb_composite_dev *cdev)) 1262 int (*bind)(struct usb_composite_dev *cdev))
1263{ 1263{
1264 if (!driver || !driver->dev || !bind || composite) 1264 if (!driver || !driver->dev || !bind || composite)
1265 return -EINVAL; 1265 return -EINVAL;
1266 1266
1267 if (!driver->iProduct)
1268 driver->iProduct = driver->name;
1269 if (!driver->name) 1267 if (!driver->name)
1270 driver->name = "composite"; 1268 driver->name = "composite";
1269 if (!driver->iProduct)
1270 driver->iProduct = driver->name;
1271 composite_driver.function = (char *) driver->name; 1271 composite_driver.function = (char *) driver->name;
1272 composite_driver.driver.name = driver->name; 1272 composite_driver.driver.name = driver->name;
1273 composite = driver; 1273 composite = driver;
diff --git a/drivers/usb/gadget/dummy_hcd.c b/drivers/usb/gadget/dummy_hcd.c
index 13b9f47feecd..3214ca375d64 100644
--- a/drivers/usb/gadget/dummy_hcd.c
+++ b/drivers/usb/gadget/dummy_hcd.c
@@ -1593,8 +1593,8 @@ hub_descriptor (struct usb_hub_descriptor *desc)
1593 desc->bDescLength = 9; 1593 desc->bDescLength = 9;
1594 desc->wHubCharacteristics = cpu_to_le16(0x0001); 1594 desc->wHubCharacteristics = cpu_to_le16(0x0001);
1595 desc->bNbrPorts = 1; 1595 desc->bNbrPorts = 1;
1596 desc->bitmap [0] = 0xff; 1596 desc->u.hs.DeviceRemovable[0] = 0xff;
1597 desc->bitmap [1] = 0xff; 1597 desc->u.hs.DeviceRemovable[1] = 0xff;
1598} 1598}
1599 1599
1600static int dummy_hub_control ( 1600static int dummy_hub_control (
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 8a832488ccdd..9b7360ff5aa7 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -128,6 +128,13 @@ ep_matches (
128 } 128 }
129 } 129 }
130 130
131 /*
132 * If the protocol driver hasn't yet decided on wMaxPacketSize
133 * and wants to know the maximum possible, provide the info.
134 */
135 if (desc->wMaxPacketSize == 0)
136 desc->wMaxPacketSize = cpu_to_le16(ep->maxpacket);
137
131 /* endpoint maxpacket size is an input parameter, except for bulk 138 /* endpoint maxpacket size is an input parameter, except for bulk
132 * where it's an output parameter representing the full speed limit. 139 * where it's an output parameter representing the full speed limit.
133 * the usb spec fixes high speed bulk maxpacket at 512 bytes. 140 * the usb spec fixes high speed bulk maxpacket at 512 bytes.
diff --git a/drivers/usb/gadget/f_fs.c b/drivers/usb/gadget/f_fs.c
index 1499f9e4afa8..19fffccc370d 100644
--- a/drivers/usb/gadget/f_fs.c
+++ b/drivers/usb/gadget/f_fs.c
@@ -368,6 +368,14 @@ static int __ffs_ep0_queue_wait(struct ffs_data *ffs, char *data, size_t len)
368 req->buf = data; 368 req->buf = data;
369 req->length = len; 369 req->length = len;
370 370
371 /*
372 * UDC layer requires to provide a buffer even for ZLP, but should
373 * not use it at all. Let's provide some poisoned pointer to catch
374 * possible bug in the driver.
375 */
376 if (req->buf == NULL)
377 req->buf = (void *)0xDEADBABE;
378
371 INIT_COMPLETION(ffs->ep0req_completion); 379 INIT_COMPLETION(ffs->ep0req_completion);
372 380
373 ret = usb_ep_queue(ffs->gadget->ep0, req, GFP_ATOMIC); 381 ret = usb_ep_queue(ffs->gadget->ep0, req, GFP_ATOMIC);
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 77b1eb577029..43a49ecc1f36 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -88,15 +88,18 @@ eenahb:
88void fsl_udc_clk_finalize(struct platform_device *pdev) 88void fsl_udc_clk_finalize(struct platform_device *pdev)
89{ 89{
90 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; 90 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
91#if defined(CONFIG_ARCH_MX35) 91#if defined(CONFIG_SOC_IMX35)
92 unsigned int v; 92 if (cpu_is_mx35()) {
93 93 unsigned int v;
94 /* workaround ENGcm09152 for i.MX35 */ 94
95 if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) { 95 /* workaround ENGcm09152 for i.MX35 */
96 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + 96 if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
97 USBPHYCTRL_OTGBASE_OFFSET)); 97 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
98 writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + 98 USBPHYCTRL_OTGBASE_OFFSET));
99 USBPHYCTRL_OTGBASE_OFFSET)); 99 writel(v | USBPHYCTRL_EVDO,
100 MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
101 USBPHYCTRL_OTGBASE_OFFSET));
102 }
100 } 103 }
101#endif 104#endif
102 105
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 4c55eda4bd20..912cb8e63fe3 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -766,7 +766,6 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
766 struct fsl_req *req = container_of(_req, struct fsl_req, req); 766 struct fsl_req *req = container_of(_req, struct fsl_req, req);
767 struct fsl_udc *udc; 767 struct fsl_udc *udc;
768 unsigned long flags; 768 unsigned long flags;
769 int is_iso = 0;
770 769
771 /* catch various bogus parameters */ 770 /* catch various bogus parameters */
772 if (!_req || !req->req.complete || !req->req.buf 771 if (!_req || !req->req.complete || !req->req.buf
@@ -781,7 +780,6 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
781 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 780 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
782 if (req->req.length > ep->ep.maxpacket) 781 if (req->req.length > ep->ep.maxpacket)
783 return -EMSGSIZE; 782 return -EMSGSIZE;
784 is_iso = 1;
785 } 783 }
786 784
787 udc = ep->udc; 785 udc = ep->udc;
diff --git a/drivers/usb/gadget/fusb300_udc.c b/drivers/usb/gadget/fusb300_udc.c
new file mode 100644
index 000000000000..763d462454b9
--- /dev/null
+++ b/drivers/usb/gadget/fusb300_udc.c
@@ -0,0 +1,1744 @@
1/*
2 * Fusb300 UDC (USB gadget)
3 *
4 * Copyright (C) 2010 Faraday Technology Corp.
5 *
6 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22#include <linux/dma-mapping.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/platform_device.h>
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29
30#include "fusb300_udc.h"
31
32MODULE_DESCRIPTION("FUSB300 USB gadget driver");
33MODULE_LICENSE("GPL");
34MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");
35MODULE_ALIAS("platform:fusb300_udc");
36
37#define DRIVER_VERSION "20 October 2010"
38
39static const char udc_name[] = "fusb300_udc";
40static const char * const fusb300_ep_name[] = {
41 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
42 "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
43};
44
45static void done(struct fusb300_ep *ep, struct fusb300_request *req,
46 int status);
47
48static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
49 u32 value)
50{
51 u32 reg = ioread32(fusb300->reg + offset);
52
53 reg |= value;
54 iowrite32(reg, fusb300->reg + offset);
55}
56
57static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
58 u32 value)
59{
60 u32 reg = ioread32(fusb300->reg + offset);
61
62 reg &= ~value;
63 iowrite32(reg, fusb300->reg + offset);
64}
65
66
67static void fusb300_ep_setting(struct fusb300_ep *ep,
68 struct fusb300_ep_info info)
69{
70 ep->epnum = info.epnum;
71 ep->type = info.type;
72}
73
74static int fusb300_ep_release(struct fusb300_ep *ep)
75{
76 if (!ep->epnum)
77 return 0;
78 ep->epnum = 0;
79 ep->stall = 0;
80 ep->wedged = 0;
81 return 0;
82}
83
84static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
85 u32 ep)
86{
87 u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
88
89 val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
90 val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
91 iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
92}
93
94static void fusb300_set_start_entry(struct fusb300 *fusb300,
95 u8 ep)
96{
97 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
98 u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
99
100 reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
101 reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
102 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
103 if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
104 fusb300->fifo_entry_num = 0;
105 fusb300->addrofs = 0;
106 pr_err("fifo entry is over the maximum number!\n");
107 } else
108 fusb300->fifo_entry_num++;
109}
110
111/* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
112static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
113 struct fusb300_ep_info info)
114{
115 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
116
117 reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
118 reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
119 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
120 fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
121}
122
123static void ep_fifo_setting(struct fusb300 *fusb300,
124 struct fusb300_ep_info info)
125{
126 fusb300_set_fifo_entry(fusb300, info.epnum);
127 fusb300_set_start_entry(fusb300, info.epnum);
128 fusb300_set_epaddrofs(fusb300, info);
129}
130
131static void fusb300_set_eptype(struct fusb300 *fusb300,
132 struct fusb300_ep_info info)
133{
134 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
135
136 reg &= ~FUSB300_EPSET1_TYPE_MSK;
137 reg |= FUSB300_EPSET1_TYPE(info.type);
138 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
139}
140
141static void fusb300_set_epdir(struct fusb300 *fusb300,
142 struct fusb300_ep_info info)
143{
144 u32 reg;
145
146 if (!info.dir_in)
147 return;
148 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
149 reg &= ~FUSB300_EPSET1_DIR_MSK;
150 reg |= FUSB300_EPSET1_DIRIN;
151 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
152}
153
154static void fusb300_set_ep_active(struct fusb300 *fusb300,
155 u8 ep)
156{
157 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
158
159 reg |= FUSB300_EPSET1_ACTEN;
160 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
161}
162
163static void fusb300_set_epmps(struct fusb300 *fusb300,
164 struct fusb300_ep_info info)
165{
166 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
167
168 reg &= ~FUSB300_EPSET2_MPS_MSK;
169 reg |= FUSB300_EPSET2_MPS(info.maxpacket);
170 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
171}
172
173static void fusb300_set_interval(struct fusb300 *fusb300,
174 struct fusb300_ep_info info)
175{
176 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
177
178 reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
179 reg |= FUSB300_EPSET1_INTERVAL(info.interval);
180 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
181}
182
183static void fusb300_set_bwnum(struct fusb300 *fusb300,
184 struct fusb300_ep_info info)
185{
186 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
187
188 reg &= ~FUSB300_EPSET1_BWNUM(0x3);
189 reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
190 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
191}
192
193static void set_ep_reg(struct fusb300 *fusb300,
194 struct fusb300_ep_info info)
195{
196 fusb300_set_eptype(fusb300, info);
197 fusb300_set_epdir(fusb300, info);
198 fusb300_set_epmps(fusb300, info);
199
200 if (info.interval)
201 fusb300_set_interval(fusb300, info);
202
203 if (info.bw_num)
204 fusb300_set_bwnum(fusb300, info);
205
206 fusb300_set_ep_active(fusb300, info.epnum);
207}
208
209static int config_ep(struct fusb300_ep *ep,
210 const struct usb_endpoint_descriptor *desc)
211{
212 struct fusb300 *fusb300 = ep->fusb300;
213 struct fusb300_ep_info info;
214
215 ep->desc = desc;
216
217 info.interval = 0;
218 info.addrofs = 0;
219 info.bw_num = 0;
220
221 info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
222 info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
223 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
224 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
225
226 if ((info.type == USB_ENDPOINT_XFER_INT) ||
227 (info.type == USB_ENDPOINT_XFER_ISOC)) {
228 info.interval = desc->bInterval;
229 if (info.type == USB_ENDPOINT_XFER_ISOC)
230 info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
231 }
232
233 ep_fifo_setting(fusb300, info);
234
235 set_ep_reg(fusb300, info);
236
237 fusb300_ep_setting(ep, info);
238
239 fusb300->ep[info.epnum] = ep;
240
241 return 0;
242}
243
244static int fusb300_enable(struct usb_ep *_ep,
245 const struct usb_endpoint_descriptor *desc)
246{
247 struct fusb300_ep *ep;
248
249 ep = container_of(_ep, struct fusb300_ep, ep);
250
251 if (ep->fusb300->reenum) {
252 ep->fusb300->fifo_entry_num = 0;
253 ep->fusb300->addrofs = 0;
254 ep->fusb300->reenum = 0;
255 }
256
257 return config_ep(ep, desc);
258}
259
260static int fusb300_disable(struct usb_ep *_ep)
261{
262 struct fusb300_ep *ep;
263 struct fusb300_request *req;
264 unsigned long flags;
265
266 ep = container_of(_ep, struct fusb300_ep, ep);
267
268 BUG_ON(!ep);
269
270 while (!list_empty(&ep->queue)) {
271 req = list_entry(ep->queue.next, struct fusb300_request, queue);
272 spin_lock_irqsave(&ep->fusb300->lock, flags);
273 done(ep, req, -ECONNRESET);
274 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
275 }
276
277 return fusb300_ep_release(ep);
278}
279
280static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
281 gfp_t gfp_flags)
282{
283 struct fusb300_request *req;
284
285 req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
286 if (!req)
287 return NULL;
288 INIT_LIST_HEAD(&req->queue);
289
290 return &req->req;
291}
292
293static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
294{
295 struct fusb300_request *req;
296
297 req = container_of(_req, struct fusb300_request, req);
298 kfree(req);
299}
300
301static int enable_fifo_int(struct fusb300_ep *ep)
302{
303 struct fusb300 *fusb300 = ep->fusb300;
304
305 if (ep->epnum) {
306 fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
307 FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
308 } else {
309 pr_err("can't enable_fifo_int ep0\n");
310 return -EINVAL;
311 }
312
313 return 0;
314}
315
316static int disable_fifo_int(struct fusb300_ep *ep)
317{
318 struct fusb300 *fusb300 = ep->fusb300;
319
320 if (ep->epnum) {
321 fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
322 FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
323 } else {
324 pr_err("can't disable_fifo_int ep0\n");
325 return -EINVAL;
326 }
327
328 return 0;
329}
330
331static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
332{
333 u32 reg;
334
335 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
336 reg &= ~FUSB300_CSR_LEN_MSK;
337 reg |= FUSB300_CSR_LEN(length);
338 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
339}
340
341/* write data to cx fifo */
342static void fusb300_wrcxf(struct fusb300_ep *ep,
343 struct fusb300_request *req)
344{
345 int i = 0;
346 u8 *tmp;
347 u32 data;
348 struct fusb300 *fusb300 = ep->fusb300;
349 u32 length = req->req.length - req->req.actual;
350
351 tmp = req->req.buf + req->req.actual;
352
353 if (length > SS_CTL_MAX_PACKET_SIZE) {
354 fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
355 for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
356 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
357 *(tmp + 3) << 24;
358 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
359 tmp += 4;
360 }
361 req->req.actual += SS_CTL_MAX_PACKET_SIZE;
362 } else { /* length is less than max packet size */
363 fusb300_set_cxlen(fusb300, length);
364 for (i = length >> 2; i > 0; i--) {
365 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
366 *(tmp + 3) << 24;
367 printk(KERN_DEBUG " 0x%x\n", data);
368 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
369 tmp = tmp + 4;
370 }
371 switch (length % 4) {
372 case 1:
373 data = *tmp;
374 printk(KERN_DEBUG " 0x%x\n", data);
375 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
376 break;
377 case 2:
378 data = *tmp | *(tmp + 1) << 8;
379 printk(KERN_DEBUG " 0x%x\n", data);
380 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
381 break;
382 case 3:
383 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
384 printk(KERN_DEBUG " 0x%x\n", data);
385 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
386 break;
387 default:
388 break;
389 }
390 req->req.actual += length;
391 }
392}
393
394static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
395{
396 fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
397 FUSB300_EPSET0_STL);
398}
399
400static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
401{
402 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
403
404 if (reg & FUSB300_EPSET0_STL) {
405 printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
406 reg &= ~FUSB300_EPSET0_STL;
407 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
408 }
409}
410
411static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
412{
413 if (ep->fusb300->ep0_dir) { /* if IN */
414 if (req->req.length) {
415 fusb300_wrcxf(ep, req);
416 } else
417 printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
418 __func__, req->req.length);
419 if ((req->req.length == req->req.actual) ||
420 (req->req.actual < ep->ep.maxpacket))
421 done(ep, req, 0);
422 } else { /* OUT */
423 if (!req->req.length)
424 done(ep, req, 0);
425 else
426 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
427 FUSB300_IGER1_CX_OUT_INT);
428 }
429}
430
431static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
432 gfp_t gfp_flags)
433{
434 struct fusb300_ep *ep;
435 struct fusb300_request *req;
436 unsigned long flags;
437 int request = 0;
438
439 ep = container_of(_ep, struct fusb300_ep, ep);
440 req = container_of(_req, struct fusb300_request, req);
441
442 if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
443 return -ESHUTDOWN;
444
445 spin_lock_irqsave(&ep->fusb300->lock, flags);
446
447 if (list_empty(&ep->queue))
448 request = 1;
449
450 list_add_tail(&req->queue, &ep->queue);
451
452 req->req.actual = 0;
453 req->req.status = -EINPROGRESS;
454
455 if (ep->desc == NULL) /* ep0 */
456 ep0_queue(ep, req);
457 else if (request && !ep->stall)
458 enable_fifo_int(ep);
459
460 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
461
462 return 0;
463}
464
465static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
466{
467 struct fusb300_ep *ep;
468 struct fusb300_request *req;
469 unsigned long flags;
470
471 ep = container_of(_ep, struct fusb300_ep, ep);
472 req = container_of(_req, struct fusb300_request, req);
473
474 spin_lock_irqsave(&ep->fusb300->lock, flags);
475 if (!list_empty(&ep->queue))
476 done(ep, req, -ECONNRESET);
477 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
478
479 return 0;
480}
481
482static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
483{
484 struct fusb300_ep *ep;
485 struct fusb300 *fusb300;
486 unsigned long flags;
487 int ret = 0;
488
489 ep = container_of(_ep, struct fusb300_ep, ep);
490
491 fusb300 = ep->fusb300;
492
493 spin_lock_irqsave(&ep->fusb300->lock, flags);
494
495 if (!list_empty(&ep->queue)) {
496 ret = -EAGAIN;
497 goto out;
498 }
499
500 if (value) {
501 fusb300_set_epnstall(fusb300, ep->epnum);
502 ep->stall = 1;
503 if (wedge)
504 ep->wedged = 1;
505 } else {
506 fusb300_clear_epnstall(fusb300, ep->epnum);
507 ep->stall = 0;
508 ep->wedged = 0;
509 }
510
511out:
512 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
513 return ret;
514}
515
516static int fusb300_set_halt(struct usb_ep *_ep, int value)
517{
518 return fusb300_set_halt_and_wedge(_ep, value, 0);
519}
520
521static int fusb300_set_wedge(struct usb_ep *_ep)
522{
523 return fusb300_set_halt_and_wedge(_ep, 1, 1);
524}
525
526static void fusb300_fifo_flush(struct usb_ep *_ep)
527{
528}
529
530static struct usb_ep_ops fusb300_ep_ops = {
531 .enable = fusb300_enable,
532 .disable = fusb300_disable,
533
534 .alloc_request = fusb300_alloc_request,
535 .free_request = fusb300_free_request,
536
537 .queue = fusb300_queue,
538 .dequeue = fusb300_dequeue,
539
540 .set_halt = fusb300_set_halt,
541 .fifo_flush = fusb300_fifo_flush,
542 .set_wedge = fusb300_set_wedge,
543};
544
545/*****************************************************************************/
546static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
547 u32 value)
548{
549 iowrite32(value, fusb300->reg + offset);
550}
551
552static void fusb300_reset(void)
553{
554}
555
556static void fusb300_set_cxstall(struct fusb300 *fusb300)
557{
558 fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
559 FUSB300_CSR_STL);
560}
561
562static void fusb300_set_cxdone(struct fusb300 *fusb300)
563{
564 fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
565 FUSB300_CSR_DONE);
566}
567
568/* read data from cx fifo */
569void fusb300_rdcxf(struct fusb300 *fusb300,
570 u8 *buffer, u32 length)
571{
572 int i = 0;
573 u8 *tmp;
574 u32 data;
575
576 tmp = buffer;
577
578 for (i = (length >> 2); i > 0; i--) {
579 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
580 printk(KERN_DEBUG " 0x%x\n", data);
581 *tmp = data & 0xFF;
582 *(tmp + 1) = (data >> 8) & 0xFF;
583 *(tmp + 2) = (data >> 16) & 0xFF;
584 *(tmp + 3) = (data >> 24) & 0xFF;
585 tmp = tmp + 4;
586 }
587
588 switch (length % 4) {
589 case 1:
590 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
591 printk(KERN_DEBUG " 0x%x\n", data);
592 *tmp = data & 0xFF;
593 break;
594 case 2:
595 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
596 printk(KERN_DEBUG " 0x%x\n", data);
597 *tmp = data & 0xFF;
598 *(tmp + 1) = (data >> 8) & 0xFF;
599 break;
600 case 3:
601 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
602 printk(KERN_DEBUG " 0x%x\n", data);
603 *tmp = data & 0xFF;
604 *(tmp + 1) = (data >> 8) & 0xFF;
605 *(tmp + 2) = (data >> 16) & 0xFF;
606 break;
607 default:
608 break;
609 }
610}
611
612#if 0
613static void fusb300_dbg_fifo(struct fusb300_ep *ep,
614 u8 entry, u16 length)
615{
616 u32 reg;
617 u32 i = 0;
618 u32 j = 0;
619
620 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
621 reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
622 FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
623 reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
624 FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
625 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
626
627 for (i = 0; i < (length >> 2); i++) {
628 if (i * 4 == 1024)
629 break;
630 reg = ioread32(ep->fusb300->reg +
631 FUSB300_OFFSET_BUFDBG_START + i * 4);
632 printk(KERN_DEBUG" 0x%-8x", reg);
633 j++;
634 if ((j % 4) == 0)
635 printk(KERN_DEBUG "\n");
636 }
637
638 if (length % 4) {
639 reg = ioread32(ep->fusb300->reg +
640 FUSB300_OFFSET_BUFDBG_START + i * 4);
641 printk(KERN_DEBUG " 0x%x\n", reg);
642 }
643
644 if ((j % 4) != 0)
645 printk(KERN_DEBUG "\n");
646
647 fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
648 FUSB300_GTM_TST_FIFO_DEG);
649}
650
651static void fusb300_cmp_dbg_fifo(struct fusb300_ep *ep,
652 u8 entry, u16 length, u8 *golden)
653{
654 u32 reg;
655 u32 i = 0;
656 u32 golden_value;
657 u8 *tmp;
658
659 tmp = golden;
660
661 printk(KERN_DEBUG "fusb300_cmp_dbg_fifo (entry %d) : start\n", entry);
662
663 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
664 reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
665 FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
666 reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
667 FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
668 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
669
670 for (i = 0; i < (length >> 2); i++) {
671 if (i * 4 == 1024)
672 break;
673 golden_value = *tmp | *(tmp + 1) << 8 |
674 *(tmp + 2) << 16 | *(tmp + 3) << 24;
675
676 reg = ioread32(ep->fusb300->reg +
677 FUSB300_OFFSET_BUFDBG_START + i*4);
678
679 if (reg != golden_value) {
680 printk(KERN_DEBUG "0x%x : ", (u32)(ep->fusb300->reg +
681 FUSB300_OFFSET_BUFDBG_START + i*4));
682 printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
683 golden_value, reg);
684 }
685 tmp += 4;
686 }
687
688 switch (length % 4) {
689 case 1:
690 golden_value = *tmp;
691 case 2:
692 golden_value = *tmp | *(tmp + 1) << 8;
693 case 3:
694 golden_value = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
695 default:
696 break;
697
698 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_BUFDBG_START + i*4);
699 if (reg != golden_value) {
700 printk(KERN_DEBUG "0x%x:", (u32)(ep->fusb300->reg +
701 FUSB300_OFFSET_BUFDBG_START + i*4));
702 printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
703 golden_value, reg);
704 }
705 }
706
707 printk(KERN_DEBUG "fusb300_cmp_dbg_fifo : end\n");
708 fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
709 FUSB300_GTM_TST_FIFO_DEG);
710}
711#endif
712
713static void fusb300_rdfifo(struct fusb300_ep *ep,
714 struct fusb300_request *req,
715 u32 length)
716{
717 int i = 0;
718 u8 *tmp;
719 u32 data, reg;
720 struct fusb300 *fusb300 = ep->fusb300;
721
722 tmp = req->req.buf + req->req.actual;
723 req->req.actual += length;
724
725 if (req->req.actual > req->req.length)
726 printk(KERN_DEBUG "req->req.actual > req->req.length\n");
727
728 for (i = (length >> 2); i > 0; i--) {
729 data = ioread32(fusb300->reg +
730 FUSB300_OFFSET_EPPORT(ep->epnum));
731 *tmp = data & 0xFF;
732 *(tmp + 1) = (data >> 8) & 0xFF;
733 *(tmp + 2) = (data >> 16) & 0xFF;
734 *(tmp + 3) = (data >> 24) & 0xFF;
735 tmp = tmp + 4;
736 }
737
738 switch (length % 4) {
739 case 1:
740 data = ioread32(fusb300->reg +
741 FUSB300_OFFSET_EPPORT(ep->epnum));
742 *tmp = data & 0xFF;
743 break;
744 case 2:
745 data = ioread32(fusb300->reg +
746 FUSB300_OFFSET_EPPORT(ep->epnum));
747 *tmp = data & 0xFF;
748 *(tmp + 1) = (data >> 8) & 0xFF;
749 break;
750 case 3:
751 data = ioread32(fusb300->reg +
752 FUSB300_OFFSET_EPPORT(ep->epnum));
753 *tmp = data & 0xFF;
754 *(tmp + 1) = (data >> 8) & 0xFF;
755 *(tmp + 2) = (data >> 16) & 0xFF;
756 break;
757 default:
758 break;
759 }
760
761 do {
762 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
763 reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
764 if (i)
765 printk(KERN_INFO "sync fifo is not empty!\n");
766 i++;
767 } while (!reg);
768}
769
770/* write data to fifo */
771static void fusb300_wrfifo(struct fusb300_ep *ep,
772 struct fusb300_request *req)
773{
774 int i = 0;
775 u8 *tmp;
776 u32 data, reg;
777 struct fusb300 *fusb300 = ep->fusb300;
778
779 tmp = req->req.buf;
780 req->req.actual = req->req.length;
781
782 for (i = (req->req.length >> 2); i > 0; i--) {
783 data = *tmp | *(tmp + 1) << 8 |
784 *(tmp + 2) << 16 | *(tmp + 3) << 24;
785
786 iowrite32(data, fusb300->reg +
787 FUSB300_OFFSET_EPPORT(ep->epnum));
788 tmp += 4;
789 }
790
791 switch (req->req.length % 4) {
792 case 1:
793 data = *tmp;
794 iowrite32(data, fusb300->reg +
795 FUSB300_OFFSET_EPPORT(ep->epnum));
796 break;
797 case 2:
798 data = *tmp | *(tmp + 1) << 8;
799 iowrite32(data, fusb300->reg +
800 FUSB300_OFFSET_EPPORT(ep->epnum));
801 break;
802 case 3:
803 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
804 iowrite32(data, fusb300->reg +
805 FUSB300_OFFSET_EPPORT(ep->epnum));
806 break;
807 default:
808 break;
809 }
810
811 do {
812 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
813 reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
814 if (i)
815 printk(KERN_INFO"sync fifo is not empty!\n");
816 i++;
817 } while (!reg);
818}
819
820static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
821{
822 u8 value;
823 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
824
825 value = reg & FUSB300_EPSET0_STL;
826
827 return value;
828}
829
830static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
831{
832 u8 value;
833 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
834
835 value = (reg & FUSB300_CSR_STL) >> 1;
836
837 return value;
838}
839
840static void request_error(struct fusb300 *fusb300)
841{
842 fusb300_set_cxstall(fusb300);
843 printk(KERN_DEBUG "request error!!\n");
844}
845
846static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
847__releases(fusb300->lock)
848__acquires(fusb300->lock)
849{
850 u8 ep;
851 u16 status = 0;
852 u16 w_index = ctrl->wIndex;
853
854 switch (ctrl->bRequestType & USB_RECIP_MASK) {
855 case USB_RECIP_DEVICE:
856 status = 1 << USB_DEVICE_SELF_POWERED;
857 break;
858 case USB_RECIP_INTERFACE:
859 status = 0;
860 break;
861 case USB_RECIP_ENDPOINT:
862 ep = w_index & USB_ENDPOINT_NUMBER_MASK;
863 if (ep) {
864 if (fusb300_get_epnstall(fusb300, ep))
865 status = 1 << USB_ENDPOINT_HALT;
866 } else {
867 if (fusb300_get_cxstall(fusb300))
868 status = 0;
869 }
870 break;
871
872 default:
873 request_error(fusb300);
874 return; /* exit */
875 }
876
877 fusb300->ep0_data = cpu_to_le16(status);
878 fusb300->ep0_req->buf = &fusb300->ep0_data;
879 fusb300->ep0_req->length = 2;
880
881 spin_unlock(&fusb300->lock);
882 fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
883 spin_lock(&fusb300->lock);
884}
885
886static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
887{
888 u8 ep;
889
890 switch (ctrl->bRequestType & USB_RECIP_MASK) {
891 case USB_RECIP_DEVICE:
892 fusb300_set_cxdone(fusb300);
893 break;
894 case USB_RECIP_INTERFACE:
895 fusb300_set_cxdone(fusb300);
896 break;
897 case USB_RECIP_ENDPOINT: {
898 u16 w_index = le16_to_cpu(ctrl->wIndex);
899
900 ep = w_index & USB_ENDPOINT_NUMBER_MASK;
901 if (ep)
902 fusb300_set_epnstall(fusb300, ep);
903 else
904 fusb300_set_cxstall(fusb300);
905 fusb300_set_cxdone(fusb300);
906 }
907 break;
908 default:
909 request_error(fusb300);
910 break;
911 }
912}
913
914static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
915{
916 fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
917 FUSB300_EPSET0_CLRSEQNUM);
918}
919
920static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
921{
922 struct fusb300_ep *ep =
923 fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
924
925 switch (ctrl->bRequestType & USB_RECIP_MASK) {
926 case USB_RECIP_DEVICE:
927 fusb300_set_cxdone(fusb300);
928 break;
929 case USB_RECIP_INTERFACE:
930 fusb300_set_cxdone(fusb300);
931 break;
932 case USB_RECIP_ENDPOINT:
933 if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
934 if (ep->wedged) {
935 fusb300_set_cxdone(fusb300);
936 break;
937 }
938 if (ep->stall) {
939 ep->stall = 0;
940 fusb300_clear_seqnum(fusb300, ep->epnum);
941 fusb300_clear_epnstall(fusb300, ep->epnum);
942 if (!list_empty(&ep->queue))
943 enable_fifo_int(ep);
944 }
945 }
946 fusb300_set_cxdone(fusb300);
947 break;
948 default:
949 request_error(fusb300);
950 break;
951 }
952}
953
954static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
955{
956 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
957
958 reg &= ~FUSB300_DAR_DRVADDR_MSK;
959 reg |= FUSB300_DAR_DRVADDR(addr);
960
961 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
962}
963
964static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
965{
966 if (ctrl->wValue >= 0x0100)
967 request_error(fusb300);
968 else {
969 fusb300_set_dev_addr(fusb300, ctrl->wValue);
970 fusb300_set_cxdone(fusb300);
971 }
972}
973
974#define UVC_COPY_DESCRIPTORS(mem, src) \
975 do { \
976 const struct usb_descriptor_header * const *__src; \
977 for (__src = src; *__src; ++__src) { \
978 memcpy(mem, *__src, (*__src)->bLength); \
979 mem += (*__src)->bLength; \
980 } \
981 } while (0)
982
983static void fusb300_ep0_complete(struct usb_ep *ep,
984 struct usb_request *req)
985{
986}
987
988static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
989{
990 u8 *p = (u8 *)ctrl;
991 u8 ret = 0;
992 u8 i = 0;
993
994 fusb300_rdcxf(fusb300, p, 8);
995 fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
996 fusb300->ep0_length = ctrl->wLength;
997
998 /* check request */
999 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1000 switch (ctrl->bRequest) {
1001 case USB_REQ_GET_STATUS:
1002 get_status(fusb300, ctrl);
1003 break;
1004 case USB_REQ_CLEAR_FEATURE:
1005 clear_feature(fusb300, ctrl);
1006 break;
1007 case USB_REQ_SET_FEATURE:
1008 set_feature(fusb300, ctrl);
1009 break;
1010 case USB_REQ_SET_ADDRESS:
1011 set_address(fusb300, ctrl);
1012 break;
1013 case USB_REQ_SET_CONFIGURATION:
1014 fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
1015 FUSB300_DAR_SETCONFG);
1016 /* clear sequence number */
1017 for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
1018 fusb300_clear_seqnum(fusb300, i);
1019 fusb300->reenum = 1;
1020 ret = 1;
1021 break;
1022 default:
1023 ret = 1;
1024 break;
1025 }
1026 } else
1027 ret = 1;
1028
1029 return ret;
1030}
1031
1032static void fusb300_set_ep_bycnt(struct fusb300_ep *ep, u32 bycnt)
1033{
1034 struct fusb300 *fusb300 = ep->fusb300;
1035 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1036
1037 reg &= ~FUSB300_FFR_BYCNT;
1038 reg |= bycnt & FUSB300_FFR_BYCNT;
1039
1040 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1041}
1042
1043static void done(struct fusb300_ep *ep, struct fusb300_request *req,
1044 int status)
1045{
1046 list_del_init(&req->queue);
1047
1048 /* don't modify queue heads during completion callback */
1049 if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
1050 req->req.status = -ESHUTDOWN;
1051 else
1052 req->req.status = status;
1053
1054 spin_unlock(&ep->fusb300->lock);
1055 req->req.complete(&ep->ep, &req->req);
1056 spin_lock(&ep->fusb300->lock);
1057
1058 if (ep->epnum) {
1059 disable_fifo_int(ep);
1060 if (!list_empty(&ep->queue))
1061 enable_fifo_int(ep);
1062 } else
1063 fusb300_set_cxdone(ep->fusb300);
1064}
1065
1066void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep,
1067 struct fusb300_request *req)
1068{
1069 u32 value;
1070 u32 reg;
1071
1072 /* wait SW owner */
1073 do {
1074 reg = ioread32(ep->fusb300->reg +
1075 FUSB300_OFFSET_EPPRD_W0(ep->epnum));
1076 reg &= FUSB300_EPPRD0_H;
1077 } while (reg);
1078
1079 iowrite32((u32) req->req.buf, ep->fusb300->reg +
1080 FUSB300_OFFSET_EPPRD_W1(ep->epnum));
1081
1082 value = FUSB300_EPPRD0_BTC(req->req.length) | FUSB300_EPPRD0_H |
1083 FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
1084 iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
1085
1086 iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
1087
1088 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
1089 FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
1090}
1091
1092static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
1093{
1094 u32 reg;
1095
1096 do {
1097 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
1098 if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
1099 (reg & FUSB300_IGR1_WARM_RST_INT) ||
1100 (reg & FUSB300_IGR1_HOT_RST_INT) ||
1101 (reg & FUSB300_IGR1_USBRST_INT)
1102 )
1103 goto IDMA_RESET;
1104 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
1105 reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
1106 } while (!reg);
1107
1108 fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
1109 FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
1110IDMA_RESET:
1111 fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0,
1112 FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
1113}
1114
1115static void fusb300_set_idma(struct fusb300_ep *ep,
1116 struct fusb300_request *req)
1117{
1118 dma_addr_t d;
1119 u8 *tmp = NULL;
1120
1121 d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE);
1122
1123 if (dma_mapping_error(NULL, d)) {
1124 kfree(req->req.buf);
1125 printk(KERN_DEBUG "dma_mapping_error\n");
1126 }
1127
1128 dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE);
1129
1130 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
1131 FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
1132
1133 tmp = req->req.buf;
1134 req->req.buf = (u8 *)d;
1135
1136 fusb300_fill_idma_prdtbl(ep, req);
1137 /* check idma is done */
1138 fusb300_wait_idma_finished(ep);
1139
1140 req->req.buf = tmp;
1141
1142 if (d)
1143 dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE);
1144}
1145
1146static void in_ep_fifo_handler(struct fusb300_ep *ep)
1147{
1148 struct fusb300_request *req = list_entry(ep->queue.next,
1149 struct fusb300_request, queue);
1150
1151 if (req->req.length) {
1152#if 0
1153 fusb300_set_ep_bycnt(ep, req->req.length);
1154 fusb300_wrfifo(ep, req);
1155#else
1156 fusb300_set_idma(ep, req);
1157#endif
1158 }
1159 done(ep, req, 0);
1160}
1161
1162static void out_ep_fifo_handler(struct fusb300_ep *ep)
1163{
1164 struct fusb300 *fusb300 = ep->fusb300;
1165 struct fusb300_request *req = list_entry(ep->queue.next,
1166 struct fusb300_request, queue);
1167 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1168 u32 length = reg & FUSB300_FFR_BYCNT;
1169
1170 fusb300_rdfifo(ep, req, length);
1171
1172 /* finish out transfer */
1173 if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
1174 done(ep, req, 0);
1175}
1176
1177static void check_device_mode(struct fusb300 *fusb300)
1178{
1179 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
1180
1181 switch (reg & FUSB300_GCR_DEVEN_MSK) {
1182 case FUSB300_GCR_DEVEN_SS:
1183 fusb300->gadget.speed = USB_SPEED_SUPER;
1184 break;
1185 case FUSB300_GCR_DEVEN_HS:
1186 fusb300->gadget.speed = USB_SPEED_HIGH;
1187 break;
1188 case FUSB300_GCR_DEVEN_FS:
1189 fusb300->gadget.speed = USB_SPEED_FULL;
1190 break;
1191 default:
1192 fusb300->gadget.speed = USB_SPEED_UNKNOWN;
1193 break;
1194 }
1195 printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
1196}
1197
1198
1199static void fusb300_ep0out(struct fusb300 *fusb300)
1200{
1201 struct fusb300_ep *ep = fusb300->ep[0];
1202 u32 reg;
1203
1204 if (!list_empty(&ep->queue)) {
1205 struct fusb300_request *req;
1206
1207 req = list_first_entry(&ep->queue,
1208 struct fusb300_request, queue);
1209 if (req->req.length)
1210 fusb300_rdcxf(ep->fusb300, req->req.buf,
1211 req->req.length);
1212 done(ep, req, 0);
1213 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
1214 reg &= ~FUSB300_IGER1_CX_OUT_INT;
1215 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
1216 } else
1217 pr_err("%s : empty queue\n", __func__);
1218}
1219
1220static void fusb300_ep0in(struct fusb300 *fusb300)
1221{
1222 struct fusb300_request *req;
1223 struct fusb300_ep *ep = fusb300->ep[0];
1224
1225 if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
1226 req = list_entry(ep->queue.next,
1227 struct fusb300_request, queue);
1228 if (req->req.length)
1229 fusb300_wrcxf(ep, req);
1230 if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
1231 done(ep, req, 0);
1232 } else
1233 fusb300_set_cxdone(fusb300);
1234}
1235
1236static void fusb300_grp2_handler(void)
1237{
1238}
1239
1240static void fusb300_grp3_handler(void)
1241{
1242}
1243
1244static void fusb300_grp4_handler(void)
1245{
1246}
1247
1248static void fusb300_grp5_handler(void)
1249{
1250}
1251
1252static irqreturn_t fusb300_irq(int irq, void *_fusb300)
1253{
1254 struct fusb300 *fusb300 = _fusb300;
1255 u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
1256 u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
1257 u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
1258 u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
1259 struct usb_ctrlrequest ctrl;
1260 u8 in;
1261 u32 reg;
1262 int i;
1263
1264 spin_lock(&fusb300->lock);
1265
1266 int_grp1 &= int_grp1_en;
1267 int_grp0 &= int_grp0_en;
1268
1269 if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
1270 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1271 FUSB300_IGR1_WARM_RST_INT);
1272 printk(KERN_INFO"fusb300_warmreset\n");
1273 fusb300_reset();
1274 }
1275
1276 if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
1277 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1278 FUSB300_IGR1_HOT_RST_INT);
1279 printk(KERN_INFO"fusb300_hotreset\n");
1280 fusb300_reset();
1281 }
1282
1283 if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
1284 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1285 FUSB300_IGR1_USBRST_INT);
1286 fusb300_reset();
1287 }
1288 /* COMABT_INT has a highest priority */
1289
1290 if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
1291 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1292 FUSB300_IGR1_CX_COMABT_INT);
1293 printk(KERN_INFO"fusb300_ep0abt\n");
1294 }
1295
1296 if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
1297 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1298 FUSB300_IGR1_VBUS_CHG_INT);
1299 printk(KERN_INFO"fusb300_vbus_change\n");
1300 }
1301
1302 if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
1303 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1304 FUSB300_IGR1_U3_EXIT_FAIL_INT);
1305 }
1306
1307 if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
1308 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1309 FUSB300_IGR1_U2_EXIT_FAIL_INT);
1310 }
1311
1312 if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
1313 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1314 FUSB300_IGR1_U1_EXIT_FAIL_INT);
1315 }
1316
1317 if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
1318 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1319 FUSB300_IGR1_U2_ENTRY_FAIL_INT);
1320 }
1321
1322 if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
1323 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1324 FUSB300_IGR1_U1_ENTRY_FAIL_INT);
1325 }
1326
1327 if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
1328 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1329 FUSB300_IGR1_U3_EXIT_INT);
1330 printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
1331 }
1332
1333 if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
1334 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1335 FUSB300_IGR1_U2_EXIT_INT);
1336 printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
1337 }
1338
1339 if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
1340 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1341 FUSB300_IGR1_U1_EXIT_INT);
1342 printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
1343 }
1344
1345 if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
1346 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1347 FUSB300_IGR1_U3_ENTRY_INT);
1348 printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
1349 fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
1350 FUSB300_SSCR1_GO_U3_DONE);
1351 }
1352
1353 if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
1354 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1355 FUSB300_IGR1_U2_ENTRY_INT);
1356 printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
1357 }
1358
1359 if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
1360 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1361 FUSB300_IGR1_U1_ENTRY_INT);
1362 printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
1363 }
1364
1365 if (int_grp1 & FUSB300_IGR1_RESM_INT) {
1366 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1367 FUSB300_IGR1_RESM_INT);
1368 printk(KERN_INFO "fusb300_resume\n");
1369 }
1370
1371 if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
1372 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1373 FUSB300_IGR1_SUSP_INT);
1374 printk(KERN_INFO "fusb300_suspend\n");
1375 }
1376
1377 if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
1378 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1379 FUSB300_IGR1_HS_LPM_INT);
1380 printk(KERN_INFO "fusb300_HS_LPM_INT\n");
1381 }
1382
1383 if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
1384 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1385 FUSB300_IGR1_DEV_MODE_CHG_INT);
1386 check_device_mode(fusb300);
1387 }
1388
1389 if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
1390 fusb300_set_cxstall(fusb300);
1391 printk(KERN_INFO "fusb300_ep0fail\n");
1392 }
1393
1394 if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
1395 printk(KERN_INFO "fusb300_ep0setup\n");
1396 if (setup_packet(fusb300, &ctrl)) {
1397 spin_unlock(&fusb300->lock);
1398 if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
1399 fusb300_set_cxstall(fusb300);
1400 spin_lock(&fusb300->lock);
1401 }
1402 }
1403
1404 if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
1405 printk(KERN_INFO "fusb300_cmdend\n");
1406
1407
1408 if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
1409 printk(KERN_INFO "fusb300_cxout\n");
1410 fusb300_ep0out(fusb300);
1411 }
1412
1413 if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
1414 printk(KERN_INFO "fusb300_cxin\n");
1415 fusb300_ep0in(fusb300);
1416 }
1417
1418 if (int_grp1 & FUSB300_IGR1_INTGRP5)
1419 fusb300_grp5_handler();
1420
1421 if (int_grp1 & FUSB300_IGR1_INTGRP4)
1422 fusb300_grp4_handler();
1423
1424 if (int_grp1 & FUSB300_IGR1_INTGRP3)
1425 fusb300_grp3_handler();
1426
1427 if (int_grp1 & FUSB300_IGR1_INTGRP2)
1428 fusb300_grp2_handler();
1429
1430 if (int_grp0) {
1431 for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
1432 if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
1433 reg = ioread32(fusb300->reg +
1434 FUSB300_OFFSET_EPSET1(i));
1435 in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
1436 if (in)
1437 in_ep_fifo_handler(fusb300->ep[i]);
1438 else
1439 out_ep_fifo_handler(fusb300->ep[i]);
1440 }
1441 }
1442 }
1443
1444 spin_unlock(&fusb300->lock);
1445
1446 return IRQ_HANDLED;
1447}
1448
1449static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
1450 u32 time)
1451{
1452 u32 reg;
1453
1454 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
1455 reg &= ~0xff;
1456 reg |= FUSB300_SSCR2_U2TIMEOUT(time);
1457
1458 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
1459}
1460
1461static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
1462 u32 time)
1463{
1464 u32 reg;
1465
1466 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
1467 reg &= ~(0xff << 8);
1468 reg |= FUSB300_SSCR2_U1TIMEOUT(time);
1469
1470 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
1471}
1472
1473static void init_controller(struct fusb300 *fusb300)
1474{
1475 u32 reg;
1476 u32 mask = 0;
1477 u32 val = 0;
1478
1479 /* split on */
1480 mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
1481 reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
1482 reg &= ~mask;
1483 reg |= val;
1484 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
1485
1486 /* enable high-speed LPM */
1487 mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
1488 reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
1489 reg &= ~mask;
1490 reg |= val;
1491 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
1492
1493 /*set u1 u2 timmer*/
1494 fusb300_set_u2_timeout(fusb300, 0xff);
1495 fusb300_set_u1_timeout(fusb300, 0xff);
1496
1497 /* enable all grp1 interrupt */
1498 iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
1499}
1500/*------------------------------------------------------------------------*/
1501static struct fusb300 *the_controller;
1502
1503int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1504 int (*bind)(struct usb_gadget *))
1505{
1506 struct fusb300 *fusb300 = the_controller;
1507 int retval;
1508
1509 if (!driver
1510 || driver->speed < USB_SPEED_FULL
1511 || !bind
1512 || !driver->setup)
1513 return -EINVAL;
1514
1515 if (!fusb300)
1516 return -ENODEV;
1517
1518 if (fusb300->driver)
1519 return -EBUSY;
1520
1521 /* hook up the driver */
1522 driver->driver.bus = NULL;
1523 fusb300->driver = driver;
1524 fusb300->gadget.dev.driver = &driver->driver;
1525
1526 retval = device_add(&fusb300->gadget.dev);
1527 if (retval) {
1528 pr_err("device_add error (%d)\n", retval);
1529 goto error;
1530 }
1531
1532 retval = bind(&fusb300->gadget);
1533 if (retval) {
1534 pr_err("bind to driver error (%d)\n", retval);
1535 device_del(&fusb300->gadget.dev);
1536 goto error;
1537 }
1538
1539 return 0;
1540
1541error:
1542 fusb300->driver = NULL;
1543 fusb300->gadget.dev.driver = NULL;
1544
1545 return retval;
1546}
1547EXPORT_SYMBOL(usb_gadget_probe_driver);
1548
1549int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1550{
1551 struct fusb300 *fusb300 = the_controller;
1552
1553 if (driver != fusb300->driver || !driver->unbind)
1554 return -EINVAL;
1555
1556 driver->unbind(&fusb300->gadget);
1557 fusb300->gadget.dev.driver = NULL;
1558
1559 init_controller(fusb300);
1560 device_del(&fusb300->gadget.dev);
1561 fusb300->driver = NULL;
1562
1563 return 0;
1564}
1565EXPORT_SYMBOL(usb_gadget_unregister_driver);
1566/*--------------------------------------------------------------------------*/
1567
1568static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
1569{
1570 return 0;
1571}
1572
1573static struct usb_gadget_ops fusb300_gadget_ops = {
1574 .pullup = fusb300_udc_pullup,
1575};
1576
1577static int __exit fusb300_remove(struct platform_device *pdev)
1578{
1579 struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev);
1580
1581 iounmap(fusb300->reg);
1582 free_irq(platform_get_irq(pdev, 0), fusb300);
1583
1584 fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
1585 kfree(fusb300);
1586
1587 return 0;
1588}
1589
1590static int __init fusb300_probe(struct platform_device *pdev)
1591{
1592 struct resource *res, *ires, *ires1;
1593 void __iomem *reg = NULL;
1594 struct fusb300 *fusb300 = NULL;
1595 struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
1596 int ret = 0;
1597 int i;
1598
1599 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1600 if (!res) {
1601 ret = -ENODEV;
1602 pr_err("platform_get_resource error.\n");
1603 goto clean_up;
1604 }
1605
1606 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1607 if (!ires) {
1608 ret = -ENODEV;
1609 dev_err(&pdev->dev,
1610 "platform_get_resource IORESOURCE_IRQ error.\n");
1611 goto clean_up;
1612 }
1613
1614 ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1615 if (!ires1) {
1616 ret = -ENODEV;
1617 dev_err(&pdev->dev,
1618 "platform_get_resource IORESOURCE_IRQ 1 error.\n");
1619 goto clean_up;
1620 }
1621
1622 reg = ioremap(res->start, resource_size(res));
1623 if (reg == NULL) {
1624 ret = -ENOMEM;
1625 pr_err("ioremap error.\n");
1626 goto clean_up;
1627 }
1628
1629 /* initialize udc */
1630 fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
1631 if (fusb300 == NULL) {
1632 pr_err("kzalloc error\n");
1633 goto clean_up;
1634 }
1635
1636 for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
1637 _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
1638 if (_ep[i] == NULL) {
1639 pr_err("_ep kzalloc error\n");
1640 goto clean_up;
1641 }
1642 fusb300->ep[i] = _ep[i];
1643 }
1644
1645 spin_lock_init(&fusb300->lock);
1646
1647 dev_set_drvdata(&pdev->dev, fusb300);
1648
1649 fusb300->gadget.ops = &fusb300_gadget_ops;
1650
1651 device_initialize(&fusb300->gadget.dev);
1652
1653 dev_set_name(&fusb300->gadget.dev, "gadget");
1654
1655 fusb300->gadget.is_dualspeed = 1;
1656 fusb300->gadget.dev.parent = &pdev->dev;
1657 fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
1658 fusb300->gadget.dev.release = pdev->dev.release;
1659 fusb300->gadget.name = udc_name;
1660 fusb300->reg = reg;
1661
1662 ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED,
1663 udc_name, fusb300);
1664 if (ret < 0) {
1665 pr_err("request_irq error (%d)\n", ret);
1666 goto clean_up;
1667 }
1668
1669 ret = request_irq(ires1->start, fusb300_irq,
1670 IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300);
1671 if (ret < 0) {
1672 pr_err("request_irq1 error (%d)\n", ret);
1673 goto clean_up;
1674 }
1675
1676 INIT_LIST_HEAD(&fusb300->gadget.ep_list);
1677
1678 for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
1679 struct fusb300_ep *ep = fusb300->ep[i];
1680
1681 if (i != 0) {
1682 INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
1683 list_add_tail(&fusb300->ep[i]->ep.ep_list,
1684 &fusb300->gadget.ep_list);
1685 }
1686 ep->fusb300 = fusb300;
1687 INIT_LIST_HEAD(&ep->queue);
1688 ep->ep.name = fusb300_ep_name[i];
1689 ep->ep.ops = &fusb300_ep_ops;
1690 ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE;
1691 }
1692 fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE;
1693 fusb300->ep[0]->epnum = 0;
1694 fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
1695 INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
1696
1697 the_controller = fusb300;
1698
1699 fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
1700 GFP_KERNEL);
1701 if (fusb300->ep0_req == NULL)
1702 goto clean_up3;
1703
1704 init_controller(fusb300);
1705 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1706
1707 return 0;
1708
1709clean_up3:
1710 free_irq(ires->start, fusb300);
1711
1712clean_up:
1713 if (fusb300) {
1714 if (fusb300->ep0_req)
1715 fusb300_free_request(&fusb300->ep[0]->ep,
1716 fusb300->ep0_req);
1717 kfree(fusb300);
1718 }
1719 if (reg)
1720 iounmap(reg);
1721
1722 return ret;
1723}
1724
1725static struct platform_driver fusb300_driver = {
1726 .remove = __exit_p(fusb300_remove),
1727 .driver = {
1728 .name = (char *) udc_name,
1729 .owner = THIS_MODULE,
1730 },
1731};
1732
1733static int __init fusb300_udc_init(void)
1734{
1735 return platform_driver_probe(&fusb300_driver, fusb300_probe);
1736}
1737
1738module_init(fusb300_udc_init);
1739
1740static void __exit fusb300_udc_cleanup(void)
1741{
1742 platform_driver_unregister(&fusb300_driver);
1743}
1744module_exit(fusb300_udc_cleanup);
diff --git a/drivers/usb/gadget/fusb300_udc.h b/drivers/usb/gadget/fusb300_udc.h
new file mode 100644
index 000000000000..f51aa2ef1f90
--- /dev/null
+++ b/drivers/usb/gadget/fusb300_udc.h
@@ -0,0 +1,687 @@
1/*
2 * Fusb300 UDC (USB gadget)
3 *
4 * Copyright (C) 2010 Faraday Technology Corp.
5 *
6 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23
24#ifndef __FUSB300_UDC_H__
25#define __FUSB300_UDC_H_
26
27#include <linux/kernel.h>
28
29#define FUSB300_OFFSET_GCR 0x00
30#define FUSB300_OFFSET_GTM 0x04
31#define FUSB300_OFFSET_DAR 0x08
32#define FUSB300_OFFSET_CSR 0x0C
33#define FUSB300_OFFSET_CXPORT 0x10
34#define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30)
35#define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30)
36#define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30)
37#define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30)
38#define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30)
39#define FUSB300_OFFSET_HSPTM 0x300
40#define FUSB300_OFFSET_HSCR 0x304
41#define FUSB300_OFFSET_SSCR0 0x308
42#define FUSB300_OFFSET_SSCR1 0x30C
43#define FUSB300_OFFSET_TT 0x310
44#define FUSB300_OFFSET_DEVNOTF 0x314
45#define FUSB300_OFFSET_DNC1 0x318
46#define FUSB300_OFFSET_CS 0x31C
47#define FUSB300_OFFSET_SOF 0x324
48#define FUSB300_OFFSET_EFCS 0x328
49#define FUSB300_OFFSET_IGR0 0x400
50#define FUSB300_OFFSET_IGR1 0x404
51#define FUSB300_OFFSET_IGR2 0x408
52#define FUSB300_OFFSET_IGR3 0x40C
53#define FUSB300_OFFSET_IGR4 0x410
54#define FUSB300_OFFSET_IGR5 0x414
55#define FUSB300_OFFSET_IGER0 0x420
56#define FUSB300_OFFSET_IGER1 0x424
57#define FUSB300_OFFSET_IGER2 0x428
58#define FUSB300_OFFSET_IGER3 0x42C
59#define FUSB300_OFFSET_IGER4 0x430
60#define FUSB300_OFFSET_IGER5 0x434
61#define FUSB300_OFFSET_DMAHMER 0x500
62#define FUSB300_OFFSET_EPPRDRDY 0x504
63#define FUSB300_OFFSET_DMAEPMR 0x508
64#define FUSB300_OFFSET_DMAENR 0x50C
65#define FUSB300_OFFSET_DMAAPR 0x510
66#define FUSB300_OFFSET_AHBCR 0x514
67#define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10)
68#define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10)
69#define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10)
70#define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10)
71#define FUSB300_OFFSET_BUFDBG_START 0x800
72#define FUSB300_OFFSET_BUFDBG_END 0xBFC
73#define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10)
74
75/*
76 * * Global Control Register (offset = 000H)
77 * */
78#define FUSB300_GCR_SF_RST (1 << 8)
79#define FUSB300_GCR_VBUS_STATUS (1 << 7)
80#define FUSB300_GCR_FORCE_HS_SUSP (1 << 6)
81#define FUSB300_GCR_SYNC_FIFO1_CLR (1 << 5)
82#define FUSB300_GCR_SYNC_FIFO0_CLR (1 << 4)
83#define FUSB300_GCR_FIFOCLR (1 << 3)
84#define FUSB300_GCR_GLINTEN (1 << 2)
85#define FUSB300_GCR_DEVEN_FS 0x3
86#define FUSB300_GCR_DEVEN_HS 0x2
87#define FUSB300_GCR_DEVEN_SS 0x1
88#define FUSB300_GCR_DEVDIS 0x0
89#define FUSB300_GCR_DEVEN_MSK 0x3
90
91
92/*
93 * *Global Test Mode (offset = 004H)
94 * */
95#define FUSB300_GTM_TST_DIS_SOFGEN (1 << 16)
96#define FUSB300_GTM_TST_CUR_EP_ENTRY(n) ((n & 0xF) << 12)
97#define FUSB300_GTM_TST_EP_ENTRY(n) ((n & 0xF) << 8)
98#define FUSB300_GTM_TST_EP_NUM(n) ((n & 0xF) << 4)
99#define FUSB300_GTM_TST_FIFO_DEG (1 << 1)
100#define FUSB300_GTM_TSTMODE (1 << 0)
101
102/*
103 * * Device Address Register (offset = 008H)
104 * */
105#define FUSB300_DAR_SETCONFG (1 << 7)
106#define FUSB300_DAR_DRVADDR(x) (x & 0x7F)
107#define FUSB300_DAR_DRVADDR_MSK 0x7F
108
109/*
110 * *Control Transfer Configuration and Status Register
111 * (CX_Config_Status, offset = 00CH)
112 * */
113#define FUSB300_CSR_LEN(x) ((x & 0xFFFF) << 8)
114#define FUSB300_CSR_LEN_MSK (0xFFFF << 8)
115#define FUSB300_CSR_EMP (1 << 4)
116#define FUSB300_CSR_FUL (1 << 3)
117#define FUSB300_CSR_CLR (1 << 2)
118#define FUSB300_CSR_STL (1 << 1)
119#define FUSB300_CSR_DONE (1 << 0)
120
121/*
122 * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 )
123 * */
124#define FUSB300_EPSET0_CLRSEQNUM (1 << 2)
125#define FUSB300_EPSET0_EPn_TX0BYTE (1 << 1)
126#define FUSB300_EPSET0_STL (1 << 0)
127
128/*
129 * * EPn Setting 1 (EPn_SET1, offset = 024H+(n-1)*30H, n=1~15)
130 * */
131#define FUSB300_EPSET1_START_ENTRY(x) ((x & 0xFF) << 24)
132#define FUSB300_EPSET1_START_ENTRY_MSK (0xFF << 24)
133#define FUSB300_EPSET1_FIFOENTRY(x) ((x & 0x1F) << 12)
134#define FUSB300_EPSET1_FIFOENTRY_MSK (0x1f << 12)
135#define FUSB300_EPSET1_INTERVAL(x) ((x & 0x7) << 6)
136#define FUSB300_EPSET1_BWNUM(x) ((x & 0x3) << 4)
137#define FUSB300_EPSET1_TYPEISO (1 << 2)
138#define FUSB300_EPSET1_TYPEBLK (2 << 2)
139#define FUSB300_EPSET1_TYPEINT (3 << 2)
140#define FUSB300_EPSET1_TYPE(x) ((x & 0x3) << 2)
141#define FUSB300_EPSET1_TYPE_MSK (0x3 << 2)
142#define FUSB300_EPSET1_DIROUT (0 << 1)
143#define FUSB300_EPSET1_DIRIN (1 << 1)
144#define FUSB300_EPSET1_DIR(x) ((x & 0x1) << 1)
145#define FUSB300_EPSET1_DIRIN (1 << 1)
146#define FUSB300_EPSET1_DIR_MSK ((0x1) << 1)
147#define FUSB300_EPSET1_ACTDIS 0
148#define FUSB300_EPSET1_ACTEN 1
149
150/*
151 * *EPn Setting 2 (EPn_SET2, offset = 028H+(n-1)*30H, n=1~15)
152 * */
153#define FUSB300_EPSET2_ADDROFS(x) ((x & 0x7FFF) << 16)
154#define FUSB300_EPSET2_ADDROFS_MSK (0x7fff << 16)
155#define FUSB300_EPSET2_MPS(x) (x & 0x7FF)
156#define FUSB300_EPSET2_MPS_MSK 0x7FF
157
158/*
159 * * EPn FIFO Register (offset = 2cH+(n-1)*30H)
160 * */
161#define FUSB300_FFR_RST (1 << 31)
162#define FUSB300_FF_FUL (1 << 30)
163#define FUSB300_FF_EMPTY (1 << 29)
164#define FUSB300_FFR_BYCNT 0x1FFFF
165
166/*
167 * *EPn Stream ID (EPn_STR_ID, offset = 040H+(n-1)*30H, n=1~15)
168 * */
169#define FUSB300_STRID_STREN (1 << 16)
170#define FUSB300_STRID_STRID(x) (x & 0xFFFF)
171
172/*
173 * *HS PHY Test Mode (offset = 300H)
174 * */
175#define FUSB300_HSPTM_TSTPKDONE (1 << 4)
176#define FUSB300_HSPTM_TSTPKT (1 << 3)
177#define FUSB300_HSPTM_TSTSET0NAK (1 << 2)
178#define FUSB300_HSPTM_TSTKSTA (1 << 1)
179#define FUSB300_HSPTM_TSTJSTA (1 << 0)
180
181/*
182 * *HS Control Register (offset = 304H)
183 * */
184#define FUSB300_HSCR_HS_LPM_PERMIT (1 << 8)
185#define FUSB300_HSCR_HS_LPM_RMWKUP (1 << 7)
186#define FUSB300_HSCR_CAP_LPM_RMWKUP (1 << 6)
187#define FUSB300_HSCR_HS_GOSUSP (1 << 5)
188#define FUSB300_HSCR_HS_GORMWKU (1 << 4)
189#define FUSB300_HSCR_CAP_RMWKUP (1 << 3)
190#define FUSB300_HSCR_IDLECNT_0MS 0
191#define FUSB300_HSCR_IDLECNT_1MS 1
192#define FUSB300_HSCR_IDLECNT_2MS 2
193#define FUSB300_HSCR_IDLECNT_3MS 3
194#define FUSB300_HSCR_IDLECNT_4MS 4
195#define FUSB300_HSCR_IDLECNT_5MS 5
196#define FUSB300_HSCR_IDLECNT_6MS 6
197#define FUSB300_HSCR_IDLECNT_7MS 7
198
199/*
200 * * SS Controller Register 0 (offset = 308H)
201 * */
202#define FUSB300_SSCR0_MAX_INTERVAL(x) ((x & 0x7) << 4)
203#define FUSB300_SSCR0_U2_FUN_EN (1 << 1)
204#define FUSB300_SSCR0_U1_FUN_EN (1 << 0)
205
206/*
207 * * SS Controller Register 1 (offset = 30CH)
208 * */
209#define FUSB300_SSCR1_GO_U3_DONE (1 << 8)
210#define FUSB300_SSCR1_TXDEEMPH_LEVEL (1 << 7)
211#define FUSB300_SSCR1_DIS_SCRMB (1 << 6)
212#define FUSB300_SSCR1_FORCE_RECOVERY (1 << 5)
213#define FUSB300_SSCR1_U3_WAKEUP_EN (1 << 4)
214#define FUSB300_SSCR1_U2_EXIT_EN (1 << 3)
215#define FUSB300_SSCR1_U1_EXIT_EN (1 << 2)
216#define FUSB300_SSCR1_U2_ENTRY_EN (1 << 1)
217#define FUSB300_SSCR1_U1_ENTRY_EN (1 << 0)
218
219/*
220 * *SS Controller Register 2 (offset = 310H)
221 * */
222#define FUSB300_SSCR2_SS_TX_SWING (1 << 25)
223#define FUSB300_SSCR2_FORCE_LINKPM_ACCEPT (1 << 24)
224#define FUSB300_SSCR2_U2_INACT_TIMEOUT(x) ((x & 0xFF) << 16)
225#define FUSB300_SSCR2_U1TIMEOUT(x) ((x & 0xFF) << 8)
226#define FUSB300_SSCR2_U2TIMEOUT(x) (x & 0xFF)
227
228/*
229 * *SS Device Notification Control (DEV_NOTF, offset = 314H)
230 * */
231#define FUSB300_DEVNOTF_CONTEXT0(x) ((x & 0xFFFFFF) << 8)
232#define FUSB300_DEVNOTF_TYPE_DIS 0
233#define FUSB300_DEVNOTF_TYPE_FUNCWAKE 1
234#define FUSB300_DEVNOTF_TYPE_LTM 2
235#define FUSB300_DEVNOTF_TYPE_BUSINT_ADJMSG 3
236
237/*
238 * *BFM Arbiter Priority Register (BFM_ARB offset = 31CH)
239 * */
240#define FUSB300_BFMARB_ARB_M1 (1 << 3)
241#define FUSB300_BFMARB_ARB_M0 (1 << 2)
242#define FUSB300_BFMARB_ARB_S1 (1 << 1)
243#define FUSB300_BFMARB_ARB_S0 1
244
245/*
246 * *Vendor Specific IO Control Register (offset = 320H)
247 * */
248#define FUSB300_VSIC_VCTLOAD_N (1 << 8)
249#define FUSB300_VSIC_VCTL(x) (x & 0x3F)
250
251/*
252 * *SOF Mask Timer (offset = 324H)
253 * */
254#define FUSB300_SOF_MASK_TIMER_HS 0x044c
255#define FUSB300_SOF_MASK_TIMER_FS 0x2710
256
257/*
258 * *Error Flag and Control Status (offset = 328H)
259 * */
260#define FUSB300_EFCS_PM_STATE_U3 3
261#define FUSB300_EFCS_PM_STATE_U2 2
262#define FUSB300_EFCS_PM_STATE_U1 1
263#define FUSB300_EFCS_PM_STATE_U0 0
264
265/*
266 * *Interrupt Group 0 Register (offset = 400H)
267 * */
268#define FUSB300_IGR0_EP15_PRD_INT (1 << 31)
269#define FUSB300_IGR0_EP14_PRD_INT (1 << 30)
270#define FUSB300_IGR0_EP13_PRD_INT (1 << 29)
271#define FUSB300_IGR0_EP12_PRD_INT (1 << 28)
272#define FUSB300_IGR0_EP11_PRD_INT (1 << 27)
273#define FUSB300_IGR0_EP10_PRD_INT (1 << 26)
274#define FUSB300_IGR0_EP9_PRD_INT (1 << 25)
275#define FUSB300_IGR0_EP8_PRD_INT (1 << 24)
276#define FUSB300_IGR0_EP7_PRD_INT (1 << 23)
277#define FUSB300_IGR0_EP6_PRD_INT (1 << 22)
278#define FUSB300_IGR0_EP5_PRD_INT (1 << 21)
279#define FUSB300_IGR0_EP4_PRD_INT (1 << 20)
280#define FUSB300_IGR0_EP3_PRD_INT (1 << 19)
281#define FUSB300_IGR0_EP2_PRD_INT (1 << 18)
282#define FUSB300_IGR0_EP1_PRD_INT (1 << 17)
283#define FUSB300_IGR0_EPn_PRD_INT(n) (1 << (n + 16))
284
285#define FUSB300_IGR0_EP15_FIFO_INT (1 << 15)
286#define FUSB300_IGR0_EP14_FIFO_INT (1 << 14)
287#define FUSB300_IGR0_EP13_FIFO_INT (1 << 13)
288#define FUSB300_IGR0_EP12_FIFO_INT (1 << 12)
289#define FUSB300_IGR0_EP11_FIFO_INT (1 << 11)
290#define FUSB300_IGR0_EP10_FIFO_INT (1 << 10)
291#define FUSB300_IGR0_EP9_FIFO_INT (1 << 9)
292#define FUSB300_IGR0_EP8_FIFO_INT (1 << 8)
293#define FUSB300_IGR0_EP7_FIFO_INT (1 << 7)
294#define FUSB300_IGR0_EP6_FIFO_INT (1 << 6)
295#define FUSB300_IGR0_EP5_FIFO_INT (1 << 5)
296#define FUSB300_IGR0_EP4_FIFO_INT (1 << 4)
297#define FUSB300_IGR0_EP3_FIFO_INT (1 << 3)
298#define FUSB300_IGR0_EP2_FIFO_INT (1 << 2)
299#define FUSB300_IGR0_EP1_FIFO_INT (1 << 1)
300#define FUSB300_IGR0_EPn_FIFO_INT(n) (1 << n)
301
302/*
303 * *Interrupt Group 1 Register (offset = 404H)
304 * */
305#define FUSB300_IGR1_INTGRP5 (1 << 31)
306#define FUSB300_IGR1_VBUS_CHG_INT (1 << 30)
307#define FUSB300_IGR1_SYNF1_EMPTY_INT (1 << 29)
308#define FUSB300_IGR1_SYNF0_EMPTY_INT (1 << 28)
309#define FUSB300_IGR1_U3_EXIT_FAIL_INT (1 << 27)
310#define FUSB300_IGR1_U2_EXIT_FAIL_INT (1 << 26)
311#define FUSB300_IGR1_U1_EXIT_FAIL_INT (1 << 25)
312#define FUSB300_IGR1_U2_ENTRY_FAIL_INT (1 << 24)
313#define FUSB300_IGR1_U1_ENTRY_FAIL_INT (1 << 23)
314#define FUSB300_IGR1_U3_EXIT_INT (1 << 22)
315#define FUSB300_IGR1_U2_EXIT_INT (1 << 21)
316#define FUSB300_IGR1_U1_EXIT_INT (1 << 20)
317#define FUSB300_IGR1_U3_ENTRY_INT (1 << 19)
318#define FUSB300_IGR1_U2_ENTRY_INT (1 << 18)
319#define FUSB300_IGR1_U1_ENTRY_INT (1 << 17)
320#define FUSB300_IGR1_HOT_RST_INT (1 << 16)
321#define FUSB300_IGR1_WARM_RST_INT (1 << 15)
322#define FUSB300_IGR1_RESM_INT (1 << 14)
323#define FUSB300_IGR1_SUSP_INT (1 << 13)
324#define FUSB300_IGR1_HS_LPM_INT (1 << 12)
325#define FUSB300_IGR1_USBRST_INT (1 << 11)
326#define FUSB300_IGR1_DEV_MODE_CHG_INT (1 << 9)
327#define FUSB300_IGR1_CX_COMABT_INT (1 << 8)
328#define FUSB300_IGR1_CX_COMFAIL_INT (1 << 7)
329#define FUSB300_IGR1_CX_CMDEND_INT (1 << 6)
330#define FUSB300_IGR1_CX_OUT_INT (1 << 5)
331#define FUSB300_IGR1_CX_IN_INT (1 << 4)
332#define FUSB300_IGR1_CX_SETUP_INT (1 << 3)
333#define FUSB300_IGR1_INTGRP4 (1 << 2)
334#define FUSB300_IGR1_INTGRP3 (1 << 1)
335#define FUSB300_IGR1_INTGRP2 (1 << 0)
336
337/*
338 * *Interrupt Group 2 Register (offset = 408H)
339 * */
340#define FUSB300_IGR2_EP6_STR_ACCEPT_INT (1 << 29)
341#define FUSB300_IGR2_EP6_STR_RESUME_INT (1 << 28)
342#define FUSB300_IGR2_EP6_STR_REQ_INT (1 << 27)
343#define FUSB300_IGR2_EP6_STR_NOTRDY_INT (1 << 26)
344#define FUSB300_IGR2_EP6_STR_PRIME_INT (1 << 25)
345#define FUSB300_IGR2_EP5_STR_ACCEPT_INT (1 << 24)
346#define FUSB300_IGR2_EP5_STR_RESUME_INT (1 << 23)
347#define FUSB300_IGR2_EP5_STR_REQ_INT (1 << 22)
348#define FUSB300_IGR2_EP5_STR_NOTRDY_INT (1 << 21)
349#define FUSB300_IGR2_EP5_STR_PRIME_INT (1 << 20)
350#define FUSB300_IGR2_EP4_STR_ACCEPT_INT (1 << 19)
351#define FUSB300_IGR2_EP4_STR_RESUME_INT (1 << 18)
352#define FUSB300_IGR2_EP4_STR_REQ_INT (1 << 17)
353#define FUSB300_IGR2_EP4_STR_NOTRDY_INT (1 << 16)
354#define FUSB300_IGR2_EP4_STR_PRIME_INT (1 << 15)
355#define FUSB300_IGR2_EP3_STR_ACCEPT_INT (1 << 14)
356#define FUSB300_IGR2_EP3_STR_RESUME_INT (1 << 13)
357#define FUSB300_IGR2_EP3_STR_REQ_INT (1 << 12)
358#define FUSB300_IGR2_EP3_STR_NOTRDY_INT (1 << 11)
359#define FUSB300_IGR2_EP3_STR_PRIME_INT (1 << 10)
360#define FUSB300_IGR2_EP2_STR_ACCEPT_INT (1 << 9)
361#define FUSB300_IGR2_EP2_STR_RESUME_INT (1 << 8)
362#define FUSB300_IGR2_EP2_STR_REQ_INT (1 << 7)
363#define FUSB300_IGR2_EP2_STR_NOTRDY_INT (1 << 6)
364#define FUSB300_IGR2_EP2_STR_PRIME_INT (1 << 5)
365#define FUSB300_IGR2_EP1_STR_ACCEPT_INT (1 << 4)
366#define FUSB300_IGR2_EP1_STR_RESUME_INT (1 << 3)
367#define FUSB300_IGR2_EP1_STR_REQ_INT (1 << 2)
368#define FUSB300_IGR2_EP1_STR_NOTRDY_INT (1 << 1)
369#define FUSB300_IGR2_EP1_STR_PRIME_INT (1 << 0)
370
371#define FUSB300_IGR2_EP_STR_ACCEPT_INT(n) (1 << (5 * n - 1))
372#define FUSB300_IGR2_EP_STR_RESUME_INT(n) (1 << (5 * n - 2))
373#define FUSB300_IGR2_EP_STR_REQ_INT(n) (1 << (5 * n - 3))
374#define FUSB300_IGR2_EP_STR_NOTRDY_INT(n) (1 << (5 * n - 4))
375#define FUSB300_IGR2_EP_STR_PRIME_INT(n) (1 << (5 * n - 5))
376
377/*
378 * *Interrupt Group 3 Register (offset = 40CH)
379 * */
380#define FUSB300_IGR3_EP12_STR_ACCEPT_INT (1 << 29)
381#define FUSB300_IGR3_EP12_STR_RESUME_INT (1 << 28)
382#define FUSB300_IGR3_EP12_STR_REQ_INT (1 << 27)
383#define FUSB300_IGR3_EP12_STR_NOTRDY_INT (1 << 26)
384#define FUSB300_IGR3_EP12_STR_PRIME_INT (1 << 25)
385#define FUSB300_IGR3_EP11_STR_ACCEPT_INT (1 << 24)
386#define FUSB300_IGR3_EP11_STR_RESUME_INT (1 << 23)
387#define FUSB300_IGR3_EP11_STR_REQ_INT (1 << 22)
388#define FUSB300_IGR3_EP11_STR_NOTRDY_INT (1 << 21)
389#define FUSB300_IGR3_EP11_STR_PRIME_INT (1 << 20)
390#define FUSB300_IGR3_EP10_STR_ACCEPT_INT (1 << 19)
391#define FUSB300_IGR3_EP10_STR_RESUME_INT (1 << 18)
392#define FUSB300_IGR3_EP10_STR_REQ_INT (1 << 17)
393#define FUSB300_IGR3_EP10_STR_NOTRDY_INT (1 << 16)
394#define FUSB300_IGR3_EP10_STR_PRIME_INT (1 << 15)
395#define FUSB300_IGR3_EP9_STR_ACCEPT_INT (1 << 14)
396#define FUSB300_IGR3_EP9_STR_RESUME_INT (1 << 13)
397#define FUSB300_IGR3_EP9_STR_REQ_INT (1 << 12)
398#define FUSB300_IGR3_EP9_STR_NOTRDY_INT (1 << 11)
399#define FUSB300_IGR3_EP9_STR_PRIME_INT (1 << 10)
400#define FUSB300_IGR3_EP8_STR_ACCEPT_INT (1 << 9)
401#define FUSB300_IGR3_EP8_STR_RESUME_INT (1 << 8)
402#define FUSB300_IGR3_EP8_STR_REQ_INT (1 << 7)
403#define FUSB300_IGR3_EP8_STR_NOTRDY_INT (1 << 6)
404#define FUSB300_IGR3_EP8_STR_PRIME_INT (1 << 5)
405#define FUSB300_IGR3_EP7_STR_ACCEPT_INT (1 << 4)
406#define FUSB300_IGR3_EP7_STR_RESUME_INT (1 << 3)
407#define FUSB300_IGR3_EP7_STR_REQ_INT (1 << 2)
408#define FUSB300_IGR3_EP7_STR_NOTRDY_INT (1 << 1)
409#define FUSB300_IGR3_EP7_STR_PRIME_INT (1 << 0)
410
411#define FUSB300_IGR3_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
412#define FUSB300_IGR3_EP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
413#define FUSB300_IGR3_EP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
414#define FUSB300_IGR3_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
415#define FUSB300_IGR3_EP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
416
417/*
418 * *Interrupt Group 4 Register (offset = 410H)
419 * */
420#define FUSB300_IGR4_EP15_RX0_INT (1 << 31)
421#define FUSB300_IGR4_EP14_RX0_INT (1 << 30)
422#define FUSB300_IGR4_EP13_RX0_INT (1 << 29)
423#define FUSB300_IGR4_EP12_RX0_INT (1 << 28)
424#define FUSB300_IGR4_EP11_RX0_INT (1 << 27)
425#define FUSB300_IGR4_EP10_RX0_INT (1 << 26)
426#define FUSB300_IGR4_EP9_RX0_INT (1 << 25)
427#define FUSB300_IGR4_EP8_RX0_INT (1 << 24)
428#define FUSB300_IGR4_EP7_RX0_INT (1 << 23)
429#define FUSB300_IGR4_EP6_RX0_INT (1 << 22)
430#define FUSB300_IGR4_EP5_RX0_INT (1 << 21)
431#define FUSB300_IGR4_EP4_RX0_INT (1 << 20)
432#define FUSB300_IGR4_EP3_RX0_INT (1 << 19)
433#define FUSB300_IGR4_EP2_RX0_INT (1 << 18)
434#define FUSB300_IGR4_EP1_RX0_INT (1 << 17)
435#define FUSB300_IGR4_EP_RX0_INT(x) (1 << (x + 16))
436#define FUSB300_IGR4_EP15_STR_ACCEPT_INT (1 << 14)
437#define FUSB300_IGR4_EP15_STR_RESUME_INT (1 << 13)
438#define FUSB300_IGR4_EP15_STR_REQ_INT (1 << 12)
439#define FUSB300_IGR4_EP15_STR_NOTRDY_INT (1 << 11)
440#define FUSB300_IGR4_EP15_STR_PRIME_INT (1 << 10)
441#define FUSB300_IGR4_EP14_STR_ACCEPT_INT (1 << 9)
442#define FUSB300_IGR4_EP14_STR_RESUME_INT (1 << 8)
443#define FUSB300_IGR4_EP14_STR_REQ_INT (1 << 7)
444#define FUSB300_IGR4_EP14_STR_NOTRDY_INT (1 << 6)
445#define FUSB300_IGR4_EP14_STR_PRIME_INT (1 << 5)
446#define FUSB300_IGR4_EP13_STR_ACCEPT_INT (1 << 4)
447#define FUSB300_IGR4_EP13_STR_RESUME_INT (1 << 3)
448#define FUSB300_IGR4_EP13_STR_REQ_INT (1 << 2)
449#define FUSB300_IGR4_EP13_STR_NOTRDY_INT (1 << 1)
450#define FUSB300_IGR4_EP13_STR_PRIME_INT (1 << 0)
451
452#define FUSB300_IGR4_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 12) - 1))
453#define FUSB300_IGR4_EP_STR_RESUME_INT(n) (1 << (5 * (n - 12) - 2))
454#define FUSB300_IGR4_EP_STR_REQ_INT(n) (1 << (5 * (n - 12) - 3))
455#define FUSB300_IGR4_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 12) - 4))
456#define FUSB300_IGR4_EP_STR_PRIME_INT(n) (1 << (5 * (n - 12) - 5))
457
458/*
459 * *Interrupt Group 5 Register (offset = 414H)
460 * */
461#define FUSB300_IGR5_EP_STL_INT(n) (1 << n)
462
463/*
464 * *Interrupt Enable Group 0 Register (offset = 420H)
465 * */
466#define FUSB300_IGER0_EEP15_PRD_INT (1 << 31)
467#define FUSB300_IGER0_EEP14_PRD_INT (1 << 30)
468#define FUSB300_IGER0_EEP13_PRD_INT (1 << 29)
469#define FUSB300_IGER0_EEP12_PRD_INT (1 << 28)
470#define FUSB300_IGER0_EEP11_PRD_INT (1 << 27)
471#define FUSB300_IGER0_EEP10_PRD_INT (1 << 26)
472#define FUSB300_IGER0_EEP9_PRD_INT (1 << 25)
473#define FUSB300_IGER0_EP8_PRD_INT (1 << 24)
474#define FUSB300_IGER0_EEP7_PRD_INT (1 << 23)
475#define FUSB300_IGER0_EEP6_PRD_INT (1 << 22)
476#define FUSB300_IGER0_EEP5_PRD_INT (1 << 21)
477#define FUSB300_IGER0_EEP4_PRD_INT (1 << 20)
478#define FUSB300_IGER0_EEP3_PRD_INT (1 << 19)
479#define FUSB300_IGER0_EEP2_PRD_INT (1 << 18)
480#define FUSB300_IGER0_EEP1_PRD_INT (1 << 17)
481#define FUSB300_IGER0_EEPn_PRD_INT(n) (1 << (n + 16))
482
483#define FUSB300_IGER0_EEP15_FIFO_INT (1 << 15)
484#define FUSB300_IGER0_EEP14_FIFO_INT (1 << 14)
485#define FUSB300_IGER0_EEP13_FIFO_INT (1 << 13)
486#define FUSB300_IGER0_EEP12_FIFO_INT (1 << 12)
487#define FUSB300_IGER0_EEP11_FIFO_INT (1 << 11)
488#define FUSB300_IGER0_EEP10_FIFO_INT (1 << 10)
489#define FUSB300_IGER0_EEP9_FIFO_INT (1 << 9)
490#define FUSB300_IGER0_EEP8_FIFO_INT (1 << 8)
491#define FUSB300_IGER0_EEP7_FIFO_INT (1 << 7)
492#define FUSB300_IGER0_EEP6_FIFO_INT (1 << 6)
493#define FUSB300_IGER0_EEP5_FIFO_INT (1 << 5)
494#define FUSB300_IGER0_EEP4_FIFO_INT (1 << 4)
495#define FUSB300_IGER0_EEP3_FIFO_INT (1 << 3)
496#define FUSB300_IGER0_EEP2_FIFO_INT (1 << 2)
497#define FUSB300_IGER0_EEP1_FIFO_INT (1 << 1)
498#define FUSB300_IGER0_EEPn_FIFO_INT(n) (1 << n)
499
500/*
501 * *Interrupt Enable Group 1 Register (offset = 424H)
502 * */
503#define FUSB300_IGER1_EINT_GRP5 (1 << 31)
504#define FUSB300_IGER1_VBUS_CHG_INT (1 << 30)
505#define FUSB300_IGER1_SYNF1_EMPTY_INT (1 << 29)
506#define FUSB300_IGER1_SYNF0_EMPTY_INT (1 << 28)
507#define FUSB300_IGER1_U3_EXIT_FAIL_INT (1 << 27)
508#define FUSB300_IGER1_U2_EXIT_FAIL_INT (1 << 26)
509#define FUSB300_IGER1_U1_EXIT_FAIL_INT (1 << 25)
510#define FUSB300_IGER1_U2_ENTRY_FAIL_INT (1 << 24)
511#define FUSB300_IGER1_U1_ENTRY_FAIL_INT (1 << 23)
512#define FUSB300_IGER1_U3_EXIT_INT (1 << 22)
513#define FUSB300_IGER1_U2_EXIT_INT (1 << 21)
514#define FUSB300_IGER1_U1_EXIT_INT (1 << 20)
515#define FUSB300_IGER1_U3_ENTRY_INT (1 << 19)
516#define FUSB300_IGER1_U2_ENTRY_INT (1 << 18)
517#define FUSB300_IGER1_U1_ENTRY_INT (1 << 17)
518#define FUSB300_IGER1_HOT_RST_INT (1 << 16)
519#define FUSB300_IGER1_WARM_RST_INT (1 << 15)
520#define FUSB300_IGER1_RESM_INT (1 << 14)
521#define FUSB300_IGER1_SUSP_INT (1 << 13)
522#define FUSB300_IGER1_LPM_INT (1 << 12)
523#define FUSB300_IGER1_HS_RST_INT (1 << 11)
524#define FUSB300_IGER1_EDEV_MODE_CHG_INT (1 << 9)
525#define FUSB300_IGER1_CX_COMABT_INT (1 << 8)
526#define FUSB300_IGER1_CX_COMFAIL_INT (1 << 7)
527#define FUSB300_IGER1_CX_CMDEND_INT (1 << 6)
528#define FUSB300_IGER1_CX_OUT_INT (1 << 5)
529#define FUSB300_IGER1_CX_IN_INT (1 << 4)
530#define FUSB300_IGER1_CX_SETUP_INT (1 << 3)
531#define FUSB300_IGER1_INTGRP4 (1 << 2)
532#define FUSB300_IGER1_INTGRP3 (1 << 1)
533#define FUSB300_IGER1_INTGRP2 (1 << 0)
534
535/*
536 * *Interrupt Enable Group 2 Register (offset = 428H)
537 * */
538#define FUSB300_IGER2_EEP_STR_ACCEPT_INT(n) (1 << (5 * n - 1))
539#define FUSB300_IGER2_EEP_STR_RESUME_INT(n) (1 << (5 * n - 2))
540#define FUSB300_IGER2_EEP_STR_REQ_INT(n) (1 << (5 * n - 3))
541#define FUSB300_IGER2_EEP_STR_NOTRDY_INT(n) (1 << (5 * n - 4))
542#define FUSB300_IGER2_EEP_STR_PRIME_INT(n) (1 << (5 * n - 5))
543
544/*
545 * *Interrupt Enable Group 3 Register (offset = 42CH)
546 * */
547
548#define FUSB300_IGER3_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
549#define FUSB300_IGER3_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
550#define FUSB300_IGER3_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
551#define FUSB300_IGER3_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
552#define FUSB300_IGER3_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
553
554/*
555 * *Interrupt Enable Group 4 Register (offset = 430H)
556 * */
557
558#define FUSB300_IGER4_EEP_RX0_INT(n) (1 << (n + 16))
559#define FUSB300_IGER4_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
560#define FUSB300_IGER4_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
561#define FUSB300_IGER4_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
562#define FUSB300_IGER4_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
563#define FUSB300_IGER4_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
564
565/* EP PRD Ready (EP_PRD_RDY, offset = 504H) */
566
567#define FUSB300_EPPRDR_EP15_PRD_RDY (1 << 15)
568#define FUSB300_EPPRDR_EP14_PRD_RDY (1 << 14)
569#define FUSB300_EPPRDR_EP13_PRD_RDY (1 << 13)
570#define FUSB300_EPPRDR_EP12_PRD_RDY (1 << 12)
571#define FUSB300_EPPRDR_EP11_PRD_RDY (1 << 11)
572#define FUSB300_EPPRDR_EP10_PRD_RDY (1 << 10)
573#define FUSB300_EPPRDR_EP9_PRD_RDY (1 << 9)
574#define FUSB300_EPPRDR_EP8_PRD_RDY (1 << 8)
575#define FUSB300_EPPRDR_EP7_PRD_RDY (1 << 7)
576#define FUSB300_EPPRDR_EP6_PRD_RDY (1 << 6)
577#define FUSB300_EPPRDR_EP5_PRD_RDY (1 << 5)
578#define FUSB300_EPPRDR_EP4_PRD_RDY (1 << 4)
579#define FUSB300_EPPRDR_EP3_PRD_RDY (1 << 3)
580#define FUSB300_EPPRDR_EP2_PRD_RDY (1 << 2)
581#define FUSB300_EPPRDR_EP1_PRD_RDY (1 << 1)
582#define FUSB300_EPPRDR_EP_PRD_RDY(n) (1 << n)
583
584/* AHB Bus Control Register (offset = 514H) */
585#define FUSB300_AHBBCR_S1_SPLIT_ON (1 << 17)
586#define FUSB300_AHBBCR_S0_SPLIT_ON (1 << 16)
587#define FUSB300_AHBBCR_S1_1entry (0 << 12)
588#define FUSB300_AHBBCR_S1_4entry (3 << 12)
589#define FUSB300_AHBBCR_S1_8entry (5 << 12)
590#define FUSB300_AHBBCR_S1_16entry (7 << 12)
591#define FUSB300_AHBBCR_S0_1entry (0 << 8)
592#define FUSB300_AHBBCR_S0_4entry (3 << 8)
593#define FUSB300_AHBBCR_S0_8entry (5 << 8)
594#define FUSB300_AHBBCR_S0_16entry (7 << 8)
595#define FUSB300_AHBBCR_M1_BURST_SINGLE (0 << 4)
596#define FUSB300_AHBBCR_M1_BURST_INCR (1 << 4)
597#define FUSB300_AHBBCR_M1_BURST_INCR4 (3 << 4)
598#define FUSB300_AHBBCR_M1_BURST_INCR8 (5 << 4)
599#define FUSB300_AHBBCR_M1_BURST_INCR16 (7 << 4)
600#define FUSB300_AHBBCR_M0_BURST_SINGLE 0
601#define FUSB300_AHBBCR_M0_BURST_INCR 1
602#define FUSB300_AHBBCR_M0_BURST_INCR4 3
603#define FUSB300_AHBBCR_M0_BURST_INCR8 5
604#define FUSB300_AHBBCR_M0_BURST_INCR16 7
605#define FUSB300_IGER5_EEP_STL_INT(n) (1 << n)
606
607/* WORD 0 Data Structure of PRD Table */
608#define FUSB300_EPPRD0_M (1 << 30)
609#define FUSB300_EPPRD0_O (1 << 29)
610/* The finished prd */
611#define FUSB300_EPPRD0_F (1 << 28)
612#define FUSB300_EPPRD0_I (1 << 27)
613#define FUSB300_EPPRD0_A (1 << 26)
614/* To decide HW point to first prd at next time */
615#define FUSB300_EPPRD0_L (1 << 25)
616#define FUSB300_EPPRD0_H (1 << 24)
617#define FUSB300_EPPRD0_BTC(n) (n & 0xFFFFFF)
618
619/*----------------------------------------------------------------------*/
620#define FUSB300_MAX_NUM_EP 16
621
622#define FUSB300_FIFO_ENTRY_NUM 8
623#define FUSB300_MAX_FIFO_ENTRY 8
624
625#define SS_CTL_MAX_PACKET_SIZE 0x200
626#define SS_BULK_MAX_PACKET_SIZE 0x400
627#define SS_INT_MAX_PACKET_SIZE 0x400
628#define SS_ISO_MAX_PACKET_SIZE 0x400
629
630#define HS_BULK_MAX_PACKET_SIZE 0x200
631#define HS_CTL_MAX_PACKET_SIZE 0x40
632#define HS_INT_MAX_PACKET_SIZE 0x400
633#define HS_ISO_MAX_PACKET_SIZE 0x400
634
635struct fusb300_ep_info {
636 u8 epnum;
637 u8 type;
638 u8 interval;
639 u8 dir_in;
640 u16 maxpacket;
641 u16 addrofs;
642 u16 bw_num;
643};
644
645struct fusb300_request {
646
647 struct usb_request req;
648 struct list_head queue;
649};
650
651
652struct fusb300_ep {
653 struct usb_ep ep;
654 struct fusb300 *fusb300;
655
656 struct list_head queue;
657 unsigned stall:1;
658 unsigned wedged:1;
659 unsigned use_dma:1;
660
661 unsigned char epnum;
662 unsigned char type;
663 const struct usb_endpoint_descriptor *desc;
664};
665
666struct fusb300 {
667 spinlock_t lock;
668 void __iomem *reg;
669
670 unsigned long irq_trigger;
671
672 struct usb_gadget gadget;
673 struct usb_gadget_driver *driver;
674
675 struct fusb300_ep *ep[FUSB300_MAX_NUM_EP];
676
677 struct usb_request *ep0_req; /* for internal request */
678 __le16 ep0_data;
679 u32 ep0_length; /* for internal request */
680 u8 ep0_dir; /* 0/0x80 out/in */
681
682 u8 fifo_entry_num; /* next start fifo entry */
683 u32 addrofs; /* next fifo address offset */
684 u8 reenum; /* if re-enumeration */
685};
686
687#endif
diff --git a/drivers/usb/gadget/m66592-udc.c b/drivers/usb/gadget/m66592-udc.c
index 51b19f3027e7..084aa080a2d5 100644
--- a/drivers/usb/gadget/m66592-udc.c
+++ b/drivers/usb/gadget/m66592-udc.c
@@ -258,7 +258,7 @@ static int pipe_buffer_setting(struct m66592 *m66592,
258 break; 258 break;
259 case M66592_BULK: 259 case M66592_BULK:
260 /* isochronous pipes may be used as bulk pipes */ 260 /* isochronous pipes may be used as bulk pipes */
261 if (info->pipe > M66592_BASE_PIPENUM_BULK) 261 if (info->pipe >= M66592_BASE_PIPENUM_BULK)
262 bufnum = info->pipe - M66592_BASE_PIPENUM_BULK; 262 bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
263 else 263 else
264 bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC; 264 bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
diff --git a/drivers/usb/gadget/pch_udc.c b/drivers/usb/gadget/pch_udc.c
index b120dbb64d0f..3e4b35e50c24 100644
--- a/drivers/usb/gadget/pch_udc.c
+++ b/drivers/usb/gadget/pch_udc.c
@@ -367,7 +367,6 @@ struct pch_udc_dev {
367static const char ep0_string[] = "ep0in"; 367static const char ep0_string[] = "ep0in";
368static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */ 368static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
369struct pch_udc_dev *pch_udc; /* pointer to device object */ 369struct pch_udc_dev *pch_udc; /* pointer to device object */
370
371static int speed_fs; 370static int speed_fs;
372module_param_named(speed_fs, speed_fs, bool, S_IRUGO); 371module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
373MODULE_PARM_DESC(speed_fs, "true for Full speed operation"); 372MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
@@ -383,6 +382,8 @@ MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
383 * @dma_mapped: DMA memory mapped for request 382 * @dma_mapped: DMA memory mapped for request
384 * @dma_done: DMA completed for request 383 * @dma_done: DMA completed for request
385 * @chain_len: chain length 384 * @chain_len: chain length
385 * @buf: Buffer memory for align adjustment
386 * @dma: DMA memory for align adjustment
386 */ 387 */
387struct pch_udc_request { 388struct pch_udc_request {
388 struct usb_request req; 389 struct usb_request req;
@@ -394,6 +395,8 @@ struct pch_udc_request {
394 dma_mapped:1, 395 dma_mapped:1,
395 dma_done:1; 396 dma_done:1;
396 unsigned chain_len; 397 unsigned chain_len;
398 void *buf;
399 dma_addr_t dma;
397}; 400};
398 401
399static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg) 402static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
@@ -615,7 +618,7 @@ static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
615/** 618/**
616 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint 619 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
617 * @ep: Reference to structure of type pch_udc_ep_regs 620 * @ep: Reference to structure of type pch_udc_ep_regs
618 * @buf_size: The buffer size 621 * @buf_size: The buffer word size
619 */ 622 */
620static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep, 623static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
621 u32 buf_size, u32 ep_in) 624 u32 buf_size, u32 ep_in)
@@ -635,7 +638,7 @@ static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
635/** 638/**
636 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint 639 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
637 * @ep: Reference to structure of type pch_udc_ep_regs 640 * @ep: Reference to structure of type pch_udc_ep_regs
638 * @pkt_size: The packet size 641 * @pkt_size: The packet byte size
639 */ 642 */
640static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size) 643static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
641{ 644{
@@ -920,25 +923,10 @@ static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
920 */ 923 */
921static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir) 924static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
922{ 925{
923 unsigned int loopcnt = 0;
924 struct pch_udc_dev *dev = ep->dev;
925
926 if (dir) { /* IN ep */ 926 if (dir) { /* IN ep */
927 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F); 927 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
928 return; 928 return;
929 } 929 }
930
931 if (pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP)
932 return;
933 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_MRXFLUSH);
934 /* Wait for RxFIFO Empty */
935 loopcnt = 10000;
936 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
937 --loopcnt)
938 udelay(5);
939 if (!loopcnt)
940 dev_err(&dev->pdev->dev, "RxFIFO not Empty\n");
941 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_MRXFLUSH);
942} 930}
943 931
944/** 932/**
@@ -1220,14 +1208,31 @@ static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1220 1208
1221 dev = ep->dev; 1209 dev = ep->dev;
1222 if (req->dma_mapped) { 1210 if (req->dma_mapped) {
1223 if (ep->in) 1211 if (req->dma == DMA_ADDR_INVALID) {
1224 dma_unmap_single(&dev->pdev->dev, req->req.dma, 1212 if (ep->in)
1225 req->req.length, DMA_TO_DEVICE); 1213 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1226 else 1214 req->req.length,
1227 dma_unmap_single(&dev->pdev->dev, req->req.dma, 1215 DMA_TO_DEVICE);
1228 req->req.length, DMA_FROM_DEVICE); 1216 else
1217 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1218 req->req.length,
1219 DMA_FROM_DEVICE);
1220 req->req.dma = DMA_ADDR_INVALID;
1221 } else {
1222 if (ep->in)
1223 dma_unmap_single(&dev->pdev->dev, req->dma,
1224 req->req.length,
1225 DMA_TO_DEVICE);
1226 else {
1227 dma_unmap_single(&dev->pdev->dev, req->dma,
1228 req->req.length,
1229 DMA_FROM_DEVICE);
1230 memcpy(req->req.buf, req->buf, req->req.length);
1231 }
1232 kfree(req->buf);
1233 req->dma = DMA_ADDR_INVALID;
1234 }
1229 req->dma_mapped = 0; 1235 req->dma_mapped = 0;
1230 req->req.dma = DMA_ADDR_INVALID;
1231 } 1236 }
1232 ep->halted = 1; 1237 ep->halted = 1;
1233 spin_unlock(&dev->lock); 1238 spin_unlock(&dev->lock);
@@ -1268,12 +1273,18 @@ static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1268 struct pch_udc_data_dma_desc *td = req->td_data; 1273 struct pch_udc_data_dma_desc *td = req->td_data;
1269 unsigned i = req->chain_len; 1274 unsigned i = req->chain_len;
1270 1275
1276 dma_addr_t addr2;
1277 dma_addr_t addr = (dma_addr_t)td->next;
1278 td->next = 0x00;
1271 for (; i > 1; --i) { 1279 for (; i > 1; --i) {
1272 dma_addr_t addr = (dma_addr_t)td->next;
1273 /* do not free first desc., will be done by free for request */ 1280 /* do not free first desc., will be done by free for request */
1274 td = phys_to_virt(addr); 1281 td = phys_to_virt(addr);
1282 addr2 = (dma_addr_t)td->next;
1275 pci_pool_free(dev->data_requests, td, addr); 1283 pci_pool_free(dev->data_requests, td, addr);
1284 td->next = 0x00;
1285 addr = addr2;
1276 } 1286 }
1287 req->chain_len = 1;
1277} 1288}
1278 1289
1279/** 1290/**
@@ -1301,23 +1312,23 @@ static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1301 if (req->chain_len > 1) 1312 if (req->chain_len > 1)
1302 pch_udc_free_dma_chain(ep->dev, req); 1313 pch_udc_free_dma_chain(ep->dev, req);
1303 1314
1304 for (; ; bytes -= buf_len, ++len) { 1315 if (req->dma == DMA_ADDR_INVALID)
1305 if (ep->in) 1316 td->dataptr = req->req.dma;
1306 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes); 1317 else
1307 else 1318 td->dataptr = req->dma;
1308 td->status = PCH_UDC_BS_HST_BSY;
1309 1319
1320 td->status = PCH_UDC_BS_HST_BSY;
1321 for (; ; bytes -= buf_len, ++len) {
1322 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1310 if (bytes <= buf_len) 1323 if (bytes <= buf_len)
1311 break; 1324 break;
1312
1313 last = td; 1325 last = td;
1314 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags, 1326 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1315 &dma_addr); 1327 &dma_addr);
1316 if (!td) 1328 if (!td)
1317 goto nomem; 1329 goto nomem;
1318
1319 i += buf_len; 1330 i += buf_len;
1320 td->dataptr = req->req.dma + i; 1331 td->dataptr = req->td_data->dataptr + i;
1321 last->next = dma_addr; 1332 last->next = dma_addr;
1322 } 1333 }
1323 1334
@@ -1352,28 +1363,15 @@ static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1352{ 1363{
1353 int retval; 1364 int retval;
1354 1365
1355 req->td_data->dataptr = req->req.dma;
1356 req->td_data->status |= PCH_UDC_DMA_LAST;
1357 /* Allocate and create a DMA chain */ 1366 /* Allocate and create a DMA chain */
1358 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp); 1367 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1359 if (retval) { 1368 if (retval) {
1360 pr_err("%s: could not create DMA chain: %d\n", 1369 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1361 __func__, retval);
1362 return retval; 1370 return retval;
1363 } 1371 }
1364 if (!ep->in) 1372 if (ep->in)
1365 return 0;
1366 if (req->req.length <= ep->ep.maxpacket)
1367 req->td_data->status = PCH_UDC_DMA_LAST | PCH_UDC_BS_HST_BSY |
1368 req->req.length;
1369 /* if bytes < max packet then tx bytes must
1370 * be written in packet per buffer mode
1371 */
1372 if ((req->req.length < ep->ep.maxpacket) || !ep->num)
1373 req->td_data->status = (req->td_data->status & 1373 req->td_data->status = (req->td_data->status &
1374 ~PCH_UDC_RXTX_BYTES) | req->req.length; 1374 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1375 req->td_data->status = (req->td_data->status &
1376 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_BSY;
1377 return 0; 1375 return 0;
1378} 1376}
1379 1377
@@ -1529,6 +1527,7 @@ static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1529 if (!req) 1527 if (!req)
1530 return NULL; 1528 return NULL;
1531 req->req.dma = DMA_ADDR_INVALID; 1529 req->req.dma = DMA_ADDR_INVALID;
1530 req->dma = DMA_ADDR_INVALID;
1532 INIT_LIST_HEAD(&req->queue); 1531 INIT_LIST_HEAD(&req->queue);
1533 if (!ep->dev->dma_addr) 1532 if (!ep->dev->dma_addr)
1534 return &req->req; 1533 return &req->req;
@@ -1613,16 +1612,33 @@ static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1613 /* map the buffer for dma */ 1612 /* map the buffer for dma */
1614 if (usbreq->length && 1613 if (usbreq->length &&
1615 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) { 1614 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1616 if (ep->in) 1615 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1617 usbreq->dma = dma_map_single(&dev->pdev->dev, 1616 if (ep->in)
1618 usbreq->buf, 1617 usbreq->dma = dma_map_single(&dev->pdev->dev,
1619 usbreq->length, 1618 usbreq->buf,
1620 DMA_TO_DEVICE); 1619 usbreq->length,
1621 else 1620 DMA_TO_DEVICE);
1622 usbreq->dma = dma_map_single(&dev->pdev->dev, 1621 else
1623 usbreq->buf, 1622 usbreq->dma = dma_map_single(&dev->pdev->dev,
1624 usbreq->length, 1623 usbreq->buf,
1625 DMA_FROM_DEVICE); 1624 usbreq->length,
1625 DMA_FROM_DEVICE);
1626 } else {
1627 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1628 if (!req->buf)
1629 return -ENOMEM;
1630 if (ep->in) {
1631 memcpy(req->buf, usbreq->buf, usbreq->length);
1632 req->dma = dma_map_single(&dev->pdev->dev,
1633 req->buf,
1634 usbreq->length,
1635 DMA_TO_DEVICE);
1636 } else
1637 req->dma = dma_map_single(&dev->pdev->dev,
1638 req->buf,
1639 usbreq->length,
1640 DMA_FROM_DEVICE);
1641 }
1626 req->dma_mapped = 1; 1642 req->dma_mapped = 1;
1627 } 1643 }
1628 if (usbreq->length > 0) { 1644 if (usbreq->length > 0) {
@@ -1920,32 +1936,46 @@ static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1920 struct pch_udc_request *req; 1936 struct pch_udc_request *req;
1921 struct pch_udc_dev *dev = ep->dev; 1937 struct pch_udc_dev *dev = ep->dev;
1922 unsigned int count; 1938 unsigned int count;
1939 struct pch_udc_data_dma_desc *td;
1940 dma_addr_t addr;
1923 1941
1924 if (list_empty(&ep->queue)) 1942 if (list_empty(&ep->queue))
1925 return; 1943 return;
1926
1927 /* next request */ 1944 /* next request */
1928 req = list_entry(ep->queue.next, struct pch_udc_request, queue); 1945 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1929 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1930 PCH_UDC_BS_DMA_DONE)
1931 return;
1932 pch_udc_clear_dma(ep->dev, DMA_DIR_RX); 1946 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1933 pch_udc_ep_set_ddptr(ep, 0); 1947 pch_udc_ep_set_ddptr(ep, 0);
1934 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) != 1948 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1935 PCH_UDC_RTS_SUCC) { 1949 PCH_UDC_BS_DMA_DONE)
1936 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) " 1950 td = req->td_data_last;
1937 "epstatus=0x%08x\n", 1951 else
1938 (req->td_data_last->status & PCH_UDC_RXTX_STS), 1952 td = req->td_data;
1939 (int)(ep->epsts));
1940 return;
1941 }
1942 count = req->td_data_last->status & PCH_UDC_RXTX_BYTES;
1943 1953
1954 while (1) {
1955 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
1956 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
1957 "epstatus=0x%08x\n",
1958 (req->td_data->status & PCH_UDC_RXTX_STS),
1959 (int)(ep->epsts));
1960 return;
1961 }
1962 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
1963 if (td->status | PCH_UDC_DMA_LAST) {
1964 count = td->status & PCH_UDC_RXTX_BYTES;
1965 break;
1966 }
1967 if (td == req->td_data_last) {
1968 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
1969 return;
1970 }
1971 addr = (dma_addr_t)td->next;
1972 td = phys_to_virt(addr);
1973 }
1944 /* on 64k packets the RXBYTES field is zero */ 1974 /* on 64k packets the RXBYTES field is zero */
1945 if (!count && (req->req.length == UDC_DMA_MAXPACKET)) 1975 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
1946 count = UDC_DMA_MAXPACKET; 1976 count = UDC_DMA_MAXPACKET;
1947 req->td_data->status |= PCH_UDC_DMA_LAST; 1977 req->td_data->status |= PCH_UDC_DMA_LAST;
1948 req->td_data_last->status |= PCH_UDC_BS_HST_BSY; 1978 td->status |= PCH_UDC_BS_HST_BSY;
1949 1979
1950 req->dma_going = 0; 1980 req->dma_going = 0;
1951 req->req.actual = count; 1981 req->req.actual = count;
diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index c2448950a8d8..6d8b04061d5d 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -902,7 +902,7 @@ static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
902 int pwr_reg; 902 int pwr_reg;
903 int ep0csr; 903 int ep0csr;
904 int i; 904 int i;
905 u32 idx; 905 u32 idx, idx2;
906 unsigned long flags; 906 unsigned long flags;
907 907
908 spin_lock_irqsave(&dev->lock, flags); 908 spin_lock_irqsave(&dev->lock, flags);
@@ -1017,6 +1017,20 @@ static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
1017 } 1017 }
1018 } 1018 }
1019 1019
1020 /* what else causes this interrupt? a receive! who is it? */
1021 if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
1022 for (i = 1; i < S3C2410_ENDPOINTS; i++) {
1023 idx2 = udc_read(S3C2410_UDC_INDEX_REG);
1024 udc_write(i, S3C2410_UDC_INDEX_REG);
1025
1026 if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
1027 s3c2410_udc_handle_ep(&dev->ep[i]);
1028
1029 /* restore index */
1030 udc_write(idx2, S3C2410_UDC_INDEX_REG);
1031 }
1032 }
1033
1020 dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD); 1034 dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
1021 1035
1022 /* Restore old index */ 1036 /* Restore old index */
@@ -1467,7 +1481,9 @@ static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
1467{ 1481{
1468 dprintk(DEBUG_NORMAL, "%s()\n", __func__); 1482 dprintk(DEBUG_NORMAL, "%s()\n", __func__);
1469 1483
1470 if (udc_info && udc_info->udc_command) { 1484 if (udc_info && (udc_info->udc_command ||
1485 gpio_is_valid(udc_info->pullup_pin))) {
1486
1471 if (is_on) 1487 if (is_on)
1472 s3c2410_udc_enable(udc); 1488 s3c2410_udc_enable(udc);
1473 else { 1489 else {
@@ -1544,6 +1560,32 @@ static const struct usb_gadget_ops s3c2410_ops = {
1544 .vbus_draw = s3c2410_vbus_draw, 1560 .vbus_draw = s3c2410_vbus_draw,
1545}; 1561};
1546 1562
1563static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
1564{
1565 if (!udc_info)
1566 return;
1567
1568 if (udc_info->udc_command) {
1569 udc_info->udc_command(S3C2410_UDC_P_DISABLE);
1570 } else if (gpio_is_valid(udc_info->pullup_pin)) {
1571 int value;
1572
1573 switch (cmd) {
1574 case S3C2410_UDC_P_ENABLE:
1575 value = 1;
1576 break;
1577 case S3C2410_UDC_P_DISABLE:
1578 value = 0;
1579 break;
1580 default:
1581 return;
1582 }
1583 value ^= udc_info->pullup_pin_inverted;
1584
1585 gpio_set_value(udc_info->pullup_pin, value);
1586 }
1587}
1588
1547/*------------------------- gadget driver handling---------------------------*/ 1589/*------------------------- gadget driver handling---------------------------*/
1548/* 1590/*
1549 * s3c2410_udc_disable 1591 * s3c2410_udc_disable
@@ -1565,8 +1607,7 @@ static void s3c2410_udc_disable(struct s3c2410_udc *dev)
1565 udc_write(0x1F, S3C2410_UDC_EP_INT_REG); 1607 udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
1566 1608
1567 /* Good bye, cruel world */ 1609 /* Good bye, cruel world */
1568 if (udc_info && udc_info->udc_command) 1610 s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
1569 udc_info->udc_command(S3C2410_UDC_P_DISABLE);
1570 1611
1571 /* Set speed to unknown */ 1612 /* Set speed to unknown */
1572 dev->gadget.speed = USB_SPEED_UNKNOWN; 1613 dev->gadget.speed = USB_SPEED_UNKNOWN;
@@ -1627,8 +1668,7 @@ static void s3c2410_udc_enable(struct s3c2410_udc *dev)
1627 udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG); 1668 udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
1628 1669
1629 /* time to say "hello, world" */ 1670 /* time to say "hello, world" */
1630 if (udc_info && udc_info->udc_command) 1671 s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
1631 udc_info->udc_command(S3C2410_UDC_P_ENABLE);
1632} 1672}
1633 1673
1634/* 1674/*
@@ -1903,6 +1943,17 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
1903 udc->vbus = 1; 1943 udc->vbus = 1;
1904 } 1944 }
1905 1945
1946 if (udc_info && !udc_info->udc_command &&
1947 gpio_is_valid(udc_info->pullup_pin)) {
1948
1949 retval = gpio_request_one(udc_info->pullup_pin,
1950 udc_info->vbus_pin_inverted ?
1951 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
1952 "udc pullup");
1953 if (retval)
1954 goto err_vbus_irq;
1955 }
1956
1906 if (s3c2410_udc_debugfs_root) { 1957 if (s3c2410_udc_debugfs_root) {
1907 udc->regs_info = debugfs_create_file("registers", S_IRUGO, 1958 udc->regs_info = debugfs_create_file("registers", S_IRUGO,
1908 s3c2410_udc_debugfs_root, 1959 s3c2410_udc_debugfs_root,
@@ -1915,6 +1966,9 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
1915 1966
1916 return 0; 1967 return 0;
1917 1968
1969err_vbus_irq:
1970 if (udc_info && udc_info->vbus_pin > 0)
1971 free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
1918err_gpio_claim: 1972err_gpio_claim:
1919 if (udc_info && udc_info->vbus_pin > 0) 1973 if (udc_info && udc_info->vbus_pin > 0)
1920 gpio_free(udc_info->vbus_pin); 1974 gpio_free(udc_info->vbus_pin);
@@ -1942,6 +1996,10 @@ static int s3c2410_udc_remove(struct platform_device *pdev)
1942 1996
1943 debugfs_remove(udc->regs_info); 1997 debugfs_remove(udc->regs_info);
1944 1998
1999 if (udc_info && !udc_info->udc_command &&
2000 gpio_is_valid(udc_info->pullup_pin))
2001 gpio_free(udc_info->pullup_pin);
2002
1945 if (udc_info && udc_info->vbus_pin > 0) { 2003 if (udc_info && udc_info->vbus_pin > 0) {
1946 irq = gpio_to_irq(udc_info->vbus_pin); 2004 irq = gpio_to_irq(udc_info->vbus_pin);
1947 free_irq(irq, udc); 2005 free_irq(irq, udc);
@@ -1973,16 +2031,14 @@ static int s3c2410_udc_remove(struct platform_device *pdev)
1973#ifdef CONFIG_PM 2031#ifdef CONFIG_PM
1974static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message) 2032static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
1975{ 2033{
1976 if (udc_info && udc_info->udc_command) 2034 s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
1977 udc_info->udc_command(S3C2410_UDC_P_DISABLE);
1978 2035
1979 return 0; 2036 return 0;
1980} 2037}
1981 2038
1982static int s3c2410_udc_resume(struct platform_device *pdev) 2039static int s3c2410_udc_resume(struct platform_device *pdev)
1983{ 2040{
1984 if (udc_info && udc_info->udc_command) 2041 s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
1985 udc_info->udc_command(S3C2410_UDC_P_ENABLE);
1986 2042
1987 return 0; 2043 return 0;
1988} 2044}
diff --git a/drivers/usb/gadget/u_ether.c b/drivers/usb/gadget/u_ether.c
index 1eda968b5644..2ac1d2147325 100644
--- a/drivers/usb/gadget/u_ether.c
+++ b/drivers/usb/gadget/u_ether.c
@@ -241,7 +241,7 @@ rx_submit(struct eth_dev *dev, struct usb_request *req, gfp_t gfp_flags)
241 size -= size % out->maxpacket; 241 size -= size % out->maxpacket;
242 242
243 if (dev->port_usb->is_fixed) 243 if (dev->port_usb->is_fixed)
244 size = max(size, dev->port_usb->fixed_out_len); 244 size = max_t(size_t, size, dev->port_usb->fixed_out_len);
245 245
246 skb = alloc_skb(size + NET_IP_ALIGN, gfp_flags); 246 skb = alloc_skb(size + NET_IP_ALIGN, gfp_flags);
247 if (skb == NULL) { 247 if (skb == NULL) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 07:23:58 -0500