diff options
Diffstat (limited to 'drivers/usb/dwc3/core.h')
-rw-r--r-- | drivers/usb/dwc3/core.h | 89 |
1 files changed, 69 insertions, 20 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 66f62563bcf9..4bb9aa696ede 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h | |||
@@ -166,6 +166,7 @@ | |||
166 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) | 166 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
167 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | 167 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) |
168 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | 168 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) |
169 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) | ||
169 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) | 170 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) |
170 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) | 171 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) |
171 | 172 | ||
@@ -175,7 +176,17 @@ | |||
175 | 176 | ||
176 | /* Global USB3 PIPE Control Register */ | 177 | /* Global USB3 PIPE Control Register */ |
177 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) | 178 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
179 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) | ||
180 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) | ||
181 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) | ||
182 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | ||
183 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | ||
184 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) | ||
178 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | 185 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) |
186 | #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) | ||
187 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) | ||
188 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) | ||
189 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | ||
179 | 190 | ||
180 | /* Global TX Fifo Size Register */ | 191 | /* Global TX Fifo Size Register */ |
181 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) | 192 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
@@ -210,6 +221,9 @@ | |||
210 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | 221 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) |
211 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | 222 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 |
212 | 223 | ||
224 | /* Global HWPARAMS6 Register */ | ||
225 | #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) | ||
226 | |||
213 | /* Device Configuration Register */ | 227 | /* Device Configuration Register */ |
214 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | 228 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
215 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | 229 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) |
@@ -243,16 +257,19 @@ | |||
243 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | 257 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) |
244 | 258 | ||
245 | /* These apply for core versions 1.94a and later */ | 259 | /* These apply for core versions 1.94a and later */ |
246 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) | 260 | #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) |
247 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | 261 | #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) |
248 | #define DWC3_DCTL_CRS (1 << 17) | 262 | |
249 | #define DWC3_DCTL_CSS (1 << 16) | 263 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) |
264 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | ||
265 | #define DWC3_DCTL_CRS (1 << 17) | ||
266 | #define DWC3_DCTL_CSS (1 << 16) | ||
250 | 267 | ||
251 | #define DWC3_DCTL_INITU2ENA (1 << 12) | 268 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
252 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | 269 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) |
253 | #define DWC3_DCTL_INITU1ENA (1 << 10) | 270 | #define DWC3_DCTL_INITU1ENA (1 << 10) |
254 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | 271 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) |
255 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | 272 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
256 | 273 | ||
257 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | 274 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) |
258 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | 275 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) |
@@ -657,17 +674,41 @@ struct dwc3_scratchpad_array { | |||
657 | * @regset: debugfs pointer to regdump file | 674 | * @regset: debugfs pointer to regdump file |
658 | * @test_mode: true when we're entering a USB test mode | 675 | * @test_mode: true when we're entering a USB test mode |
659 | * @test_mode_nr: test feature selector | 676 | * @test_mode_nr: test feature selector |
677 | * @lpm_nyet_threshold: LPM NYET response threshold | ||
678 | * @hird_threshold: HIRD threshold | ||
660 | * @delayed_status: true when gadget driver asks for delayed status | 679 | * @delayed_status: true when gadget driver asks for delayed status |
661 | * @ep0_bounced: true when we used bounce buffer | 680 | * @ep0_bounced: true when we used bounce buffer |
662 | * @ep0_expect_in: true when we expect a DATA IN transfer | 681 | * @ep0_expect_in: true when we expect a DATA IN transfer |
663 | * @has_hibernation: true when dwc3 was configured with Hibernation | 682 | * @has_hibernation: true when dwc3 was configured with Hibernation |
683 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that | ||
684 | * there's now way for software to detect this in runtime. | ||
685 | * @is_utmi_l1_suspend: the core asserts output signal | ||
686 | * 0 - utmi_sleep_n | ||
687 | * 1 - utmi_l1_suspend_n | ||
664 | * @is_selfpowered: true when we are selfpowered | 688 | * @is_selfpowered: true when we are selfpowered |
689 | * @is_fpga: true when we are using the FPGA board | ||
665 | * @needs_fifo_resize: not all users might want fifo resizing, flag it | 690 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
666 | * @pullups_connected: true when Run/Stop bit is set | 691 | * @pullups_connected: true when Run/Stop bit is set |
667 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | 692 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. |
668 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround | 693 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
669 | * @start_config_issued: true when StartConfig command has been issued | 694 | * @start_config_issued: true when StartConfig command has been issued |
670 | * @three_stage_setup: set if we perform a three phase setup | 695 | * @three_stage_setup: set if we perform a three phase setup |
696 | * @disable_scramble_quirk: set if we enable the disable scramble quirk | ||
697 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk | ||
698 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk | ||
699 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk | ||
700 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk | ||
701 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk | ||
702 | * @lfps_filter_quirk: set if we enable LFPS filter quirk | ||
703 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk | ||
704 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy | ||
705 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy | ||
706 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk | ||
707 | * @tx_de_emphasis: Tx de-emphasis value | ||
708 | * 0 - -6dB de-emphasis | ||
709 | * 1 - -3.5dB de-emphasis | ||
710 | * 2 - No de-emphasis | ||
711 | * 3 - Reserved | ||
671 | */ | 712 | */ |
672 | struct dwc3 { | 713 | struct dwc3 { |
673 | struct usb_ctrlrequest *ctrl_req; | 714 | struct usb_ctrlrequest *ctrl_req; |
@@ -759,18 +800,37 @@ struct dwc3 { | |||
759 | 800 | ||
760 | u8 test_mode; | 801 | u8 test_mode; |
761 | u8 test_mode_nr; | 802 | u8 test_mode_nr; |
803 | u8 lpm_nyet_threshold; | ||
804 | u8 hird_threshold; | ||
762 | 805 | ||
763 | unsigned delayed_status:1; | 806 | unsigned delayed_status:1; |
764 | unsigned ep0_bounced:1; | 807 | unsigned ep0_bounced:1; |
765 | unsigned ep0_expect_in:1; | 808 | unsigned ep0_expect_in:1; |
766 | unsigned has_hibernation:1; | 809 | unsigned has_hibernation:1; |
810 | unsigned has_lpm_erratum:1; | ||
811 | unsigned is_utmi_l1_suspend:1; | ||
767 | unsigned is_selfpowered:1; | 812 | unsigned is_selfpowered:1; |
813 | unsigned is_fpga:1; | ||
768 | unsigned needs_fifo_resize:1; | 814 | unsigned needs_fifo_resize:1; |
769 | unsigned pullups_connected:1; | 815 | unsigned pullups_connected:1; |
770 | unsigned resize_fifos:1; | 816 | unsigned resize_fifos:1; |
771 | unsigned setup_packet_pending:1; | 817 | unsigned setup_packet_pending:1; |
772 | unsigned start_config_issued:1; | 818 | unsigned start_config_issued:1; |
773 | unsigned three_stage_setup:1; | 819 | unsigned three_stage_setup:1; |
820 | |||
821 | unsigned disable_scramble_quirk:1; | ||
822 | unsigned u2exit_lfps_quirk:1; | ||
823 | unsigned u2ss_inp3_quirk:1; | ||
824 | unsigned req_p1p2p3_quirk:1; | ||
825 | unsigned del_p1p2p3_quirk:1; | ||
826 | unsigned del_phy_power_chg_quirk:1; | ||
827 | unsigned lfps_filter_quirk:1; | ||
828 | unsigned rx_detect_poll_quirk:1; | ||
829 | unsigned dis_u3_susphy_quirk:1; | ||
830 | unsigned dis_u2_susphy_quirk:1; | ||
831 | |||
832 | unsigned tx_de_emphasis_quirk:1; | ||
833 | unsigned tx_de_emphasis:2; | ||
774 | }; | 834 | }; |
775 | 835 | ||
776 | /* -------------------------------------------------------------------------- */ | 836 | /* -------------------------------------------------------------------------- */ |
@@ -964,20 +1024,9 @@ static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |||
964 | 1024 | ||
965 | /* power management interface */ | 1025 | /* power management interface */ |
966 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | 1026 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) |
967 | int dwc3_gadget_prepare(struct dwc3 *dwc); | ||
968 | void dwc3_gadget_complete(struct dwc3 *dwc); | ||
969 | int dwc3_gadget_suspend(struct dwc3 *dwc); | 1027 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
970 | int dwc3_gadget_resume(struct dwc3 *dwc); | 1028 | int dwc3_gadget_resume(struct dwc3 *dwc); |
971 | #else | 1029 | #else |
972 | static inline int dwc3_gadget_prepare(struct dwc3 *dwc) | ||
973 | { | ||
974 | return 0; | ||
975 | } | ||
976 | |||
977 | static inline void dwc3_gadget_complete(struct dwc3 *dwc) | ||
978 | { | ||
979 | } | ||
980 | |||
981 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) | 1030 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
982 | { | 1031 | { |
983 | return 0; | 1032 | return 0; |