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path: root/drivers/tty/serial/xilinx_uartps.c
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-rw-r--r--drivers/tty/serial/xilinx_uartps.c1129
1 files changed, 540 insertions, 589 deletions
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index f619ad5b5eae..8809775e2ba3 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Xilinx PS UART driver 2 * Cadence UART driver (found in Xilinx Zynq)
3 * 3 *
4 * 2011 - 2013 (C) Xilinx Inc. 4 * 2011 - 2014 (C) Xilinx Inc.
5 * 5 *
6 * This program is free software; you can redistribute it 6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public 7 * and/or modify it under the terms of the GNU General Public
@@ -9,6 +9,9 @@
9 * either version 2 of the License, or (at your option) any 9 * either version 2 of the License, or (at your option) any
10 * later version. 10 * later version.
11 * 11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
12 */ 15 */
13 16
14#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
@@ -28,16 +31,16 @@
28#include <linux/of.h> 31#include <linux/of.h>
29#include <linux/module.h> 32#include <linux/module.h>
30 33
31#define XUARTPS_TTY_NAME "ttyPS" 34#define CDNS_UART_TTY_NAME "ttyPS"
32#define XUARTPS_NAME "xuartps" 35#define CDNS_UART_NAME "xuartps"
33#define XUARTPS_MAJOR 0 /* use dynamic node allocation */ 36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
34#define XUARTPS_MINOR 0 /* works best with devtmpfs */ 37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
35#define XUARTPS_NR_PORTS 2 38#define CDNS_UART_NR_PORTS 2
36#define XUARTPS_FIFO_SIZE 64 /* FIFO size */ 39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
37#define XUARTPS_REGISTER_SPACE 0xFFF 40#define CDNS_UART_REGISTER_SPACE 0xFFF
38 41
39#define xuartps_readl(offset) ioread32(port->membase + offset) 42#define cdns_uart_readl(offset) ioread32(port->membase + offset)
40#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) 43#define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset)
41 44
42/* Rx Trigger level */ 45/* Rx Trigger level */
43static int rx_trigger_level = 56; 46static int rx_trigger_level = 56;
@@ -49,77 +52,62 @@ static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO); 52module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 53MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51 54
52/********************************Register Map********************************/ 55/* Register offsets for the UART. */
53/** UART 56#define CDNS_UART_CR_OFFSET 0x00 /* Control Register */
54 * 57#define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */
55 * Register offsets for the UART. 58#define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */
56 * 59#define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */
57 */ 60#define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */
58#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ 61#define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */
59#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ 62#define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
60#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ 63#define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */
61#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ 64#define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
62#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ 65#define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */
63#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ 66#define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */
64#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ 67#define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */
65#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ 68#define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */
66#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ 69#define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
67#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ 70#define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */
68#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ 71#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */
69#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ 72#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
70#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 73#define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
71#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ 74
72#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ 75/* Control Register Bit Definitions */
73#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse 76#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74 Width [15:0] */ 77#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse 78#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76 Width [7:0] */ 79#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ 80#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78 81#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79/** Control Register 82#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80 * 83#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81 * The Control register (CR) controls the major functions of the device. 84#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82 * 85
83 * Control Register Bit Definitions 86/*
84 */ 87 * Mode Register:
85#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
94
95/** Mode Register
96 *
97 * The mode register (MR) defines the mode of transfer as well as the data 88 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception, 89 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed. 90 * data validity cannot be guaranteed.
100 *
101 * Mode Register Bit Definitions
102 *
103 */ 91 */
104#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 92#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 93#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 94#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
107 95
108#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 96#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 97#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
110 98
111#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ 99#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
112#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 100#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 101#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 102#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 103#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
116 104
117#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 105#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 106#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 107#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
120 108
121/** Interrupt Registers 109/*
122 * 110 * Interrupt Registers:
123 * Interrupt control logic uses the interrupt enable register (IER) and the 111 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the 112 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an 113 * interrupt mask register (IMR). The IMR determines whether to pass an
@@ -127,65 +115,65 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 116 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00. 117 * Reading either IER or IDR returns 0x00.
130 *
131 * All four registers have the same bit definitions. 118 * All four registers have the same bit definitions.
132 */ 119 */
133#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 120#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ 121#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
135#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 122#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 123#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 124#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 125#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 126#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 127#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 128#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 129#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ 130#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
144 131
145/* Goes in read_status_mask for break detection as the HW doesn't do it*/ 132/* Goes in read_status_mask for break detection as the HW doesn't do it*/
146#define XUARTPS_IXR_BRK 0x80000000 133#define CDNS_UART_IXR_BRK 0x80000000
147 134
148/** Channel Status Register 135/*
149 * 136 * Channel Status Register:
150 * The channel status register (CSR) is provided to enable the control logic 137 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register, 138 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register. 139 * even if these are masked out by the interrupt mask register.
153 */ 140 */
154#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 141#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 142#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ 143#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
157#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ 144#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
158 145
159/* baud dividers min/max values */ 146/* baud dividers min/max values */
160#define XUARTPS_BDIV_MIN 4 147#define CDNS_UART_BDIV_MIN 4
161#define XUARTPS_BDIV_MAX 255 148#define CDNS_UART_BDIV_MAX 255
162#define XUARTPS_CD_MAX 65535 149#define CDNS_UART_CD_MAX 65535
163 150
164/** 151/**
165 * struct xuartps - device data 152 * struct cdns_uart - device data
166 * @port Pointer to the UART port 153 * @port: Pointer to the UART port
167 * @refclk Reference clock 154 * @uartclk: Reference clock
168 * @aperclk APB clock 155 * @pclk: APB clock
169 * @baud Current baud rate 156 * @baud: Current baud rate
170 * @clk_rate_change_nb Notifier block for clock changes 157 * @clk_rate_change_nb: Notifier block for clock changes
171 */ 158 */
172struct xuartps { 159struct cdns_uart {
173 struct uart_port *port; 160 struct uart_port *port;
174 struct clk *refclk; 161 struct clk *uartclk;
175 struct clk *aperclk; 162 struct clk *pclk;
176 unsigned int baud; 163 unsigned int baud;
177 struct notifier_block clk_rate_change_nb; 164 struct notifier_block clk_rate_change_nb;
178}; 165};
179#define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb); 166#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
167 clk_rate_change_nb);
180 168
181/** 169/**
182 * xuartps_isr - Interrupt handler 170 * cdns_uart_isr - Interrupt handler
183 * @irq: Irq number 171 * @irq: Irq number
184 * @dev_id: Id of the port 172 * @dev_id: Id of the port
185 * 173 *
186 * Returns IRQHANDLED 174 * Return: IRQHANDLED
187 **/ 175 */
188static irqreturn_t xuartps_isr(int irq, void *dev_id) 176static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
189{ 177{
190 struct uart_port *port = (struct uart_port *)dev_id; 178 struct uart_port *port = (struct uart_port *)dev_id;
191 unsigned long flags; 179 unsigned long flags;
@@ -198,43 +186,42 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
198 /* Read the interrupt status register to determine which 186 /* Read the interrupt status register to determine which
199 * interrupt(s) is/are active. 187 * interrupt(s) is/are active.
200 */ 188 */
201 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); 189 isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET);
202 190
203 /* 191 /*
204 * There is no hardware break detection, so we interpret framing 192 * There is no hardware break detection, so we interpret framing
205 * error with all-zeros data as a break sequence. Most of the time, 193 * error with all-zeros data as a break sequence. Most of the time,
206 * there's another non-zero byte at the end of the sequence. 194 * there's another non-zero byte at the end of the sequence.
207 */ 195 */
208 196 if (isrstatus & CDNS_UART_IXR_FRAMING) {
209 if (isrstatus & XUARTPS_IXR_FRAMING) { 197 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
210 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & 198 CDNS_UART_SR_RXEMPTY)) {
211 XUARTPS_SR_RXEMPTY)) { 199 if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) {
212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) { 200 port->read_status_mask |= CDNS_UART_IXR_BRK;
213 port->read_status_mask |= XUARTPS_IXR_BRK; 201 isrstatus &= ~CDNS_UART_IXR_FRAMING;
214 isrstatus &= ~XUARTPS_IXR_FRAMING;
215 } 202 }
216 } 203 }
217 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET); 204 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET);
218 } 205 }
219 206
220 /* drop byte with parity error if IGNPAR specified */ 207 /* drop byte with parity error if IGNPAR specified */
221 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) 208 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
222 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); 209 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
223 210
224 isrstatus &= port->read_status_mask; 211 isrstatus &= port->read_status_mask;
225 isrstatus &= ~port->ignore_status_mask; 212 isrstatus &= ~port->ignore_status_mask;
226 213
227 if ((isrstatus & XUARTPS_IXR_TOUT) || 214 if ((isrstatus & CDNS_UART_IXR_TOUT) ||
228 (isrstatus & XUARTPS_IXR_RXTRIG)) { 215 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
229 /* Receive Timeout Interrupt */ 216 /* Receive Timeout Interrupt */
230 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 217 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
231 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 218 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
232 data = xuartps_readl(XUARTPS_FIFO_OFFSET); 219 data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
233 220
234 /* Non-NULL byte after BREAK is garbage (99%) */ 221 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data && (port->read_status_mask & 222 if (data && (port->read_status_mask &
236 XUARTPS_IXR_BRK)) { 223 CDNS_UART_IXR_BRK)) {
237 port->read_status_mask &= ~XUARTPS_IXR_BRK; 224 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
238 port->icount.brk++; 225 port->icount.brk++;
239 if (uart_handle_break(port)) 226 if (uart_handle_break(port))
240 continue; 227 continue;
@@ -258,16 +245,17 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
258 245
259 port->icount.rx++; 246 port->icount.rx++;
260 247
261 if (isrstatus & XUARTPS_IXR_PARITY) { 248 if (isrstatus & CDNS_UART_IXR_PARITY) {
262 port->icount.parity++; 249 port->icount.parity++;
263 status = TTY_PARITY; 250 status = TTY_PARITY;
264 } else if (isrstatus & XUARTPS_IXR_FRAMING) { 251 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
265 port->icount.frame++; 252 port->icount.frame++;
266 status = TTY_FRAME; 253 status = TTY_FRAME;
267 } else if (isrstatus & XUARTPS_IXR_OVERRUN) 254 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
268 port->icount.overrun++; 255 port->icount.overrun++;
256 }
269 257
270 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, 258 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
271 data, status); 259 data, status);
272 } 260 }
273 spin_unlock(&port->lock); 261 spin_unlock(&port->lock);
@@ -276,10 +264,10 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
276 } 264 }
277 265
278 /* Dispatch an appropriate handler */ 266 /* Dispatch an appropriate handler */
279 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { 267 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
280 if (uart_circ_empty(&port->state->xmit)) { 268 if (uart_circ_empty(&port->state->xmit)) {
281 xuartps_writel(XUARTPS_IXR_TXEMPTY, 269 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY,
282 XUARTPS_IDR_OFFSET); 270 CDNS_UART_IDR_OFFSET);
283 } else { 271 } else {
284 numbytes = port->fifosize; 272 numbytes = port->fifosize;
285 /* Break if no more data available in the UART buffer */ 273 /* Break if no more data available in the UART buffer */
@@ -287,12 +275,12 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
287 if (uart_circ_empty(&port->state->xmit)) 275 if (uart_circ_empty(&port->state->xmit))
288 break; 276 break;
289 /* Get the data from the UART circular buffer 277 /* Get the data from the UART circular buffer
290 * and write it to the xuartps's TX_FIFO 278 * and write it to the cdns_uart's TX_FIFO
291 * register. 279 * register.
292 */ 280 */
293 xuartps_writel( 281 cdns_uart_writel(
294 port->state->xmit.buf[port->state->xmit. 282 port->state->xmit.buf[port->state->xmit.
295 tail], XUARTPS_FIFO_OFFSET); 283 tail], CDNS_UART_FIFO_OFFSET);
296 284
297 port->icount.tx++; 285 port->icount.tx++;
298 286
@@ -300,7 +288,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
300 * the buffer if it reaches limit. 288 * the buffer if it reaches limit.
301 */ 289 */
302 port->state->xmit.tail = 290 port->state->xmit.tail =
303 (port->state->xmit.tail + 1) & \ 291 (port->state->xmit.tail + 1) &
304 (UART_XMIT_SIZE - 1); 292 (UART_XMIT_SIZE - 1);
305 } 293 }
306 294
@@ -310,7 +298,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
310 } 298 }
311 } 299 }
312 300
313 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); 301 cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET);
314 302
315 /* be sure to release the lock and tty before leaving */ 303 /* be sure to release the lock and tty before leaving */
316 spin_unlock_irqrestore(&port->lock, flags); 304 spin_unlock_irqrestore(&port->lock, flags);
@@ -319,13 +307,13 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
319} 307}
320 308
321/** 309/**
322 * xuartps_calc_baud_divs - Calculate baud rate divisors 310 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
323 * @clk: UART module input clock 311 * @clk: UART module input clock
324 * @baud: Desired baud rate 312 * @baud: Desired baud rate
325 * @rbdiv: BDIV value (return value) 313 * @rbdiv: BDIV value (return value)
326 * @rcd: CD value (return value) 314 * @rcd: CD value (return value)
327 * @div8: Value for clk_sel bit in mod (return value) 315 * @div8: Value for clk_sel bit in mod (return value)
328 * Returns baud rate, requested baud when possible, or actual baud when there 316 * Return: baud rate, requested baud when possible, or actual baud when there
329 * was too much error, zero if no valid divisors are found. 317 * was too much error, zero if no valid divisors are found.
330 * 318 *
331 * Formula to obtain baud rate is 319 * Formula to obtain baud rate is
@@ -338,8 +326,8 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
338 * baud rate generate register 326 * baud rate generate register
339 * baud rate clock divisor register 327 * baud rate clock divisor register
340 */ 328 */
341static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud, 329static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
342 u32 *rbdiv, u32 *rcd, int *div8) 330 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
343{ 331{
344 u32 cd, bdiv; 332 u32 cd, bdiv;
345 unsigned int calc_baud; 333 unsigned int calc_baud;
@@ -347,16 +335,16 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
347 unsigned int bauderror; 335 unsigned int bauderror;
348 unsigned int besterror = ~0; 336 unsigned int besterror = ~0;
349 337
350 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) { 338 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
351 *div8 = 1; 339 *div8 = 1;
352 clk /= 8; 340 clk /= 8;
353 } else { 341 } else {
354 *div8 = 0; 342 *div8 = 0;
355 } 343 }
356 344
357 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) { 345 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
358 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 346 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
359 if (cd < 1 || cd > XUARTPS_CD_MAX) 347 if (cd < 1 || cd > CDNS_UART_CD_MAX)
360 continue; 348 continue;
361 349
362 calc_baud = clk / (cd * (bdiv + 1)); 350 calc_baud = clk / (cd * (bdiv + 1));
@@ -381,47 +369,47 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
381} 369}
382 370
383/** 371/**
384 * xuartps_set_baud_rate - Calculate and set the baud rate 372 * cdns_uart_set_baud_rate - Calculate and set the baud rate
385 * @port: Handle to the uart port structure 373 * @port: Handle to the uart port structure
386 * @baud: Baud rate to set 374 * @baud: Baud rate to set
387 * Returns baud rate, requested baud when possible, or actual baud when there 375 * Return: baud rate, requested baud when possible, or actual baud when there
388 * was too much error, zero if no valid divisors are found. 376 * was too much error, zero if no valid divisors are found.
389 */ 377 */
390static unsigned int xuartps_set_baud_rate(struct uart_port *port, 378static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
391 unsigned int baud) 379 unsigned int baud)
392{ 380{
393 unsigned int calc_baud; 381 unsigned int calc_baud;
394 u32 cd = 0, bdiv = 0; 382 u32 cd = 0, bdiv = 0;
395 u32 mreg; 383 u32 mreg;
396 int div8; 384 int div8;
397 struct xuartps *xuartps = port->private_data; 385 struct cdns_uart *cdns_uart = port->private_data;
398 386
399 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 387 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
400 &div8); 388 &div8);
401 389
402 /* Write new divisors to hardware */ 390 /* Write new divisors to hardware */
403 mreg = xuartps_readl(XUARTPS_MR_OFFSET); 391 mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
404 if (div8) 392 if (div8)
405 mreg |= XUARTPS_MR_CLKSEL; 393 mreg |= CDNS_UART_MR_CLKSEL;
406 else 394 else
407 mreg &= ~XUARTPS_MR_CLKSEL; 395 mreg &= ~CDNS_UART_MR_CLKSEL;
408 xuartps_writel(mreg, XUARTPS_MR_OFFSET); 396 cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET);
409 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET); 397 cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET);
410 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET); 398 cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET);
411 xuartps->baud = baud; 399 cdns_uart->baud = baud;
412 400
413 return calc_baud; 401 return calc_baud;
414} 402}
415 403
416#ifdef CONFIG_COMMON_CLK 404#ifdef CONFIG_COMMON_CLK
417/** 405/**
418 * xuartps_clk_notitifer_cb - Clock notifier callback 406 * cdns_uart_clk_notitifer_cb - Clock notifier callback
419 * @nb: Notifier block 407 * @nb: Notifier block
420 * @event: Notify event 408 * @event: Notify event
421 * @data: Notifier data 409 * @data: Notifier data
422 * Returns NOTIFY_OK on success, NOTIFY_BAD on error. 410 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
423 */ 411 */
424static int xuartps_clk_notifier_cb(struct notifier_block *nb, 412static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
425 unsigned long event, void *data) 413 unsigned long event, void *data)
426{ 414{
427 u32 ctrl_reg; 415 u32 ctrl_reg;
@@ -429,35 +417,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
429 int locked = 0; 417 int locked = 0;
430 struct clk_notifier_data *ndata = data; 418 struct clk_notifier_data *ndata = data;
431 unsigned long flags = 0; 419 unsigned long flags = 0;
432 struct xuartps *xuartps = to_xuartps(nb); 420 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
433 421
434 port = xuartps->port; 422 port = cdns_uart->port;
435 if (port->suspended) 423 if (port->suspended)
436 return NOTIFY_OK; 424 return NOTIFY_OK;
437 425
438 switch (event) { 426 switch (event) {
439 case PRE_RATE_CHANGE: 427 case PRE_RATE_CHANGE:
440 { 428 {
441 u32 bdiv; 429 u32 bdiv, cd;
442 u32 cd;
443 int div8; 430 int div8;
444 431
445 /* 432 /*
446 * Find out if current baud-rate can be achieved with new clock 433 * Find out if current baud-rate can be achieved with new clock
447 * frequency. 434 * frequency.
448 */ 435 */
449 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud, 436 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
450 &bdiv, &cd, &div8)) 437 &bdiv, &cd, &div8)) {
438 dev_warn(port->dev, "clock rate change rejected\n");
451 return NOTIFY_BAD; 439 return NOTIFY_BAD;
440 }
452 441
453 spin_lock_irqsave(&xuartps->port->lock, flags); 442 spin_lock_irqsave(&cdns_uart->port->lock, flags);
454 443
455 /* Disable the TX and RX to set baud rate */ 444 /* Disable the TX and RX to set baud rate */
456 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 445 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
457 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 446 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
458 XUARTPS_CR_OFFSET); 447 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
459 448
460 spin_unlock_irqrestore(&xuartps->port->lock, flags); 449 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
461 450
462 return NOTIFY_OK; 451 return NOTIFY_OK;
463 } 452 }
@@ -467,25 +456,25 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
467 * frequency. 456 * frequency.
468 */ 457 */
469 458
470 spin_lock_irqsave(&xuartps->port->lock, flags); 459 spin_lock_irqsave(&cdns_uart->port->lock, flags);
471 460
472 locked = 1; 461 locked = 1;
473 port->uartclk = ndata->new_rate; 462 port->uartclk = ndata->new_rate;
474 463
475 xuartps->baud = xuartps_set_baud_rate(xuartps->port, 464 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
476 xuartps->baud); 465 cdns_uart->baud);
477 /* fall through */ 466 /* fall through */
478 case ABORT_RATE_CHANGE: 467 case ABORT_RATE_CHANGE:
479 if (!locked) 468 if (!locked)
480 spin_lock_irqsave(&xuartps->port->lock, flags); 469 spin_lock_irqsave(&cdns_uart->port->lock, flags);
481 470
482 /* Set TX/RX Reset */ 471 /* Set TX/RX Reset */
483 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 472 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
484 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 473 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
485 XUARTPS_CR_OFFSET); 474 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
486 475
487 while (xuartps_readl(XUARTPS_CR_OFFSET) & 476 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
488 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) 477 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
489 cpu_relax(); 478 cpu_relax();
490 479
491 /* 480 /*
@@ -493,14 +482,13 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
493 * enable bit and RX enable bit to enable the transmitter and 482 * enable bit and RX enable bit to enable the transmitter and
494 * receiver. 483 * receiver.
495 */ 484 */
496 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 485 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
497 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 486 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
498 xuartps_writel( 487 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
499 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | 488 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
500 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 489 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
501 XUARTPS_CR_OFFSET);
502 490
503 spin_unlock_irqrestore(&xuartps->port->lock, flags); 491 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
504 492
505 return NOTIFY_OK; 493 return NOTIFY_OK;
506 default: 494 default:
@@ -509,40 +497,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
509} 497}
510#endif 498#endif
511 499
512/*----------------------Uart Operations---------------------------*/
513
514/** 500/**
515 * xuartps_start_tx - Start transmitting bytes 501 * cdns_uart_start_tx - Start transmitting bytes
516 * @port: Handle to the uart port structure 502 * @port: Handle to the uart port structure
517 * 503 */
518 **/ 504static void cdns_uart_start_tx(struct uart_port *port)
519static void xuartps_start_tx(struct uart_port *port)
520{ 505{
521 unsigned int status, numbytes = port->fifosize; 506 unsigned int status, numbytes = port->fifosize;
522 507
523 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 508 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
524 return; 509 return;
525 510
526 status = xuartps_readl(XUARTPS_CR_OFFSET); 511 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
527 /* Set the TX enable bit and clear the TX disable bit to enable the 512 /* Set the TX enable bit and clear the TX disable bit to enable the
528 * transmitter. 513 * transmitter.
529 */ 514 */
530 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 515 cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
531 XUARTPS_CR_OFFSET); 516 CDNS_UART_CR_OFFSET);
532
533 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
534 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
535 517
518 while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
519 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
536 /* Break if no more data available in the UART buffer */ 520 /* Break if no more data available in the UART buffer */
537 if (uart_circ_empty(&port->state->xmit)) 521 if (uart_circ_empty(&port->state->xmit))
538 break; 522 break;
539 523
540 /* Get the data from the UART circular buffer and 524 /* Get the data from the UART circular buffer and
541 * write it to the xuartps's TX_FIFO register. 525 * write it to the cdns_uart's TX_FIFO register.
542 */ 526 */
543 xuartps_writel( 527 cdns_uart_writel(
544 port->state->xmit.buf[port->state->xmit.tail], 528 port->state->xmit.buf[port->state->xmit.tail],
545 XUARTPS_FIFO_OFFSET); 529 CDNS_UART_FIFO_OFFSET);
546 port->icount.tx++; 530 port->icount.tx++;
547 531
548 /* Adjust the tail of the UART buffer and wrap 532 /* Adjust the tail of the UART buffer and wrap
@@ -551,94 +535,90 @@ static void xuartps_start_tx(struct uart_port *port)
551 port->state->xmit.tail = (port->state->xmit.tail + 1) & 535 port->state->xmit.tail = (port->state->xmit.tail + 1) &
552 (UART_XMIT_SIZE - 1); 536 (UART_XMIT_SIZE - 1);
553 } 537 }
554 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET); 538 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET);
555 /* Enable the TX Empty interrupt */ 539 /* Enable the TX Empty interrupt */
556 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); 540 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET);
557 541
558 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 542 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(port); 543 uart_write_wakeup(port);
560} 544}
561 545
562/** 546/**
563 * xuartps_stop_tx - Stop TX 547 * cdns_uart_stop_tx - Stop TX
564 * @port: Handle to the uart port structure 548 * @port: Handle to the uart port structure
565 * 549 */
566 **/ 550static void cdns_uart_stop_tx(struct uart_port *port)
567static void xuartps_stop_tx(struct uart_port *port)
568{ 551{
569 unsigned int regval; 552 unsigned int regval;
570 553
571 regval = xuartps_readl(XUARTPS_CR_OFFSET); 554 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
572 regval |= XUARTPS_CR_TX_DIS; 555 regval |= CDNS_UART_CR_TX_DIS;
573 /* Disable the transmitter */ 556 /* Disable the transmitter */
574 xuartps_writel(regval, XUARTPS_CR_OFFSET); 557 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
575} 558}
576 559
577/** 560/**
578 * xuartps_stop_rx - Stop RX 561 * cdns_uart_stop_rx - Stop RX
579 * @port: Handle to the uart port structure 562 * @port: Handle to the uart port structure
580 * 563 */
581 **/ 564static void cdns_uart_stop_rx(struct uart_port *port)
582static void xuartps_stop_rx(struct uart_port *port)
583{ 565{
584 unsigned int regval; 566 unsigned int regval;
585 567
586 regval = xuartps_readl(XUARTPS_CR_OFFSET); 568 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
587 regval |= XUARTPS_CR_RX_DIS; 569 regval |= CDNS_UART_CR_RX_DIS;
588 /* Disable the receiver */ 570 /* Disable the receiver */
589 xuartps_writel(regval, XUARTPS_CR_OFFSET); 571 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
590} 572}
591 573
592/** 574/**
593 * xuartps_tx_empty - Check whether TX is empty 575 * cdns_uart_tx_empty - Check whether TX is empty
594 * @port: Handle to the uart port structure 576 * @port: Handle to the uart port structure
595 * 577 *
596 * Returns TIOCSER_TEMT on success, 0 otherwise 578 * Return: TIOCSER_TEMT on success, 0 otherwise
597 **/ 579 */
598static unsigned int xuartps_tx_empty(struct uart_port *port) 580static unsigned int cdns_uart_tx_empty(struct uart_port *port)
599{ 581{
600 unsigned int status; 582 unsigned int status;
601 583
602 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; 584 status = cdns_uart_readl(CDNS_UART_ISR_OFFSET) & CDNS_UART_IXR_TXEMPTY;
603 return status ? TIOCSER_TEMT : 0; 585 return status ? TIOCSER_TEMT : 0;
604} 586}
605 587
606/** 588/**
607 * xuartps_break_ctl - Based on the input ctl we have to start or stop 589 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
608 * transmitting char breaks 590 * transmitting char breaks
609 * @port: Handle to the uart port structure 591 * @port: Handle to the uart port structure
610 * @ctl: Value based on which start or stop decision is taken 592 * @ctl: Value based on which start or stop decision is taken
611 * 593 */
612 **/ 594static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
613static void xuartps_break_ctl(struct uart_port *port, int ctl)
614{ 595{
615 unsigned int status; 596 unsigned int status;
616 unsigned long flags; 597 unsigned long flags;
617 598
618 spin_lock_irqsave(&port->lock, flags); 599 spin_lock_irqsave(&port->lock, flags);
619 600
620 status = xuartps_readl(XUARTPS_CR_OFFSET); 601 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
621 602
622 if (ctl == -1) 603 if (ctl == -1)
623 xuartps_writel(XUARTPS_CR_STARTBRK | status, 604 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status,
624 XUARTPS_CR_OFFSET); 605 CDNS_UART_CR_OFFSET);
625 else { 606 else {
626 if ((status & XUARTPS_CR_STOPBRK) == 0) 607 if ((status & CDNS_UART_CR_STOPBRK) == 0)
627 xuartps_writel(XUARTPS_CR_STOPBRK | status, 608 cdns_uart_writel(CDNS_UART_CR_STOPBRK | status,
628 XUARTPS_CR_OFFSET); 609 CDNS_UART_CR_OFFSET);
629 } 610 }
630 spin_unlock_irqrestore(&port->lock, flags); 611 spin_unlock_irqrestore(&port->lock, flags);
631} 612}
632 613
633/** 614/**
634 * xuartps_set_termios - termios operations, handling data length, parity, 615 * cdns_uart_set_termios - termios operations, handling data length, parity,
635 * stop bits, flow control, baud rate 616 * stop bits, flow control, baud rate
636 * @port: Handle to the uart port structure 617 * @port: Handle to the uart port structure
637 * @termios: Handle to the input termios structure 618 * @termios: Handle to the input termios structure
638 * @old: Values of the previously saved termios structure 619 * @old: Values of the previously saved termios structure
639 * 620 */
640 **/ 621static void cdns_uart_set_termios(struct uart_port *port,
641static void xuartps_set_termios(struct uart_port *port,
642 struct ktermios *termios, struct ktermios *old) 622 struct ktermios *termios, struct ktermios *old)
643{ 623{
644 unsigned int cval = 0; 624 unsigned int cval = 0;
@@ -649,81 +629,79 @@ static void xuartps_set_termios(struct uart_port *port,
649 spin_lock_irqsave(&port->lock, flags); 629 spin_lock_irqsave(&port->lock, flags);
650 630
651 /* Empty the receive FIFO 1st before making changes */ 631 /* Empty the receive FIFO 1st before making changes */
652 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 632 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
653 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 633 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
654 xuartps_readl(XUARTPS_FIFO_OFFSET); 634 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
655 } 635 }
656 636
657 /* Disable the TX and RX to set baud rate */ 637 /* Disable the TX and RX to set baud rate */
658 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 638 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
659 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 639 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
660 XUARTPS_CR_OFFSET); 640 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
661 641
662 /* 642 /*
663 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 643 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
664 * min and max baud should be calculated here based on port->uartclk. 644 * min and max baud should be calculated here based on port->uartclk.
665 * this way we get a valid baud and can safely call set_baud() 645 * this way we get a valid baud and can safely call set_baud()
666 */ 646 */
667 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8); 647 minbaud = port->uartclk /
668 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1); 648 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
649 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
669 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 650 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
670 baud = xuartps_set_baud_rate(port, baud); 651 baud = cdns_uart_set_baud_rate(port, baud);
671 if (tty_termios_baud_rate(termios)) 652 if (tty_termios_baud_rate(termios))
672 tty_termios_encode_baud_rate(termios, baud, baud); 653 tty_termios_encode_baud_rate(termios, baud, baud);
673 654
674 /* 655 /* Update the per-port timeout. */
675 * Update the per-port timeout.
676 */
677 uart_update_timeout(port, termios->c_cflag, baud); 656 uart_update_timeout(port, termios->c_cflag, baud);
678 657
679 /* Set TX/RX Reset */ 658 /* Set TX/RX Reset */
680 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 659 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
681 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 660 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
682 XUARTPS_CR_OFFSET); 661 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
683 662
684 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 663 /*
685 664 * Clear the RX disable and TX disable bits and then set the TX enable
686 /* Clear the RX disable and TX disable bits and then set the TX enable
687 * bit and RX enable bit to enable the transmitter and receiver. 665 * bit and RX enable bit to enable the transmitter and receiver.
688 */ 666 */
689 xuartps_writel( 667 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
690 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 668 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
691 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 669 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
692 XUARTPS_CR_OFFSET); 670 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
693 671
694 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 672 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
695 673
696 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | 674 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
697 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; 675 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
698 port->ignore_status_mask = 0; 676 port->ignore_status_mask = 0;
699 677
700 if (termios->c_iflag & INPCK) 678 if (termios->c_iflag & INPCK)
701 port->read_status_mask |= XUARTPS_IXR_PARITY | 679 port->read_status_mask |= CDNS_UART_IXR_PARITY |
702 XUARTPS_IXR_FRAMING; 680 CDNS_UART_IXR_FRAMING;
703 681
704 if (termios->c_iflag & IGNPAR) 682 if (termios->c_iflag & IGNPAR)
705 port->ignore_status_mask |= XUARTPS_IXR_PARITY | 683 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
706 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 684 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
707 685
708 /* ignore all characters if CREAD is not set */ 686 /* ignore all characters if CREAD is not set */
709 if ((termios->c_cflag & CREAD) == 0) 687 if ((termios->c_cflag & CREAD) == 0)
710 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | 688 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
711 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | 689 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
712 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 690 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
713 691
714 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); 692 mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
715 693
716 /* Handling Data Size */ 694 /* Handling Data Size */
717 switch (termios->c_cflag & CSIZE) { 695 switch (termios->c_cflag & CSIZE) {
718 case CS6: 696 case CS6:
719 cval |= XUARTPS_MR_CHARLEN_6_BIT; 697 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
720 break; 698 break;
721 case CS7: 699 case CS7:
722 cval |= XUARTPS_MR_CHARLEN_7_BIT; 700 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
723 break; 701 break;
724 default: 702 default:
725 case CS8: 703 case CS8:
726 cval |= XUARTPS_MR_CHARLEN_8_BIT; 704 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
727 termios->c_cflag &= ~CSIZE; 705 termios->c_cflag &= ~CSIZE;
728 termios->c_cflag |= CS8; 706 termios->c_cflag |= CS8;
729 break; 707 break;
@@ -731,134 +709,135 @@ static void xuartps_set_termios(struct uart_port *port,
731 709
732 /* Handling Parity and Stop Bits length */ 710 /* Handling Parity and Stop Bits length */
733 if (termios->c_cflag & CSTOPB) 711 if (termios->c_cflag & CSTOPB)
734 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 712 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
735 else 713 else
736 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 714 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
737 715
738 if (termios->c_cflag & PARENB) { 716 if (termios->c_cflag & PARENB) {
739 /* Mark or Space parity */ 717 /* Mark or Space parity */
740 if (termios->c_cflag & CMSPAR) { 718 if (termios->c_cflag & CMSPAR) {
741 if (termios->c_cflag & PARODD) 719 if (termios->c_cflag & PARODD)
742 cval |= XUARTPS_MR_PARITY_MARK; 720 cval |= CDNS_UART_MR_PARITY_MARK;
743 else 721 else
744 cval |= XUARTPS_MR_PARITY_SPACE; 722 cval |= CDNS_UART_MR_PARITY_SPACE;
745 } else { 723 } else {
746 if (termios->c_cflag & PARODD) 724 if (termios->c_cflag & PARODD)
747 cval |= XUARTPS_MR_PARITY_ODD; 725 cval |= CDNS_UART_MR_PARITY_ODD;
748 else 726 else
749 cval |= XUARTPS_MR_PARITY_EVEN; 727 cval |= CDNS_UART_MR_PARITY_EVEN;
750 } 728 }
751 } else { 729 } else {
752 cval |= XUARTPS_MR_PARITY_NONE; 730 cval |= CDNS_UART_MR_PARITY_NONE;
753 } 731 }
754 cval |= mode_reg & 1; 732 cval |= mode_reg & 1;
755 xuartps_writel(cval, XUARTPS_MR_OFFSET); 733 cdns_uart_writel(cval, CDNS_UART_MR_OFFSET);
756 734
757 spin_unlock_irqrestore(&port->lock, flags); 735 spin_unlock_irqrestore(&port->lock, flags);
758} 736}
759 737
760/** 738/**
761 * xuartps_startup - Called when an application opens a xuartps port 739 * cdns_uart_startup - Called when an application opens a cdns_uart port
762 * @port: Handle to the uart port structure 740 * @port: Handle to the uart port structure
763 * 741 *
764 * Returns 0 on success, negative error otherwise 742 * Return: 0 on success, negative errno otherwise
765 **/ 743 */
766static int xuartps_startup(struct uart_port *port) 744static int cdns_uart_startup(struct uart_port *port)
767{ 745{
768 unsigned int retval = 0, status = 0; 746 unsigned int retval = 0, status = 0;
769 747
770 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, 748 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
771 (void *)port); 749 (void *)port);
772 if (retval) 750 if (retval)
773 return retval; 751 return retval;
774 752
775 /* Disable the TX and RX */ 753 /* Disable the TX and RX */
776 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 754 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
777 XUARTPS_CR_OFFSET); 755 CDNS_UART_CR_OFFSET);
778 756
779 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 757 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
780 * no break chars. 758 * no break chars.
781 */ 759 */
782 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, 760 cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
783 XUARTPS_CR_OFFSET); 761 CDNS_UART_CR_OFFSET);
784 762
785 status = xuartps_readl(XUARTPS_CR_OFFSET); 763 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
786 764
787 /* Clear the RX disable and TX disable bits and then set the TX enable 765 /* Clear the RX disable and TX disable bits and then set the TX enable
788 * bit and RX enable bit to enable the transmitter and receiver. 766 * bit and RX enable bit to enable the transmitter and receiver.
789 */ 767 */
790 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 768 cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
791 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | 769 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
792 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); 770 CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET);
793 771
794 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 772 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
795 * no parity. 773 * no parity.
796 */ 774 */
797 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT 775 cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
798 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, 776 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
799 XUARTPS_MR_OFFSET); 777 CDNS_UART_MR_OFFSET);
800 778
801 /* 779 /*
802 * Set the RX FIFO Trigger level to use most of the FIFO, but it 780 * Set the RX FIFO Trigger level to use most of the FIFO, but it
803 * can be tuned with a module parameter 781 * can be tuned with a module parameter
804 */ 782 */
805 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); 783 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
806 784
807 /* 785 /*
808 * Receive Timeout register is enabled but it 786 * Receive Timeout register is enabled but it
809 * can be tuned with a module parameter 787 * can be tuned with a module parameter
810 */ 788 */
811 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 789 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
812 790
813 /* Clear out any pending interrupts before enabling them */ 791 /* Clear out any pending interrupts before enabling them */
814 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); 792 cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET),
793 CDNS_UART_ISR_OFFSET);
815 794
816 /* Set the Interrupt Registers with desired interrupts */ 795 /* Set the Interrupt Registers with desired interrupts */
817 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | 796 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
818 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | 797 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
819 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 798 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
799 CDNS_UART_IER_OFFSET);
820 800
821 return retval; 801 return retval;
822} 802}
823 803
824/** 804/**
825 * xuartps_shutdown - Called when an application closes a xuartps port 805 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
826 * @port: Handle to the uart port structure 806 * @port: Handle to the uart port structure
827 * 807 */
828 **/ 808static void cdns_uart_shutdown(struct uart_port *port)
829static void xuartps_shutdown(struct uart_port *port)
830{ 809{
831 int status; 810 int status;
832 811
833 /* Disable interrupts */ 812 /* Disable interrupts */
834 status = xuartps_readl(XUARTPS_IMR_OFFSET); 813 status = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
835 xuartps_writel(status, XUARTPS_IDR_OFFSET); 814 cdns_uart_writel(status, CDNS_UART_IDR_OFFSET);
836 815
837 /* Disable the TX and RX */ 816 /* Disable the TX and RX */
838 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 817 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
839 XUARTPS_CR_OFFSET); 818 CDNS_UART_CR_OFFSET);
840 free_irq(port->irq, port); 819 free_irq(port->irq, port);
841} 820}
842 821
843/** 822/**
844 * xuartps_type - Set UART type to xuartps port 823 * cdns_uart_type - Set UART type to cdns_uart port
845 * @port: Handle to the uart port structure 824 * @port: Handle to the uart port structure
846 * 825 *
847 * Returns string on success, NULL otherwise 826 * Return: string on success, NULL otherwise
848 **/ 827 */
849static const char *xuartps_type(struct uart_port *port) 828static const char *cdns_uart_type(struct uart_port *port)
850{ 829{
851 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; 830 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
852} 831}
853 832
854/** 833/**
855 * xuartps_verify_port - Verify the port params 834 * cdns_uart_verify_port - Verify the port params
856 * @port: Handle to the uart port structure 835 * @port: Handle to the uart port structure
857 * @ser: Handle to the structure whose members are compared 836 * @ser: Handle to the structure whose members are compared
858 * 837 *
859 * Returns 0 if success otherwise -EINVAL 838 * Return: 0 on success, negative errno otherwise.
860 **/ 839 */
861static int xuartps_verify_port(struct uart_port *port, 840static int cdns_uart_verify_port(struct uart_port *port,
862 struct serial_struct *ser) 841 struct serial_struct *ser)
863{ 842{
864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 843 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
@@ -875,187 +854,170 @@ static int xuartps_verify_port(struct uart_port *port,
875} 854}
876 855
877/** 856/**
878 * xuartps_request_port - Claim the memory region attached to xuartps port, 857 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
879 * called when the driver adds a xuartps port via 858 * called when the driver adds a cdns_uart port via
880 * uart_add_one_port() 859 * uart_add_one_port()
881 * @port: Handle to the uart port structure 860 * @port: Handle to the uart port structure
882 * 861 *
883 * Returns 0, -ENOMEM if request fails 862 * Return: 0 on success, negative errno otherwise.
884 **/ 863 */
885static int xuartps_request_port(struct uart_port *port) 864static int cdns_uart_request_port(struct uart_port *port)
886{ 865{
887 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, 866 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
888 XUARTPS_NAME)) { 867 CDNS_UART_NAME)) {
889 return -ENOMEM; 868 return -ENOMEM;
890 } 869 }
891 870
892 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); 871 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
893 if (!port->membase) { 872 if (!port->membase) {
894 dev_err(port->dev, "Unable to map registers\n"); 873 dev_err(port->dev, "Unable to map registers\n");
895 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 874 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
896 return -ENOMEM; 875 return -ENOMEM;
897 } 876 }
898 return 0; 877 return 0;
899} 878}
900 879
901/** 880/**
902 * xuartps_release_port - Release the memory region attached to a xuartps 881 * cdns_uart_release_port - Release UART port
903 * port, called when the driver removes a xuartps
904 * port via uart_remove_one_port().
905 * @port: Handle to the uart port structure 882 * @port: Handle to the uart port structure
906 * 883 *
907 **/ 884 * Release the memory region attached to a cdns_uart port. Called when the
908static void xuartps_release_port(struct uart_port *port) 885 * driver removes a cdns_uart port via uart_remove_one_port().
886 */
887static void cdns_uart_release_port(struct uart_port *port)
909{ 888{
910 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 889 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
911 iounmap(port->membase); 890 iounmap(port->membase);
912 port->membase = NULL; 891 port->membase = NULL;
913} 892}
914 893
915/** 894/**
916 * xuartps_config_port - Configure xuartps, called when the driver adds a 895 * cdns_uart_config_port - Configure UART port
917 * xuartps port
918 * @port: Handle to the uart port structure 896 * @port: Handle to the uart port structure
919 * @flags: If any 897 * @flags: If any
920 * 898 */
921 **/ 899static void cdns_uart_config_port(struct uart_port *port, int flags)
922static void xuartps_config_port(struct uart_port *port, int flags)
923{ 900{
924 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) 901 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
925 port->type = PORT_XUARTPS; 902 port->type = PORT_XUARTPS;
926} 903}
927 904
928/** 905/**
929 * xuartps_get_mctrl - Get the modem control state 906 * cdns_uart_get_mctrl - Get the modem control state
930 *
931 * @port: Handle to the uart port structure 907 * @port: Handle to the uart port structure
932 * 908 *
933 * Returns the modem control state 909 * Return: the modem control state
934 * 910 */
935 **/ 911static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
936static unsigned int xuartps_get_mctrl(struct uart_port *port)
937{ 912{
938 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 913 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
939} 914}
940 915
941static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) 916static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
942{ 917{
943 /* N/A */ 918 /* N/A */
944} 919}
945 920
946static void xuartps_enable_ms(struct uart_port *port) 921static void cdns_uart_enable_ms(struct uart_port *port)
947{ 922{
948 /* N/A */ 923 /* N/A */
949} 924}
950 925
951#ifdef CONFIG_CONSOLE_POLL 926#ifdef CONFIG_CONSOLE_POLL
952static int xuartps_poll_get_char(struct uart_port *port) 927static int cdns_uart_poll_get_char(struct uart_port *port)
953{ 928{
954 u32 imr; 929 u32 imr;
955 int c; 930 int c;
956 931
957 /* Disable all interrupts */ 932 /* Disable all interrupts */
958 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 933 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
959 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 934 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
960 935
961 /* Check if FIFO is empty */ 936 /* Check if FIFO is empty */
962 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) 937 if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
963 c = NO_POLL_CHAR; 938 c = NO_POLL_CHAR;
964 else /* Read a character */ 939 else /* Read a character */
965 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET); 940 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
966 941
967 /* Enable interrupts */ 942 /* Enable interrupts */
968 xuartps_writel(imr, XUARTPS_IER_OFFSET); 943 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
969 944
970 return c; 945 return c;
971} 946}
972 947
973static void xuartps_poll_put_char(struct uart_port *port, unsigned char c) 948static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
974{ 949{
975 u32 imr; 950 u32 imr;
976 951
977 /* Disable all interrupts */ 952 /* Disable all interrupts */
978 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 953 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
979 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 954 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
980 955
981 /* Wait until FIFO is empty */ 956 /* Wait until FIFO is empty */
982 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) 957 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
983 cpu_relax(); 958 cpu_relax();
984 959
985 /* Write a character */ 960 /* Write a character */
986 xuartps_writel(c, XUARTPS_FIFO_OFFSET); 961 cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET);
987 962
988 /* Wait until FIFO is empty */ 963 /* Wait until FIFO is empty */
989 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) 964 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
990 cpu_relax(); 965 cpu_relax();
991 966
992 /* Enable interrupts */ 967 /* Enable interrupts */
993 xuartps_writel(imr, XUARTPS_IER_OFFSET); 968 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
994 969
995 return; 970 return;
996} 971}
997#endif 972#endif
998 973
999/** The UART operations structure 974static struct uart_ops cdns_uart_ops = {
1000 */ 975 .set_mctrl = cdns_uart_set_mctrl,
1001static struct uart_ops xuartps_ops = { 976 .get_mctrl = cdns_uart_get_mctrl,
1002 .set_mctrl = xuartps_set_mctrl, 977 .enable_ms = cdns_uart_enable_ms,
1003 .get_mctrl = xuartps_get_mctrl, 978 .start_tx = cdns_uart_start_tx,
1004 .enable_ms = xuartps_enable_ms, 979 .stop_tx = cdns_uart_stop_tx,
1005 980 .stop_rx = cdns_uart_stop_rx,
1006 .start_tx = xuartps_start_tx, /* Start transmitting */ 981 .tx_empty = cdns_uart_tx_empty,
1007 .stop_tx = xuartps_stop_tx, /* Stop transmission */ 982 .break_ctl = cdns_uart_break_ctl,
1008 .stop_rx = xuartps_stop_rx, /* Stop reception */ 983 .set_termios = cdns_uart_set_termios,
1009 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ 984 .startup = cdns_uart_startup,
1010 .break_ctl = xuartps_break_ctl, /* Start/stop 985 .shutdown = cdns_uart_shutdown,
1011 * transmitting break 986 .type = cdns_uart_type,
1012 */ 987 .verify_port = cdns_uart_verify_port,
1013 .set_termios = xuartps_set_termios, /* Set termios */ 988 .request_port = cdns_uart_request_port,
1014 .startup = xuartps_startup, /* App opens xuartps */ 989 .release_port = cdns_uart_release_port,
1015 .shutdown = xuartps_shutdown, /* App closes xuartps */ 990 .config_port = cdns_uart_config_port,
1016 .type = xuartps_type, /* Set UART type */
1017 .verify_port = xuartps_verify_port, /* Verification of port
1018 * params
1019 */
1020 .request_port = xuartps_request_port, /* Claim resources
1021 * associated with a
1022 * xuartps port
1023 */
1024 .release_port = xuartps_release_port, /* Release resources
1025 * associated with a
1026 * xuartps port
1027 */
1028 .config_port = xuartps_config_port, /* Configure when driver
1029 * adds a xuartps port
1030 */
1031#ifdef CONFIG_CONSOLE_POLL 991#ifdef CONFIG_CONSOLE_POLL
1032 .poll_get_char = xuartps_poll_get_char, 992 .poll_get_char = cdns_uart_poll_get_char,
1033 .poll_put_char = xuartps_poll_put_char, 993 .poll_put_char = cdns_uart_poll_put_char,
1034#endif 994#endif
1035}; 995};
1036 996
1037static struct uart_port xuartps_port[2]; 997static struct uart_port cdns_uart_port[2];
1038 998
1039/** 999/**
1040 * xuartps_get_port - Configure the port from the platform device resource 1000 * cdns_uart_get_port - Configure the port from platform device resource info
1041 * info 1001 * @id: Port id
1042 * 1002 *
1043 * Returns a pointer to a uart_port or NULL for failure 1003 * Return: a pointer to a uart_port or NULL for failure
1044 **/ 1004 */
1045static struct uart_port *xuartps_get_port(void) 1005static struct uart_port *cdns_uart_get_port(int id)
1046{ 1006{
1047 struct uart_port *port; 1007 struct uart_port *port;
1048 int id;
1049 1008
1050 /* Find the next unused port */ 1009 /* Try the given port id if failed use default method */
1051 for (id = 0; id < XUARTPS_NR_PORTS; id++) 1010 if (cdns_uart_port[id].mapbase != 0) {
1052 if (xuartps_port[id].mapbase == 0) 1011 /* Find the next unused port */
1053 break; 1012 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1013 if (cdns_uart_port[id].mapbase == 0)
1014 break;
1015 }
1054 1016
1055 if (id >= XUARTPS_NR_PORTS) 1017 if (id >= CDNS_UART_NR_PORTS)
1056 return NULL; 1018 return NULL;
1057 1019
1058 port = &xuartps_port[id]; 1020 port = &cdns_uart_port[id];
1059 1021
1060 /* At this point, we've got an empty uart_port struct, initialize it */ 1022 /* At this point, we've got an empty uart_port struct, initialize it */
1061 spin_lock_init(&port->lock); 1023 spin_lock_init(&port->lock);
@@ -1065,50 +1027,46 @@ static struct uart_port *xuartps_get_port(void)
1065 port->type = PORT_UNKNOWN; 1027 port->type = PORT_UNKNOWN;
1066 port->iotype = UPIO_MEM32; 1028 port->iotype = UPIO_MEM32;
1067 port->flags = UPF_BOOT_AUTOCONF; 1029 port->flags = UPF_BOOT_AUTOCONF;
1068 port->ops = &xuartps_ops; 1030 port->ops = &cdns_uart_ops;
1069 port->fifosize = XUARTPS_FIFO_SIZE; 1031 port->fifosize = CDNS_UART_FIFO_SIZE;
1070 port->line = id; 1032 port->line = id;
1071 port->dev = NULL; 1033 port->dev = NULL;
1072 return port; 1034 return port;
1073} 1035}
1074 1036
1075/*-----------------------Console driver operations--------------------------*/
1076
1077#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1037#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1078/** 1038/**
1079 * xuartps_console_wait_tx - Wait for the TX to be full 1039 * cdns_uart_console_wait_tx - Wait for the TX to be full
1080 * @port: Handle to the uart port structure 1040 * @port: Handle to the uart port structure
1081 * 1041 */
1082 **/ 1042static void cdns_uart_console_wait_tx(struct uart_port *port)
1083static void xuartps_console_wait_tx(struct uart_port *port)
1084{ 1043{
1085 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) 1044 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)
1086 != XUARTPS_SR_TXEMPTY) 1045 != CDNS_UART_SR_TXEMPTY)
1087 barrier(); 1046 barrier();
1088} 1047}
1089 1048
1090/** 1049/**
1091 * xuartps_console_putchar - write the character to the FIFO buffer 1050 * cdns_uart_console_putchar - write the character to the FIFO buffer
1092 * @port: Handle to the uart port structure 1051 * @port: Handle to the uart port structure
1093 * @ch: Character to be written 1052 * @ch: Character to be written
1094 * 1053 */
1095 **/ 1054static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1096static void xuartps_console_putchar(struct uart_port *port, int ch)
1097{ 1055{
1098 xuartps_console_wait_tx(port); 1056 cdns_uart_console_wait_tx(port);
1099 xuartps_writel(ch, XUARTPS_FIFO_OFFSET); 1057 cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET);
1100} 1058}
1101 1059
1102/** 1060/**
1103 * xuartps_console_write - perform write operation 1061 * cdns_uart_console_write - perform write operation
1104 * @port: Handle to the uart port structure 1062 * @co: Console handle
1105 * @s: Pointer to character array 1063 * @s: Pointer to character array
1106 * @count: No of characters 1064 * @count: No of characters
1107 **/ 1065 */
1108static void xuartps_console_write(struct console *co, const char *s, 1066static void cdns_uart_console_write(struct console *co, const char *s,
1109 unsigned int count) 1067 unsigned int count)
1110{ 1068{
1111 struct uart_port *port = &xuartps_port[co->index]; 1069 struct uart_port *port = &cdns_uart_port[co->index];
1112 unsigned long flags; 1070 unsigned long flags;
1113 unsigned int imr, ctrl; 1071 unsigned int imr, ctrl;
1114 int locked = 1; 1072 int locked = 1;
@@ -1119,49 +1077,45 @@ static void xuartps_console_write(struct console *co, const char *s,
1119 spin_lock_irqsave(&port->lock, flags); 1077 spin_lock_irqsave(&port->lock, flags);
1120 1078
1121 /* save and disable interrupt */ 1079 /* save and disable interrupt */
1122 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 1080 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
1123 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 1081 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
1124 1082
1125 /* 1083 /*
1126 * Make sure that the tx part is enabled. Set the TX enable bit and 1084 * Make sure that the tx part is enabled. Set the TX enable bit and
1127 * clear the TX disable bit to enable the transmitter. 1085 * clear the TX disable bit to enable the transmitter.
1128 */ 1086 */
1129 ctrl = xuartps_readl(XUARTPS_CR_OFFSET); 1087 ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1130 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 1088 cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
1131 XUARTPS_CR_OFFSET); 1089 CDNS_UART_CR_OFFSET);
1132 1090
1133 uart_console_write(port, s, count, xuartps_console_putchar); 1091 uart_console_write(port, s, count, cdns_uart_console_putchar);
1134 xuartps_console_wait_tx(port); 1092 cdns_uart_console_wait_tx(port);
1135 1093
1136 xuartps_writel(ctrl, XUARTPS_CR_OFFSET); 1094 cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET);
1137 1095
1138 /* restore interrupt state, it seems like there may be a h/w bug 1096 /* restore interrupt state */
1139 * in that the interrupt enable register should not need to be 1097 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
1140 * written based on the data sheet
1141 */
1142 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
1143 xuartps_writel(imr, XUARTPS_IER_OFFSET);
1144 1098
1145 if (locked) 1099 if (locked)
1146 spin_unlock_irqrestore(&port->lock, flags); 1100 spin_unlock_irqrestore(&port->lock, flags);
1147} 1101}
1148 1102
1149/** 1103/**
1150 * xuartps_console_setup - Initialize the uart to default config 1104 * cdns_uart_console_setup - Initialize the uart to default config
1151 * @co: Console handle 1105 * @co: Console handle
1152 * @options: Initial settings of uart 1106 * @options: Initial settings of uart
1153 * 1107 *
1154 * Returns 0, -ENODEV if no device 1108 * Return: 0 on success, negative errno otherwise.
1155 **/ 1109 */
1156static int __init xuartps_console_setup(struct console *co, char *options) 1110static int __init cdns_uart_console_setup(struct console *co, char *options)
1157{ 1111{
1158 struct uart_port *port = &xuartps_port[co->index]; 1112 struct uart_port *port = &cdns_uart_port[co->index];
1159 int baud = 9600; 1113 int baud = 9600;
1160 int bits = 8; 1114 int bits = 8;
1161 int parity = 'n'; 1115 int parity = 'n';
1162 int flow = 'n'; 1116 int flow = 'n';
1163 1117
1164 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) 1118 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1165 return -EINVAL; 1119 return -EINVAL;
1166 1120
1167 if (!port->mapbase) { 1121 if (!port->mapbase) {
@@ -1175,55 +1129,53 @@ static int __init xuartps_console_setup(struct console *co, char *options)
1175 return uart_set_options(port, co, baud, parity, bits, flow); 1129 return uart_set_options(port, co, baud, parity, bits, flow);
1176} 1130}
1177 1131
1178static struct uart_driver xuartps_uart_driver; 1132static struct uart_driver cdns_uart_uart_driver;
1179 1133
1180static struct console xuartps_console = { 1134static struct console cdns_uart_console = {
1181 .name = XUARTPS_TTY_NAME, 1135 .name = CDNS_UART_TTY_NAME,
1182 .write = xuartps_console_write, 1136 .write = cdns_uart_console_write,
1183 .device = uart_console_device, 1137 .device = uart_console_device,
1184 .setup = xuartps_console_setup, 1138 .setup = cdns_uart_console_setup,
1185 .flags = CON_PRINTBUFFER, 1139 .flags = CON_PRINTBUFFER,
1186 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1140 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1187 .data = &xuartps_uart_driver, 1141 .data = &cdns_uart_uart_driver,
1188}; 1142};
1189 1143
1190/** 1144/**
1191 * xuartps_console_init - Initialization call 1145 * cdns_uart_console_init - Initialization call
1192 * 1146 *
1193 * Returns 0 on success, negative error otherwise 1147 * Return: 0 on success, negative errno otherwise
1194 **/ 1148 */
1195static int __init xuartps_console_init(void) 1149static int __init cdns_uart_console_init(void)
1196{ 1150{
1197 register_console(&xuartps_console); 1151 register_console(&cdns_uart_console);
1198 return 0; 1152 return 0;
1199} 1153}
1200 1154
1201console_initcall(xuartps_console_init); 1155console_initcall(cdns_uart_console_init);
1202 1156
1203#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1157#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1204 1158
1205/** Structure Definitions 1159static struct uart_driver cdns_uart_uart_driver = {
1206 */ 1160 .owner = THIS_MODULE,
1207static struct uart_driver xuartps_uart_driver = { 1161 .driver_name = CDNS_UART_NAME,
1208 .owner = THIS_MODULE, /* Owner */ 1162 .dev_name = CDNS_UART_TTY_NAME,
1209 .driver_name = XUARTPS_NAME, /* Driver name */ 1163 .major = CDNS_UART_MAJOR,
1210 .dev_name = XUARTPS_TTY_NAME, /* Node name */ 1164 .minor = CDNS_UART_MINOR,
1211 .major = XUARTPS_MAJOR, /* Major number */ 1165 .nr = CDNS_UART_NR_PORTS,
1212 .minor = XUARTPS_MINOR, /* Minor number */
1213 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1214#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1166#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1215 .cons = &xuartps_console, /* Console */ 1167 .cons = &cdns_uart_console,
1216#endif 1168#endif
1217}; 1169};
1218 1170
1219#ifdef CONFIG_PM_SLEEP 1171#ifdef CONFIG_PM_SLEEP
1220/** 1172/**
1221 * xuartps_suspend - suspend event 1173 * cdns_uart_suspend - suspend event
1222 * @device: Pointer to the device structure 1174 * @device: Pointer to the device structure
1223 * 1175 *
1224 * Returns 0 1176 * Return: 0
1225 */ 1177 */
1226static int xuartps_suspend(struct device *device) 1178static int cdns_uart_suspend(struct device *device)
1227{ 1179{
1228 struct uart_port *port = dev_get_drvdata(device); 1180 struct uart_port *port = dev_get_drvdata(device);
1229 struct tty_struct *tty; 1181 struct tty_struct *tty;
@@ -1242,23 +1194,24 @@ static int xuartps_suspend(struct device *device)
1242 * Call the API provided in serial_core.c file which handles 1194 * Call the API provided in serial_core.c file which handles
1243 * the suspend. 1195 * the suspend.
1244 */ 1196 */
1245 uart_suspend_port(&xuartps_uart_driver, port); 1197 uart_suspend_port(&cdns_uart_uart_driver, port);
1246 if (console_suspend_enabled && !may_wake) { 1198 if (console_suspend_enabled && !may_wake) {
1247 struct xuartps *xuartps = port->private_data; 1199 struct cdns_uart *cdns_uart = port->private_data;
1248 1200
1249 clk_disable(xuartps->refclk); 1201 clk_disable(cdns_uart->uartclk);
1250 clk_disable(xuartps->aperclk); 1202 clk_disable(cdns_uart->pclk);
1251 } else { 1203 } else {
1252 unsigned long flags = 0; 1204 unsigned long flags = 0;
1253 1205
1254 spin_lock_irqsave(&port->lock, flags); 1206 spin_lock_irqsave(&port->lock, flags);
1255 /* Empty the receive FIFO 1st before making changes */ 1207 /* Empty the receive FIFO 1st before making changes */
1256 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)) 1208 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
1257 xuartps_readl(XUARTPS_FIFO_OFFSET); 1209 CDNS_UART_SR_RXEMPTY))
1210 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
1258 /* set RX trigger level to 1 */ 1211 /* set RX trigger level to 1 */
1259 xuartps_writel(1, XUARTPS_RXWM_OFFSET); 1212 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET);
1260 /* disable RX timeout interrups */ 1213 /* disable RX timeout interrups */
1261 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET); 1214 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET);
1262 spin_unlock_irqrestore(&port->lock, flags); 1215 spin_unlock_irqrestore(&port->lock, flags);
1263 } 1216 }
1264 1217
@@ -1266,12 +1219,12 @@ static int xuartps_suspend(struct device *device)
1266} 1219}
1267 1220
1268/** 1221/**
1269 * xuartps_resume - Resume after a previous suspend 1222 * cdns_uart_resume - Resume after a previous suspend
1270 * @device: Pointer to the device structure 1223 * @device: Pointer to the device structure
1271 * 1224 *
1272 * Returns 0 1225 * Return: 0
1273 */ 1226 */
1274static int xuartps_resume(struct device *device) 1227static int cdns_uart_resume(struct device *device)
1275{ 1228{
1276 struct uart_port *port = dev_get_drvdata(device); 1229 struct uart_port *port = dev_get_drvdata(device);
1277 unsigned long flags = 0; 1230 unsigned long flags = 0;
@@ -1289,87 +1242,95 @@ static int xuartps_resume(struct device *device)
1289 } 1242 }
1290 1243
1291 if (console_suspend_enabled && !may_wake) { 1244 if (console_suspend_enabled && !may_wake) {
1292 struct xuartps *xuartps = port->private_data; 1245 struct cdns_uart *cdns_uart = port->private_data;
1293 1246
1294 clk_enable(xuartps->aperclk); 1247 clk_enable(cdns_uart->pclk);
1295 clk_enable(xuartps->refclk); 1248 clk_enable(cdns_uart->uartclk);
1296 1249
1297 spin_lock_irqsave(&port->lock, flags); 1250 spin_lock_irqsave(&port->lock, flags);
1298 1251
1299 /* Set TX/RX Reset */ 1252 /* Set TX/RX Reset */
1300 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 1253 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1301 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 1254 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1302 XUARTPS_CR_OFFSET); 1255 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1303 while (xuartps_readl(XUARTPS_CR_OFFSET) & 1256 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
1304 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) 1257 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1305 cpu_relax(); 1258 cpu_relax();
1306 1259
1307 /* restore rx timeout value */ 1260 /* restore rx timeout value */
1308 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 1261 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
1309 /* Enable Tx/Rx */ 1262 /* Enable Tx/Rx */
1310 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 1263 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1311 xuartps_writel( 1264 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1312 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | 1265 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1313 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 1266 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1314 XUARTPS_CR_OFFSET);
1315 1267
1316 spin_unlock_irqrestore(&port->lock, flags); 1268 spin_unlock_irqrestore(&port->lock, flags);
1317 } else { 1269 } else {
1318 spin_lock_irqsave(&port->lock, flags); 1270 spin_lock_irqsave(&port->lock, flags);
1319 /* restore original rx trigger level */ 1271 /* restore original rx trigger level */
1320 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); 1272 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
1321 /* enable RX timeout interrupt */ 1273 /* enable RX timeout interrupt */
1322 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 1274 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
1323 spin_unlock_irqrestore(&port->lock, flags); 1275 spin_unlock_irqrestore(&port->lock, flags);
1324 } 1276 }
1325 1277
1326 return uart_resume_port(&xuartps_uart_driver, port); 1278 return uart_resume_port(&cdns_uart_uart_driver, port);
1327} 1279}
1328#endif /* ! CONFIG_PM_SLEEP */ 1280#endif /* ! CONFIG_PM_SLEEP */
1329 1281
1330static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume); 1282static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1283 cdns_uart_resume);
1331 1284
1332/* ---------------------------------------------------------------------
1333 * Platform bus binding
1334 */
1335/** 1285/**
1336 * xuartps_probe - Platform driver probe 1286 * cdns_uart_probe - Platform driver probe
1337 * @pdev: Pointer to the platform device structure 1287 * @pdev: Pointer to the platform device structure
1338 * 1288 *
1339 * Returns 0 on success, negative error otherwise 1289 * Return: 0 on success, negative errno otherwise
1340 **/ 1290 */
1341static int xuartps_probe(struct platform_device *pdev) 1291static int cdns_uart_probe(struct platform_device *pdev)
1342{ 1292{
1343 int rc; 1293 int rc, id;
1344 struct uart_port *port; 1294 struct uart_port *port;
1345 struct resource *res, *res2; 1295 struct resource *res, *res2;
1346 struct xuartps *xuartps_data; 1296 struct cdns_uart *cdns_uart_data;
1347 1297
1348 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data), 1298 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1349 GFP_KERNEL); 1299 GFP_KERNEL);
1350 if (!xuartps_data) 1300 if (!cdns_uart_data)
1351 return -ENOMEM; 1301 return -ENOMEM;
1352 1302
1353 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk"); 1303 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1354 if (IS_ERR(xuartps_data->aperclk)) { 1304 if (IS_ERR(cdns_uart_data->pclk)) {
1355 dev_err(&pdev->dev, "aper_clk clock not found.\n"); 1305 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1356 return PTR_ERR(xuartps_data->aperclk); 1306 if (!IS_ERR(cdns_uart_data->pclk))
1307 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1357 } 1308 }
1358 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 1309 if (IS_ERR(cdns_uart_data->pclk)) {
1359 if (IS_ERR(xuartps_data->refclk)) { 1310 dev_err(&pdev->dev, "pclk clock not found.\n");
1360 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 1311 return PTR_ERR(cdns_uart_data->pclk);
1361 return PTR_ERR(xuartps_data->refclk);
1362 } 1312 }
1363 1313
1364 rc = clk_prepare_enable(xuartps_data->aperclk); 1314 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1315 if (IS_ERR(cdns_uart_data->uartclk)) {
1316 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1317 if (!IS_ERR(cdns_uart_data->uartclk))
1318 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1319 }
1320 if (IS_ERR(cdns_uart_data->uartclk)) {
1321 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1322 return PTR_ERR(cdns_uart_data->uartclk);
1323 }
1324
1325 rc = clk_prepare_enable(cdns_uart_data->pclk);
1365 if (rc) { 1326 if (rc) {
1366 dev_err(&pdev->dev, "Unable to enable APER clock.\n"); 1327 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1367 return rc; 1328 return rc;
1368 } 1329 }
1369 rc = clk_prepare_enable(xuartps_data->refclk); 1330 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1370 if (rc) { 1331 if (rc) {
1371 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1332 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1372 goto err_out_clk_dis_aper; 1333 goto err_out_clk_dis_pclk;
1373 } 1334 }
1374 1335
1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1385,15 +1346,19 @@ static int xuartps_probe(struct platform_device *pdev)
1385 } 1346 }
1386 1347
1387#ifdef CONFIG_COMMON_CLK 1348#ifdef CONFIG_COMMON_CLK
1388 xuartps_data->clk_rate_change_nb.notifier_call = 1349 cdns_uart_data->clk_rate_change_nb.notifier_call =
1389 xuartps_clk_notifier_cb; 1350 cdns_uart_clk_notifier_cb;
1390 if (clk_notifier_register(xuartps_data->refclk, 1351 if (clk_notifier_register(cdns_uart_data->uartclk,
1391 &xuartps_data->clk_rate_change_nb)) 1352 &cdns_uart_data->clk_rate_change_nb))
1392 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1353 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1393#endif 1354#endif
1355 /* Look for a serialN alias */
1356 id = of_alias_get_id(pdev->dev.of_node, "serial");
1357 if (id < 0)
1358 id = 0;
1394 1359
1395 /* Initialize the port structure */ 1360 /* Initialize the port structure */
1396 port = xuartps_get_port(); 1361 port = cdns_uart_get_port(id);
1397 1362
1398 if (!port) { 1363 if (!port) {
1399 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1364 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
@@ -1407,11 +1372,11 @@ static int xuartps_probe(struct platform_device *pdev)
1407 port->mapbase = res->start; 1372 port->mapbase = res->start;
1408 port->irq = res2->start; 1373 port->irq = res2->start;
1409 port->dev = &pdev->dev; 1374 port->dev = &pdev->dev;
1410 port->uartclk = clk_get_rate(xuartps_data->refclk); 1375 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1411 port->private_data = xuartps_data; 1376 port->private_data = cdns_uart_data;
1412 xuartps_data->port = port; 1377 cdns_uart_data->port = port;
1413 platform_set_drvdata(pdev, port); 1378 platform_set_drvdata(pdev, port);
1414 rc = uart_add_one_port(&xuartps_uart_driver, port); 1379 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1415 if (rc) { 1380 if (rc) {
1416 dev_err(&pdev->dev, 1381 dev_err(&pdev->dev,
1417 "uart_add_one_port() failed; err=%i\n", rc); 1382 "uart_add_one_port() failed; err=%i\n", rc);
@@ -1422,103 +1387,89 @@ static int xuartps_probe(struct platform_device *pdev)
1422 1387
1423err_out_notif_unreg: 1388err_out_notif_unreg:
1424#ifdef CONFIG_COMMON_CLK 1389#ifdef CONFIG_COMMON_CLK
1425 clk_notifier_unregister(xuartps_data->refclk, 1390 clk_notifier_unregister(cdns_uart_data->uartclk,
1426 &xuartps_data->clk_rate_change_nb); 1391 &cdns_uart_data->clk_rate_change_nb);
1427#endif 1392#endif
1428err_out_clk_disable: 1393err_out_clk_disable:
1429 clk_disable_unprepare(xuartps_data->refclk); 1394 clk_disable_unprepare(cdns_uart_data->uartclk);
1430err_out_clk_dis_aper: 1395err_out_clk_dis_pclk:
1431 clk_disable_unprepare(xuartps_data->aperclk); 1396 clk_disable_unprepare(cdns_uart_data->pclk);
1432 1397
1433 return rc; 1398 return rc;
1434} 1399}
1435 1400
1436/** 1401/**
1437 * xuartps_remove - called when the platform driver is unregistered 1402 * cdns_uart_remove - called when the platform driver is unregistered
1438 * @pdev: Pointer to the platform device structure 1403 * @pdev: Pointer to the platform device structure
1439 * 1404 *
1440 * Returns 0 on success, negative error otherwise 1405 * Return: 0 on success, negative errno otherwise
1441 **/ 1406 */
1442static int xuartps_remove(struct platform_device *pdev) 1407static int cdns_uart_remove(struct platform_device *pdev)
1443{ 1408{
1444 struct uart_port *port = platform_get_drvdata(pdev); 1409 struct uart_port *port = platform_get_drvdata(pdev);
1445 struct xuartps *xuartps_data = port->private_data; 1410 struct cdns_uart *cdns_uart_data = port->private_data;
1446 int rc; 1411 int rc;
1447 1412
1448 /* Remove the xuartps port from the serial core */ 1413 /* Remove the cdns_uart port from the serial core */
1449#ifdef CONFIG_COMMON_CLK 1414#ifdef CONFIG_COMMON_CLK
1450 clk_notifier_unregister(xuartps_data->refclk, 1415 clk_notifier_unregister(cdns_uart_data->uartclk,
1451 &xuartps_data->clk_rate_change_nb); 1416 &cdns_uart_data->clk_rate_change_nb);
1452#endif 1417#endif
1453 rc = uart_remove_one_port(&xuartps_uart_driver, port); 1418 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1454 port->mapbase = 0; 1419 port->mapbase = 0;
1455 clk_disable_unprepare(xuartps_data->refclk); 1420 clk_disable_unprepare(cdns_uart_data->uartclk);
1456 clk_disable_unprepare(xuartps_data->aperclk); 1421 clk_disable_unprepare(cdns_uart_data->pclk);
1457 return rc; 1422 return rc;
1458} 1423}
1459 1424
1460/* Match table for of_platform binding */ 1425/* Match table for of_platform binding */
1461static struct of_device_id xuartps_of_match[] = { 1426static struct of_device_id cdns_uart_of_match[] = {
1462 { .compatible = "xlnx,xuartps", }, 1427 { .compatible = "xlnx,xuartps", },
1428 { .compatible = "cdns,uart-r1p8", },
1463 {} 1429 {}
1464}; 1430};
1465MODULE_DEVICE_TABLE(of, xuartps_of_match); 1431MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1466 1432
1467static struct platform_driver xuartps_platform_driver = { 1433static struct platform_driver cdns_uart_platform_driver = {
1468 .probe = xuartps_probe, /* Probe method */ 1434 .probe = cdns_uart_probe,
1469 .remove = xuartps_remove, /* Detach method */ 1435 .remove = cdns_uart_remove,
1470 .driver = { 1436 .driver = {
1471 .owner = THIS_MODULE, 1437 .owner = THIS_MODULE,
1472 .name = XUARTPS_NAME, /* Driver name */ 1438 .name = CDNS_UART_NAME,
1473 .of_match_table = xuartps_of_match, 1439 .of_match_table = cdns_uart_of_match,
1474 .pm = &xuartps_dev_pm_ops, 1440 .pm = &cdns_uart_dev_pm_ops,
1475 }, 1441 },
1476}; 1442};
1477 1443
1478/* --------------------------------------------------------------------- 1444static int __init cdns_uart_init(void)
1479 * Module Init and Exit
1480 */
1481/**
1482 * xuartps_init - Initial driver registration call
1483 *
1484 * Returns whether the registration was successful or not
1485 **/
1486static int __init xuartps_init(void)
1487{ 1445{
1488 int retval = 0; 1446 int retval = 0;
1489 1447
1490 /* Register the xuartps driver with the serial core */ 1448 /* Register the cdns_uart driver with the serial core */
1491 retval = uart_register_driver(&xuartps_uart_driver); 1449 retval = uart_register_driver(&cdns_uart_uart_driver);
1492 if (retval) 1450 if (retval)
1493 return retval; 1451 return retval;
1494 1452
1495 /* Register the platform driver */ 1453 /* Register the platform driver */
1496 retval = platform_driver_register(&xuartps_platform_driver); 1454 retval = platform_driver_register(&cdns_uart_platform_driver);
1497 if (retval) 1455 if (retval)
1498 uart_unregister_driver(&xuartps_uart_driver); 1456 uart_unregister_driver(&cdns_uart_uart_driver);
1499 1457
1500 return retval; 1458 return retval;
1501} 1459}
1502 1460
1503/** 1461static void __exit cdns_uart_exit(void)
1504 * xuartps_exit - Driver unregistration call
1505 **/
1506static void __exit xuartps_exit(void)
1507{ 1462{
1508 /* The order of unregistration is important. Unregister the
1509 * UART driver before the platform driver crashes the system.
1510 */
1511
1512 /* Unregister the platform driver */ 1463 /* Unregister the platform driver */
1513 platform_driver_unregister(&xuartps_platform_driver); 1464 platform_driver_unregister(&cdns_uart_platform_driver);
1514 1465
1515 /* Unregister the xuartps driver */ 1466 /* Unregister the cdns_uart driver */
1516 uart_unregister_driver(&xuartps_uart_driver); 1467 uart_unregister_driver(&cdns_uart_uart_driver);
1517} 1468}
1518 1469
1519module_init(xuartps_init); 1470module_init(cdns_uart_init);
1520module_exit(xuartps_exit); 1471module_exit(cdns_uart_exit);
1521 1472
1522MODULE_DESCRIPTION("Driver for PS UART"); 1473MODULE_DESCRIPTION("Driver for Cadence UART");
1523MODULE_AUTHOR("Xilinx Inc."); 1474MODULE_AUTHOR("Xilinx Inc.");
1524MODULE_LICENSE("GPL"); 1475MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 09:54:37 -0500