1 files changed, 9 insertions, 80 deletions

diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 1b4a6444ea61..c58c7663a3fe 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -34,11 +34,6 @@ enum calibration_type {
         TYPE_NONE,
 };
 
-enum calibration_mode {
-        SW_MODE,
-        HW_MODE,
-};
-
 enum soc_type {
         SOC_ARCH_EXYNOS3250 = 1,
         SOC_ARCH_EXYNOS4210,
@@ -82,46 +77,19 @@ enum soc_type {
  * bitfields. The register validity, offsets and bitfield values may vary
  * slightly across different exynos SOC's.
  * @triminfo_data: register containing 2 pont trimming data
- * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
- * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
  * @triminfo_ctrl: trim info controller register.
- * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
-        reg.
+ * @triminfo_ctrl_count: the number of trim info controller register.
  * @tmu_ctrl: TMU main controller register.
  * @test_mux_addr_shift: shift bits of test mux address.
- * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
- * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
  * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
  * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
  * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
- * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
-        register.
- * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
- * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
-        register.
- * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
-        register.
- * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
-        tmu_ctrl register.
- * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
  * @tmu_status: register drescribing the TMU status.
  * @tmu_cur_temp: register containing the current temperature of the TMU.
- * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp
-        register.
  * @threshold_temp: register containing the base threshold level.
  * @threshold_th0: Register containing first set of rising levels.
- * @threshold_th0_l0_shift: shift bits of level0 threshold temperature.
- * @threshold_th0_l1_shift: shift bits of level1 threshold temperature.
- * @threshold_th0_l2_shift: shift bits of level2 threshold temperature.
- * @threshold_th0_l3_shift: shift bits of level3 threshold temperature.
  * @threshold_th1: Register containing second set of rising levels.
- * @threshold_th1_l0_shift: shift bits of level0 threshold temperature.
- * @threshold_th1_l1_shift: shift bits of level1 threshold temperature.
- * @threshold_th1_l2_shift: shift bits of level2 threshold temperature.
- * @threshold_th1_l3_shift: shift bits of level3 threshold temperature.
  * @threshold_th2: Register containing third set of rising levels.
- * @threshold_th2_l0_shift: shift bits of level0 threshold temperature.
- * @threshold_th3: Register containing fourth set of rising levels.
  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
  * @tmu_inten: register containing the different threshold interrupt
         enable bits.
@@ -130,68 +98,35 @@ enum soc_type {
  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
  * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
  * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
- * @inten_fall1_shift: shift bits of falling 1 interrupt bits.
- * @inten_fall2_shift: shift bits of falling 2 interrupt bits.
- * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
- * @intclr_fall_shift: shift bits for interrupt clear fall 0
- * @intclr_rise_shift: shift bits of all rising interrupt bits.
- * @intclr_rise_mask: mask bits of all rising interrupt bits.
- * @intclr_fall_mask: mask bits of all rising interrupt bits.
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
- * @emul_time_mask: mask bits of emulation time.
  * @tmu_irqstatus: register to find which TMU generated interrupts.
  * @tmu_pmin: register to get/set the Pmin value.
  */
 struct exynos_tmu_registers {
         u32     triminfo_data;
-        u32     triminfo_25_shift;
-        u32     triminfo_85_shift;
 
-        u32     triminfo_ctrl;
-        u32     triminfo_ctrl1;
-        u32     triminfo_reload_shift;
+        u32     triminfo_ctrl[MAX_TRIMINFO_CTRL_REG];
+        u32     triminfo_ctrl_count;
 
         u32     tmu_ctrl;
         u32     test_mux_addr_shift;
-        u32     buf_vref_sel_shift;
-        u32     buf_vref_sel_mask;
         u32     therm_trip_mode_shift;
         u32     therm_trip_mode_mask;
         u32     therm_trip_en_shift;
-        u32     buf_slope_sel_shift;
-        u32     buf_slope_sel_mask;
-        u32     calib_mode_shift;
-        u32     calib_mode_mask;
-        u32     therm_trip_tq_en_shift;
-        u32     core_en_shift;
 
         u32     tmu_status;
 
         u32     tmu_cur_temp;
-        u32     tmu_cur_temp_shift;
 
         u32     threshold_temp;
 
         u32     threshold_th0;
-        u32     threshold_th0_l0_shift;
-        u32     threshold_th0_l1_shift;
-        u32     threshold_th0_l2_shift;
-        u32     threshold_th0_l3_shift;
-
         u32     threshold_th1;
-        u32     threshold_th1_l0_shift;
-        u32     threshold_th1_l1_shift;
-        u32     threshold_th1_l2_shift;
-        u32     threshold_th1_l3_shift;
-
         u32     threshold_th2;
-        u32     threshold_th2_l0_shift;
-
-        u32     threshold_th3;
         u32     threshold_th3_l0_shift;
 
         u32     tmu_inten;
@@ -200,22 +135,14 @@ struct exynos_tmu_registers {
         u32     inten_rise2_shift;
         u32     inten_rise3_shift;
         u32     inten_fall0_shift;
-        u32     inten_fall1_shift;
-        u32     inten_fall2_shift;
-        u32     inten_fall3_shift;
 
         u32     tmu_intstat;
 
         u32     tmu_intclear;
-        u32     intclr_fall_shift;
-        u32     intclr_rise_shift;
-        u32     intclr_fall_mask;
-        u32     intclr_rise_mask;
 
         u32     emul_con;
         u32     emul_temp_shift;
         u32     emul_time_shift;
-        u32     emul_time_mask;
 
         u32     tmu_irqstatus;
         u32     tmu_pmin;
@@ -250,11 +177,12 @@ struct exynos_tmu_registers {
  *      1 = enable trigger_level[] interrupt,
  *      0 = disable trigger_level[] interrupt
  * @max_trigger_level: max trigger level supported by the TMU
+ * @non_hw_trigger_levels: number of defined non-hardware trigger levels
  * @gain: gain of amplifier in the positive-TC generator block
- *      0 <= gain <= 15
+ *      0 < gain <= 15
  * @reference_voltage: reference voltage of amplifier
  *      in the positive-TC generator block
- *      0 <= reference_voltage <= 31
+ *      0 < reference_voltage <= 31
  * @noise_cancel_mode: noise cancellation mode
  *      000, 100, 101, 110 and 111 can be different modes
  * @type: determines the type of SOC
@@ -265,8 +193,8 @@ struct exynos_tmu_registers {
  * @second_point_trim: temp value of the second point trimming
  * @default_temp_offset: default temperature offset in case of no trimming
  * @test_mux; information if SoC supports test MUX
+ * @triminfo_reload: reload value to read TRIMINFO register
  * @cal_type: calibration type for temperature
- * @cal_mode: calibration mode for temperature
  * @freq_clip_table: Table representing frequency reduction percentage.
  * @freq_tab_count: Count of the above table as frequency reduction may
  *      applicable to only some of the trigger levels.
@@ -284,6 +212,7 @@ struct exynos_tmu_platform_data {
         enum trigger_type trigger_type[MAX_TRIP_COUNT];
         bool trigger_enable[MAX_TRIP_COUNT];
         u8 max_trigger_level;
+        u8 non_hw_trigger_levels;
         u8 gain;
         u8 reference_voltage;
         u8 noise_cancel_mode;
@@ -295,9 +224,9 @@ struct exynos_tmu_platform_data {
         u8 second_point_trim;
         u8 default_temp_offset;
         u8 test_mux;
+        u8 triminfo_reload[MAX_TRIMINFO_CTRL_REG];
 
         enum calibration_type cal_type;
-        enum calibration_mode cal_mode;
         enum soc_type type;
         struct freq_clip_table freq_tab[4];
         unsigned int freq_tab_count;