12 files changed, 483 insertions, 174 deletions

diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig
index 2d8cc455dbc7..42cdaa9a4d8a 100644
--- a/drivers/ssb/Kconfig
+++ b/drivers/ssb/Kconfig
@@ -82,7 +82,7 @@ config SSB_SDIOHOST
 
 config SSB_SILENT
         bool "No SSB kernel messages"
-        depends on SSB && EMBEDDED
+        depends on SSB && EXPERT
         help
           This option turns off all Sonics Silicon Backplane printks.
           Note that you won't be able to identify problems, once
diff --git a/drivers/ssb/b43_pci_bridge.c b/drivers/ssb/b43_pci_bridge.c
index ef9c6a04ad8f..744d3f6e4709 100644
--- a/drivers/ssb/b43_pci_bridge.c
+++ b/drivers/ssb/b43_pci_bridge.c
@@ -24,6 +24,7 @@ static const struct pci_device_id b43_pci_bridge_tbl[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
+        { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC,  0x4318) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
index 7c031fdc8205..06d15b6f2215 100644
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
         if (!ccdev)
                 return;
         bus = ccdev->bus;
+
+        /* We support SLOW only on 6..9 */
+        if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
+                mode = SSB_CLKMODE_DYNAMIC;
+
+        if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
+                return; /* PMU controls clockmode, separated function needed */
+        SSB_WARN_ON(ccdev->id.revision >= 20);
+
         /* chipcommon cores prior to rev6 don't support dynamic clock control */
         if (ccdev->id.revision < 6)
                 return;
-        /* chipcommon cores rev10 are a whole new ball game */
+
+        /* ChipCommon cores rev10+ need testing */
         if (ccdev->id.revision >= 10)
                 return;
+
         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
                 return;
 
         switch (mode) {
-        case SSB_CLKMODE_SLOW:
+        case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
                 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
                 break;
         case SSB_CLKMODE_FAST:
-                ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
-                tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-                tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
-                chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+                if (ccdev->id.revision < 10) {
+                        ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
+                        tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+                        tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+                        tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
+                        chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+                } else {
+                        chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
+                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
+                                 SSB_CHIPCO_SYSCLKCTL_FORCEHT));
+                        /* udelay(150); TODO: not available in early init */
+                }
                 break;
         case SSB_CLKMODE_DYNAMIC:
-                tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
-                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-                if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
-                        tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-                chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-
-                /* for dynamic control, we have to release our xtal_pu "force on" */
-                if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
-                        ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
+                if (ccdev->id.revision < 10) {
+                        tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+                        tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+                        tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
+                        tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+                        if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
+                            SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
+                                tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+                        chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+
+                        /* For dynamic control, we have to release our xtal_pu
+                         * "force on" */
+                        if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
+                                ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
+                } else {
+                        chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
+                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
+                                 ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
+                }
                 break;
         default:
                 SSB_WARN_ON(1);
@@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
         if (cc->dev->id.revision >= 11)
                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
         ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
+
+        if (cc->dev->id.revision >= 20) {
+                chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
+                chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
+        }
+
         ssb_pmu_init(cc);
         chipco_powercontrol_init(cc);
         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
index 5732bb2c3578..305ade7825f7 100644
--- a/drivers/ssb/driver_chipcommon_pmu.c
+++ b/drivers/ssb/driver_chipcommon_pmu.c
@@ -423,6 +423,8 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
 
         switch (bus->chip_id) {
         case 0x4312:
+                 min_msk = 0xCBB;
+                 break;
         case 0x4322:
                 /* We keep the default settings:
                  * min_msk = 0xCBB
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
index 0e8d35224614..d6620ad309ce 100644
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
@@ -15,6 +15,11 @@
 
 #include "ssb_private.h"
 
+static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
+static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
+static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
+                                u8 address, u16 data);
 
 static inline
 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
@@ -403,6 +408,107 @@ static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
 }
 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 
+/**************************************************
+ * Workarounds.
+ **************************************************/
+
+static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
+{
+        u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
+        if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
+                tmp &= ~0xF000;
+                tmp |= (pc->dev->core_index << 12);
+                pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
+        }
+}
+
+static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
+{
+        return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
+}
+
+static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
+{
+        const u8 serdes_pll_device = 0x1D;
+        const u8 serdes_rx_device = 0x1F;
+        u16 tmp;
+
+        ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
+                            ssb_pcicore_polarity_workaround(pc));
+        tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
+        if (tmp & 0x4000)
+                ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
+}
+
+static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
+{
+        struct ssb_device *pdev = pc->dev;
+        struct ssb_bus *bus = pdev->bus;
+        u32 tmp;
+
+        tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
+        tmp |= SSB_PCICORE_SBTOPCI_PREF;
+        tmp |= SSB_PCICORE_SBTOPCI_BURST;
+        pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
+
+        if (pdev->id.revision < 5) {
+                tmp = ssb_read32(pdev, SSB_IMCFGLO);
+                tmp &= ~SSB_IMCFGLO_SERTO;
+                tmp |= 2;
+                tmp &= ~SSB_IMCFGLO_REQTO;
+                tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
+                ssb_write32(pdev, SSB_IMCFGLO, tmp);
+                ssb_commit_settings(bus);
+        } else if (pdev->id.revision >= 11) {
+                tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
+                tmp |= SSB_PCICORE_SBTOPCI_MRM;
+                pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
+        }
+}
+
+static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
+{
+        u32 tmp;
+        u8 rev = pc->dev->id.revision;
+
+        if (rev == 0 || rev == 1) {
+                /* TLP Workaround register. */
+                tmp = ssb_pcie_read(pc, 0x4);
+                tmp |= 0x8;
+                ssb_pcie_write(pc, 0x4, tmp);
+        }
+        if (rev == 1) {
+                /* DLLP Link Control register. */
+                tmp = ssb_pcie_read(pc, 0x100);
+                tmp |= 0x40;
+                ssb_pcie_write(pc, 0x100, tmp);
+        }
+
+        if (rev == 0) {
+                const u8 serdes_rx_device = 0x1F;
+
+                ssb_pcie_mdio_write(pc, serdes_rx_device,
+                                        2 /* Timer */, 0x8128);
+                ssb_pcie_mdio_write(pc, serdes_rx_device,
+                                        6 /* CDR */, 0x0100);
+                ssb_pcie_mdio_write(pc, serdes_rx_device,
+                                        7 /* CDR BW */, 0x1466);
+        } else if (rev == 3 || rev == 4 || rev == 5) {
+                /* TODO: DLLP Power Management Threshold */
+                ssb_pcicore_serdes_workaround(pc);
+                /* TODO: ASPM */
+        } else if (rev == 7) {
+                /* TODO: No PLL down */
+        }
+
+        if (rev >= 6) {
+                /* Miscellaneous Configuration Fixup */
+                tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
+                if (!(tmp & 0x8000))
+                        pcicore_write16(pc, SSB_PCICORE_SPROM(5),
+                                        tmp | 0x8000);
+        }
+}
 
 /**************************************************
  * Generic and Clientmode operation code.
@@ -410,18 +516,25 @@ static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
 
 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
 {
+        ssb_pcicore_fix_sprom_core_index(pc);
+
         /* Disable PCI interrupts. */
         ssb_write32(pc->dev, SSB_INTVEC, 0);
+
+        /* Additional PCIe always once-executed workarounds */
+        if (pc->dev->id.coreid == SSB_DEV_PCIE) {
+                ssb_pcicore_serdes_workaround(pc);
+                /* TODO: ASPM */
+                /* TODO: Clock Request Update */
+        }
 }
 
 void ssb_pcicore_init(struct ssb_pcicore *pc)
 {
         struct ssb_device *dev = pc->dev;
-        struct ssb_bus *bus;
 
         if (!dev)
                 return;
-        bus = dev->bus;
         if (!ssb_device_is_enabled(dev))
                 ssb_device_enable(dev, 0);
 
@@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
         pcicore_write32(pc, 0x134, data);
 }
 
-static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
-                                u8 address, u16 data)
+static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
+{
+        const u16 mdio_control = 0x128;
+        const u16 mdio_data = 0x12C;
+        u32 v;
+        int i;
+
+        v = (1 << 30); /* Start of Transaction */
+        v |= (1 << 28); /* Write Transaction */
+        v |= (1 << 17); /* Turnaround */
+        v |= (0x1F << 18);
+        v |= (phy << 4);
+        pcicore_write32(pc, mdio_data, v);
+
+        udelay(10);
+        for (i = 0; i < 200; i++) {
+                v = pcicore_read32(pc, mdio_control);
+                if (v & 0x100 /* Trans complete */)
+                        break;
+                msleep(1);
+        }
+}
+
+static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
 {
         const u16 mdio_control = 0x128;
         const u16 mdio_data = 0x12C;
+        int max_retries = 10;
+        u16 ret = 0;
         u32 v;
         int i;
 
@@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
         v |= 0x2; /* MDIO Clock Divisor */
         pcicore_write32(pc, mdio_control, v);
 
+        if (pc->dev->id.revision >= 10) {
+                max_retries = 200;
+                ssb_pcie_mdio_set_phy(pc, device);
+        }
+
         v = (1 << 30); /* Start of Transaction */
-        v |= (1 << 28); /* Write Transaction */
+        v |= (1 << 29); /* Read Transaction */
         v |= (1 << 17); /* Turnaround */
-        v |= (u32)device << 22;
+        if (pc->dev->id.revision < 10)
+                v |= (u32)device << 22;
         v |= (u32)address << 18;
-        v |= data;
         pcicore_write32(pc, mdio_data, v);
         /* Wait for the device to complete the transaction */
         udelay(10);
-        for (i = 0; i < 10; i++) {
+        for (i = 0; i < max_retries; i++) {
                 v = pcicore_read32(pc, mdio_control);
-                if (v & 0x100 /* Trans complete */)
+                if (v & 0x100 /* Trans complete */) {
+                        udelay(10);
+                        ret = pcicore_read32(pc, mdio_data);
                         break;
+                }
                 msleep(1);
         }
         pcicore_write32(pc, mdio_control, 0);
+        return ret;
 }
 
-static void ssb_broadcast_value(struct ssb_device *dev,
-                                u32 address, u32 data)
+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
+                                u8 address, u16 data)
 {
-        /* This is used for both, PCI and ChipCommon core, so be careful. */
-        BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-        BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-
-        ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
-        ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
-        ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
-        ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
-}
+        const u16 mdio_control = 0x128;
+        const u16 mdio_data = 0x12C;
+        int max_retries = 10;
+        u32 v;
+        int i;
 
-static void ssb_commit_settings(struct ssb_bus *bus)
-{
-        struct ssb_device *dev;
+        v = 0x80; /* Enable Preamble Sequence */
+        v |= 0x2; /* MDIO Clock Divisor */
+        pcicore_write32(pc, mdio_control, v);
 
-        dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-        if (WARN_ON(!dev))
-                return;
-        /* This forces an update of the cached registers. */
-        ssb_broadcast_value(dev, 0xFD8, 0);
+        if (pc->dev->id.revision >= 10) {
+                max_retries = 200;
+                ssb_pcie_mdio_set_phy(pc, device);
+        }
+
+        v = (1 << 30); /* Start of Transaction */
+        v |= (1 << 28); /* Write Transaction */
+        v |= (1 << 17); /* Turnaround */
+        if (pc->dev->id.revision < 10)
+                v |= (u32)device << 22;
+        v |= (u32)address << 18;
+        v |= data;
+        pcicore_write32(pc, mdio_data, v);
+        /* Wait for the device to complete the transaction */
+        udelay(10);
+        for (i = 0; i < max_retries; i++) {
+                v = pcicore_read32(pc, mdio_control);
+                if (v & 0x100 /* Trans complete */)
+                        break;
+                msleep(1);
+        }
+        pcicore_write32(pc, mdio_control, 0);
 }
 
 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
@@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
         if (pc->setup_done)
                 goto out;
         if (pdev->id.coreid == SSB_DEV_PCI) {
-                tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-                tmp |= SSB_PCICORE_SBTOPCI_PREF;
-                tmp |= SSB_PCICORE_SBTOPCI_BURST;
-                pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-
-                if (pdev->id.revision < 5) {
-                        tmp = ssb_read32(pdev, SSB_IMCFGLO);
-                        tmp &= ~SSB_IMCFGLO_SERTO;
-                        tmp |= 2;
-                        tmp &= ~SSB_IMCFGLO_REQTO;
-                        tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
-                        ssb_write32(pdev, SSB_IMCFGLO, tmp);
-                        ssb_commit_settings(bus);
-                } else if (pdev->id.revision >= 11) {
-                        tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-                        tmp |= SSB_PCICORE_SBTOPCI_MRM;
-                        pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-                }
+                ssb_pcicore_pci_setup_workarounds(pc);
         } else {
                 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
-                //TODO: Better make defines for all these magic PCIE values.
-                if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
-                        /* TLP Workaround register. */
-                        tmp = ssb_pcie_read(pc, 0x4);
-                        tmp |= 0x8;
-                        ssb_pcie_write(pc, 0x4, tmp);
-                }
-                if (pdev->id.revision == 0) {
-                        const u8 serdes_rx_device = 0x1F;
-
-                        ssb_pcie_mdio_write(pc, serdes_rx_device,
-                                            2 /* Timer */, 0x8128);
-                        ssb_pcie_mdio_write(pc, serdes_rx_device,
-                                            6 /* CDR */, 0x0100);
-                        ssb_pcie_mdio_write(pc, serdes_rx_device,
-                                            7 /* CDR BW */, 0x1466);
-                } else if (pdev->id.revision == 1) {
-                        /* DLLP Link Control register. */
-                        tmp = ssb_pcie_read(pc, 0x100);
-                        tmp |= 0x40;
-                        ssb_pcie_write(pc, 0x100, tmp);
-                }
+                ssb_pcicore_pcie_setup_workarounds(pc);
         }
         pc->setup_done = 1;
 out:
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index 7892ac163522..f8a13f863217 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -20,7 +20,6 @@
 #include <linux/mmc/sdio_func.h>
 #include <linux/slab.h>
 
-#include <pcmcia/cs.h>
 #include <pcmcia/cistpl.h>
 #include <pcmcia/ds.h>
 
@@ -384,6 +383,35 @@ static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
                              ssb_dev->id.revision);
 }
 
+#define ssb_config_attr(attrib, field, format_string) \
+static ssize_t \
+attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
+{ \
+        return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
+}
+
+ssb_config_attr(core_num, core_index, "%u\n")
+ssb_config_attr(coreid, id.coreid, "0x%04x\n")
+ssb_config_attr(vendor, id.vendor, "0x%04x\n")
+ssb_config_attr(revision, id.revision, "%u\n")
+ssb_config_attr(irq, irq, "%u\n")
+static ssize_t
+name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%s\n",
+                       ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
+}
+
+static struct device_attribute ssb_device_attrs[] = {
+        __ATTR_RO(name),
+        __ATTR_RO(core_num),
+        __ATTR_RO(coreid),
+        __ATTR_RO(vendor),
+        __ATTR_RO(revision),
+        __ATTR_RO(irq),
+        __ATTR_NULL,
+};
+
 static struct bus_type ssb_bustype = {
         .name           = "ssb",
         .match          = ssb_bus_match,
@@ -393,6 +421,7 @@ static struct bus_type ssb_bustype = {
         .suspend        = ssb_device_suspend,
         .resume         = ssb_device_resume,
         .uevent         = ssb_device_uevent,
+        .dev_attrs      = ssb_device_attrs,
 };
 
 static void ssb_buses_lock(void)
@@ -1088,23 +1117,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
 {
         u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
 
-        /* The REJECT bit changed position in TMSLOW between
-         * Backplane revisions. */
+        /* The REJECT bit seems to be different for Backplane rev 2.3 */
         switch (rev) {
         case SSB_IDLOW_SSBREV_22:
-                return SSB_TMSLOW_REJECT_22;
+        case SSB_IDLOW_SSBREV_24:
+        case SSB_IDLOW_SSBREV_26:
+                return SSB_TMSLOW_REJECT;
         case SSB_IDLOW_SSBREV_23:
                 return SSB_TMSLOW_REJECT_23;
-        case SSB_IDLOW_SSBREV_24:     /* TODO - find the proper REJECT bits */
-        case SSB_IDLOW_SSBREV_25:     /* same here */
-        case SSB_IDLOW_SSBREV_26:     /* same here */
+        case SSB_IDLOW_SSBREV_25:     /* TODO - find the proper REJECT bit */
         case SSB_IDLOW_SSBREV_27:     /* same here */
-                return SSB_TMSLOW_REJECT_23;    /* this is a guess */
+                return SSB_TMSLOW_REJECT;       /* this is a guess */
         default:
                 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
                 WARN_ON(1);
         }
-        return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
+        return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
 }
 
 int ssb_device_is_enabled(struct ssb_device *dev)
@@ -1163,10 +1191,10 @@ void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
 }
 EXPORT_SYMBOL(ssb_device_enable);
 
-/* Wait for a bit in a register to get set or unset.
+/* Wait for bitmask in a register to get set or cleared.
  * timeout is in units of ten-microseconds */
-static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
-                        int timeout, int set)
+static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
+                         int timeout, int set)
 {
         int i;
         u32 val;
@@ -1174,7 +1202,7 @@ static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
         for (i = 0; i < timeout; i++) {
                 val = ssb_read32(dev, reg);
                 if (set) {
-                        if (val & bitmask)
+                        if ((val & bitmask) == bitmask)
                                 return 0;
                 } else {
                         if (!(val & bitmask))
@@ -1191,20 +1219,38 @@ static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
 
 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
 {
-        u32 reject;
+        u32 reject, val;
 
         if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
                 return;
 
         reject = ssb_tmslow_reject_bitmask(dev);
-        ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
-        ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
-        ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
-        ssb_write32(dev, SSB_TMSLOW,
-                    SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
-                    reject | SSB_TMSLOW_RESET |
-                    core_specific_flags);
-        ssb_flush_tmslow(dev);
+
+        if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
+                ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
+                ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
+                ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
+
+                if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
+                        val = ssb_read32(dev, SSB_IMSTATE);
+                        val |= SSB_IMSTATE_REJECT;
+                        ssb_write32(dev, SSB_IMSTATE, val);
+                        ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
+                                      0);
+                }
+
+                ssb_write32(dev, SSB_TMSLOW,
+                        SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
+                        reject | SSB_TMSLOW_RESET |
+                        core_specific_flags);
+                ssb_flush_tmslow(dev);
+
+                if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
+                        val = ssb_read32(dev, SSB_IMSTATE);
+                        val &= ~SSB_IMSTATE_REJECT;
+                        ssb_write32(dev, SSB_IMSTATE, val);
+                }
+        }
 
         ssb_write32(dev, SSB_TMSLOW,
                     reject | SSB_TMSLOW_RESET |
@@ -1262,20 +1308,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
 
 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
 {
-        struct ssb_chipcommon *cc;
         int err;
         enum ssb_clkmode mode;
 
         err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
         if (err)
                 goto error;
-        cc = &bus->chipco;
-        mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
-        ssb_chipco_set_clockmode(cc, mode);
 
 #ifdef CONFIG_SSB_DEBUG
         bus->powered_up = 1;
 #endif
+
+        mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
+        ssb_chipco_set_clockmode(&bus->chipco, mode);
+
         return 0;
 error:
         ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
@@ -1283,6 +1329,37 @@ error:
 }
 EXPORT_SYMBOL(ssb_bus_powerup);
 
+static void ssb_broadcast_value(struct ssb_device *dev,
+                                u32 address, u32 data)
+{
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        /* This is used for both, PCI and ChipCommon core, so be careful. */
+        BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+        BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+#endif
+
+        ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
+        ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
+        ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
+        ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
+}
+
+void ssb_commit_settings(struct ssb_bus *bus)
+{
+        struct ssb_device *dev;
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+#else
+        dev = bus->chipco.dev;
+#endif
+        if (WARN_ON(!dev))
+                return;
+        /* This forces an update of the cached registers. */
+        ssb_broadcast_value(dev, 0xFD8, 0);
+}
+EXPORT_SYMBOL(ssb_commit_settings);
+
 u32 ssb_admatch_base(u32 adm)
 {
         u32 base = 0;
diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
index 6e88d2b603b4..7ad48585c5e6 100644
--- a/drivers/ssb/pci.c
+++ b/drivers/ssb/pci.c
@@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
         out->antenna_gain.ghz5.a3 = gain;
 }
 
+/* Revs 4 5 and 8 have partially shared layout */
+static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
+{
+        SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
+             SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
+        SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
+             SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
+        SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
+             SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
+        SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
+             SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
+
+        SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
+             SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
+        SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
+             SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
+        SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
+             SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
+        SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
+             SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
+
+        SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
+             SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
+        SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
+             SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
+        SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
+             SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
+        SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
+             SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
+
+        SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
+             SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
+        SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
+             SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
+        SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
+             SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
+        SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
+             SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
+}
+
 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
 {
         int i;
@@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
                 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
+                SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
+                SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
         } else {
                 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
+                SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
+                SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
         }
         SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
              SSB_SPROM4_ANTAVAIL_A_SHIFT);
@@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
         memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
                sizeof(out->antenna_gain.ghz5));
 
+        sprom_extract_r458(out, in);
+
         /* TODO - get remaining rev 4 stuff needed */
 }
 
@@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
         memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
                sizeof(out->antenna_gain.ghz5));
 
+        sprom_extract_r458(out, in);
+
         /* TODO - get remaining rev 8 stuff needed */
 }
 
@@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
         ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
         memset(out->et0mac, 0xFF, 6);           /* preset et0 and et1 mac */
         memset(out->et1mac, 0xFF, 6);
+
         if ((bus->chip_id & 0xFF00) == 0x4400) {
                 /* Workaround: The BCM44XX chip has a stupid revision
                  * number stored in the SPROM.
                  * Always extract r1. */
                 out->revision = 1;
+                ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
+        }
+
+        switch (out->revision) {
+        case 1:
+        case 2:
+        case 3:
                 sprom_extract_r123(out, in);
-        } else if (bus->chip_id == 0x4321) {
-                /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
-                out->revision = 4;
+                break;
+        case 4:
+        case 5:
                 sprom_extract_r45(out, in);
-        } else {
-                switch (out->revision) {
-                case 1:
-                case 2:
-                case 3:
-                        sprom_extract_r123(out, in);
-                        break;
-                case 4:
-                case 5:
-                        sprom_extract_r45(out, in);
-                        break;
-                case 8:
-                        sprom_extract_r8(out, in);
-                        break;
-                default:
-                        ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
-                                   "  revision %d detected. Will extract"
-                                   " v1\n", out->revision);
-                        out->revision = 1;
-                        sprom_extract_r123(out, in);
-                }
+                break;
+        case 8:
+                sprom_extract_r8(out, in);
+                break;
+        default:
+                ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
+                           " revision %d detected. Will extract"
+                           " v1\n", out->revision);
+                out->revision = 1;
+                sprom_extract_r123(out, in);
         }
 
         if (out->boardflags_lo == 0xFFFF)
@@ -617,15 +662,14 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
 static int ssb_pci_sprom_get(struct ssb_bus *bus,
                              struct ssb_sprom *sprom)
 {
-        const struct ssb_sprom *fallback;
-        int err = -ENOMEM;
+        int err;
         u16 *buf;
 
         if (!ssb_is_sprom_available(bus)) {
                 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
                 return -ENODEV;
         }
-        if (bus->chipco.dev) {  /* can be unavailible! */
+        if (bus->chipco.dev) {  /* can be unavailable! */
                 /*
                  * get SPROM offset: SSB_SPROM_BASE1 except for
                  * chipcommon rev >= 31 or chip ID is 0x4312 and
@@ -645,7 +689,7 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
 
         buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
         if (!buf)
-                goto out;
+                return -ENOMEM;
         bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
         sprom_do_read(bus, buf);
         err = sprom_check_crc(buf, bus->sprom_size);
@@ -655,17 +699,24 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
                 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
                               GFP_KERNEL);
                 if (!buf)
-                        goto out;
+                        return -ENOMEM;
                 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
                 sprom_do_read(bus, buf);
                 err = sprom_check_crc(buf, bus->sprom_size);
                 if (err) {
                         /* All CRC attempts failed.
                          * Maybe there is no SPROM on the device?
-                         * If we have a fallback, use that. */
-                        fallback = ssb_get_fallback_sprom();
-                        if (fallback) {
-                                memcpy(sprom, fallback, sizeof(*sprom));
+                         * Now we ask the arch code if there is some sprom
+                         * available for this device in some other storage */
+                        err = ssb_fill_sprom_with_fallback(bus, sprom);
+                        if (err) {
+                                ssb_printk(KERN_WARNING PFX "WARNING: Using"
+                                           " fallback SPROM failed (err %d)\n",
+                                           err);
+                        } else {
+                                ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
+                                            " revision %d provided by"
+                                            " platform.\n", sprom->revision);
                                 err = 0;
                                 goto out_free;
                         }
@@ -677,7 +728,6 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
 
 out_free:
         kfree(buf);
-out:
         return err;
 }
 
diff --git a/drivers/ssb/pcihost_wrapper.c b/drivers/ssb/pcihost_wrapper.c
index 6536a041d90d..f6c8c81a0025 100644
--- a/drivers/ssb/pcihost_wrapper.c
+++ b/drivers/ssb/pcihost_wrapper.c
@@ -59,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_dev *dev,
         struct ssb_bus *ssb;
         int err = -ENOMEM;
         const char *name;
+        u32 val;
 
         ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
         if (!ssb)
@@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_dev *dev,
                 goto err_pci_disable;
         pci_set_master(dev);
 
+        /* Disable the RETRY_TIMEOUT register (0x41) to keep
+         * PCI Tx retries from interfering with C3 CPU state */
+        pci_read_config_dword(dev, 0x40, &val);
+        if ((val & 0x0000ff00) != 0)
+                pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
+
         err = ssb_bus_pcibus_register(ssb, dev);
         if (err)
                 goto err_pci_release_regions;
diff --git a/drivers/ssb/pcmcia.c b/drivers/ssb/pcmcia.c
index 526682d68de8..f8533795ee7f 100644
--- a/drivers/ssb/pcmcia.c
+++ b/drivers/ssb/pcmcia.c
@@ -13,7 +13,6 @@
 #include <linux/io.h>
 #include <linux/etherdevice.h>
 
-#include <pcmcia/cs.h>
 #include <pcmcia/cistpl.h>
 #include <pcmcia/ciscode.h>
 #include <pcmcia/ds.h>
@@ -734,7 +733,7 @@ int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
 
         /* Fetch the vendor specific tuples. */
         res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
-                                ssb_pcmcia_do_get_invariants, sprom);
+                                ssb_pcmcia_do_get_invariants, iv);
         if ((res == 0) || (res == -ENOSPC))
                 return 0;
 
diff --git a/drivers/ssb/scan.c b/drivers/ssb/scan.c
index 9738cad4ba13..45e5babd3961 100644
--- a/drivers/ssb/scan.c
+++ b/drivers/ssb/scan.c
@@ -17,7 +17,6 @@
 #include <linux/pci.h>
 #include <linux/io.h>
 
-#include <pcmcia/cs.h>
 #include <pcmcia/cistpl.h>
 #include <pcmcia/ds.h>
 
@@ -259,7 +258,10 @@ static int we_support_multiple_80211_cores(struct ssb_bus *bus)
 #ifdef CONFIG_SSB_PCIHOST
         if (bus->bustype == SSB_BUSTYPE_PCI) {
                 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
-                    bus->host_pci->device == 0x4324)
+                    ((bus->host_pci->device == 0x4313) ||
+                     (bus->host_pci->device == 0x431A) ||
+                     (bus->host_pci->device == 0x4321) ||
+                     (bus->host_pci->device == 0x4324)))
                         return 1;
         }
 #endif /* CONFIG_SSB_PCIHOST */
@@ -308,7 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
         } else {
                 if (bus->bustype == SSB_BUSTYPE_PCI) {
                         bus->chip_id = pcidev_to_chipid(bus->host_pci);
-                        pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
+                        pci_read_config_byte(bus->host_pci, PCI_REVISION_ID,
                                              &bus->chip_rev);
                         bus->chip_package = 0;
                 } else {
@@ -406,10 +408,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
                                 /* Ignore PCI cores on PCI-E cards.
                                  * Ignore PCI-E cores on PCI cards. */
                                 if (dev->id.coreid == SSB_DEV_PCI) {
-                                        if (bus->host_pci->is_pcie)
+                                        if (pci_is_pcie(bus->host_pci))
                                                 continue;
                                 } else {
-                                        if (!bus->host_pci->is_pcie)
+                                        if (!pci_is_pcie(bus->host_pci))
                                                 continue;
                                 }
                         }
@@ -421,6 +423,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
                         bus->pcicore.dev = dev;
 #endif /* CONFIG_SSB_DRIVER_PCICORE */
                         break;
+                case SSB_DEV_ETHERNET:
+                        if (bus->bustype == SSB_BUSTYPE_PCI) {
+                                if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
+                                    (bus->host_pci->device & 0xFF00) == 0x4300) {
+                                        /* This is a dangling ethernet core on a
+                                         * wireless device. Ignore it. */
+                                        continue;
+                                }
+                        }
+                        break;
                 default:
                         break;
                 }
diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
index 4f7cc8d13277..45ff0e3a3828 100644
--- a/drivers/ssb/sprom.c
+++ b/drivers/ssb/sprom.c
@@ -17,7 +17,7 @@
 #include <linux/slab.h>
 
 
-static const struct ssb_sprom *fallback_sprom;
+static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
 
 
 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
@@ -145,36 +145,43 @@ out:
 }
 
 /**
- * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
+ * ssb_arch_register_fallback_sprom - Registers a method providing a
+ * fallback SPROM if no SPROM is found.
  *
- * @sprom: The SPROM data structure to register.
+ * @sprom_callback: The callback function.
  *
- * With this function the architecture implementation may register a fallback
- * SPROM data structure. The fallback is only used for PCI based SSB devices,
- * where no valid SPROM can be found in the shadow registers.
+ * With this function the architecture implementation may register a
+ * callback handler which fills the SPROM data structure. The fallback is
+ * only used for PCI based SSB devices, where no valid SPROM can be found
+ * in the shadow registers.
  *
- * This function is useful for weird architectures that have a half-assed SSB device
- * hardwired to their PCI bus.
+ * This function is useful for weird architectures that have a half-assed
+ * SSB device hardwired to their PCI bus.
  *
- * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
- * don't use this fallback.
- * Architectures must provide the SPROM for native SSB devices anyway,
- * so the fallback also isn't used for native devices.
+ * Note that it does only work with PCI attached SSB devices. PCMCIA
+ * devices currently don't use this fallback.
+ * Architectures must provide the SPROM for native SSB devices anyway, so
+ * the fallback also isn't used for native devices.
  *
- * This function is available for architecture code, only. So it is not exported.
+ * This function is available for architecture code, only. So it is not
+ * exported.
  */
-int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
+int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
+                                     struct ssb_sprom *out))
 {
-        if (fallback_sprom)
+        if (get_fallback_sprom)
                 return -EEXIST;
-        fallback_sprom = sprom;
+        get_fallback_sprom = sprom_callback;
 
         return 0;
 }
 
-const struct ssb_sprom *ssb_get_fallback_sprom(void)
+int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
 {
-        return fallback_sprom;
+        if (!get_fallback_sprom)
+                return -ENOENT;
+
+        return get_fallback_sprom(bus, out);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
@@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_bus *bus)
         /* this routine differs from specs as we do not access SPROM directly
            on PCMCIA */
         if (bus->bustype == SSB_BUSTYPE_PCI &&
-            bus->chipco.dev &&  /* can be unavailible! */
+            bus->chipco.dev &&  /* can be unavailable! */
             bus->chipco.dev->id.revision >= 31)
                 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
 
diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
index 0331139a726f..77653014db0b 100644
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
@@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_bus *bus,
                              const char *buf, size_t count,
                              int (*sprom_check_crc)(const u16 *sprom, size_t size),
                              int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
-extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
+extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
+                                        struct ssb_sprom *out);
 
 
 /* core.c */