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path: root/drivers/spi/spi_imx.c
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Diffstat (limited to 'drivers/spi/spi_imx.c')
-rw-r--r--drivers/spi/spi_imx.c390
1 files changed, 322 insertions, 68 deletions
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 7972e9077473..69d6dba67c19 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -56,7 +56,27 @@ struct spi_imx_config {
56 unsigned int speed_hz; 56 unsigned int speed_hz;
57 unsigned int bpw; 57 unsigned int bpw;
58 unsigned int mode; 58 unsigned int mode;
59 int cs; 59 u8 cs;
60};
61
62enum spi_imx_devtype {
63 SPI_IMX_VER_IMX1,
64 SPI_IMX_VER_0_0,
65 SPI_IMX_VER_0_4,
66 SPI_IMX_VER_0_5,
67 SPI_IMX_VER_0_7,
68 SPI_IMX_VER_2_3,
69};
70
71struct spi_imx_data;
72
73struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
78 void (*reset)(struct spi_imx_data *);
79 unsigned int fifosize;
60}; 80};
61 81
62struct spi_imx_data { 82struct spi_imx_data {
@@ -76,11 +96,7 @@ struct spi_imx_data {
76 const void *tx_buf; 96 const void *tx_buf;
77 unsigned int txfifo; /* number of words pushed in tx FIFO */ 97 unsigned int txfifo; /* number of words pushed in tx FIFO */
78 98
79 /* SoC specific functions */ 99 struct spi_imx_devtype_data devtype_data;
80 void (*intctrl)(struct spi_imx_data *, int);
81 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
82 void (*trigger)(struct spi_imx_data *);
83 int (*rx_available)(struct spi_imx_data *);
84}; 100};
85 101
86#define MXC_SPI_BUF_RX(type) \ 102#define MXC_SPI_BUF_RX(type) \
@@ -140,7 +156,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin,
140 return max; 156 return max;
141} 157}
142 158
143/* MX1, MX31, MX35 */ 159/* MX1, MX31, MX35, MX51 CSPI */
144static unsigned int spi_imx_clkdiv_2(unsigned int fin, 160static unsigned int spi_imx_clkdiv_2(unsigned int fin,
145 unsigned int fspi) 161 unsigned int fspi)
146{ 162{
@@ -155,6 +171,134 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
155 return 7; 171 return 7;
156} 172}
157 173
174#define SPI_IMX2_3_CTRL 0x08
175#define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
176#define SPI_IMX2_3_CTRL_XCH (1 << 2)
177#define SPI_IMX2_3_CTRL_MODE_MASK (0xf << 4)
178#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
179#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
180#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
181#define SPI_IMX2_3_CTRL_BL_OFFSET 20
182
183#define SPI_IMX2_3_CONFIG 0x0c
184#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
185#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
186#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
187#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
188
189#define SPI_IMX2_3_INT 0x10
190#define SPI_IMX2_3_INT_TEEN (1 << 0)
191#define SPI_IMX2_3_INT_RREN (1 << 3)
192
193#define SPI_IMX2_3_STAT 0x18
194#define SPI_IMX2_3_STAT_RR (1 << 3)
195
196/* MX51 eCSPI */
197static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi)
198{
199 /*
200 * there are two 4-bit dividers, the pre-divider divides by
201 * $pre, the post-divider by 2^$post
202 */
203 unsigned int pre, post;
204
205 if (unlikely(fspi > fin))
206 return 0;
207
208 post = fls(fin) - fls(fspi);
209 if (fin > fspi << post)
210 post++;
211
212 /* now we have: (fin <= fspi << post) with post being minimal */
213
214 post = max(4U, post) - 4;
215 if (unlikely(post > 0xf)) {
216 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
217 __func__, fspi, fin);
218 return 0xff;
219 }
220
221 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
222
223 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
224 __func__, fin, fspi, post, pre);
225 return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) |
226 (post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET);
227}
228
229static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable)
230{
231 unsigned val = 0;
232
233 if (enable & MXC_INT_TE)
234 val |= SPI_IMX2_3_INT_TEEN;
235
236 if (enable & MXC_INT_RR)
237 val |= SPI_IMX2_3_INT_RREN;
238
239 writel(val, spi_imx->base + SPI_IMX2_3_INT);
240}
241
242static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx)
243{
244 u32 reg;
245
246 reg = readl(spi_imx->base + SPI_IMX2_3_CTRL);
247 reg |= SPI_IMX2_3_CTRL_XCH;
248 writel(reg, spi_imx->base + SPI_IMX2_3_CTRL);
249}
250
251static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
252 struct spi_imx_config *config)
253{
254 u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;
255
256 /*
257 * The hardware seems to have a race condition when changing modes. The
258 * current assumption is that the selection of the channel arrives
259 * earlier in the hardware than the mode bits when they are written at
260 * the same time.
261 * So set master mode for all channels as we do not support slave mode.
262 */
263 ctrl |= SPI_IMX2_3_CTRL_MODE_MASK;
264
265 /* set clock speed */
266 ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);
267
268 /* set chip select to use */
269 ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);
270
271 ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;
272
273 cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);
274
275 if (config->mode & SPI_CPHA)
276 cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);
277
278 if (config->mode & SPI_CPOL)
279 cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);
280
281 if (config->mode & SPI_CS_HIGH)
282 cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);
283
284 writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
285 writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);
286
287 return 0;
288}
289
290static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx)
291{
292 return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR;
293}
294
295static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx)
296{
297 /* drain receive buffer */
298 while (spi_imx2_3_rx_available(spi_imx))
299 readl(spi_imx->base + MXC_CSPIRXDATA);
300}
301
158#define MX31_INTREG_TEEN (1 << 0) 302#define MX31_INTREG_TEEN (1 << 0)
159#define MX31_INTREG_RREN (1 << 3) 303#define MX31_INTREG_RREN (1 << 3)
160 304
@@ -178,7 +322,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
178 * the i.MX35 has a slightly different register layout for bits 322 * the i.MX35 has a slightly different register layout for bits
179 * we do not use here. 323 * we do not use here.
180 */ 324 */
181static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 325static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
182{ 326{
183 unsigned int val = 0; 327 unsigned int val = 0;
184 328
@@ -190,7 +334,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
190 writel(val, spi_imx->base + MXC_CSPIINT); 334 writel(val, spi_imx->base + MXC_CSPIINT);
191} 335}
192 336
193static void mx31_trigger(struct spi_imx_data *spi_imx) 337static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
194{ 338{
195 unsigned int reg; 339 unsigned int reg;
196 340
@@ -199,20 +343,16 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
199 writel(reg, spi_imx->base + MXC_CSPICTRL); 343 writel(reg, spi_imx->base + MXC_CSPICTRL);
200} 344}
201 345
202static int mx31_config(struct spi_imx_data *spi_imx, 346static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
203 struct spi_imx_config *config) 347 struct spi_imx_config *config)
204{ 348{
205 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 349 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
350 int cs = spi_imx->chipselect[config->cs];
206 351
207 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 352 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
208 MX31_CSPICTRL_DR_SHIFT; 353 MX31_CSPICTRL_DR_SHIFT;
209 354
210 if (cpu_is_mx31()) 355 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
211 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
212 else if (cpu_is_mx25() || cpu_is_mx35()) {
213 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
214 reg |= MX31_CSPICTRL_SSCTL;
215 }
216 356
217 if (config->mode & SPI_CPHA) 357 if (config->mode & SPI_CPHA)
218 reg |= MX31_CSPICTRL_PHA; 358 reg |= MX31_CSPICTRL_PHA;
@@ -220,23 +360,52 @@ static int mx31_config(struct spi_imx_data *spi_imx,
220 reg |= MX31_CSPICTRL_POL; 360 reg |= MX31_CSPICTRL_POL;
221 if (config->mode & SPI_CS_HIGH) 361 if (config->mode & SPI_CS_HIGH)
222 reg |= MX31_CSPICTRL_SSPOL; 362 reg |= MX31_CSPICTRL_SSPOL;
223 if (config->cs < 0) { 363 if (cs < 0)
224 if (cpu_is_mx31()) 364 reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
225 reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT; 365
226 else if (cpu_is_mx25() || cpu_is_mx35()) 366 writel(reg, spi_imx->base + MXC_CSPICTRL);
227 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; 367
228 } 368 return 0;
369}
370
371static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
372 struct spi_imx_config *config)
373{
374 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
375 int cs = spi_imx->chipselect[config->cs];
376
377 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
378 MX31_CSPICTRL_DR_SHIFT;
379
380 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
381 reg |= MX31_CSPICTRL_SSCTL;
382
383 if (config->mode & SPI_CPHA)
384 reg |= MX31_CSPICTRL_PHA;
385 if (config->mode & SPI_CPOL)
386 reg |= MX31_CSPICTRL_POL;
387 if (config->mode & SPI_CS_HIGH)
388 reg |= MX31_CSPICTRL_SSPOL;
389 if (cs < 0)
390 reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
229 391
230 writel(reg, spi_imx->base + MXC_CSPICTRL); 392 writel(reg, spi_imx->base + MXC_CSPICTRL);
231 393
232 return 0; 394 return 0;
233} 395}
234 396
235static int mx31_rx_available(struct spi_imx_data *spi_imx) 397static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
236{ 398{
237 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 399 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
238} 400}
239 401
402static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
403{
404 /* drain receive buffer */
405 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
406 readl(spi_imx->base + MXC_CSPIRXDATA);
407}
408
240#define MX27_INTREG_RR (1 << 4) 409#define MX27_INTREG_RR (1 << 4)
241#define MX27_INTREG_TEEN (1 << 9) 410#define MX27_INTREG_TEEN (1 << 9)
242#define MX27_INTREG_RREN (1 << 13) 411#define MX27_INTREG_RREN (1 << 13)
@@ -250,7 +419,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
250#define MX27_CSPICTRL_DR_SHIFT 14 419#define MX27_CSPICTRL_DR_SHIFT 14
251#define MX27_CSPICTRL_CS_SHIFT 19 420#define MX27_CSPICTRL_CS_SHIFT 19
252 421
253static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) 422static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
254{ 423{
255 unsigned int val = 0; 424 unsigned int val = 0;
256 425
@@ -262,7 +431,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
262 writel(val, spi_imx->base + MXC_CSPIINT); 431 writel(val, spi_imx->base + MXC_CSPIINT);
263} 432}
264 433
265static void mx27_trigger(struct spi_imx_data *spi_imx) 434static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
266{ 435{
267 unsigned int reg; 436 unsigned int reg;
268 437
@@ -271,10 +440,11 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
271 writel(reg, spi_imx->base + MXC_CSPICTRL); 440 writel(reg, spi_imx->base + MXC_CSPICTRL);
272} 441}
273 442
274static int mx27_config(struct spi_imx_data *spi_imx, 443static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
275 struct spi_imx_config *config) 444 struct spi_imx_config *config)
276{ 445{
277 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; 446 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
447 int cs = spi_imx->chipselect[config->cs];
278 448
279 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << 449 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
280 MX27_CSPICTRL_DR_SHIFT; 450 MX27_CSPICTRL_DR_SHIFT;
@@ -286,19 +456,24 @@ static int mx27_config(struct spi_imx_data *spi_imx,
286 reg |= MX27_CSPICTRL_POL; 456 reg |= MX27_CSPICTRL_POL;
287 if (config->mode & SPI_CS_HIGH) 457 if (config->mode & SPI_CS_HIGH)
288 reg |= MX27_CSPICTRL_SSPOL; 458 reg |= MX27_CSPICTRL_SSPOL;
289 if (config->cs < 0) 459 if (cs < 0)
290 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; 460 reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
291 461
292 writel(reg, spi_imx->base + MXC_CSPICTRL); 462 writel(reg, spi_imx->base + MXC_CSPICTRL);
293 463
294 return 0; 464 return 0;
295} 465}
296 466
297static int mx27_rx_available(struct spi_imx_data *spi_imx) 467static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
298{ 468{
299 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; 469 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
300} 470}
301 471
472static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
473{
474 writel(1, spi_imx->base + MXC_RESET);
475}
476
302#define MX1_INTREG_RR (1 << 3) 477#define MX1_INTREG_RR (1 << 3)
303#define MX1_INTREG_TEEN (1 << 8) 478#define MX1_INTREG_TEEN (1 << 8)
304#define MX1_INTREG_RREN (1 << 11) 479#define MX1_INTREG_RREN (1 << 11)
@@ -310,7 +485,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
310#define MX1_CSPICTRL_MASTER (1 << 10) 485#define MX1_CSPICTRL_MASTER (1 << 10)
311#define MX1_CSPICTRL_DR_SHIFT 13 486#define MX1_CSPICTRL_DR_SHIFT 13
312 487
313static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 488static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
314{ 489{
315 unsigned int val = 0; 490 unsigned int val = 0;
316 491
@@ -322,7 +497,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
322 writel(val, spi_imx->base + MXC_CSPIINT); 497 writel(val, spi_imx->base + MXC_CSPIINT);
323} 498}
324 499
325static void mx1_trigger(struct spi_imx_data *spi_imx) 500static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
326{ 501{
327 unsigned int reg; 502 unsigned int reg;
328 503
@@ -331,7 +506,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
331 writel(reg, spi_imx->base + MXC_CSPICTRL); 506 writel(reg, spi_imx->base + MXC_CSPICTRL);
332} 507}
333 508
334static int mx1_config(struct spi_imx_data *spi_imx, 509static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
335 struct spi_imx_config *config) 510 struct spi_imx_config *config)
336{ 511{
337 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 512 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
@@ -350,11 +525,73 @@ static int mx1_config(struct spi_imx_data *spi_imx,
350 return 0; 525 return 0;
351} 526}
352 527
353static int mx1_rx_available(struct spi_imx_data *spi_imx) 528static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
354{ 529{
355 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 530 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
356} 531}
357 532
533static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
534{
535 writel(1, spi_imx->base + MXC_RESET);
536}
537
538/*
539 * These version numbers are taken from the Freescale driver. Unfortunately it
540 * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
541 */
542static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
543#ifdef CONFIG_SPI_IMX_VER_IMX1
544 [SPI_IMX_VER_IMX1] = {
545 .intctrl = mx1_intctrl,
546 .config = mx1_config,
547 .trigger = mx1_trigger,
548 .rx_available = mx1_rx_available,
549 .reset = mx1_reset,
550 .fifosize = 8,
551 },
552#endif
553#ifdef CONFIG_SPI_IMX_VER_0_0
554 [SPI_IMX_VER_0_0] = {
555 .intctrl = mx27_intctrl,
556 .config = mx27_config,
557 .trigger = mx27_trigger,
558 .rx_available = mx27_rx_available,
559 .reset = spi_imx0_0_reset,
560 .fifosize = 8,
561 },
562#endif
563#ifdef CONFIG_SPI_IMX_VER_0_4
564 [SPI_IMX_VER_0_4] = {
565 .intctrl = mx31_intctrl,
566 .config = spi_imx0_4_config,
567 .trigger = mx31_trigger,
568 .rx_available = mx31_rx_available,
569 .reset = spi_imx0_4_reset,
570 .fifosize = 8,
571 },
572#endif
573#ifdef CONFIG_SPI_IMX_VER_0_7
574 [SPI_IMX_VER_0_7] = {
575 .intctrl = mx31_intctrl,
576 .config = spi_imx0_7_config,
577 .trigger = mx31_trigger,
578 .rx_available = mx31_rx_available,
579 .reset = spi_imx0_4_reset,
580 .fifosize = 8,
581 },
582#endif
583#ifdef CONFIG_SPI_IMX_VER_2_3
584 [SPI_IMX_VER_2_3] = {
585 .intctrl = spi_imx2_3_intctrl,
586 .config = spi_imx2_3_config,
587 .trigger = spi_imx2_3_trigger,
588 .rx_available = spi_imx2_3_rx_available,
589 .reset = spi_imx2_3_reset,
590 .fifosize = 64,
591 },
592#endif
593};
594
358static void spi_imx_chipselect(struct spi_device *spi, int is_active) 595static void spi_imx_chipselect(struct spi_device *spi, int is_active)
359{ 596{
360 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 597 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
@@ -370,21 +607,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
370 607
371static void spi_imx_push(struct spi_imx_data *spi_imx) 608static void spi_imx_push(struct spi_imx_data *spi_imx)
372{ 609{
373 while (spi_imx->txfifo < 8) { 610 while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) {
374 if (!spi_imx->count) 611 if (!spi_imx->count)
375 break; 612 break;
376 spi_imx->tx(spi_imx); 613 spi_imx->tx(spi_imx);
377 spi_imx->txfifo++; 614 spi_imx->txfifo++;
378 } 615 }
379 616
380 spi_imx->trigger(spi_imx); 617 spi_imx->devtype_data.trigger(spi_imx);
381} 618}
382 619
383static irqreturn_t spi_imx_isr(int irq, void *dev_id) 620static irqreturn_t spi_imx_isr(int irq, void *dev_id)
384{ 621{
385 struct spi_imx_data *spi_imx = dev_id; 622 struct spi_imx_data *spi_imx = dev_id;
386 623
387 while (spi_imx->rx_available(spi_imx)) { 624 while (spi_imx->devtype_data.rx_available(spi_imx)) {
388 spi_imx->rx(spi_imx); 625 spi_imx->rx(spi_imx);
389 spi_imx->txfifo--; 626 spi_imx->txfifo--;
390 } 627 }
@@ -398,11 +635,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
398 /* No data left to push, but still waiting for rx data, 635 /* No data left to push, but still waiting for rx data,
399 * enable receive data available interrupt. 636 * enable receive data available interrupt.
400 */ 637 */
401 spi_imx->intctrl(spi_imx, MXC_INT_RR); 638 spi_imx->devtype_data.intctrl(
639 spi_imx, MXC_INT_RR);
402 return IRQ_HANDLED; 640 return IRQ_HANDLED;
403 } 641 }
404 642
405 spi_imx->intctrl(spi_imx, 0); 643 spi_imx->devtype_data.intctrl(spi_imx, 0);
406 complete(&spi_imx->xfer_done); 644 complete(&spi_imx->xfer_done);
407 645
408 return IRQ_HANDLED; 646 return IRQ_HANDLED;
@@ -417,7 +655,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
417 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 655 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
418 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 656 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
419 config.mode = spi->mode; 657 config.mode = spi->mode;
420 config.cs = spi_imx->chipselect[spi->chip_select]; 658 config.cs = spi->chip_select;
421 659
422 if (!config.speed_hz) 660 if (!config.speed_hz)
423 config.speed_hz = spi->max_speed_hz; 661 config.speed_hz = spi->max_speed_hz;
@@ -439,7 +677,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
439 } else 677 } else
440 BUG(); 678 BUG();
441 679
442 spi_imx->config(spi_imx, &config); 680 spi_imx->devtype_data.config(spi_imx, &config);
443 681
444 return 0; 682 return 0;
445} 683}
@@ -458,7 +696,7 @@ static int spi_imx_transfer(struct spi_device *spi,
458 696
459 spi_imx_push(spi_imx); 697 spi_imx_push(spi_imx);
460 698
461 spi_imx->intctrl(spi_imx, MXC_INT_TE); 699 spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
462 700
463 wait_for_completion(&spi_imx->xfer_done); 701 wait_for_completion(&spi_imx->xfer_done);
464 702
@@ -485,6 +723,42 @@ static void spi_imx_cleanup(struct spi_device *spi)
485{ 723{
486} 724}
487 725
726static struct platform_device_id spi_imx_devtype[] = {
727 {
728 .name = "imx1-cspi",
729 .driver_data = SPI_IMX_VER_IMX1,
730 }, {
731 .name = "imx21-cspi",
732 .driver_data = SPI_IMX_VER_0_0,
733 }, {
734 .name = "imx25-cspi",
735 .driver_data = SPI_IMX_VER_0_7,
736 }, {
737 .name = "imx27-cspi",
738 .driver_data = SPI_IMX_VER_0_0,
739 }, {
740 .name = "imx31-cspi",
741 .driver_data = SPI_IMX_VER_0_4,
742 }, {
743 .name = "imx35-cspi",
744 .driver_data = SPI_IMX_VER_0_7,
745 }, {
746 .name = "imx51-cspi",
747 .driver_data = SPI_IMX_VER_0_7,
748 }, {
749 .name = "imx51-ecspi",
750 .driver_data = SPI_IMX_VER_2_3,
751 }, {
752 .name = "imx53-cspi",
753 .driver_data = SPI_IMX_VER_0_7,
754 }, {
755 .name = "imx53-ecspi",
756 .driver_data = SPI_IMX_VER_2_3,
757 }, {
758 /* sentinel */
759 }
760};
761
488static int __devinit spi_imx_probe(struct platform_device *pdev) 762static int __devinit spi_imx_probe(struct platform_device *pdev)
489{ 763{
490 struct spi_imx_master *mxc_platform_info; 764 struct spi_imx_master *mxc_platform_info;
@@ -536,6 +810,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
536 810
537 init_completion(&spi_imx->xfer_done); 811 init_completion(&spi_imx->xfer_done);
538 812
813 spi_imx->devtype_data =
814 spi_imx_devtype_data[pdev->id_entry->driver_data];
815
539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 816 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 if (!res) { 817 if (!res) {
541 dev_err(&pdev->dev, "can't get platform resource\n"); 818 dev_err(&pdev->dev, "can't get platform resource\n");
@@ -556,7 +833,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
556 } 833 }
557 834
558 spi_imx->irq = platform_get_irq(pdev, 0); 835 spi_imx->irq = platform_get_irq(pdev, 0);
559 if (spi_imx->irq <= 0) { 836 if (spi_imx->irq < 0) {
560 ret = -EINVAL; 837 ret = -EINVAL;
561 goto out_iounmap; 838 goto out_iounmap;
562 } 839 }
@@ -567,24 +844,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
567 goto out_iounmap; 844 goto out_iounmap;
568 } 845 }
569 846
570 if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
571 spi_imx->intctrl = mx31_intctrl;
572 spi_imx->config = mx31_config;
573 spi_imx->trigger = mx31_trigger;
574 spi_imx->rx_available = mx31_rx_available;
575 } else if (cpu_is_mx27() || cpu_is_mx21()) {
576 spi_imx->intctrl = mx27_intctrl;
577 spi_imx->config = mx27_config;
578 spi_imx->trigger = mx27_trigger;
579 spi_imx->rx_available = mx27_rx_available;
580 } else if (cpu_is_mx1()) {
581 spi_imx->intctrl = mx1_intctrl;
582 spi_imx->config = mx1_config;
583 spi_imx->trigger = mx1_trigger;
584 spi_imx->rx_available = mx1_rx_available;
585 } else
586 BUG();
587
588 spi_imx->clk = clk_get(&pdev->dev, NULL); 847 spi_imx->clk = clk_get(&pdev->dev, NULL);
589 if (IS_ERR(spi_imx->clk)) { 848 if (IS_ERR(spi_imx->clk)) {
590 dev_err(&pdev->dev, "unable to get clock\n"); 849 dev_err(&pdev->dev, "unable to get clock\n");
@@ -595,15 +854,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
595 clk_enable(spi_imx->clk); 854 clk_enable(spi_imx->clk);
596 spi_imx->spi_clk = clk_get_rate(spi_imx->clk); 855 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
597 856
598 if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) 857 spi_imx->devtype_data.reset(spi_imx);
599 writel(1, spi_imx->base + MXC_RESET);
600
601 /* drain receive buffer */
602 if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
603 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
604 readl(spi_imx->base + MXC_CSPIRXDATA);
605 858
606 spi_imx->intctrl(spi_imx, 0); 859 spi_imx->devtype_data.intctrl(spi_imx, 0);
607 860
608 ret = spi_bitbang_start(&spi_imx->bitbang); 861 ret = spi_bitbang_start(&spi_imx->bitbang);
609 if (ret) { 862 if (ret) {
@@ -668,6 +921,7 @@ static struct platform_driver spi_imx_driver = {
668 .name = DRIVER_NAME, 921 .name = DRIVER_NAME,
669 .owner = THIS_MODULE, 922 .owner = THIS_MODULE,
670 }, 923 },
924 .id_table = spi_imx_devtype,
671 .probe = spi_imx_probe, 925 .probe = spi_imx_probe,
672 .remove = __devexit_p(spi_imx_remove), 926 .remove = __devexit_p(spi_imx_remove),
673}; 927};
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-16 10:37:30 -0400