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path: root/drivers/spi/spi-s3c64xx.c
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Diffstat (limited to 'drivers/spi/spi-s3c64xx.c')
-rw-r--r--drivers/spi/spi-s3c64xx.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index c6ad4e1c3dc0..a2062b231a6b 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1480,40 +1480,40 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
1480 s3c64xx_spi_runtime_resume, NULL) 1480 s3c64xx_spi_runtime_resume, NULL)
1481}; 1481};
1482 1482
1483struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1483static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1484 .fifo_lvl_mask = { 0x7f }, 1484 .fifo_lvl_mask = { 0x7f },
1485 .rx_lvl_offset = 13, 1485 .rx_lvl_offset = 13,
1486 .tx_st_done = 21, 1486 .tx_st_done = 21,
1487 .high_speed = true, 1487 .high_speed = true,
1488}; 1488};
1489 1489
1490struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1490static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1491 .fifo_lvl_mask = { 0x7f, 0x7F }, 1491 .fifo_lvl_mask = { 0x7f, 0x7F },
1492 .rx_lvl_offset = 13, 1492 .rx_lvl_offset = 13,
1493 .tx_st_done = 21, 1493 .tx_st_done = 21,
1494}; 1494};
1495 1495
1496struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { 1496static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1497 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1497 .fifo_lvl_mask = { 0x1ff, 0x7F },
1498 .rx_lvl_offset = 15, 1498 .rx_lvl_offset = 15,
1499 .tx_st_done = 25, 1499 .tx_st_done = 25,
1500}; 1500};
1501 1501
1502struct s3c64xx_spi_port_config s5pc100_spi_port_config = { 1502static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1503 .fifo_lvl_mask = { 0x7f, 0x7F }, 1503 .fifo_lvl_mask = { 0x7f, 0x7F },
1504 .rx_lvl_offset = 13, 1504 .rx_lvl_offset = 13,
1505 .tx_st_done = 21, 1505 .tx_st_done = 21,
1506 .high_speed = true, 1506 .high_speed = true,
1507}; 1507};
1508 1508
1509struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1509static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1510 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1510 .fifo_lvl_mask = { 0x1ff, 0x7F },
1511 .rx_lvl_offset = 15, 1511 .rx_lvl_offset = 15,
1512 .tx_st_done = 25, 1512 .tx_st_done = 25,
1513 .high_speed = true, 1513 .high_speed = true,
1514}; 1514};
1515 1515
1516struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1516static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1517 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1517 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1518 .rx_lvl_offset = 15, 1518 .rx_lvl_offset = 15,
1519 .tx_st_done = 25, 1519 .tx_st_done = 25,