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path: root/drivers/spi/spi-dw-mid.c
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Diffstat (limited to 'drivers/spi/spi-dw-mid.c')
-rw-r--r--drivers/spi/spi-dw-mid.c29
1 files changed, 15 insertions, 14 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 1ca8f66ca2ea..46c6d58e1fda 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -113,8 +113,7 @@ static void dw_spi_dma_done(void *arg)
113 113
114static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) 114static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
115{ 115{
116 struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL; 116 struct dma_async_tx_descriptor *txdesc, *rxdesc;
117 struct dma_chan *txchan, *rxchan;
118 struct dma_slave_config txconf, rxconf; 117 struct dma_slave_config txconf, rxconf;
119 u16 dma_ctrl = 0; 118 u16 dma_ctrl = 0;
120 119
@@ -124,16 +123,14 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
124 dw_writew(dws, DW_SPI_DMARDLR, 0xf); 123 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
125 dw_writew(dws, DW_SPI_DMATDLR, 0x10); 124 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
126 if (dws->tx_dma) 125 if (dws->tx_dma)
127 dma_ctrl |= 0x2; 126 dma_ctrl |= SPI_DMA_TDMAE;
128 if (dws->rx_dma) 127 if (dws->rx_dma)
129 dma_ctrl |= 0x1; 128 dma_ctrl |= SPI_DMA_RDMAE;
130 dw_writew(dws, DW_SPI_DMACR, dma_ctrl); 129 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
131 spi_enable_chip(dws, 1); 130 spi_enable_chip(dws, 1);
132 } 131 }
133 132
134 dws->dma_chan_done = 0; 133 dws->dma_chan_done = 0;
135 txchan = dws->txchan;
136 rxchan = dws->rxchan;
137 134
138 /* 2. Prepare the TX dma transfer */ 135 /* 2. Prepare the TX dma transfer */
139 txconf.direction = DMA_MEM_TO_DEV; 136 txconf.direction = DMA_MEM_TO_DEV;
@@ -143,17 +140,17 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
143 txconf.dst_addr_width = dws->dma_width; 140 txconf.dst_addr_width = dws->dma_width;
144 txconf.device_fc = false; 141 txconf.device_fc = false;
145 142
146 dmaengine_slave_config(txchan, &txconf); 143 dmaengine_slave_config(dws->txchan, &txconf);
147 144
148 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl)); 145 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
149 dws->tx_sgl.dma_address = dws->tx_dma; 146 dws->tx_sgl.dma_address = dws->tx_dma;
150 dws->tx_sgl.length = dws->len; 147 dws->tx_sgl.length = dws->len;
151 148
152 txdesc = dmaengine_prep_slave_sg(txchan, 149 txdesc = dmaengine_prep_slave_sg(dws->txchan,
153 &dws->tx_sgl, 150 &dws->tx_sgl,
154 1, 151 1,
155 DMA_MEM_TO_DEV, 152 DMA_MEM_TO_DEV,
156 DMA_PREP_INTERRUPT); 153 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
157 txdesc->callback = dw_spi_dma_done; 154 txdesc->callback = dw_spi_dma_done;
158 txdesc->callback_param = dws; 155 txdesc->callback_param = dws;
159 156
@@ -165,23 +162,27 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
165 rxconf.src_addr_width = dws->dma_width; 162 rxconf.src_addr_width = dws->dma_width;
166 rxconf.device_fc = false; 163 rxconf.device_fc = false;
167 164
168 dmaengine_slave_config(txchan, &rxconf); 165 dmaengine_slave_config(dws->rxchan, &rxconf);
169 166
170 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl)); 167 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
171 dws->rx_sgl.dma_address = dws->rx_dma; 168 dws->rx_sgl.dma_address = dws->rx_dma;
172 dws->rx_sgl.length = dws->len; 169 dws->rx_sgl.length = dws->len;
173 170
174 rxdesc = dmaengine_prep_slave_sg(rxchan, 171 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
175 &dws->rx_sgl, 172 &dws->rx_sgl,
176 1, 173 1,
177 DMA_DEV_TO_MEM, 174 DMA_DEV_TO_MEM,
178 DMA_PREP_INTERRUPT); 175 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
179 rxdesc->callback = dw_spi_dma_done; 176 rxdesc->callback = dw_spi_dma_done;
180 rxdesc->callback_param = dws; 177 rxdesc->callback_param = dws;
181 178
182 /* rx must be started before tx due to spi instinct */ 179 /* rx must be started before tx due to spi instinct */
183 rxdesc->tx_submit(rxdesc); 180 dmaengine_submit(rxdesc);
184 txdesc->tx_submit(txdesc); 181 dma_async_issue_pending(dws->rxchan);
182
183 dmaengine_submit(txdesc);
184 dma_async_issue_pending(dws->txchan);
185
185 return 0; 186 return 0;
186} 187}
187 188