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-rw-r--r--drivers/sh/Kconfig1
-rw-r--r--drivers/sh/Makefile3
-rw-r--r--drivers/sh/clk/cpg.c333
-rw-r--r--drivers/sh/intc/Kconfig4
-rw-r--r--drivers/sh/intc/Makefile2
-rw-r--r--drivers/sh/intc/core.c11
-rw-r--r--drivers/sh/intc/dynamic.c57
-rw-r--r--drivers/sh/intc/internals.h5
-rw-r--r--drivers/sh/intc/irqdomain.c68
-rw-r--r--drivers/sh/intc/virq.c4
-rw-r--r--drivers/sh/pfc.c739
-rw-r--r--drivers/sh/pfc/Kconfig26
-rw-r--r--drivers/sh/pfc/Makefile3
-rw-r--r--drivers/sh/pfc/core.c572
-rw-r--r--drivers/sh/pfc/gpio.c239
-rw-r--r--drivers/sh/pfc/pinctrl.c526
16 files changed, 1599 insertions, 994 deletions
diff --git a/drivers/sh/Kconfig b/drivers/sh/Kconfig
index f168a6159961..d860ef743568 100644
--- a/drivers/sh/Kconfig
+++ b/drivers/sh/Kconfig
@@ -1,5 +1,6 @@
1menu "SuperH / SH-Mobile Driver Options" 1menu "SuperH / SH-Mobile Driver Options"
2 2
3source "drivers/sh/intc/Kconfig" 3source "drivers/sh/intc/Kconfig"
4source "drivers/sh/pfc/Kconfig"
4 5
5endmenu 6endmenu
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index 7139ad2f2086..e57895b1a425 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -5,6 +5,7 @@ obj-y := intc/
5 5
6obj-$(CONFIG_HAVE_CLK) += clk/ 6obj-$(CONFIG_HAVE_CLK) += clk/
7obj-$(CONFIG_MAPLE) += maple/ 7obj-$(CONFIG_MAPLE) += maple/
8obj-$(CONFIG_SH_PFC) += pfc/
8obj-$(CONFIG_SUPERHYWAY) += superhyway/ 9obj-$(CONFIG_SUPERHYWAY) += superhyway/
9obj-$(CONFIG_GENERIC_GPIO) += pfc.o 10
10obj-y += pm_runtime.o 11obj-y += pm_runtime.o
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index f0d015dd0fef..07e9fb4f8041 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -14,6 +14,8 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_clk.h> 15#include <linux/sh_clk.h>
16 16
17#define CPG_CKSTP_BIT BIT(8)
18
17static unsigned int sh_clk_read(struct clk *clk) 19static unsigned int sh_clk_read(struct clk *clk)
18{ 20{
19 if (clk->flags & CLK_ENABLE_REG_8BIT) 21 if (clk->flags & CLK_ENABLE_REG_8BIT)
@@ -66,71 +68,43 @@ int __init sh_clk_mstp_register(struct clk *clks, int nr)
66 return ret; 68 return ret;
67} 69}
68 70
69static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) 71/*
72 * Div/mult table lookup helpers
73 */
74static inline struct clk_div_table *clk_to_div_table(struct clk *clk)
70{ 75{
71 return clk_rate_table_round(clk, clk->freq_table, rate); 76 return clk->priv;
72} 77}
73 78
74static int sh_clk_div6_divisors[64] = { 79static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)
75 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 80{
76 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 81 return clk_to_div_table(clk)->div_mult_table;
77 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 82}
78 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
79};
80 83
81static struct clk_div_mult_table sh_clk_div6_table = { 84/*
82 .divisors = sh_clk_div6_divisors, 85 * Common div ops
83 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors), 86 */
84}; 87static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
88{
89 return clk_rate_table_round(clk, clk->freq_table, rate);
90}
85 91
86static unsigned long sh_clk_div6_recalc(struct clk *clk) 92static unsigned long sh_clk_div_recalc(struct clk *clk)
87{ 93{
88 struct clk_div_mult_table *table = &sh_clk_div6_table; 94 struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
89 unsigned int idx; 95 unsigned int idx;
90 96
91 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 97 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
92 table, NULL); 98 table, clk->arch_flags ? &clk->arch_flags : NULL);
93 99
94 idx = sh_clk_read(clk) & 0x003f; 100 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
95 101
96 return clk->freq_table[idx].frequency; 102 return clk->freq_table[idx].frequency;
97} 103}
98 104
99static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) 105static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
100{
101 struct clk_div_mult_table *table = &sh_clk_div6_table;
102 u32 value;
103 int ret, i;
104
105 if (!clk->parent_table || !clk->parent_num)
106 return -EINVAL;
107
108 /* Search the parent */
109 for (i = 0; i < clk->parent_num; i++)
110 if (clk->parent_table[i] == parent)
111 break;
112
113 if (i == clk->parent_num)
114 return -ENODEV;
115
116 ret = clk_reparent(clk, parent);
117 if (ret < 0)
118 return ret;
119
120 value = sh_clk_read(clk) &
121 ~(((1 << clk->src_width) - 1) << clk->src_shift);
122
123 sh_clk_write(value | (i << clk->src_shift), clk);
124
125 /* Rebuild the frequency table */
126 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
127 table, NULL);
128
129 return 0;
130}
131
132static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
133{ 106{
107 struct clk_div_table *dt = clk_to_div_table(clk);
134 unsigned long value; 108 unsigned long value;
135 int idx; 109 int idx;
136 110
@@ -139,51 +113,53 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
139 return idx; 113 return idx;
140 114
141 value = sh_clk_read(clk); 115 value = sh_clk_read(clk);
142 value &= ~0x3f; 116 value &= ~(clk->div_mask << clk->enable_bit);
143 value |= idx; 117 value |= (idx << clk->enable_bit);
144 sh_clk_write(value, clk); 118 sh_clk_write(value, clk);
119
120 /* XXX: Should use a post-change notifier */
121 if (dt->kick)
122 dt->kick(clk);
123
145 return 0; 124 return 0;
146} 125}
147 126
148static int sh_clk_div6_enable(struct clk *clk) 127static int sh_clk_div_enable(struct clk *clk)
149{ 128{
150 unsigned long value; 129 sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
151 int ret; 130 return 0;
152
153 ret = sh_clk_div6_set_rate(clk, clk->rate);
154 if (ret == 0) {
155 value = sh_clk_read(clk);
156 value &= ~0x100; /* clear stop bit to enable clock */
157 sh_clk_write(value, clk);
158 }
159 return ret;
160} 131}
161 132
162static void sh_clk_div6_disable(struct clk *clk) 133static void sh_clk_div_disable(struct clk *clk)
163{ 134{
164 unsigned long value; 135 unsigned int val;
165 136
166 value = sh_clk_read(clk); 137 val = sh_clk_read(clk);
167 value |= 0x100; /* stop clock */ 138 val |= CPG_CKSTP_BIT;
168 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ 139
169 sh_clk_write(value, clk); 140 /*
141 * div6 clocks require the divisor field to be non-zero or the
142 * above CKSTP toggle silently fails. Ensure that the divisor
143 * array is reset to its initial state on disable.
144 */
145 if (clk->flags & CLK_MASK_DIV_ON_DISABLE)
146 val |= clk->div_mask;
147
148 sh_clk_write(val, clk);
170} 149}
171 150
172static struct sh_clk_ops sh_clk_div6_clk_ops = { 151static struct sh_clk_ops sh_clk_div_clk_ops = {
173 .recalc = sh_clk_div6_recalc, 152 .recalc = sh_clk_div_recalc,
153 .set_rate = sh_clk_div_set_rate,
174 .round_rate = sh_clk_div_round_rate, 154 .round_rate = sh_clk_div_round_rate,
175 .set_rate = sh_clk_div6_set_rate,
176 .enable = sh_clk_div6_enable,
177 .disable = sh_clk_div6_disable,
178}; 155};
179 156
180static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { 157static struct sh_clk_ops sh_clk_div_enable_clk_ops = {
181 .recalc = sh_clk_div6_recalc, 158 .recalc = sh_clk_div_recalc,
159 .set_rate = sh_clk_div_set_rate,
182 .round_rate = sh_clk_div_round_rate, 160 .round_rate = sh_clk_div_round_rate,
183 .set_rate = sh_clk_div6_set_rate, 161 .enable = sh_clk_div_enable,
184 .enable = sh_clk_div6_enable, 162 .disable = sh_clk_div_disable,
185 .disable = sh_clk_div6_disable,
186 .set_parent = sh_clk_div6_set_parent,
187}; 163};
188 164
189static int __init sh_clk_init_parent(struct clk *clk) 165static int __init sh_clk_init_parent(struct clk *clk)
@@ -218,12 +194,12 @@ static int __init sh_clk_init_parent(struct clk *clk)
218 return 0; 194 return 0;
219} 195}
220 196
221static int __init sh_clk_div6_register_ops(struct clk *clks, int nr, 197static int __init sh_clk_div_register_ops(struct clk *clks, int nr,
222 struct sh_clk_ops *ops) 198 struct clk_div_table *table, struct sh_clk_ops *ops)
223{ 199{
224 struct clk *clkp; 200 struct clk *clkp;
225 void *freq_table; 201 void *freq_table;
226 int nr_divs = sh_clk_div6_table.nr_divisors; 202 int nr_divs = table->div_mult_table->nr_divisors;
227 int freq_table_size = sizeof(struct cpufreq_frequency_table); 203 int freq_table_size = sizeof(struct cpufreq_frequency_table);
228 int ret = 0; 204 int ret = 0;
229 int k; 205 int k;
@@ -231,7 +207,7 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
231 freq_table_size *= (nr_divs + 1); 207 freq_table_size *= (nr_divs + 1);
232 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL); 208 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
233 if (!freq_table) { 209 if (!freq_table) {
234 pr_err("sh_clk_div6_register: unable to alloc memory\n"); 210 pr_err("%s: unable to alloc memory\n", __func__);
235 return -ENOMEM; 211 return -ENOMEM;
236 } 212 }
237 213
@@ -239,47 +215,98 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
239 clkp = clks + k; 215 clkp = clks + k;
240 216
241 clkp->ops = ops; 217 clkp->ops = ops;
218 clkp->priv = table;
219
242 clkp->freq_table = freq_table + (k * freq_table_size); 220 clkp->freq_table = freq_table + (k * freq_table_size);
243 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; 221 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
244 ret = clk_register(clkp);
245 if (ret < 0)
246 break;
247 222
248 ret = sh_clk_init_parent(clkp); 223 ret = clk_register(clkp);
224 if (ret == 0)
225 ret = sh_clk_init_parent(clkp);
249 } 226 }
250 227
251 return ret; 228 return ret;
252} 229}
253 230
254int __init sh_clk_div6_register(struct clk *clks, int nr) 231/*
255{ 232 * div6 support
256 return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops); 233 */
257} 234static int sh_clk_div6_divisors[64] = {
235 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
236 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
237 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
238 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
239};
258 240
259int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) 241static struct clk_div_mult_table div6_div_mult_table = {
260{ 242 .divisors = sh_clk_div6_divisors,
261 return sh_clk_div6_register_ops(clks, nr, 243 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
262 &sh_clk_div6_reparent_clk_ops); 244};
263}
264 245
265static unsigned long sh_clk_div4_recalc(struct clk *clk) 246static struct clk_div_table sh_clk_div6_table = {
247 .div_mult_table = &div6_div_mult_table,
248};
249
250static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
266{ 251{
267 struct clk_div4_table *d4t = clk->priv; 252 struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
268 struct clk_div_mult_table *table = d4t->div_mult_table; 253 u32 value;
269 unsigned int idx; 254 int ret, i;
270 255
256 if (!clk->parent_table || !clk->parent_num)
257 return -EINVAL;
258
259 /* Search the parent */
260 for (i = 0; i < clk->parent_num; i++)
261 if (clk->parent_table[i] == parent)
262 break;
263
264 if (i == clk->parent_num)
265 return -ENODEV;
266
267 ret = clk_reparent(clk, parent);
268 if (ret < 0)
269 return ret;
270
271 value = sh_clk_read(clk) &
272 ~(((1 << clk->src_width) - 1) << clk->src_shift);
273
274 sh_clk_write(value | (i << clk->src_shift), clk);
275
276 /* Rebuild the frequency table */
271 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 277 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
272 table, &clk->arch_flags); 278 table, NULL);
273 279
274 idx = (sh_clk_read(clk) >> clk->enable_bit) & 0x000f; 280 return 0;
281}
275 282
276 return clk->freq_table[idx].frequency; 283static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
284 .recalc = sh_clk_div_recalc,
285 .round_rate = sh_clk_div_round_rate,
286 .set_rate = sh_clk_div_set_rate,
287 .enable = sh_clk_div_enable,
288 .disable = sh_clk_div_disable,
289 .set_parent = sh_clk_div6_set_parent,
290};
291
292int __init sh_clk_div6_register(struct clk *clks, int nr)
293{
294 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
295 &sh_clk_div_enable_clk_ops);
296}
297
298int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
299{
300 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
301 &sh_clk_div6_reparent_clk_ops);
277} 302}
278 303
304/*
305 * div4 support
306 */
279static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) 307static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
280{ 308{
281 struct clk_div4_table *d4t = clk->priv; 309 struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
282 struct clk_div_mult_table *table = d4t->div_mult_table;
283 u32 value; 310 u32 value;
284 int ret; 311 int ret;
285 312
@@ -306,107 +333,31 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
306 return 0; 333 return 0;
307} 334}
308 335
309static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
310{
311 struct clk_div4_table *d4t = clk->priv;
312 unsigned long value;
313 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
314 if (idx < 0)
315 return idx;
316
317 value = sh_clk_read(clk);
318 value &= ~(0xf << clk->enable_bit);
319 value |= (idx << clk->enable_bit);
320 sh_clk_write(value, clk);
321
322 if (d4t->kick)
323 d4t->kick(clk);
324
325 return 0;
326}
327
328static int sh_clk_div4_enable(struct clk *clk)
329{
330 sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk);
331 return 0;
332}
333
334static void sh_clk_div4_disable(struct clk *clk)
335{
336 sh_clk_write(sh_clk_read(clk) | (1 << 8), clk);
337}
338
339static struct sh_clk_ops sh_clk_div4_clk_ops = {
340 .recalc = sh_clk_div4_recalc,
341 .set_rate = sh_clk_div4_set_rate,
342 .round_rate = sh_clk_div_round_rate,
343};
344
345static struct sh_clk_ops sh_clk_div4_enable_clk_ops = {
346 .recalc = sh_clk_div4_recalc,
347 .set_rate = sh_clk_div4_set_rate,
348 .round_rate = sh_clk_div_round_rate,
349 .enable = sh_clk_div4_enable,
350 .disable = sh_clk_div4_disable,
351};
352
353static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { 336static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = {
354 .recalc = sh_clk_div4_recalc, 337 .recalc = sh_clk_div_recalc,
355 .set_rate = sh_clk_div4_set_rate, 338 .set_rate = sh_clk_div_set_rate,
356 .round_rate = sh_clk_div_round_rate, 339 .round_rate = sh_clk_div_round_rate,
357 .enable = sh_clk_div4_enable, 340 .enable = sh_clk_div_enable,
358 .disable = sh_clk_div4_disable, 341 .disable = sh_clk_div_disable,
359 .set_parent = sh_clk_div4_set_parent, 342 .set_parent = sh_clk_div4_set_parent,
360}; 343};
361 344
362static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
363 struct clk_div4_table *table, struct sh_clk_ops *ops)
364{
365 struct clk *clkp;
366 void *freq_table;
367 int nr_divs = table->div_mult_table->nr_divisors;
368 int freq_table_size = sizeof(struct cpufreq_frequency_table);
369 int ret = 0;
370 int k;
371
372 freq_table_size *= (nr_divs + 1);
373 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
374 if (!freq_table) {
375 pr_err("sh_clk_div4_register: unable to alloc memory\n");
376 return -ENOMEM;
377 }
378
379 for (k = 0; !ret && (k < nr); k++) {
380 clkp = clks + k;
381
382 clkp->ops = ops;
383 clkp->priv = table;
384
385 clkp->freq_table = freq_table + (k * freq_table_size);
386 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
387
388 ret = clk_register(clkp);
389 }
390
391 return ret;
392}
393
394int __init sh_clk_div4_register(struct clk *clks, int nr, 345int __init sh_clk_div4_register(struct clk *clks, int nr,
395 struct clk_div4_table *table) 346 struct clk_div4_table *table)
396{ 347{
397 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops); 348 return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops);
398} 349}
399 350
400int __init sh_clk_div4_enable_register(struct clk *clks, int nr, 351int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
401 struct clk_div4_table *table) 352 struct clk_div4_table *table)
402{ 353{
403 return sh_clk_div4_register_ops(clks, nr, table, 354 return sh_clk_div_register_ops(clks, nr, table,
404 &sh_clk_div4_enable_clk_ops); 355 &sh_clk_div_enable_clk_ops);
405} 356}
406 357
407int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, 358int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
408 struct clk_div4_table *table) 359 struct clk_div4_table *table)
409{ 360{
410 return sh_clk_div4_register_ops(clks, nr, table, 361 return sh_clk_div_register_ops(clks, nr, table,
411 &sh_clk_div4_reparent_clk_ops); 362 &sh_clk_div4_reparent_clk_ops);
412} 363}
diff --git a/drivers/sh/intc/Kconfig b/drivers/sh/intc/Kconfig
index c88cbccc62b0..a305731742a9 100644
--- a/drivers/sh/intc/Kconfig
+++ b/drivers/sh/intc/Kconfig
@@ -1,3 +1,7 @@
1config SH_INTC
2 def_bool y
3 select IRQ_DOMAIN
4
1comment "Interrupt controller options" 5comment "Interrupt controller options"
2 6
3config INTC_USERIMASK 7config INTC_USERIMASK
diff --git a/drivers/sh/intc/Makefile b/drivers/sh/intc/Makefile
index bb5df868d77a..54ec2a0643df 100644
--- a/drivers/sh/intc/Makefile
+++ b/drivers/sh/intc/Makefile
@@ -1,4 +1,4 @@
1obj-y := access.o chip.o core.o dynamic.o handle.o virq.o 1obj-y := access.o chip.o core.o handle.o irqdomain.o virq.o
2 2
3obj-$(CONFIG_INTC_BALANCING) += balancing.o 3obj-$(CONFIG_INTC_BALANCING) += balancing.o
4obj-$(CONFIG_INTC_USERIMASK) += userimask.o 4obj-$(CONFIG_INTC_USERIMASK) += userimask.o
diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c
index 7e562ccb6997..2374468615ed 100644
--- a/drivers/sh/intc/core.c
+++ b/drivers/sh/intc/core.c
@@ -25,6 +25,7 @@
25#include <linux/stat.h> 25#include <linux/stat.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/sh_intc.h> 27#include <linux/sh_intc.h>
28#include <linux/irqdomain.h>
28#include <linux/device.h> 29#include <linux/device.h>
29#include <linux/syscore_ops.h> 30#include <linux/syscore_ops.h>
30#include <linux/list.h> 31#include <linux/list.h>
@@ -310,6 +311,8 @@ int __init register_intc_controller(struct intc_desc *desc)
310 311
311 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 312 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
312 313
314 intc_irq_domain_init(d, hw);
315
313 /* register the vectors one by one */ 316 /* register the vectors one by one */
314 for (i = 0; i < hw->nr_vectors; i++) { 317 for (i = 0; i < hw->nr_vectors; i++) {
315 struct intc_vect *vect = hw->vectors + i; 318 struct intc_vect *vect = hw->vectors + i;
@@ -319,8 +322,8 @@ int __init register_intc_controller(struct intc_desc *desc)
319 if (!vect->enum_id) 322 if (!vect->enum_id)
320 continue; 323 continue;
321 324
322 res = irq_alloc_desc_at(irq, numa_node_id()); 325 res = irq_create_identity_mapping(d->domain, irq);
323 if (res != irq && res != -EEXIST) { 326 if (unlikely(res)) {
324 pr_err("can't get irq_desc for %d\n", irq); 327 pr_err("can't get irq_desc for %d\n", irq);
325 continue; 328 continue;
326 } 329 }
@@ -340,8 +343,8 @@ int __init register_intc_controller(struct intc_desc *desc)
340 * IRQ support, each vector still needs to have 343 * IRQ support, each vector still needs to have
341 * its own backing irq_desc. 344 * its own backing irq_desc.
342 */ 345 */
343 res = irq_alloc_desc_at(irq2, numa_node_id()); 346 res = irq_create_identity_mapping(d->domain, irq2);
344 if (res != irq2 && res != -EEXIST) { 347 if (unlikely(res)) {
345 pr_err("can't get irq_desc for %d\n", irq2); 348 pr_err("can't get irq_desc for %d\n", irq2);
346 continue; 349 continue;
347 } 350 }
diff --git a/drivers/sh/intc/dynamic.c b/drivers/sh/intc/dynamic.c
deleted file mode 100644
index 14eb01ef5d72..000000000000
--- a/drivers/sh/intc/dynamic.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Dynamic IRQ management
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * Modelled after arch/x86/kernel/apic/io_apic.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#define pr_fmt(fmt) "intc: " fmt
13
14#include <linux/irq.h>
15#include <linux/bitmap.h>
16#include <linux/spinlock.h>
17#include <linux/module.h>
18#include "internals.h" /* only for activate_irq() damage.. */
19
20/*
21 * The IRQ bitmap provides a global map of bound IRQ vectors for a
22 * given platform. Allocation of IRQs are either static through the CPU
23 * vector map, or dynamic in the case of board mux vectors or MSI.
24 *
25 * As this is a central point for all IRQ controllers on the system,
26 * each of the available sources are mapped out here. This combined with
27 * sparseirq makes it quite trivial to keep the vector map tightly packed
28 * when dynamically creating IRQs, as well as tying in to otherwise
29 * unused irq_desc positions in the sparse array.
30 */
31
32/*
33 * Dynamic IRQ allocation and deallocation
34 */
35unsigned int create_irq_nr(unsigned int irq_want, int node)
36{
37 int irq = irq_alloc_desc_at(irq_want, node);
38 if (irq < 0)
39 return 0;
40
41 activate_irq(irq);
42 return irq;
43}
44
45int create_irq(void)
46{
47 int irq = irq_alloc_desc(numa_node_id());
48 if (irq >= 0)
49 activate_irq(irq);
50
51 return irq;
52}
53
54void destroy_irq(unsigned int irq)
55{
56 irq_free_desc(irq);
57}
diff --git a/drivers/sh/intc/internals.h b/drivers/sh/intc/internals.h
index f034a979a16f..7dff08e2a071 100644
--- a/drivers/sh/intc/internals.h
+++ b/drivers/sh/intc/internals.h
@@ -1,5 +1,6 @@
1#include <linux/sh_intc.h> 1#include <linux/sh_intc.h>
2#include <linux/irq.h> 2#include <linux/irq.h>
3#include <linux/irqdomain.h>
3#include <linux/list.h> 4#include <linux/list.h>
4#include <linux/kernel.h> 5#include <linux/kernel.h>
5#include <linux/types.h> 6#include <linux/types.h>
@@ -66,6 +67,7 @@ struct intc_desc_int {
66 unsigned int nr_sense; 67 unsigned int nr_sense;
67 struct intc_window *window; 68 struct intc_window *window;
68 unsigned int nr_windows; 69 unsigned int nr_windows;
70 struct irq_domain *domain;
69 struct irq_chip chip; 71 struct irq_chip chip;
70 bool skip_suspend; 72 bool skip_suspend;
71}; 73};
@@ -187,6 +189,9 @@ unsigned long intc_get_ack_handle(unsigned int irq);
187void intc_enable_disable_enum(struct intc_desc *desc, struct intc_desc_int *d, 189void intc_enable_disable_enum(struct intc_desc *desc, struct intc_desc_int *d,
188 intc_enum enum_id, int enable); 190 intc_enum enum_id, int enable);
189 191
192/* irqdomain.c */
193void intc_irq_domain_init(struct intc_desc_int *d, struct intc_hw_desc *hw);
194
190/* virq.c */ 195/* virq.c */
191void intc_subgroup_init(struct intc_desc *desc, struct intc_desc_int *d); 196void intc_subgroup_init(struct intc_desc *desc, struct intc_desc_int *d);
192void intc_irq_xlate_set(unsigned int irq, intc_enum id, struct intc_desc_int *d); 197void intc_irq_xlate_set(unsigned int irq, intc_enum id, struct intc_desc_int *d);
diff --git a/drivers/sh/intc/irqdomain.c b/drivers/sh/intc/irqdomain.c
new file mode 100644
index 000000000000..3968f1c3c5c3
--- /dev/null
+++ b/drivers/sh/intc/irqdomain.c
@@ -0,0 +1,68 @@
1/*
2 * IRQ domain support for SH INTC subsystem
3 *
4 * Copyright (C) 2012 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#define pr_fmt(fmt) "intc: " fmt
11
12#include <linux/irqdomain.h>
13#include <linux/sh_intc.h>
14#include <linux/export.h>
15#include "internals.h"
16
17/**
18 * intc_irq_domain_evt_xlate() - Generic xlate for vectored IRQs.
19 *
20 * This takes care of exception vector to hwirq translation through
21 * by way of evt2irq() translation.
22 *
23 * Note: For platforms that use a flat vector space without INTEVT this
24 * basically just mimics irq_domain_xlate_onecell() by way of a nopped
25 * out evt2irq() implementation.
26 */
27static int intc_evt_xlate(struct irq_domain *d, struct device_node *ctrlr,
28 const u32 *intspec, unsigned int intsize,
29 unsigned long *out_hwirq, unsigned int *out_type)
30{
31 if (WARN_ON(intsize < 1))
32 return -EINVAL;
33
34 *out_hwirq = evt2irq(intspec[0]);
35 *out_type = IRQ_TYPE_NONE;
36
37 return 0;
38}
39
40static const struct irq_domain_ops intc_evt_ops = {
41 .xlate = intc_evt_xlate,
42};
43
44void __init intc_irq_domain_init(struct intc_desc_int *d,
45 struct intc_hw_desc *hw)
46{
47 unsigned int irq_base, irq_end;
48
49 /*
50 * Quick linear revmap check
51 */
52 irq_base = evt2irq(hw->vectors[0].vect);
53 irq_end = evt2irq(hw->vectors[hw->nr_vectors - 1].vect);
54
55 /*
56 * Linear domains have a hard-wired assertion that IRQs start at
57 * 0 in order to make some performance optimizations. Lamely
58 * restrict the linear case to these conditions here, taking the
59 * tree penalty for linear cases with non-zero hwirq bases.
60 */
61 if (irq_base == 0 && irq_end == (irq_base + hw->nr_vectors - 1))
62 d->domain = irq_domain_add_linear(NULL, hw->nr_vectors,
63 &intc_evt_ops, NULL);
64 else
65 d->domain = irq_domain_add_tree(NULL, &intc_evt_ops, NULL);
66
67 BUG_ON(!d->domain);
68}
diff --git a/drivers/sh/intc/virq.c b/drivers/sh/intc/virq.c
index 93cec21e788b..f30ac9354ff2 100644
--- a/drivers/sh/intc/virq.c
+++ b/drivers/sh/intc/virq.c
@@ -219,12 +219,14 @@ restart:
219 if (radix_tree_deref_retry(entry)) 219 if (radix_tree_deref_retry(entry))
220 goto restart; 220 goto restart;
221 221
222 irq = create_irq(); 222 irq = irq_alloc_desc(numa_node_id());
223 if (unlikely(irq < 0)) { 223 if (unlikely(irq < 0)) {
224 pr_err("no more free IRQs, bailing..\n"); 224 pr_err("no more free IRQs, bailing..\n");
225 break; 225 break;
226 } 226 }
227 227
228 activate_irq(irq);
229
228 pr_info("Setting up a chained VIRQ from %d -> %d\n", 230 pr_info("Setting up a chained VIRQ from %d -> %d\n",
229 irq, entry->pirq); 231 irq, entry->pirq);
230 232
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
deleted file mode 100644
index 522c6c46d1be..000000000000
--- a/drivers/sh/pfc.c
+++ /dev/null
@@ -1,739 +0,0 @@
1/*
2 * Pinmuxed GPIO support for SuperH.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/module.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/bitops.h>
21#include <linux/gpio.h>
22#include <linux/slab.h>
23#include <linux/ioport.h>
24
25static void pfc_iounmap(struct pinmux_info *pip)
26{
27 int k;
28
29 for (k = 0; k < pip->num_resources; k++)
30 if (pip->window[k].virt)
31 iounmap(pip->window[k].virt);
32
33 kfree(pip->window);
34 pip->window = NULL;
35}
36
37static int pfc_ioremap(struct pinmux_info *pip)
38{
39 struct resource *res;
40 int k;
41
42 if (!pip->num_resources)
43 return 0;
44
45 pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
46 GFP_NOWAIT);
47 if (!pip->window)
48 goto err1;
49
50 for (k = 0; k < pip->num_resources; k++) {
51 res = pip->resource + k;
52 WARN_ON(resource_type(res) != IORESOURCE_MEM);
53 pip->window[k].phys = res->start;
54 pip->window[k].size = resource_size(res);
55 pip->window[k].virt = ioremap_nocache(res->start,
56 resource_size(res));
57 if (!pip->window[k].virt)
58 goto err2;
59 }
60
61 return 0;
62
63err2:
64 pfc_iounmap(pip);
65err1:
66 return -1;
67}
68
69static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
70 unsigned long address)
71{
72 struct pfc_window *window;
73 int k;
74
75 /* scan through physical windows and convert address */
76 for (k = 0; k < pip->num_resources; k++) {
77 window = pip->window + k;
78
79 if (address < window->phys)
80 continue;
81
82 if (address >= (window->phys + window->size))
83 continue;
84
85 return window->virt + (address - window->phys);
86 }
87
88 /* no windows defined, register must be 1:1 mapped virt:phys */
89 return (void __iomem *)address;
90}
91
92static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
93{
94 if (enum_id < r->begin)
95 return 0;
96
97 if (enum_id > r->end)
98 return 0;
99
100 return 1;
101}
102
103static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
104 unsigned long reg_width)
105{
106 switch (reg_width) {
107 case 8:
108 return ioread8(mapped_reg);
109 case 16:
110 return ioread16(mapped_reg);
111 case 32:
112 return ioread32(mapped_reg);
113 }
114
115 BUG();
116 return 0;
117}
118
119static void gpio_write_raw_reg(void __iomem *mapped_reg,
120 unsigned long reg_width,
121 unsigned long data)
122{
123 switch (reg_width) {
124 case 8:
125 iowrite8(data, mapped_reg);
126 return;
127 case 16:
128 iowrite16(data, mapped_reg);
129 return;
130 case 32:
131 iowrite32(data, mapped_reg);
132 return;
133 }
134
135 BUG();
136}
137
138static int gpio_read_bit(struct pinmux_data_reg *dr,
139 unsigned long in_pos)
140{
141 unsigned long pos;
142
143 pos = dr->reg_width - (in_pos + 1);
144
145 pr_debug("read_bit: addr = %lx, pos = %ld, "
146 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
147
148 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
149}
150
151static void gpio_write_bit(struct pinmux_data_reg *dr,
152 unsigned long in_pos, unsigned long value)
153{
154 unsigned long pos;
155
156 pos = dr->reg_width - (in_pos + 1);
157
158 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
159 "r_width = %ld\n",
160 dr->reg, !!value, pos, dr->reg_width);
161
162 if (value)
163 set_bit(pos, &dr->reg_shadow);
164 else
165 clear_bit(pos, &dr->reg_shadow);
166
167 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
168}
169
170static void config_reg_helper(struct pinmux_info *gpioc,
171 struct pinmux_cfg_reg *crp,
172 unsigned long in_pos,
173 void __iomem **mapped_regp,
174 unsigned long *maskp,
175 unsigned long *posp)
176{
177 int k;
178
179 *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
180
181 if (crp->field_width) {
182 *maskp = (1 << crp->field_width) - 1;
183 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
184 } else {
185 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
186 *posp = crp->reg_width;
187 for (k = 0; k <= in_pos; k++)
188 *posp -= crp->var_field_width[k];
189 }
190}
191
192static int read_config_reg(struct pinmux_info *gpioc,
193 struct pinmux_cfg_reg *crp,
194 unsigned long field)
195{
196 void __iomem *mapped_reg;
197 unsigned long mask, pos;
198
199 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
200
201 pr_debug("read_reg: addr = %lx, field = %ld, "
202 "r_width = %ld, f_width = %ld\n",
203 crp->reg, field, crp->reg_width, crp->field_width);
204
205 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
206}
207
208static void write_config_reg(struct pinmux_info *gpioc,
209 struct pinmux_cfg_reg *crp,
210 unsigned long field, unsigned long value)
211{
212 void __iomem *mapped_reg;
213 unsigned long mask, pos, data;
214
215 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
216
217 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
218 "r_width = %ld, f_width = %ld\n",
219 crp->reg, value, field, crp->reg_width, crp->field_width);
220
221 mask = ~(mask << pos);
222 value = value << pos;
223
224 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
225 data &= mask;
226 data |= value;
227
228 if (gpioc->unlock_reg)
229 gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
230 32, ~data);
231
232 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
233}
234
235static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
236{
237 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
238 struct pinmux_data_reg *data_reg;
239 int k, n;
240
241 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
242 return -1;
243
244 k = 0;
245 while (1) {
246 data_reg = gpioc->data_regs + k;
247
248 if (!data_reg->reg_width)
249 break;
250
251 data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
252
253 for (n = 0; n < data_reg->reg_width; n++) {
254 if (data_reg->enum_ids[n] == gpiop->enum_id) {
255 gpiop->flags &= ~PINMUX_FLAG_DREG;
256 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
257 gpiop->flags &= ~PINMUX_FLAG_DBIT;
258 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
259 return 0;
260 }
261 }
262 k++;
263 }
264
265 BUG();
266
267 return -1;
268}
269
270static void setup_data_regs(struct pinmux_info *gpioc)
271{
272 struct pinmux_data_reg *drp;
273 int k;
274
275 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
276 setup_data_reg(gpioc, k);
277
278 k = 0;
279 while (1) {
280 drp = gpioc->data_regs + k;
281
282 if (!drp->reg_width)
283 break;
284
285 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
286 drp->reg_width);
287 k++;
288 }
289}
290
291static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
292 struct pinmux_data_reg **drp, int *bitp)
293{
294 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
295 int k, n;
296
297 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
298 return -1;
299
300 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
301 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
302 *drp = gpioc->data_regs + k;
303 *bitp = n;
304 return 0;
305}
306
307static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
308 struct pinmux_cfg_reg **crp,
309 int *fieldp, int *valuep,
310 unsigned long **cntp)
311{
312 struct pinmux_cfg_reg *config_reg;
313 unsigned long r_width, f_width, curr_width, ncomb;
314 int k, m, n, pos, bit_pos;
315
316 k = 0;
317 while (1) {
318 config_reg = gpioc->cfg_regs + k;
319
320 r_width = config_reg->reg_width;
321 f_width = config_reg->field_width;
322
323 if (!r_width)
324 break;
325
326 pos = 0;
327 m = 0;
328 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
329 if (f_width)
330 curr_width = f_width;
331 else
332 curr_width = config_reg->var_field_width[m];
333
334 ncomb = 1 << curr_width;
335 for (n = 0; n < ncomb; n++) {
336 if (config_reg->enum_ids[pos + n] == enum_id) {
337 *crp = config_reg;
338 *fieldp = m;
339 *valuep = n;
340 *cntp = &config_reg->cnt[m];
341 return 0;
342 }
343 }
344 pos += ncomb;
345 m++;
346 }
347 k++;
348 }
349
350 return -1;
351}
352
353static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
354 int pos, pinmux_enum_t *enum_idp)
355{
356 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
357 pinmux_enum_t *data = gpioc->gpio_data;
358 int k;
359
360 if (!enum_in_range(enum_id, &gpioc->data)) {
361 if (!enum_in_range(enum_id, &gpioc->mark)) {
362 pr_err("non data/mark enum_id for gpio %d\n", gpio);
363 return -1;
364 }
365 }
366
367 if (pos) {
368 *enum_idp = data[pos + 1];
369 return pos + 1;
370 }
371
372 for (k = 0; k < gpioc->gpio_data_size; k++) {
373 if (data[k] == enum_id) {
374 *enum_idp = data[k + 1];
375 return k + 1;
376 }
377 }
378
379 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
380 return -1;
381}
382
383enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
384
385static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
386 int pinmux_type, int cfg_mode)
387{
388 struct pinmux_cfg_reg *cr = NULL;
389 pinmux_enum_t enum_id;
390 struct pinmux_range *range;
391 int in_range, pos, field, value;
392 unsigned long *cntp;
393
394 switch (pinmux_type) {
395
396 case PINMUX_TYPE_FUNCTION:
397 range = NULL;
398 break;
399
400 case PINMUX_TYPE_OUTPUT:
401 range = &gpioc->output;
402 break;
403
404 case PINMUX_TYPE_INPUT:
405 range = &gpioc->input;
406 break;
407
408 case PINMUX_TYPE_INPUT_PULLUP:
409 range = &gpioc->input_pu;
410 break;
411
412 case PINMUX_TYPE_INPUT_PULLDOWN:
413 range = &gpioc->input_pd;
414 break;
415
416 default:
417 goto out_err;
418 }
419
420 pos = 0;
421 enum_id = 0;
422 field = 0;
423 value = 0;
424 while (1) {
425 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
426 if (pos <= 0)
427 goto out_err;
428
429 if (!enum_id)
430 break;
431
432 /* first check if this is a function enum */
433 in_range = enum_in_range(enum_id, &gpioc->function);
434 if (!in_range) {
435 /* not a function enum */
436 if (range) {
437 /*
438 * other range exists, so this pin is
439 * a regular GPIO pin that now is being
440 * bound to a specific direction.
441 *
442 * for this case we only allow function enums
443 * and the enums that match the other range.
444 */
445 in_range = enum_in_range(enum_id, range);
446
447 /*
448 * special case pass through for fixed
449 * input-only or output-only pins without
450 * function enum register association.
451 */
452 if (in_range && enum_id == range->force)
453 continue;
454 } else {
455 /*
456 * no other range exists, so this pin
457 * must then be of the function type.
458 *
459 * allow function type pins to select
460 * any combination of function/in/out
461 * in their MARK lists.
462 */
463 in_range = 1;
464 }
465 }
466
467 if (!in_range)
468 continue;
469
470 if (get_config_reg(gpioc, enum_id, &cr,
471 &field, &value, &cntp) != 0)
472 goto out_err;
473
474 switch (cfg_mode) {
475 case GPIO_CFG_DRYRUN:
476 if (!*cntp ||
477 (read_config_reg(gpioc, cr, field) != value))
478 continue;
479 break;
480
481 case GPIO_CFG_REQ:
482 write_config_reg(gpioc, cr, field, value);
483 *cntp = *cntp + 1;
484 break;
485
486 case GPIO_CFG_FREE:
487 *cntp = *cntp - 1;
488 break;
489 }
490 }
491
492 return 0;
493 out_err:
494 return -1;
495}
496
497static DEFINE_SPINLOCK(gpio_lock);
498
499static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
500{
501 return container_of(chip, struct pinmux_info, chip);
502}
503
504static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
505{
506 struct pinmux_info *gpioc = chip_to_pinmux(chip);
507 struct pinmux_data_reg *dummy;
508 unsigned long flags;
509 int i, ret, pinmux_type;
510
511 ret = -EINVAL;
512
513 if (!gpioc)
514 goto err_out;
515
516 spin_lock_irqsave(&gpio_lock, flags);
517
518 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
519 goto err_unlock;
520
521 /* setup pin function here if no data is associated with pin */
522
523 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
524 pinmux_type = PINMUX_TYPE_FUNCTION;
525 else
526 pinmux_type = PINMUX_TYPE_GPIO;
527
528 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
529 if (pinmux_config_gpio(gpioc, offset,
530 pinmux_type,
531 GPIO_CFG_DRYRUN) != 0)
532 goto err_unlock;
533
534 if (pinmux_config_gpio(gpioc, offset,
535 pinmux_type,
536 GPIO_CFG_REQ) != 0)
537 BUG();
538 }
539
540 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
541 gpioc->gpios[offset].flags |= pinmux_type;
542
543 ret = 0;
544 err_unlock:
545 spin_unlock_irqrestore(&gpio_lock, flags);
546 err_out:
547 return ret;
548}
549
550static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
551{
552 struct pinmux_info *gpioc = chip_to_pinmux(chip);
553 unsigned long flags;
554 int pinmux_type;
555
556 if (!gpioc)
557 return;
558
559 spin_lock_irqsave(&gpio_lock, flags);
560
561 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
562 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
563 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
564 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
565
566 spin_unlock_irqrestore(&gpio_lock, flags);
567}
568
569static int pinmux_direction(struct pinmux_info *gpioc,
570 unsigned gpio, int new_pinmux_type)
571{
572 int pinmux_type;
573 int ret = -EINVAL;
574
575 if (!gpioc)
576 goto err_out;
577
578 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
579
580 switch (pinmux_type) {
581 case PINMUX_TYPE_GPIO:
582 break;
583 case PINMUX_TYPE_OUTPUT:
584 case PINMUX_TYPE_INPUT:
585 case PINMUX_TYPE_INPUT_PULLUP:
586 case PINMUX_TYPE_INPUT_PULLDOWN:
587 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
588 break;
589 default:
590 goto err_out;
591 }
592
593 if (pinmux_config_gpio(gpioc, gpio,
594 new_pinmux_type,
595 GPIO_CFG_DRYRUN) != 0)
596 goto err_out;
597
598 if (pinmux_config_gpio(gpioc, gpio,
599 new_pinmux_type,
600 GPIO_CFG_REQ) != 0)
601 BUG();
602
603 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
604 gpioc->gpios[gpio].flags |= new_pinmux_type;
605
606 ret = 0;
607 err_out:
608 return ret;
609}
610
611static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
612{
613 struct pinmux_info *gpioc = chip_to_pinmux(chip);
614 unsigned long flags;
615 int ret;
616
617 spin_lock_irqsave(&gpio_lock, flags);
618 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
619 spin_unlock_irqrestore(&gpio_lock, flags);
620
621 return ret;
622}
623
624static void sh_gpio_set_value(struct pinmux_info *gpioc,
625 unsigned gpio, int value)
626{
627 struct pinmux_data_reg *dr = NULL;
628 int bit = 0;
629
630 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
631 BUG();
632 else
633 gpio_write_bit(dr, bit, value);
634}
635
636static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
637 int value)
638{
639 struct pinmux_info *gpioc = chip_to_pinmux(chip);
640 unsigned long flags;
641 int ret;
642
643 sh_gpio_set_value(gpioc, offset, value);
644 spin_lock_irqsave(&gpio_lock, flags);
645 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
646 spin_unlock_irqrestore(&gpio_lock, flags);
647
648 return ret;
649}
650
651static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
652{
653 struct pinmux_data_reg *dr = NULL;
654 int bit = 0;
655
656 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
657 return -EINVAL;
658
659 return gpio_read_bit(dr, bit);
660}
661
662static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
663{
664 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
665}
666
667static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
668{
669 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
670}
671
672static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
673{
674 struct pinmux_info *gpioc = chip_to_pinmux(chip);
675 pinmux_enum_t enum_id;
676 pinmux_enum_t *enum_ids;
677 int i, k, pos;
678
679 pos = 0;
680 enum_id = 0;
681 while (1) {
682 pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
683 if (pos <= 0 || !enum_id)
684 break;
685
686 for (i = 0; i < gpioc->gpio_irq_size; i++) {
687 enum_ids = gpioc->gpio_irq[i].enum_ids;
688 for (k = 0; enum_ids[k]; k++) {
689 if (enum_ids[k] == enum_id)
690 return gpioc->gpio_irq[i].irq;
691 }
692 }
693 }
694
695 return -ENOSYS;
696}
697
698int register_pinmux(struct pinmux_info *pip)
699{
700 struct gpio_chip *chip = &pip->chip;
701 int ret;
702
703 pr_info("%s handling gpio %d -> %d\n",
704 pip->name, pip->first_gpio, pip->last_gpio);
705
706 ret = pfc_ioremap(pip);
707 if (ret < 0)
708 return ret;
709
710 setup_data_regs(pip);
711
712 chip->request = sh_gpio_request;
713 chip->free = sh_gpio_free;
714 chip->direction_input = sh_gpio_direction_input;
715 chip->get = sh_gpio_get;
716 chip->direction_output = sh_gpio_direction_output;
717 chip->set = sh_gpio_set;
718 chip->to_irq = sh_gpio_to_irq;
719
720 WARN_ON(pip->first_gpio != 0); /* needs testing */
721
722 chip->label = pip->name;
723 chip->owner = THIS_MODULE;
724 chip->base = pip->first_gpio;
725 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
726
727 ret = gpiochip_add(chip);
728 if (ret < 0)
729 pfc_iounmap(pip);
730
731 return ret;
732}
733
734int unregister_pinmux(struct pinmux_info *pip)
735{
736 pr_info("%s deregistering\n", pip->name);
737 pfc_iounmap(pip);
738 return gpiochip_remove(&pip->chip);
739}
diff --git a/drivers/sh/pfc/Kconfig b/drivers/sh/pfc/Kconfig
new file mode 100644
index 000000000000..804f9ad1bf4a
--- /dev/null
+++ b/drivers/sh/pfc/Kconfig
@@ -0,0 +1,26 @@
1comment "Pin function controller options"
2
3config SH_PFC
4 # XXX move off the gpio dependency
5 depends on GENERIC_GPIO
6 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
7 select PINCTRL_SH_PFC
8 def_bool y
9
10#
11# Placeholder for now, rehome to drivers/pinctrl once the PFC APIs
12# have settled.
13#
14config PINCTRL_SH_PFC
15 tristate "SuperH PFC pin controller driver"
16 depends on SH_PFC
17 select PINCTRL
18 select PINMUX
19 select PINCONF
20
21config GPIO_SH_PFC
22 tristate "SuperH PFC GPIO support"
23 depends on SH_PFC && GPIOLIB
24 help
25 This enables support for GPIOs within the SoC's pin function
26 controller.
diff --git a/drivers/sh/pfc/Makefile b/drivers/sh/pfc/Makefile
new file mode 100644
index 000000000000..7916027cce37
--- /dev/null
+++ b/drivers/sh/pfc/Makefile
@@ -0,0 +1,3 @@
1obj-y += core.o
2obj-$(CONFIG_PINCTRL_SH_PFC) += pinctrl.o
3obj-$(CONFIG_GPIO_SH_PFC) += gpio.o
diff --git a/drivers/sh/pfc/core.c b/drivers/sh/pfc/core.c
new file mode 100644
index 000000000000..68169373c98b
--- /dev/null
+++ b/drivers/sh/pfc/core.c
@@ -0,0 +1,572 @@
1/*
2 * SuperH Pin Function Controller support.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt
12
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/sh_pfc.h>
16#include <linux/module.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/bitops.h>
20#include <linux/slab.h>
21#include <linux/ioport.h>
22#include <linux/pinctrl/machine.h>
23
24static struct sh_pfc *sh_pfc __read_mostly;
25
26static inline bool sh_pfc_initialized(void)
27{
28 return !!sh_pfc;
29}
30
31static void pfc_iounmap(struct sh_pfc *pfc)
32{
33 int k;
34
35 for (k = 0; k < pfc->num_resources; k++)
36 if (pfc->window[k].virt)
37 iounmap(pfc->window[k].virt);
38
39 kfree(pfc->window);
40 pfc->window = NULL;
41}
42
43static int pfc_ioremap(struct sh_pfc *pfc)
44{
45 struct resource *res;
46 int k;
47
48 if (!pfc->num_resources)
49 return 0;
50
51 pfc->window = kzalloc(pfc->num_resources * sizeof(*pfc->window),
52 GFP_NOWAIT);
53 if (!pfc->window)
54 goto err1;
55
56 for (k = 0; k < pfc->num_resources; k++) {
57 res = pfc->resource + k;
58 WARN_ON(resource_type(res) != IORESOURCE_MEM);
59 pfc->window[k].phys = res->start;
60 pfc->window[k].size = resource_size(res);
61 pfc->window[k].virt = ioremap_nocache(res->start,
62 resource_size(res));
63 if (!pfc->window[k].virt)
64 goto err2;
65 }
66
67 return 0;
68
69err2:
70 pfc_iounmap(pfc);
71err1:
72 return -1;
73}
74
75static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
76 unsigned long address)
77{
78 struct pfc_window *window;
79 int k;
80
81 /* scan through physical windows and convert address */
82 for (k = 0; k < pfc->num_resources; k++) {
83 window = pfc->window + k;
84
85 if (address < window->phys)
86 continue;
87
88 if (address >= (window->phys + window->size))
89 continue;
90
91 return window->virt + (address - window->phys);
92 }
93
94 /* no windows defined, register must be 1:1 mapped virt:phys */
95 return (void __iomem *)address;
96}
97
98static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
99{
100 if (enum_id < r->begin)
101 return 0;
102
103 if (enum_id > r->end)
104 return 0;
105
106 return 1;
107}
108
109static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
110 unsigned long reg_width)
111{
112 switch (reg_width) {
113 case 8:
114 return ioread8(mapped_reg);
115 case 16:
116 return ioread16(mapped_reg);
117 case 32:
118 return ioread32(mapped_reg);
119 }
120
121 BUG();
122 return 0;
123}
124
125static void gpio_write_raw_reg(void __iomem *mapped_reg,
126 unsigned long reg_width,
127 unsigned long data)
128{
129 switch (reg_width) {
130 case 8:
131 iowrite8(data, mapped_reg);
132 return;
133 case 16:
134 iowrite16(data, mapped_reg);
135 return;
136 case 32:
137 iowrite32(data, mapped_reg);
138 return;
139 }
140
141 BUG();
142}
143
144int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
145{
146 unsigned long pos;
147
148 pos = dr->reg_width - (in_pos + 1);
149
150 pr_debug("read_bit: addr = %lx, pos = %ld, "
151 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
152
153 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
154}
155EXPORT_SYMBOL_GPL(sh_pfc_read_bit);
156
157void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
158 unsigned long value)
159{
160 unsigned long pos;
161
162 pos = dr->reg_width - (in_pos + 1);
163
164 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
165 "r_width = %ld\n",
166 dr->reg, !!value, pos, dr->reg_width);
167
168 if (value)
169 set_bit(pos, &dr->reg_shadow);
170 else
171 clear_bit(pos, &dr->reg_shadow);
172
173 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
174}
175EXPORT_SYMBOL_GPL(sh_pfc_write_bit);
176
177static void config_reg_helper(struct sh_pfc *pfc,
178 struct pinmux_cfg_reg *crp,
179 unsigned long in_pos,
180 void __iomem **mapped_regp,
181 unsigned long *maskp,
182 unsigned long *posp)
183{
184 int k;
185
186 *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
187
188 if (crp->field_width) {
189 *maskp = (1 << crp->field_width) - 1;
190 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
191 } else {
192 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
193 *posp = crp->reg_width;
194 for (k = 0; k <= in_pos; k++)
195 *posp -= crp->var_field_width[k];
196 }
197}
198
199static int read_config_reg(struct sh_pfc *pfc,
200 struct pinmux_cfg_reg *crp,
201 unsigned long field)
202{
203 void __iomem *mapped_reg;
204 unsigned long mask, pos;
205
206 config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
207
208 pr_debug("read_reg: addr = %lx, field = %ld, "
209 "r_width = %ld, f_width = %ld\n",
210 crp->reg, field, crp->reg_width, crp->field_width);
211
212 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
213}
214
215static void write_config_reg(struct sh_pfc *pfc,
216 struct pinmux_cfg_reg *crp,
217 unsigned long field, unsigned long value)
218{
219 void __iomem *mapped_reg;
220 unsigned long mask, pos, data;
221
222 config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
223
224 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
225 "r_width = %ld, f_width = %ld\n",
226 crp->reg, value, field, crp->reg_width, crp->field_width);
227
228 mask = ~(mask << pos);
229 value = value << pos;
230
231 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
232 data &= mask;
233 data |= value;
234
235 if (pfc->unlock_reg)
236 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->unlock_reg),
237 32, ~data);
238
239 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
240}
241
242static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
243{
244 struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
245 struct pinmux_data_reg *data_reg;
246 int k, n;
247
248 if (!enum_in_range(gpiop->enum_id, &pfc->data))
249 return -1;
250
251 k = 0;
252 while (1) {
253 data_reg = pfc->data_regs + k;
254
255 if (!data_reg->reg_width)
256 break;
257
258 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
259
260 for (n = 0; n < data_reg->reg_width; n++) {
261 if (data_reg->enum_ids[n] == gpiop->enum_id) {
262 gpiop->flags &= ~PINMUX_FLAG_DREG;
263 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
264 gpiop->flags &= ~PINMUX_FLAG_DBIT;
265 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
266 return 0;
267 }
268 }
269 k++;
270 }
271
272 BUG();
273
274 return -1;
275}
276
277static void setup_data_regs(struct sh_pfc *pfc)
278{
279 struct pinmux_data_reg *drp;
280 int k;
281
282 for (k = pfc->first_gpio; k <= pfc->last_gpio; k++)
283 setup_data_reg(pfc, k);
284
285 k = 0;
286 while (1) {
287 drp = pfc->data_regs + k;
288
289 if (!drp->reg_width)
290 break;
291
292 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
293 drp->reg_width);
294 k++;
295 }
296}
297
298int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
299 struct pinmux_data_reg **drp, int *bitp)
300{
301 struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
302 int k, n;
303
304 if (!enum_in_range(gpiop->enum_id, &pfc->data))
305 return -1;
306
307 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
308 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
309 *drp = pfc->data_regs + k;
310 *bitp = n;
311 return 0;
312}
313EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg);
314
315static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
316 struct pinmux_cfg_reg **crp,
317 int *fieldp, int *valuep,
318 unsigned long **cntp)
319{
320 struct pinmux_cfg_reg *config_reg;
321 unsigned long r_width, f_width, curr_width, ncomb;
322 int k, m, n, pos, bit_pos;
323
324 k = 0;
325 while (1) {
326 config_reg = pfc->cfg_regs + k;
327
328 r_width = config_reg->reg_width;
329 f_width = config_reg->field_width;
330
331 if (!r_width)
332 break;
333
334 pos = 0;
335 m = 0;
336 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
337 if (f_width)
338 curr_width = f_width;
339 else
340 curr_width = config_reg->var_field_width[m];
341
342 ncomb = 1 << curr_width;
343 for (n = 0; n < ncomb; n++) {
344 if (config_reg->enum_ids[pos + n] == enum_id) {
345 *crp = config_reg;
346 *fieldp = m;
347 *valuep = n;
348 *cntp = &config_reg->cnt[m];
349 return 0;
350 }
351 }
352 pos += ncomb;
353 m++;
354 }
355 k++;
356 }
357
358 return -1;
359}
360
361int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
362 pinmux_enum_t *enum_idp)
363{
364 pinmux_enum_t enum_id = pfc->gpios[gpio].enum_id;
365 pinmux_enum_t *data = pfc->gpio_data;
366 int k;
367
368 if (!enum_in_range(enum_id, &pfc->data)) {
369 if (!enum_in_range(enum_id, &pfc->mark)) {
370 pr_err("non data/mark enum_id for gpio %d\n", gpio);
371 return -1;
372 }
373 }
374
375 if (pos) {
376 *enum_idp = data[pos + 1];
377 return pos + 1;
378 }
379
380 for (k = 0; k < pfc->gpio_data_size; k++) {
381 if (data[k] == enum_id) {
382 *enum_idp = data[k + 1];
383 return k + 1;
384 }
385 }
386
387 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
388 return -1;
389}
390EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum);
391
392int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
393 int cfg_mode)
394{
395 struct pinmux_cfg_reg *cr = NULL;
396 pinmux_enum_t enum_id;
397 struct pinmux_range *range;
398 int in_range, pos, field, value;
399 unsigned long *cntp;
400
401 switch (pinmux_type) {
402
403 case PINMUX_TYPE_FUNCTION:
404 range = NULL;
405 break;
406
407 case PINMUX_TYPE_OUTPUT:
408 range = &pfc->output;
409 break;
410
411 case PINMUX_TYPE_INPUT:
412 range = &pfc->input;
413 break;
414
415 case PINMUX_TYPE_INPUT_PULLUP:
416 range = &pfc->input_pu;
417 break;
418
419 case PINMUX_TYPE_INPUT_PULLDOWN:
420 range = &pfc->input_pd;
421 break;
422
423 default:
424 goto out_err;
425 }
426
427 pos = 0;
428 enum_id = 0;
429 field = 0;
430 value = 0;
431 while (1) {
432 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
433 if (pos <= 0)
434 goto out_err;
435
436 if (!enum_id)
437 break;
438
439 /* first check if this is a function enum */
440 in_range = enum_in_range(enum_id, &pfc->function);
441 if (!in_range) {
442 /* not a function enum */
443 if (range) {
444 /*
445 * other range exists, so this pin is
446 * a regular GPIO pin that now is being
447 * bound to a specific direction.
448 *
449 * for this case we only allow function enums
450 * and the enums that match the other range.
451 */
452 in_range = enum_in_range(enum_id, range);
453
454 /*
455 * special case pass through for fixed
456 * input-only or output-only pins without
457 * function enum register association.
458 */
459 if (in_range && enum_id == range->force)
460 continue;
461 } else {
462 /*
463 * no other range exists, so this pin
464 * must then be of the function type.
465 *
466 * allow function type pins to select
467 * any combination of function/in/out
468 * in their MARK lists.
469 */
470 in_range = 1;
471 }
472 }
473
474 if (!in_range)
475 continue;
476
477 if (get_config_reg(pfc, enum_id, &cr,
478 &field, &value, &cntp) != 0)
479 goto out_err;
480
481 switch (cfg_mode) {
482 case GPIO_CFG_DRYRUN:
483 if (!*cntp ||
484 (read_config_reg(pfc, cr, field) != value))
485 continue;
486 break;
487
488 case GPIO_CFG_REQ:
489 write_config_reg(pfc, cr, field, value);
490 *cntp = *cntp + 1;
491 break;
492
493 case GPIO_CFG_FREE:
494 *cntp = *cntp - 1;
495 break;
496 }
497 }
498
499 return 0;
500 out_err:
501 return -1;
502}
503EXPORT_SYMBOL_GPL(sh_pfc_config_gpio);
504
505int register_sh_pfc(struct sh_pfc *pfc)
506{
507 int (*initroutine)(struct sh_pfc *) = NULL;
508 int ret;
509
510 /*
511 * Ensure that the type encoding fits
512 */
513 BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
514
515 if (sh_pfc)
516 return -EBUSY;
517
518 ret = pfc_ioremap(pfc);
519 if (unlikely(ret < 0))
520 return ret;
521
522 spin_lock_init(&pfc->lock);
523
524 pinctrl_provide_dummies();
525 setup_data_regs(pfc);
526
527 sh_pfc = pfc;
528
529 /*
530 * Initialize pinctrl bindings first
531 */
532 initroutine = symbol_request(sh_pfc_register_pinctrl);
533 if (initroutine) {
534 ret = (*initroutine)(pfc);
535 symbol_put_addr(initroutine);
536
537 if (unlikely(ret != 0))
538 goto err;
539 } else {
540 pr_err("failed to initialize pinctrl bindings\n");
541 goto err;
542 }
543
544 /*
545 * Then the GPIO chip
546 */
547 initroutine = symbol_request(sh_pfc_register_gpiochip);
548 if (initroutine) {
549 ret = (*initroutine)(pfc);
550 symbol_put_addr(initroutine);
551
552 /*
553 * If the GPIO chip fails to come up we still leave the
554 * PFC state as it is, given that there are already
555 * extant users of it that have succeeded by this point.
556 */
557 if (unlikely(ret != 0)) {
558 pr_notice("failed to init GPIO chip, ignoring...\n");
559 ret = 0;
560 }
561 }
562
563 pr_info("%s support registered\n", pfc->name);
564
565 return 0;
566
567err:
568 pfc_iounmap(pfc);
569 sh_pfc = NULL;
570
571 return ret;
572}
diff --git a/drivers/sh/pfc/gpio.c b/drivers/sh/pfc/gpio.c
new file mode 100644
index 000000000000..62bca98474a9
--- /dev/null
+++ b/drivers/sh/pfc/gpio.c
@@ -0,0 +1,239 @@
1/*
2 * SuperH Pin Function Controller GPIO driver.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt
12
13#include <linux/init.h>
14#include <linux/gpio.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/pinctrl/consumer.h>
20
21struct sh_pfc_chip {
22 struct sh_pfc *pfc;
23 struct gpio_chip gpio_chip;
24};
25
26static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
27{
28 return container_of(gc, struct sh_pfc_chip, gpio_chip);
29}
30
31static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
32{
33 return gpio_to_pfc_chip(gc)->pfc;
34}
35
36static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
37{
38 return pinctrl_request_gpio(offset);
39}
40
41static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
42{
43 pinctrl_free_gpio(offset);
44}
45
46static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
47{
48 struct pinmux_data_reg *dr = NULL;
49 int bit = 0;
50
51 if (!pfc || sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
52 BUG();
53 else
54 sh_pfc_write_bit(dr, bit, value);
55}
56
57static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
58{
59 struct pinmux_data_reg *dr = NULL;
60 int bit = 0;
61
62 if (!pfc || sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
63 return -EINVAL;
64
65 return sh_pfc_read_bit(dr, bit);
66}
67
68static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
69{
70 return pinctrl_gpio_direction_input(offset);
71}
72
73static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
74 int value)
75{
76 sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
77
78 return pinctrl_gpio_direction_output(offset);
79}
80
81static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
82{
83 return sh_gpio_get_value(gpio_to_pfc(gc), offset);
84}
85
86static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
87{
88 sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
89}
90
91static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
92{
93 struct sh_pfc *pfc = gpio_to_pfc(gc);
94 pinmux_enum_t enum_id;
95 pinmux_enum_t *enum_ids;
96 int i, k, pos;
97
98 pos = 0;
99 enum_id = 0;
100 while (1) {
101 pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
102 if (pos <= 0 || !enum_id)
103 break;
104
105 for (i = 0; i < pfc->gpio_irq_size; i++) {
106 enum_ids = pfc->gpio_irq[i].enum_ids;
107 for (k = 0; enum_ids[k]; k++) {
108 if (enum_ids[k] == enum_id)
109 return pfc->gpio_irq[i].irq;
110 }
111 }
112 }
113
114 return -ENOSYS;
115}
116
117static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
118{
119 struct sh_pfc *pfc = chip->pfc;
120 struct gpio_chip *gc = &chip->gpio_chip;
121
122 gc->request = sh_gpio_request;
123 gc->free = sh_gpio_free;
124 gc->direction_input = sh_gpio_direction_input;
125 gc->get = sh_gpio_get;
126 gc->direction_output = sh_gpio_direction_output;
127 gc->set = sh_gpio_set;
128 gc->to_irq = sh_gpio_to_irq;
129
130 WARN_ON(pfc->first_gpio != 0); /* needs testing */
131
132 gc->label = pfc->name;
133 gc->owner = THIS_MODULE;
134 gc->base = pfc->first_gpio;
135 gc->ngpio = (pfc->last_gpio - pfc->first_gpio) + 1;
136}
137
138int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
139{
140 struct sh_pfc_chip *chip;
141 int ret;
142
143 chip = kzalloc(sizeof(struct sh_pfc_chip), GFP_KERNEL);
144 if (unlikely(!chip))
145 return -ENOMEM;
146
147 chip->pfc = pfc;
148
149 sh_pfc_gpio_setup(chip);
150
151 ret = gpiochip_add(&chip->gpio_chip);
152 if (unlikely(ret < 0))
153 kfree(chip);
154
155 pr_info("%s handling gpio %d -> %d\n",
156 pfc->name, pfc->first_gpio, pfc->last_gpio);
157
158 return ret;
159}
160EXPORT_SYMBOL_GPL(sh_pfc_register_gpiochip);
161
162static int sh_pfc_gpio_match(struct gpio_chip *gc, void *data)
163{
164 return !!strstr(gc->label, data);
165}
166
167static int __devinit sh_pfc_gpio_probe(struct platform_device *pdev)
168{
169 struct sh_pfc_chip *chip;
170 struct gpio_chip *gc;
171
172 gc = gpiochip_find("_pfc", sh_pfc_gpio_match);
173 if (unlikely(!gc)) {
174 pr_err("Cant find gpio chip\n");
175 return -ENODEV;
176 }
177
178 chip = gpio_to_pfc_chip(gc);
179 platform_set_drvdata(pdev, chip);
180
181 pr_info("attaching to GPIO chip %s\n", chip->pfc->name);
182
183 return 0;
184}
185
186static int __devexit sh_pfc_gpio_remove(struct platform_device *pdev)
187{
188 struct sh_pfc_chip *chip = platform_get_drvdata(pdev);
189 int ret;
190
191 ret = gpiochip_remove(&chip->gpio_chip);
192 if (unlikely(ret < 0))
193 return ret;
194
195 kfree(chip);
196 return 0;
197}
198
199static struct platform_driver sh_pfc_gpio_driver = {
200 .probe = sh_pfc_gpio_probe,
201 .remove = __devexit_p(sh_pfc_gpio_remove),
202 .driver = {
203 .name = KBUILD_MODNAME,
204 .owner = THIS_MODULE,
205 },
206};
207
208static struct platform_device sh_pfc_gpio_device = {
209 .name = KBUILD_MODNAME,
210 .id = -1,
211};
212
213static int __init sh_pfc_gpio_init(void)
214{
215 int rc;
216
217 rc = platform_driver_register(&sh_pfc_gpio_driver);
218 if (likely(!rc)) {
219 rc = platform_device_register(&sh_pfc_gpio_device);
220 if (unlikely(rc))
221 platform_driver_unregister(&sh_pfc_gpio_driver);
222 }
223
224 return rc;
225}
226
227static void __exit sh_pfc_gpio_exit(void)
228{
229 platform_device_unregister(&sh_pfc_gpio_device);
230 platform_driver_unregister(&sh_pfc_gpio_driver);
231}
232
233module_init(sh_pfc_gpio_init);
234module_exit(sh_pfc_gpio_exit);
235
236MODULE_AUTHOR("Magnus Damm, Paul Mundt");
237MODULE_DESCRIPTION("GPIO driver for SuperH pin function controller");
238MODULE_LICENSE("GPL v2");
239MODULE_ALIAS("platform:pfc-gpio");
diff --git a/drivers/sh/pfc/pinctrl.c b/drivers/sh/pfc/pinctrl.c
new file mode 100644
index 000000000000..2804eaae804e
--- /dev/null
+++ b/drivers/sh/pfc/pinctrl.c
@@ -0,0 +1,526 @@
1/*
2 * SuperH Pin Function Controller pinmux support.
3 *
4 * Copyright (C) 2012 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#define DRV_NAME "pinctrl-sh_pfc"
11
12#define pr_fmt(fmt) DRV_NAME " " KBUILD_MODNAME ": " fmt
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/sh_pfc.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/platform_device.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/pinctrl/pinconf-generic.h>
26
27struct sh_pfc_pinctrl {
28 struct pinctrl_dev *pctl;
29 struct sh_pfc *pfc;
30
31 struct pinmux_gpio **functions;
32 unsigned int nr_functions;
33
34 struct pinctrl_pin_desc *pads;
35 unsigned int nr_pads;
36
37 spinlock_t lock;
38};
39
40static struct sh_pfc_pinctrl *sh_pfc_pmx;
41
42static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
43{
44 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
45
46 return pmx->nr_pads;
47}
48
49static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
50 unsigned selector)
51{
52 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
53
54 return pmx->pads[selector].name;
55}
56
57static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
58 const unsigned **pins, unsigned *num_pins)
59{
60 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
61
62 *pins = &pmx->pads[group].number;
63 *num_pins = 1;
64
65 return 0;
66}
67
68static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
69 unsigned offset)
70{
71 seq_printf(s, "%s", DRV_NAME);
72}
73
74static struct pinctrl_ops sh_pfc_pinctrl_ops = {
75 .get_groups_count = sh_pfc_get_groups_count,
76 .get_group_name = sh_pfc_get_group_name,
77 .get_group_pins = sh_pfc_get_group_pins,
78 .pin_dbg_show = sh_pfc_pin_dbg_show,
79};
80
81static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
82{
83 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
84
85 return pmx->nr_functions;
86}
87
88static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
89 unsigned selector)
90{
91 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
92
93 return pmx->functions[selector]->name;
94}
95
96static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
97 const char * const **groups,
98 unsigned * const num_groups)
99{
100 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
101
102 *groups = &pmx->functions[func]->name;
103 *num_groups = 1;
104
105 return 0;
106}
107
108static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
109 unsigned group)
110{
111 return 0;
112}
113
114static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
115 unsigned group)
116{
117}
118
119static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
120{
121 if (sh_pfc_config_gpio(pfc, offset,
122 PINMUX_TYPE_FUNCTION,
123 GPIO_CFG_DRYRUN) != 0)
124 return -EINVAL;
125
126 if (sh_pfc_config_gpio(pfc, offset,
127 PINMUX_TYPE_FUNCTION,
128 GPIO_CFG_REQ) != 0)
129 return -EINVAL;
130
131 return 0;
132}
133
134static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
135 int new_type)
136{
137 unsigned long flags;
138 int pinmux_type;
139 int ret = -EINVAL;
140
141 spin_lock_irqsave(&pfc->lock, flags);
142
143 pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
144
145 /*
146 * See if the present config needs to first be de-configured.
147 */
148 switch (pinmux_type) {
149 case PINMUX_TYPE_GPIO:
150 break;
151 case PINMUX_TYPE_OUTPUT:
152 case PINMUX_TYPE_INPUT:
153 case PINMUX_TYPE_INPUT_PULLUP:
154 case PINMUX_TYPE_INPUT_PULLDOWN:
155 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
156 break;
157 default:
158 goto err;
159 }
160
161 /*
162 * Dry run
163 */
164 if (sh_pfc_config_gpio(pfc, offset, new_type,
165 GPIO_CFG_DRYRUN) != 0)
166 goto err;
167
168 /*
169 * Request
170 */
171 if (sh_pfc_config_gpio(pfc, offset, new_type,
172 GPIO_CFG_REQ) != 0)
173 goto err;
174
175 pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
176 pfc->gpios[offset].flags |= new_type;
177
178 ret = 0;
179
180err:
181 spin_unlock_irqrestore(&pfc->lock, flags);
182
183 return ret;
184}
185
186
187static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
188 struct pinctrl_gpio_range *range,
189 unsigned offset)
190{
191 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
192 struct sh_pfc *pfc = pmx->pfc;
193 unsigned long flags;
194 int ret, pinmux_type;
195
196 spin_lock_irqsave(&pfc->lock, flags);
197
198 pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
199
200 switch (pinmux_type) {
201 case PINMUX_TYPE_FUNCTION:
202 pr_notice_once("Use of GPIO API for function requests is "
203 "deprecated, convert to pinctrl\n");
204 /* handle for now */
205 ret = sh_pfc_config_function(pfc, offset);
206 if (unlikely(ret < 0))
207 goto err;
208
209 break;
210 case PINMUX_TYPE_GPIO:
211 break;
212 default:
213 pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
214 return -ENOTSUPP;
215 }
216
217 ret = 0;
218
219err:
220 spin_unlock_irqrestore(&pfc->lock, flags);
221
222 return ret;
223}
224
225static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
226 struct pinctrl_gpio_range *range,
227 unsigned offset)
228{
229 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
230 struct sh_pfc *pfc = pmx->pfc;
231 unsigned long flags;
232 int pinmux_type;
233
234 spin_lock_irqsave(&pfc->lock, flags);
235
236 pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
237
238 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
239
240 spin_unlock_irqrestore(&pfc->lock, flags);
241}
242
243static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
244 struct pinctrl_gpio_range *range,
245 unsigned offset, bool input)
246{
247 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
248 int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
249
250 return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
251}
252
253static struct pinmux_ops sh_pfc_pinmux_ops = {
254 .get_functions_count = sh_pfc_get_functions_count,
255 .get_function_name = sh_pfc_get_function_name,
256 .get_function_groups = sh_pfc_get_function_groups,
257 .enable = sh_pfc_noop_enable,
258 .disable = sh_pfc_noop_disable,
259 .gpio_request_enable = sh_pfc_gpio_request_enable,
260 .gpio_disable_free = sh_pfc_gpio_disable_free,
261 .gpio_set_direction = sh_pfc_gpio_set_direction,
262};
263
264static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
265 unsigned long *config)
266{
267 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
268 struct sh_pfc *pfc = pmx->pfc;
269
270 *config = pfc->gpios[pin].flags & PINMUX_FLAG_TYPE;
271
272 return 0;
273}
274
275static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
276 unsigned long config)
277{
278 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
279
280 /* Validate the new type */
281 if (config >= PINMUX_FLAG_TYPE)
282 return -EINVAL;
283
284 return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
285}
286
287static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
288 struct seq_file *s, unsigned pin)
289{
290 const char *pinmux_type_str[] = {
291 [PINMUX_TYPE_NONE] = "none",
292 [PINMUX_TYPE_FUNCTION] = "function",
293 [PINMUX_TYPE_GPIO] = "gpio",
294 [PINMUX_TYPE_OUTPUT] = "output",
295 [PINMUX_TYPE_INPUT] = "input",
296 [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
297 [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
298 };
299 unsigned long config;
300 int rc;
301
302 rc = sh_pfc_pinconf_get(pctldev, pin, &config);
303 if (unlikely(rc != 0))
304 return;
305
306 seq_printf(s, " %s", pinmux_type_str[config]);
307}
308
309static struct pinconf_ops sh_pfc_pinconf_ops = {
310 .pin_config_get = sh_pfc_pinconf_get,
311 .pin_config_set = sh_pfc_pinconf_set,
312 .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
313};
314
315static struct pinctrl_gpio_range sh_pfc_gpio_range = {
316 .name = DRV_NAME,
317 .id = 0,
318};
319
320static struct pinctrl_desc sh_pfc_pinctrl_desc = {
321 .name = DRV_NAME,
322 .owner = THIS_MODULE,
323 .pctlops = &sh_pfc_pinctrl_ops,
324 .pmxops = &sh_pfc_pinmux_ops,
325 .confops = &sh_pfc_pinconf_ops,
326};
327
328static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
329 struct sh_pfc_pinctrl *pmx,
330 struct pinmux_gpio *gpio,
331 unsigned offset)
332{
333 struct pinmux_data_reg *dummy;
334 unsigned long flags;
335 int bit;
336
337 gpio->flags &= ~PINMUX_FLAG_TYPE;
338
339 if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
340 gpio->flags |= PINMUX_TYPE_GPIO;
341 else {
342 gpio->flags |= PINMUX_TYPE_FUNCTION;
343
344 spin_lock_irqsave(&pmx->lock, flags);
345 pmx->nr_functions++;
346 spin_unlock_irqrestore(&pmx->lock, flags);
347 }
348}
349
350/* pinmux ranges -> pinctrl pin descs */
351static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
352 struct sh_pfc_pinctrl *pmx)
353{
354 unsigned long flags;
355 int i;
356
357 pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;
358
359 pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
360 GFP_KERNEL);
361 if (unlikely(!pmx->pads)) {
362 pmx->nr_pads = 0;
363 return -ENOMEM;
364 }
365
366 spin_lock_irqsave(&pfc->lock, flags);
367
368 /*
369 * We don't necessarily have a 1:1 mapping between pin and linux
370 * GPIO number, as the latter maps to the associated enum_id.
371 * Care needs to be taken to translate back to pin space when
372 * dealing with any pin configurations.
373 */
374 for (i = 0; i < pmx->nr_pads; i++) {
375 struct pinctrl_pin_desc *pin = pmx->pads + i;
376 struct pinmux_gpio *gpio = pfc->gpios + i;
377
378 pin->number = pfc->first_gpio + i;
379 pin->name = gpio->name;
380
381 /* XXX */
382 if (unlikely(!gpio->enum_id))
383 continue;
384
385 sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
386 }
387
388 spin_unlock_irqrestore(&pfc->lock, flags);
389
390 sh_pfc_pinctrl_desc.pins = pmx->pads;
391 sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
392
393 return 0;
394}
395
396static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
397 struct sh_pfc_pinctrl *pmx)
398{
399 unsigned long flags;
400 int i, fn;
401
402 pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
403 GFP_KERNEL);
404 if (unlikely(!pmx->functions))
405 return -ENOMEM;
406
407 spin_lock_irqsave(&pmx->lock, flags);
408
409 for (i = fn = 0; i < pmx->nr_pads; i++) {
410 struct pinmux_gpio *gpio = pfc->gpios + i;
411
412 if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
413 pmx->functions[fn++] = gpio;
414 }
415
416 spin_unlock_irqrestore(&pmx->lock, flags);
417
418 return 0;
419}
420
421static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
422{
423 struct sh_pfc *pfc;
424 int ret;
425
426 if (unlikely(!sh_pfc_pmx))
427 return -ENODEV;
428
429 pfc = sh_pfc_pmx->pfc;
430
431 ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
432 if (unlikely(ret != 0))
433 return ret;
434
435 ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
436 if (unlikely(ret != 0))
437 goto free_pads;
438
439 sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
440 sh_pfc_pmx);
441 if (IS_ERR(sh_pfc_pmx->pctl)) {
442 ret = PTR_ERR(sh_pfc_pmx->pctl);
443 goto free_functions;
444 }
445
446 sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
447 sh_pfc_gpio_range.base = pfc->first_gpio;
448 sh_pfc_gpio_range.pin_base = pfc->first_gpio;
449
450 pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);
451
452 platform_set_drvdata(pdev, sh_pfc_pmx);
453
454 return 0;
455
456free_functions:
457 kfree(sh_pfc_pmx->functions);
458free_pads:
459 kfree(sh_pfc_pmx->pads);
460 kfree(sh_pfc_pmx);
461
462 return ret;
463}
464
465static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
466{
467 struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);
468
469 pinctrl_unregister(pmx->pctl);
470
471 platform_set_drvdata(pdev, NULL);
472
473 kfree(sh_pfc_pmx->functions);
474 kfree(sh_pfc_pmx->pads);
475 kfree(sh_pfc_pmx);
476
477 return 0;
478}
479
480static struct platform_driver sh_pfc_pinctrl_driver = {
481 .probe = sh_pfc_pinctrl_probe,
482 .remove = __devexit_p(sh_pfc_pinctrl_remove),
483 .driver = {
484 .name = DRV_NAME,
485 .owner = THIS_MODULE,
486 },
487};
488
489static struct platform_device sh_pfc_pinctrl_device = {
490 .name = DRV_NAME,
491 .id = -1,
492};
493
494static int sh_pfc_pinctrl_init(void)
495{
496 int rc;
497
498 rc = platform_driver_register(&sh_pfc_pinctrl_driver);
499 if (likely(!rc)) {
500 rc = platform_device_register(&sh_pfc_pinctrl_device);
501 if (unlikely(rc))
502 platform_driver_unregister(&sh_pfc_pinctrl_driver);
503 }
504
505 return rc;
506}
507
508int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
509{
510 sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
511 if (unlikely(!sh_pfc_pmx))
512 return -ENOMEM;
513
514 spin_lock_init(&sh_pfc_pmx->lock);
515
516 sh_pfc_pmx->pfc = pfc;
517
518 return sh_pfc_pinctrl_init();
519}
520EXPORT_SYMBOL_GPL(sh_pfc_register_pinctrl);
521
522static void __exit sh_pfc_pinctrl_exit(void)
523{
524 platform_driver_unregister(&sh_pfc_pinctrl_driver);
525}
526module_exit(sh_pfc_pinctrl_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-15 05:21:15 -0400