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Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r--drivers/serial/sh-sci.h35
1 files changed, 27 insertions, 8 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index fad67d33b0bd..f70c49f915fa 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -31,7 +31,9 @@
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
34 defined(CONFIG_ARCH_SHMOBILE) 34 defined(CONFIG_ARCH_SH7367) || \
35 defined(CONFIG_ARCH_SH7377) || \
36 defined(CONFIG_ARCH_SH7372)
35# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 37# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
36# define PORT_PTCR 0xA405011EUL 38# define PORT_PTCR 0xA405011EUL
37# define PORT_PVCR 0xA4050122UL 39# define PORT_PVCR 0xA4050122UL
@@ -94,7 +96,9 @@
94# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
95#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 97#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
96# define SCIF_ORER 0x0001 /* overrun error bit */ 98# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 99# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
100 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
101 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
98#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 102#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
99# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 103# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
100# define SCIF_ORER 0x0001 /* overrun error bit */ 104# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -197,6 +201,8 @@
197 defined(CONFIG_CPU_SUBTYPE_SH7786) || \ 201 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
198 defined(CONFIG_CPU_SUBTYPE_SHX3) 202 defined(CONFIG_CPU_SUBTYPE_SHX3)
199#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 203#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
204#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
205#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
200#else 206#else
201#define SCI_CTRL_FLAGS_REIE 0 207#define SCI_CTRL_FLAGS_REIE 0
202#endif 208#endif
@@ -230,7 +236,9 @@
230#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 236#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
231 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 237 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
232 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 238 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
233 defined(CONFIG_ARCH_SHMOBILE) 239 defined(CONFIG_ARCH_SH7367) || \
240 defined(CONFIG_ARCH_SH7377) || \
241 defined(CONFIG_ARCH_SH7372)
234# define SCIF_ORER 0x0200 242# define SCIF_ORER 0x0200
235# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 243# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
236# define SCIF_RFDC_MASK 0x007f 244# define SCIF_RFDC_MASK 0x007f
@@ -264,7 +272,9 @@
264#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 272#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 273 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 274 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
267 defined(CONFIG_ARCH_SHMOBILE) 275 defined(CONFIG_ARCH_SH7367) || \
276 defined(CONFIG_ARCH_SH7377) || \
277 defined(CONFIG_ARCH_SH7372)
268# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 278# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
269# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 279# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
270# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 280# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
@@ -359,7 +369,10 @@
359 SCI_OUT(sci_size, sci_offset, value); \ 369 SCI_OUT(sci_size, sci_offset, value); \
360 } 370 }
361 371
362#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) 372#if defined(CONFIG_CPU_SH3) || \
373 defined(CONFIG_ARCH_SH7367) || \
374 defined(CONFIG_ARCH_SH7377) || \
375 defined(CONFIG_ARCH_SH7372)
363#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 376#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
364#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 377#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
365 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
@@ -370,7 +383,9 @@
370#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 383#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
371 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
372 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
373 defined(CONFIG_ARCH_SHMOBILE) 386 defined(CONFIG_ARCH_SH7367) || \
387 defined(CONFIG_ARCH_SH7377) || \
388 defined(CONFIG_ARCH_SH7372)
374#define SCIF_FNS(name, scif_offset, scif_size) \ 389#define SCIF_FNS(name, scif_offset, scif_size) \
375 CPU_SCIF_FNS(name, scif_offset, scif_size) 390 CPU_SCIF_FNS(name, scif_offset, scif_size)
376#else 391#else
@@ -406,7 +421,9 @@
406#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 421#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
407 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 422 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
408 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 423 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
409 defined(CONFIG_ARCH_SHMOBILE) 424 defined(CONFIG_ARCH_SH7367) || \
425 defined(CONFIG_ARCH_SH7377) || \
426 defined(CONFIG_ARCH_SH7372)
410 427
411SCIF_FNS(SCSMR, 0x00, 16) 428SCIF_FNS(SCSMR, 0x00, 16)
412SCIF_FNS(SCBRR, 0x04, 8) 429SCIF_FNS(SCBRR, 0x04, 8)
@@ -589,7 +606,9 @@ static inline int sci_rxd_in(struct uart_port *port)
589#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 606#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
590 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 607 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
591 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 608 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
592 defined(CONFIG_ARCH_SHMOBILE) 609 defined(CONFIG_ARCH_SH7367) || \
610 defined(CONFIG_ARCH_SH7377) || \
611 defined(CONFIG_ARCH_SH7372)
593#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 612#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
594#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 613#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
595 defined(CONFIG_CPU_SUBTYPE_SH7724) 614 defined(CONFIG_CPU_SUBTYPE_SH7724)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 07:18:30 -0500