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-rw-r--r--drivers/serial/mfd.c1488
1 files changed, 1488 insertions, 0 deletions
diff --git a/drivers/serial/mfd.c b/drivers/serial/mfd.c
new file mode 100644
index 000000000000..300dcb134e07
--- /dev/null
+++ b/drivers/serial/mfd.c
@@ -0,0 +1,1488 @@
1/*
2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
3 *
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5 *
6 * (C) Copyright 2009 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14
15/* Notes:
16 * 1. there should be 2 types of register access method, one for
17 * UART ports, the other for the general purpose registers
18 *
19 * 2. It used to have a Irda port, but was defeatured recently
20 *
21 * 3. Based on the info from HSU MAS, 0/1 channel are assigned to
22 * port0, 2/3 chan to port 1, 4/5 chan to port 3. Even number
23 * chan will be read, odd chan for write
24 *
25 * 4. HUS supports both the 64B and 16B FIFO version, but this driver
26 * will only use 64B version
27 *
28 * 5. In A0 stepping, UART will not support TX half empty flag, thus
29 * need add a #ifdef judgement
30 *
31 * 6. One more bug for A0, the loopback mode won't support AFC
32 * auto-flow control
33 *
34 * 7. HSU has some special FCR control bits, we add it to serial_reg.h
35 *
36 * 8. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always asserted,
37 * only when the HW is reset the DDCD and DDSR will be triggered
38 */
39
40#include <linux/module.h>
41#include <linux/init.h>
42#include <linux/console.h>
43#include <linux/sysrq.h>
44#include <linux/serial_reg.h>
45#include <linux/circ_buf.h>
46#include <linux/delay.h>
47#include <linux/interrupt.h>
48#include <linux/tty.h>
49#include <linux/tty_flip.h>
50#include <linux/serial_core.h>
51#include <linux/serial_mfd.h>
52#include <linux/dma-mapping.h>
53#include <linux/pci.h>
54#include <linux/io.h>
55#include <linux/debugfs.h>
56
57#define MFD_HSU_A0_STEPPING 1
58
59#define HSU_DMA_BUF_SIZE 2048
60
61#define chan_readl(chan, offset) readl(chan->reg + offset)
62#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
63
64#define mfd_readl(obj, offset) readl(obj->reg + offset)
65#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
66
67struct hsu_dma_buffer {
68 u8 *buf;
69 dma_addr_t dma_addr;
70 u32 dma_size;
71 u32 ofs;
72};
73
74struct hsu_dma_chan {
75 u32 id;
76 u32 dirt; /* to or from device */
77 struct uart_hsu_port *uport;
78 void __iomem *reg;
79};
80
81struct uart_hsu_port {
82 struct uart_port port;
83 unsigned char ier;
84 unsigned char lcr;
85 unsigned char mcr;
86 unsigned int lsr_break_flag;
87 char name[12];
88 int index;
89 struct device *dev;
90
91 struct hsu_dma_chan *txc;
92 struct hsu_dma_chan *rxc;
93 struct hsu_dma_buffer txbuf;
94 struct hsu_dma_buffer rxbuf;
95 int use_dma; /* flag for DMA/PIO */
96 int running;
97 int dma_tx_on;
98};
99
100/* Top level data structure of HSU */
101struct hsu_port {
102 struct pci_device *pdev;
103
104 void __iomem *reg;
105 unsigned long paddr;
106 unsigned long iolen;
107 u32 irq;
108
109 struct uart_hsu_port port[3];
110 struct hsu_dma_chan chans[10];
111
112#ifdef CONFIG_DEBUG_FS
113 struct dentry *debugfs;
114#endif
115};
116
117static inline void hexdump(char *str, u8 *addr, int cnt)
118{
119 int i;
120
121 for (i = 0; i < cnt; i += 8) {
122 printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
123 addr[i], addr[i+1], addr[i+2], addr[i+3],
124 addr[i+4], addr[i+5], addr[i+6], addr[i+7]);
125 printk("\n");
126 }
127}
128
129static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
130{
131 unsigned int val;
132
133 if (offset > UART_MSR) {
134 offset <<= 2;
135 val = readl(up->port.membase + offset);
136 } else
137 val = (unsigned int)readb(up->port.membase + offset);
138
139 return val;
140}
141
142static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
143{
144 if (offset > UART_MSR) {
145 offset <<= 2;
146 writel(value, up->port.membase + offset);
147 } else {
148 unsigned char val = value & 0xff;
149 writeb(val, up->port.membase + offset);
150 }
151}
152
153#ifdef CONFIG_DEBUG_FS
154
155#define HSU_REGS_BUFSIZE 1024
156
157static int hsu_show_regs_open(struct inode *inode, struct file *file)
158{
159 file->private_data = inode->i_private;
160 return 0;
161}
162
163static ssize_t port_show_regs(struct file *file, char __user *user_buf,
164 size_t count, loff_t *ppos)
165{
166 struct uart_hsu_port *up = file->private_data;
167 char *buf;
168 u32 len = 0;
169 ssize_t ret;
170
171 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
172 if (!buf)
173 return 0;
174
175 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
176 "MFD HSU port[%d] regs:\n", up->index);
177
178 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
179 "=================================\n");
180 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
181 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
182 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
183 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
184 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
185 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
186 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
187 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
188 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
189 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
190 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
191 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
192 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
193 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
194 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
195 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
196 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
197 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
198 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
199 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
200
201 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
202 kfree(buf);
203 return ret;
204}
205
206static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
207 size_t count, loff_t *ppos)
208{
209 struct hsu_dma_chan *chan = file->private_data;
210 char *buf;
211 u32 len = 0;
212 ssize_t ret;
213
214 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
215 if (!buf)
216 return 0;
217
218 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
219 "MFD HSU DMA channel [%d] regs:\n", chan->id);
220
221 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
222 "=================================\n");
223 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
224 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
225 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
226 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
227 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
228 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
229 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
230 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
231 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
232 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
233 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
234 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
235 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
236 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
237 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
238 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
239 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
240 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
241 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
242 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
243 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
244 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
245 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
246 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
247
248 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
249 kfree(buf);
250 return ret;
251}
252
253static const struct file_operations port_regs_ops = {
254 .owner = THIS_MODULE,
255 .open = hsu_show_regs_open,
256 .read = port_show_regs,
257};
258
259static const struct file_operations dma_regs_ops = {
260 .owner = THIS_MODULE,
261 .open = hsu_show_regs_open,
262 .read = dma_show_regs,
263};
264
265static int hsu_debugfs_init(struct hsu_port *hsu)
266{
267 int i;
268 char name[32];
269
270 hsu->debugfs = debugfs_create_dir("hsu", NULL);
271 if (!hsu->debugfs)
272 return -ENOMEM;
273
274 for (i = 0; i < 3; i++) {
275 snprintf(name, sizeof(name), "port_%d_regs", i);
276 debugfs_create_file(name, S_IFREG | S_IRUGO,
277 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
278 }
279
280 for (i = 0; i < 6; i++) {
281 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
282 debugfs_create_file(name, S_IFREG | S_IRUGO,
283 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
284 }
285
286 return 0;
287}
288
289static void hsu_debugfs_remove(struct hsu_port *hsu)
290{
291 if (hsu->debugfs)
292 debugfs_remove_recursive(hsu->debugfs);
293}
294
295#else
296static inline int hsu_debugfs_init(struct hsu_port *hsu)
297{
298 return 0;
299}
300
301static inline void hsu_debugfs_remove(struct hsu_port *hsu)
302{
303}
304#endif /* CONFIG_DEBUG_FS */
305
306static void serial_hsu_enable_ms(struct uart_port *port)
307{
308 struct uart_hsu_port *up =
309 container_of(port, struct uart_hsu_port, port);
310
311 up->ier |= UART_IER_MSI;
312 serial_out(up, UART_IER, up->ier);
313}
314
315void hsu_dma_tx(struct uart_hsu_port *up)
316{
317 struct circ_buf *xmit = &up->port.state->xmit;
318 struct hsu_dma_buffer *dbuf = &up->txbuf;
319 int count;
320
321 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
322 if (up->dma_tx_on)
323 return;
324
325 /* Update the circ buf info */
326 xmit->tail += dbuf->ofs;
327 xmit->tail &= UART_XMIT_SIZE - 1;
328
329 up->port.icount.tx += dbuf->ofs;
330 dbuf->ofs = 0;
331
332 /* Disable the channel */
333 chan_writel(up->txc, HSU_CH_CR, 0x0);
334
335 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
336 dma_sync_single_for_device(up->port.dev,
337 dbuf->dma_addr,
338 dbuf->dma_size,
339 DMA_TO_DEVICE);
340
341 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
342 dbuf->ofs = count;
343
344 /* Reprogram the channel */
345 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
346 chan_writel(up->txc, HSU_CH_D0TSR, count);
347
348 /* Reenable the channel */
349 chan_writel(up->txc, HSU_CH_DCR, 0x1
350 | (0x1 << 8)
351 | (0x1 << 16)
352 | (0x1 << 24));
353
354 WARN(chan_readl(up->txc, HSU_CH_CR) & 0x1,
355 "TX channel has already be started!!\n");
356 up->dma_tx_on = 1;
357 chan_writel(up->txc, HSU_CH_CR, 0x1);
358 }
359
360 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
361 uart_write_wakeup(&up->port);
362}
363
364/* The buffer is already cache coherent */
365void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
366{
367 /* Need start RX dma channel here */
368 dbuf->ofs = 0;
369
370 chan_writel(rxc, HSU_CH_BSR, 32);
371 chan_writel(rxc, HSU_CH_MOTSR, 4);
372
373 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
374 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
375 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
376 | (0x1 << 16)
377 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
378 );
379 chan_writel(rxc, HSU_CH_CR, 0x3);
380}
381
382/* Protected by spin_lock_irqsave(port->lock) */
383static void serial_hsu_start_tx(struct uart_port *port)
384{
385 struct uart_hsu_port *up =
386 container_of(port, struct uart_hsu_port, port);
387
388 if (up->use_dma) {
389 hsu_dma_tx(up);
390 } else if (!(up->ier & UART_IER_THRI)) {
391 up->ier |= UART_IER_THRI;
392 serial_out(up, UART_IER, up->ier);
393 }
394}
395
396static void serial_hsu_stop_tx(struct uart_port *port)
397{
398 struct uart_hsu_port *up =
399 container_of(port, struct uart_hsu_port, port);
400 struct hsu_dma_chan *txc = up->txc;
401
402 if (up->use_dma)
403 chan_writel(txc, HSU_CH_CR, 0x0);
404 else if (up->ier & UART_IER_THRI) {
405 up->ier &= ~UART_IER_THRI;
406 serial_out(up, UART_IER, up->ier);
407 }
408}
409
410/* This is always called in spinlock protected mode, so
411 * modify timeout timer is safe here */
412void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
413{
414 struct hsu_dma_buffer *dbuf = &up->rxbuf;
415 struct hsu_dma_chan *chan = up->rxc;
416 struct uart_port *port = &up->port;
417 struct tty_struct *tty = port->state->port.tty;
418 int count;
419
420 if (!tty)
421 return;
422
423 /*
424 * first need to know how many is already transferred,
425 * then check if its a timeout DMA irq, and return
426 * the trail bytes out, push them up and reenable the
427 * channel, better to use 2 descriptors at the same time
428 */
429
430 /* timeout IRQ, need wait some time, see Errata 2 */
431 if (int_sts & 0xf00)
432 udelay(2);
433
434 /* Stop the channel */
435 chan_writel(chan, HSU_CH_CR, 0x0);
436
437 /* We can use 2 ways to calc the actual transfer len */
438 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
439
440 if (!count)
441 return;
442
443 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
444 dbuf->dma_size, DMA_FROM_DEVICE);
445
446 /*
447 * head will only wrap around when we recycle
448 * the DMA buffer, and when that happens, we
449 * explicitly set tail to 0. So head will
450 * always be greater than tail.
451 */
452 tty_insert_flip_string(tty, dbuf->buf, count);
453 port->icount.rx += count;
454
455 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
456 dbuf->dma_size, DMA_FROM_DEVICE);
457
458 /* Reprogram the channel */
459 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
460 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
461 chan_writel(chan, HSU_CH_DCR, 0x1
462 | (0x1 << 8)
463 | (0x1 << 16)
464 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
465 );
466 chan_writel(chan, HSU_CH_CR, 0x3);
467
468 tty_flip_buffer_push(tty);
469}
470
471static void serial_hsu_stop_rx(struct uart_port *port)
472{
473 struct uart_hsu_port *up =
474 container_of(port, struct uart_hsu_port, port);
475 struct hsu_dma_chan *chan = up->rxc;
476
477 if (up->use_dma)
478 chan_writel(chan, HSU_CH_CR, 0x2);
479 else {
480 up->ier &= ~UART_IER_RLSI;
481 up->port.read_status_mask &= ~UART_LSR_DR;
482 serial_out(up, UART_IER, up->ier);
483 }
484}
485
486/*
487 * if there is error flag, should we just reset the FIFO or keeps
488 * working on it
489 */
490static inline void receive_chars(struct uart_hsu_port *up, int *status)
491{
492 struct tty_struct *tty = up->port.state->port.tty;
493 unsigned int ch, flag;
494 unsigned int max_count = 256;
495
496 if (!tty)
497 return;
498
499 do {
500 ch = serial_in(up, UART_RX);
501 flag = TTY_NORMAL;
502 up->port.icount.rx++;
503
504 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
505 UART_LSR_FE | UART_LSR_OE))) {
506
507 dev_warn(up->dev, "We really rush into ERR/BI case"
508 "status = 0x%02x", *status);
509 /* For statistics only */
510 if (*status & UART_LSR_BI) {
511 *status &= ~(UART_LSR_FE | UART_LSR_PE);
512 up->port.icount.brk++;
513 /*
514 * We do the SysRQ and SAK checking
515 * here because otherwise the break
516 * may get masked by ignore_status_mask
517 * or read_status_mask.
518 */
519 if (uart_handle_break(&up->port))
520 goto ignore_char;
521 } else if (*status & UART_LSR_PE)
522 up->port.icount.parity++;
523 else if (*status & UART_LSR_FE)
524 up->port.icount.frame++;
525 if (*status & UART_LSR_OE)
526 up->port.icount.overrun++;
527
528 /* Mask off conditions which should be ignored. */
529 *status &= up->port.read_status_mask;
530
531#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
532 if (up->port.cons &&
533 up->port.cons->index == up->port.line) {
534 /* Recover the break flag from console xmit */
535 *status |= up->lsr_break_flag;
536 up->lsr_break_flag = 0;
537 }
538#endif
539 if (*status & UART_LSR_BI) {
540 flag = TTY_BREAK;
541 } else if (*status & UART_LSR_PE)
542 flag = TTY_PARITY;
543 else if (*status & UART_LSR_FE)
544 flag = TTY_FRAME;
545 }
546
547 if (uart_handle_sysrq_char(&up->port, ch))
548 goto ignore_char;
549
550 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
551 ignore_char:
552 *status = serial_in(up, UART_LSR);
553 } while ((*status & UART_LSR_DR) && max_count--);
554 tty_flip_buffer_push(tty);
555}
556
557static void transmit_chars(struct uart_hsu_port *up)
558{
559 struct circ_buf *xmit = &up->port.state->xmit;
560 int count;
561 int i = 0; /* for debug use */
562
563 if (up->port.x_char) {
564 serial_out(up, UART_TX, up->port.x_char);
565 up->port.icount.tx++;
566 up->port.x_char = 0;
567 return;
568 }
569 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
570 serial_hsu_stop_tx(&up->port);
571 return;
572 }
573
574#ifndef MFD_HSU_A0_STEPPING
575 count = up->port.fifosize / 2;
576#else
577 /*
578 * A0 only supports fully empty IRQ, and the first char written
579 * into it won't clear the EMPT bit, so we may need be cautious
580 * by useing a shorter buffer
581 */
582 /* count = up->port.fifosize; */
583 count = up->port.fifosize - 4;
584#endif
585 do {
586 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
587 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
588 i++;
589
590 up->port.icount.tx++;
591 if (uart_circ_empty(xmit))
592 break;
593 } while (--count > 0);
594
595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
596 uart_write_wakeup(&up->port);
597
598 if (uart_circ_empty(xmit))
599 serial_hsu_stop_tx(&up->port);
600}
601
602static inline void check_modem_status(struct uart_hsu_port *up)
603{
604 int status;
605
606 status = serial_in(up, UART_MSR);
607
608 if ((status & UART_MSR_ANY_DELTA) == 0)
609 return;
610
611 if (status & UART_MSR_TERI)
612 up->port.icount.rng++;
613 if (status & UART_MSR_DDSR)
614 up->port.icount.dsr++;
615 /* We may only get DDCD when HW init and reset */
616 if (status & UART_MSR_DDCD)
617 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
618 /* will start/stop_tx accordingly */
619 if (status & UART_MSR_DCTS)
620 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
621
622 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
623}
624
625/*
626 * This handles the interrupt from one port.
627 */
628static irqreturn_t port_irq(int irq, void *dev_id)
629{
630 struct uart_hsu_port *up = dev_id;
631 unsigned int iir, lsr;
632 unsigned long flags;
633
634 if (unlikely(!up->running))
635 return IRQ_NONE;
636
637 if (up->use_dma) {
638 lsr = serial_in(up, UART_LSR);
639 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
640 UART_LSR_FE | UART_LSR_OE)))
641 dev_warn(up->dev,
642 "Got lsr irq while using DMA, lsr = 0x%2x\n",
643 lsr);
644 check_modem_status(up);
645 return IRQ_HANDLED;
646 }
647
648 spin_lock_irqsave(&up->port.lock, flags);
649 iir = serial_in(up, UART_IIR);
650 if (iir & UART_IIR_NO_INT) {
651 spin_unlock_irqrestore(&up->port.lock, flags);
652 return IRQ_NONE;
653 }
654
655 lsr = serial_in(up, UART_LSR);
656
657 if (lsr & UART_LSR_DR)
658 receive_chars(up, &lsr);
659
660 /* lsr will be renewed during the receive_chars */
661 if (lsr & UART_LSR_THRE)
662 transmit_chars(up);
663
664 spin_unlock_irqrestore(&up->port.lock, flags);
665 return IRQ_HANDLED;
666}
667
668static inline void dma_chan_irq(struct hsu_dma_chan *chan)
669{
670 struct uart_hsu_port *up = chan->uport;
671 unsigned long flags;
672 u32 int_sts;
673
674 spin_lock_irqsave(&up->port.lock, flags);
675
676 if (!up->use_dma || !up->running)
677 goto exit;
678
679 /*
680 * No matter what situation, need read clear the IRQ status
681 * There is a bug, see Errata 5, HSD 2900918
682 */
683 int_sts = chan_readl(chan, HSU_CH_SR);
684
685 /* Rx channel */
686 if (chan->dirt == DMA_FROM_DEVICE)
687 hsu_dma_rx(up, int_sts);
688
689 /* Tx channel */
690 if (chan->dirt == DMA_TO_DEVICE) {
691 /* dma for irq should be done */
692 chan_writel(chan, HSU_CH_CR, 0x0);
693 up->dma_tx_on = 0;
694 hsu_dma_tx(up);
695 }
696
697exit:
698 spin_unlock_irqrestore(&up->port.lock, flags);
699 return;
700}
701
702static irqreturn_t dma_irq(int irq, void *dev_id)
703{
704 struct hsu_port *hsu = dev_id;
705 u32 int_sts, i;
706
707 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
708
709 /* Currently we only have 6 channels may be used */
710 for (i = 0; i < 6; i++) {
711 if (int_sts & 0x1)
712 dma_chan_irq(&hsu->chans[i]);
713 int_sts >>= 1;
714 }
715
716 return IRQ_HANDLED;
717}
718
719static unsigned int serial_hsu_tx_empty(struct uart_port *port)
720{
721 struct uart_hsu_port *up =
722 container_of(port, struct uart_hsu_port, port);
723 unsigned long flags;
724 unsigned int ret;
725
726 spin_lock_irqsave(&up->port.lock, flags);
727 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
728 spin_unlock_irqrestore(&up->port.lock, flags);
729
730 return ret;
731}
732
733static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
734{
735 struct uart_hsu_port *up =
736 container_of(port, struct uart_hsu_port, port);
737 unsigned char status;
738 unsigned int ret;
739
740 status = serial_in(up, UART_MSR);
741
742 ret = 0;
743 if (status & UART_MSR_DCD)
744 ret |= TIOCM_CAR;
745 if (status & UART_MSR_RI)
746 ret |= TIOCM_RNG;
747 if (status & UART_MSR_DSR)
748 ret |= TIOCM_DSR;
749 if (status & UART_MSR_CTS)
750 ret |= TIOCM_CTS;
751 return ret;
752}
753
754static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
755{
756 struct uart_hsu_port *up =
757 container_of(port, struct uart_hsu_port, port);
758 unsigned char mcr = 0;
759
760 if (mctrl & TIOCM_RTS)
761 mcr |= UART_MCR_RTS;
762 if (mctrl & TIOCM_DTR)
763 mcr |= UART_MCR_DTR;
764 if (mctrl & TIOCM_OUT1)
765 mcr |= UART_MCR_OUT1;
766 if (mctrl & TIOCM_OUT2)
767 mcr |= UART_MCR_OUT2;
768 if (mctrl & TIOCM_LOOP)
769 mcr |= UART_MCR_LOOP;
770
771 mcr |= up->mcr;
772
773 serial_out(up, UART_MCR, mcr);
774}
775
776static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
777{
778 struct uart_hsu_port *up =
779 container_of(port, struct uart_hsu_port, port);
780 unsigned long flags;
781
782 spin_lock_irqsave(&up->port.lock, flags);
783 if (break_state == -1)
784 up->lcr |= UART_LCR_SBC;
785 else
786 up->lcr &= ~UART_LCR_SBC;
787 serial_out(up, UART_LCR, up->lcr);
788 spin_unlock_irqrestore(&up->port.lock, flags);
789}
790
791/*
792 * What special to do:
793 * 1. chose the 64B fifo mode
794 * 2. make sure not to select half empty mode for A0 stepping
795 * 3. start dma or pio depends on configuration
796 * 4. we only allocate dma memory when needed
797 */
798static int serial_hsu_startup(struct uart_port *port)
799{
800 struct uart_hsu_port *up =
801 container_of(port, struct uart_hsu_port, port);
802 unsigned long flags;
803
804 /*
805 * Clear the FIFO buffers and disable them.
806 * (they will be reenabled in set_termios())
807 */
808 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
809 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
810 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
811 serial_out(up, UART_FCR, 0);
812
813 /* Clear the interrupt registers. */
814 (void) serial_in(up, UART_LSR);
815 (void) serial_in(up, UART_RX);
816 (void) serial_in(up, UART_IIR);
817 (void) serial_in(up, UART_MSR);
818
819 /* Now, initialize the UART, default is 8n1 */
820 serial_out(up, UART_LCR, UART_LCR_WLEN8);
821
822 spin_lock_irqsave(&up->port.lock, flags);
823
824 up->port.mctrl |= TIOCM_OUT2;
825 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
826
827 /*
828 * Finally, enable interrupts. Note: Modem status interrupts
829 * are set via set_termios(), which will be occurring imminently
830 * anyway, so we don't enable them here.
831 */
832 if (!up->use_dma)
833 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
834 else
835 up->ier = 0;
836 serial_out(up, UART_IER, up->ier);
837
838 spin_unlock_irqrestore(&up->port.lock, flags);
839
840 /* DMA init */
841 /* When use DMA, TX/RX's FIFO and IRQ should be disabled */
842 if (up->use_dma) {
843 struct hsu_dma_buffer *dbuf;
844 struct circ_buf *xmit = &port->state->xmit;
845
846 up->dma_tx_on = 0;
847
848 /* First allocate the RX buffer */
849 dbuf = &up->rxbuf;
850 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
851 if (!dbuf->buf) {
852 up->use_dma = 0;
853 goto exit;
854 }
855 dbuf->dma_addr = dma_map_single(port->dev,
856 dbuf->buf,
857 HSU_DMA_BUF_SIZE,
858 DMA_FROM_DEVICE);
859 dbuf->dma_size = HSU_DMA_BUF_SIZE;
860
861 /* Start the RX channel right now */
862 hsu_dma_start_rx_chan(up->rxc, dbuf);
863
864 /* Next init the TX DMA */
865 dbuf = &up->txbuf;
866 dbuf->buf = xmit->buf;
867 dbuf->dma_addr = dma_map_single(port->dev,
868 dbuf->buf,
869 UART_XMIT_SIZE,
870 DMA_TO_DEVICE);
871 dbuf->dma_size = UART_XMIT_SIZE;
872
873 /* This should not be changed all around */
874 chan_writel(up->txc, HSU_CH_BSR, 32);
875 chan_writel(up->txc, HSU_CH_MOTSR, 4);
876 dbuf->ofs = 0;
877 }
878
879exit:
880 /* And clear the interrupt registers again for luck. */
881 (void) serial_in(up, UART_LSR);
882 (void) serial_in(up, UART_RX);
883 (void) serial_in(up, UART_IIR);
884 (void) serial_in(up, UART_MSR);
885
886 up->running = 1;
887 return 0;
888}
889
890static void serial_hsu_shutdown(struct uart_port *port)
891{
892 struct uart_hsu_port *up =
893 container_of(port, struct uart_hsu_port, port);
894 unsigned long flags;
895
896 /* Disable interrupts from this port */
897 up->ier = 0;
898 serial_out(up, UART_IER, 0);
899 up->running = 0;
900
901 spin_lock_irqsave(&up->port.lock, flags);
902 up->port.mctrl &= ~TIOCM_OUT2;
903 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
904 spin_unlock_irqrestore(&up->port.lock, flags);
905
906 /* Disable break condition and FIFOs */
907 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
908 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
909 UART_FCR_CLEAR_RCVR |
910 UART_FCR_CLEAR_XMIT);
911 serial_out(up, UART_FCR, 0);
912}
913
914static void
915serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
916 struct ktermios *old)
917{
918 struct uart_hsu_port *up =
919 container_of(port, struct uart_hsu_port, port);
920 struct tty_struct *tty = port->state->port.tty;
921 unsigned char cval, fcr = 0;
922 unsigned long flags;
923 unsigned int baud, quot;
924 u32 mul = 0x3600;
925 u32 ps = 0x10;
926
927 switch (termios->c_cflag & CSIZE) {
928 case CS5:
929 cval = UART_LCR_WLEN5;
930 break;
931 case CS6:
932 cval = UART_LCR_WLEN6;
933 break;
934 case CS7:
935 cval = UART_LCR_WLEN7;
936 break;
937 default:
938 case CS8:
939 cval = UART_LCR_WLEN8;
940 break;
941 }
942
943 /* CMSPAR isn't supported by this driver */
944 if (tty)
945 tty->termios->c_cflag &= ~CMSPAR;
946
947 if (termios->c_cflag & CSTOPB)
948 cval |= UART_LCR_STOP;
949 if (termios->c_cflag & PARENB)
950 cval |= UART_LCR_PARITY;
951 if (!(termios->c_cflag & PARODD))
952 cval |= UART_LCR_EPAR;
953
954 /*
955 * For those basic low baud rate we can get the direct
956 * scalar from 2746800, like 115200 = 2746800/24, for those
957 * higher baud rate, we have to handle them case by case,
958 * but DIV reg is never touched as its default value 0x3d09
959 */
960 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
961 quot = uart_get_divisor(port, baud);
962
963 switch (baud) {
964 case 3500000:
965 mul = 0x3345;
966 ps = 0xC;
967 quot = 1;
968 break;
969 case 2500000:
970 mul = 0x2710;
971 ps = 0x10;
972 quot = 1;
973 break;
974 case 18432000:
975 mul = 0x2400;
976 ps = 0x10;
977 quot = 1;
978 break;
979 case 1500000:
980 mul = 0x1D4C;
981 ps = 0xc;
982 quot = 1;
983 break;
984 default:
985 ;
986 }
987
988 if ((up->port.uartclk / quot) < (2400 * 16))
989 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
990 else if ((up->port.uartclk / quot) < (230400 * 16))
991 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
992 else
993 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
994
995 fcr |= UART_FCR_HSU_64B_FIFO;
996#ifdef MFD_HSU_A0_STEPPING
997 /* A0 doesn't support half empty IRQ */
998 fcr |= UART_FCR_FULL_EMPT_TXI;
999#endif
1000
1001 /*
1002 * Ok, we're now changing the port state. Do it with
1003 * interrupts disabled.
1004 */
1005 spin_lock_irqsave(&up->port.lock, flags);
1006
1007 /* Update the per-port timeout */
1008 uart_update_timeout(port, termios->c_cflag, baud);
1009
1010 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1011 if (termios->c_iflag & INPCK)
1012 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1013 if (termios->c_iflag & (BRKINT | PARMRK))
1014 up->port.read_status_mask |= UART_LSR_BI;
1015
1016 /* Characters to ignore */
1017 up->port.ignore_status_mask = 0;
1018 if (termios->c_iflag & IGNPAR)
1019 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1020 if (termios->c_iflag & IGNBRK) {
1021 up->port.ignore_status_mask |= UART_LSR_BI;
1022 /*
1023 * If we're ignoring parity and break indicators,
1024 * ignore overruns too (for real raw support).
1025 */
1026 if (termios->c_iflag & IGNPAR)
1027 up->port.ignore_status_mask |= UART_LSR_OE;
1028 }
1029
1030 /* Ignore all characters if CREAD is not set */
1031 if ((termios->c_cflag & CREAD) == 0)
1032 up->port.ignore_status_mask |= UART_LSR_DR;
1033
1034 /*
1035 * CTS flow control flag and modem status interrupts, disable
1036 * MSI by default
1037 */
1038 up->ier &= ~UART_IER_MSI;
1039 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1040 up->ier |= UART_IER_MSI;
1041
1042 serial_out(up, UART_IER, up->ier);
1043
1044 if (termios->c_cflag & CRTSCTS)
1045 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1046 else
1047 up->mcr &= ~UART_MCR_AFE;
1048
1049 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1050 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1051 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1052 serial_out(up, UART_LCR, cval); /* reset DLAB */
1053 serial_out(up, UART_MUL, mul); /* set MUL */
1054 serial_out(up, UART_PS, ps); /* set PS */
1055 up->lcr = cval; /* Save LCR */
1056 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1057 serial_out(up, UART_FCR, fcr);
1058 spin_unlock_irqrestore(&up->port.lock, flags);
1059}
1060
1061static void
1062serial_hsu_pm(struct uart_port *port, unsigned int state,
1063 unsigned int oldstate)
1064{
1065}
1066
1067static void serial_hsu_release_port(struct uart_port *port)
1068{
1069}
1070
1071static int serial_hsu_request_port(struct uart_port *port)
1072{
1073 return 0;
1074}
1075
1076static void serial_hsu_config_port(struct uart_port *port, int flags)
1077{
1078#if 0
1079 struct uart_hsu_port *up =
1080 container_of(port, struct uart_hsu_port, port);
1081 up->port.type = PORT_MFD;
1082#endif
1083}
1084
1085static int
1086serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1087{
1088 /* We don't want the core code to modify any port params */
1089 return -EINVAL;
1090}
1091
1092static const char *
1093serial_hsu_type(struct uart_port *port)
1094{
1095 struct uart_hsu_port *up =
1096 container_of(port, struct uart_hsu_port, port);
1097 return up->name;
1098}
1099
1100/* Mainly for uart console use */
1101static struct uart_hsu_port *serial_hsu_ports[3];
1102static struct uart_driver serial_hsu_reg;
1103
1104#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1105
1106#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1107
1108/* Wait for transmitter & holding register to empty */
1109static inline void wait_for_xmitr(struct uart_hsu_port *up)
1110{
1111 unsigned int status, tmout = 1000;
1112
1113 /* Wait up to 1ms for the character to be sent. */
1114 do {
1115 status = serial_in(up, UART_LSR);
1116
1117 if (status & UART_LSR_BI)
1118 up->lsr_break_flag = UART_LSR_BI;
1119
1120 if (--tmout == 0)
1121 break;
1122 udelay(1);
1123 } while (!(status & BOTH_EMPTY));
1124
1125 /* Wait up to 1s for flow control if necessary */
1126 if (up->port.flags & UPF_CONS_FLOW) {
1127 tmout = 1000000;
1128 while (--tmout &&
1129 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1130 udelay(1);
1131 }
1132}
1133
1134static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1135{
1136 struct uart_hsu_port *up =
1137 container_of(port, struct uart_hsu_port, port);
1138
1139 wait_for_xmitr(up);
1140 serial_out(up, UART_TX, ch);
1141}
1142
1143/*
1144 * Print a string to the serial port trying not to disturb
1145 * any possible real use of the port...
1146 *
1147 * The console_lock must be held when we get here.
1148 */
1149static void
1150serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1151{
1152 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1153 unsigned long flags;
1154 unsigned int ier;
1155 int locked = 1;
1156
1157 local_irq_save(flags);
1158 if (up->port.sysrq)
1159 locked = 0;
1160 else if (oops_in_progress) {
1161 locked = spin_trylock(&up->port.lock);
1162 } else
1163 spin_lock(&up->port.lock);
1164
1165 /* First save the IER then disable the interrupts */
1166 ier = serial_in(up, UART_IER);
1167 serial_out(up, UART_IER, 0);
1168
1169 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1170
1171 /*
1172 * Finally, wait for transmitter to become empty
1173 * and restore the IER
1174 */
1175 wait_for_xmitr(up);
1176 serial_out(up, UART_IER, ier);
1177
1178 if (locked)
1179 spin_unlock(&up->port.lock);
1180 local_irq_restore(flags);
1181}
1182
1183static struct console serial_hsu_console;
1184
1185static int __init
1186serial_hsu_console_setup(struct console *co, char *options)
1187{
1188 struct uart_hsu_port *up;
1189 int baud = 115200;
1190 int bits = 8;
1191 int parity = 'n';
1192 int flow = 'n';
1193 int ret;
1194
1195 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1196 co->index = 0;
1197 up = serial_hsu_ports[co->index];
1198 if (!up)
1199 return -ENODEV;
1200
1201 if (options)
1202 uart_parse_options(options, &baud, &parity, &bits, &flow);
1203
1204 ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1205
1206 return ret;
1207}
1208
1209static struct console serial_hsu_console = {
1210 .name = "ttyMFD",
1211 .write = serial_hsu_console_write,
1212 .device = uart_console_device,
1213 .setup = serial_hsu_console_setup,
1214 .flags = CON_PRINTBUFFER,
1215 .index = 2,
1216 .data = &serial_hsu_reg,
1217};
1218#endif
1219
1220struct uart_ops serial_hsu_pops = {
1221 .tx_empty = serial_hsu_tx_empty,
1222 .set_mctrl = serial_hsu_set_mctrl,
1223 .get_mctrl = serial_hsu_get_mctrl,
1224 .stop_tx = serial_hsu_stop_tx,
1225 .start_tx = serial_hsu_start_tx,
1226 .stop_rx = serial_hsu_stop_rx,
1227 .enable_ms = serial_hsu_enable_ms,
1228 .break_ctl = serial_hsu_break_ctl,
1229 .startup = serial_hsu_startup,
1230 .shutdown = serial_hsu_shutdown,
1231 .set_termios = serial_hsu_set_termios,
1232 .pm = serial_hsu_pm,
1233 .type = serial_hsu_type,
1234 .release_port = serial_hsu_release_port,
1235 .request_port = serial_hsu_request_port,
1236 .config_port = serial_hsu_config_port,
1237 .verify_port = serial_hsu_verify_port,
1238};
1239
1240static struct uart_driver serial_hsu_reg = {
1241 .owner = THIS_MODULE,
1242 .driver_name = "MFD serial",
1243 .dev_name = "ttyMFD",
1244 .major = TTY_MAJOR,
1245 .minor = 128,
1246 .nr = 3,
1247};
1248
1249#ifdef CONFIG_PM
1250static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1251{
1252 struct uart_hsu_port *up;
1253
1254 up = pci_get_drvdata(pdev);
1255 if (!up)
1256 return 0;
1257
1258 uart_suspend_port(&serial_hsu_reg, &up->port);
1259
1260 return 0;
1261}
1262
1263static int serial_hsu_resume(struct pci_dev *pdev)
1264{
1265 struct uart_hsu_port *up;
1266
1267 up = pci_get_drvdata(pdev);
1268 if (!up)
1269 return 0;
1270 uart_resume_port(&serial_hsu_reg, &up->port);
1271 return 0;
1272}
1273#else
1274#define serial_hsu_suspend NULL
1275#define serial_hsu_resume NULL
1276#endif
1277
1278/* temp global pointer before we settle down on using one or four PCI dev */
1279static struct hsu_port *phsu;
1280
1281static int serial_hsu_probe(struct pci_dev *pdev,
1282 const struct pci_device_id *ent)
1283{
1284 struct uart_hsu_port *uport;
1285 int index, ret;
1286
1287 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1288 pdev->vendor, pdev->device);
1289
1290 switch (pdev->device) {
1291 case 0x081B:
1292 index = 0;
1293 break;
1294 case 0x081C:
1295 index = 1;
1296 break;
1297 case 0x081D:
1298 index = 2;
1299 break;
1300 case 0x081E:
1301 /* internal DMA controller */
1302 index = 3;
1303 break;
1304 default:
1305 dev_err(&pdev->dev, "HSU: out of index!");
1306 return -ENODEV;
1307 }
1308
1309 ret = pci_enable_device(pdev);
1310 if (ret)
1311 return ret;
1312
1313 if (index == 3) {
1314 /* DMA controller */
1315 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1316 if (ret) {
1317 dev_err(&pdev->dev, "can not get IRQ\n");
1318 goto err_disable;
1319 }
1320 pci_set_drvdata(pdev, phsu);
1321 } else {
1322 /* UART port 0~2 */
1323 uport = &phsu->port[index];
1324 uport->port.irq = pdev->irq;
1325 uport->port.dev = &pdev->dev;
1326 uport->dev = &pdev->dev;
1327
1328 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1329 if (ret) {
1330 dev_err(&pdev->dev, "can not get IRQ\n");
1331 goto err_disable;
1332 }
1333 uart_add_one_port(&serial_hsu_reg, &uport->port);
1334
1335#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1336 if (index == 2) {
1337 register_console(&serial_hsu_console);
1338 uport->port.cons = &serial_hsu_console;
1339 }
1340#endif
1341 pci_set_drvdata(pdev, uport);
1342 }
1343
1344 return 0;
1345
1346err_disable:
1347 pci_disable_device(pdev);
1348 return ret;
1349}
1350
1351static void hsu_global_init(void)
1352{
1353 struct hsu_port *hsu;
1354 struct uart_hsu_port *uport;
1355 struct hsu_dma_chan *dchan;
1356 int i, ret;
1357
1358 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1359 if (!hsu)
1360 return;
1361
1362 /* Get basic io resource and map it */
1363 hsu->paddr = 0xffa28000;
1364 hsu->iolen = 0x1000;
1365
1366 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1367 pr_warning("HSU: error in request mem region\n");
1368
1369 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1370 if (!hsu->reg) {
1371 pr_err("HSU: error in ioremap\n");
1372 ret = -ENOMEM;
1373 goto err_free_region;
1374 }
1375
1376 /* Initialise the 3 UART ports */
1377 uport = hsu->port;
1378 for (i = 0; i < 3; i++) {
1379 uport->port.type = PORT_MFD;
1380 uport->port.iotype = UPIO_MEM;
1381 uport->port.mapbase = (resource_size_t)hsu->paddr
1382 + HSU_PORT_REG_OFFSET
1383 + i * HSU_PORT_REG_LENGTH;
1384 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1385 + i * HSU_PORT_REG_LENGTH;
1386
1387 sprintf(uport->name, "hsu_port%d", i);
1388 uport->port.fifosize = 64;
1389 uport->port.ops = &serial_hsu_pops;
1390 uport->port.line = i;
1391 uport->port.flags = UPF_IOREMAP;
1392 /* make the maxim support rate to 2746800 bps */
1393 uport->port.uartclk = 115200 * 24 * 16;
1394
1395 uport->running = 0;
1396 uport->txc = &hsu->chans[i * 2];
1397 uport->rxc = &hsu->chans[i * 2 + 1];
1398
1399 serial_hsu_ports[i] = uport;
1400 uport->index = i;
1401 uport++;
1402 }
1403
1404 /* Initialise 6 dma channels */
1405 dchan = hsu->chans;
1406 for (i = 0; i < 6; i++) {
1407 dchan->id = i;
1408 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1409 dchan->uport = &hsu->port[i/2];
1410 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1411 i * HSU_DMA_CHANS_REG_LENGTH;
1412 dchan++;
1413 }
1414
1415 phsu = hsu;
1416
1417 hsu_debugfs_init(hsu);
1418 return;
1419
1420err_free_region:
1421 release_mem_region(hsu->paddr, hsu->iolen);
1422 kfree(hsu);
1423 return;
1424}
1425
1426static void serial_hsu_remove(struct pci_dev *pdev)
1427{
1428 struct hsu_port *hsu;
1429 int i;
1430
1431 hsu = pci_get_drvdata(pdev);
1432 if (!hsu)
1433 return;
1434
1435 for (i = 0; i < 3; i++)
1436 uart_remove_one_port(&serial_hsu_reg, &hsu->port[i].port);
1437
1438 pci_set_drvdata(pdev, NULL);
1439 free_irq(hsu->irq, hsu);
1440 pci_disable_device(pdev);
1441}
1442
1443/* First 3 are UART ports, and the 4th is the DMA */
1444static const struct pci_device_id pci_ids[] __devinitdata = {
1445 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1446 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1447 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1448 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1449 {},
1450};
1451
1452static struct pci_driver hsu_pci_driver = {
1453 .name = "HSU serial",
1454 .id_table = pci_ids,
1455 .probe = serial_hsu_probe,
1456 .remove = __devexit_p(serial_hsu_remove),
1457 .suspend = serial_hsu_suspend,
1458 .resume = serial_hsu_resume,
1459};
1460
1461static int __init hsu_pci_init(void)
1462{
1463 int ret;
1464
1465 hsu_global_init();
1466
1467 ret = uart_register_driver(&serial_hsu_reg);
1468 if (ret)
1469 return ret;
1470
1471 return pci_register_driver(&hsu_pci_driver);
1472}
1473
1474static void __exit hsu_pci_exit(void)
1475{
1476 pci_unregister_driver(&hsu_pci_driver);
1477 uart_unregister_driver(&serial_hsu_reg);
1478
1479 hsu_debugfs_remove(phsu);
1480
1481 kfree(phsu);
1482}
1483
1484module_init(hsu_pci_init);
1485module_exit(hsu_pci_exit);
1486
1487MODULE_LICENSE("GPL v2");
1488MODULE_ALIAS("platform:medfield-hsu");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 00:08:13 -0500