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-rw-r--r--drivers/serial/bfin_sport_uart.c841
1 files changed, 579 insertions, 262 deletions
diff --git a/drivers/serial/bfin_sport_uart.c b/drivers/serial/bfin_sport_uart.c
index 34b4ae0fe760..e95c524d9d18 100644
--- a/drivers/serial/bfin_sport_uart.c
+++ b/drivers/serial/bfin_sport_uart.c
@@ -1,134 +1,101 @@
1/* 1/*
2 * File: linux/drivers/serial/bfin_sport_uart.c 2 * Blackfin On-Chip Sport Emulated UART Driver
3 * 3 *
4 * Based on: drivers/serial/bfin_5xx.c by Aubrey Li. 4 * Copyright 2006-2009 Analog Devices Inc.
5 * Author: Roy Huang <roy.huang@analog.com>
6 * 5 *
7 * Created: Nov 22, 2006 6 * Enter bugs at http://blackfin.uclinux.org/
8 * Copyright: (c) 2006-2007 Analog Devices Inc.
9 * Description: this driver enable SPORTs on Blackfin emulate UART.
10 * 7 *
11 * This program is free software; you can redistribute it and/or modify 8 * Licensed under the GPL-2 or later.
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see the file COPYING, or write
23 * to the Free Software Foundation, Inc.,
24 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 */ 9 */
26 10
27/* 11/*
28 * This driver and the hardware supported are in term of EE-191 of ADI. 12 * This driver and the hardware supported are in term of EE-191 of ADI.
29 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf 13 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
30 * This application note describe how to implement a UART on a Sharc DSP, 14 * This application note describe how to implement a UART on a Sharc DSP,
31 * but this driver is implemented on Blackfin Processor. 15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
32 */ 17 */
33 18
34/* After reset, there is a prelude of low level pulse when transmit data first 19/* #define DEBUG */
35 * time. No addtional pulse in following transmit.
36 * According to document:
37 * The SPORTs are ready to start transmitting or receiving data no later than
38 * three serial clock cycles after they are enabled in the SPORTx_TCR1 or
39 * SPORTx_RCR1 register. No serial clock cycles are lost from this point on.
40 * The first internal frame sync will occur one frame sync delay after the
41 * SPORTs are ready. External frame syncs can occur as soon as the SPORT is
42 * ready.
43 */
44 20
45/* Thanks to Axel Alatalo <axel@rubico.se> for fixing sport rx bug. Sometimes 21#define DRV_NAME "bfin-sport-uart"
46 * sport receives data incorrectly. The following is Axel's words. 22#define DEVICE_NAME "ttySS"
47 * As EE-191, sport rx samples 3 times of the UART baudrate and takes the 23#define pr_fmt(fmt) DRV_NAME ": " fmt
48 * middle smaple of every 3 samples as the data bit. For a 8-N-1 UART setting,
49 * 30 samples will be required for a byte. If transmitter sends a 1/3 bit short
50 * byte due to buadrate drift, then the 30th sample of a byte, this sample is
51 * also the third sample of the stop bit, will happens on the immediately
52 * following start bit which will be thrown away and missed. Thus since parts
53 * of the startbit will be missed and the receiver will begin to drift, the
54 * effect accumulates over time until synchronization is lost.
55 * If only require 2 samples of the stopbit (by sampling in total 29 samples),
56 * then a to short byte as in the case above will be tolerated. Then the 1/3
57 * early startbit will trigger a framesync since the last read is complete
58 * after only 2/3 stopbit and framesync is active during the last 1/3 looking
59 * for a possible early startbit. */
60
61//#define DEBUG
62 24
63#include <linux/module.h> 25#include <linux/module.h>
64#include <linux/ioport.h> 26#include <linux/ioport.h>
27#include <linux/io.h>
65#include <linux/init.h> 28#include <linux/init.h>
66#include <linux/console.h> 29#include <linux/console.h>
67#include <linux/sysrq.h> 30#include <linux/sysrq.h>
31#include <linux/slab.h>
68#include <linux/platform_device.h> 32#include <linux/platform_device.h>
69#include <linux/tty.h> 33#include <linux/tty.h>
70#include <linux/tty_flip.h> 34#include <linux/tty_flip.h>
71#include <linux/serial_core.h> 35#include <linux/serial_core.h>
72 36
37#include <asm/bfin_sport.h>
73#include <asm/delay.h> 38#include <asm/delay.h>
74#include <asm/portmux.h> 39#include <asm/portmux.h>
75 40
76#include "bfin_sport_uart.h" 41#include "bfin_sport_uart.h"
77 42
78unsigned short bfin_uart_pin_req_sport0[] =
79 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
80 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
81
82unsigned short bfin_uart_pin_req_sport1[] =
83 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
84 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
85
86#define DRV_NAME "bfin-sport-uart"
87
88struct sport_uart_port { 43struct sport_uart_port {
89 struct uart_port port; 44 struct uart_port port;
90 char *name;
91
92 int tx_irq;
93 int rx_irq;
94 int err_irq; 45 int err_irq;
46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51/* unsigned char parib; */
52#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55#endif
95}; 56};
96 57
97static void sport_uart_tx_chars(struct sport_uart_port *up); 58static int sport_uart_tx_chars(struct sport_uart_port *up);
98static void sport_stop_tx(struct uart_port *port); 59static void sport_stop_tx(struct uart_port *port);
99 60
100static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value) 61static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
101{ 62{
102 pr_debug("%s value:%x\n", __func__, value); 63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
103 /* Place a Start and Stop bit */ 64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
104 __asm__ __volatile__ ( 67 __asm__ __volatile__ (
105 "R2 = b#01111111100;" 68 "%[val] <<= 1;"
106 "R3 = b#10000000001;" 69 "%[val] = %[val] & %[mask1];"
107 "%0 <<= 2;" 70 "%[val] = %[val] | %[mask2];"
108 "%0 = %0 & R2;" 71 : [val]"+d"(value)
109 "%0 = %0 | R3;" 72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
110 : "=d"(value) 73 : "ASTAT"
111 : "d"(value)
112 : "ASTAT", "R2", "R3"
113 ); 74 );
114 pr_debug("%s value:%x\n", __func__, value); 75 pr_debug("%s value:%x\n", __func__, value);
115 76
116 SPORT_PUT_TX(up, value); 77 SPORT_PUT_TX(up, value);
117} 78}
118 79
119static inline unsigned int rx_one_byte(struct sport_uart_port *up) 80static inline unsigned char rx_one_byte(struct sport_uart_port *up)
120{ 81{
121 unsigned int value, extract; 82 unsigned int value;
83 unsigned char extract;
122 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp; 84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
123 85
124 value = SPORT_GET_RX32(up); 86 if ((up->csize + up->stopb) > 7)
125 pr_debug("%s value:%x\n", __func__, value); 87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
126 90
127 /* Extract 8 bits data */ 91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
93
94 /* Extract data */
128 __asm__ __volatile__ ( 95 __asm__ __volatile__ (
129 "%[extr] = 0;" 96 "%[extr] = 0;"
130 "%[mask1] = 0x1801(Z);" 97 "%[mask1] = %[rxmask];"
131 "%[mask2] = 0x0300(Z);" 98 "%[mask2] = 0x0200(Z);"
132 "%[shift] = 0;" 99 "%[shift] = 0;"
133 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];" 100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
134 ".Lloop_s:" 101 ".Lloop_s:"
@@ -138,9 +105,9 @@ static inline unsigned int rx_one_byte(struct sport_uart_port *up)
138 "%[mask1] = %[mask1] - %[mask2];" 105 "%[mask1] = %[mask1] - %[mask2];"
139 ".Lloop_e:" 106 ".Lloop_e:"
140 "%[shift] += 1;" 107 "%[shift] += 1;"
141 : [val]"=d"(value), [extr]"=d"(extract), [shift]"=d"(tmp_shift), [tmp]"=d"(tmp), 108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
142 [mask1]"=d"(tmp_mask1), [mask2]"=d"(tmp_mask2) 109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
143 : "d"(value), [lc]"a"(8) 110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
144 : "ASTAT", "LB0", "LC0", "LT0" 111 : "ASTAT", "LB0", "LC0", "LT0"
145 ); 112 );
146 113
@@ -148,29 +115,33 @@ static inline unsigned int rx_one_byte(struct sport_uart_port *up)
148 return extract; 115 return extract;
149} 116}
150 117
151static int sport_uart_setup(struct sport_uart_port *up, int sclk, int baud_rate) 118static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
152{ 119{
153 int tclkdiv, tfsdiv, rclkdiv; 120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
154 122
155 /* Set TCR1 and TCR2 */ 123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
156 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK)); 124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
157 SPORT_PUT_TCR2(up, 10); 125 SPORT_PUT_TCR2(up, size + 1);
158 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up)); 126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
159 127
160 /* Set RCR1 and RCR2 */ 128 /* Set RCR1 and RCR2 */
161 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK)); 129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
162 SPORT_PUT_RCR2(up, 28); 130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
163 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up)); 131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
164 132
165 tclkdiv = sclk/(2 * baud_rate) - 1; 133 tclkdiv = sclk / (2 * baud_rate) - 1;
166 tfsdiv = 12; 134 /* The actual uart baud rate of devices vary between +/-2%. The sport
167 rclkdiv = sclk/(2 * baud_rate * 3) - 1; 135 * RX sample rate should be faster than the double of the worst case,
136 * otherwise, wrong data are received. So, set sport RX clock to be
137 * 3% faster.
138 */
139 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
168 SPORT_PUT_TCLKDIV(up, tclkdiv); 140 SPORT_PUT_TCLKDIV(up, tclkdiv);
169 SPORT_PUT_TFSDIV(up, tfsdiv);
170 SPORT_PUT_RCLKDIV(up, rclkdiv); 141 SPORT_PUT_RCLKDIV(up, rclkdiv);
171 SSYNC(); 142 SSYNC();
172 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, tfsdiv:%d, rclkdiv:%d\n", 143 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
173 __func__, sclk, baud_rate, tclkdiv, tfsdiv, rclkdiv); 144 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
174 145
175 return 0; 146 return 0;
176} 147}
@@ -178,26 +149,32 @@ static int sport_uart_setup(struct sport_uart_port *up, int sclk, int baud_rate)
178static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id) 149static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
179{ 150{
180 struct sport_uart_port *up = dev_id; 151 struct sport_uart_port *up = dev_id;
181 struct tty_struct *tty = up->port.info->port.tty; 152 struct tty_struct *tty = up->port.state->port.tty;
182 unsigned int ch; 153 unsigned int ch;
183 154
184 do { 155 spin_lock(&up->port.lock);
156
157 while (SPORT_GET_STAT(up) & RXNE) {
185 ch = rx_one_byte(up); 158 ch = rx_one_byte(up);
186 up->port.icount.rx++; 159 up->port.icount.rx++;
187 160
188 if (uart_handle_sysrq_char(&up->port, ch)) 161 if (!uart_handle_sysrq_char(&up->port, ch))
189 ;
190 else
191 tty_insert_flip_char(tty, ch, TTY_NORMAL); 162 tty_insert_flip_char(tty, ch, TTY_NORMAL);
192 } while (SPORT_GET_STAT(up) & RXNE); 163 }
193 tty_flip_buffer_push(tty); 164 tty_flip_buffer_push(tty);
194 165
166 spin_unlock(&up->port.lock);
167
195 return IRQ_HANDLED; 168 return IRQ_HANDLED;
196} 169}
197 170
198static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id) 171static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
199{ 172{
200 sport_uart_tx_chars(dev_id); 173 struct sport_uart_port *up = dev_id;
174
175 spin_lock(&up->port.lock);
176 sport_uart_tx_chars(up);
177 spin_unlock(&up->port.lock);
201 178
202 return IRQ_HANDLED; 179 return IRQ_HANDLED;
203} 180}
@@ -205,9 +182,11 @@ static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
205static irqreturn_t sport_uart_err_irq(int irq, void *dev_id) 182static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
206{ 183{
207 struct sport_uart_port *up = dev_id; 184 struct sport_uart_port *up = dev_id;
208 struct tty_struct *tty = up->port.info->port.tty; 185 struct tty_struct *tty = up->port.state->port.tty;
209 unsigned int stat = SPORT_GET_STAT(up); 186 unsigned int stat = SPORT_GET_STAT(up);
210 187
188 spin_lock(&up->port.lock);
189
211 /* Overflow in RX FIFO */ 190 /* Overflow in RX FIFO */
212 if (stat & ROVF) { 191 if (stat & ROVF) {
213 up->port.icount.overrun++; 192 up->port.icount.overrun++;
@@ -216,96 +195,153 @@ static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
216 } 195 }
217 /* These should not happen */ 196 /* These should not happen */
218 if (stat & (TOVF | TUVF | RUVF)) { 197 if (stat & (TOVF | TUVF | RUVF)) {
219 printk(KERN_ERR "SPORT Error:%s %s %s\n", 198 pr_err("SPORT Error:%s %s %s\n",
220 (stat & TOVF)?"TX overflow":"", 199 (stat & TOVF) ? "TX overflow" : "",
221 (stat & TUVF)?"TX underflow":"", 200 (stat & TUVF) ? "TX underflow" : "",
222 (stat & RUVF)?"RX underflow":""); 201 (stat & RUVF) ? "RX underflow" : "");
223 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); 202 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
224 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); 203 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
225 } 204 }
226 SSYNC(); 205 SSYNC();
227 206
207 spin_unlock(&up->port.lock);
228 return IRQ_HANDLED; 208 return IRQ_HANDLED;
229} 209}
230 210
211#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
212static unsigned int sport_get_mctrl(struct uart_port *port)
213{
214 struct sport_uart_port *up = (struct sport_uart_port *)port;
215 if (up->cts_pin < 0)
216 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
217
218 /* CTS PIN is negative assertive. */
219 if (SPORT_UART_GET_CTS(up))
220 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
221 else
222 return TIOCM_DSR | TIOCM_CAR;
223}
224
225static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
226{
227 struct sport_uart_port *up = (struct sport_uart_port *)port;
228 if (up->rts_pin < 0)
229 return;
230
231 /* RTS PIN is negative assertive. */
232 if (mctrl & TIOCM_RTS)
233 SPORT_UART_ENABLE_RTS(up);
234 else
235 SPORT_UART_DISABLE_RTS(up);
236}
237
238/*
239 * Handle any change of modem status signal.
240 */
241static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
242{
243 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
244 unsigned int status;
245
246 status = sport_get_mctrl(&up->port);
247 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
248
249 return IRQ_HANDLED;
250}
251#else
252static unsigned int sport_get_mctrl(struct uart_port *port)
253{
254 pr_debug("%s enter\n", __func__);
255 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
256}
257
258static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
259{
260 pr_debug("%s enter\n", __func__);
261}
262#endif
263
231/* Reqeust IRQ, Setup clock */ 264/* Reqeust IRQ, Setup clock */
232static int sport_startup(struct uart_port *port) 265static int sport_startup(struct uart_port *port)
233{ 266{
234 struct sport_uart_port *up = (struct sport_uart_port *)port; 267 struct sport_uart_port *up = (struct sport_uart_port *)port;
235 char buffer[20]; 268 int ret;
236 int retval;
237 269
238 pr_debug("%s enter\n", __func__); 270 pr_debug("%s enter\n", __func__);
239 memset(buffer, 20, '\0'); 271 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
240 snprintf(buffer, 20, "%s rx", up->name); 272 "SPORT_UART_RX", up);
241 retval = request_irq(up->rx_irq, sport_uart_rx_irq, IRQF_SAMPLE_RANDOM, buffer, up); 273 if (ret) {
242 if (retval) { 274 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
243 printk(KERN_ERR "Unable to request interrupt %s\n", buffer); 275 return ret;
244 return retval;
245 } 276 }
246 277
247 snprintf(buffer, 20, "%s tx", up->name); 278 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
248 retval = request_irq(up->tx_irq, sport_uart_tx_irq, IRQF_SAMPLE_RANDOM, buffer, up); 279 "SPORT_UART_TX", up);
249 if (retval) { 280 if (ret) {
250 printk(KERN_ERR "Unable to request interrupt %s\n", buffer); 281 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
251 goto fail1; 282 goto fail1;
252 } 283 }
253 284
254 snprintf(buffer, 20, "%s err", up->name); 285 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
255 retval = request_irq(up->err_irq, sport_uart_err_irq, IRQF_SAMPLE_RANDOM, buffer, up); 286 "SPORT_UART_STATUS", up);
256 if (retval) { 287 if (ret) {
257 printk(KERN_ERR "Unable to request interrupt %s\n", buffer); 288 dev_err(port->dev, "unable to request SPORT status interrupt\n");
258 goto fail2; 289 goto fail2;
259 } 290 }
260 291
261 if (port->line) { 292#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
262 if (peripheral_request_list(bfin_uart_pin_req_sport1, DRV_NAME)) 293 if (up->cts_pin >= 0) {
263 goto fail3; 294 if (request_irq(gpio_to_irq(up->cts_pin),
264 } else { 295 sport_mctrl_cts_int,
265 if (peripheral_request_list(bfin_uart_pin_req_sport0, DRV_NAME)) 296 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
266 goto fail3; 297 IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
298 up->cts_pin = -1;
299 dev_info(port->dev, "Unable to attach BlackFin UART \
300 over SPORT CTS interrupt. So, disable it.\n");
301 }
267 } 302 }
268 303 if (up->rts_pin >= 0)
269 sport_uart_setup(up, get_sclk(), port->uartclk); 304 gpio_direction_output(up->rts_pin, 0);
270 305#endif
271 /* Enable receive interrupt */
272 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) | RSPEN));
273 SSYNC();
274 306
275 return 0; 307 return 0;
308 fail2:
309 free_irq(up->port.irq+1, up);
310 fail1:
311 free_irq(up->port.irq, up);
276 312
277 313 return ret;
278fail3:
279 printk(KERN_ERR DRV_NAME
280 ": Requesting Peripherals failed\n");
281
282 free_irq(up->err_irq, up);
283fail2:
284 free_irq(up->tx_irq, up);
285fail1:
286 free_irq(up->rx_irq, up);
287
288 return retval;
289
290} 314}
291 315
292static void sport_uart_tx_chars(struct sport_uart_port *up) 316/*
317 * sport_uart_tx_chars
318 *
319 * ret 1 means need to enable sport.
320 * ret 0 means do nothing.
321 */
322static int sport_uart_tx_chars(struct sport_uart_port *up)
293{ 323{
294 struct circ_buf *xmit = &up->port.info->xmit; 324 struct circ_buf *xmit = &up->port.state->xmit;
295 325
296 if (SPORT_GET_STAT(up) & TXF) 326 if (SPORT_GET_STAT(up) & TXF)
297 return; 327 return 0;
298 328
299 if (up->port.x_char) { 329 if (up->port.x_char) {
300 tx_one_byte(up, up->port.x_char); 330 tx_one_byte(up, up->port.x_char);
301 up->port.icount.tx++; 331 up->port.icount.tx++;
302 up->port.x_char = 0; 332 up->port.x_char = 0;
303 return; 333 return 1;
304 } 334 }
305 335
306 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 336 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
307 sport_stop_tx(&up->port); 337 /* The waiting loop to stop SPORT TX from TX interrupt is
308 return; 338 * too long. This may block SPORT RX interrupts and cause
339 * RX FIFO overflow. So, do stop sport TX only after the last
340 * char in TX FIFO is moved into the shift register.
341 */
342 if (SPORT_GET_STAT(up) & TXHRE)
343 sport_stop_tx(&up->port);
344 return 0;
309 } 345 }
310 346
311 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) { 347 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
@@ -316,6 +352,8 @@ static void sport_uart_tx_chars(struct sport_uart_port *up)
316 352
317 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 353 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
318 uart_write_wakeup(&up->port); 354 uart_write_wakeup(&up->port);
355
356 return 1;
319} 357}
320 358
321static unsigned int sport_tx_empty(struct uart_port *port) 359static unsigned int sport_tx_empty(struct uart_port *port)
@@ -331,34 +369,23 @@ static unsigned int sport_tx_empty(struct uart_port *port)
331 return 0; 369 return 0;
332} 370}
333 371
334static unsigned int sport_get_mctrl(struct uart_port *port)
335{
336 pr_debug("%s enter\n", __func__);
337 return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR);
338}
339
340static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
341{
342 pr_debug("%s enter\n", __func__);
343}
344
345static void sport_stop_tx(struct uart_port *port) 372static void sport_stop_tx(struct uart_port *port)
346{ 373{
347 struct sport_uart_port *up = (struct sport_uart_port *)port; 374 struct sport_uart_port *up = (struct sport_uart_port *)port;
348 unsigned int stat;
349 375
350 pr_debug("%s enter\n", __func__); 376 pr_debug("%s enter\n", __func__);
351 377
352 stat = SPORT_GET_STAT(up); 378 if (!(SPORT_GET_TCR1(up) & TSPEN))
353 while(!(stat & TXHRE)) { 379 return;
354 udelay(1); 380
355 stat = SPORT_GET_STAT(up);
356 }
357 /* Although the hold register is empty, last byte is still in shift 381 /* Although the hold register is empty, last byte is still in shift
358 * register and not sent out yet. If baud rate is lower than default, 382 * register and not sent out yet. So, put a dummy data into TX FIFO.
359 * delay should be longer. For example, if the baud rate is 9600, 383 * Then, sport tx stops when last byte is shift out and the dummy
360 * the delay must be at least 2ms by experience */ 384 * data is moved into the shift register.
361 udelay(500); 385 */
386 SPORT_PUT_TX(up, 0xffff);
387 while (!(SPORT_GET_STAT(up) & TXHRE))
388 cpu_relax();
362 389
363 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 390 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
364 SSYNC(); 391 SSYNC();
@@ -371,12 +398,14 @@ static void sport_start_tx(struct uart_port *port)
371 struct sport_uart_port *up = (struct sport_uart_port *)port; 398 struct sport_uart_port *up = (struct sport_uart_port *)port;
372 399
373 pr_debug("%s enter\n", __func__); 400 pr_debug("%s enter\n", __func__);
401
374 /* Write data into SPORT FIFO before enable SPROT to transmit */ 402 /* Write data into SPORT FIFO before enable SPROT to transmit */
375 sport_uart_tx_chars(up); 403 if (sport_uart_tx_chars(up)) {
404 /* Enable transmit, then an interrupt will generated */
405 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
406 SSYNC();
407 }
376 408
377 /* Enable transmit, then an interrupt will generated */
378 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
379 SSYNC();
380 pr_debug("%s exit\n", __func__); 409 pr_debug("%s exit\n", __func__);
381} 410}
382 411
@@ -404,29 +433,20 @@ static void sport_shutdown(struct uart_port *port)
404{ 433{
405 struct sport_uart_port *up = (struct sport_uart_port *)port; 434 struct sport_uart_port *up = (struct sport_uart_port *)port;
406 435
407 pr_debug("%s enter\n", __func__); 436 dev_dbg(port->dev, "%s enter\n", __func__);
408 437
409 /* Disable sport */ 438 /* Disable sport */
410 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 439 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
411 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); 440 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
412 SSYNC(); 441 SSYNC();
413 442
414 if (port->line) { 443 free_irq(up->port.irq, up);
415 peripheral_free_list(bfin_uart_pin_req_sport1); 444 free_irq(up->port.irq+1, up);
416 } else {
417 peripheral_free_list(bfin_uart_pin_req_sport0);
418 }
419
420 free_irq(up->rx_irq, up);
421 free_irq(up->tx_irq, up);
422 free_irq(up->err_irq, up); 445 free_irq(up->err_irq, up);
423} 446#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
424 447 if (up->cts_pin >= 0)
425static void sport_set_termios(struct uart_port *port, 448 free_irq(gpio_to_irq(up->cts_pin), up);
426 struct ktermios *termios, struct ktermios *old) 449#endif
427{
428 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
429 uart_update_timeout(port, CS8 ,port->uartclk);
430} 450}
431 451
432static const char *sport_type(struct uart_port *port) 452static const char *sport_type(struct uart_port *port)
@@ -434,7 +454,7 @@ static const char *sport_type(struct uart_port *port)
434 struct sport_uart_port *up = (struct sport_uart_port *)port; 454 struct sport_uart_port *up = (struct sport_uart_port *)port;
435 455
436 pr_debug("%s enter\n", __func__); 456 pr_debug("%s enter\n", __func__);
437 return up->name; 457 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
438} 458}
439 459
440static void sport_release_port(struct uart_port *port) 460static void sport_release_port(struct uart_port *port)
@@ -462,6 +482,95 @@ static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
462 return 0; 482 return 0;
463} 483}
464 484
485static void sport_set_termios(struct uart_port *port,
486 struct ktermios *termios, struct ktermios *old)
487{
488 struct sport_uart_port *up = (struct sport_uart_port *)port;
489 unsigned long flags;
490 int i;
491
492 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
493
494 switch (termios->c_cflag & CSIZE) {
495 case CS8:
496 up->csize = 8;
497 break;
498 case CS7:
499 up->csize = 7;
500 break;
501 case CS6:
502 up->csize = 6;
503 break;
504 case CS5:
505 up->csize = 5;
506 break;
507 default:
508 pr_warning("requested word length not supported\n");
509 }
510
511 if (termios->c_cflag & CSTOPB) {
512 up->stopb = 1;
513 }
514 if (termios->c_cflag & PARENB) {
515 pr_warning("PAREN bits is not supported yet\n");
516 /* up->parib = 1; */
517 }
518
519 spin_lock_irqsave(&up->port.lock, flags);
520
521 port->read_status_mask = 0;
522
523 /*
524 * Characters to ignore
525 */
526 port->ignore_status_mask = 0;
527
528 /* RX extract mask */
529 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
530 /* TX masks, 8 bit data and 1 bit stop for example:
531 * mask1 = b#0111111110
532 * mask2 = b#1000000000
533 */
534 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
535 up->txmask1 |= (1<<i);
536 up->txmask2 = (1<<i);
537 if (up->stopb) {
538 ++i;
539 up->txmask2 |= (1<<i);
540 }
541 up->txmask1 <<= 1;
542 up->txmask2 <<= 1;
543 /* uart baud rate */
544 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
545
546 /* Disable UART */
547 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
548 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
549
550 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
551
552 /* driver TX line high after config, one dummy data is
553 * necessary to stop sport after shift one byte
554 */
555 SPORT_PUT_TX(up, 0xffff);
556 SPORT_PUT_TX(up, 0xffff);
557 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
558 SSYNC();
559 while (!(SPORT_GET_STAT(up) & TXHRE))
560 cpu_relax();
561 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
562 SSYNC();
563
564 /* Port speed changed, update the per-port timeout. */
565 uart_update_timeout(port, termios->c_cflag, port->uartclk);
566
567 /* Enable sport rx */
568 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
569 SSYNC();
570
571 spin_unlock_irqrestore(&up->port.lock, flags);
572}
573
465struct uart_ops sport_uart_ops = { 574struct uart_ops sport_uart_ops = {
466 .tx_empty = sport_tx_empty, 575 .tx_empty = sport_tx_empty,
467 .set_mctrl = sport_set_mctrl, 576 .set_mctrl = sport_set_mctrl,
@@ -481,138 +590,346 @@ struct uart_ops sport_uart_ops = {
481 .verify_port = sport_verify_port, 590 .verify_port = sport_verify_port,
482}; 591};
483 592
484static struct sport_uart_port sport_uart_ports[] = { 593#define BFIN_SPORT_UART_MAX_PORTS 4
485 { /* SPORT 0 */ 594
486 .name = "SPORT0", 595static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
487 .tx_irq = IRQ_SPORT0_TX, 596
488 .rx_irq = IRQ_SPORT0_RX, 597#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
489 .err_irq= IRQ_SPORT0_ERROR, 598#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
490 .port = { 599
491 .type = PORT_BFIN_SPORT, 600static int __init
492 .iotype = UPIO_MEM, 601sport_uart_console_setup(struct console *co, char *options)
493 .membase = (void __iomem *)SPORT0_TCR1, 602{
494 .mapbase = SPORT0_TCR1, 603 struct sport_uart_port *up;
495 .irq = IRQ_SPORT0_RX, 604 int baud = 57600;
496 .uartclk = CONFIG_SPORT_BAUD_RATE, 605 int bits = 8;
497 .fifosize = 8, 606 int parity = 'n';
498 .ops = &sport_uart_ops, 607# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
499 .line = 0, 608 int flow = 'r';
500 }, 609# else
501 }, { /* SPORT 1 */ 610 int flow = 'n';
502 .name = "SPORT1", 611# endif
503 .tx_irq = IRQ_SPORT1_TX, 612
504 .rx_irq = IRQ_SPORT1_RX, 613 /* Check whether an invalid uart number has been specified */
505 .err_irq= IRQ_SPORT1_ERROR, 614 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
506 .port = { 615 return -ENODEV;
507 .type = PORT_BFIN_SPORT, 616
508 .iotype = UPIO_MEM, 617 up = bfin_sport_uart_ports[co->index];
509 .membase = (void __iomem *)SPORT1_TCR1, 618 if (!up)
510 .mapbase = SPORT1_TCR1, 619 return -ENODEV;
511 .irq = IRQ_SPORT1_RX, 620
512 .uartclk = CONFIG_SPORT_BAUD_RATE, 621 if (options)
513 .fifosize = 8, 622 uart_parse_options(options, &baud, &parity, &bits, &flow);
514 .ops = &sport_uart_ops, 623
515 .line = 1, 624 return uart_set_options(&up->port, co, baud, parity, bits, flow);
516 }, 625}
626
627static void sport_uart_console_putchar(struct uart_port *port, int ch)
628{
629 struct sport_uart_port *up = (struct sport_uart_port *)port;
630
631 while (SPORT_GET_STAT(up) & TXF)
632 barrier();
633
634 tx_one_byte(up, ch);
635}
636
637/*
638 * Interrupts are disabled on entering
639 */
640static void
641sport_uart_console_write(struct console *co, const char *s, unsigned int count)
642{
643 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
644 unsigned long flags;
645
646 spin_lock_irqsave(&up->port.lock, flags);
647
648 if (SPORT_GET_TCR1(up) & TSPEN)
649 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
650 else {
651 /* dummy data to start sport */
652 while (SPORT_GET_STAT(up) & TXF)
653 barrier();
654 SPORT_PUT_TX(up, 0xffff);
655 /* Enable transmit, then an interrupt will generated */
656 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
657 SSYNC();
658
659 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
660
661 /* Although the hold register is empty, last byte is still in shift
662 * register and not sent out yet. So, put a dummy data into TX FIFO.
663 * Then, sport tx stops when last byte is shift out and the dummy
664 * data is moved into the shift register.
665 */
666 while (SPORT_GET_STAT(up) & TXF)
667 barrier();
668 SPORT_PUT_TX(up, 0xffff);
669 while (!(SPORT_GET_STAT(up) & TXHRE))
670 barrier();
671
672 /* Stop sport tx transfer */
673 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
674 SSYNC();
517 } 675 }
676
677 spin_unlock_irqrestore(&up->port.lock, flags);
678}
679
680static struct uart_driver sport_uart_reg;
681
682static struct console sport_uart_console = {
683 .name = DEVICE_NAME,
684 .write = sport_uart_console_write,
685 .device = uart_console_device,
686 .setup = sport_uart_console_setup,
687 .flags = CON_PRINTBUFFER,
688 .index = -1,
689 .data = &sport_uart_reg,
518}; 690};
519 691
692#define SPORT_UART_CONSOLE (&sport_uart_console)
693#else
694#define SPORT_UART_CONSOLE NULL
695#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
696
697
520static struct uart_driver sport_uart_reg = { 698static struct uart_driver sport_uart_reg = {
521 .owner = THIS_MODULE, 699 .owner = THIS_MODULE,
522 .driver_name = "SPORT-UART", 700 .driver_name = DRV_NAME,
523 .dev_name = "ttySS", 701 .dev_name = DEVICE_NAME,
524 .major = 204, 702 .major = 204,
525 .minor = 84, 703 .minor = 84,
526 .nr = ARRAY_SIZE(sport_uart_ports), 704 .nr = BFIN_SPORT_UART_MAX_PORTS,
527 .cons = NULL, 705 .cons = SPORT_UART_CONSOLE,
528}; 706};
529 707
530static int sport_uart_suspend(struct platform_device *dev, pm_message_t state) 708#ifdef CONFIG_PM
709static int sport_uart_suspend(struct device *dev)
531{ 710{
532 struct sport_uart_port *sport = platform_get_drvdata(dev); 711 struct sport_uart_port *sport = dev_get_drvdata(dev);
533 712
534 pr_debug("%s enter\n", __func__); 713 dev_dbg(dev, "%s enter\n", __func__);
535 if (sport) 714 if (sport)
536 uart_suspend_port(&sport_uart_reg, &sport->port); 715 uart_suspend_port(&sport_uart_reg, &sport->port);
537 716
538 return 0; 717 return 0;
539} 718}
540 719
541static int sport_uart_resume(struct platform_device *dev) 720static int sport_uart_resume(struct device *dev)
542{ 721{
543 struct sport_uart_port *sport = platform_get_drvdata(dev); 722 struct sport_uart_port *sport = dev_get_drvdata(dev);
544 723
545 pr_debug("%s enter\n", __func__); 724 dev_dbg(dev, "%s enter\n", __func__);
546 if (sport) 725 if (sport)
547 uart_resume_port(&sport_uart_reg, &sport->port); 726 uart_resume_port(&sport_uart_reg, &sport->port);
548 727
549 return 0; 728 return 0;
550} 729}
551 730
552static int sport_uart_probe(struct platform_device *dev) 731static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
732 .suspend = sport_uart_suspend,
733 .resume = sport_uart_resume,
734};
735#endif
736
737static int __devinit sport_uart_probe(struct platform_device *pdev)
553{ 738{
554 pr_debug("%s enter\n", __func__); 739 struct resource *res;
555 sport_uart_ports[dev->id].port.dev = &dev->dev; 740 struct sport_uart_port *sport;
556 uart_add_one_port(&sport_uart_reg, &sport_uart_ports[dev->id].port); 741 int ret = 0;
557 platform_set_drvdata(dev, &sport_uart_ports[dev->id]);
558 742
559 return 0; 743 dev_dbg(&pdev->dev, "%s enter\n", __func__);
744
745 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
746 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
747 return -ENOENT;
748 }
749
750 if (bfin_sport_uart_ports[pdev->id] == NULL) {
751 bfin_sport_uart_ports[pdev->id] =
752 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
753 sport = bfin_sport_uart_ports[pdev->id];
754 if (!sport) {
755 dev_err(&pdev->dev,
756 "Fail to malloc sport_uart_port\n");
757 return -ENOMEM;
758 }
759
760 ret = peripheral_request_list(
761 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
762 if (ret) {
763 dev_err(&pdev->dev,
764 "Fail to request SPORT peripherals\n");
765 goto out_error_free_mem;
766 }
767
768 spin_lock_init(&sport->port.lock);
769 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
770 sport->port.ops = &sport_uart_ops;
771 sport->port.line = pdev->id;
772 sport->port.iotype = UPIO_MEM;
773 sport->port.flags = UPF_BOOT_AUTOCONF;
774
775 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
776 if (res == NULL) {
777 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
778 ret = -ENOENT;
779 goto out_error_free_peripherals;
780 }
781
782 sport->port.membase = ioremap(res->start, resource_size(res));
783 if (!sport->port.membase) {
784 dev_err(&pdev->dev, "Cannot map sport IO\n");
785 ret = -ENXIO;
786 goto out_error_free_peripherals;
787 }
788 sport->port.mapbase = res->start;
789
790 sport->port.irq = platform_get_irq(pdev, 0);
791 if (sport->port.irq < 0) {
792 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
793 ret = -ENOENT;
794 goto out_error_unmap;
795 }
796
797 sport->err_irq = platform_get_irq(pdev, 1);
798 if (sport->err_irq < 0) {
799 dev_err(&pdev->dev, "No sport status IRQ specified\n");
800 ret = -ENOENT;
801 goto out_error_unmap;
802 }
803#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
804 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
805 if (res == NULL)
806 sport->cts_pin = -1;
807 else
808 sport->cts_pin = res->start;
809
810 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
811 if (res == NULL)
812 sport->rts_pin = -1;
813 else
814 sport->rts_pin = res->start;
815
816 if (sport->rts_pin >= 0)
817 gpio_request(sport->rts_pin, DRV_NAME);
818#endif
819 }
820
821#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
822 if (!is_early_platform_device(pdev)) {
823#endif
824 sport = bfin_sport_uart_ports[pdev->id];
825 sport->port.dev = &pdev->dev;
826 dev_set_drvdata(&pdev->dev, sport);
827 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
828#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
829 }
830#endif
831 if (!ret)
832 return 0;
833
834 if (sport) {
835out_error_unmap:
836 iounmap(sport->port.membase);
837out_error_free_peripherals:
838 peripheral_free_list(
839 (unsigned short *)pdev->dev.platform_data);
840out_error_free_mem:
841 kfree(sport);
842 bfin_sport_uart_ports[pdev->id] = NULL;
843 }
844
845 return ret;
560} 846}
561 847
562static int sport_uart_remove(struct platform_device *dev) 848static int __devexit sport_uart_remove(struct platform_device *pdev)
563{ 849{
564 struct sport_uart_port *sport = platform_get_drvdata(dev); 850 struct sport_uart_port *sport = platform_get_drvdata(pdev);
565 851
566 pr_debug("%s enter\n", __func__); 852 dev_dbg(&pdev->dev, "%s enter\n", __func__);
567 platform_set_drvdata(dev, NULL); 853 dev_set_drvdata(&pdev->dev, NULL);
568 854
569 if (sport) 855 if (sport) {
570 uart_remove_one_port(&sport_uart_reg, &sport->port); 856 uart_remove_one_port(&sport_uart_reg, &sport->port);
857#ifdef CONFIG_SERIAL_BFIN_CTSRTS
858 if (sport->rts_pin >= 0)
859 gpio_free(sport->rts_pin);
860#endif
861 iounmap(sport->port.membase);
862 peripheral_free_list(
863 (unsigned short *)pdev->dev.platform_data);
864 kfree(sport);
865 bfin_sport_uart_ports[pdev->id] = NULL;
866 }
571 867
572 return 0; 868 return 0;
573} 869}
574 870
575static struct platform_driver sport_uart_driver = { 871static struct platform_driver sport_uart_driver = {
576 .probe = sport_uart_probe, 872 .probe = sport_uart_probe,
577 .remove = sport_uart_remove, 873 .remove = __devexit_p(sport_uart_remove),
578 .suspend = sport_uart_suspend,
579 .resume = sport_uart_resume,
580 .driver = { 874 .driver = {
581 .name = DRV_NAME, 875 .name = DRV_NAME,
876#ifdef CONFIG_PM
877 .pm = &bfin_sport_uart_dev_pm_ops,
878#endif
582 }, 879 },
583}; 880};
584 881
882#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
883static __initdata struct early_platform_driver early_sport_uart_driver = {
884 .class_str = CLASS_BFIN_SPORT_CONSOLE,
885 .pdrv = &sport_uart_driver,
886 .requested_id = EARLY_PLATFORM_ID_UNSET,
887};
888
889static int __init sport_uart_rs_console_init(void)
890{
891 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
892
893 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
894 BFIN_SPORT_UART_MAX_PORTS, 0);
895
896 register_console(&sport_uart_console);
897
898 return 0;
899}
900console_initcall(sport_uart_rs_console_init);
901#endif
902
585static int __init sport_uart_init(void) 903static int __init sport_uart_init(void)
586{ 904{
587 int ret; 905 int ret;
588 906
589 pr_debug("%s enter\n", __func__); 907 pr_info("Blackfin uart over sport driver\n");
908
590 ret = uart_register_driver(&sport_uart_reg); 909 ret = uart_register_driver(&sport_uart_reg);
591 if (ret != 0) { 910 if (ret) {
592 printk(KERN_ERR "Failed to register %s:%d\n", 911 pr_err("failed to register %s:%d\n",
593 sport_uart_reg.driver_name, ret); 912 sport_uart_reg.driver_name, ret);
594 return ret; 913 return ret;
595 } 914 }
596 915
597 ret = platform_driver_register(&sport_uart_driver); 916 ret = platform_driver_register(&sport_uart_driver);
598 if (ret != 0) { 917 if (ret) {
599 printk(KERN_ERR "Failed to register sport uart driver:%d\n", ret); 918 pr_err("failed to register sport uart driver:%d\n", ret);
600 uart_unregister_driver(&sport_uart_reg); 919 uart_unregister_driver(&sport_uart_reg);
601 } 920 }
602 921
603
604 pr_debug("%s exit\n", __func__);
605 return ret; 922 return ret;
606} 923}
924module_init(sport_uart_init);
607 925
608static void __exit sport_uart_exit(void) 926static void __exit sport_uart_exit(void)
609{ 927{
610 pr_debug("%s enter\n", __func__);
611 platform_driver_unregister(&sport_uart_driver); 928 platform_driver_unregister(&sport_uart_driver);
612 uart_unregister_driver(&sport_uart_reg); 929 uart_unregister_driver(&sport_uart_reg);
613} 930}
614
615module_init(sport_uart_init);
616module_exit(sport_uart_exit); 931module_exit(sport_uart_exit);
617 932
933MODULE_AUTHOR("Sonic Zhang, Roy Huang");
934MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
618MODULE_LICENSE("GPL"); 935MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 06:26:52 -0500