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-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c23
-rw-r--r--drivers/scsi/qla2xxx/qla_bsg.c10
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c521
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.h49
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h37
-rw-r--r--drivers/scsi/qla2xxx/qla_dfs.c2
-rw-r--r--drivers/scsi/qla2xxx/qla_fw.h13
-rw-r--r--drivers/scsi/qla2xxx/qla_gbl.h10
-rw-r--r--drivers/scsi/qla2xxx/qla_gs.c6
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c66
-rw-r--r--drivers/scsi/qla2xxx/qla_iocb.c9
-rw-r--r--drivers/scsi/qla2xxx/qla_isr.c44
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c262
-rw-r--r--drivers/scsi/qla2xxx/qla_nx.c8
-rw-r--r--drivers/scsi/qla2xxx/qla_nx.h3
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c192
-rw-r--r--drivers/scsi/qla2xxx/qla_sup.c148
17 files changed, 1233 insertions, 170 deletions
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index 9f41b3b4358f..7f895cdcaeb0 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -356,7 +356,8 @@ qla2x00_sysfs_write_optrom_ctl(struct file *filp, struct kobject *kobj,
356 else if (start == (ha->flt_region_boot * 4) || 356 else if (start == (ha->flt_region_boot * 4) ||
357 start == (ha->flt_region_fw * 4)) 357 start == (ha->flt_region_fw * 4))
358 valid = 1; 358 valid = 1;
359 else if (IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha)) 359 else if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)
360 || IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
360 valid = 1; 361 valid = 1;
361 if (!valid) { 362 if (!valid) {
362 ql_log(ql_log_warn, vha, 0x7065, 363 ql_log(ql_log_warn, vha, 0x7065,
@@ -898,7 +899,7 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *vha)
898 continue; 899 continue;
899 if (iter->is4GBp_only == 2 && !IS_QLA25XX(vha->hw)) 900 if (iter->is4GBp_only == 2 && !IS_QLA25XX(vha->hw))
900 continue; 901 continue;
901 if (iter->is4GBp_only == 3 && !(IS_QLA8XXX_TYPE(vha->hw))) 902 if (iter->is4GBp_only == 3 && !(IS_CNA_CAPABLE(vha->hw)))
902 continue; 903 continue;
903 904
904 ret = sysfs_create_bin_file(&host->shost_gendev.kobj, 905 ret = sysfs_create_bin_file(&host->shost_gendev.kobj,
@@ -926,7 +927,7 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *vha)
926 continue; 927 continue;
927 if (iter->is4GBp_only == 2 && !IS_QLA25XX(ha)) 928 if (iter->is4GBp_only == 2 && !IS_QLA25XX(ha))
928 continue; 929 continue;
929 if (iter->is4GBp_only == 3 && !!(IS_QLA8XXX_TYPE(vha->hw))) 930 if (iter->is4GBp_only == 3 && !(IS_CNA_CAPABLE(vha->hw)))
930 continue; 931 continue;
931 932
932 sysfs_remove_bin_file(&host->shost_gendev.kobj, 933 sysfs_remove_bin_file(&host->shost_gendev.kobj,
@@ -1231,7 +1232,7 @@ qla2x00_optrom_gold_fw_version_show(struct device *dev,
1231 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); 1232 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
1232 struct qla_hw_data *ha = vha->hw; 1233 struct qla_hw_data *ha = vha->hw;
1233 1234
1234 if (!IS_QLA81XX(ha)) 1235 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
1235 return snprintf(buf, PAGE_SIZE, "\n"); 1236 return snprintf(buf, PAGE_SIZE, "\n");
1236 1237
1237 return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d (%d)\n", 1238 return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d (%d)\n",
@@ -1278,7 +1279,7 @@ qla2x00_mpi_version_show(struct device *dev, struct device_attribute *attr,
1278 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); 1279 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
1279 struct qla_hw_data *ha = vha->hw; 1280 struct qla_hw_data *ha = vha->hw;
1280 1281
1281 if (!IS_QLA81XX(ha)) 1282 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
1282 return snprintf(buf, PAGE_SIZE, "\n"); 1283 return snprintf(buf, PAGE_SIZE, "\n");
1283 1284
1284 return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d (%x)\n", 1285 return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d (%x)\n",
@@ -1293,7 +1294,7 @@ qla2x00_phy_version_show(struct device *dev, struct device_attribute *attr,
1293 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); 1294 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
1294 struct qla_hw_data *ha = vha->hw; 1295 struct qla_hw_data *ha = vha->hw;
1295 1296
1296 if (!IS_QLA81XX(ha)) 1297 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
1297 return snprintf(buf, PAGE_SIZE, "\n"); 1298 return snprintf(buf, PAGE_SIZE, "\n");
1298 1299
1299 return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d\n", 1300 return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d\n",
@@ -1316,7 +1317,7 @@ qla2x00_vlan_id_show(struct device *dev, struct device_attribute *attr,
1316{ 1317{
1317 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); 1318 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
1318 1319
1319 if (!IS_QLA8XXX_TYPE(vha->hw)) 1320 if (!IS_CNA_CAPABLE(vha->hw))
1320 return snprintf(buf, PAGE_SIZE, "\n"); 1321 return snprintf(buf, PAGE_SIZE, "\n");
1321 1322
1322 return snprintf(buf, PAGE_SIZE, "%d\n", vha->fcoe_vlan_id); 1323 return snprintf(buf, PAGE_SIZE, "%d\n", vha->fcoe_vlan_id);
@@ -1328,7 +1329,7 @@ qla2x00_vn_port_mac_address_show(struct device *dev,
1328{ 1329{
1329 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); 1330 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
1330 1331
1331 if (!IS_QLA8XXX_TYPE(vha->hw)) 1332 if (!IS_CNA_CAPABLE(vha->hw))
1332 return snprintf(buf, PAGE_SIZE, "\n"); 1333 return snprintf(buf, PAGE_SIZE, "\n");
1333 1334
1334 return snprintf(buf, PAGE_SIZE, "%02x:%02x:%02x:%02x:%02x:%02x\n", 1335 return snprintf(buf, PAGE_SIZE, "%02x:%02x:%02x:%02x:%02x:%02x\n",
@@ -1493,6 +1494,9 @@ qla2x00_get_host_speed(struct Scsi_Host *shost)
1493 case PORT_SPEED_10GB: 1494 case PORT_SPEED_10GB:
1494 speed = FC_PORTSPEED_10GBIT; 1495 speed = FC_PORTSPEED_10GBIT;
1495 break; 1496 break;
1497 case PORT_SPEED_16GB:
1498 speed = FC_PORTSPEED_16GBIT;
1499 break;
1496 } 1500 }
1497 fc_host_speed(shost) = speed; 1501 fc_host_speed(shost) = speed;
1498} 1502}
@@ -1889,6 +1893,7 @@ qla24xx_vport_create(struct fc_vport *fc_vport, bool disable)
1889 break; 1893 break;
1890 } 1894 }
1891 } 1895 }
1896
1892 if (qos) { 1897 if (qos) {
1893 ret = qla25xx_create_req_que(ha, options, vha->vp_idx, 0, 0, 1898 ret = qla25xx_create_req_que(ha, options, vha->vp_idx, 0, 0,
1894 qos); 1899 qos);
@@ -2086,7 +2091,7 @@ qla2x00_init_host_attr(scsi_qla_host_t *vha)
2086 fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports; 2091 fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports;
2087 fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count; 2092 fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count;
2088 2093
2089 if (IS_QLA8XXX_TYPE(ha)) 2094 if (IS_CNA_CAPABLE(ha))
2090 speed = FC_PORTSPEED_10GBIT; 2095 speed = FC_PORTSPEED_10GBIT;
2091 else if (IS_QLA25XX(ha)) 2096 else if (IS_QLA25XX(ha))
2092 speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT | 2097 speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT |
diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c
index 1682e2e4201d..6887538d1736 100644
--- a/drivers/scsi/qla2xxx/qla_bsg.c
+++ b/drivers/scsi/qla2xxx/qla_bsg.c
@@ -540,7 +540,7 @@ qla81xx_set_internal_loopback(scsi_qla_host_t *vha, uint16_t *config,
540 int rval = 0; 540 int rval = 0;
541 struct qla_hw_data *ha = vha->hw; 541 struct qla_hw_data *ha = vha->hw;
542 542
543 if (!IS_QLA81XX(ha)) 543 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
544 goto done_set_internal; 544 goto done_set_internal;
545 545
546 new_config[0] = config[0] | (ENABLE_INTERNAL_LOOPBACK << 1); 546 new_config[0] = config[0] | (ENABLE_INTERNAL_LOOPBACK << 1);
@@ -582,7 +582,7 @@ qla81xx_reset_internal_loopback(scsi_qla_host_t *vha, uint16_t *config,
582 uint16_t new_config[4]; 582 uint16_t new_config[4];
583 struct qla_hw_data *ha = vha->hw; 583 struct qla_hw_data *ha = vha->hw;
584 584
585 if (!IS_QLA81XX(ha)) 585 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
586 goto done_reset_internal; 586 goto done_reset_internal;
587 587
588 memset(new_config, 0 , sizeof(new_config)); 588 memset(new_config, 0 , sizeof(new_config));
@@ -707,7 +707,7 @@ qla2x00_process_loopback(struct fc_bsg_job *bsg_job)
707 707
708 if ((ha->current_topology == ISP_CFG_F || 708 if ((ha->current_topology == ISP_CFG_F ||
709 (atomic_read(&vha->loop_state) == LOOP_DOWN) || 709 (atomic_read(&vha->loop_state) == LOOP_DOWN) ||
710 (IS_QLA81XX(ha) && 710 ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
711 le32_to_cpu(*(uint32_t *)req_data) == ELS_OPCODE_BYTE 711 le32_to_cpu(*(uint32_t *)req_data) == ELS_OPCODE_BYTE
712 && req_data_len == MAX_ELS_FRAME_PAYLOAD)) && 712 && req_data_len == MAX_ELS_FRAME_PAYLOAD)) &&
713 elreq.options == EXTERNAL_LOOPBACK) { 713 elreq.options == EXTERNAL_LOOPBACK) {
@@ -717,7 +717,7 @@ qla2x00_process_loopback(struct fc_bsg_job *bsg_job)
717 command_sent = INT_DEF_LB_ECHO_CMD; 717 command_sent = INT_DEF_LB_ECHO_CMD;
718 rval = qla2x00_echo_test(vha, &elreq, response); 718 rval = qla2x00_echo_test(vha, &elreq, response);
719 } else { 719 } else {
720 if (IS_QLA81XX(ha)) { 720 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) {
721 memset(config, 0, sizeof(config)); 721 memset(config, 0, sizeof(config));
722 memset(new_config, 0, sizeof(new_config)); 722 memset(new_config, 0, sizeof(new_config));
723 if (qla81xx_get_port_config(vha, config)) { 723 if (qla81xx_get_port_config(vha, config)) {
@@ -1331,7 +1331,7 @@ qla2x00_optrom_setup(struct fc_bsg_job *bsg_job, scsi_qla_host_t *vha,
1331 start == (ha->flt_region_fw * 4)) 1331 start == (ha->flt_region_fw * 4))
1332 valid = 1; 1332 valid = 1;
1333 else if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 1333 else if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
1334 IS_QLA8XXX_TYPE(ha)) 1334 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
1335 valid = 1; 1335 valid = 1;
1336 if (!valid) { 1336 if (!valid) {
1337 ql_log(ql_log_warn, vha, 0x7058, 1337 ql_log(ql_log_warn, vha, 0x7058,
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index cdf061763544..e4c6b9409933 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -11,23 +11,23 @@
11 * ---------------------------------------------------------------------- 11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes | 12 * | Level | Last Value Used | Holes |
13 * ---------------------------------------------------------------------- 13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x0116 | 0xfa | 14 * | Module Init and Probe | 0x011f | 0x4b,0xfa |
15 * | Mailbox commands | 0x112b | | 15 * | Mailbox commands | 0x1139 | 0x112c-0x112e |
16 * | Device Discovery | 0x2084 | | 16 * | Device Discovery | 0x2084 | |
17 * | Queue Command and IO tracing | 0x302f | 0x3008,0x302d, | 17 * | Queue Command and IO tracing | 0x302f | 0x3008 |
18 * | | | 0x302e | 18 * | | | 0x302d-0x302e |
19 * | DPC Thread | 0x401c | | 19 * | DPC Thread | 0x401c | |
20 * | Async Events | 0x5057 | 0x5052 | 20 * | Async Events | 0x5057 | 0x5052 |
21 * | Timer Routines | 0x6011 | 0x600e,0x600f | 21 * | Timer Routines | 0x6011 | 0x600e-0x600f |
22 * | User Space Interactions | 0x709e | 0x7018,0x702e | 22 * | User Space Interactions | 0x709e | 0x7018,0x702e |
23 * | | | 0x7039,0x7045 | 23 * | | | 0x7039,0x7045 |
24 * | Task Management | 0x803c | 0x8025-0x8026 | 24 * | Task Management | 0x803c | 0x8025-0x8026 |
25 * | | | 0x800b,0x8039 | 25 * | | | 0x800b,0x8039 |
26 * | AER/EEH | 0x900f | | 26 * | AER/EEH | 0x900f | |
27 * | Virtual Port | 0xa007 | | 27 * | Virtual Port | 0xa007 | |
28 * | ISP82XX Specific | 0xb052 | | 28 * | ISP82XX Specific | 0xb052 | |
29 * | MultiQ | 0xc00b | | 29 * | MultiQ | 0xc00c | |
30 * | Misc | 0xd00b | | 30 * | Misc | 0xd010 | |
31 * ---------------------------------------------------------------------- 31 * ----------------------------------------------------------------------
32 */ 32 */
33 33
@@ -453,7 +453,7 @@ qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
453 struct qla2xxx_mq_chain *mq = ptr; 453 struct qla2xxx_mq_chain *mq = ptr;
454 struct device_reg_25xxmq __iomem *reg; 454 struct device_reg_25xxmq __iomem *reg;
455 455
456 if (!ha->mqenable) 456 if (!ha->mqenable || IS_QLA83XX(ha))
457 return ptr; 457 return ptr;
458 458
459 mq = ptr; 459 mq = ptr;
@@ -1729,6 +1729,507 @@ qla81xx_fw_dump_failed:
1729 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1729 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1730} 1730}
1731 1731
1732void
1733qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1734{
1735 int rval;
1736 uint32_t cnt, reg_data;
1737 uint32_t risc_address;
1738 struct qla_hw_data *ha = vha->hw;
1739 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1740 uint32_t __iomem *dmp_reg;
1741 uint32_t *iter_reg;
1742 uint16_t __iomem *mbx_reg;
1743 unsigned long flags;
1744 struct qla83xx_fw_dump *fw;
1745 uint32_t ext_mem_cnt;
1746 void *nxt, *nxt_chain;
1747 uint32_t *last_chain = NULL;
1748 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1749
1750 risc_address = ext_mem_cnt = 0;
1751 flags = 0;
1752
1753 if (!hardware_locked)
1754 spin_lock_irqsave(&ha->hardware_lock, flags);
1755
1756 if (!ha->fw_dump) {
1757 ql_log(ql_log_warn, vha, 0xd00c,
1758 "No buffer available for dump!!!\n");
1759 goto qla83xx_fw_dump_failed;
1760 }
1761
1762 if (ha->fw_dumped) {
1763 ql_log(ql_log_warn, vha, 0xd00d,
1764 "Firmware has been previously dumped (%p) -- ignoring "
1765 "request...\n", ha->fw_dump);
1766 goto qla83xx_fw_dump_failed;
1767 }
1768 fw = &ha->fw_dump->isp.isp83;
1769 qla2xxx_prep_dump(ha, ha->fw_dump);
1770
1771 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1772
1773 /* Pause RISC. */
1774 rval = qla24xx_pause_risc(reg);
1775 if (rval != QLA_SUCCESS)
1776 goto qla83xx_fw_dump_failed_0;
1777
1778 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1779 dmp_reg = &reg->iobase_window;
1780 reg_data = RD_REG_DWORD(dmp_reg);
1781 WRT_REG_DWORD(dmp_reg, 0);
1782
1783 dmp_reg = &reg->unused_4_1[0];
1784 reg_data = RD_REG_DWORD(dmp_reg);
1785 WRT_REG_DWORD(dmp_reg, 0);
1786
1787 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1788 dmp_reg = &reg->unused_4_1[2];
1789 reg_data = RD_REG_DWORD(dmp_reg);
1790 WRT_REG_DWORD(dmp_reg, 0);
1791
1792 /* select PCR and disable ecc checking and correction */
1793 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1794 RD_REG_DWORD(&reg->iobase_addr);
1795 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1796
1797 /* Host/Risc registers. */
1798 iter_reg = fw->host_risc_reg;
1799 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1800 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1801 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1802
1803 /* PCIe registers. */
1804 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1805 RD_REG_DWORD(&reg->iobase_addr);
1806 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1807 dmp_reg = &reg->iobase_c4;
1808 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1809 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1810 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1811 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1812
1813 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1814 RD_REG_DWORD(&reg->iobase_window);
1815
1816 /* Host interface registers. */
1817 dmp_reg = &reg->flash_addr;
1818 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1819 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1820
1821 /* Disable interrupts. */
1822 WRT_REG_DWORD(&reg->ictrl, 0);
1823 RD_REG_DWORD(&reg->ictrl);
1824
1825 /* Shadow registers. */
1826 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1827 RD_REG_DWORD(&reg->iobase_addr);
1828 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1829 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1830
1831 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1832 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1833
1834 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1835 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1836
1837 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1838 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1839
1840 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1841 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1842
1843 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1844 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1845
1846 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1847 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1848
1849 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1850 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1851
1852 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1853 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1854
1855 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1856 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1857
1858 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1859 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1860
1861 /* RISC I/O register. */
1862 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1863 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1864
1865 /* Mailbox registers. */
1866 mbx_reg = &reg->mailbox0;
1867 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1868 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1869
1870 /* Transfer sequence registers. */
1871 iter_reg = fw->xseq_gp_reg;
1872 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1873 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1874 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1875 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1876 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1877 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1878 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1879 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1880 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1881 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1882 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1883 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1884 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1885 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1886 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1887 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1888
1889 iter_reg = fw->xseq_0_reg;
1890 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1891 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1892 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1893
1894 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1895
1896 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1897
1898 /* Receive sequence registers. */
1899 iter_reg = fw->rseq_gp_reg;
1900 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1901 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1902 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1903 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1904 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1905 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1906 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1907 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1908 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1909 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1910 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1911 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1912 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1913 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1914 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1915 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1916
1917 iter_reg = fw->rseq_0_reg;
1918 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1919 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1920
1921 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1922 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1923 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
1924
1925 /* Auxiliary sequence registers. */
1926 iter_reg = fw->aseq_gp_reg;
1927 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1928 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1929 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1930 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1931 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1932 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1933 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1934 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1935 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
1936 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
1937 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
1938 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
1939 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
1940 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
1941 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
1942 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
1943
1944 iter_reg = fw->aseq_0_reg;
1945 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1946 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1947
1948 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1949 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1950 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
1951
1952 /* Command DMA registers. */
1953 iter_reg = fw->cmd_dma_reg;
1954 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
1955 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
1956 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
1957 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
1958
1959 /* Queues. */
1960 iter_reg = fw->req0_dma_reg;
1961 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1962 dmp_reg = &reg->iobase_q;
1963 for (cnt = 0; cnt < 7; cnt++)
1964 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1965
1966 iter_reg = fw->resp0_dma_reg;
1967 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1968 dmp_reg = &reg->iobase_q;
1969 for (cnt = 0; cnt < 7; cnt++)
1970 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1971
1972 iter_reg = fw->req1_dma_reg;
1973 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1974 dmp_reg = &reg->iobase_q;
1975 for (cnt = 0; cnt < 7; cnt++)
1976 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1977
1978 /* Transmit DMA registers. */
1979 iter_reg = fw->xmt0_dma_reg;
1980 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1981 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1982
1983 iter_reg = fw->xmt1_dma_reg;
1984 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1985 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1986
1987 iter_reg = fw->xmt2_dma_reg;
1988 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1989 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1990
1991 iter_reg = fw->xmt3_dma_reg;
1992 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1993 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1994
1995 iter_reg = fw->xmt4_dma_reg;
1996 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1997 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1998
1999 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2000
2001 /* Receive DMA registers. */
2002 iter_reg = fw->rcvt0_data_dma_reg;
2003 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2004 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2005
2006 iter_reg = fw->rcvt1_data_dma_reg;
2007 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2008 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2009
2010 /* RISC registers. */
2011 iter_reg = fw->risc_gp_reg;
2012 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2013 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2014 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2015 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2016 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2017 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2018 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2019 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2020
2021 /* Local memory controller registers. */
2022 iter_reg = fw->lmc_reg;
2023 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2024 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2025 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2026 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2027 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2028 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2029 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2030 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2031
2032 /* Fibre Protocol Module registers. */
2033 iter_reg = fw->fpm_hdw_reg;
2034 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2035 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2036 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2037 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2038 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2039 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2040 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2041 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2042 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2043 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2044 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2045 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2046 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2047 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2048 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2049 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2050
2051 /* RQ0 Array registers. */
2052 iter_reg = fw->rq0_array_reg;
2053 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2054 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2055 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2056 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2057 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2058 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2059 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2060 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2061 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2062 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2063 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2064 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2065 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2066 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2067 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2068 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2069
2070 /* RQ1 Array registers. */
2071 iter_reg = fw->rq1_array_reg;
2072 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2073 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2074 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2075 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2076 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2077 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2078 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2079 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2080 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2081 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2082 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2083 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2084 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2085 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2086 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2087 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2088
2089 /* RP0 Array registers. */
2090 iter_reg = fw->rp0_array_reg;
2091 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2092 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2093 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2095 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2096 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2097 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2098 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2099 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2100 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2101 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2102 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2103 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2104 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2106 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2107
2108 /* RP1 Array registers. */
2109 iter_reg = fw->rp1_array_reg;
2110 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2111 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2113 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2114 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2115 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2125 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2126
2127 iter_reg = fw->at0_array_reg;
2128 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2129 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2130 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2135 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2136
2137 /* I/O Queue Control registers. */
2138 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2139
2140 /* Frame Buffer registers. */
2141 iter_reg = fw->fb_hdw_reg;
2142 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2145 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2146 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2147 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2148 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2149 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2150 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2151 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2152 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2163 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2164 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2165 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2166 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2167 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2168 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2169
2170 /* Multi queue registers */
2171 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2172 &last_chain);
2173
2174 rval = qla24xx_soft_reset(ha);
2175 if (rval != QLA_SUCCESS) {
2176 ql_log(ql_log_warn, vha, 0xd00e,
2177 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2178 rval = QLA_SUCCESS;
2179
2180 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2181
2182 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2183 RD_REG_DWORD(&reg->hccr);
2184
2185 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2186 RD_REG_DWORD(&reg->hccr);
2187
2188 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2189 RD_REG_DWORD(&reg->hccr);
2190
2191 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2192 udelay(5);
2193
2194 if (!cnt) {
2195 nxt = fw->code_ram;
2196 nxt += sizeof(fw->code_ram),
2197 nxt += (ha->fw_memory_size - 0x100000 + 1);
2198 goto copy_queue;
2199 } else
2200 ql_log(ql_log_warn, vha, 0xd010,
2201 "bigger hammer success?\n");
2202 }
2203
2204 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2205 &nxt);
2206 if (rval != QLA_SUCCESS)
2207 goto qla83xx_fw_dump_failed_0;
2208
2209copy_queue:
2210 nxt = qla2xxx_copy_queues(ha, nxt);
2211
2212 nxt = qla24xx_copy_eft(ha, nxt);
2213
2214 /* Chain entries -- started with MQ. */
2215 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2216 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2217 if (last_chain) {
2218 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2219 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2220 }
2221
2222 /* Adjust valid length. */
2223 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2224
2225qla83xx_fw_dump_failed_0:
2226 qla2xxx_dump_post_process(base_vha, rval);
2227
2228qla83xx_fw_dump_failed:
2229 if (!hardware_locked)
2230 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2231}
2232
1732/****************************************************************************/ 2233/****************************************************************************/
1733/* Driver Debug Functions. */ 2234/* Driver Debug Functions. */
1734/****************************************************************************/ 2235/****************************************************************************/
diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h
index 6b05cb1d1874..2157bdf1569a 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.h
+++ b/drivers/scsi/qla2xxx/qla_dbg.h
@@ -165,6 +165,54 @@ struct qla81xx_fw_dump {
165 uint32_t ext_mem[1]; 165 uint32_t ext_mem[1];
166}; 166};
167 167
168struct qla83xx_fw_dump {
169 uint32_t host_status;
170 uint32_t host_risc_reg[48];
171 uint32_t pcie_regs[4];
172 uint32_t host_reg[32];
173 uint32_t shadow_reg[11];
174 uint32_t risc_io_reg;
175 uint16_t mailbox_reg[32];
176 uint32_t xseq_gp_reg[256];
177 uint32_t xseq_0_reg[48];
178 uint32_t xseq_1_reg[16];
179 uint32_t xseq_2_reg[16];
180 uint32_t rseq_gp_reg[256];
181 uint32_t rseq_0_reg[32];
182 uint32_t rseq_1_reg[16];
183 uint32_t rseq_2_reg[16];
184 uint32_t rseq_3_reg[16];
185 uint32_t aseq_gp_reg[256];
186 uint32_t aseq_0_reg[32];
187 uint32_t aseq_1_reg[16];
188 uint32_t aseq_2_reg[16];
189 uint32_t aseq_3_reg[16];
190 uint32_t cmd_dma_reg[64];
191 uint32_t req0_dma_reg[15];
192 uint32_t resp0_dma_reg[15];
193 uint32_t req1_dma_reg[15];
194 uint32_t xmt0_dma_reg[32];
195 uint32_t xmt1_dma_reg[32];
196 uint32_t xmt2_dma_reg[32];
197 uint32_t xmt3_dma_reg[32];
198 uint32_t xmt4_dma_reg[32];
199 uint32_t xmt_data_dma_reg[16];
200 uint32_t rcvt0_data_dma_reg[32];
201 uint32_t rcvt1_data_dma_reg[32];
202 uint32_t risc_gp_reg[128];
203 uint32_t lmc_reg[128];
204 uint32_t fpm_hdw_reg[256];
205 uint32_t rq0_array_reg[256];
206 uint32_t rq1_array_reg[256];
207 uint32_t rp0_array_reg[256];
208 uint32_t rp1_array_reg[256];
209 uint32_t queue_control_reg[16];
210 uint32_t fb_hdw_reg[432];
211 uint32_t at0_array_reg[128];
212 uint32_t code_ram[0x2400];
213 uint32_t ext_mem[1];
214};
215
168#define EFT_NUM_BUFFERS 4 216#define EFT_NUM_BUFFERS 4
169#define EFT_BYTES_PER_BUFFER 0x4000 217#define EFT_BYTES_PER_BUFFER 0x4000
170#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 218#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
@@ -242,6 +290,7 @@ struct qla2xxx_fw_dump {
242 struct qla24xx_fw_dump isp24; 290 struct qla24xx_fw_dump isp24;
243 struct qla25xx_fw_dump isp25; 291 struct qla25xx_fw_dump isp25;
244 struct qla81xx_fw_dump isp81; 292 struct qla81xx_fw_dump isp81;
293 struct qla83xx_fw_dump isp83;
245 } isp; 294 } isp;
246}; 295};
247 296
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index af1003f9de1e..7b7d829bef8b 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -653,6 +653,7 @@ typedef struct {
653#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 653#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
654#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 654#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
655#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 655#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
656#define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
656#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 657#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
657#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 658#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
658#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 659#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
@@ -2261,6 +2262,7 @@ struct isp_operations {
2261#define QLA_MIDX_DEFAULT 0 2262#define QLA_MIDX_DEFAULT 0
2262#define QLA_MIDX_RSP_Q 1 2263#define QLA_MIDX_RSP_Q 1
2263#define QLA_PCI_MSIX_CONTROL 0xa2 2264#define QLA_PCI_MSIX_CONTROL 0xa2
2265#define QLA_83XX_PCI_MSIX_CONTROL 0x92
2264 2266
2265struct scsi_qla_host; 2267struct scsi_qla_host;
2266 2268
@@ -2341,7 +2343,7 @@ struct qla_statistics {
2341#define QLA_MQ_SIZE 32 2343#define QLA_MQ_SIZE 32
2342#define QLA_MAX_QUEUES 256 2344#define QLA_MAX_QUEUES 256
2343#define ISP_QUE_REG(ha, id) \ 2345#define ISP_QUE_REG(ha, id) \
2344 ((ha->mqenable) ? \ 2346 ((ha->mqenable || IS_QLA83XX(ha)) ? \
2345 ((void *)(ha->mqiobase) +\ 2347 ((void *)(ha->mqiobase) +\
2346 (QLA_QUE_PAGE * id)) :\ 2348 (QLA_QUE_PAGE * id)) :\
2347 ((void *)(ha->iobase))) 2349 ((void *)(ha->iobase)))
@@ -2461,6 +2463,7 @@ struct qla_hw_data {
2461#define MIN_IOBASE_LEN 0x100 2463#define MIN_IOBASE_LEN 0x100
2462/* Multi queue data structs */ 2464/* Multi queue data structs */
2463 device_reg_t __iomem *mqiobase; 2465 device_reg_t __iomem *mqiobase;
2466 device_reg_t __iomem *msixbase;
2464 uint16_t msix_count; 2467 uint16_t msix_count;
2465 uint8_t mqenable; 2468 uint8_t mqenable;
2466 struct req_que **req_q_map; 2469 struct req_que **req_q_map;
@@ -2494,6 +2497,7 @@ struct qla_hw_data {
2494#define PORT_SPEED_2GB 0x01 2497#define PORT_SPEED_2GB 0x01
2495#define PORT_SPEED_4GB 0x03 2498#define PORT_SPEED_4GB 0x03
2496#define PORT_SPEED_8GB 0x04 2499#define PORT_SPEED_8GB 0x04
2500#define PORT_SPEED_16GB 0x05
2497#define PORT_SPEED_10GB 0x13 2501#define PORT_SPEED_10GB 0x13
2498 uint16_t link_data_rate; /* F/W operating speed */ 2502 uint16_t link_data_rate; /* F/W operating speed */
2499 2503
@@ -2515,6 +2519,8 @@ struct qla_hw_data {
2515#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2519#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2516#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 2520#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2517#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 2521#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2522#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2523#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
2518 uint32_t device_type; 2524 uint32_t device_type;
2519#define DT_ISP2100 BIT_0 2525#define DT_ISP2100 BIT_0
2520#define DT_ISP2200 BIT_1 2526#define DT_ISP2200 BIT_1
@@ -2531,7 +2537,9 @@ struct qla_hw_data {
2531#define DT_ISP8432 BIT_12 2537#define DT_ISP8432 BIT_12
2532#define DT_ISP8001 BIT_13 2538#define DT_ISP8001 BIT_13
2533#define DT_ISP8021 BIT_14 2539#define DT_ISP8021 BIT_14
2534#define DT_ISP_LAST (DT_ISP8021 << 1) 2540#define DT_ISP2031 BIT_15
2541#define DT_ISP8031 BIT_16
2542#define DT_ISP_LAST (DT_ISP8031 << 1)
2535 2543
2536#define DT_T10_PI BIT_25 2544#define DT_T10_PI BIT_25
2537#define DT_IIDMA BIT_26 2545#define DT_IIDMA BIT_26
@@ -2555,26 +2563,30 @@ struct qla_hw_data {
2555#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2563#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2556#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 2564#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2557#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 2565#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2566#define IS_QLA81XX(ha) (IS_QLA8001(ha))
2558#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 2567#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2568#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2569#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
2559 2570
2560#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2571#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2561 IS_QLA6312(ha) || IS_QLA6322(ha)) 2572 IS_QLA6312(ha) || IS_QLA6322(ha))
2562#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2573#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2563#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2574#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2564#define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2575#define IS_QLA25XX(ha) (IS_QLA2532(ha))
2576#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
2565#define IS_QLA84XX(ha) (IS_QLA8432(ha)) 2577#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2566#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 2578#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2567 IS_QLA84XX(ha)) 2579 IS_QLA84XX(ha))
2568#define IS_QLA81XX(ha) (IS_QLA8001(ha)) 2580#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
2569#define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha)) 2581 IS_QLA8031(ha))
2570#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 2582#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2571 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 2583 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2572 IS_QLA82XX(ha)) 2584 IS_QLA82XX(ha) || IS_QLA83XX(ha))
2573#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha)) 2585#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2574#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \ 2586#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2575 (ha)->flags.msix_enabled) 2587 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
2576#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha)) 2588#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2577#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha)) 2589#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2578#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 2590#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2579 2591
2580#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 2592#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
@@ -2583,6 +2595,8 @@ struct qla_hw_data {
2583#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 2595#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2584#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 2596#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2585#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 2597#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2598#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
2599#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
2586 2600
2587 /* HBA serial number */ 2601 /* HBA serial number */
2588 uint8_t serial0; 2602 uint8_t serial0;
@@ -2674,6 +2688,8 @@ struct qla_hw_data {
2674 uint16_t fw_minor_version; 2688 uint16_t fw_minor_version;
2675 uint16_t fw_subminor_version; 2689 uint16_t fw_subminor_version;
2676 uint16_t fw_attributes; 2690 uint16_t fw_attributes;
2691 uint16_t fw_attributes_h;
2692 uint16_t fw_attributes_ext[2];
2677 uint32_t fw_memory_size; 2693 uint32_t fw_memory_size;
2678 uint32_t fw_transfer_size; 2694 uint32_t fw_transfer_size;
2679 uint32_t fw_srisc_address; 2695 uint32_t fw_srisc_address;
@@ -3021,6 +3037,7 @@ typedef struct scsi_qla_host {
3021#define OPTROM_SIZE_25XX 0x200000 3037#define OPTROM_SIZE_25XX 0x200000
3022#define OPTROM_SIZE_81XX 0x400000 3038#define OPTROM_SIZE_81XX 0x400000
3023#define OPTROM_SIZE_82XX 0x800000 3039#define OPTROM_SIZE_82XX 0x800000
3040#define OPTROM_SIZE_83XX 0x1000000
3024 3041
3025#define OPTROM_BURST_SIZE 0x1000 3042#define OPTROM_BURST_SIZE 0x1000
3026#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3043#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
diff --git a/drivers/scsi/qla2xxx/qla_dfs.c b/drivers/scsi/qla2xxx/qla_dfs.c
index 0b4c2b794c6f..499c74e39ee5 100644
--- a/drivers/scsi/qla2xxx/qla_dfs.c
+++ b/drivers/scsi/qla2xxx/qla_dfs.c
@@ -114,7 +114,7 @@ qla2x00_dfs_setup(scsi_qla_host_t *vha)
114{ 114{
115 struct qla_hw_data *ha = vha->hw; 115 struct qla_hw_data *ha = vha->hw;
116 116
117 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)) 117 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
118 goto out; 118 goto out;
119 if (!ha->fce) 119 if (!ha->fce)
120 goto out; 120 goto out;
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
index aa69486dc064..6d7d7758c797 100644
--- a/drivers/scsi/qla2xxx/qla_fw.h
+++ b/drivers/scsi/qla2xxx/qla_fw.h
@@ -1327,6 +1327,11 @@ struct qla_flt_header {
1327#define FLT_REG_GOLD_FW 0x2f 1327#define FLT_REG_GOLD_FW 0x2f
1328#define FLT_REG_FCP_PRIO_0 0x87 1328#define FLT_REG_FCP_PRIO_0 0x87
1329#define FLT_REG_FCP_PRIO_1 0x88 1329#define FLT_REG_FCP_PRIO_1 0x88
1330#define FLT_REG_FCOE_FW 0xA4
1331#define FLT_REG_FCOE_VPD_0 0xA9
1332#define FLT_REG_FCOE_NVRAM_0 0xAA
1333#define FLT_REG_FCOE_VPD_1 0xAB
1334#define FLT_REG_FCOE_NVRAM_1 0xAC
1330 1335
1331struct qla_flt_region { 1336struct qla_flt_region {
1332 uint32_t code; 1337 uint32_t code;
@@ -1494,6 +1499,11 @@ struct access_chip_rsp_84xx {
1494#define MBC_GET_XGMAC_STATS 0x7a 1499#define MBC_GET_XGMAC_STATS 0x7a
1495#define MBC_GET_DCBX_PARAMS 0x51 1500#define MBC_GET_DCBX_PARAMS 0x51
1496 1501
1502/*
1503 * ISP83xx mailbox commands
1504 */
1505#define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1506
1497/* Flash access control option field bit definitions */ 1507/* Flash access control option field bit definitions */
1498#define FAC_OPT_FORCE_SEMAPHORE BIT_15 1508#define FAC_OPT_FORCE_SEMAPHORE BIT_15
1499#define FAC_OPT_REQUESTOR_ID BIT_14 1509#define FAC_OPT_REQUESTOR_ID BIT_14
@@ -1875,4 +1885,7 @@ struct qla_fcp_prio_cfg {
1875#define FA_NPIV_CONF0_ADDR_81 0xD1000 1885#define FA_NPIV_CONF0_ADDR_81 0xD1000
1876#define FA_NPIV_CONF1_ADDR_81 0xD2000 1886#define FA_NPIV_CONF1_ADDR_81 0xD2000
1877 1887
1888/* 83XX Flash locations -- occupies second 8MB region. */
1889#define FA_FLASH_LAYOUT_ADDR_83 0xFC400
1890
1878#endif 1891#endif
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
index 408679be8fdf..362d49cbcb72 100644
--- a/drivers/scsi/qla2xxx/qla_gbl.h
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
@@ -205,8 +205,7 @@ extern int
205qla2x00_execute_fw(scsi_qla_host_t *, uint32_t); 205qla2x00_execute_fw(scsi_qla_host_t *, uint32_t);
206 206
207extern int 207extern int
208qla2x00_get_fw_version(scsi_qla_host_t *, uint16_t *, uint16_t *, uint16_t *, 208qla2x00_get_fw_version(scsi_qla_host_t *);
209 uint16_t *, uint32_t *, uint8_t *, uint32_t *, uint8_t *);
210 209
211extern int 210extern int
212qla2x00_get_fw_options(scsi_qla_host_t *, uint16_t *); 211qla2x00_get_fw_options(scsi_qla_host_t *, uint16_t *);
@@ -409,8 +408,10 @@ extern void qla2x00_beacon_blink(struct scsi_qla_host *);
409extern int qla24xx_beacon_on(struct scsi_qla_host *); 408extern int qla24xx_beacon_on(struct scsi_qla_host *);
410extern int qla24xx_beacon_off(struct scsi_qla_host *); 409extern int qla24xx_beacon_off(struct scsi_qla_host *);
411extern void qla24xx_beacon_blink(struct scsi_qla_host *); 410extern void qla24xx_beacon_blink(struct scsi_qla_host *);
411extern void qla83xx_beacon_blink(struct scsi_qla_host *);
412extern int qla82xx_beacon_on(struct scsi_qla_host *); 412extern int qla82xx_beacon_on(struct scsi_qla_host *);
413extern int qla82xx_beacon_off(struct scsi_qla_host *); 413extern int qla82xx_beacon_off(struct scsi_qla_host *);
414extern int qla83xx_write_remote_reg(struct scsi_qla_host *, uint32_t, uint32_t);
414 415
415extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *, 416extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *,
416 uint32_t, uint32_t); 417 uint32_t, uint32_t);
@@ -576,6 +577,8 @@ extern void qla82xx_start_iocbs(scsi_qla_host_t *);
576extern int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *); 577extern int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *);
577extern int qla82xx_check_md_needed(scsi_qla_host_t *); 578extern int qla82xx_check_md_needed(scsi_qla_host_t *);
578extern void qla82xx_chip_reset_cleanup(scsi_qla_host_t *); 579extern void qla82xx_chip_reset_cleanup(scsi_qla_host_t *);
580extern int qla81xx_set_led_config(scsi_qla_host_t *, uint16_t *);
581extern int qla81xx_get_led_config(scsi_qla_host_t *, uint16_t *);
579extern int qla82xx_mbx_beacon_ctl(scsi_qla_host_t *, int); 582extern int qla82xx_mbx_beacon_ctl(scsi_qla_host_t *, int);
580extern char *qdev_state(uint32_t); 583extern char *qdev_state(uint32_t);
581extern void qla82xx_clear_pending_mbx(scsi_qla_host_t *); 584extern void qla82xx_clear_pending_mbx(scsi_qla_host_t *);
@@ -589,6 +592,9 @@ extern int qla2x00_issue_iocb_timeout(scsi_qla_host_t *, void *,
589extern int qla2x00_get_idma_speed(scsi_qla_host_t *, uint16_t, 592extern int qla2x00_get_idma_speed(scsi_qla_host_t *, uint16_t,
590 uint16_t *, uint16_t *); 593 uint16_t *, uint16_t *);
591 594
595/* 83xx related functions */
596extern void qla83xx_fw_dump(scsi_qla_host_t *, int);
597
592/* Minidump related functions */ 598/* Minidump related functions */
593extern int qla82xx_md_get_template_size(scsi_qla_host_t *); 599extern int qla82xx_md_get_template_size(scsi_qla_host_t *);
594extern int qla82xx_md_get_template(scsi_qla_host_t *); 600extern int qla82xx_md_get_template(scsi_qla_host_t *);
diff --git a/drivers/scsi/qla2xxx/qla_gs.c b/drivers/scsi/qla2xxx/qla_gs.c
index 4aea4ae23300..dd8339928a5f 100644
--- a/drivers/scsi/qla2xxx/qla_gs.c
+++ b/drivers/scsi/qla2xxx/qla_gs.c
@@ -1547,7 +1547,7 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *vha)
1547 eiter = (struct ct_fdmi_port_attr *) (entries + size); 1547 eiter = (struct ct_fdmi_port_attr *) (entries + size);
1548 eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); 1548 eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED);
1549 eiter->len = __constant_cpu_to_be16(4 + 4); 1549 eiter->len = __constant_cpu_to_be16(4 + 4);
1550 if (IS_QLA8XXX_TYPE(ha)) 1550 if (IS_CNA_CAPABLE(ha))
1551 eiter->a.sup_speed = __constant_cpu_to_be32( 1551 eiter->a.sup_speed = __constant_cpu_to_be32(
1552 FDMI_PORT_SPEED_10GB); 1552 FDMI_PORT_SPEED_10GB);
1553 else if (IS_QLA25XX(ha)) 1553 else if (IS_QLA25XX(ha))
@@ -1594,6 +1594,10 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *vha)
1594 eiter->a.cur_speed = 1594 eiter->a.cur_speed =
1595 __constant_cpu_to_be32(FDMI_PORT_SPEED_10GB); 1595 __constant_cpu_to_be32(FDMI_PORT_SPEED_10GB);
1596 break; 1596 break;
1597 case PORT_SPEED_16GB:
1598 eiter->a.cur_speed =
1599 __constant_cpu_to_be32(FDMI_PORT_SPEED_16GB);
1600 break;
1597 default: 1601 default:
1598 eiter->a.cur_speed = 1602 eiter->a.cur_speed =
1599 __constant_cpu_to_be32(FDMI_PORT_SPEED_UNKNOWN); 1603 __constant_cpu_to_be32(FDMI_PORT_SPEED_UNKNOWN);
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 68555dfee6ac..38d865911ee4 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -969,6 +969,9 @@ qla81xx_reset_mpi(scsi_qla_host_t *vha)
969{ 969{
970 uint16_t mb[4] = {0x1010, 0, 1, 0}; 970 uint16_t mb[4] = {0x1010, 0, 1, 0};
971 971
972 if (!IS_QLA81XX(vha->hw))
973 return QLA_SUCCESS;
974
972 return qla81xx_write_mpi_register(vha, mb); 975 return qla81xx_write_mpi_register(vha, mb);
973} 976}
974 977
@@ -1262,7 +1265,9 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1262 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 1265 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1263 sizeof(uint16_t); 1266 sizeof(uint16_t);
1264 } else if (IS_FWI2_CAPABLE(ha)) { 1267 } else if (IS_FWI2_CAPABLE(ha)) {
1265 if (IS_QLA81XX(ha)) 1268 if (IS_QLA83XX(ha))
1269 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1270 else if (IS_QLA81XX(ha))
1266 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 1271 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1267 else if (IS_QLA25XX(ha)) 1272 else if (IS_QLA25XX(ha))
1268 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 1273 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
@@ -1271,7 +1276,8 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1271 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 1276 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1272 sizeof(uint32_t); 1277 sizeof(uint32_t);
1273 if (ha->mqenable) { 1278 if (ha->mqenable) {
1274 mq_size = sizeof(struct qla2xxx_mq_chain); 1279 if (!IS_QLA83XX(ha))
1280 mq_size = sizeof(struct qla2xxx_mq_chain);
1275 /* 1281 /*
1276 * Allocate maximum buffer size for all queues. 1282 * Allocate maximum buffer size for all queues.
1277 * Resizing must be done at end-of-dump processing. 1283 * Resizing must be done at end-of-dump processing.
@@ -1282,7 +1288,7 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1282 (rsp->length * sizeof(response_t)); 1288 (rsp->length * sizeof(response_t));
1283 } 1289 }
1284 /* Allocate memory for Fibre Channel Event Buffer. */ 1290 /* Allocate memory for Fibre Channel Event Buffer. */
1285 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)) 1291 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
1286 goto try_eft; 1292 goto try_eft;
1287 1293
1288 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 1294 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
@@ -1493,17 +1499,8 @@ enable_82xx_npiv:
1493 fw_major_version = ha->fw_major_version; 1499 fw_major_version = ha->fw_major_version;
1494 if (IS_QLA82XX(ha)) 1500 if (IS_QLA82XX(ha))
1495 qla82xx_check_md_needed(vha); 1501 qla82xx_check_md_needed(vha);
1496 else { 1502 else
1497 rval = qla2x00_get_fw_version(vha, 1503 rval = qla2x00_get_fw_version(vha);
1498 &ha->fw_major_version,
1499 &ha->fw_minor_version,
1500 &ha->fw_subminor_version,
1501 &ha->fw_attributes,
1502 &ha->fw_memory_size,
1503 ha->mpi_version,
1504 &ha->mpi_capabilities,
1505 ha->phy_version);
1506 }
1507 if (rval != QLA_SUCCESS) 1504 if (rval != QLA_SUCCESS)
1508 goto failed; 1505 goto failed;
1509 ha->flags.npiv_supported = 0; 1506 ha->flags.npiv_supported = 0;
@@ -1544,6 +1541,9 @@ enable_82xx_npiv:
1544 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1541 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1545 } 1542 }
1546 1543
1544 if (IS_QLA83XX(ha))
1545 goto skip_fac_check;
1546
1547 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 1547 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1548 uint32_t size; 1548 uint32_t size;
1549 1549
@@ -1556,6 +1556,11 @@ enable_82xx_npiv:
1556 "Unsupported FAC firmware (%d.%02d.%02d).\n", 1556 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1557 ha->fw_major_version, ha->fw_minor_version, 1557 ha->fw_major_version, ha->fw_minor_version,
1558 ha->fw_subminor_version); 1558 ha->fw_subminor_version);
1559skip_fac_check:
1560 if (IS_QLA83XX(ha)) {
1561 ha->flags.fac_supported = 0;
1562 rval = QLA_SUCCESS;
1563 }
1559 } 1564 }
1560 } 1565 }
1561failed: 1566failed:
@@ -1734,7 +1739,7 @@ qla24xx_config_rings(struct scsi_qla_host *vha)
1734 struct req_que *req = ha->req_q_map[0]; 1739 struct req_que *req = ha->req_q_map[0];
1735 struct rsp_que *rsp = ha->rsp_q_map[0]; 1740 struct rsp_que *rsp = ha->rsp_q_map[0];
1736 1741
1737/* Setup ring parameters in initialization control block. */ 1742 /* Setup ring parameters in initialization control block. */
1738 icb = (struct init_cb_24xx *)ha->init_cb; 1743 icb = (struct init_cb_24xx *)ha->init_cb;
1739 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1744 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1740 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1745 icb->response_q_inpointer = __constant_cpu_to_le16(0);
@@ -1745,7 +1750,7 @@ qla24xx_config_rings(struct scsi_qla_host *vha)
1745 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1750 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1746 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1751 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1747 1752
1748 if (ha->mqenable) { 1753 if (ha->mqenable || IS_QLA83XX(ha)) {
1749 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS); 1754 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1750 icb->rid = __constant_cpu_to_le16(rid); 1755 icb->rid = __constant_cpu_to_le16(rid);
1751 if (ha->flags.msix_enabled) { 1756 if (ha->flags.msix_enabled) {
@@ -1765,7 +1770,8 @@ qla24xx_config_rings(struct scsi_qla_host *vha)
1765 __constant_cpu_to_le32(BIT_18); 1770 __constant_cpu_to_le32(BIT_18);
1766 1771
1767 /* Use Disable MSIX Handshake mode for capable adapters */ 1772 /* Use Disable MSIX Handshake mode for capable adapters */
1768 if (IS_MSIX_NACK_CAPABLE(ha)) { 1773 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1774 (ha->flags.msix_enabled)) {
1769 icb->firmware_options_2 &= 1775 icb->firmware_options_2 &=
1770 __constant_cpu_to_le32(~BIT_22); 1776 __constant_cpu_to_le32(~BIT_22);
1771 ha->flags.disable_msix_handshake = 1; 1777 ha->flags.disable_msix_handshake = 1;
@@ -2037,7 +2043,7 @@ qla2x00_configure_hba(scsi_qla_host_t *vha)
2037 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 2043 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
2038 if (rval != QLA_SUCCESS) { 2044 if (rval != QLA_SUCCESS) {
2039 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 2045 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
2040 IS_QLA8XXX_TYPE(ha) || 2046 IS_CNA_CAPABLE(ha) ||
2041 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 2047 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
2042 ql_dbg(ql_dbg_disc, vha, 0x2008, 2048 ql_dbg(ql_dbg_disc, vha, 0x2008,
2043 "Loop is in a transition state.\n"); 2049 "Loop is in a transition state.\n");
@@ -2129,7 +2135,7 @@ qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2129 uint16_t index; 2135 uint16_t index;
2130 struct qla_hw_data *ha = vha->hw; 2136 struct qla_hw_data *ha = vha->hw;
2131 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 2137 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
2132 !IS_QLA8XXX_TYPE(ha); 2138 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
2133 2139
2134 if (memcmp(model, BINZERO, len) != 0) { 2140 if (memcmp(model, BINZERO, len) != 0) {
2135 strncpy(ha->model_number, model, len); 2141 strncpy(ha->model_number, model, len);
@@ -4109,15 +4115,8 @@ qla2x00_abort_isp(scsi_qla_host_t *vha)
4109 ha->isp_abort_cnt = 0; 4115 ha->isp_abort_cnt = 0;
4110 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4116 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4111 4117
4112 if (IS_QLA81XX(ha)) 4118 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4113 qla2x00_get_fw_version(vha, 4119 qla2x00_get_fw_version(vha);
4114 &ha->fw_major_version,
4115 &ha->fw_minor_version,
4116 &ha->fw_subminor_version,
4117 &ha->fw_attributes, &ha->fw_memory_size,
4118 ha->mpi_version, &ha->mpi_capabilities,
4119 ha->phy_version);
4120
4121 if (ha->fce) { 4120 if (ha->fce) {
4122 ha->flags.fce_enabled = 1; 4121 ha->flags.fce_enabled = 1;
4123 memset(ha->fce, 0, 4122 memset(ha->fce, 0,
@@ -4983,7 +4982,6 @@ try_blob_fw:
4983 4982
4984 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); 4983 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
4985 ha->flags.running_gold_fw = 1; 4984 ha->flags.running_gold_fw = 1;
4986
4987 return rval; 4985 return rval;
4988} 4986}
4989 4987
@@ -5223,10 +5221,10 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
5223 nv->reset_delay = 5; 5221 nv->reset_delay = 5;
5224 nv->max_luns_per_target = __constant_cpu_to_le16(128); 5222 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5225 nv->port_down_retry_count = __constant_cpu_to_le16(30); 5223 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5226 nv->link_down_timeout = __constant_cpu_to_le16(30); 5224 nv->link_down_timeout = __constant_cpu_to_le16(180);
5227 nv->enode_mac[0] = 0x00; 5225 nv->enode_mac[0] = 0x00;
5228 nv->enode_mac[1] = 0x02; 5226 nv->enode_mac[1] = 0xC0;
5229 nv->enode_mac[2] = 0x03; 5227 nv->enode_mac[2] = 0xDD;
5230 nv->enode_mac[3] = 0x04; 5228 nv->enode_mac[3] = 0x04;
5231 nv->enode_mac[4] = 0x05; 5229 nv->enode_mac[4] = 0x05;
5232 nv->enode_mac[5] = 0x06 + ha->port_no; 5230 nv->enode_mac[5] = 0x06 + ha->port_no;
@@ -5362,6 +5360,10 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
5362 if (ql2xloginretrycount) 5360 if (ql2xloginretrycount)
5363 ha->login_retry_count = ql2xloginretrycount; 5361 ha->login_retry_count = ql2xloginretrycount;
5364 5362
5363 /* if not running MSI-X we need handshaking on interrupts */
5364 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5365 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5366
5365 /* Enable ZIO. */ 5367 /* Enable ZIO. */
5366 if (!vha->flags.init_done) { 5368 if (!vha->flags.init_done) {
5367 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 5369 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c
index 55a96761b5a4..a281b5422df1 100644
--- a/drivers/scsi/qla2xxx/qla_iocb.c
+++ b/drivers/scsi/qla2xxx/qla_iocb.c
@@ -473,7 +473,6 @@ qla2x00_start_iocbs(struct scsi_qla_host *vha, struct req_que *req)
473{ 473{
474 struct qla_hw_data *ha = vha->hw; 474 struct qla_hw_data *ha = vha->hw;
475 device_reg_t __iomem *reg = ISP_QUE_REG(ha, req->id); 475 device_reg_t __iomem *reg = ISP_QUE_REG(ha, req->id);
476 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
477 476
478 if (IS_QLA82XX(ha)) { 477 if (IS_QLA82XX(ha)) {
479 qla82xx_start_iocbs(vha); 478 qla82xx_start_iocbs(vha);
@@ -487,9 +486,9 @@ qla2x00_start_iocbs(struct scsi_qla_host *vha, struct req_que *req)
487 req->ring_ptr++; 486 req->ring_ptr++;
488 487
489 /* Set chip new ring index. */ 488 /* Set chip new ring index. */
490 if (ha->mqenable) { 489 if (ha->mqenable || IS_QLA83XX(ha)) {
491 WRT_REG_DWORD(&reg->isp25mq.req_q_in, req->ring_index); 490 WRT_REG_DWORD(req->req_q_in, req->ring_index);
492 RD_REG_DWORD(&ioreg->hccr); 491 RD_REG_DWORD_RELAXED(&reg->isp24.req_q_in);
493 } else if (IS_FWI2_CAPABLE(ha)) { 492 } else if (IS_FWI2_CAPABLE(ha)) {
494 WRT_REG_DWORD(&reg->isp24.req_q_in, req->ring_index); 493 WRT_REG_DWORD(&reg->isp24.req_q_in, req->ring_index);
495 RD_REG_DWORD_RELAXED(&reg->isp24.req_q_in); 494 RD_REG_DWORD_RELAXED(&reg->isp24.req_q_in);
@@ -1856,7 +1855,7 @@ qla2x00_alloc_iocbs(scsi_qla_host_t *vha, srb_t *sp)
1856skip_cmd_array: 1855skip_cmd_array:
1857 /* Check for room on request queue. */ 1856 /* Check for room on request queue. */
1858 if (req->cnt < req_cnt) { 1857 if (req->cnt < req_cnt) {
1859 if (ha->mqenable) 1858 if (ha->mqenable || IS_QLA83XX(ha))
1860 cnt = RD_REG_DWORD(&reg->isp25mq.req_q_out); 1859 cnt = RD_REG_DWORD(&reg->isp25mq.req_q_out);
1861 else if (IS_QLA82XX(ha)) 1860 else if (IS_QLA82XX(ha))
1862 cnt = RD_REG_DWORD(&reg->isp82.req_q_out); 1861 cnt = RD_REG_DWORD(&reg->isp82.req_q_out);
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 349843ea32f6..18e7d961aa09 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -289,7 +289,7 @@ qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
289 mb[cnt] = RD_REG_WORD(wptr); 289 mb[cnt] = RD_REG_WORD(wptr);
290 290
291 ql_dbg(ql_dbg_async, vha, 0x5021, 291 ql_dbg(ql_dbg_async, vha, 0x5021,
292 "Inter-Driver Commucation %s -- " 292 "Inter-Driver Communication %s -- "
293 "%04x %04x %04x %04x %04x %04x %04x.\n", 293 "%04x %04x %04x %04x %04x %04x %04x.\n",
294 event[aen & 0xff], mb[0], mb[1], mb[2], mb[3], 294 event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
295 mb[4], mb[5], mb[6]); 295 mb[4], mb[5], mb[6]);
@@ -318,7 +318,7 @@ void
318qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb) 318qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
319{ 319{
320#define LS_UNKNOWN 2 320#define LS_UNKNOWN 2
321 static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" }; 321 static char *link_speeds[] = { "1", "2", "?", "4", "8", "16", "10" };
322 char *link_speed; 322 char *link_speed;
323 uint16_t handle_cnt; 323 uint16_t handle_cnt;
324 uint16_t cnt, mbx; 324 uint16_t cnt, mbx;
@@ -333,7 +333,7 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
333 333
334 /* Setup to process RIO completion. */ 334 /* Setup to process RIO completion. */
335 handle_cnt = 0; 335 handle_cnt = 0;
336 if (IS_QLA8XXX_TYPE(ha)) 336 if (IS_CNA_CAPABLE(ha))
337 goto skip_rio; 337 goto skip_rio;
338 switch (mb[0]) { 338 switch (mb[0]) {
339 case MBA_SCSI_COMPLETION: 339 case MBA_SCSI_COMPLETION:
@@ -405,7 +405,8 @@ skip_rio:
405 break; 405 break;
406 406
407 case MBA_SYSTEM_ERR: /* System Error */ 407 case MBA_SYSTEM_ERR: /* System Error */
408 mbx = IS_QLA81XX(ha) ? RD_REG_WORD(&reg24->mailbox7) : 0; 408 mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
409 RD_REG_WORD(&reg24->mailbox7) : 0;
409 ql_log(ql_log_warn, vha, 0x5003, 410 ql_log(ql_log_warn, vha, 0x5003,
410 "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh " 411 "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
411 "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx); 412 "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
@@ -418,6 +419,7 @@ skip_rio:
418 "Unrecoverable Hardware Error: adapter " 419 "Unrecoverable Hardware Error: adapter "
419 "marked OFFLINE!\n"); 420 "marked OFFLINE!\n");
420 vha->flags.online = 0; 421 vha->flags.online = 0;
422 vha->device_flags |= DFLG_DEV_FAILED;
421 } else { 423 } else {
422 /* Check to see if MPI timeout occurred */ 424 /* Check to see if MPI timeout occurred */
423 if ((mbx & MBX_3) && (ha->flags.port0)) 425 if ((mbx & MBX_3) && (ha->flags.port0))
@@ -431,6 +433,7 @@ skip_rio:
431 "Unrecoverable Hardware Error: adapter marked " 433 "Unrecoverable Hardware Error: adapter marked "
432 "OFFLINE!\n"); 434 "OFFLINE!\n");
433 vha->flags.online = 0; 435 vha->flags.online = 0;
436 vha->device_flags |= DFLG_DEV_FAILED;
434 } else 437 } else
435 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 438 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
436 break; 439 break;
@@ -482,10 +485,10 @@ skip_rio:
482 ha->link_data_rate = PORT_SPEED_1GB; 485 ha->link_data_rate = PORT_SPEED_1GB;
483 } else { 486 } else {
484 link_speed = link_speeds[LS_UNKNOWN]; 487 link_speed = link_speeds[LS_UNKNOWN];
485 if (mb[1] < 5) 488 if (mb[1] < 6)
486 link_speed = link_speeds[mb[1]]; 489 link_speed = link_speeds[mb[1]];
487 else if (mb[1] == 0x13) 490 else if (mb[1] == 0x13)
488 link_speed = link_speeds[5]; 491 link_speed = link_speeds[6];
489 ha->link_data_rate = mb[1]; 492 ha->link_data_rate = mb[1];
490 } 493 }
491 494
@@ -497,7 +500,8 @@ skip_rio:
497 break; 500 break;
498 501
499 case MBA_LOOP_DOWN: /* Loop Down Event */ 502 case MBA_LOOP_DOWN: /* Loop Down Event */
500 mbx = IS_QLA81XX(ha) ? RD_REG_WORD(&reg24->mailbox4) : 0; 503 mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
504 ? RD_REG_WORD(&reg24->mailbox4) : 0;
501 mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx; 505 mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
502 ql_dbg(ql_dbg_async, vha, 0x500b, 506 ql_dbg(ql_dbg_async, vha, 0x500b,
503 "LOOP DOWN detected (%x %x %x %x).\n", 507 "LOOP DOWN detected (%x %x %x %x).\n",
@@ -547,7 +551,7 @@ skip_rio:
547 if (IS_QLA2100(ha)) 551 if (IS_QLA2100(ha))
548 break; 552 break;
549 553
550 if (IS_QLA8XXX_TYPE(ha)) { 554 if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
551 ql_dbg(ql_dbg_async, vha, 0x500d, 555 ql_dbg(ql_dbg_async, vha, 0x500d,
552 "DCBX Completed -- %04x %04x %04x.\n", 556 "DCBX Completed -- %04x %04x %04x.\n",
553 mb[1], mb[2], mb[3]); 557 mb[1], mb[2], mb[3]);
@@ -809,6 +813,10 @@ skip_rio:
809 case MBA_IDC_TIME_EXT: 813 case MBA_IDC_TIME_EXT:
810 qla81xx_idc_event(vha, mb[0], mb[1]); 814 qla81xx_idc_event(vha, mb[0], mb[1]);
811 break; 815 break;
816 default:
817 ql_dbg(ql_dbg_async, vha, 0x5057,
818 "Unknown AEN:%04x %04x %04x %04x\n",
819 mb[0], mb[1], mb[2], mb[3]);
812 } 820 }
813 821
814 if (!vha->vp_idx && ha->num_vhosts) 822 if (!vha->vp_idx && ha->num_vhosts)
@@ -2127,7 +2135,7 @@ qla2xxx_check_risc_status(scsi_qla_host_t *vha)
2127 struct qla_hw_data *ha = vha->hw; 2135 struct qla_hw_data *ha = vha->hw;
2128 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2136 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2129 2137
2130 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)) 2138 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
2131 return; 2139 return;
2132 2140
2133 rval = QLA_SUCCESS; 2141 rval = QLA_SUCCESS;
@@ -2168,7 +2176,7 @@ done:
2168} 2176}
2169 2177
2170/** 2178/**
2171 * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2179 * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
2172 * @irq: 2180 * @irq:
2173 * @dev_id: SCSI driver HA context 2181 * @dev_id: SCSI driver HA context
2174 * 2182 *
@@ -2530,8 +2538,14 @@ msix_failed:
2530 } 2538 }
2531 2539
2532 /* Enable MSI-X vector for response queue update for queue 0 */ 2540 /* Enable MSI-X vector for response queue update for queue 0 */
2533 if (ha->mqiobase && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1)) 2541 if (IS_QLA83XX(ha)) {
2534 ha->mqenable = 1; 2542 if (ha->msixbase && ha->mqiobase &&
2543 (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
2544 ha->mqenable = 1;
2545 } else
2546 if (ha->mqiobase
2547 && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
2548 ha->mqenable = 1;
2535 ql_dbg(ql_dbg_multiq, vha, 0xc005, 2549 ql_dbg(ql_dbg_multiq, vha, 0xc005,
2536 "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n", 2550 "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
2537 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues); 2551 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
@@ -2552,8 +2566,8 @@ qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
2552 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2566 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2553 2567
2554 /* If possible, enable MSI-X. */ 2568 /* If possible, enable MSI-X. */
2555 if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && 2569 if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
2556 !IS_QLA8432(ha) && !IS_QLA8XXX_TYPE(ha)) 2570 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
2557 goto skip_msi; 2571 goto skip_msi;
2558 2572
2559 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 2573 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
@@ -2615,7 +2629,7 @@ clear_risc_ints:
2615 * FIXME: Noted that 8014s were being dropped during NK testing. 2629 * FIXME: Noted that 8014s were being dropped during NK testing.
2616 * Timing deltas during MSI-X/INTa transitions? 2630 * Timing deltas during MSI-X/INTa transitions?
2617 */ 2631 */
2618 if (IS_QLA81XX(ha) || IS_QLA82XX(ha)) 2632 if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA83XX(ha))
2619 goto fail; 2633 goto fail;
2620 spin_lock_irq(&ha->hardware_lock); 2634 spin_lock_irq(&ha->hardware_lock);
2621 if (IS_FWI2_CAPABLE(ha)) { 2635 if (IS_FWI2_CAPABLE(ha)) {
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index 08f1d01bdc1c..be520a9d0b71 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -364,8 +364,8 @@ premature_exit:
364mbx_done: 364mbx_done:
365 if (rval) { 365 if (rval) {
366 ql_dbg(ql_dbg_mbx, base_vha, 0x1020, 366 ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
367 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, cmd=%x ****.\n", 367 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
368 mcp->mb[0], mcp->mb[1], mcp->mb[2], command); 368 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
369 } else { 369 } else {
370 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 370 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
371 } 371 }
@@ -455,7 +455,7 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
455 mcp->mb[1] = MSW(risc_addr); 455 mcp->mb[1] = MSW(risc_addr);
456 mcp->mb[2] = LSW(risc_addr); 456 mcp->mb[2] = LSW(risc_addr);
457 mcp->mb[3] = 0; 457 mcp->mb[3] = 0;
458 if (IS_QLA81XX(ha)) { 458 if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
459 struct nvram_81xx *nv = ha->nvram; 459 struct nvram_81xx *nv = ha->nvram;
460 mcp->mb[4] = (nv->enhanced_features & 460 mcp->mb[4] = (nv->enhanced_features &
461 EXTENDED_BB_CREDITS); 461 EXTENDED_BB_CREDITS);
@@ -508,21 +508,22 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
508 * Kernel context. 508 * Kernel context.
509 */ 509 */
510int 510int
511qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor, 511qla2x00_get_fw_version(scsi_qla_host_t *vha)
512 uint16_t *subminor, uint16_t *attributes, uint32_t *memory, uint8_t *mpi,
513 uint32_t *mpi_caps, uint8_t *phy)
514{ 512{
515 int rval; 513 int rval;
516 mbx_cmd_t mc; 514 mbx_cmd_t mc;
517 mbx_cmd_t *mcp = &mc; 515 mbx_cmd_t *mcp = &mc;
516 struct qla_hw_data *ha = vha->hw;
518 517
519 ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__); 518 ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__);
520 519
521 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 520 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
522 mcp->out_mb = MBX_0; 521 mcp->out_mb = MBX_0;
523 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 522 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
524 if (IS_QLA81XX(vha->hw)) 523 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha))
525 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 524 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
525 if (IS_QLA83XX(vha->hw))
526 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
526 mcp->flags = 0; 527 mcp->flags = 0;
527 mcp->tov = MBX_TOV_SECONDS; 528 mcp->tov = MBX_TOV_SECONDS;
528 rval = qla2x00_mailbox_command(vha, mcp); 529 rval = qla2x00_mailbox_command(vha, mcp);
@@ -530,23 +531,37 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
530 goto failed; 531 goto failed;
531 532
532 /* Return mailbox data. */ 533 /* Return mailbox data. */
533 *major = mcp->mb[1]; 534 ha->fw_major_version = mcp->mb[1];
534 *minor = mcp->mb[2]; 535 ha->fw_minor_version = mcp->mb[2];
535 *subminor = mcp->mb[3]; 536 ha->fw_subminor_version = mcp->mb[3];
536 *attributes = mcp->mb[6]; 537 ha->fw_attributes = mcp->mb[6];
537 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 538 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
538 *memory = 0x1FFFF; /* Defaults to 128KB. */ 539 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
539 else 540 else
540 *memory = (mcp->mb[5] << 16) | mcp->mb[4]; 541 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
541 if (IS_QLA81XX(vha->hw)) { 542 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) {
542 mpi[0] = mcp->mb[10] & 0xff; 543 ha->mpi_version[0] = mcp->mb[10] & 0xff;
543 mpi[1] = mcp->mb[11] >> 8; 544 ha->mpi_version[1] = mcp->mb[11] >> 8;
544 mpi[2] = mcp->mb[11] & 0xff; 545 ha->mpi_version[2] = mcp->mb[11] & 0xff;
545 *mpi_caps = (mcp->mb[12] << 16) | mcp->mb[13]; 546 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
546 phy[0] = mcp->mb[8] & 0xff; 547 ha->phy_version[0] = mcp->mb[8] & 0xff;
547 phy[1] = mcp->mb[9] >> 8; 548 ha->phy_version[1] = mcp->mb[9] >> 8;
548 phy[2] = mcp->mb[9] & 0xff; 549 ha->phy_version[2] = mcp->mb[9] & 0xff;
550 }
551 if (IS_QLA83XX(ha)) {
552 if (mcp->mb[6] & BIT_15) {
553 ha->fw_attributes_h = mcp->mb[15];
554 ha->fw_attributes_ext[0] = mcp->mb[16];
555 ha->fw_attributes_ext[1] = mcp->mb[17];
556 ql_dbg(ql_dbg_mbx, vha, 0x1139,
557 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
558 __func__, mcp->mb[15], mcp->mb[6]);
559 } else
560 ql_dbg(ql_dbg_mbx, vha, 0x112f,
561 "%s: FwAttributes [Upper] invalid, MB6:%04x\n",
562 __func__, mcp->mb[6]);
549 } 563 }
564
550failed: 565failed:
551 if (rval != QLA_SUCCESS) { 566 if (rval != QLA_SUCCESS) {
552 /*EMPTY*/ 567 /*EMPTY*/
@@ -1028,7 +1043,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1028 mcp->mb[9] = vha->vp_idx; 1043 mcp->mb[9] = vha->vp_idx;
1029 mcp->out_mb = MBX_9|MBX_0; 1044 mcp->out_mb = MBX_9|MBX_0;
1030 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1045 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1031 if (IS_QLA8XXX_TYPE(vha->hw)) 1046 if (IS_CNA_CAPABLE(vha->hw))
1032 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1047 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1033 mcp->tov = MBX_TOV_SECONDS; 1048 mcp->tov = MBX_TOV_SECONDS;
1034 mcp->flags = 0; 1049 mcp->flags = 0;
@@ -1052,7 +1067,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1052 } else { 1067 } else {
1053 ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__); 1068 ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__);
1054 1069
1055 if (IS_QLA8XXX_TYPE(vha->hw)) { 1070 if (IS_CNA_CAPABLE(vha->hw)) {
1056 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1071 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1057 vha->fcoe_fcf_idx = mcp->mb[10]; 1072 vha->fcoe_fcf_idx = mcp->mb[10];
1058 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1073 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
@@ -1163,7 +1178,7 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1163 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1178 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1164 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1179 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1165 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1180 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1166 if (IS_QLA81XX(ha) && ha->ex_init_cb->ex_version) { 1181 if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
1167 mcp->mb[1] = BIT_0; 1182 mcp->mb[1] = BIT_0;
1168 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1183 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1169 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1184 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
@@ -1172,7 +1187,11 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1172 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1187 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1173 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1188 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1174 } 1189 }
1175 mcp->in_mb = MBX_0; 1190 /* 1 and 2 should normally be captured. */
1191 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1192 if (IS_QLA83XX(ha))
1193 /* mb3 is additional info about the installed SFP. */
1194 mcp->in_mb |= MBX_3;
1176 mcp->buf_size = size; 1195 mcp->buf_size = size;
1177 mcp->flags = MBX_DMA_OUT; 1196 mcp->flags = MBX_DMA_OUT;
1178 mcp->tov = MBX_TOV_SECONDS; 1197 mcp->tov = MBX_TOV_SECONDS;
@@ -1181,7 +1200,8 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1181 if (rval != QLA_SUCCESS) { 1200 if (rval != QLA_SUCCESS) {
1182 /*EMPTY*/ 1201 /*EMPTY*/
1183 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1202 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1184 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1203 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1204 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1185 } else { 1205 } else {
1186 /*EMPTY*/ 1206 /*EMPTY*/
1187 ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__); 1207 ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__);
@@ -1481,7 +1501,7 @@ qla2x00_lip_reset(scsi_qla_host_t *vha)
1481 1501
1482 ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__); 1502 ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__);
1483 1503
1484 if (IS_QLA8XXX_TYPE(vha->hw)) { 1504 if (IS_CNA_CAPABLE(vha->hw)) {
1485 /* Logout across all FCFs. */ 1505 /* Logout across all FCFs. */
1486 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1506 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1487 mcp->mb[1] = BIT_1; 1507 mcp->mb[1] = BIT_1;
@@ -2094,7 +2114,7 @@ qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
2094 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2114 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2095 mcp->out_mb = MBX_0; 2115 mcp->out_mb = MBX_0;
2096 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2116 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2097 if (IS_QLA81XX(vha->hw)) 2117 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
2098 mcp->in_mb |= MBX_12; 2118 mcp->in_mb |= MBX_12;
2099 mcp->tov = MBX_TOV_SECONDS; 2119 mcp->tov = MBX_TOV_SECONDS;
2100 mcp->flags = 0; 2120 mcp->flags = 0;
@@ -2121,7 +2141,7 @@ qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
2121 *orig_iocb_cnt = mcp->mb[10]; 2141 *orig_iocb_cnt = mcp->mb[10];
2122 if (vha->hw->flags.npiv_supported && max_npiv_vports) 2142 if (vha->hw->flags.npiv_supported && max_npiv_vports)
2123 *max_npiv_vports = mcp->mb[11]; 2143 *max_npiv_vports = mcp->mb[11];
2124 if (IS_QLA81XX(vha->hw) && max_fcfs) 2144 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
2125 *max_fcfs = mcp->mb[12]; 2145 *max_fcfs = mcp->mb[12];
2126 } 2146 }
2127 2147
@@ -2686,7 +2706,8 @@ qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
2686 2706
2687 ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__); 2707 ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__);
2688 2708
2689 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw)) 2709 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
2710 !IS_QLA83XX(vha->hw))
2690 return QLA_FUNCTION_FAILED; 2711 return QLA_FUNCTION_FAILED;
2691 2712
2692 if (unlikely(pci_channel_offline(vha->hw->pdev))) 2713 if (unlikely(pci_channel_offline(vha->hw->pdev)))
@@ -2828,7 +2849,7 @@ qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
2828 mcp->mb[0] = MBC_PORT_PARAMS; 2849 mcp->mb[0] = MBC_PORT_PARAMS;
2829 mcp->mb[1] = loop_id; 2850 mcp->mb[1] = loop_id;
2830 mcp->mb[2] = BIT_0; 2851 mcp->mb[2] = BIT_0;
2831 if (IS_QLA8XXX_TYPE(vha->hw)) 2852 if (IS_CNA_CAPABLE(vha->hw))
2832 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 2853 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
2833 else 2854 else
2834 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 2855 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
@@ -3298,6 +3319,8 @@ qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
3298 mcp->mb[12] = req->qos; 3319 mcp->mb[12] = req->qos;
3299 mcp->mb[11] = req->vp_idx; 3320 mcp->mb[11] = req->vp_idx;
3300 mcp->mb[13] = req->rid; 3321 mcp->mb[13] = req->rid;
3322 if (IS_QLA83XX(ha))
3323 mcp->mb[15] = 0;
3301 3324
3302 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) + 3325 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
3303 QLA_QUE_PAGE * req->id); 3326 QLA_QUE_PAGE * req->id);
@@ -3311,12 +3334,21 @@ qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
3311 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3334 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3312 mcp->in_mb = MBX_0; 3335 mcp->in_mb = MBX_0;
3313 mcp->flags = MBX_DMA_OUT; 3336 mcp->flags = MBX_DMA_OUT;
3314 mcp->tov = 60; 3337 mcp->tov = MBX_TOV_SECONDS * 2;
3338
3339 if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
3340 mcp->in_mb |= MBX_1;
3341 if (IS_QLA83XX(ha)) {
3342 mcp->out_mb |= MBX_15;
3343 /* debug q create issue in SR-IOV */
3344 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3345 }
3315 3346
3316 spin_lock_irqsave(&ha->hardware_lock, flags); 3347 spin_lock_irqsave(&ha->hardware_lock, flags);
3317 if (!(req->options & BIT_0)) { 3348 if (!(req->options & BIT_0)) {
3318 WRT_REG_DWORD(&reg->req_q_in, 0); 3349 WRT_REG_DWORD(&reg->req_q_in, 0);
3319 WRT_REG_DWORD(&reg->req_q_out, 0); 3350 if (!IS_QLA83XX(ha))
3351 WRT_REG_DWORD(&reg->req_q_out, 0);
3320 } 3352 }
3321 req->req_q_in = &reg->req_q_in; 3353 req->req_q_in = &reg->req_q_in;
3322 req->req_q_out = &reg->req_q_out; 3354 req->req_q_out = &reg->req_q_out;
@@ -3354,6 +3386,8 @@ qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
3354 mcp->mb[5] = rsp->length; 3386 mcp->mb[5] = rsp->length;
3355 mcp->mb[14] = rsp->msix->entry; 3387 mcp->mb[14] = rsp->msix->entry;
3356 mcp->mb[13] = rsp->rid; 3388 mcp->mb[13] = rsp->rid;
3389 if (IS_QLA83XX(ha))
3390 mcp->mb[15] = 0;
3357 3391
3358 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) + 3392 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
3359 QLA_QUE_PAGE * rsp->id); 3393 QLA_QUE_PAGE * rsp->id);
@@ -3367,12 +3401,23 @@ qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
3367 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3401 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3368 mcp->in_mb = MBX_0; 3402 mcp->in_mb = MBX_0;
3369 mcp->flags = MBX_DMA_OUT; 3403 mcp->flags = MBX_DMA_OUT;
3370 mcp->tov = 60; 3404 mcp->tov = MBX_TOV_SECONDS * 2;
3405
3406 if (IS_QLA81XX(ha)) {
3407 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
3408 mcp->in_mb |= MBX_1;
3409 } else if (IS_QLA83XX(ha)) {
3410 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
3411 mcp->in_mb |= MBX_1;
3412 /* debug q create issue in SR-IOV */
3413 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3414 }
3371 3415
3372 spin_lock_irqsave(&ha->hardware_lock, flags); 3416 spin_lock_irqsave(&ha->hardware_lock, flags);
3373 if (!(rsp->options & BIT_0)) { 3417 if (!(rsp->options & BIT_0)) {
3374 WRT_REG_DWORD(&reg->rsp_q_out, 0); 3418 WRT_REG_DWORD(&reg->rsp_q_out, 0);
3375 WRT_REG_DWORD(&reg->rsp_q_in, 0); 3419 if (!IS_QLA83XX(ha))
3420 WRT_REG_DWORD(&reg->rsp_q_in, 0);
3376 } 3421 }
3377 3422
3378 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3423 spin_unlock_irqrestore(&ha->hardware_lock, flags);
@@ -3424,7 +3469,7 @@ qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3424 3469
3425 ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__); 3470 ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__);
3426 3471
3427 if (!IS_QLA81XX(vha->hw)) 3472 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
3428 return QLA_FUNCTION_FAILED; 3473 return QLA_FUNCTION_FAILED;
3429 3474
3430 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3475 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
@@ -3454,7 +3499,7 @@ qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3454 mbx_cmd_t mc; 3499 mbx_cmd_t mc;
3455 mbx_cmd_t *mcp = &mc; 3500 mbx_cmd_t *mcp = &mc;
3456 3501
3457 if (!IS_QLA81XX(vha->hw)) 3502 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
3458 return QLA_FUNCTION_FAILED; 3503 return QLA_FUNCTION_FAILED;
3459 3504
3460 ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__); 3505 ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__);
@@ -3486,7 +3531,7 @@ qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3486 mbx_cmd_t mc; 3531 mbx_cmd_t mc;
3487 mbx_cmd_t *mcp = &mc; 3532 mbx_cmd_t *mcp = &mc;
3488 3533
3489 if (!IS_QLA81XX(vha->hw)) 3534 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
3490 return QLA_FUNCTION_FAILED; 3535 return QLA_FUNCTION_FAILED;
3491 3536
3492 ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__); 3537 ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__);
@@ -3641,7 +3686,7 @@ qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
3641 3686
3642 ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__); 3687 ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__);
3643 3688
3644 if (!IS_QLA8XXX_TYPE(vha->hw)) 3689 if (!IS_CNA_CAPABLE(vha->hw))
3645 return QLA_FUNCTION_FAILED; 3690 return QLA_FUNCTION_FAILED;
3646 3691
3647 mcp->mb[0] = MBC_GET_XGMAC_STATS; 3692 mcp->mb[0] = MBC_GET_XGMAC_STATS;
@@ -3680,7 +3725,7 @@ qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
3680 3725
3681 ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__); 3726 ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__);
3682 3727
3683 if (!IS_QLA8XXX_TYPE(vha->hw)) 3728 if (!IS_CNA_CAPABLE(vha->hw))
3684 return QLA_FUNCTION_FAILED; 3729 return QLA_FUNCTION_FAILED;
3685 3730
3686 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 3731 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
@@ -3775,7 +3820,7 @@ qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3775 3820
3776 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 3821 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
3777 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 3822 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
3778 if (IS_QLA8XXX_TYPE(vha->hw)) 3823 if (IS_CNA_CAPABLE(vha->hw))
3779 mcp->out_mb |= MBX_2; 3824 mcp->out_mb |= MBX_2;
3780 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 3825 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
3781 3826
@@ -3813,7 +3858,7 @@ qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3813 memset(mcp->mb, 0 , sizeof(mcp->mb)); 3858 memset(mcp->mb, 0 , sizeof(mcp->mb));
3814 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 3859 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
3815 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 3860 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
3816 if (IS_QLA8XXX_TYPE(ha)) { 3861 if (IS_CNA_CAPABLE(ha)) {
3817 mcp->mb[1] |= BIT_15; 3862 mcp->mb[1] |= BIT_15;
3818 mcp->mb[2] = vha->fcoe_fcf_idx; 3863 mcp->mb[2] = vha->fcoe_fcf_idx;
3819 } 3864 }
@@ -3831,13 +3876,14 @@ qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3831 3876
3832 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 3877 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
3833 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 3878 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
3834 if (IS_QLA8XXX_TYPE(ha)) 3879 if (IS_CNA_CAPABLE(ha))
3835 mcp->out_mb |= MBX_2; 3880 mcp->out_mb |= MBX_2;
3836 3881
3837 mcp->in_mb = MBX_0; 3882 mcp->in_mb = MBX_0;
3838 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha)) 3883 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
3884 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
3839 mcp->in_mb |= MBX_1; 3885 mcp->in_mb |= MBX_1;
3840 if (IS_QLA8XXX_TYPE(ha)) 3886 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
3841 mcp->in_mb |= MBX_3; 3887 mcp->in_mb |= MBX_3;
3842 3888
3843 mcp->tov = MBX_TOV_SECONDS; 3889 mcp->tov = MBX_TOV_SECONDS;
@@ -3976,6 +4022,7 @@ qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
3976 4022
3977 return rval; 4023 return rval;
3978} 4024}
4025
3979int 4026int
3980qla2x00_get_data_rate(scsi_qla_host_t *vha) 4027qla2x00_get_data_rate(scsi_qla_host_t *vha)
3981{ 4028{
@@ -3993,6 +4040,8 @@ qla2x00_get_data_rate(scsi_qla_host_t *vha)
3993 mcp->mb[1] = 0; 4040 mcp->mb[1] = 0;
3994 mcp->out_mb = MBX_1|MBX_0; 4041 mcp->out_mb = MBX_1|MBX_0;
3995 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4042 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4043 if (IS_QLA83XX(ha))
4044 mcp->in_mb |= MBX_3;
3996 mcp->tov = MBX_TOV_SECONDS; 4045 mcp->tov = MBX_TOV_SECONDS;
3997 mcp->flags = 0; 4046 mcp->flags = 0;
3998 rval = qla2x00_mailbox_command(vha, mcp); 4047 rval = qla2x00_mailbox_command(vha, mcp);
@@ -4018,7 +4067,7 @@ qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4018 4067
4019 ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__); 4068 ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__);
4020 4069
4021 if (!IS_QLA81XX(ha)) 4070 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
4022 return QLA_FUNCTION_FAILED; 4071 return QLA_FUNCTION_FAILED;
4023 mcp->mb[0] = MBC_GET_PORT_CONFIG; 4072 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4024 mcp->out_mb = MBX_0; 4073 mcp->out_mb = MBX_0;
@@ -4299,6 +4348,90 @@ qla82xx_md_get_template(scsi_qla_host_t *vha)
4299} 4348}
4300 4349
4301int 4350int
4351qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4352{
4353 int rval;
4354 struct qla_hw_data *ha = vha->hw;
4355 mbx_cmd_t mc;
4356 mbx_cmd_t *mcp = &mc;
4357
4358 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4359 return QLA_FUNCTION_FAILED;
4360
4361 ql_dbg(ql_dbg_mbx, vha, 0x1133, "Entered %s.\n", __func__);
4362
4363 memset(mcp, 0, sizeof(mbx_cmd_t));
4364 mcp->mb[0] = MBC_SET_LED_CONFIG;
4365 mcp->mb[1] = led_cfg[0];
4366 mcp->mb[2] = led_cfg[1];
4367 if (IS_QLA8031(ha)) {
4368 mcp->mb[3] = led_cfg[2];
4369 mcp->mb[4] = led_cfg[3];
4370 mcp->mb[5] = led_cfg[4];
4371 mcp->mb[6] = led_cfg[5];
4372 }
4373
4374 mcp->out_mb = MBX_2|MBX_1|MBX_0;
4375 if (IS_QLA8031(ha))
4376 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4377 mcp->in_mb = MBX_0;
4378 mcp->tov = 30;
4379 mcp->flags = 0;
4380
4381 rval = qla2x00_mailbox_command(vha, mcp);
4382 if (rval != QLA_SUCCESS) {
4383 ql_dbg(ql_dbg_mbx, vha, 0x1134,
4384 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4385 } else {
4386 ql_dbg(ql_dbg_mbx, vha, 0x1135, "Done %s.\n", __func__);
4387 }
4388
4389 return rval;
4390}
4391
4392int
4393qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4394{
4395 int rval;
4396 struct qla_hw_data *ha = vha->hw;
4397 mbx_cmd_t mc;
4398 mbx_cmd_t *mcp = &mc;
4399
4400 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4401 return QLA_FUNCTION_FAILED;
4402
4403 ql_dbg(ql_dbg_mbx, vha, 0x1136, "Entered %s.\n", __func__);
4404
4405 memset(mcp, 0, sizeof(mbx_cmd_t));
4406 mcp->mb[0] = MBC_GET_LED_CONFIG;
4407
4408 mcp->out_mb = MBX_0;
4409 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4410 if (IS_QLA8031(ha))
4411 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4412 mcp->tov = 30;
4413 mcp->flags = 0;
4414
4415 rval = qla2x00_mailbox_command(vha, mcp);
4416 if (rval != QLA_SUCCESS) {
4417 ql_dbg(ql_dbg_mbx, vha, 0x1137,
4418 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4419 } else {
4420 led_cfg[0] = mcp->mb[1];
4421 led_cfg[1] = mcp->mb[2];
4422 if (IS_QLA8031(ha)) {
4423 led_cfg[2] = mcp->mb[3];
4424 led_cfg[3] = mcp->mb[4];
4425 led_cfg[4] = mcp->mb[5];
4426 led_cfg[5] = mcp->mb[6];
4427 }
4428 ql_dbg(ql_dbg_mbx, vha, 0x1138, "Done %s.\n", __func__);
4429 }
4430
4431 return rval;
4432}
4433
4434int
4302qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 4435qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4303{ 4436{
4304 int rval; 4437 int rval;
@@ -4321,7 +4454,7 @@ qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4321 4454
4322 mcp->out_mb = MBX_7|MBX_0; 4455 mcp->out_mb = MBX_7|MBX_0;
4323 mcp->in_mb = MBX_0; 4456 mcp->in_mb = MBX_0;
4324 mcp->tov = 30; 4457 mcp->tov = MBX_TOV_SECONDS;
4325 mcp->flags = 0; 4458 mcp->flags = 0;
4326 4459
4327 rval = qla2x00_mailbox_command(vha, mcp); 4460 rval = qla2x00_mailbox_command(vha, mcp);
@@ -4335,3 +4468,38 @@ qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4335 4468
4336 return rval; 4469 return rval;
4337} 4470}
4471
4472int
4473qla83xx_write_remote_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
4474{
4475 int rval;
4476 struct qla_hw_data *ha = vha->hw;
4477 mbx_cmd_t mc;
4478 mbx_cmd_t *mcp = &mc;
4479
4480 if (!IS_QLA83XX(ha))
4481 return QLA_FUNCTION_FAILED;
4482
4483 ql_dbg(ql_dbg_mbx, vha, 0x1130, "Entered %s.\n", __func__);
4484
4485 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
4486 mcp->mb[1] = LSW(reg);
4487 mcp->mb[2] = MSW(reg);
4488 mcp->mb[3] = LSW(data);
4489 mcp->mb[4] = MSW(data);
4490 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4491
4492 mcp->in_mb = MBX_1|MBX_0;
4493 mcp->tov = MBX_TOV_SECONDS;
4494 mcp->flags = 0;
4495 rval = qla2x00_mailbox_command(vha, mcp);
4496
4497 if (rval != QLA_SUCCESS) {
4498 ql_dbg(ql_dbg_mbx, vha, 0x1131,
4499 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4500 } else {
4501 ql_dbg(ql_dbg_mbx, vha, 0x1132,
4502 "Done %s.\n", __func__);
4503 }
4504 return rval;
4505}
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
index 270ba3130fde..34fb91904fd9 100644
--- a/drivers/scsi/qla2xxx/qla_nx.c
+++ b/drivers/scsi/qla2xxx/qla_nx.c
@@ -3136,12 +3136,7 @@ qla82xx_check_md_needed(scsi_qla_host_t *vha)
3136 fw_minor_version = ha->fw_minor_version; 3136 fw_minor_version = ha->fw_minor_version;
3137 fw_subminor_version = ha->fw_subminor_version; 3137 fw_subminor_version = ha->fw_subminor_version;
3138 3138
3139 rval = qla2x00_get_fw_version(vha, &ha->fw_major_version, 3139 rval = qla2x00_get_fw_version(vha);
3140 &ha->fw_minor_version, &ha->fw_subminor_version,
3141 &ha->fw_attributes, &ha->fw_memory_size,
3142 ha->mpi_version, &ha->mpi_capabilities,
3143 ha->phy_version);
3144
3145 if (rval != QLA_SUCCESS) 3140 if (rval != QLA_SUCCESS)
3146 return rval; 3141 return rval;
3147 3142
@@ -3150,7 +3145,6 @@ qla82xx_check_md_needed(scsi_qla_host_t *vha)
3150 if (fw_major_version != ha->fw_major_version || 3145 if (fw_major_version != ha->fw_major_version ||
3151 fw_minor_version != ha->fw_minor_version || 3146 fw_minor_version != ha->fw_minor_version ||
3152 fw_subminor_version != ha->fw_subminor_version) { 3147 fw_subminor_version != ha->fw_subminor_version) {
3153
3154 ql_log(ql_log_info, vha, 0xb02d, 3148 ql_log(ql_log_info, vha, 0xb02d,
3155 "Firmware version differs " 3149 "Firmware version differs "
3156 "Previous version: %d:%d:%d - " 3150 "Previous version: %d:%d:%d - "
diff --git a/drivers/scsi/qla2xxx/qla_nx.h b/drivers/scsi/qla2xxx/qla_nx.h
index 57a226be339a..4ac50e274661 100644
--- a/drivers/scsi/qla2xxx/qla_nx.h
+++ b/drivers/scsi/qla2xxx/qla_nx.h
@@ -888,7 +888,8 @@ struct ct6_dsd {
888}; 888};
889 889
890#define MBC_TOGGLE_INTERRUPT 0x10 890#define MBC_TOGGLE_INTERRUPT 0x10
891#define MBC_SET_LED_CONFIG 0x125 891#define MBC_SET_LED_CONFIG 0x125 /* FCoE specific LED control */
892#define MBC_GET_LED_CONFIG 0x126 /* FCoE specific LED control */
892 893
893/* Flash offset */ 894/* Flash offset */
894#define FLT_REG_BOOTLOAD_82XX 0x72 895#define FLT_REG_BOOTLOAD_82XX 0x72
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 036030c95339..79c752eef991 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -1219,7 +1219,7 @@ qla2x00_loop_reset(scsi_qla_host_t *vha)
1219 } 1219 }
1220 } 1220 }
1221 1221
1222 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) { 1222 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1223 ret = qla2x00_full_login_lip(vha); 1223 ret = qla2x00_full_login_lip(vha);
1224 if (ret != QLA_SUCCESS) { 1224 if (ret != QLA_SUCCESS) {
1225 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1225 ql_dbg(ql_dbg_taskm, vha, 0x802d,
@@ -1488,9 +1488,6 @@ qla2x00_iospace_config(struct qla_hw_data *ha)
1488 uint16_t msix; 1488 uint16_t msix;
1489 int cpus; 1489 int cpus;
1490 1490
1491 if (IS_QLA82XX(ha))
1492 return qla82xx_iospace_config(ha);
1493
1494 if (pci_request_selected_regions(ha->pdev, ha->bars, 1491 if (pci_request_selected_regions(ha->pdev, ha->bars,
1495 QLA2XXX_DRIVER_NAME)) { 1492 QLA2XXX_DRIVER_NAME)) {
1496 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1493 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
@@ -1593,6 +1590,96 @@ iospace_error_exit:
1593} 1590}
1594 1591
1595 1592
1593static int
1594qla83xx_iospace_config(struct qla_hw_data *ha)
1595{
1596 uint16_t msix;
1597 int cpus;
1598
1599 if (pci_request_selected_regions(ha->pdev, ha->bars,
1600 QLA2XXX_DRIVER_NAME)) {
1601 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1602 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1603 pci_name(ha->pdev));
1604
1605 goto iospace_error_exit;
1606 }
1607
1608 /* Use MMIO operations for all accesses. */
1609 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1610 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1611 "Invalid pci I/O region size (%s).\n",
1612 pci_name(ha->pdev));
1613 goto iospace_error_exit;
1614 }
1615 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1616 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1617 "Invalid PCI mem region size (%s), aborting\n",
1618 pci_name(ha->pdev));
1619 goto iospace_error_exit;
1620 }
1621
1622 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1623 if (!ha->iobase) {
1624 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1625 "Cannot remap MMIO (%s), aborting.\n",
1626 pci_name(ha->pdev));
1627 goto iospace_error_exit;
1628 }
1629
1630 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1631 /* 83XX 26XX always use MQ type access for queues
1632 * - mbar 2, a.k.a region 4 */
1633 ha->max_req_queues = ha->max_rsp_queues = 1;
1634 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1635 pci_resource_len(ha->pdev, 4));
1636
1637 if (!ha->mqiobase) {
1638 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1639 "BAR2/region4 not enabled\n");
1640 goto mqiobase_exit;
1641 }
1642
1643 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1644 pci_resource_len(ha->pdev, 2));
1645 if (ha->msixbase) {
1646 /* Read MSIX vector size of the board */
1647 pci_read_config_word(ha->pdev,
1648 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1649 ha->msix_count = msix;
1650 /* Max queues are bounded by available msix vectors */
1651 /* queue 0 uses two msix vectors */
1652 if (ql2xmultique_tag) {
1653 cpus = num_online_cpus();
1654 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1655 (cpus + 1) : (ha->msix_count - 1);
1656 ha->max_req_queues = 2;
1657 } else if (ql2xmaxqueues > 1) {
1658 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1659 QLA_MQ_SIZE : ql2xmaxqueues;
1660 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1661 "QoS mode set, max no of request queues:%d.\n",
1662 ha->max_req_queues);
1663 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1664 "QoS mode set, max no of request queues:%d.\n",
1665 ha->max_req_queues);
1666 }
1667 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1668 "MSI-X vector count: %d.\n", msix);
1669 } else
1670 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1671 "BAR 1 not enabled.\n");
1672
1673mqiobase_exit:
1674 ha->msix_count = ha->max_rsp_queues + 1;
1675 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1676 "MSIX Count:%d.\n", ha->msix_count);
1677 return 0;
1678
1679iospace_error_exit:
1680 return -ENOMEM;
1681}
1682
1596static struct isp_operations qla2100_isp_ops = { 1683static struct isp_operations qla2100_isp_ops = {
1597 .pci_config = qla2100_pci_config, 1684 .pci_config = qla2100_pci_config,
1598 .reset_chip = qla2x00_reset_chip, 1685 .reset_chip = qla2x00_reset_chip,
@@ -1769,7 +1856,7 @@ static struct isp_operations qla81xx_isp_ops = {
1769 .fw_dump = qla81xx_fw_dump, 1856 .fw_dump = qla81xx_fw_dump,
1770 .beacon_on = qla24xx_beacon_on, 1857 .beacon_on = qla24xx_beacon_on,
1771 .beacon_off = qla24xx_beacon_off, 1858 .beacon_off = qla24xx_beacon_off,
1772 .beacon_blink = qla24xx_beacon_blink, 1859 .beacon_blink = qla83xx_beacon_blink,
1773 .read_optrom = qla25xx_read_optrom_data, 1860 .read_optrom = qla25xx_read_optrom_data,
1774 .write_optrom = qla24xx_write_optrom_data, 1861 .write_optrom = qla24xx_write_optrom_data,
1775 .get_flash_version = qla24xx_get_flash_version, 1862 .get_flash_version = qla24xx_get_flash_version,
@@ -1815,6 +1902,43 @@ static struct isp_operations qla82xx_isp_ops = {
1815 .iospace_config = qla82xx_iospace_config, 1902 .iospace_config = qla82xx_iospace_config,
1816}; 1903};
1817 1904
1905static struct isp_operations qla83xx_isp_ops = {
1906 .pci_config = qla25xx_pci_config,
1907 .reset_chip = qla24xx_reset_chip,
1908 .chip_diag = qla24xx_chip_diag,
1909 .config_rings = qla24xx_config_rings,
1910 .reset_adapter = qla24xx_reset_adapter,
1911 .nvram_config = qla81xx_nvram_config,
1912 .update_fw_options = qla81xx_update_fw_options,
1913 .load_risc = qla81xx_load_risc,
1914 .pci_info_str = qla24xx_pci_info_str,
1915 .fw_version_str = qla24xx_fw_version_str,
1916 .intr_handler = qla24xx_intr_handler,
1917 .enable_intrs = qla24xx_enable_intrs,
1918 .disable_intrs = qla24xx_disable_intrs,
1919 .abort_command = qla24xx_abort_command,
1920 .target_reset = qla24xx_abort_target,
1921 .lun_reset = qla24xx_lun_reset,
1922 .fabric_login = qla24xx_login_fabric,
1923 .fabric_logout = qla24xx_fabric_logout,
1924 .calc_req_entries = NULL,
1925 .build_iocbs = NULL,
1926 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1927 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1928 .read_nvram = NULL,
1929 .write_nvram = NULL,
1930 .fw_dump = qla83xx_fw_dump,
1931 .beacon_on = qla24xx_beacon_on,
1932 .beacon_off = qla24xx_beacon_off,
1933 .beacon_blink = qla83xx_beacon_blink,
1934 .read_optrom = qla25xx_read_optrom_data,
1935 .write_optrom = qla24xx_write_optrom_data,
1936 .get_flash_version = qla24xx_get_flash_version,
1937 .start_scsi = qla24xx_dif_start_scsi,
1938 .abort_isp = qla2x00_abort_isp,
1939 .iospace_config = qla83xx_iospace_config,
1940};
1941
1818static inline void 1942static inline void
1819qla2x00_set_isp_flags(struct qla_hw_data *ha) 1943qla2x00_set_isp_flags(struct qla_hw_data *ha)
1820{ 1944{
@@ -1909,6 +2033,22 @@ qla2x00_set_isp_flags(struct qla_hw_data *ha)
1909 /* Initialize 82XX ISP flags */ 2033 /* Initialize 82XX ISP flags */
1910 qla82xx_init_flags(ha); 2034 qla82xx_init_flags(ha);
1911 break; 2035 break;
2036 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2037 ha->device_type |= DT_ISP2031;
2038 ha->device_type |= DT_ZIO_SUPPORTED;
2039 ha->device_type |= DT_FWI2;
2040 ha->device_type |= DT_IIDMA;
2041 ha->device_type |= DT_T10_PI;
2042 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2043 break;
2044 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2045 ha->device_type |= DT_ISP8031;
2046 ha->device_type |= DT_ZIO_SUPPORTED;
2047 ha->device_type |= DT_FWI2;
2048 ha->device_type |= DT_IIDMA;
2049 ha->device_type |= DT_T10_PI;
2050 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2051 break;
1912 } 2052 }
1913 2053
1914 if (IS_QLA82XX(ha)) 2054 if (IS_QLA82XX(ha))
@@ -1980,7 +2120,9 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1980 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2120 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
1981 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2121 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
1982 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2122 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
1983 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) { 2123 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2124 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2125 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
1984 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2126 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1985 mem_only = 1; 2127 mem_only = 1;
1986 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2128 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
@@ -2020,9 +2162,8 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2020 qla2x00_set_isp_flags(ha); 2162 qla2x00_set_isp_flags(ha);
2021 2163
2022 /* Set EEH reset type to fundamental if required by hba */ 2164 /* Set EEH reset type to fundamental if required by hba */
2023 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) { 2165 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha))
2024 pdev->needs_freset = 1; 2166 pdev->needs_freset = 1;
2025 }
2026 2167
2027 ha->prev_topology = 0; 2168 ha->prev_topology = 0;
2028 ha->init_cb_size = sizeof(init_cb_t); 2169 ha->init_cb_size = sizeof(init_cb_t);
@@ -2123,7 +2264,22 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2123 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2264 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2124 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2265 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2125 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2266 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2267 } else if (IS_QLA83XX(ha)) {
2268 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2269 req_length = REQUEST_ENTRY_CNT_24XX;
2270 rsp_length = RESPONSE_ENTRY_CNT_2300;
2271 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2272 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2273 ha->gid_list_info_size = 8;
2274 ha->optrom_size = OPTROM_SIZE_83XX;
2275 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2276 ha->isp_ops = &qla83xx_isp_ops;
2277 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2278 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2279 ha->nvram_conf_off = ~0;
2280 ha->nvram_data_off = ~0;
2126 } 2281 }
2282
2127 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2283 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2128 "mbx_count=%d, req_length=%d, " 2284 "mbx_count=%d, req_length=%d, "
2129 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2285 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
@@ -2251,7 +2407,7 @@ que_init:
2251 req->req_q_out = &ha->iobase->isp24.req_q_out; 2407 req->req_q_out = &ha->iobase->isp24.req_q_out;
2252 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2408 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2253 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2409 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2254 if (ha->mqenable) { 2410 if (ha->mqenable || IS_QLA83XX(ha)) {
2255 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2411 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2256 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2412 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2257 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2413 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
@@ -2552,6 +2708,9 @@ qla2x00_remove_one(struct pci_dev *pdev)
2552 2708
2553 if (ha->mqiobase) 2709 if (ha->mqiobase)
2554 iounmap(ha->mqiobase); 2710 iounmap(ha->mqiobase);
2711
2712 if (IS_QLA83XX(ha) && ha->msixbase)
2713 iounmap(ha->msixbase);
2555 } 2714 }
2556 2715
2557 pci_release_selected_regions(ha->pdev, ha->bars); 2716 pci_release_selected_regions(ha->pdev, ha->bars);
@@ -2893,7 +3052,7 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2893 ha->npiv_info = NULL; 3052 ha->npiv_info = NULL;
2894 3053
2895 /* Get consistent memory allocated for EX-INIT-CB. */ 3054 /* Get consistent memory allocated for EX-INIT-CB. */
2896 if (IS_QLA8XXX_TYPE(ha)) { 3055 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
2897 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3056 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2898 &ha->ex_init_cb_dma); 3057 &ha->ex_init_cb_dma);
2899 if (!ha->ex_init_cb) 3058 if (!ha->ex_init_cb)
@@ -3889,7 +4048,7 @@ qla2x00_timer(scsi_qla_host_t *vha)
3889 4048
3890/* Firmware interface routines. */ 4049/* Firmware interface routines. */
3891 4050
3892#define FW_BLOBS 8 4051#define FW_BLOBS 10
3893#define FW_ISP21XX 0 4052#define FW_ISP21XX 0
3894#define FW_ISP22XX 1 4053#define FW_ISP22XX 1
3895#define FW_ISP2300 2 4054#define FW_ISP2300 2
@@ -3898,6 +4057,8 @@ qla2x00_timer(scsi_qla_host_t *vha)
3898#define FW_ISP25XX 5 4057#define FW_ISP25XX 5
3899#define FW_ISP81XX 6 4058#define FW_ISP81XX 6
3900#define FW_ISP82XX 7 4059#define FW_ISP82XX 7
4060#define FW_ISP2031 8
4061#define FW_ISP8031 9
3901 4062
3902#define FW_FILE_ISP21XX "ql2100_fw.bin" 4063#define FW_FILE_ISP21XX "ql2100_fw.bin"
3903#define FW_FILE_ISP22XX "ql2200_fw.bin" 4064#define FW_FILE_ISP22XX "ql2200_fw.bin"
@@ -3907,6 +4068,8 @@ qla2x00_timer(scsi_qla_host_t *vha)
3907#define FW_FILE_ISP25XX "ql2500_fw.bin" 4068#define FW_FILE_ISP25XX "ql2500_fw.bin"
3908#define FW_FILE_ISP81XX "ql8100_fw.bin" 4069#define FW_FILE_ISP81XX "ql8100_fw.bin"
3909#define FW_FILE_ISP82XX "ql8200_fw.bin" 4070#define FW_FILE_ISP82XX "ql8200_fw.bin"
4071#define FW_FILE_ISP2031 "ql2600_fw.bin"
4072#define FW_FILE_ISP8031 "ql8300_fw.bin"
3910 4073
3911static DEFINE_MUTEX(qla_fw_lock); 4074static DEFINE_MUTEX(qla_fw_lock);
3912 4075
@@ -3919,6 +4082,8 @@ static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
3919 { .name = FW_FILE_ISP25XX, }, 4082 { .name = FW_FILE_ISP25XX, },
3920 { .name = FW_FILE_ISP81XX, }, 4083 { .name = FW_FILE_ISP81XX, },
3921 { .name = FW_FILE_ISP82XX, }, 4084 { .name = FW_FILE_ISP82XX, },
4085 { .name = FW_FILE_ISP2031, },
4086 { .name = FW_FILE_ISP8031, },
3922}; 4087};
3923 4088
3924struct fw_blob * 4089struct fw_blob *
@@ -3944,6 +4109,10 @@ qla2x00_request_firmware(scsi_qla_host_t *vha)
3944 blob = &qla_fw_blobs[FW_ISP81XX]; 4109 blob = &qla_fw_blobs[FW_ISP81XX];
3945 } else if (IS_QLA82XX(ha)) { 4110 } else if (IS_QLA82XX(ha)) {
3946 blob = &qla_fw_blobs[FW_ISP82XX]; 4111 blob = &qla_fw_blobs[FW_ISP82XX];
4112 } else if (IS_QLA2031(ha)) {
4113 blob = &qla_fw_blobs[FW_ISP2031];
4114 } else if (IS_QLA8031(ha)) {
4115 blob = &qla_fw_blobs[FW_ISP8031];
3947 } 4116 }
3948 4117
3949 mutex_lock(&qla_fw_lock); 4118 mutex_lock(&qla_fw_lock);
@@ -4265,6 +4434,7 @@ static struct pci_device_id qla2xxx_pci_tbl[] = {
4265 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 4434 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4266 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 4435 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
4267 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 4436 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
4437 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
4268 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 4438 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
4269 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 4439 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
4270 { 0 }, 4440 { 0 },
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index 16bc72844a97..3c13c0a6be63 100644
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -568,6 +568,9 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
568 else if (IS_QLA82XX(ha)) { 568 else if (IS_QLA82XX(ha)) {
569 *start = FA_FLASH_LAYOUT_ADDR_82; 569 *start = FA_FLASH_LAYOUT_ADDR_82;
570 goto end; 570 goto end;
571 } else if (IS_QLA83XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
573 goto end;
571 } 574 }
572 /* Begin with first PCI expansion ROM header. */ 575 /* Begin with first PCI expansion ROM header. */
573 buf = (uint8_t *)req->ring; 576 buf = (uint8_t *)req->ring;
@@ -721,13 +724,22 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
721 le32_to_cpu(region->size)); 724 le32_to_cpu(region->size));
722 725
723 switch (le32_to_cpu(region->code) & 0xff) { 726 switch (le32_to_cpu(region->code) & 0xff) {
727 case FLT_REG_FCOE_FW:
728 if (!IS_QLA8031(ha))
729 break;
730 ha->flt_region_fw = start;
731 break;
724 case FLT_REG_FW: 732 case FLT_REG_FW:
733 if (IS_QLA8031(ha))
734 break;
725 ha->flt_region_fw = start; 735 ha->flt_region_fw = start;
726 break; 736 break;
727 case FLT_REG_BOOT_CODE: 737 case FLT_REG_BOOT_CODE:
728 ha->flt_region_boot = start; 738 ha->flt_region_boot = start;
729 break; 739 break;
730 case FLT_REG_VPD_0: 740 case FLT_REG_VPD_0:
741 if (IS_QLA8031(ha))
742 break;
731 ha->flt_region_vpd_nvram = start; 743 ha->flt_region_vpd_nvram = start;
732 if (IS_QLA82XX(ha)) 744 if (IS_QLA82XX(ha))
733 break; 745 break;
@@ -735,16 +747,20 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
735 ha->flt_region_vpd = start; 747 ha->flt_region_vpd = start;
736 break; 748 break;
737 case FLT_REG_VPD_1: 749 case FLT_REG_VPD_1:
738 if (IS_QLA82XX(ha)) 750 if (IS_QLA82XX(ha) || IS_QLA8031(ha))
739 break; 751 break;
740 if (!ha->flags.port0) 752 if (!ha->flags.port0)
741 ha->flt_region_vpd = start; 753 ha->flt_region_vpd = start;
742 break; 754 break;
743 case FLT_REG_NVRAM_0: 755 case FLT_REG_NVRAM_0:
756 if (IS_QLA8031(ha))
757 break;
744 if (ha->flags.port0) 758 if (ha->flags.port0)
745 ha->flt_region_nvram = start; 759 ha->flt_region_nvram = start;
746 break; 760 break;
747 case FLT_REG_NVRAM_1: 761 case FLT_REG_NVRAM_1:
762 if (IS_QLA8031(ha))
763 break;
748 if (!ha->flags.port0) 764 if (!ha->flags.port0)
749 ha->flt_region_nvram = start; 765 ha->flt_region_nvram = start;
750 break; 766 break;
@@ -785,6 +801,31 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
785 case FLT_REG_VPD_82XX: 801 case FLT_REG_VPD_82XX:
786 ha->flt_region_vpd = start; 802 ha->flt_region_vpd = start;
787 break; 803 break;
804 case FLT_REG_FCOE_VPD_0:
805 if (!IS_QLA8031(ha))
806 break;
807 ha->flt_region_vpd_nvram = start;
808 if (ha->flags.port0)
809 ha->flt_region_vpd = start;
810 break;
811 case FLT_REG_FCOE_VPD_1:
812 if (!IS_QLA8031(ha))
813 break;
814 if (!ha->flags.port0)
815 ha->flt_region_vpd = start;
816 break;
817 case FLT_REG_FCOE_NVRAM_0:
818 if (!IS_QLA8031(ha))
819 break;
820 if (ha->flags.port0)
821 ha->flt_region_nvram = start;
822 break;
823 case FLT_REG_FCOE_NVRAM_1:
824 if (!IS_QLA8031(ha))
825 break;
826 if (!ha->flags.port0)
827 ha->flt_region_nvram = start;
828 break;
788 } 829 }
789 } 830 }
790 goto done; 831 goto done;
@@ -804,15 +845,12 @@ no_flash_data:
804 def_npiv_conf0[def] : def_npiv_conf1[def]; 845 def_npiv_conf0[def] : def_npiv_conf1[def];
805done: 846done:
806 ql_dbg(ql_dbg_init, vha, 0x004a, 847 ql_dbg(ql_dbg_init, vha, 0x004a,
807 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x.\n", 848 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
808 loc, ha->flt_region_boot, 849 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
809 ha->flt_region_fw, ha->flt_region_vpd_nvram, 850 loc, ha->flt_region_boot, ha->flt_region_fw,
810 ha->flt_region_vpd); 851 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
811 ql_dbg(ql_dbg_init, vha, 0x004b, 852 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
812 "nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 853 ha->flt_region_fcp_prio);
813 ha->flt_region_nvram,
814 ha->flt_region_fdt, ha->flt_region_flt,
815 ha->flt_region_npiv_conf, ha->flt_region_fcp_prio);
816} 854}
817 855
818static void 856static void
@@ -948,7 +986,8 @@ qla2xxx_get_flash_info(scsi_qla_host_t *vha)
948 uint32_t flt_addr; 986 uint32_t flt_addr;
949 struct qla_hw_data *ha = vha->hw; 987 struct qla_hw_data *ha = vha->hw;
950 988
951 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) 989 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
990 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
952 return QLA_SUCCESS; 991 return QLA_SUCCESS;
953 992
954 ret = qla2xxx_find_flt_start(vha, &flt_addr); 993 ret = qla2xxx_find_flt_start(vha, &flt_addr);
@@ -974,7 +1013,8 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
974 struct qla_npiv_entry *entry; 1013 struct qla_npiv_entry *entry;
975 struct qla_hw_data *ha = vha->hw; 1014 struct qla_hw_data *ha = vha->hw;
976 1015
977 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) 1016 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1017 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
978 return; 1018 return;
979 1019
980 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, 1020 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
@@ -1144,8 +1184,8 @@ qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1144 struct qla_hw_data *ha = vha->hw; 1184 struct qla_hw_data *ha = vha->hw;
1145 1185
1146 /* Prepare burst-capable write on supported ISPs. */ 1186 /* Prepare burst-capable write on supported ISPs. */
1147 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) && 1187 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
1148 dwords > OPTROM_BURST_DWORDS) { 1188 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1149 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1189 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1150 &optrom_dma, GFP_KERNEL); 1190 &optrom_dma, GFP_KERNEL);
1151 if (!optrom) { 1191 if (!optrom) {
@@ -1619,6 +1659,71 @@ qla24xx_beacon_blink(struct scsi_qla_host *vha)
1619 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1659 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1620} 1660}
1621 1661
1662void
1663qla83xx_beacon_blink(struct scsi_qla_host *vha)
1664{
1665 uint32_t led_select_value;
1666 struct qla_hw_data *ha = vha->hw;
1667 uint16_t led_cfg[6];
1668 uint16_t orig_led_cfg[6];
1669
1670 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha))
1671 return;
1672
1673 if (IS_QLA2031(ha) && ha->beacon_blink_led) {
1674 if (ha->flags.port0)
1675 led_select_value = 0x00201320;
1676 else
1677 led_select_value = 0x00201328;
1678
1679 qla83xx_write_remote_reg(vha, led_select_value, 0x40002000);
1680 qla83xx_write_remote_reg(vha, led_select_value + 4, 0x40002000);
1681 msleep(1000);
1682 qla83xx_write_remote_reg(vha, led_select_value, 0x40004000);
1683 qla83xx_write_remote_reg(vha, led_select_value + 4, 0x40004000);
1684 } else if ((IS_QLA8031(ha) || IS_QLA81XX(ha)) && ha->beacon_blink_led) {
1685 int rval;
1686
1687 /* Save Current */
1688 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1689 /* Do the blink */
1690 if (rval == QLA_SUCCESS) {
1691 if (IS_QLA81XX(ha)) {
1692 led_cfg[0] = 0x4000;
1693 led_cfg[1] = 0x2000;
1694 led_cfg[2] = 0;
1695 led_cfg[3] = 0;
1696 led_cfg[4] = 0;
1697 led_cfg[5] = 0;
1698 } else {
1699 led_cfg[0] = 0x4000;
1700 led_cfg[1] = 0x4000;
1701 led_cfg[2] = 0x4000;
1702 led_cfg[3] = 0x2000;
1703 led_cfg[4] = 0;
1704 led_cfg[5] = 0x2000;
1705 }
1706 rval = qla81xx_set_led_config(vha, led_cfg);
1707 msleep(1000);
1708 if (IS_QLA81XX(ha)) {
1709 led_cfg[0] = 0x4000;
1710 led_cfg[1] = 0x2000;
1711 led_cfg[2] = 0;
1712 } else {
1713 led_cfg[0] = 0x4000;
1714 led_cfg[1] = 0x2000;
1715 led_cfg[2] = 0x4000;
1716 led_cfg[3] = 0x4000;
1717 led_cfg[4] = 0;
1718 led_cfg[5] = 0x2000;
1719 }
1720 rval = qla81xx_set_led_config(vha, led_cfg);
1721 }
1722 /* On exit, restore original (presumes no status change) */
1723 qla81xx_set_led_config(vha, orig_led_cfg);
1724 }
1725}
1726
1622int 1727int
1623qla24xx_beacon_on(struct scsi_qla_host *vha) 1728qla24xx_beacon_on(struct scsi_qla_host *vha)
1624{ 1729{
@@ -1630,6 +1735,9 @@ qla24xx_beacon_on(struct scsi_qla_host *vha)
1630 if (IS_QLA82XX(ha)) 1735 if (IS_QLA82XX(ha))
1631 return QLA_SUCCESS; 1736 return QLA_SUCCESS;
1632 1737
1738 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1739 goto skip_gpio; /* let blink handle it */
1740
1633 if (ha->beacon_blink_led == 0) { 1741 if (ha->beacon_blink_led == 0) {
1634 /* Enable firmware for update */ 1742 /* Enable firmware for update */
1635 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1743 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
@@ -1644,6 +1752,9 @@ qla24xx_beacon_on(struct scsi_qla_host *vha)
1644 return QLA_FUNCTION_FAILED; 1752 return QLA_FUNCTION_FAILED;
1645 } 1753 }
1646 1754
1755 if (IS_QLA2031(ha))
1756 goto skip_gpio;
1757
1647 spin_lock_irqsave(&ha->hardware_lock, flags); 1758 spin_lock_irqsave(&ha->hardware_lock, flags);
1648 gpio_data = RD_REG_DWORD(&reg->gpiod); 1759 gpio_data = RD_REG_DWORD(&reg->gpiod);
1649 1760
@@ -1658,6 +1769,7 @@ qla24xx_beacon_on(struct scsi_qla_host *vha)
1658 /* So all colors blink together. */ 1769 /* So all colors blink together. */
1659 ha->beacon_color_state = 0; 1770 ha->beacon_color_state = 0;
1660 1771
1772skip_gpio:
1661 /* Let the per HBA timer kick off the blinking process. */ 1773 /* Let the per HBA timer kick off the blinking process. */
1662 ha->beacon_blink_led = 1; 1774 ha->beacon_blink_led = 1;
1663 1775
@@ -1676,6 +1788,13 @@ qla24xx_beacon_off(struct scsi_qla_host *vha)
1676 return QLA_SUCCESS; 1788 return QLA_SUCCESS;
1677 1789
1678 ha->beacon_blink_led = 0; 1790 ha->beacon_blink_led = 0;
1791
1792 if (IS_QLA2031(ha))
1793 goto set_fw_options;
1794
1795 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1796 return QLA_SUCCESS;
1797
1679 ha->beacon_color_state = QLA_LED_ALL_ON; 1798 ha->beacon_color_state = QLA_LED_ALL_ON;
1680 1799
1681 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1800 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
@@ -1690,6 +1809,7 @@ qla24xx_beacon_off(struct scsi_qla_host *vha)
1690 RD_REG_DWORD(&reg->gpiod); 1809 RD_REG_DWORD(&reg->gpiod);
1691 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1810 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1692 1811
1812set_fw_options:
1693 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1813 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1694 1814
1695 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1815 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 00:30:20 -0400