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path: root/drivers/scsi/sata_sil.c
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Diffstat (limited to 'drivers/scsi/sata_sil.c')
-rw-r--r--drivers/scsi/sata_sil.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/scsi/sata_sil.c b/drivers/scsi/sata_sil.c
index 2b2ff48be396..49ed557a4b66 100644
--- a/drivers/scsi/sata_sil.c
+++ b/drivers/scsi/sata_sil.c
@@ -161,6 +161,7 @@ static struct ata_port_operations sil_ops = {
161 .scr_write = sil_scr_write, 161 .scr_write = sil_scr_write,
162 .port_start = ata_port_start, 162 .port_start = ata_port_start,
163 .port_stop = ata_port_stop, 163 .port_stop = ata_port_stop,
164 .host_stop = ata_host_stop,
164}; 165};
165 166
166static struct ata_port_info sil_port_info[] = { 167static struct ata_port_info sil_port_info[] = {
@@ -431,7 +432,13 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
431 writeb(cls, mmio_base + SIL_FIFO_R0); 432 writeb(cls, mmio_base + SIL_FIFO_R0);
432 writeb(cls, mmio_base + SIL_FIFO_W0); 433 writeb(cls, mmio_base + SIL_FIFO_W0);
433 writeb(cls, mmio_base + SIL_FIFO_R1); 434 writeb(cls, mmio_base + SIL_FIFO_R1);
434 writeb(cls, mmio_base + SIL_FIFO_W2); 435 writeb(cls, mmio_base + SIL_FIFO_W1);
436 if (ent->driver_data == sil_3114) {
437 writeb(cls, mmio_base + SIL_FIFO_R2);
438 writeb(cls, mmio_base + SIL_FIFO_W2);
439 writeb(cls, mmio_base + SIL_FIFO_R3);
440 writeb(cls, mmio_base + SIL_FIFO_W3);
441 }
435 } else 442 } else
436 printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n", 443 printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
437 pci_name(pdev)); 444 pci_name(pdev));