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-rw-r--r--drivers/scsi/qla2xxx/qla_fw.h1073
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diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
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--- /dev/null
+++ b/drivers/scsi/qla2xxx/qla_fw.h
@@ -0,0 +1,1073 @@
1
2/********************************************************************************
3* QLOGIC LINUX SOFTWARE
4*
5* QLogic ISP2x00 device driver for Linux 2.6.x
6* Copyright (C) 2003-2005 QLogic Corporation
7* (www.qlogic.com)
8*
9* This program is free software; you can redistribute it and/or modify it
10* under the terms of the GNU General Public License as published by the
11* Free Software Foundation; either version 2, or (at your option) any
12* later version.
13*
14* This program is distributed in the hope that it will be useful, but
15* WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17* General Public License for more details.
18**
19******************************************************************************/
20
21#ifndef __QLA_FW_H
22#define __QLA_FW_H
23
24#define RISC_SADDRESS 0x100000
25#define MBS_CHECKSUM_ERROR 0x4010
26
27/*
28 * Firmware Options.
29 */
30#define FO1_ENABLE_PUREX BIT_10
31#define FO1_DISABLE_LED_CTRL BIT_6
32#define FO2_ENABLE_SEL_CLASS2 BIT_5
33#define FO3_NO_ABTS_ON_LINKDOWN BIT_14
34
35/*
36 * Port Database structure definition for ISP 24xx.
37 */
38#define PDO_FORCE_ADISC BIT_1
39#define PDO_FORCE_PLOGI BIT_0
40
41
42#define PORT_DATABASE_24XX_SIZE 64
43struct port_database_24xx {
44 uint16_t flags;
45#define PDF_TASK_RETRY_ID BIT_14
46#define PDF_FC_TAPE BIT_7
47#define PDF_ACK0_CAPABLE BIT_6
48#define PDF_FCP2_CONF BIT_5
49#define PDF_CLASS_2 BIT_4
50#define PDF_HARD_ADDR BIT_1
51
52 uint8_t current_login_state;
53 uint8_t last_login_state;
54#define PDS_PLOGI_PENDING 0x03
55#define PDS_PLOGI_COMPLETE 0x04
56#define PDS_PRLI_PENDING 0x05
57#define PDS_PRLI_COMPLETE 0x06
58#define PDS_PORT_UNAVAILABLE 0x07
59#define PDS_PRLO_PENDING 0x09
60#define PDS_LOGO_PENDING 0x11
61#define PDS_PRLI2_PENDING 0x12
62
63 uint8_t hard_address[3];
64 uint8_t reserved_1;
65
66 uint8_t port_id[3];
67 uint8_t sequence_id;
68
69 uint16_t port_timer;
70
71 uint16_t nport_handle; /* N_PORT handle. */
72
73 uint16_t receive_data_size;
74 uint16_t reserved_2;
75
76 uint8_t prli_svc_param_word_0[2]; /* Big endian */
77 /* Bits 15-0 of word 0 */
78 uint8_t prli_svc_param_word_3[2]; /* Big endian */
79 /* Bits 15-0 of word 3 */
80
81 uint8_t port_name[WWN_SIZE];
82 uint8_t node_name[WWN_SIZE];
83
84 uint8_t reserved_3[24];
85};
86
87struct nvram_24xx {
88 /* NVRAM header. */
89 uint8_t id[4];
90 uint16_t nvram_version;
91 uint16_t reserved_0;
92
93 /* Firmware Initialization Control Block. */
94 uint16_t version;
95 uint16_t reserved_1;
96 uint16_t frame_payload_size;
97 uint16_t execution_throttle;
98 uint16_t exchange_count;
99 uint16_t hard_address;
100
101 uint8_t port_name[WWN_SIZE];
102 uint8_t node_name[WWN_SIZE];
103
104 uint16_t login_retry_count;
105 uint16_t link_down_on_nos;
106 uint16_t interrupt_delay_timer;
107 uint16_t login_timeout;
108
109 uint32_t firmware_options_1;
110 uint32_t firmware_options_2;
111 uint32_t firmware_options_3;
112
113 /* Offset 56. */
114
115 /*
116 * BIT 0 = Control Enable
117 * BIT 1-15 =
118 *
119 * BIT 0-7 = Reserved
120 * BIT 8-10 = Output Swing 1G
121 * BIT 11-13 = Output Emphasis 1G
122 * BIT 14-15 = Reserved
123 *
124 * BIT 0-7 = Reserved
125 * BIT 8-10 = Output Swing 2G
126 * BIT 11-13 = Output Emphasis 2G
127 * BIT 14-15 = Reserved
128 *
129 * BIT 0-7 = Reserved
130 * BIT 8-10 = Output Swing 4G
131 * BIT 11-13 = Output Emphasis 4G
132 * BIT 14-15 = Reserved
133 */
134 uint16_t seriallink_options[4];
135
136 uint16_t reserved_2[16];
137
138 /* Offset 96. */
139 uint16_t reserved_3[16];
140
141 /* PCIe table entries. */
142 uint16_t reserved_4[16];
143
144 /* Offset 160. */
145 uint16_t reserved_5[16];
146
147 /* Offset 192. */
148 uint16_t reserved_6[16];
149
150 /* Offset 224. */
151 uint16_t reserved_7[16];
152
153 /*
154 * BIT 0 = Enable spinup delay
155 * BIT 1 = Disable BIOS
156 * BIT 2 = Enable Memory Map BIOS
157 * BIT 3 = Enable Selectable Boot
158 * BIT 4 = Disable RISC code load
159 * BIT 5 =
160 * BIT 6 =
161 * BIT 7 =
162 *
163 * BIT 8 =
164 * BIT 9 =
165 * BIT 10 = Enable lip full login
166 * BIT 11 = Enable target reset
167 * BIT 12 =
168 * BIT 13 =
169 * BIT 14 =
170 * BIT 15 = Enable alternate WWN
171 *
172 * BIT 16-31 =
173 */
174 uint32_t host_p;
175
176 uint8_t alternate_port_name[WWN_SIZE];
177 uint8_t alternate_node_name[WWN_SIZE];
178
179 uint8_t boot_port_name[WWN_SIZE];
180 uint16_t boot_lun_number;
181 uint16_t reserved_8;
182
183 uint8_t alt1_boot_port_name[WWN_SIZE];
184 uint16_t alt1_boot_lun_number;
185 uint16_t reserved_9;
186
187 uint8_t alt2_boot_port_name[WWN_SIZE];
188 uint16_t alt2_boot_lun_number;
189 uint16_t reserved_10;
190
191 uint8_t alt3_boot_port_name[WWN_SIZE];
192 uint16_t alt3_boot_lun_number;
193 uint16_t reserved_11;
194
195 /*
196 * BIT 0 = Selective Login
197 * BIT 1 = Alt-Boot Enable
198 * BIT 2 = Reserved
199 * BIT 3 = Boot Order List
200 * BIT 4 = Reserved
201 * BIT 5 = Selective LUN
202 * BIT 6 = Reserved
203 * BIT 7-31 =
204 */
205 uint32_t efi_parameters;
206
207 uint8_t reset_delay;
208 uint8_t reserved_12;
209 uint16_t reserved_13;
210
211 uint16_t boot_id_number;
212 uint16_t reserved_14;
213
214 uint16_t max_luns_per_target;
215 uint16_t reserved_15;
216
217 uint16_t port_down_retry_count;
218 uint16_t link_down_timeout;
219
220 /* FCode parameters. */
221 uint16_t fcode_parameter;
222
223 uint16_t reserved_16[3];
224
225 /* Offset 352. */
226 uint8_t prev_drv_ver_major;
227 uint8_t prev_drv_ver_submajob;
228 uint8_t prev_drv_ver_minor;
229 uint8_t prev_drv_ver_subminor;
230
231 uint16_t prev_bios_ver_major;
232 uint16_t prev_bios_ver_minor;
233
234 uint16_t prev_efi_ver_major;
235 uint16_t prev_efi_ver_minor;
236
237 uint16_t prev_fw_ver_major;
238 uint8_t prev_fw_ver_minor;
239 uint8_t prev_fw_ver_subminor;
240
241 uint16_t reserved_17[8];
242
243 /* Offset 384. */
244 uint16_t reserved_18[16];
245
246 /* Offset 416. */
247 uint16_t reserved_19[16];
248
249 /* Offset 448. */
250 uint16_t reserved_20[16];
251
252 /* Offset 480. */
253 uint8_t model_name[16];
254
255 uint16_t reserved_21[2];
256
257 /* Offset 500. */
258 /* HW Parameter Block. */
259 uint16_t pcie_table_sig;
260 uint16_t pcie_table_offset;
261
262 uint16_t subsystem_vendor_id;
263 uint16_t subsystem_device_id;
264
265 uint32_t checksum;
266};
267
268/*
269 * ISP Initialization Control Block.
270 * Little endian except where noted.
271 */
272#define ICB_VERSION 1
273struct init_cb_24xx {
274 uint16_t version;
275 uint16_t reserved_1;
276
277 uint16_t frame_payload_size;
278 uint16_t execution_throttle;
279 uint16_t exchange_count;
280
281 uint16_t hard_address;
282
283 uint8_t port_name[WWN_SIZE]; /* Big endian. */
284 uint8_t node_name[WWN_SIZE]; /* Big endian. */
285
286 uint16_t response_q_inpointer;
287 uint16_t request_q_outpointer;
288
289 uint16_t login_retry_count;
290
291 uint16_t prio_request_q_outpointer;
292
293 uint16_t response_q_length;
294 uint16_t request_q_length;
295
296 uint16_t link_down_timeout; /* Milliseconds. */
297
298 uint16_t prio_request_q_length;
299
300 uint32_t request_q_address[2];
301 uint32_t response_q_address[2];
302 uint32_t prio_request_q_address[2];
303
304 uint8_t reserved_2[8];
305
306 uint16_t atio_q_inpointer;
307 uint16_t atio_q_length;
308 uint32_t atio_q_address[2];
309
310 uint16_t interrupt_delay_timer; /* 100us increments. */
311 uint16_t login_timeout;
312
313 /*
314 * BIT 0 = Enable Hard Loop Id
315 * BIT 1 = Enable Fairness
316 * BIT 2 = Enable Full-Duplex
317 * BIT 3 = Reserved
318 * BIT 4 = Enable Target Mode
319 * BIT 5 = Disable Initiator Mode
320 * BIT 6 = Reserved
321 * BIT 7 = Reserved
322 *
323 * BIT 8 = Reserved
324 * BIT 9 = Non Participating LIP
325 * BIT 10 = Descending Loop ID Search
326 * BIT 11 = Acquire Loop ID in LIPA
327 * BIT 12 = Reserved
328 * BIT 13 = Full Login after LIP
329 * BIT 14 = Node Name Option
330 * BIT 15-31 = Reserved
331 */
332 uint32_t firmware_options_1;
333
334 /*
335 * BIT 0 = Operation Mode bit 0
336 * BIT 1 = Operation Mode bit 1
337 * BIT 2 = Operation Mode bit 2
338 * BIT 3 = Operation Mode bit 3
339 * BIT 4 = Connection Options bit 0
340 * BIT 5 = Connection Options bit 1
341 * BIT 6 = Connection Options bit 2
342 * BIT 7 = Enable Non part on LIHA failure
343 *
344 * BIT 8 = Enable Class 2
345 * BIT 9 = Enable ACK0
346 * BIT 10 = Reserved
347 * BIT 11 = Enable FC-SP Security
348 * BIT 12 = FC Tape Enable
349 * BIT 13-31 = Reserved
350 */
351 uint32_t firmware_options_2;
352
353 /*
354 * BIT 0 = Reserved
355 * BIT 1 = Soft ID only
356 * BIT 2 = Reserved
357 * BIT 3 = Reserved
358 * BIT 4 = FCP RSP Payload bit 0
359 * BIT 5 = FCP RSP Payload bit 1
360 * BIT 6 = Enable Receive Out-of-Order data frame handling
361 * BIT 7 = Disable Automatic PLOGI on Local Loop
362 *
363 * BIT 8 = Reserved
364 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
365 * BIT 10 = Reserved
366 * BIT 11 = Reserved
367 * BIT 12 = Reserved
368 * BIT 13 = Data Rate bit 0
369 * BIT 14 = Data Rate bit 1
370 * BIT 15 = Data Rate bit 2
371 * BIT 16-31 = Reserved
372 */
373 uint32_t firmware_options_3;
374
375 uint8_t reserved_3[24];
376};
377
378/*
379 * ISP queue - command entry structure definition.
380 */
381#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
382struct cmd_type_6 {
383 uint8_t entry_type; /* Entry type. */
384 uint8_t entry_count; /* Entry count. */
385 uint8_t sys_define; /* System defined. */
386 uint8_t entry_status; /* Entry Status. */
387
388 uint32_t handle; /* System handle. */
389
390 uint16_t nport_handle; /* N_PORT handle. */
391 uint16_t timeout; /* Command timeout. */
392
393 uint16_t dseg_count; /* Data segment count. */
394
395 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
396
397 uint8_t lun[8]; /* FCP LUN (BE). */
398
399 uint16_t control_flags; /* Control flags. */
400#define CF_DATA_SEG_DESCR_ENABLE BIT_2
401#define CF_READ_DATA BIT_1
402#define CF_WRITE_DATA BIT_0
403
404 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
405 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
406
407 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
408
409 uint32_t byte_count; /* Total byte count. */
410
411 uint8_t port_id[3]; /* PortID of destination port. */
412 uint8_t vp_index;
413
414 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
415 uint16_t fcp_data_dseg_len; /* Data segment length. */
416 uint16_t reserved_1; /* MUST be set to 0. */
417};
418
419#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
420struct cmd_type_7 {
421 uint8_t entry_type; /* Entry type. */
422 uint8_t entry_count; /* Entry count. */
423 uint8_t sys_define; /* System defined. */
424 uint8_t entry_status; /* Entry Status. */
425
426 uint32_t handle; /* System handle. */
427
428 uint16_t nport_handle; /* N_PORT handle. */
429 uint16_t timeout; /* Command timeout. */
430#define FW_MAX_TIMEOUT 0x1999
431
432 uint16_t dseg_count; /* Data segment count. */
433 uint16_t reserved_1;
434
435 uint8_t lun[8]; /* FCP LUN (BE). */
436
437 uint16_t task_mgmt_flags; /* Task management flags. */
438#define TMF_CLEAR_ACA BIT_14
439#define TMF_TARGET_RESET BIT_13
440#define TMF_LUN_RESET BIT_12
441#define TMF_CLEAR_TASK_SET BIT_10
442#define TMF_ABORT_TASK_SET BIT_9
443#define TMF_READ_DATA BIT_1
444#define TMF_WRITE_DATA BIT_0
445
446 uint8_t task;
447#define TSK_SIMPLE 0
448#define TSK_HEAD_OF_QUEUE 1
449#define TSK_ORDERED 2
450#define TSK_ACA 4
451#define TSK_UNTAGGED 5
452
453 uint8_t crn;
454
455 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
456 uint32_t byte_count; /* Total byte count. */
457
458 uint8_t port_id[3]; /* PortID of destination port. */
459 uint8_t vp_index;
460
461 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
462 uint32_t dseg_0_len; /* Data segment 0 length. */
463};
464
465/*
466 * ISP queue - status entry structure definition.
467 */
468#define STATUS_TYPE 0x03 /* Status entry. */
469struct sts_entry_24xx {
470 uint8_t entry_type; /* Entry type. */
471 uint8_t entry_count; /* Entry count. */
472 uint8_t sys_define; /* System defined. */
473 uint8_t entry_status; /* Entry Status. */
474
475 uint32_t handle; /* System handle. */
476
477 uint16_t comp_status; /* Completion status. */
478 uint16_t ox_id; /* OX_ID used by the firmware. */
479
480 uint32_t residual_len; /* Residual transfer length. */
481
482 uint16_t reserved_1;
483 uint16_t state_flags; /* State flags. */
484#define SF_TRANSFERRED_DATA BIT_11
485#define SF_FCP_RSP_DMA BIT_0
486
487 uint16_t reserved_2;
488 uint16_t scsi_status; /* SCSI status. */
489#define SS_CONFIRMATION_REQ BIT_12
490
491 uint32_t rsp_residual_count; /* FCP RSP residual count. */
492
493 uint32_t sense_len; /* FCP SENSE length. */
494 uint32_t rsp_data_len; /* FCP response data length. */
495
496 uint8_t data[28]; /* FCP response/sense information. */
497};
498
499/*
500 * Status entry completion status
501 */
502#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
503#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
504#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
505#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
506#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
507
508/*
509 * ISP queue - marker entry structure definition.
510 */
511#define MARKER_TYPE 0x04 /* Marker entry. */
512struct mrk_entry_24xx {
513 uint8_t entry_type; /* Entry type. */
514 uint8_t entry_count; /* Entry count. */
515 uint8_t handle_count; /* Handle count. */
516 uint8_t entry_status; /* Entry Status. */
517
518 uint32_t handle; /* System handle. */
519
520 uint16_t nport_handle; /* N_PORT handle. */
521
522 uint8_t modifier; /* Modifier (7-0). */
523#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
524#define MK_SYNC_ID 1 /* Synchronize ID */
525#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
526 uint8_t reserved_1;
527
528 uint8_t reserved_2;
529 uint8_t vp_index;
530
531 uint16_t reserved_3;
532
533 uint8_t lun[8]; /* FCP LUN (BE). */
534 uint8_t reserved_4[40];
535};
536
537/*
538 * ISP queue - CT Pass-Through entry structure definition.
539 */
540#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
541struct ct_entry_24xx {
542 uint8_t entry_type; /* Entry type. */
543 uint8_t entry_count; /* Entry count. */
544 uint8_t sys_define; /* System Defined. */
545 uint8_t entry_status; /* Entry Status. */
546
547 uint32_t handle; /* System handle. */
548
549 uint16_t comp_status; /* Completion status. */
550
551 uint16_t nport_handle; /* N_PORT handle. */
552
553 uint16_t cmd_dsd_count;
554
555 uint8_t vp_index;
556 uint8_t reserved_1;
557
558 uint16_t timeout; /* Command timeout. */
559 uint16_t reserved_2;
560
561 uint16_t rsp_dsd_count;
562
563 uint8_t reserved_3[10];
564
565 uint32_t rsp_byte_count;
566 uint32_t cmd_byte_count;
567
568 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
569 uint32_t dseg_0_len; /* Data segment 0 length. */
570 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
571 uint32_t dseg_1_len; /* Data segment 1 length. */
572};
573
574/*
575 * ISP queue - ELS Pass-Through entry structure definition.
576 */
577#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
578struct els_entry_24xx {
579 uint8_t entry_type; /* Entry type. */
580 uint8_t entry_count; /* Entry count. */
581 uint8_t sys_define; /* System Defined. */
582 uint8_t entry_status; /* Entry Status. */
583
584 uint32_t handle; /* System handle. */
585
586 uint16_t reserved_1;
587
588 uint16_t nport_handle; /* N_PORT handle. */
589
590 uint16_t tx_dsd_count;
591
592 uint8_t vp_index;
593 uint8_t sof_type;
594#define EST_SOFI3 (1 << 4)
595#define EST_SOFI2 (3 << 4)
596
597 uint32_t rx_xchg_address[2]; /* Receive exchange address. */
598 uint16_t rx_dsd_count;
599
600 uint8_t opcode;
601 uint8_t reserved_2;
602
603 uint8_t port_id[3];
604 uint8_t reserved_3;
605
606 uint16_t reserved_4;
607
608 uint16_t control_flags; /* Control flags. */
609#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
610#define EPD_ELS_COMMAND (0 << 13)
611#define EPD_ELS_ACC (1 << 13)
612#define EPD_ELS_RJT (2 << 13)
613#define EPD_RX_XCHG (3 << 13)
614#define ECF_CLR_PASSTHRU_PEND BIT_12
615#define ECF_INCL_FRAME_HDR BIT_11
616
617 uint32_t rx_byte_count;
618 uint32_t tx_byte_count;
619
620 uint32_t tx_address[2]; /* Data segment 0 address. */
621 uint32_t tx_len; /* Data segment 0 length. */
622 uint32_t rx_address[2]; /* Data segment 1 address. */
623 uint32_t rx_len; /* Data segment 1 length. */
624};
625
626/*
627 * ISP queue - Mailbox Command entry structure definition.
628 */
629#define MBX_IOCB_TYPE 0x39
630struct mbx_entry_24xx {
631 uint8_t entry_type; /* Entry type. */
632 uint8_t entry_count; /* Entry count. */
633 uint8_t handle_count; /* Handle count. */
634 uint8_t entry_status; /* Entry Status. */
635
636 uint32_t handle; /* System handle. */
637
638 uint16_t mbx[28];
639};
640
641
642#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
643struct logio_entry_24xx {
644 uint8_t entry_type; /* Entry type. */
645 uint8_t entry_count; /* Entry count. */
646 uint8_t sys_define; /* System defined. */
647 uint8_t entry_status; /* Entry Status. */
648
649 uint32_t handle; /* System handle. */
650
651 uint16_t comp_status; /* Completion status. */
652#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
653
654 uint16_t nport_handle; /* N_PORT handle. */
655
656 uint16_t control_flags; /* Control flags. */
657 /* Modifiers. */
658#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
659#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
660#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
661#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
662#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
663#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
664#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
665#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
666#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
667 /* Commands. */
668#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
669#define LCF_COMMAND_PRLI 0x01 /* PRLI. */
670#define LCF_COMMAND_PDISC 0x02 /* PDISC. */
671#define LCF_COMMAND_ADISC 0x03 /* ADISC. */
672#define LCF_COMMAND_LOGO 0x08 /* LOGO. */
673#define LCF_COMMAND_PRLO 0x09 /* PRLO. */
674#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
675
676 uint8_t vp_index;
677 uint8_t reserved_1;
678
679 uint8_t port_id[3]; /* PortID of destination port. */
680
681 uint8_t rsp_size; /* Response size in 32bit words. */
682
683 uint32_t io_parameter[11]; /* General I/O parameters. */
684#define LSC_SCODE_NOLINK 0x01
685#define LSC_SCODE_NOIOCB 0x02
686#define LSC_SCODE_NOXCB 0x03
687#define LSC_SCODE_CMD_FAILED 0x04
688#define LSC_SCODE_NOFABRIC 0x05
689#define LSC_SCODE_FW_NOT_READY 0x07
690#define LSC_SCODE_NOT_LOGGED_IN 0x09
691#define LSC_SCODE_NOPCB 0x0A
692
693#define LSC_SCODE_ELS_REJECT 0x18
694#define LSC_SCODE_CMD_PARAM_ERR 0x19
695#define LSC_SCODE_PORTID_USED 0x1A
696#define LSC_SCODE_NPORT_USED 0x1B
697#define LSC_SCODE_NONPORT 0x1C
698#define LSC_SCODE_LOGGED_IN 0x1D
699#define LSC_SCODE_NOFLOGI_ACC 0x1F
700};
701
702#define TSK_MGMT_IOCB_TYPE 0x14
703struct tsk_mgmt_entry {
704 uint8_t entry_type; /* Entry type. */
705 uint8_t entry_count; /* Entry count. */
706 uint8_t handle_count; /* Handle count. */
707 uint8_t entry_status; /* Entry Status. */
708
709 uint32_t handle; /* System handle. */
710
711 uint16_t nport_handle; /* N_PORT handle. */
712
713 uint16_t reserved_1;
714
715 uint16_t delay; /* Activity delay in seconds. */
716
717 uint16_t timeout; /* Command timeout. */
718
719 uint8_t lun[8]; /* FCP LUN (BE). */
720
721 uint32_t control_flags; /* Control Flags. */
722#define TCF_NOTMCMD_TO_TARGET BIT_31
723#define TCF_LUN_RESET BIT_4
724#define TCF_ABORT_TASK_SET BIT_3
725#define TCF_CLEAR_TASK_SET BIT_2
726#define TCF_TARGET_RESET BIT_1
727#define TCF_CLEAR_ACA BIT_0
728
729 uint8_t reserved_2[20];
730
731 uint8_t port_id[3]; /* PortID of destination port. */
732 uint8_t vp_index;
733
734 uint8_t reserved_3[12];
735};
736
737#define ABORT_IOCB_TYPE 0x33
738struct abort_entry_24xx {
739 uint8_t entry_type; /* Entry type. */
740 uint8_t entry_count; /* Entry count. */
741 uint8_t handle_count; /* Handle count. */
742 uint8_t entry_status; /* Entry Status. */
743
744 uint32_t handle; /* System handle. */
745
746 uint16_t nport_handle; /* N_PORT handle. */
747 /* or Completion status. */
748
749 uint16_t options; /* Options. */
750#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
751
752 uint32_t handle_to_abort; /* System handle to abort. */
753
754 uint8_t reserved_1[32];
755
756 uint8_t port_id[3]; /* PortID of destination port. */
757 uint8_t vp_index;
758
759 uint8_t reserved_2[12];
760};
761
762/*
763 * ISP I/O Register Set structure definitions.
764 */
765struct device_reg_24xx {
766 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
767#define FARX_DATA_FLAG BIT_31
768#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
769#define FARX_ACCESS_FLASH_DATA 0x7FF00000
770#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
771#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
772
773#define FA_NVRAM_FUNC0_ADDR 0x80
774#define FA_NVRAM_FUNC1_ADDR 0x180
775
776#define FA_NVRAM_VPD_SIZE 0x80
777#define FA_NVRAM_VPD0_ADDR 0x00
778#define FA_NVRAM_VPD1_ADDR 0x100
779 /*
780 * RISC code begins at offset 512KB
781 * within flash. Consisting of two
782 * contiguous RISC code segments.
783 */
784#define FA_RISC_CODE_ADDR 0x20000
785#define FA_RISC_CODE_SEGMENTS 2
786
787 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
788
789 uint32_t ctrl_status; /* Control/Status. */
790#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
791#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
792#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
793#define CSRX_FUNCTION BIT_15 /* Function number. */
794 /* PCI-X Bus Mode. */
795#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
796#define PBM_PCI_33MHZ (0 << 8)
797#define PBM_PCIX_M1_66MHZ (1 << 8)
798#define PBM_PCIX_M1_100MHZ (2 << 8)
799#define PBM_PCIX_M1_133MHZ (3 << 8)
800#define PBM_PCIX_M2_66MHZ (5 << 8)
801#define PBM_PCIX_M2_100MHZ (6 << 8)
802#define PBM_PCIX_M2_133MHZ (7 << 8)
803#define PBM_PCI_66MHZ (8 << 8)
804 /* Max Write Burst byte count. */
805#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
806#define MWB_512_BYTES (0 << 4)
807#define MWB_1024_BYTES (1 << 4)
808#define MWB_2048_BYTES (2 << 4)
809#define MWB_4096_BYTES (3 << 4)
810
811#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
812#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
813#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
814
815 uint32_t ictrl; /* Interrupt control. */
816#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
817
818 uint32_t istatus; /* Interrupt status. */
819#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
820
821 uint32_t unused_1[2]; /* Gap. */
822
823 /* Request Queue. */
824 uint32_t req_q_in; /* In-Pointer. */
825 uint32_t req_q_out; /* Out-Pointer. */
826 /* Response Queue. */
827 uint32_t rsp_q_in; /* In-Pointer. */
828 uint32_t rsp_q_out; /* Out-Pointer. */
829 /* Priority Request Queue. */
830 uint32_t preq_q_in; /* In-Pointer. */
831 uint32_t preq_q_out; /* Out-Pointer. */
832
833 uint32_t unused_2[2]; /* Gap. */
834
835 /* ATIO Queue. */
836 uint32_t atio_q_in; /* In-Pointer. */
837 uint32_t atio_q_out; /* Out-Pointer. */
838
839 uint32_t host_status;
840#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
841#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
842
843 uint32_t hccr; /* Host command & control register. */
844 /* HCCR statuses. */
845#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
846#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
847#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */
848 /* HCCR commands. */
849 /* NOOP. */
850#define HCCRX_NOOP 0x00000000
851 /* Set RISC Reset. */
852#define HCCRX_SET_RISC_RESET 0x10000000
853 /* Clear RISC Reset. */
854#define HCCRX_CLR_RISC_RESET 0x20000000
855 /* Set RISC Pause. */
856#define HCCRX_SET_RISC_PAUSE 0x30000000
857 /* Releases RISC Pause. */
858#define HCCRX_REL_RISC_PAUSE 0x40000000
859 /* Set HOST to RISC interrupt. */
860#define HCCRX_SET_HOST_INT 0x50000000
861 /* Clear HOST to RISC interrupt. */
862#define HCCRX_CLR_HOST_INT 0x60000000
863 /* Clear RISC to PCI interrupt. */
864#define HCCRX_CLR_RISC_INT 0xA0000000
865
866 uint32_t gpiod; /* GPIO Data register. */
867 /* LED update mask. */
868#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
869 /* Data update mask. */
870#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
871 /* LED control mask. */
872#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
873 /* LED bit values. Color names as
874 * referenced in fw spec.
875 */
876#define GPDX_LED_YELLOW_ON BIT_2
877#define GPDX_LED_GREEN_ON BIT_3
878#define GPDX_LED_AMBER_ON BIT_4
879 /* Data in/out. */
880#define GPDX_DATA_INOUT (BIT_1|BIT_0)
881
882 uint32_t gpioe; /* GPIO Enable register. */
883 /* Enable update mask. */
884#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
885 /* Enable. */
886#define GPEX_ENABLE (BIT_1|BIT_0)
887
888 uint32_t iobase_addr; /* I/O Bus Base Address register. */
889
890 uint32_t unused_3[10]; /* Gap. */
891
892 uint16_t mailbox0;
893 uint16_t mailbox1;
894 uint16_t mailbox2;
895 uint16_t mailbox3;
896 uint16_t mailbox4;
897 uint16_t mailbox5;
898 uint16_t mailbox6;
899 uint16_t mailbox7;
900 uint16_t mailbox8;
901 uint16_t mailbox9;
902 uint16_t mailbox10;
903 uint16_t mailbox11;
904 uint16_t mailbox12;
905 uint16_t mailbox13;
906 uint16_t mailbox14;
907 uint16_t mailbox15;
908 uint16_t mailbox16;
909 uint16_t mailbox17;
910 uint16_t mailbox18;
911 uint16_t mailbox19;
912 uint16_t mailbox20;
913 uint16_t mailbox21;
914 uint16_t mailbox22;
915 uint16_t mailbox23;
916 uint16_t mailbox24;
917 uint16_t mailbox25;
918 uint16_t mailbox26;
919 uint16_t mailbox27;
920 uint16_t mailbox28;
921 uint16_t mailbox29;
922 uint16_t mailbox30;
923 uint16_t mailbox31;
924};
925
926/* MID Support ***************************************************************/
927
928#define MAX_MID_VPS 125
929
930struct mid_conf_entry_24xx {
931 uint16_t reserved_1;
932
933 /*
934 * BIT 0 = Enable Hard Loop Id
935 * BIT 1 = Acquire Loop ID in LIPA
936 * BIT 2 = ID not Acquired
937 * BIT 3 = Enable VP
938 * BIT 4 = Enable Initiator Mode
939 * BIT 5 = Disable Target Mode
940 * BIT 6-7 = Reserved
941 */
942 uint8_t options;
943
944 uint8_t hard_address;
945
946 uint8_t port_name[WWN_SIZE];
947 uint8_t node_name[WWN_SIZE];
948};
949
950struct mid_init_cb_24xx {
951 struct init_cb_24xx init_cb;
952
953 uint16_t count;
954 uint16_t options;
955
956 struct mid_conf_entry_24xx entries[MAX_MID_VPS];
957};
958
959
960struct mid_db_entry_24xx {
961 uint16_t status;
962#define MDBS_NON_PARTIC BIT_3
963#define MDBS_ID_ACQUIRED BIT_1
964#define MDBS_ENABLED BIT_0
965
966 uint8_t options;
967 uint8_t hard_address;
968
969 uint8_t port_name[WWN_SIZE];
970 uint8_t node_name[WWN_SIZE];
971
972 uint8_t port_id[3];
973 uint8_t reserved_1;
974};
975
976struct mid_db_24xx {
977 struct mid_db_entry_24xx entries[MAX_MID_VPS];
978};
979
980#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */
981struct vp_ctrl_entry_24xx {
982 uint8_t entry_type; /* Entry type. */
983 uint8_t entry_count; /* Entry count. */
984 uint8_t sys_define; /* System defined. */
985 uint8_t entry_status; /* Entry Status. */
986
987 uint32_t handle; /* System handle. */
988
989 uint16_t vp_idx_failed;
990
991 uint16_t comp_status; /* Completion status. */
992#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
993#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
994
995 uint16_t command;
996#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
997#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
998#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
999#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1000
1001 uint16_t vp_count;
1002
1003 uint8_t vp_idx_map[16];
1004
1005 uint8_t reserved_4[32];
1006};
1007
1008#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */
1009struct vp_config_entry_24xx {
1010 uint8_t entry_type; /* Entry type. */
1011 uint8_t entry_count; /* Entry count. */
1012 uint8_t sys_define; /* System defined. */
1013 uint8_t entry_status; /* Entry Status. */
1014
1015 uint32_t handle; /* System handle. */
1016
1017 uint16_t reserved_1;
1018
1019 uint16_t comp_status; /* Completion status. */
1020#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1021#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1022#define CS_VCT_ERROR 0x03 /* Unknown error. */
1023#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1024#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1025
1026 uint8_t command;
1027#define VCT_COMMAND_MOD_VPS 0x00 /* Enable VPs. */
1028#define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */
1029
1030 uint8_t vp_count;
1031
1032 uint8_t vp_idx1;
1033 uint8_t vp_idx2;
1034
1035 uint8_t options_idx1;
1036 uint8_t hard_address_idx1;
1037 uint16_t reserved_2;
1038 uint8_t port_name_idx1[WWN_SIZE];
1039 uint8_t node_name_idx1[WWN_SIZE];
1040
1041 uint8_t options_idx2;
1042 uint8_t hard_address_idx2;
1043 uint16_t reserved_3;
1044 uint8_t port_name_idx2[WWN_SIZE];
1045 uint8_t node_name_idx2[WWN_SIZE];
1046
1047 uint8_t reserved_4[8];
1048};
1049
1050#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1051struct vp_rpt_id_entry_24xx {
1052 uint8_t entry_type; /* Entry type. */
1053 uint8_t entry_count; /* Entry count. */
1054 uint8_t sys_define; /* System defined. */
1055 uint8_t entry_status; /* Entry Status. */
1056
1057 uint32_t handle; /* System handle. */
1058
1059 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */
1060 /* Format 1 -- | VP count |. */
1061 uint16_t vp_idx; /* Format 0 -- Reserved. */
1062 /* Format 1 -- VP status and index. */
1063
1064 uint8_t port_id[3];
1065 uint8_t format;
1066
1067 uint8_t vp_idx_map[16];
1068
1069 uint8_t reserved_4[32];
1070};
1071
1072/* END MID Support ***********************************************************/
1073#endif
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