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-rw-r--r--drivers/scsi/isci/phy.c1312
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diff --git a/drivers/scsi/isci/phy.c b/drivers/scsi/isci/phy.c
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1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56#include "isci.h"
57#include "host.h"
58#include "phy.h"
59#include "scu_event_codes.h"
60#include "probe_roms.h"
61
62/* Maximum arbitration wait time in micro-seconds */
63#define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME (700)
64
65enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy)
66{
67 return iphy->max_negotiated_speed;
68}
69
70static enum sci_status
71sci_phy_transport_layer_initialization(struct isci_phy *iphy,
72 struct scu_transport_layer_registers __iomem *reg)
73{
74 u32 tl_control;
75
76 iphy->transport_layer_registers = reg;
77
78 writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
79 &iphy->transport_layer_registers->stp_rni);
80
81 /*
82 * Hardware team recommends that we enable the STP prefetch for all
83 * transports
84 */
85 tl_control = readl(&iphy->transport_layer_registers->control);
86 tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
87 writel(tl_control, &iphy->transport_layer_registers->control);
88
89 return SCI_SUCCESS;
90}
91
92static enum sci_status
93sci_phy_link_layer_initialization(struct isci_phy *iphy,
94 struct scu_link_layer_registers __iomem *reg)
95{
96 struct isci_host *ihost = iphy->owning_port->owning_controller;
97 int phy_idx = iphy->phy_index;
98 struct sci_phy_user_params *phy_user = &ihost->user_parameters.phys[phy_idx];
99 struct sci_phy_oem_params *phy_oem =
100 &ihost->oem_parameters.phys[phy_idx];
101 u32 phy_configuration;
102 struct sci_phy_cap phy_cap;
103 u32 parity_check = 0;
104 u32 parity_count = 0;
105 u32 llctl, link_rate;
106 u32 clksm_value = 0;
107
108 iphy->link_layer_registers = reg;
109
110 /* Set our IDENTIFY frame data */
111 #define SCI_END_DEVICE 0x01
112
113 writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
114 SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
115 SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
116 SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
117 SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
118 &iphy->link_layer_registers->transmit_identification);
119
120 /* Write the device SAS Address */
121 writel(0xFEDCBA98,
122 &iphy->link_layer_registers->sas_device_name_high);
123 writel(phy_idx, &iphy->link_layer_registers->sas_device_name_low);
124
125 /* Write the source SAS Address */
126 writel(phy_oem->sas_address.high,
127 &iphy->link_layer_registers->source_sas_address_high);
128 writel(phy_oem->sas_address.low,
129 &iphy->link_layer_registers->source_sas_address_low);
130
131 /* Clear and Set the PHY Identifier */
132 writel(0, &iphy->link_layer_registers->identify_frame_phy_id);
133 writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx),
134 &iphy->link_layer_registers->identify_frame_phy_id);
135
136 /* Change the initial state of the phy configuration register */
137 phy_configuration =
138 readl(&iphy->link_layer_registers->phy_configuration);
139
140 /* Hold OOB state machine in reset */
141 phy_configuration |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
142 writel(phy_configuration,
143 &iphy->link_layer_registers->phy_configuration);
144
145 /* Configure the SNW capabilities */
146 phy_cap.all = 0;
147 phy_cap.start = 1;
148 phy_cap.gen3_no_ssc = 1;
149 phy_cap.gen2_no_ssc = 1;
150 phy_cap.gen1_no_ssc = 1;
151 if (ihost->oem_parameters.controller.do_enable_ssc == true) {
152 phy_cap.gen3_ssc = 1;
153 phy_cap.gen2_ssc = 1;
154 phy_cap.gen1_ssc = 1;
155 }
156
157 /*
158 * The SAS specification indicates that the phy_capabilities that
159 * are transmitted shall have an even parity. Calculate the parity. */
160 parity_check = phy_cap.all;
161 while (parity_check != 0) {
162 if (parity_check & 0x1)
163 parity_count++;
164 parity_check >>= 1;
165 }
166
167 /*
168 * If parity indicates there are an odd number of bits set, then
169 * set the parity bit to 1 in the phy capabilities. */
170 if ((parity_count % 2) != 0)
171 phy_cap.parity = 1;
172
173 writel(phy_cap.all, &iphy->link_layer_registers->phy_capabilities);
174
175 /* Set the enable spinup period but disable the ability to send
176 * notify enable spinup
177 */
178 writel(SCU_ENSPINUP_GEN_VAL(COUNT,
179 phy_user->notify_enable_spin_up_insertion_frequency),
180 &iphy->link_layer_registers->notify_enable_spinup_control);
181
182 /* Write the ALIGN Insertion Ferequency for connected phy and
183 * inpendent of connected state
184 */
185 clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
186 phy_user->in_connection_align_insertion_frequency);
187
188 clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
189 phy_user->align_insertion_frequency);
190
191 writel(clksm_value, &iphy->link_layer_registers->clock_skew_management);
192
193 /* @todo Provide a way to write this register correctly */
194 writel(0x02108421,
195 &iphy->link_layer_registers->afe_lookup_table_control);
196
197 llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
198 (u8)ihost->user_parameters.no_outbound_task_timeout);
199
200 switch(phy_user->max_speed_generation) {
201 case SCIC_SDS_PARM_GEN3_SPEED:
202 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
203 break;
204 case SCIC_SDS_PARM_GEN2_SPEED:
205 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
206 break;
207 default:
208 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
209 break;
210 }
211 llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
212 writel(llctl, &iphy->link_layer_registers->link_layer_control);
213
214 if (is_a2(ihost->pdev)) {
215 /* Program the max ARB time for the PHY to 700us so we inter-operate with
216 * the PMC expander which shuts down PHYs if the expander PHY generates too
217 * many breaks. This time value will guarantee that the initiator PHY will
218 * generate the break.
219 */
220 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
221 &iphy->link_layer_registers->maximum_arbitration_wait_timer_timeout);
222 }
223
224 /* Disable link layer hang detection, rely on the OS timeout for I/O timeouts. */
225 writel(0, &iphy->link_layer_registers->link_layer_hang_detection_timeout);
226
227 /* We can exit the initial state to the stopped state */
228 sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
229
230 return SCI_SUCCESS;
231}
232
233static void phy_sata_timeout(unsigned long data)
234{
235 struct sci_timer *tmr = (struct sci_timer *)data;
236 struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer);
237 struct isci_host *ihost = iphy->owning_port->owning_controller;
238 unsigned long flags;
239
240 spin_lock_irqsave(&ihost->scic_lock, flags);
241
242 if (tmr->cancel)
243 goto done;
244
245 dev_dbg(sciphy_to_dev(iphy),
246 "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
247 "timeout.\n",
248 __func__,
249 iphy);
250
251 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
252done:
253 spin_unlock_irqrestore(&ihost->scic_lock, flags);
254}
255
256/**
257 * This method returns the port currently containing this phy. If the phy is
258 * currently contained by the dummy port, then the phy is considered to not
259 * be part of a port.
260 * @sci_phy: This parameter specifies the phy for which to retrieve the
261 * containing port.
262 *
263 * This method returns a handle to a port that contains the supplied phy.
264 * NULL This value is returned if the phy is not part of a real
265 * port (i.e. it's contained in the dummy port). !NULL All other
266 * values indicate a handle/pointer to the port containing the phy.
267 */
268struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy)
269{
270 struct isci_port *iport = iphy->owning_port;
271
272 if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT)
273 return NULL;
274
275 return iphy->owning_port;
276}
277
278/**
279 * This method will assign a port to the phy object.
280 * @out]: iphy This parameter specifies the phy for which to assign a port
281 * object.
282 *
283 *
284 */
285void sci_phy_set_port(
286 struct isci_phy *iphy,
287 struct isci_port *iport)
288{
289 iphy->owning_port = iport;
290
291 if (iphy->bcn_received_while_port_unassigned) {
292 iphy->bcn_received_while_port_unassigned = false;
293 sci_port_broadcast_change_received(iphy->owning_port, iphy);
294 }
295}
296
297enum sci_status sci_phy_initialize(struct isci_phy *iphy,
298 struct scu_transport_layer_registers __iomem *tl,
299 struct scu_link_layer_registers __iomem *ll)
300{
301 /* Perfrom the initialization of the TL hardware */
302 sci_phy_transport_layer_initialization(iphy, tl);
303
304 /* Perofrm the initialization of the PE hardware */
305 sci_phy_link_layer_initialization(iphy, ll);
306
307 /* There is nothing that needs to be done in this state just
308 * transition to the stopped state
309 */
310 sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
311
312 return SCI_SUCCESS;
313}
314
315/**
316 * This method assigns the direct attached device ID for this phy.
317 *
318 * @iphy The phy for which the direct attached device id is to
319 * be assigned.
320 * @device_id The direct attached device ID to assign to the phy.
321 * This will either be the RNi for the device or an invalid RNi if there
322 * is no current device assigned to the phy.
323 */
324void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id)
325{
326 u32 tl_control;
327
328 writel(device_id, &iphy->transport_layer_registers->stp_rni);
329
330 /*
331 * The read should guarantee that the first write gets posted
332 * before the next write
333 */
334 tl_control = readl(&iphy->transport_layer_registers->control);
335 tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
336 writel(tl_control, &iphy->transport_layer_registers->control);
337}
338
339static void sci_phy_suspend(struct isci_phy *iphy)
340{
341 u32 scu_sas_pcfg_value;
342
343 scu_sas_pcfg_value =
344 readl(&iphy->link_layer_registers->phy_configuration);
345 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
346 writel(scu_sas_pcfg_value,
347 &iphy->link_layer_registers->phy_configuration);
348
349 sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
350}
351
352void sci_phy_resume(struct isci_phy *iphy)
353{
354 u32 scu_sas_pcfg_value;
355
356 scu_sas_pcfg_value =
357 readl(&iphy->link_layer_registers->phy_configuration);
358 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
359 writel(scu_sas_pcfg_value,
360 &iphy->link_layer_registers->phy_configuration);
361}
362
363void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
364{
365 sas->high = readl(&iphy->link_layer_registers->source_sas_address_high);
366 sas->low = readl(&iphy->link_layer_registers->source_sas_address_low);
367}
368
369void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
370{
371 struct sas_identify_frame *iaf;
372
373 iaf = &iphy->frame_rcvd.iaf;
374 memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE);
375}
376
377void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto)
378{
379 proto->all = readl(&iphy->link_layer_registers->transmit_identification);
380}
381
382enum sci_status sci_phy_start(struct isci_phy *iphy)
383{
384 enum sci_phy_states state = iphy->sm.current_state_id;
385
386 if (state != SCI_PHY_STOPPED) {
387 dev_dbg(sciphy_to_dev(iphy),
388 "%s: in wrong state: %d\n", __func__, state);
389 return SCI_FAILURE_INVALID_STATE;
390 }
391
392 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
393 return SCI_SUCCESS;
394}
395
396enum sci_status sci_phy_stop(struct isci_phy *iphy)
397{
398 enum sci_phy_states state = iphy->sm.current_state_id;
399
400 switch (state) {
401 case SCI_PHY_SUB_INITIAL:
402 case SCI_PHY_SUB_AWAIT_OSSP_EN:
403 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
404 case SCI_PHY_SUB_AWAIT_SAS_POWER:
405 case SCI_PHY_SUB_AWAIT_SATA_POWER:
406 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
407 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
408 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
409 case SCI_PHY_SUB_FINAL:
410 case SCI_PHY_READY:
411 break;
412 default:
413 dev_dbg(sciphy_to_dev(iphy),
414 "%s: in wrong state: %d\n", __func__, state);
415 return SCI_FAILURE_INVALID_STATE;
416 }
417
418 sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
419 return SCI_SUCCESS;
420}
421
422enum sci_status sci_phy_reset(struct isci_phy *iphy)
423{
424 enum sci_phy_states state = iphy->sm.current_state_id;
425
426 if (state != SCI_PHY_READY) {
427 dev_dbg(sciphy_to_dev(iphy),
428 "%s: in wrong state: %d\n", __func__, state);
429 return SCI_FAILURE_INVALID_STATE;
430 }
431
432 sci_change_state(&iphy->sm, SCI_PHY_RESETTING);
433 return SCI_SUCCESS;
434}
435
436enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy)
437{
438 enum sci_phy_states state = iphy->sm.current_state_id;
439
440 switch (state) {
441 case SCI_PHY_SUB_AWAIT_SAS_POWER: {
442 u32 enable_spinup;
443
444 enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
445 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
446 writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
447
448 /* Change state to the final state this substate machine has run to completion */
449 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
450
451 return SCI_SUCCESS;
452 }
453 case SCI_PHY_SUB_AWAIT_SATA_POWER: {
454 u32 scu_sas_pcfg_value;
455
456 /* Release the spinup hold state and reset the OOB state machine */
457 scu_sas_pcfg_value =
458 readl(&iphy->link_layer_registers->phy_configuration);
459 scu_sas_pcfg_value &=
460 ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
461 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
462 writel(scu_sas_pcfg_value,
463 &iphy->link_layer_registers->phy_configuration);
464
465 /* Now restart the OOB operation */
466 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
467 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
468 writel(scu_sas_pcfg_value,
469 &iphy->link_layer_registers->phy_configuration);
470
471 /* Change state to the final state this substate machine has run to completion */
472 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
473
474 return SCI_SUCCESS;
475 }
476 default:
477 dev_dbg(sciphy_to_dev(iphy),
478 "%s: in wrong state: %d\n", __func__, state);
479 return SCI_FAILURE_INVALID_STATE;
480 }
481}
482
483static void sci_phy_start_sas_link_training(struct isci_phy *iphy)
484{
485 /* continue the link training for the phy as if it were a SAS PHY
486 * instead of a SATA PHY. This is done because the completion queue had a SAS
487 * PHY DETECTED event when the state machine was expecting a SATA PHY event.
488 */
489 u32 phy_control;
490
491 phy_control = readl(&iphy->link_layer_registers->phy_configuration);
492 phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
493 writel(phy_control,
494 &iphy->link_layer_registers->phy_configuration);
495
496 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
497
498 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
499}
500
501static void sci_phy_start_sata_link_training(struct isci_phy *iphy)
502{
503 /* This method continues the link training for the phy as if it were a SATA PHY
504 * instead of a SAS PHY. This is done because the completion queue had a SATA
505 * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
506 */
507 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
508
509 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
510}
511
512/**
513 * sci_phy_complete_link_training - perform processing common to
514 * all protocols upon completion of link training.
515 * @sci_phy: This parameter specifies the phy object for which link training
516 * has completed.
517 * @max_link_rate: This parameter specifies the maximum link rate to be
518 * associated with this phy.
519 * @next_state: This parameter specifies the next state for the phy's starting
520 * sub-state machine.
521 *
522 */
523static void sci_phy_complete_link_training(struct isci_phy *iphy,
524 enum sas_linkrate max_link_rate,
525 u32 next_state)
526{
527 iphy->max_negotiated_speed = max_link_rate;
528
529 sci_change_state(&iphy->sm, next_state);
530}
531
532enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code)
533{
534 enum sci_phy_states state = iphy->sm.current_state_id;
535
536 switch (state) {
537 case SCI_PHY_SUB_AWAIT_OSSP_EN:
538 switch (scu_get_event_code(event_code)) {
539 case SCU_EVENT_SAS_PHY_DETECTED:
540 sci_phy_start_sas_link_training(iphy);
541 iphy->is_in_link_training = true;
542 break;
543 case SCU_EVENT_SATA_SPINUP_HOLD:
544 sci_phy_start_sata_link_training(iphy);
545 iphy->is_in_link_training = true;
546 break;
547 default:
548 dev_dbg(sciphy_to_dev(iphy),
549 "%s: PHY starting substate machine received "
550 "unexpected event_code %x\n",
551 __func__,
552 event_code);
553 return SCI_FAILURE;
554 }
555 return SCI_SUCCESS;
556 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
557 switch (scu_get_event_code(event_code)) {
558 case SCU_EVENT_SAS_PHY_DETECTED:
559 /*
560 * Why is this being reported again by the controller?
561 * We would re-enter this state so just stay here */
562 break;
563 case SCU_EVENT_SAS_15:
564 case SCU_EVENT_SAS_15_SSC:
565 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
566 SCI_PHY_SUB_AWAIT_IAF_UF);
567 break;
568 case SCU_EVENT_SAS_30:
569 case SCU_EVENT_SAS_30_SSC:
570 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
571 SCI_PHY_SUB_AWAIT_IAF_UF);
572 break;
573 case SCU_EVENT_SAS_60:
574 case SCU_EVENT_SAS_60_SSC:
575 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
576 SCI_PHY_SUB_AWAIT_IAF_UF);
577 break;
578 case SCU_EVENT_SATA_SPINUP_HOLD:
579 /*
580 * We were doing SAS PHY link training and received a SATA PHY event
581 * continue OOB/SN as if this were a SATA PHY */
582 sci_phy_start_sata_link_training(iphy);
583 break;
584 case SCU_EVENT_LINK_FAILURE:
585 /* Link failure change state back to the starting state */
586 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
587 break;
588 default:
589 dev_warn(sciphy_to_dev(iphy),
590 "%s: PHY starting substate machine received "
591 "unexpected event_code %x\n",
592 __func__, event_code);
593
594 return SCI_FAILURE;
595 break;
596 }
597 return SCI_SUCCESS;
598 case SCI_PHY_SUB_AWAIT_IAF_UF:
599 switch (scu_get_event_code(event_code)) {
600 case SCU_EVENT_SAS_PHY_DETECTED:
601 /* Backup the state machine */
602 sci_phy_start_sas_link_training(iphy);
603 break;
604 case SCU_EVENT_SATA_SPINUP_HOLD:
605 /* We were doing SAS PHY link training and received a
606 * SATA PHY event continue OOB/SN as if this were a
607 * SATA PHY
608 */
609 sci_phy_start_sata_link_training(iphy);
610 break;
611 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
612 case SCU_EVENT_LINK_FAILURE:
613 case SCU_EVENT_HARD_RESET_RECEIVED:
614 /* Start the oob/sn state machine over again */
615 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
616 break;
617 default:
618 dev_warn(sciphy_to_dev(iphy),
619 "%s: PHY starting substate machine received "
620 "unexpected event_code %x\n",
621 __func__, event_code);
622 return SCI_FAILURE;
623 }
624 return SCI_SUCCESS;
625 case SCI_PHY_SUB_AWAIT_SAS_POWER:
626 switch (scu_get_event_code(event_code)) {
627 case SCU_EVENT_LINK_FAILURE:
628 /* Link failure change state back to the starting state */
629 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
630 break;
631 default:
632 dev_warn(sciphy_to_dev(iphy),
633 "%s: PHY starting substate machine received unexpected "
634 "event_code %x\n",
635 __func__,
636 event_code);
637 return SCI_FAILURE;
638 }
639 return SCI_SUCCESS;
640 case SCI_PHY_SUB_AWAIT_SATA_POWER:
641 switch (scu_get_event_code(event_code)) {
642 case SCU_EVENT_LINK_FAILURE:
643 /* Link failure change state back to the starting state */
644 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
645 break;
646 case SCU_EVENT_SATA_SPINUP_HOLD:
647 /* These events are received every 10ms and are
648 * expected while in this state
649 */
650 break;
651
652 case SCU_EVENT_SAS_PHY_DETECTED:
653 /* There has been a change in the phy type before OOB/SN for the
654 * SATA finished start down the SAS link traning path.
655 */
656 sci_phy_start_sas_link_training(iphy);
657 break;
658
659 default:
660 dev_warn(sciphy_to_dev(iphy),
661 "%s: PHY starting substate machine received "
662 "unexpected event_code %x\n",
663 __func__, event_code);
664
665 return SCI_FAILURE;
666 }
667 return SCI_SUCCESS;
668 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
669 switch (scu_get_event_code(event_code)) {
670 case SCU_EVENT_LINK_FAILURE:
671 /* Link failure change state back to the starting state */
672 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
673 break;
674 case SCU_EVENT_SATA_SPINUP_HOLD:
675 /* These events might be received since we dont know how many may be in
676 * the completion queue while waiting for power
677 */
678 break;
679 case SCU_EVENT_SATA_PHY_DETECTED:
680 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
681
682 /* We have received the SATA PHY notification change state */
683 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
684 break;
685 case SCU_EVENT_SAS_PHY_DETECTED:
686 /* There has been a change in the phy type before OOB/SN for the
687 * SATA finished start down the SAS link traning path.
688 */
689 sci_phy_start_sas_link_training(iphy);
690 break;
691 default:
692 dev_warn(sciphy_to_dev(iphy),
693 "%s: PHY starting substate machine received "
694 "unexpected event_code %x\n",
695 __func__,
696 event_code);
697
698 return SCI_FAILURE;;
699 }
700 return SCI_SUCCESS;
701 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
702 switch (scu_get_event_code(event_code)) {
703 case SCU_EVENT_SATA_PHY_DETECTED:
704 /*
705 * The hardware reports multiple SATA PHY detected events
706 * ignore the extras */
707 break;
708 case SCU_EVENT_SATA_15:
709 case SCU_EVENT_SATA_15_SSC:
710 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
711 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
712 break;
713 case SCU_EVENT_SATA_30:
714 case SCU_EVENT_SATA_30_SSC:
715 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
716 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
717 break;
718 case SCU_EVENT_SATA_60:
719 case SCU_EVENT_SATA_60_SSC:
720 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
721 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
722 break;
723 case SCU_EVENT_LINK_FAILURE:
724 /* Link failure change state back to the starting state */
725 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
726 break;
727 case SCU_EVENT_SAS_PHY_DETECTED:
728 /*
729 * There has been a change in the phy type before OOB/SN for the
730 * SATA finished start down the SAS link traning path. */
731 sci_phy_start_sas_link_training(iphy);
732 break;
733 default:
734 dev_warn(sciphy_to_dev(iphy),
735 "%s: PHY starting substate machine received "
736 "unexpected event_code %x\n",
737 __func__, event_code);
738
739 return SCI_FAILURE;
740 }
741
742 return SCI_SUCCESS;
743 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
744 switch (scu_get_event_code(event_code)) {
745 case SCU_EVENT_SATA_PHY_DETECTED:
746 /* Backup the state machine */
747 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
748 break;
749
750 case SCU_EVENT_LINK_FAILURE:
751 /* Link failure change state back to the starting state */
752 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
753 break;
754
755 default:
756 dev_warn(sciphy_to_dev(iphy),
757 "%s: PHY starting substate machine received "
758 "unexpected event_code %x\n",
759 __func__,
760 event_code);
761
762 return SCI_FAILURE;
763 }
764 return SCI_SUCCESS;
765 case SCI_PHY_READY:
766 switch (scu_get_event_code(event_code)) {
767 case SCU_EVENT_LINK_FAILURE:
768 /* Link failure change state back to the starting state */
769 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
770 break;
771 case SCU_EVENT_BROADCAST_CHANGE:
772 /* Broadcast change received. Notify the port. */
773 if (phy_get_non_dummy_port(iphy) != NULL)
774 sci_port_broadcast_change_received(iphy->owning_port, iphy);
775 else
776 iphy->bcn_received_while_port_unassigned = true;
777 break;
778 default:
779 dev_warn(sciphy_to_dev(iphy),
780 "%sP SCIC PHY 0x%p ready state machine received "
781 "unexpected event_code %x\n",
782 __func__, iphy, event_code);
783 return SCI_FAILURE_INVALID_STATE;
784 }
785 return SCI_SUCCESS;
786 case SCI_PHY_RESETTING:
787 switch (scu_get_event_code(event_code)) {
788 case SCU_EVENT_HARD_RESET_TRANSMITTED:
789 /* Link failure change state back to the starting state */
790 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
791 break;
792 default:
793 dev_warn(sciphy_to_dev(iphy),
794 "%s: SCIC PHY 0x%p resetting state machine received "
795 "unexpected event_code %x\n",
796 __func__, iphy, event_code);
797
798 return SCI_FAILURE_INVALID_STATE;
799 break;
800 }
801 return SCI_SUCCESS;
802 default:
803 dev_dbg(sciphy_to_dev(iphy),
804 "%s: in wrong state: %d\n", __func__, state);
805 return SCI_FAILURE_INVALID_STATE;
806 }
807}
808
809enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index)
810{
811 enum sci_phy_states state = iphy->sm.current_state_id;
812 struct isci_host *ihost = iphy->owning_port->owning_controller;
813 enum sci_status result;
814 unsigned long flags;
815
816 switch (state) {
817 case SCI_PHY_SUB_AWAIT_IAF_UF: {
818 u32 *frame_words;
819 struct sas_identify_frame iaf;
820
821 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
822 frame_index,
823 (void **)&frame_words);
824
825 if (result != SCI_SUCCESS)
826 return result;
827
828 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
829 if (iaf.frame_type == 0) {
830 u32 state;
831
832 spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
833 memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
834 spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
835 if (iaf.smp_tport) {
836 /* We got the IAF for an expander PHY go to the final
837 * state since there are no power requirements for
838 * expander phys.
839 */
840 state = SCI_PHY_SUB_FINAL;
841 } else {
842 /* We got the IAF we can now go to the await spinup
843 * semaphore state
844 */
845 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
846 }
847 sci_change_state(&iphy->sm, state);
848 result = SCI_SUCCESS;
849 } else
850 dev_warn(sciphy_to_dev(iphy),
851 "%s: PHY starting substate machine received "
852 "unexpected frame id %x\n",
853 __func__, frame_index);
854
855 sci_controller_release_frame(ihost, frame_index);
856 return result;
857 }
858 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
859 struct dev_to_host_fis *frame_header;
860 u32 *fis_frame_data;
861
862 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
863 frame_index,
864 (void **)&frame_header);
865
866 if (result != SCI_SUCCESS)
867 return result;
868
869 if ((frame_header->fis_type == FIS_REGD2H) &&
870 !(frame_header->status & ATA_BUSY)) {
871 sci_unsolicited_frame_control_get_buffer(&ihost->uf_control,
872 frame_index,
873 (void **)&fis_frame_data);
874
875 spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
876 sci_controller_copy_sata_response(&iphy->frame_rcvd.fis,
877 frame_header,
878 fis_frame_data);
879 spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
880
881 /* got IAF we can now go to the await spinup semaphore state */
882 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
883
884 result = SCI_SUCCESS;
885 } else
886 dev_warn(sciphy_to_dev(iphy),
887 "%s: PHY starting substate machine received "
888 "unexpected frame id %x\n",
889 __func__, frame_index);
890
891 /* Regardless of the result we are done with this frame with it */
892 sci_controller_release_frame(ihost, frame_index);
893
894 return result;
895 }
896 default:
897 dev_dbg(sciphy_to_dev(iphy),
898 "%s: in wrong state: %d\n", __func__, state);
899 return SCI_FAILURE_INVALID_STATE;
900 }
901
902}
903
904static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
905{
906 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
907
908 /* This is just an temporary state go off to the starting state */
909 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
910}
911
912static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
913{
914 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
915 struct isci_host *ihost = iphy->owning_port->owning_controller;
916
917 sci_controller_power_control_queue_insert(ihost, iphy);
918}
919
920static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
921{
922 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
923 struct isci_host *ihost = iphy->owning_port->owning_controller;
924
925 sci_controller_power_control_queue_remove(ihost, iphy);
926}
927
928static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
929{
930 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
931 struct isci_host *ihost = iphy->owning_port->owning_controller;
932
933 sci_controller_power_control_queue_insert(ihost, iphy);
934}
935
936static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
937{
938 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
939 struct isci_host *ihost = iphy->owning_port->owning_controller;
940
941 sci_controller_power_control_queue_remove(ihost, iphy);
942}
943
944static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
945{
946 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
947
948 sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
949}
950
951static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
952{
953 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
954
955 sci_del_timer(&iphy->sata_timer);
956}
957
958static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
959{
960 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
961
962 sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
963}
964
965static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
966{
967 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
968
969 sci_del_timer(&iphy->sata_timer);
970}
971
972static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
973{
974 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
975
976 if (sci_port_link_detected(iphy->owning_port, iphy)) {
977
978 /*
979 * Clear the PE suspend condition so we can actually
980 * receive SIG FIS
981 * The hardware will not respond to the XRDY until the PE
982 * suspend condition is cleared.
983 */
984 sci_phy_resume(iphy);
985
986 sci_mod_timer(&iphy->sata_timer,
987 SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
988 } else
989 iphy->is_in_link_training = false;
990}
991
992static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
993{
994 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
995
996 sci_del_timer(&iphy->sata_timer);
997}
998
999static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1000{
1001 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1002
1003 /* State machine has run to completion so exit out and change
1004 * the base state machine to the ready state
1005 */
1006 sci_change_state(&iphy->sm, SCI_PHY_READY);
1007}
1008
1009/**
1010 *
1011 * @sci_phy: This is the struct isci_phy object to stop.
1012 *
1013 * This method will stop the struct isci_phy object. This does not reset the
1014 * protocol engine it just suspends it and places it in a state where it will
1015 * not cause the end device to power up. none
1016 */
1017static void scu_link_layer_stop_protocol_engine(
1018 struct isci_phy *iphy)
1019{
1020 u32 scu_sas_pcfg_value;
1021 u32 enable_spinup_value;
1022
1023 /* Suspend the protocol engine and place it in a sata spinup hold state */
1024 scu_sas_pcfg_value =
1025 readl(&iphy->link_layer_registers->phy_configuration);
1026 scu_sas_pcfg_value |=
1027 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1028 SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1029 SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1030 writel(scu_sas_pcfg_value,
1031 &iphy->link_layer_registers->phy_configuration);
1032
1033 /* Disable the notify enable spinup primitives */
1034 enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
1035 enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1036 writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
1037}
1038
1039/**
1040 *
1041 *
1042 * This method will start the OOB/SN state machine for this struct isci_phy object.
1043 */
1044static void scu_link_layer_start_oob(
1045 struct isci_phy *iphy)
1046{
1047 u32 scu_sas_pcfg_value;
1048
1049 scu_sas_pcfg_value =
1050 readl(&iphy->link_layer_registers->phy_configuration);
1051 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1052 scu_sas_pcfg_value &=
1053 ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1054 SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1055 writel(scu_sas_pcfg_value,
1056 &iphy->link_layer_registers->phy_configuration);
1057}
1058
1059/**
1060 *
1061 *
1062 * This method will transmit a hard reset request on the specified phy. The SCU
1063 * hardware requires that we reset the OOB state machine and set the hard reset
1064 * bit in the phy configuration register. We then must start OOB over with the
1065 * hard reset bit set.
1066 */
1067static void scu_link_layer_tx_hard_reset(
1068 struct isci_phy *iphy)
1069{
1070 u32 phy_configuration_value;
1071
1072 /*
1073 * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1074 * to the starting state. */
1075 phy_configuration_value =
1076 readl(&iphy->link_layer_registers->phy_configuration);
1077 phy_configuration_value |=
1078 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1079 SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1080 writel(phy_configuration_value,
1081 &iphy->link_layer_registers->phy_configuration);
1082
1083 /* Now take the OOB state machine out of reset */
1084 phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1085 phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1086 writel(phy_configuration_value,
1087 &iphy->link_layer_registers->phy_configuration);
1088}
1089
1090static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1091{
1092 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1093 struct isci_port *iport = iphy->owning_port;
1094 struct isci_host *ihost = iport->owning_controller;
1095
1096 /*
1097 * @todo We need to get to the controller to place this PE in a
1098 * reset state
1099 */
1100 sci_del_timer(&iphy->sata_timer);
1101
1102 scu_link_layer_stop_protocol_engine(iphy);
1103
1104 if (iphy->sm.previous_state_id != SCI_PHY_INITIAL)
1105 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1106}
1107
1108static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm)
1109{
1110 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1111 struct isci_port *iport = iphy->owning_port;
1112 struct isci_host *ihost = iport->owning_controller;
1113
1114 scu_link_layer_stop_protocol_engine(iphy);
1115 scu_link_layer_start_oob(iphy);
1116
1117 /* We don't know what kind of phy we are going to be just yet */
1118 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1119 iphy->bcn_received_while_port_unassigned = false;
1120
1121 if (iphy->sm.previous_state_id == SCI_PHY_READY)
1122 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1123
1124 sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL);
1125}
1126
1127static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm)
1128{
1129 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1130 struct isci_port *iport = iphy->owning_port;
1131 struct isci_host *ihost = iport->owning_controller;
1132
1133 sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy);
1134}
1135
1136static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm)
1137{
1138 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1139
1140 sci_phy_suspend(iphy);
1141}
1142
1143static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1144{
1145 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1146
1147 /* The phy is being reset, therefore deactivate it from the port. In
1148 * the resetting state we don't notify the user regarding link up and
1149 * link down notifications
1150 */
1151 sci_port_deactivate_phy(iphy->owning_port, iphy, false);
1152
1153 if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1154 scu_link_layer_tx_hard_reset(iphy);
1155 } else {
1156 /* The SCU does not need to have a discrete reset state so
1157 * just go back to the starting state.
1158 */
1159 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
1160 }
1161}
1162
1163static const struct sci_base_state sci_phy_state_table[] = {
1164 [SCI_PHY_INITIAL] = { },
1165 [SCI_PHY_STOPPED] = {
1166 .enter_state = sci_phy_stopped_state_enter,
1167 },
1168 [SCI_PHY_STARTING] = {
1169 .enter_state = sci_phy_starting_state_enter,
1170 },
1171 [SCI_PHY_SUB_INITIAL] = {
1172 .enter_state = sci_phy_starting_initial_substate_enter,
1173 },
1174 [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1175 [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1176 [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1177 [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1178 .enter_state = sci_phy_starting_await_sas_power_substate_enter,
1179 .exit_state = sci_phy_starting_await_sas_power_substate_exit,
1180 },
1181 [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1182 .enter_state = sci_phy_starting_await_sata_power_substate_enter,
1183 .exit_state = sci_phy_starting_await_sata_power_substate_exit
1184 },
1185 [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1186 .enter_state = sci_phy_starting_await_sata_phy_substate_enter,
1187 .exit_state = sci_phy_starting_await_sata_phy_substate_exit
1188 },
1189 [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1190 .enter_state = sci_phy_starting_await_sata_speed_substate_enter,
1191 .exit_state = sci_phy_starting_await_sata_speed_substate_exit
1192 },
1193 [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1194 .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter,
1195 .exit_state = sci_phy_starting_await_sig_fis_uf_substate_exit
1196 },
1197 [SCI_PHY_SUB_FINAL] = {
1198 .enter_state = sci_phy_starting_final_substate_enter,
1199 },
1200 [SCI_PHY_READY] = {
1201 .enter_state = sci_phy_ready_state_enter,
1202 .exit_state = sci_phy_ready_state_exit,
1203 },
1204 [SCI_PHY_RESETTING] = {
1205 .enter_state = sci_phy_resetting_state_enter,
1206 },
1207 [SCI_PHY_FINAL] = { },
1208};
1209
1210void sci_phy_construct(struct isci_phy *iphy,
1211 struct isci_port *iport, u8 phy_index)
1212{
1213 sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL);
1214
1215 /* Copy the rest of the input data to our locals */
1216 iphy->owning_port = iport;
1217 iphy->phy_index = phy_index;
1218 iphy->bcn_received_while_port_unassigned = false;
1219 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1220 iphy->link_layer_registers = NULL;
1221 iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1222
1223 /* Create the SIGNATURE FIS Timeout timer for this phy */
1224 sci_init_timer(&iphy->sata_timer, phy_sata_timeout);
1225}
1226
1227void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1228{
1229 struct sci_oem_params *oem = &ihost->oem_parameters;
1230 u64 sci_sas_addr;
1231 __be64 sas_addr;
1232
1233 sci_sas_addr = oem->phys[index].sas_address.high;
1234 sci_sas_addr <<= 32;
1235 sci_sas_addr |= oem->phys[index].sas_address.low;
1236 sas_addr = cpu_to_be64(sci_sas_addr);
1237 memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1238
1239 iphy->isci_port = NULL;
1240 iphy->sas_phy.enabled = 0;
1241 iphy->sas_phy.id = index;
1242 iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1243 iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1244 iphy->sas_phy.ha = &ihost->sas_ha;
1245 iphy->sas_phy.lldd_phy = iphy;
1246 iphy->sas_phy.enabled = 1;
1247 iphy->sas_phy.class = SAS;
1248 iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1249 iphy->sas_phy.tproto = 0;
1250 iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1251 iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1252 iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1253 iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1254 memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1255}
1256
1257
1258/**
1259 * isci_phy_control() - This function is one of the SAS Domain Template
1260 * functions. This is a phy management function.
1261 * @phy: This parameter specifies the sphy being controlled.
1262 * @func: This parameter specifies the phy control function being invoked.
1263 * @buf: This parameter is specific to the phy function being invoked.
1264 *
1265 * status, zero indicates success.
1266 */
1267int isci_phy_control(struct asd_sas_phy *sas_phy,
1268 enum phy_func func,
1269 void *buf)
1270{
1271 int ret = 0;
1272 struct isci_phy *iphy = sas_phy->lldd_phy;
1273 struct isci_port *iport = iphy->isci_port;
1274 struct isci_host *ihost = sas_phy->ha->lldd_ha;
1275 unsigned long flags;
1276
1277 dev_dbg(&ihost->pdev->dev,
1278 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1279 __func__, sas_phy, func, buf, iphy, iport);
1280
1281 switch (func) {
1282 case PHY_FUNC_DISABLE:
1283 spin_lock_irqsave(&ihost->scic_lock, flags);
1284 sci_phy_stop(iphy);
1285 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1286 break;
1287
1288 case PHY_FUNC_LINK_RESET:
1289 spin_lock_irqsave(&ihost->scic_lock, flags);
1290 sci_phy_stop(iphy);
1291 sci_phy_start(iphy);
1292 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1293 break;
1294
1295 case PHY_FUNC_HARD_RESET:
1296 if (!iport)
1297 return -ENODEV;
1298
1299 /* Perform the port reset. */
1300 ret = isci_port_perform_hard_reset(ihost, iport, iphy);
1301
1302 break;
1303
1304 default:
1305 dev_dbg(&ihost->pdev->dev,
1306 "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1307 __func__, sas_phy, func);
1308 ret = -ENOSYS;
1309 break;
1310 }
1311 return ret;
1312}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 07:19:23 -0500