diff options
Diffstat (limited to 'drivers/scsi/csiostor')
-rw-r--r-- | drivers/scsi/csiostor/csio_hw.c | 61 | ||||
-rw-r--r-- | drivers/scsi/csiostor/csio_hw_chip.h | 43 | ||||
-rw-r--r-- | drivers/scsi/csiostor/csio_init.c | 6 | ||||
-rw-r--r-- | drivers/scsi/csiostor/csio_wr.c | 15 |
4 files changed, 24 insertions, 101 deletions
diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c index 5c31fa603de4..35c5f83b08a0 100644 --- a/drivers/scsi/csiostor/csio_hw.c +++ b/drivers/scsi/csiostor/csio_hw.c | |||
@@ -60,37 +60,10 @@ int csio_msi = 2; | |||
60 | static int dev_num; | 60 | static int dev_num; |
61 | 61 | ||
62 | /* FCoE Adapter types & its description */ | 62 | /* FCoE Adapter types & its description */ |
63 | static const struct csio_adap_desc csio_t4_fcoe_adapters[] = { | ||
64 | {"T440-Dbg 10G", "Chelsio T440-Dbg 10G [FCoE]"}, | ||
65 | {"T420-CR 10G", "Chelsio T420-CR 10G [FCoE]"}, | ||
66 | {"T422-CR 10G/1G", "Chelsio T422-CR 10G/1G [FCoE]"}, | ||
67 | {"T440-CR 10G", "Chelsio T440-CR 10G [FCoE]"}, | ||
68 | {"T420-BCH 10G", "Chelsio T420-BCH 10G [FCoE]"}, | ||
69 | {"T440-BCH 10G", "Chelsio T440-BCH 10G [FCoE]"}, | ||
70 | {"T440-CH 10G", "Chelsio T440-CH 10G [FCoE]"}, | ||
71 | {"T420-SO 10G", "Chelsio T420-SO 10G [FCoE]"}, | ||
72 | {"T420-CX4 10G", "Chelsio T420-CX4 10G [FCoE]"}, | ||
73 | {"T420-BT 10G", "Chelsio T420-BT 10G [FCoE]"}, | ||
74 | {"T404-BT 1G", "Chelsio T404-BT 1G [FCoE]"}, | ||
75 | {"B420-SR 10G", "Chelsio B420-SR 10G [FCoE]"}, | ||
76 | {"B404-BT 1G", "Chelsio B404-BT 1G [FCoE]"}, | ||
77 | {"T480-CR 10G", "Chelsio T480-CR 10G [FCoE]"}, | ||
78 | {"T440-LP-CR 10G", "Chelsio T440-LP-CR 10G [FCoE]"}, | ||
79 | {"AMSTERDAM 10G", "Chelsio AMSTERDAM 10G [FCoE]"}, | ||
80 | {"HUAWEI T480 10G", "Chelsio HUAWEI T480 10G [FCoE]"}, | ||
81 | {"HUAWEI T440 10G", "Chelsio HUAWEI T440 10G [FCoE]"}, | ||
82 | {"HUAWEI STG 10G", "Chelsio HUAWEI STG 10G [FCoE]"}, | ||
83 | {"ACROMAG XAUI 10G", "Chelsio ACROMAG XAUI 10G [FCoE]"}, | ||
84 | {"ACROMAG SFP+ 10G", "Chelsio ACROMAG SFP+ 10G [FCoE]"}, | ||
85 | {"QUANTA SFP+ 10G", "Chelsio QUANTA SFP+ 10G [FCoE]"}, | ||
86 | {"HUAWEI 10Gbase-T", "Chelsio HUAWEI 10Gbase-T [FCoE]"}, | ||
87 | {"HUAWEI T4TOE 10G", "Chelsio HUAWEI T4TOE 10G [FCoE]"} | ||
88 | }; | ||
89 | |||
90 | static const struct csio_adap_desc csio_t5_fcoe_adapters[] = { | 63 | static const struct csio_adap_desc csio_t5_fcoe_adapters[] = { |
91 | {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"}, | 64 | {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"}, |
92 | {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"}, | 65 | {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"}, |
93 | {"T522-CR 10G/1G", "Chelsio T452-CR 10G/1G [FCoE]"}, | 66 | {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"}, |
94 | {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"}, | 67 | {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"}, |
95 | {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"}, | 68 | {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"}, |
96 | {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"}, | 69 | {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"}, |
@@ -107,7 +80,9 @@ static const struct csio_adap_desc csio_t5_fcoe_adapters[] = { | |||
107 | {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"}, | 80 | {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"}, |
108 | {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"}, | 81 | {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"}, |
109 | {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"}, | 82 | {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"}, |
110 | {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"} | 83 | {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"}, |
84 | {"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"}, | ||
85 | {"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"} | ||
111 | }; | 86 | }; |
112 | 87 | ||
113 | static void csio_mgmtm_cleanup(struct csio_mgmtm *); | 88 | static void csio_mgmtm_cleanup(struct csio_mgmtm *); |
@@ -1716,9 +1691,9 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path) | |||
1716 | uint32_t *cfg_data; | 1691 | uint32_t *cfg_data; |
1717 | int value_to_add = 0; | 1692 | int value_to_add = 0; |
1718 | 1693 | ||
1719 | if (request_firmware(&cf, CSIO_CF_FNAME(hw), dev) < 0) { | 1694 | if (request_firmware(&cf, FW_CFG_NAME_T5, dev) < 0) { |
1720 | csio_err(hw, "could not find config file %s, err: %d\n", | 1695 | csio_err(hw, "could not find config file %s, err: %d\n", |
1721 | CSIO_CF_FNAME(hw), ret); | 1696 | FW_CFG_NAME_T5, ret); |
1722 | return -ENOENT; | 1697 | return -ENOENT; |
1723 | } | 1698 | } |
1724 | 1699 | ||
@@ -1758,8 +1733,8 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path) | |||
1758 | } | 1733 | } |
1759 | if (ret == 0) { | 1734 | if (ret == 0) { |
1760 | csio_info(hw, "config file upgraded to %s\n", | 1735 | csio_info(hw, "config file upgraded to %s\n", |
1761 | CSIO_CF_FNAME(hw)); | 1736 | FW_CFG_NAME_T5); |
1762 | snprintf(path, 64, "%s%s", "/lib/firmware/", CSIO_CF_FNAME(hw)); | 1737 | snprintf(path, 64, "%s%s", "/lib/firmware/", FW_CFG_NAME_T5); |
1763 | } | 1738 | } |
1764 | 1739 | ||
1765 | leave: | 1740 | leave: |
@@ -2123,9 +2098,9 @@ csio_hw_flash_fw(struct csio_hw *hw, int *reset) | |||
2123 | return -EINVAL; | 2098 | return -EINVAL; |
2124 | } | 2099 | } |
2125 | 2100 | ||
2126 | if (request_firmware(&fw, CSIO_FW_FNAME(hw), dev) < 0) { | 2101 | if (request_firmware(&fw, FW_FNAME_T5, dev) < 0) { |
2127 | csio_err(hw, "could not find firmware image %s, err: %d\n", | 2102 | csio_err(hw, "could not find firmware image %s, err: %d\n", |
2128 | CSIO_FW_FNAME(hw), ret); | 2103 | FW_FNAME_T5, ret); |
2129 | return -EINVAL; | 2104 | return -EINVAL; |
2130 | } | 2105 | } |
2131 | 2106 | ||
@@ -3207,7 +3182,7 @@ static void csio_ncsi_intr_handler(struct csio_hw *hw) | |||
3207 | */ | 3182 | */ |
3208 | static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) | 3183 | static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) |
3209 | { | 3184 | { |
3210 | uint32_t v = csio_rd_reg32(hw, CSIO_MAC_INT_CAUSE_REG(hw, port)); | 3185 | uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); |
3211 | 3186 | ||
3212 | v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; | 3187 | v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; |
3213 | if (!v) | 3188 | if (!v) |
@@ -3217,7 +3192,7 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) | |||
3217 | csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); | 3192 | csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); |
3218 | if (v & RXFIFO_PRTY_ERR_F) | 3193 | if (v & RXFIFO_PRTY_ERR_F) |
3219 | csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); | 3194 | csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); |
3220 | csio_wr_reg32(hw, v, CSIO_MAC_INT_CAUSE_REG(hw, port)); | 3195 | csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); |
3221 | csio_hw_fatal_err(hw); | 3196 | csio_hw_fatal_err(hw); |
3222 | } | 3197 | } |
3223 | 3198 | ||
@@ -3966,13 +3941,7 @@ csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id) | |||
3966 | prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK); | 3941 | prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK); |
3967 | adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK); | 3942 | adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK); |
3968 | 3943 | ||
3969 | if (prot_type == CSIO_T4_FCOE_ASIC) { | 3944 | if (prot_type == CSIO_T5_FCOE_ASIC) { |
3970 | memcpy(hw->hw_ver, | ||
3971 | csio_t4_fcoe_adapters[adap_type].model_no, 16); | ||
3972 | memcpy(hw->model_desc, | ||
3973 | csio_t4_fcoe_adapters[adap_type].description, | ||
3974 | 32); | ||
3975 | } else if (prot_type == CSIO_T5_FCOE_ASIC) { | ||
3976 | memcpy(hw->hw_ver, | 3945 | memcpy(hw->hw_ver, |
3977 | csio_t5_fcoe_adapters[adap_type].model_no, 16); | 3946 | csio_t5_fcoe_adapters[adap_type].model_no, 16); |
3978 | memcpy(hw->model_desc, | 3947 | memcpy(hw->model_desc, |
@@ -4009,8 +3978,8 @@ csio_hw_init(struct csio_hw *hw) | |||
4009 | 3978 | ||
4010 | strcpy(hw->name, CSIO_HW_NAME); | 3979 | strcpy(hw->name, CSIO_HW_NAME); |
4011 | 3980 | ||
4012 | /* Initialize the HW chip ops with T4/T5 specific ops */ | 3981 | /* Initialize the HW chip ops T5 specific ops */ |
4013 | hw->chip_ops = csio_is_t4(hw->chip_id) ? &t4_ops : &t5_ops; | 3982 | hw->chip_ops = &t5_ops; |
4014 | 3983 | ||
4015 | /* Set the model & its description */ | 3984 | /* Set the model & its description */ |
4016 | 3985 | ||
diff --git a/drivers/scsi/csiostor/csio_hw_chip.h b/drivers/scsi/csiostor/csio_hw_chip.h index eec98f523ec9..e962d3df7f04 100644 --- a/drivers/scsi/csiostor/csio_hw_chip.h +++ b/drivers/scsi/csiostor/csio_hw_chip.h | |||
@@ -37,24 +37,14 @@ | |||
37 | #include "csio_defs.h" | 37 | #include "csio_defs.h" |
38 | 38 | ||
39 | /* Define MACRO values */ | 39 | /* Define MACRO values */ |
40 | #define CSIO_HW_T4 0x4000 | ||
41 | #define CSIO_T4_FCOE_ASIC 0x4600 | ||
42 | #define CSIO_HW_T5 0x5000 | 40 | #define CSIO_HW_T5 0x5000 |
43 | #define CSIO_T5_FCOE_ASIC 0x5600 | 41 | #define CSIO_T5_FCOE_ASIC 0x5600 |
44 | #define CSIO_HW_CHIP_MASK 0xF000 | 42 | #define CSIO_HW_CHIP_MASK 0xF000 |
45 | 43 | ||
46 | #define T4_REGMAP_SIZE (160 * 1024) | ||
47 | #define T5_REGMAP_SIZE (332 * 1024) | 44 | #define T5_REGMAP_SIZE (332 * 1024) |
48 | #define FW_FNAME_T4 "cxgb4/t4fw.bin" | ||
49 | #define FW_FNAME_T5 "cxgb4/t5fw.bin" | 45 | #define FW_FNAME_T5 "cxgb4/t5fw.bin" |
50 | #define FW_CFG_NAME_T4 "cxgb4/t4-config.txt" | ||
51 | #define FW_CFG_NAME_T5 "cxgb4/t5-config.txt" | 46 | #define FW_CFG_NAME_T5 "cxgb4/t5-config.txt" |
52 | 47 | ||
53 | #define T4FW_VERSION_MAJOR 0x01 | ||
54 | #define T4FW_VERSION_MINOR 0x0B | ||
55 | #define T4FW_VERSION_MICRO 0x1B | ||
56 | #define T4FW_VERSION_BUILD 0x00 | ||
57 | |||
58 | #define T5FW_VERSION_MAJOR 0x01 | 48 | #define T5FW_VERSION_MAJOR 0x01 |
59 | #define T5FW_VERSION_MINOR 0x0B | 49 | #define T5FW_VERSION_MINOR 0x0B |
60 | #define T5FW_VERSION_MICRO 0x1B | 50 | #define T5FW_VERSION_MICRO 0x1B |
@@ -65,27 +55,15 @@ | |||
65 | #define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf) | 55 | #define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf) |
66 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) | 56 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) |
67 | 57 | ||
68 | #define CHELSIO_T4 0x4 | ||
69 | #define CHELSIO_T5 0x5 | 58 | #define CHELSIO_T5 0x5 |
70 | 59 | ||
71 | enum chip_type { | 60 | enum chip_type { |
72 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), | ||
73 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), | ||
74 | T4_FIRST_REV = T4_A1, | ||
75 | T4_LAST_REV = T4_A2, | ||
76 | |||
77 | T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), | 61 | T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), |
78 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), | 62 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), |
79 | T5_FIRST_REV = T5_A0, | 63 | T5_FIRST_REV = T5_A0, |
80 | T5_LAST_REV = T5_A1, | 64 | T5_LAST_REV = T5_A1, |
81 | }; | 65 | }; |
82 | 66 | ||
83 | /* Define static functions */ | ||
84 | static inline int csio_is_t4(uint16_t chip) | ||
85 | { | ||
86 | return (chip == CSIO_HW_T4); | ||
87 | } | ||
88 | |||
89 | static inline int csio_is_t5(uint16_t chip) | 67 | static inline int csio_is_t5(uint16_t chip) |
90 | { | 68 | { |
91 | return (chip == CSIO_HW_T5); | 69 | return (chip == CSIO_HW_T5); |
@@ -95,21 +73,6 @@ static inline int csio_is_t5(uint16_t chip) | |||
95 | #define CSIO_DEVICE(devid, idx) \ | 73 | #define CSIO_DEVICE(devid, idx) \ |
96 | { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) } | 74 | { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) } |
97 | 75 | ||
98 | #define CSIO_HW_PIDX(hw, index) \ | ||
99 | (csio_is_t4(hw->chip_id) ? (PIDX_V(index)) : \ | ||
100 | (PIDX_T5_G(index) | DBTYPE_F)) | ||
101 | |||
102 | #define CSIO_HW_LP_INT_THRESH(hw, val) \ | ||
103 | (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \ | ||
104 | (LP_INT_THRESH_T5_V(val))) | ||
105 | |||
106 | #define CSIO_HW_M_LP_INT_THRESH(hw) \ | ||
107 | (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M)) | ||
108 | |||
109 | #define CSIO_MAC_INT_CAUSE_REG(hw, port) \ | ||
110 | (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE_A)) : \ | ||
111 | (T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A))) | ||
112 | |||
113 | #include "t4fw_api.h" | 76 | #include "t4fw_api.h" |
114 | 77 | ||
115 | #define FW_VERSION(chip) ( \ | 78 | #define FW_VERSION(chip) ( \ |
@@ -125,11 +88,6 @@ struct fw_info { | |||
125 | char *fw_mod_name; | 88 | char *fw_mod_name; |
126 | struct fw_hdr fw_hdr; | 89 | struct fw_hdr fw_hdr; |
127 | }; | 90 | }; |
128 | #define CSIO_FW_FNAME(hw) \ | ||
129 | (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5) | ||
130 | |||
131 | #define CSIO_CF_FNAME(hw) \ | ||
132 | (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5) | ||
133 | 91 | ||
134 | /* Declare ENUMS */ | 92 | /* Declare ENUMS */ |
135 | enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; | 93 | enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; |
@@ -163,7 +121,6 @@ struct csio_hw_chip_ops { | |||
163 | void (*chip_dfs_create_ext_mem)(struct csio_hw *); | 121 | void (*chip_dfs_create_ext_mem)(struct csio_hw *); |
164 | }; | 122 | }; |
165 | 123 | ||
166 | extern struct csio_hw_chip_ops t4_ops; | ||
167 | extern struct csio_hw_chip_ops t5_ops; | 124 | extern struct csio_hw_chip_ops t5_ops; |
168 | 125 | ||
169 | #endif /* #ifndef __CSIO_HW_CHIP_H__ */ | 126 | #endif /* #ifndef __CSIO_HW_CHIP_H__ */ |
diff --git a/drivers/scsi/csiostor/csio_init.c b/drivers/scsi/csiostor/csio_init.c index 34d20cc3e110..9b9794d42ffe 100644 --- a/drivers/scsi/csiostor/csio_init.c +++ b/drivers/scsi/csiostor/csio_init.c | |||
@@ -1176,9 +1176,8 @@ static struct pci_error_handlers csio_err_handler = { | |||
1176 | */ | 1176 | */ |
1177 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ | 1177 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ |
1178 | static struct pci_device_id csio_pci_tbl[] = { | 1178 | static struct pci_device_id csio_pci_tbl[] = { |
1179 | /* Define for iSCSI uses PF5, FCoE uses PF6 */ | 1179 | /* Define for FCoE uses PF6 */ |
1180 | #define CH_PCI_DEVICE_ID_FUNCTION 0x5 | 1180 | #define CH_PCI_DEVICE_ID_FUNCTION 0x6 |
1181 | #define CH_PCI_DEVICE_ID_FUNCTION2 0x6 | ||
1182 | 1181 | ||
1183 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ | 1182 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ |
1184 | { PCI_VDEVICE(CHELSIO, (devid)), 0 } | 1183 | { PCI_VDEVICE(CHELSIO, (devid)), 0 } |
@@ -1256,5 +1255,4 @@ MODULE_DESCRIPTION(CSIO_DRV_DESC); | |||
1256 | MODULE_LICENSE(CSIO_DRV_LICENSE); | 1255 | MODULE_LICENSE(CSIO_DRV_LICENSE); |
1257 | MODULE_DEVICE_TABLE(pci, csio_pci_tbl); | 1256 | MODULE_DEVICE_TABLE(pci, csio_pci_tbl); |
1258 | MODULE_VERSION(CSIO_DRV_VERSION); | 1257 | MODULE_VERSION(CSIO_DRV_VERSION); |
1259 | MODULE_FIRMWARE(FW_FNAME_T4); | ||
1260 | MODULE_FIRMWARE(FW_FNAME_T5); | 1258 | MODULE_FIRMWARE(FW_FNAME_T5); |
diff --git a/drivers/scsi/csiostor/csio_wr.c b/drivers/scsi/csiostor/csio_wr.c index b47ea336e912..e8f18174f2e9 100644 --- a/drivers/scsi/csiostor/csio_wr.c +++ b/drivers/scsi/csiostor/csio_wr.c | |||
@@ -85,7 +85,7 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq) | |||
85 | */ | 85 | */ |
86 | if (flq->inc_idx >= 8) { | 86 | if (flq->inc_idx >= 8) { |
87 | csio_wr_reg32(hw, DBPRIO_F | QID_V(flq->un.fl.flid) | | 87 | csio_wr_reg32(hw, DBPRIO_F | QID_V(flq->un.fl.flid) | |
88 | CSIO_HW_PIDX(hw, flq->inc_idx / 8), | 88 | PIDX_T5_V(flq->inc_idx / 8) | DBTYPE_F, |
89 | MYPF_REG(SGE_PF_KDOORBELL_A)); | 89 | MYPF_REG(SGE_PF_KDOORBELL_A)); |
90 | flq->inc_idx &= 7; | 90 | flq->inc_idx &= 7; |
91 | } | 91 | } |
@@ -983,7 +983,7 @@ csio_wr_issue(struct csio_hw *hw, int qidx, bool prio) | |||
983 | wmb(); | 983 | wmb(); |
984 | /* Ring SGE Doorbell writing q->pidx into it */ | 984 | /* Ring SGE Doorbell writing q->pidx into it */ |
985 | csio_wr_reg32(hw, DBPRIO_V(prio) | QID_V(q->un.eq.physeqid) | | 985 | csio_wr_reg32(hw, DBPRIO_V(prio) | QID_V(q->un.eq.physeqid) | |
986 | CSIO_HW_PIDX(hw, q->inc_idx), | 986 | PIDX_T5_V(q->inc_idx) | DBTYPE_F, |
987 | MYPF_REG(SGE_PF_KDOORBELL_A)); | 987 | MYPF_REG(SGE_PF_KDOORBELL_A)); |
988 | q->inc_idx = 0; | 988 | q->inc_idx = 0; |
989 | 989 | ||
@@ -1467,12 +1467,11 @@ csio_wr_set_sge(struct csio_hw *hw) | |||
1467 | * and generate an interrupt when this occurs so we can recover. | 1467 | * and generate an interrupt when this occurs so we can recover. |
1468 | */ | 1468 | */ |
1469 | csio_set_reg_field(hw, SGE_DBFIFO_STATUS_A, | 1469 | csio_set_reg_field(hw, SGE_DBFIFO_STATUS_A, |
1470 | HP_INT_THRESH_V(HP_INT_THRESH_M) | | 1470 | LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M), |
1471 | CSIO_HW_LP_INT_THRESH(hw, | 1471 | LP_INT_THRESH_T5_V(CSIO_SGE_DBFIFO_INT_THRESH)); |
1472 | CSIO_HW_M_LP_INT_THRESH(hw)), | 1472 | csio_set_reg_field(hw, SGE_DBFIFO_STATUS2_A, |
1473 | HP_INT_THRESH_V(CSIO_SGE_DBFIFO_INT_THRESH) | | 1473 | HP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M), |
1474 | CSIO_HW_LP_INT_THRESH(hw, | 1474 | HP_INT_THRESH_T5_V(CSIO_SGE_DBFIFO_INT_THRESH)); |
1475 | CSIO_SGE_DBFIFO_INT_THRESH)); | ||
1476 | 1475 | ||
1477 | csio_set_reg_field(hw, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F, | 1476 | csio_set_reg_field(hw, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F, |
1478 | ENABLE_DROP_F); | 1477 | ENABLE_DROP_F); |