1 files changed, 75 insertions, 75 deletions

diff --git a/drivers/scsi/csiostor/csio_hw_t5.c b/drivers/scsi/csiostor/csio_hw_t5.c
index 66e180a58718..3267f4f627c9 100644
--- a/drivers/scsi/csiostor/csio_hw_t5.c
+++ b/drivers/scsi/csiostor/csio_hw_t5.c
@@ -56,11 +56,11 @@ csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
          * back MA register to ensure that changes propagate before we attempt
          * to use the new values.)
          */
-        csio_wr_reg32(hw, mem_win_base | BIR(0) |
-                          WINDOW(ilog2(MEMWIN_APERTURE) - 10),
-                          PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
+        csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
+                          WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
+                          PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
         csio_rd_reg32(hw,
-                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
+                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
 
         return 0;
 }
@@ -72,74 +72,74 @@ static void
 csio_t5_pcie_intr_handler(struct csio_hw *hw)
 {
         static struct intr_info sysbus_intr_info[] = {
-                { RNPP, "RXNP array parity error", -1, 1 },
-                { RPCP, "RXPC array parity error", -1, 1 },
-                { RCIP, "RXCIF array parity error", -1, 1 },
-                { RCCP, "Rx completions control array parity error", -1, 1 },
-                { RFTP, "RXFT array parity error", -1, 1 },
+                { RNPP_F, "RXNP array parity error", -1, 1 },
+                { RPCP_F, "RXPC array parity error", -1, 1 },
+                { RCIP_F, "RXCIF array parity error", -1, 1 },
+                { RCCP_F, "Rx completions control array parity error", -1, 1 },
+                { RFTP_F, "RXFT array parity error", -1, 1 },
                 { 0, NULL, 0, 0 }
         };
         static struct intr_info pcie_port_intr_info[] = {
-                { TPCP, "TXPC array parity error", -1, 1 },
-                { TNPP, "TXNP array parity error", -1, 1 },
-                { TFTP, "TXFT array parity error", -1, 1 },
-                { TCAP, "TXCA array parity error", -1, 1 },
-                { TCIP, "TXCIF array parity error", -1, 1 },
-                { RCAP, "RXCA array parity error", -1, 1 },
-                { OTDD, "outbound request TLP discarded", -1, 1 },
-                { RDPE, "Rx data parity error", -1, 1 },
-                { TDUE, "Tx uncorrectable data error", -1, 1 },
+                { TPCP_F, "TXPC array parity error", -1, 1 },
+                { TNPP_F, "TXNP array parity error", -1, 1 },
+                { TFTP_F, "TXFT array parity error", -1, 1 },
+                { TCAP_F, "TXCA array parity error", -1, 1 },
+                { TCIP_F, "TXCIF array parity error", -1, 1 },
+                { RCAP_F, "RXCA array parity error", -1, 1 },
+                { OTDD_F, "outbound request TLP discarded", -1, 1 },
+                { RDPE_F, "Rx data parity error", -1, 1 },
+                { TDUE_F, "Tx uncorrectable data error", -1, 1 },
                 { 0, NULL, 0, 0 }
         };
 
         static struct intr_info pcie_intr_info[] = {
-                { MSTGRPPERR, "Master Response Read Queue parity error",
+                { MSTGRPPERR_F, "Master Response Read Queue parity error",
                 -1, 1 },
-                { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
-                { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
-                { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
-                { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
-                { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
-                { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
-                { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
+                { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
+                { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
+                { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
+                { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
+                { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
+                { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
+                { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
                 -1, 1 },
-                { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
+                { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
                 -1, 1 },
-                { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
-                { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
-                { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
-                { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
-                { DREQWRPERR, "PCI DMA channel write request parity error",
+                { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
+                { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
+                { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
+                { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
+                { DREQWRPERR_F, "PCI DMA channel write request parity error",
                 -1, 1 },
-                { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
-                { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
-                { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
-                { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
-                { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
-                { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
-                { FIDPERR, "PCI FID parity error", -1, 1 },
-                { VFIDPERR, "PCI INTx clear parity error", -1, 1 },
-                { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
-                { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
-                { IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
+                { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
+                { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
+                { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
+                { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
+                { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
+                { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
+                { FIDPERR_F, "PCI FID parity error", -1, 1 },
+                { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
+                { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
+                { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
+                { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
                 -1, 1 },
-                { IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
+                { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
                 -1, 1 },
-                { RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
-                { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
-                { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
-                { READRSPERR, "Outbound read error", -1, 0 },
+                { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
+                { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
+                { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
+                { READRSPERR_F, "Outbound read error", -1, 0 },
                 { 0, NULL, 0, 0 }
         };
 
         int fat;
         fat = csio_handle_intr_status(hw,
-                                      PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
+                                      PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
                                       sysbus_intr_info) +
               csio_handle_intr_status(hw,
-                                      PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
+                                      PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
                                       pcie_port_intr_info) +
-              csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
+              csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
         if (fat)
                 csio_hw_fatal_err(hw);
 }
@@ -177,25 +177,25 @@ csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
         uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
         uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
 
-        mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD, idx);
-        mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR, idx);
-        mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN, idx);
-        mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
-        mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
+        mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx);
+        mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
+        mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
+        mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx);
+        mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
 
-        if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST)
+        if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
                 return -EBUSY;
         csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
         csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
         csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
-        csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST |  BIST_CMD_GAP(1),
+        csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F |  BIST_CMD_GAP_V(1),
                       mc_bist_cmd_reg);
-        i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST,
+        i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,
                                      0, 10, 1, NULL);
         if (i)
                 return i;
 
-#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
+#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
 
         for (i = 15; i >= 0; i--)
                 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
@@ -231,27 +231,27 @@ csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
 
-        edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD, idx);
-        edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
-        edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
-        edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
-        edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
+        edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
+        edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
+        edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
+        edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
+        edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx);
 #undef EDC_REG_T5
 #undef EDC_STRIDE_T5
 
-        if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST)
+        if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
                 return -EBUSY;
         csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
         csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
         csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
-        csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST |  BIST_CMD_GAP(1),
+        csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F |  BIST_CMD_GAP_V(1),
                       edc_bist_cmd_reg);
-        i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST,
+        i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,
                                      0, 10, 1, NULL);
         if (i)
                 return i;
 
-#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
+#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
 
         for (i = 15; i >= 0; i--)
                 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
@@ -320,13 +320,13 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
          * the address is relative to BAR0.
          */
         mem_reg = csio_rd_reg32(hw,
-                        PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
-        mem_aperture = 1 << (WINDOW(mem_reg) + 10);
-        mem_base = GET_PCIEOFST(mem_reg) << 10;
+                        PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
+        mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
+        mem_base = PCIEOFST_G(mem_reg) << 10;
 
         start = addr & ~(mem_aperture-1);
         offset = addr - start;
-        win_pf = V_PFNUM(hw->pfn);
+        win_pf = PFNUM_V(hw->pfn);
 
         csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
                  mem_reg, mem_aperture);
@@ -344,9 +344,9 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
                  * before we attempt to use the new value.
                  */
                 csio_wr_reg32(hw, pos | win_pf,
-                        PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
+                        PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
                 csio_rd_reg32(hw,
-                        PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
+                        PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 
                 while (offset < mem_aperture && len > 0) {
                         if (dir)