diff options
Diffstat (limited to 'drivers/scsi/bfa/bfa_ioc_ct.c')
| -rw-r--r-- | drivers/scsi/bfa/bfa_ioc_ct.c | 137 |
1 files changed, 55 insertions, 82 deletions
diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c index 68f027da001e..f21b82c5f64c 100644 --- a/drivers/scsi/bfa/bfa_ioc_ct.c +++ b/drivers/scsi/bfa/bfa_ioc_ct.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. | 2 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. |
| 3 | * All rights reserved | 3 | * All rights reserved |
| 4 | * www.brocade.com | 4 | * www.brocade.com |
| 5 | * | 5 | * |
| @@ -15,22 +15,15 @@ | |||
| 15 | * General Public License for more details. | 15 | * General Public License for more details. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <bfa.h> | 18 | #include "bfa_ioc.h" |
| 19 | #include <bfa_ioc.h> | 19 | #include "bfi_ctreg.h" |
| 20 | #include <bfa_fwimg_priv.h> | 20 | #include "bfa_defs.h" |
| 21 | #include <cna/bfa_cna_trcmod.h> | ||
| 22 | #include <cs/bfa_debug.h> | ||
| 23 | #include <bfi/bfi_ioc.h> | ||
| 24 | #include <bfi/bfi_ctreg.h> | ||
| 25 | #include <log/bfa_log_hal.h> | ||
| 26 | #include <defs/bfa_defs_pci.h> | ||
| 27 | 21 | ||
| 28 | BFA_TRC_FILE(CNA, IOC_CT); | 22 | BFA_TRC_FILE(CNA, IOC_CT); |
| 29 | 23 | ||
| 30 | /* | 24 | /* |
| 31 | * forward declarations | 25 | * forward declarations |
| 32 | */ | 26 | */ |
| 33 | static bfa_status_t bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc); | ||
| 34 | static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc); | 27 | static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc); |
| 35 | static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc); | 28 | static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc); |
| 36 | static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc); | 29 | static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc); |
| @@ -78,7 +71,8 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc) | |||
| 78 | /** | 71 | /** |
| 79 | * If bios boot (flash based) -- do not increment usage count | 72 | * If bios boot (flash based) -- do not increment usage count |
| 80 | */ | 73 | */ |
| 81 | if (bfi_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < BFA_IOC_FWIMG_MINSZ) | 74 | if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < |
| 75 | BFA_IOC_FWIMG_MINSZ) | ||
| 82 | return BFA_TRUE; | 76 | return BFA_TRUE; |
| 83 | 77 | ||
| 84 | bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); | 78 | bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); |
| @@ -136,7 +130,8 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc) | |||
| 136 | /** | 130 | /** |
| 137 | * If bios boot (flash based) -- do not decrement usage count | 131 | * If bios boot (flash based) -- do not decrement usage count |
| 138 | */ | 132 | */ |
| 139 | if (bfi_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < BFA_IOC_FWIMG_MINSZ) | 133 | if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < |
| 134 | BFA_IOC_FWIMG_MINSZ) | ||
| 140 | return; | 135 | return; |
| 141 | 136 | ||
| 142 | /** | 137 | /** |
| @@ -308,16 +303,47 @@ bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) | |||
| 308 | bfa_reg_write(rb + FNC_PERS_REG, r32); | 303 | bfa_reg_write(rb + FNC_PERS_REG, r32); |
| 309 | } | 304 | } |
| 310 | 305 | ||
| 311 | static bfa_status_t | 306 | /** |
| 312 | bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) | 307 | * Cleanup hw semaphore and usecnt registers |
| 308 | */ | ||
| 309 | static void | ||
| 310 | bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc) | ||
| 313 | { | 311 | { |
| 314 | bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; | 312 | |
| 315 | u32 pll_sclk, pll_fclk, r32; | 313 | if (ioc->cna) { |
| 314 | bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); | ||
| 315 | bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0); | ||
| 316 | bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); | ||
| 317 | } | ||
| 316 | 318 | ||
| 317 | /* | 319 | /* |
| 318 | * Hold semaphore so that nobody can access the chip during init. | 320 | * Read the hw sem reg to make sure that it is locked |
| 321 | * before we clear it. If it is not locked, writing 1 | ||
| 322 | * will lock it instead of clearing it. | ||
| 319 | */ | 323 | */ |
| 320 | bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg); | 324 | bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); |
| 325 | bfa_ioc_hw_sem_release(ioc); | ||
| 326 | } | ||
| 327 | |||
| 328 | |||
| 329 | |||
| 330 | /* | ||
| 331 | * Check the firmware state to know if pll_init has been completed already | ||
| 332 | */ | ||
| 333 | bfa_boolean_t | ||
| 334 | bfa_ioc_ct_pll_init_complete(bfa_os_addr_t rb) | ||
| 335 | { | ||
| 336 | if ((bfa_reg_read(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) || | ||
| 337 | (bfa_reg_read(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP)) | ||
| 338 | return BFA_TRUE; | ||
| 339 | |||
| 340 | return BFA_FALSE; | ||
| 341 | } | ||
| 342 | |||
| 343 | bfa_status_t | ||
| 344 | bfa_ioc_ct_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode) | ||
| 345 | { | ||
| 346 | u32 pll_sclk, pll_fclk, r32; | ||
| 321 | 347 | ||
| 322 | pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST | | 348 | pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST | |
| 323 | __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) | | 349 | __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) | |
| @@ -327,70 +353,50 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) | |||
| 327 | __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) | | 353 | __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) | |
| 328 | __APP_PLL_425_JITLMT0_1(3U) | | 354 | __APP_PLL_425_JITLMT0_1(3U) | |
| 329 | __APP_PLL_425_CNTLMT0_1(1U); | 355 | __APP_PLL_425_CNTLMT0_1(1U); |
| 330 | 356 | if (fcmode) { | |
| 331 | /** | ||
| 332 | * For catapult, choose operational mode FC/FCoE | ||
| 333 | */ | ||
| 334 | if (ioc->fcmode) { | ||
| 335 | bfa_reg_write((rb + OP_MODE), 0); | 357 | bfa_reg_write((rb + OP_MODE), 0); |
| 336 | bfa_reg_write((rb + ETH_MAC_SER_REG), | 358 | bfa_reg_write((rb + ETH_MAC_SER_REG), |
| 337 | __APP_EMS_CMLCKSEL | | 359 | __APP_EMS_CMLCKSEL | |
| 338 | __APP_EMS_REFCKBUFEN2 | | 360 | __APP_EMS_REFCKBUFEN2 | |
| 339 | __APP_EMS_CHANNEL_SEL); | 361 | __APP_EMS_CHANNEL_SEL); |
| 340 | } else { | 362 | } else { |
| 341 | ioc->pllinit = BFA_TRUE; | ||
| 342 | bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE); | 363 | bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE); |
| 343 | bfa_reg_write((rb + ETH_MAC_SER_REG), | 364 | bfa_reg_write((rb + ETH_MAC_SER_REG), |
| 344 | __APP_EMS_REFCKBUFEN1); | 365 | __APP_EMS_REFCKBUFEN1); |
| 345 | } | 366 | } |
| 346 | |||
| 347 | bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); | 367 | bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); |
| 348 | bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); | 368 | bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); |
| 349 | |||
| 350 | bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); | 369 | bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); |
| 351 | bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); | 370 | bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); |
| 352 | bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); | 371 | bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); |
| 353 | bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); | 372 | bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); |
| 354 | bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); | 373 | bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); |
| 355 | bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); | 374 | bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); |
| 356 | 375 | bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk | | |
| 357 | bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk | | ||
| 358 | __APP_PLL_312_LOGIC_SOFT_RESET); | 376 | __APP_PLL_312_LOGIC_SOFT_RESET); |
| 359 | bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk | | 377 | bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk | |
| 360 | __APP_PLL_425_LOGIC_SOFT_RESET); | 378 | __APP_PLL_425_LOGIC_SOFT_RESET); |
| 361 | bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk | | 379 | bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk | |
| 362 | __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE); | 380 | __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE); |
| 363 | bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk | | 381 | bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk | |
| 364 | __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE); | 382 | __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE); |
| 365 | |||
| 366 | /** | ||
| 367 | * Wait for PLLs to lock. | ||
| 368 | */ | ||
| 369 | bfa_reg_read(rb + HOSTFN0_INT_MSK); | 383 | bfa_reg_read(rb + HOSTFN0_INT_MSK); |
| 370 | bfa_os_udelay(2000); | 384 | bfa_os_udelay(2000); |
| 371 | bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); | 385 | bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); |
| 372 | bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); | 386 | bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); |
| 373 | 387 | bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk | | |
| 374 | bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk | | ||
| 375 | __APP_PLL_312_ENABLE); | 388 | __APP_PLL_312_ENABLE); |
| 376 | bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk | | 389 | bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk | |
| 377 | __APP_PLL_425_ENABLE); | 390 | __APP_PLL_425_ENABLE); |
| 378 | 391 | if (!fcmode) { | |
| 379 | /** | ||
| 380 | * PSS memory reset is asserted at power-on-reset. Need to clear | ||
| 381 | * this before running EDRAM BISTR | ||
| 382 | */ | ||
| 383 | if (ioc->cna) { | ||
| 384 | bfa_reg_write((rb + PMM_1T_RESET_REG_P0), __PMM_1T_RESET_P); | 392 | bfa_reg_write((rb + PMM_1T_RESET_REG_P0), __PMM_1T_RESET_P); |
| 385 | bfa_reg_write((rb + PMM_1T_RESET_REG_P1), __PMM_1T_RESET_P); | 393 | bfa_reg_write((rb + PMM_1T_RESET_REG_P1), __PMM_1T_RESET_P); |
| 386 | } | 394 | } |
| 387 | |||
| 388 | r32 = bfa_reg_read((rb + PSS_CTL_REG)); | 395 | r32 = bfa_reg_read((rb + PSS_CTL_REG)); |
| 389 | r32 &= ~__PSS_LMEM_RESET; | 396 | r32 &= ~__PSS_LMEM_RESET; |
| 390 | bfa_reg_write((rb + PSS_CTL_REG), r32); | 397 | bfa_reg_write((rb + PSS_CTL_REG), r32); |
| 391 | bfa_os_udelay(1000); | 398 | bfa_os_udelay(1000); |
| 392 | 399 | if (!fcmode) { | |
| 393 | if (ioc->cna) { | ||
| 394 | bfa_reg_write((rb + PMM_1T_RESET_REG_P0), 0); | 400 | bfa_reg_write((rb + PMM_1T_RESET_REG_P0), 0); |
| 395 | bfa_reg_write((rb + PMM_1T_RESET_REG_P1), 0); | 401 | bfa_reg_write((rb + PMM_1T_RESET_REG_P1), 0); |
| 396 | } | 402 | } |
| @@ -398,39 +404,6 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) | |||
| 398 | bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START); | 404 | bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START); |
| 399 | bfa_os_udelay(1000); | 405 | bfa_os_udelay(1000); |
| 400 | r32 = bfa_reg_read((rb + MBIST_STAT_REG)); | 406 | r32 = bfa_reg_read((rb + MBIST_STAT_REG)); |
| 401 | bfa_trc(ioc, r32); | ||
| 402 | |||
| 403 | /** | ||
| 404 | * Clear BISTR | ||
| 405 | */ | ||
| 406 | bfa_reg_write((rb + MBIST_CTL_REG), 0); | 407 | bfa_reg_write((rb + MBIST_CTL_REG), 0); |
| 407 | |||
| 408 | /* | ||
| 409 | * release semaphore. | ||
| 410 | */ | ||
| 411 | bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg); | ||
| 412 | |||
| 413 | return BFA_STATUS_OK; | 408 | return BFA_STATUS_OK; |
| 414 | } | 409 | } |
| 415 | |||
| 416 | /** | ||
| 417 | * Cleanup hw semaphore and usecnt registers | ||
| 418 | */ | ||
| 419 | static void | ||
| 420 | bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc) | ||
| 421 | { | ||
| 422 | |||
| 423 | if (ioc->cna) { | ||
| 424 | bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); | ||
| 425 | bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0); | ||
| 426 | bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); | ||
| 427 | } | ||
| 428 | |||
| 429 | /* | ||
| 430 | * Read the hw sem reg to make sure that it is locked | ||
| 431 | * before we clear it. If it is not locked, writing 1 | ||
| 432 | * will lock it instead of clearing it. | ||
| 433 | */ | ||
| 434 | bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); | ||
| 435 | bfa_ioc_hw_sem_release(ioc); | ||
| 436 | } | ||
