diff options
Diffstat (limited to 'drivers/scsi/bfa/bfa_ioc_cb.c')
-rw-r--r-- | drivers/scsi/bfa/bfa_ioc_cb.c | 69 |
1 files changed, 27 insertions, 42 deletions
diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c index 89ae4c8f95a2..30df8a284715 100644 --- a/drivers/scsi/bfa/bfa_ioc_cb.c +++ b/drivers/scsi/bfa/bfa_ioc_cb.c | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | #include "bfad_drv.h" | 18 | #include "bfad_drv.h" |
19 | #include "bfa_ioc.h" | 19 | #include "bfa_ioc.h" |
20 | #include "bfi_cbreg.h" | 20 | #include "bfi_reg.h" |
21 | #include "bfa_defs.h" | 21 | #include "bfa_defs.h" |
22 | 22 | ||
23 | BFA_TRC_FILE(CNA, IOC_CB); | 23 | BFA_TRC_FILE(CNA, IOC_CB); |
@@ -69,21 +69,6 @@ bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc) | |||
69 | static bfa_boolean_t | 69 | static bfa_boolean_t |
70 | bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) | 70 | bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) |
71 | { | 71 | { |
72 | struct bfi_ioc_image_hdr_s fwhdr; | ||
73 | uint32_t fwstate = readl(ioc->ioc_regs.ioc_fwstate); | ||
74 | |||
75 | if (fwstate == BFI_IOC_UNINIT) | ||
76 | return BFA_TRUE; | ||
77 | |||
78 | bfa_ioc_fwver_get(ioc, &fwhdr); | ||
79 | |||
80 | if (swab32(fwhdr.exec) == BFI_BOOT_TYPE_NORMAL) | ||
81 | return BFA_TRUE; | ||
82 | |||
83 | bfa_trc(ioc, fwstate); | ||
84 | bfa_trc(ioc, fwhdr.exec); | ||
85 | writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); | ||
86 | |||
87 | return BFA_TRUE; | 72 | return BFA_TRUE; |
88 | } | 73 | } |
89 | 74 | ||
@@ -98,7 +83,7 @@ bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc) | |||
98 | static void | 83 | static void |
99 | bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) | 84 | bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) |
100 | { | 85 | { |
101 | writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set); | 86 | writel(~0U, ioc->ioc_regs.err_set); |
102 | readl(ioc->ioc_regs.err_set); | 87 | readl(ioc->ioc_regs.err_set); |
103 | } | 88 | } |
104 | 89 | ||
@@ -152,8 +137,8 @@ bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) | |||
152 | */ | 137 | */ |
153 | ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); | 138 | ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); |
154 | ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); | 139 | ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); |
155 | ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG); | 140 | ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG); |
156 | ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG); | 141 | ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG); |
157 | 142 | ||
158 | /* | 143 | /* |
159 | * IOC semaphore registers and serialization | 144 | * IOC semaphore registers and serialization |
@@ -285,18 +270,18 @@ bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc) | |||
285 | } | 270 | } |
286 | 271 | ||
287 | bfa_status_t | 272 | bfa_status_t |
288 | bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode) | 273 | bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode) |
289 | { | 274 | { |
290 | u32 pll_sclk, pll_fclk; | 275 | u32 pll_sclk, pll_fclk; |
291 | 276 | ||
292 | pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN | | 277 | pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN | |
293 | __APP_PLL_212_P0_1(3U) | | 278 | __APP_PLL_SCLK_P0_1(3U) | |
294 | __APP_PLL_212_JITLMT0_1(3U) | | 279 | __APP_PLL_SCLK_JITLMT0_1(3U) | |
295 | __APP_PLL_212_CNTLMT0_1(3U); | 280 | __APP_PLL_SCLK_CNTLMT0_1(3U); |
296 | pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN | | 281 | pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN | |
297 | __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) | | 282 | __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) | |
298 | __APP_PLL_400_JITLMT0_1(3U) | | 283 | __APP_PLL_LCLK_JITLMT0_1(3U) | |
299 | __APP_PLL_400_CNTLMT0_1(3U); | 284 | __APP_PLL_LCLK_CNTLMT0_1(3U); |
300 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); | 285 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); |
301 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); | 286 | writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); |
302 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); | 287 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); |
@@ -305,24 +290,24 @@ bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode) | |||
305 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); | 290 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); |
306 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); | 291 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); |
307 | writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); | 292 | writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); |
308 | writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); | 293 | writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); |
309 | writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET, | 294 | writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET, |
310 | rb + APP_PLL_212_CTL_REG); | 295 | rb + APP_PLL_SCLK_CTL_REG); |
311 | writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); | 296 | writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); |
312 | writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET, | 297 | writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET, |
313 | rb + APP_PLL_400_CTL_REG); | 298 | rb + APP_PLL_LCLK_CTL_REG); |
314 | udelay(2); | 299 | udelay(2); |
315 | writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); | 300 | writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); |
316 | writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); | 301 | writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); |
317 | writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET, | 302 | writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET, |
318 | rb + APP_PLL_212_CTL_REG); | 303 | rb + APP_PLL_SCLK_CTL_REG); |
319 | writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET, | 304 | writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET, |
320 | rb + APP_PLL_400_CTL_REG); | 305 | rb + APP_PLL_LCLK_CTL_REG); |
321 | udelay(2000); | 306 | udelay(2000); |
322 | writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); | 307 | writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); |
323 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); | 308 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); |
324 | writel(pll_sclk, (rb + APP_PLL_212_CTL_REG)); | 309 | writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG)); |
325 | writel(pll_fclk, (rb + APP_PLL_400_CTL_REG)); | 310 | writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG)); |
326 | 311 | ||
327 | return BFA_STATUS_OK; | 312 | return BFA_STATUS_OK; |
328 | } | 313 | } |