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path: root/drivers/scsi/be2iscsi/be_cmds.c
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Diffstat (limited to 'drivers/scsi/be2iscsi/be_cmds.c')
-rw-r--r--drivers/scsi/be2iscsi/be_cmds.c263
1 files changed, 234 insertions, 29 deletions
diff --git a/drivers/scsi/be2iscsi/be_cmds.c b/drivers/scsi/be2iscsi/be_cmds.c
index 08007b6e42df..10f8fe7a38d2 100644
--- a/drivers/scsi/be2iscsi/be_cmds.c
+++ b/drivers/scsi/be2iscsi/be_cmds.c
@@ -19,6 +19,16 @@
19#include "be_mgmt.h" 19#include "be_mgmt.h"
20#include "be_main.h" 20#include "be_main.h"
21 21
22static void be_mcc_notify(struct beiscsi_hba *phba)
23{
24 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
25 u32 val = 0;
26
27 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
28 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
29 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
30}
31
22static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 32static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
23{ 33{
24 if (compl->flags != 0) { 34 if (compl->flags != 0) {
@@ -54,13 +64,56 @@ static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
54 return 0; 64 return 0;
55} 65}
56 66
67
57static inline bool is_link_state_evt(u32 trailer) 68static inline bool is_link_state_evt(u32 trailer)
58{ 69{
59 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 70 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
60 ASYNC_TRAILER_EVENT_CODE_MASK) == ASYNC_EVENT_CODE_LINK_STATE); 71 ASYNC_TRAILER_EVENT_CODE_MASK) ==
72 ASYNC_EVENT_CODE_LINK_STATE);
73}
74
75static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
76{
77 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
78 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
79
80 if (be_mcc_compl_is_new(compl)) {
81 queue_tail_inc(mcc_cq);
82 return compl;
83 }
84 return NULL;
85}
86
87static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
88{
89 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
90}
91
92static void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
93 struct be_async_event_link_state *evt)
94{
95 switch (evt->port_link_status) {
96 case ASYNC_EVENT_LINK_DOWN:
97 SE_DEBUG(DBG_LVL_1, "Link Down on Physical Port %d \n",
98 evt->physical_port);
99 phba->state |= BE_ADAPTER_LINK_DOWN;
100 break;
101 case ASYNC_EVENT_LINK_UP:
102 phba->state = BE_ADAPTER_UP;
103 SE_DEBUG(DBG_LVL_1, "Link UP on Physical Port %d \n",
104 evt->physical_port);
105 iscsi_host_for_each_session(phba->shost,
106 be2iscsi_fail_session);
107 break;
108 default:
109 SE_DEBUG(DBG_LVL_1, "Unexpected Async Notification %d on"
110 "Physical Port %d \n",
111 evt->port_link_status,
112 evt->physical_port);
113 }
61} 114}
62 115
63void beiscsi_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm, 116static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm,
64 u16 num_popped) 117 u16 num_popped)
65{ 118{
66 u32 val = 0; 119 u32 val = 0;
@@ -68,7 +121,66 @@ void beiscsi_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm,
68 if (arm) 121 if (arm)
69 val |= 1 << DB_CQ_REARM_SHIFT; 122 val |= 1 << DB_CQ_REARM_SHIFT;
70 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; 123 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
71 iowrite32(val, ctrl->db + DB_CQ_OFFSET); 124 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
125}
126
127
128int be_process_mcc(struct beiscsi_hba *phba)
129{
130 struct be_mcc_compl *compl;
131 int num = 0, status = 0;
132 struct be_ctrl_info *ctrl = &phba->ctrl;
133
134 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
135 while ((compl = be_mcc_compl_get(phba))) {
136 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
137 /* Interpret flags as an async trailer */
138 BUG_ON(!is_link_state_evt(compl->flags));
139
140 /* Interpret compl as a async link evt */
141 beiscsi_async_link_state_process(phba,
142 (struct be_async_event_link_state *) compl);
143 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
144 status = be_mcc_compl_process(ctrl, compl);
145 atomic_dec(&phba->ctrl.mcc_obj.q.used);
146 }
147 be_mcc_compl_use(compl);
148 num++;
149 }
150
151 if (num)
152 beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num);
153
154 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
155 return status;
156}
157
158/* Wait till no more pending mcc requests are present */
159static int be_mcc_wait_compl(struct beiscsi_hba *phba)
160{
161#define mcc_timeout 120000 /* 5s timeout */
162 int i, status;
163 for (i = 0; i < mcc_timeout; i++) {
164 status = be_process_mcc(phba);
165 if (status)
166 return status;
167
168 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
169 break;
170 udelay(100);
171 }
172 if (i == mcc_timeout) {
173 dev_err(&phba->pcidev->dev, "mccq poll timed out\n");
174 return -1;
175 }
176 return 0;
177}
178
179/* Notify MCC requests and wait for completion */
180int be_mcc_notify_wait(struct beiscsi_hba *phba)
181{
182 be_mcc_notify(phba);
183 return be_mcc_wait_compl(phba);
72} 184}
73 185
74static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl) 186static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
@@ -142,6 +254,52 @@ int be_mbox_notify(struct be_ctrl_info *ctrl)
142 return 0; 254 return 0;
143} 255}
144 256
257/*
258 * Insert the mailbox address into the doorbell in two steps
259 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
260 */
261static int be_mbox_notify_wait(struct beiscsi_hba *phba)
262{
263 int status;
264 u32 val = 0;
265 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
266 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
267 struct be_mcc_mailbox *mbox = mbox_mem->va;
268 struct be_mcc_compl *compl = &mbox->compl;
269 struct be_ctrl_info *ctrl = &phba->ctrl;
270
271 val |= MPU_MAILBOX_DB_HI_MASK;
272 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
273 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
274 iowrite32(val, db);
275
276 /* wait for ready to be set */
277 status = be_mbox_db_ready_wait(ctrl);
278 if (status != 0)
279 return status;
280
281 val = 0;
282 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
283 val |= (u32)(mbox_mem->dma >> 4) << 2;
284 iowrite32(val, db);
285
286 status = be_mbox_db_ready_wait(ctrl);
287 if (status != 0)
288 return status;
289
290 /* A cq entry has been made now */
291 if (be_mcc_compl_is_new(compl)) {
292 status = be_mcc_compl_process(ctrl, &mbox->compl);
293 be_mcc_compl_use(compl);
294 if (status)
295 return status;
296 } else {
297 dev_err(&phba->pcidev->dev, "invalid mailbox completion\n");
298 return -1;
299 }
300 return 0;
301}
302
145void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, 303void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
146 bool embedded, u8 sge_cnt) 304 bool embedded, u8 sge_cnt)
147{ 305{
@@ -203,6 +361,20 @@ struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
203 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 361 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
204} 362}
205 363
364struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
365{
366 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
367 struct be_mcc_wrb *wrb;
368
369 BUG_ON(atomic_read(&mccq->used) >= mccq->len);
370 wrb = queue_head_node(mccq);
371 queue_head_inc(mccq);
372 atomic_inc(&mccq->used);
373 memset(wrb, 0, sizeof(*wrb));
374 return wrb;
375}
376
377
206int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, 378int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
207 struct be_queue_info *eq, int eq_delay) 379 struct be_queue_info *eq, int eq_delay)
208{ 380{
@@ -212,6 +384,7 @@ int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
212 struct be_dma_mem *q_mem = &eq->dma_mem; 384 struct be_dma_mem *q_mem = &eq->dma_mem;
213 int status; 385 int status;
214 386
387 SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_eq_create\n");
215 spin_lock(&ctrl->mbox_lock); 388 spin_lock(&ctrl->mbox_lock);
216 memset(wrb, 0, sizeof(*wrb)); 389 memset(wrb, 0, sizeof(*wrb));
217 390
@@ -249,6 +422,7 @@ int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
249 int status; 422 int status;
250 u8 *endian_check; 423 u8 *endian_check;
251 424
425 SE_DEBUG(DBG_LVL_8, "In be_cmd_fw_initialize\n");
252 spin_lock(&ctrl->mbox_lock); 426 spin_lock(&ctrl->mbox_lock);
253 memset(wrb, 0, sizeof(*wrb)); 427 memset(wrb, 0, sizeof(*wrb));
254 428
@@ -282,6 +456,7 @@ int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
282 void *ctxt = &req->context; 456 void *ctxt = &req->context;
283 int status; 457 int status;
284 458
459 SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_cq_create \n");
285 spin_lock(&ctrl->mbox_lock); 460 spin_lock(&ctrl->mbox_lock);
286 memset(wrb, 0, sizeof(*wrb)); 461 memset(wrb, 0, sizeof(*wrb));
287 462
@@ -289,7 +464,6 @@ int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
289 464
290 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 465 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
291 OPCODE_COMMON_CQ_CREATE, sizeof(*req)); 466 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
292
293 if (!q_mem->va) 467 if (!q_mem->va)
294 SE_DEBUG(DBG_LVL_1, "uninitialized q_mem->va\n"); 468 SE_DEBUG(DBG_LVL_1, "uninitialized q_mem->va\n");
295 469
@@ -329,6 +503,53 @@ static u32 be_encoded_q_len(int q_len)
329 len_encoded = 0; 503 len_encoded = 0;
330 return len_encoded; 504 return len_encoded;
331} 505}
506
507int be_cmd_mccq_create(struct beiscsi_hba *phba,
508 struct be_queue_info *mccq,
509 struct be_queue_info *cq)
510{
511 struct be_mcc_wrb *wrb;
512 struct be_cmd_req_mcc_create *req;
513 struct be_dma_mem *q_mem = &mccq->dma_mem;
514 struct be_ctrl_info *ctrl;
515 void *ctxt;
516 int status;
517
518 spin_lock(&phba->ctrl.mbox_lock);
519 ctrl = &phba->ctrl;
520 wrb = wrb_from_mbox(&ctrl->mbox_mem);
521 req = embedded_payload(wrb);
522 ctxt = &req->context;
523
524 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
525
526 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
527 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
528
529 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
530
531 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
532 PCI_FUNC(phba->pcidev->devfn));
533 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
534 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
535 be_encoded_q_len(mccq->len));
536 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
537
538 be_dws_cpu_to_le(ctxt, sizeof(req->context));
539
540 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
541
542 status = be_mbox_notify_wait(phba);
543 if (!status) {
544 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
545 mccq->id = le16_to_cpu(resp->id);
546 mccq->created = true;
547 }
548 spin_unlock(&phba->ctrl.mbox_lock);
549
550 return status;
551}
552
332int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, 553int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
333 int queue_type) 554 int queue_type)
334{ 555{
@@ -337,6 +558,7 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
337 u8 subsys = 0, opcode = 0; 558 u8 subsys = 0, opcode = 0;
338 int status; 559 int status;
339 560
561 SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_q_destroy \n");
340 spin_lock(&ctrl->mbox_lock); 562 spin_lock(&ctrl->mbox_lock);
341 memset(wrb, 0, sizeof(*wrb)); 563 memset(wrb, 0, sizeof(*wrb));
342 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 564 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
@@ -350,6 +572,10 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
350 subsys = CMD_SUBSYSTEM_COMMON; 572 subsys = CMD_SUBSYSTEM_COMMON;
351 opcode = OPCODE_COMMON_CQ_DESTROY; 573 opcode = OPCODE_COMMON_CQ_DESTROY;
352 break; 574 break;
575 case QTYPE_MCCQ:
576 subsys = CMD_SUBSYSTEM_COMMON;
577 opcode = OPCODE_COMMON_MCC_DESTROY;
578 break;
353 case QTYPE_WRBQ: 579 case QTYPE_WRBQ:
354 subsys = CMD_SUBSYSTEM_ISCSI; 580 subsys = CMD_SUBSYSTEM_ISCSI;
355 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; 581 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
@@ -377,30 +603,6 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
377 return status; 603 return status;
378} 604}
379 605
380int be_cmd_get_mac_addr(struct be_ctrl_info *ctrl, u8 *mac_addr)
381{
382 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
383 struct be_cmd_req_get_mac_addr *req = embedded_payload(wrb);
384 int status;
385
386 spin_lock(&ctrl->mbox_lock);
387 memset(wrb, 0, sizeof(*wrb));
388 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
389 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
390 OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG,
391 sizeof(*req));
392
393 status = be_mbox_notify(ctrl);
394 if (!status) {
395 struct be_cmd_resp_get_mac_addr *resp = embedded_payload(wrb);
396
397 memcpy(mac_addr, resp->mac_address, ETH_ALEN);
398 }
399
400 spin_unlock(&ctrl->mbox_lock);
401 return status;
402}
403
404int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, 606int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
405 struct be_queue_info *cq, 607 struct be_queue_info *cq,
406 struct be_queue_info *dq, int length, 608 struct be_queue_info *dq, int length,
@@ -412,6 +614,7 @@ int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
412 void *ctxt = &req->context; 614 void *ctxt = &req->context;
413 int status; 615 int status;
414 616
617 SE_DEBUG(DBG_LVL_8, "In be_cmd_create_default_pdu_queue\n");
415 spin_lock(&ctrl->mbox_lock); 618 spin_lock(&ctrl->mbox_lock);
416 memset(wrb, 0, sizeof(*wrb)); 619 memset(wrb, 0, sizeof(*wrb));
417 620
@@ -468,8 +671,10 @@ int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
468 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 671 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
469 672
470 status = be_mbox_notify(ctrl); 673 status = be_mbox_notify(ctrl);
471 if (!status) 674 if (!status) {
472 wrbq->id = le16_to_cpu(resp->cid); 675 wrbq->id = le16_to_cpu(resp->cid);
676 wrbq->created = true;
677 }
473 spin_unlock(&ctrl->mbox_lock); 678 spin_unlock(&ctrl->mbox_lock);
474 return status; 679 return status;
475} 680}