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-rw-r--r--drivers/rtc/Kconfig147
-rw-r--r--drivers/rtc/Makefile3
-rw-r--r--drivers/rtc/rtc-ab-b5ze-s3.c1035
-rw-r--r--drivers/rtc/rtc-armada38x.c320
-rw-r--r--drivers/rtc/rtc-at91sam9.c2
-rw-r--r--drivers/rtc/rtc-ds1685.c2250
-rw-r--r--drivers/rtc/rtc-imxdi.c50
-rw-r--r--drivers/rtc/rtc-isl12022.c3
-rw-r--r--drivers/rtc/rtc-isl12057.c351
-rw-r--r--drivers/rtc/rtc-pcf2123.c10
-rw-r--r--drivers/rtc/rtc-rk808.c10
11 files changed, 4128 insertions, 53 deletions
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f15cddfeb897..b5b5c3d485d6 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -65,7 +65,7 @@ config RTC_DEBUG
65comment "RTC interfaces" 65comment "RTC interfaces"
66 66
67config RTC_INTF_SYSFS 67config RTC_INTF_SYSFS
68 boolean "/sys/class/rtc/rtcN (sysfs)" 68 bool "/sys/class/rtc/rtcN (sysfs)"
69 depends on SYSFS 69 depends on SYSFS
70 default RTC_CLASS 70 default RTC_CLASS
71 help 71 help
@@ -75,7 +75,7 @@ config RTC_INTF_SYSFS
75 If unsure, say Y. 75 If unsure, say Y.
76 76
77config RTC_INTF_PROC 77config RTC_INTF_PROC
78 boolean "/proc/driver/rtc (procfs for rtcN)" 78 bool "/proc/driver/rtc (procfs for rtcN)"
79 depends on PROC_FS 79 depends on PROC_FS
80 default RTC_CLASS 80 default RTC_CLASS
81 help 81 help
@@ -88,7 +88,7 @@ config RTC_INTF_PROC
88 If unsure, say Y. 88 If unsure, say Y.
89 89
90config RTC_INTF_DEV 90config RTC_INTF_DEV
91 boolean "/dev/rtcN (character devices)" 91 bool "/dev/rtcN (character devices)"
92 default RTC_CLASS 92 default RTC_CLASS
93 help 93 help
94 Say yes here if you want to use your RTCs using the /dev 94 Say yes here if you want to use your RTCs using the /dev
@@ -153,6 +153,17 @@ config RTC_DRV_88PM80X
153 This driver can also be built as a module. If so, the module 153 This driver can also be built as a module. If so, the module
154 will be called rtc-88pm80x. 154 will be called rtc-88pm80x.
155 155
156config RTC_DRV_ABB5ZES3
157 depends on I2C
158 select REGMAP_I2C
159 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"
160 help
161 If you say yes here you get support for the Abracon
162 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.
163
164 This driver can also be built as a module. If so, the module
165 will be called rtc-ab-b5ze-s3.
166
156config RTC_DRV_AS3722 167config RTC_DRV_AS3722
157 tristate "ams AS3722 RTC driver" 168 tristate "ams AS3722 RTC driver"
158 depends on MFD_AS3722 169 depends on MFD_AS3722
@@ -455,7 +466,7 @@ config RTC_DRV_DM355EVM
455 Supports the RTC firmware in the MSP430 on the DM355 EVM. 466 Supports the RTC firmware in the MSP430 on the DM355 EVM.
456 467
457config RTC_DRV_TWL92330 468config RTC_DRV_TWL92330
458 boolean "TI TWL92330/Menelaus" 469 bool "TI TWL92330/Menelaus"
459 depends on MENELAUS 470 depends on MENELAUS
460 help 471 help
461 If you say yes here you get support for the RTC on the 472 If you say yes here you get support for the RTC on the
@@ -790,6 +801,96 @@ config RTC_DRV_DS1553
790 This driver can also be built as a module. If so, the module 801 This driver can also be built as a module. If so, the module
791 will be called rtc-ds1553. 802 will be called rtc-ds1553.
792 803
804config RTC_DRV_DS1685_FAMILY
805 tristate "Dallas/Maxim DS1685 Family"
806 help
807 If you say yes here you get support for the Dallas/Maxim DS1685
808 family of real time chips. This family includes the DS1685/DS1687,
809 DS1689/DS1693, DS17285/DS17287, DS17485/DS17487, and
810 DS17885/DS17887 chips.
811
812 This driver can also be built as a module. If so, the module
813 will be called rtc-ds1685.
814
815choice
816 prompt "Subtype"
817 depends on RTC_DRV_DS1685_FAMILY
818 default RTC_DRV_DS1685
819
820config RTC_DRV_DS1685
821 bool "DS1685/DS1687"
822 help
823 This enables support for the Dallas/Maxim DS1685/DS1687 real time
824 clock chip.
825
826 This chip is commonly found in SGI O2 (IP32) and SGI Octane (IP30)
827 systems, as well as EPPC-405-UC modules by electronic system design
828 GmbH.
829
830config RTC_DRV_DS1689
831 bool "DS1689/DS1693"
832 help
833 This enables support for the Dallas/Maxim DS1689/DS1693 real time
834 clock chip.
835
836 This is an older RTC chip, supplanted by the DS1685/DS1687 above,
837 which supports a few minor features such as Vcc, Vbat, and Power
838 Cycle counters, plus a customer-specific, 8-byte ROM/Serial number.
839
840 It also works for the even older DS1688/DS1691 RTC chips, which are
841 virtually the same and carry the same model number. Both chips
842 have 114 bytes of user NVRAM.
843
844config RTC_DRV_DS17285
845 bool "DS17285/DS17287"
846 help
847 This enables support for the Dallas/Maxim DS17285/DS17287 real time
848 clock chip.
849
850 This chip features 2kb of extended NV-SRAM. It may possibly be
851 found in some SGI O2 systems (rare).
852
853config RTC_DRV_DS17485
854 bool "DS17485/DS17487"
855 help
856 This enables support for the Dallas/Maxim DS17485/DS17487 real time
857 clock chip.
858
859 This chip features 4kb of extended NV-SRAM.
860
861config RTC_DRV_DS17885
862 bool "DS17885/DS17887"
863 help
864 This enables support for the Dallas/Maxim DS17885/DS17887 real time
865 clock chip.
866
867 This chip features 8kb of extended NV-SRAM.
868
869endchoice
870
871config RTC_DS1685_PROC_REGS
872 bool "Display register values in /proc"
873 depends on RTC_DRV_DS1685_FAMILY && PROC_FS
874 help
875 Enable this to display a readout of all of the RTC registers in
876 /proc/drivers/rtc. Keep in mind that this can potentially lead
877 to lost interrupts, as reading Control Register C will clear
878 all pending IRQ flags.
879
880 Unless you are debugging this driver, choose N.
881
882config RTC_DS1685_SYSFS_REGS
883 bool "SysFS access to RTC register bits"
884 depends on RTC_DRV_DS1685_FAMILY && SYSFS
885 help
886 Enable this to provide access to the RTC control register bits
887 in /sys. Some of the bits are read-write, others are read-only.
888
889 Keep in mind that reading Control C's bits automatically clears
890 all pending IRQ flags - this can cause lost interrupts.
891
892 If you know that you need access to these bits, choose Y, Else N.
893
793config RTC_DRV_DS1742 894config RTC_DRV_DS1742
794 tristate "Maxim/Dallas DS1742/1743" 895 tristate "Maxim/Dallas DS1742/1743"
795 depends on HAS_IOMEM 896 depends on HAS_IOMEM
@@ -1141,34 +1242,6 @@ config RTC_DRV_AT91SAM9
1141 probably want to use the real RTC block instead of the "RTT as an 1242 probably want to use the real RTC block instead of the "RTT as an
1142 RTC" driver. 1243 RTC" driver.
1143 1244
1144config RTC_DRV_AT91SAM9_RTT
1145 int
1146 range 0 1
1147 default 0
1148 depends on RTC_DRV_AT91SAM9
1149 help
1150 This option is only relevant for legacy board support and
1151 won't be used when booting a DT board.
1152
1153 More than one RTT module is available. You can choose which
1154 one will be used as an RTC. The default of zero is normally
1155 OK to use, though some systems use that for non-RTC purposes.
1156
1157config RTC_DRV_AT91SAM9_GPBR
1158 int
1159 range 0 3
1160 default 0
1161 prompt "Backup Register Number"
1162 depends on RTC_DRV_AT91SAM9
1163 help
1164 This option is only relevant for legacy board support and
1165 won't be used when booting a DT board.
1166
1167 The RTC driver needs to use one of the General Purpose Backup
1168 Registers (GPBRs) as well as the RTT. You can choose which one
1169 will be used. The default of zero is normally OK to use, but
1170 on some systems other software needs to use that register.
1171
1172config RTC_DRV_AU1XXX 1245config RTC_DRV_AU1XXX
1173 tristate "Au1xxx Counter0 RTC support" 1246 tristate "Au1xxx Counter0 RTC support"
1174 depends on MIPS_ALCHEMY 1247 depends on MIPS_ALCHEMY
@@ -1269,6 +1342,16 @@ config RTC_DRV_MV
1269 This driver can also be built as a module. If so, the module 1342 This driver can also be built as a module. If so, the module
1270 will be called rtc-mv. 1343 will be called rtc-mv.
1271 1344
1345config RTC_DRV_ARMADA38X
1346 tristate "Armada 38x Marvell SoC RTC"
1347 depends on ARCH_MVEBU
1348 help
1349 If you say yes here you will get support for the in-chip RTC
1350 that can be found in the Armada 38x Marvell's SoC device
1351
1352 This driver can also be built as a module. If so, the module
1353 will be called armada38x-rtc.
1354
1272config RTC_DRV_PS3 1355config RTC_DRV_PS3
1273 tristate "PS3 RTC" 1356 tristate "PS3 RTC"
1274 depends on PPC_PS3 1357 depends on PPC_PS3
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index c8ef3e1e6ccd..69c87062b098 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -24,6 +24,8 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o
24obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o 24obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
25obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o 25obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
26obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o 26obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
27obj-$(CONFIG_RTC_DRV_ABB5ZES3) += rtc-ab-b5ze-s3.o
28obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o
27obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o 29obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
28obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o 30obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
29obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o 31obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
@@ -52,6 +54,7 @@ obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds1390.o
52obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o 54obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
53obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o 55obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
54obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o 56obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
57obj-$(CONFIG_RTC_DRV_DS1685_FAMILY) += rtc-ds1685.o
55obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o 58obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
56obj-$(CONFIG_RTC_DRV_DS2404) += rtc-ds2404.o 59obj-$(CONFIG_RTC_DRV_DS2404) += rtc-ds2404.o
57obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o 60obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
diff --git a/drivers/rtc/rtc-ab-b5ze-s3.c b/drivers/rtc/rtc-ab-b5ze-s3.c
new file mode 100644
index 000000000000..cfc2ef98d393
--- /dev/null
+++ b/drivers/rtc/rtc-ab-b5ze-s3.c
@@ -0,0 +1,1035 @@
1/*
2 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
3 * I2C RTC / Alarm chip
4 *
5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
6 *
7 * Detailed datasheet of the chip is available here:
8 *
9 * http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
10 *
11 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/mutex.h>
26#include <linux/rtc.h>
27#include <linux/i2c.h>
28#include <linux/bcd.h>
29#include <linux/of.h>
30#include <linux/regmap.h>
31#include <linux/interrupt.h>
32
33#define DRV_NAME "rtc-ab-b5ze-s3"
34
35/* Control section */
36#define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
37#define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
38#define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
39#define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
40#define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
41#define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
42#define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
43#define ABB5ZES3_REG_CTRL1_CAP BIT(7)
44
45#define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
46#define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
47#define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
48#define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
49#define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
50#define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
51#define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
52#define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
53#define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
54
55#define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
56#define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
57#define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
58#define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
59#define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
60#define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
61#define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
62#define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
63
64#define ABB5ZES3_CTRL_SEC_LEN 3
65
66/* RTC section */
67#define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
68#define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
69#define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
70#define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
71#define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
72#define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
73#define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
74#define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
75#define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
76
77#define ABB5ZES3_RTC_SEC_LEN 7
78
79/* Alarm section (enable bits are all active low) */
80#define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
81#define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
82#define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
83#define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
84#define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
85#define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
86#define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
87#define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
88
89#define ABB5ZES3_ALRM_SEC_LEN 4
90
91/* Frequency offset section */
92#define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
93#define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
94
95/* CLOCKOUT section */
96#define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
97#define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
98#define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
99#define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
100#define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
101#define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
102#define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
103#define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
104#define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
105
106/* Timer A Section */
107#define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
108#define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
109#define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
110#define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
111#define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
112
113#define ABB5ZES3_TIMA_SEC_LEN 2
114
115/* Timer B Section */
116#define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
117#define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
118#define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
119#define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
120#define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
121#define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
122#define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
123#define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
124#define ABB5ZES3_TIMB_SEC_LEN 2
125
126#define ABB5ZES3_MEM_MAP_LEN 0x14
127
128struct abb5zes3_rtc_data {
129 struct rtc_device *rtc;
130 struct regmap *regmap;
131 struct mutex lock;
132
133 int irq;
134
135 bool battery_low;
136 bool timer_alarm; /* current alarm is via timer A */
137};
138
139/*
140 * Try and match register bits w/ fixed null values to see whether we
141 * are dealing with an ABB5ZES3. Note: this function is called early
142 * during init and hence does need mutex protection.
143 */
144static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
145{
146 u8 regs[ABB5ZES3_MEM_MAP_LEN];
147 static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
148 0x80, 0xc0, 0xc0, 0xf8,
149 0xe0, 0x00, 0x00, 0x40,
150 0x40, 0x78, 0x00, 0x00,
151 0xf8, 0x00, 0x88, 0x00 };
152 int ret, i;
153
154 ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
155 if (ret)
156 return ret;
157
158 for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
159 if (regs[i] & mask[i]) /* check if bits are cleared */
160 return -ENODEV;
161 }
162
163 return 0;
164}
165
166/* Clear alarm status bit. */
167static int _abb5zes3_rtc_clear_alarm(struct device *dev)
168{
169 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
170 int ret;
171
172 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
173 ABB5ZES3_REG_CTRL2_AF, 0);
174 if (ret)
175 dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
176
177 return ret;
178}
179
180/* Enable or disable alarm (i.e. alarm interrupt generation) */
181static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
182{
183 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
184 int ret;
185
186 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
187 ABB5ZES3_REG_CTRL1_AIE,
188 enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
189 if (ret)
190 dev_err(dev, "%s: writing alarm INT failed (%d)\n",
191 __func__, ret);
192
193 return ret;
194}
195
196/* Enable or disable timer (watchdog timer A interrupt generation) */
197static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
198{
199 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
200 int ret;
201
202 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
203 ABB5ZES3_REG_CTRL2_WTAIE,
204 enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
205 if (ret)
206 dev_err(dev, "%s: writing timer INT failed (%d)\n",
207 __func__, ret);
208
209 return ret;
210}
211
212/*
213 * Note: we only read, so regmap inner lock protection is sufficient, i.e.
214 * we do not need driver's main lock protection.
215 */
216static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
217{
218 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
219 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
220 int ret;
221
222 /*
223 * As we need to read CTRL1 register anyway to access 24/12h
224 * mode bit, we do a single bulk read of both control and RTC
225 * sections (they are consecutive). This also ease indexing
226 * of register values after bulk read.
227 */
228 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
229 sizeof(regs));
230 if (ret) {
231 dev_err(dev, "%s: reading RTC time failed (%d)\n",
232 __func__, ret);
233 goto err;
234 }
235
236 /* If clock integrity is not guaranteed, do not return a time value */
237 if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC) {
238 ret = -ENODATA;
239 goto err;
240 }
241
242 tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
243 tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
244
245 if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
246 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
247 if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
248 tm->tm_hour += 12;
249 } else { /* 24hr mode */
250 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
251 }
252
253 tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
254 tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
255 tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
256 tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
257
258 ret = rtc_valid_tm(tm);
259
260err:
261 return ret;
262}
263
264static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
265{
266 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
267 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
268 int ret;
269
270 /*
271 * Year register is 8-bit wide and bcd-coded, i.e records values
272 * between 0 and 99. tm_year is an offset from 1900 and we are
273 * interested in the 2000-2099 range, so any value less than 100
274 * is invalid.
275 */
276 if (tm->tm_year < 100)
277 return -EINVAL;
278
279 regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
280 regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
281 regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
282 regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
283 regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
284 regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
285 regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
286
287 mutex_lock(&data->lock);
288 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
289 regs + ABB5ZES3_REG_RTC_SC,
290 ABB5ZES3_RTC_SEC_LEN);
291 mutex_unlock(&data->lock);
292
293
294 return ret;
295}
296
297/*
298 * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
299 * given number of seconds.
300 */
301static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
302{
303 *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
304 *timer_a = secs;
305}
306
307/*
308 * Return current number of seconds in Timer A. As we only use
309 * timer A with a 1Hz freq, this is what we expect to have.
310 */
311static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
312{
313 if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
314 return -EINVAL;
315
316 *secs = timer_a;
317
318 return 0;
319}
320
321/*
322 * Read alarm currently configured via a watchdog timer using timer A. This
323 * is done by reading current RTC time and adding remaining timer time.
324 */
325static int _abb5zes3_rtc_read_timer(struct device *dev,
326 struct rtc_wkalrm *alarm)
327{
328 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
329 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
330 u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
331 unsigned long rtc_secs;
332 unsigned int reg;
333 u8 timer_secs;
334 int ret;
335
336 /*
337 * Instead of doing two separate calls, because they are consecutive,
338 * we grab both clockout register and Timer A section. The latter is
339 * used to decide if timer A is enabled (as a watchdog timer).
340 */
341 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
342 ABB5ZES3_TIMA_SEC_LEN + 1);
343 if (ret) {
344 dev_err(dev, "%s: reading Timer A section failed (%d)\n",
345 __func__, ret);
346 goto err;
347 }
348
349 /* get current time ... */
350 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
351 if (ret)
352 goto err;
353
354 /* ... convert to seconds ... */
355 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
356 if (ret)
357 goto err;
358
359 /* ... add remaining timer A time ... */
360 ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
361 if (ret)
362 goto err;
363
364 /* ... and convert back. */
365 rtc_time_to_tm(rtc_secs + timer_secs, alarm_tm);
366
367 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, &reg);
368 if (ret) {
369 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
370 __func__, ret);
371 goto err;
372 }
373
374 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
375
376err:
377 return ret;
378}
379
380/* Read alarm currently configured via a RTC alarm registers. */
381static int _abb5zes3_rtc_read_alarm(struct device *dev,
382 struct rtc_wkalrm *alarm)
383{
384 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
385 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
386 unsigned long rtc_secs, alarm_secs;
387 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
388 unsigned int reg;
389 int ret;
390
391 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
392 ABB5ZES3_ALRM_SEC_LEN);
393 if (ret) {
394 dev_err(dev, "%s: reading alarm section failed (%d)\n",
395 __func__, ret);
396 goto err;
397 }
398
399 alarm_tm->tm_sec = 0;
400 alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
401 alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
402 alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
403 alarm_tm->tm_wday = -1;
404
405 /*
406 * The alarm section does not store year/month. We use the ones in rtc
407 * section as a basis and increment month and then year if needed to get
408 * alarm after current time.
409 */
410 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
411 if (ret)
412 goto err;
413
414 alarm_tm->tm_year = rtc_tm.tm_year;
415 alarm_tm->tm_mon = rtc_tm.tm_mon;
416
417 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
418 if (ret)
419 goto err;
420
421 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
422 if (ret)
423 goto err;
424
425 if (alarm_secs < rtc_secs) {
426 if (alarm_tm->tm_mon == 11) {
427 alarm_tm->tm_mon = 0;
428 alarm_tm->tm_year += 1;
429 } else {
430 alarm_tm->tm_mon += 1;
431 }
432 }
433
434 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, &reg);
435 if (ret) {
436 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
437 __func__, ret);
438 goto err;
439 }
440
441 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
442
443err:
444 return ret;
445}
446
447/*
448 * As the Alarm mechanism supported by the chip is only accurate to the
449 * minute, we use the watchdog timer mechanism provided by timer A
450 * (up to 256 seconds w/ a second accuracy) for low alarm values (below
451 * 4 minutes). Otherwise, we use the common alarm mechanism provided
452 * by the chip. In order for that to work, we keep track of currently
453 * configured timer type via 'timer_alarm' flag in our private data
454 * structure.
455 */
456static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
457{
458 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
459 int ret;
460
461 mutex_lock(&data->lock);
462 if (data->timer_alarm)
463 ret = _abb5zes3_rtc_read_timer(dev, alarm);
464 else
465 ret = _abb5zes3_rtc_read_alarm(dev, alarm);
466 mutex_unlock(&data->lock);
467
468 return ret;
469}
470
471/*
472 * Set alarm using chip alarm mechanism. It is only accurate to the
473 * minute (not the second). The function expects alarm interrupt to
474 * be disabled.
475 */
476static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
477{
478 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
479 struct rtc_time *alarm_tm = &alarm->time;
480 unsigned long rtc_secs, alarm_secs;
481 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
482 struct rtc_time rtc_tm;
483 int ret, enable = 1;
484
485 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
486 if (ret)
487 goto err;
488
489 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
490 if (ret)
491 goto err;
492
493 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
494 if (ret)
495 goto err;
496
497 /* If alarm time is before current time, disable the alarm */
498 if (!alarm->enabled || alarm_secs <= rtc_secs) {
499 enable = 0;
500 } else {
501 /*
502 * Chip only support alarms up to one month in the future. Let's
503 * return an error if we get something after that limit.
504 * Comparison is done by incrementing rtc_tm month field by one
505 * and checking alarm value is still below.
506 */
507 if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
508 rtc_tm.tm_mon = 0;
509 rtc_tm.tm_year += 1;
510 } else {
511 rtc_tm.tm_mon += 1;
512 }
513
514 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
515 if (ret)
516 goto err;
517
518 if (alarm_secs > rtc_secs) {
519 dev_err(dev, "%s: alarm maximum is one month in the "
520 "future (%d)\n", __func__, ret);
521 ret = -EINVAL;
522 goto err;
523 }
524 }
525
526 /*
527 * Program all alarm registers but DW one. For each register, setting
528 * MSB to 0 enables associated alarm.
529 */
530 regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
531 regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
532 regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
533 regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
534
535 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
536 ABB5ZES3_ALRM_SEC_LEN);
537 if (ret < 0) {
538 dev_err(dev, "%s: writing ALARM section failed (%d)\n",
539 __func__, ret);
540 goto err;
541 }
542
543 /* Record currently configured alarm is not a timer */
544 data->timer_alarm = 0;
545
546 /* Enable or disable alarm interrupt generation */
547 ret = _abb5zes3_rtc_update_alarm(dev, enable);
548
549err:
550 return ret;
551}
552
553/*
554 * Set alarm using timer watchdog (via timer A) mechanism. The function expects
555 * timer A interrupt to be disabled.
556 */
557static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
558 u8 secs)
559{
560 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
561 u8 regs[ABB5ZES3_TIMA_SEC_LEN];
562 u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
563 int ret = 0;
564
565 /* Program given number of seconds to Timer A registers */
566 sec_to_timer_a(secs, &regs[0], &regs[1]);
567 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
568 ABB5ZES3_TIMA_SEC_LEN);
569 if (ret < 0) {
570 dev_err(dev, "%s: writing timer section failed\n", __func__);
571 goto err;
572 }
573
574 /* Configure Timer A as a watchdog timer */
575 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
576 mask, ABB5ZES3_REG_TIM_CLK_TAC1);
577 if (ret)
578 dev_err(dev, "%s: failed to update timer\n", __func__);
579
580 /* Record currently configured alarm is a timer */
581 data->timer_alarm = 1;
582
583 /* Enable or disable timer interrupt generation */
584 ret = _abb5zes3_rtc_update_timer(dev, alarm->enabled);
585
586err:
587 return ret;
588}
589
590/*
591 * The chip has an alarm which is only accurate to the minute. In order to
592 * handle alarms below that limit, we use the watchdog timer function of
593 * timer A. More precisely, the timer method is used for alarms below 240
594 * seconds.
595 */
596static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
597{
598 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
599 struct rtc_time *alarm_tm = &alarm->time;
600 unsigned long rtc_secs, alarm_secs;
601 struct rtc_time rtc_tm;
602 int ret;
603
604 mutex_lock(&data->lock);
605 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
606 if (ret)
607 goto err;
608
609 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
610 if (ret)
611 goto err;
612
613 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
614 if (ret)
615 goto err;
616
617 /* Let's first disable both the alarm and the timer interrupts */
618 ret = _abb5zes3_rtc_update_alarm(dev, false);
619 if (ret < 0) {
620 dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
621 ret);
622 goto err;
623 }
624 ret = _abb5zes3_rtc_update_timer(dev, false);
625 if (ret < 0) {
626 dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
627 ret);
628 goto err;
629 }
630
631 data->timer_alarm = 0;
632
633 /*
634 * Let's now configure the alarm; if we are expected to ring in
635 * more than 240s, then we setup an alarm. Otherwise, a timer.
636 */
637 if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
638 ret = _abb5zes3_rtc_set_timer(dev, alarm,
639 alarm_secs - rtc_secs);
640 else
641 ret = _abb5zes3_rtc_set_alarm(dev, alarm);
642
643 err:
644 mutex_unlock(&data->lock);
645
646 if (ret)
647 dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
648 ret);
649
650 return ret;
651 }
652
653/* Enable or disable battery low irq generation */
654static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
655 bool enable)
656{
657 return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
658 ABB5ZES3_REG_CTRL3_BLIE,
659 enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
660}
661
662/*
663 * Check current RTC status and enable/disable what needs to be. Return 0 if
664 * everything went ok and a negative value upon error. Note: this function
665 * is called early during init and hence does need mutex protection.
666 */
667static int abb5zes3_rtc_check_setup(struct device *dev)
668{
669 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
670 struct regmap *regmap = data->regmap;
671 unsigned int reg;
672 int ret;
673 u8 mask;
674
675 /*
676 * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
677 * is disabled here to prevent polluting the interrupt line and
678 * uselessly triggering the IRQ handler we install for alarm and battery
679 * low events. Note: this is done before clearing int. status below
680 * in this function.
681 * We also disable all timers and set timer interrupt to permanent (not
682 * pulsed).
683 */
684 mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
685 ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
686 ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
687 ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
688 ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
689 ABB5ZES3_REG_TIM_CLK_COF0 | ABB5ZES3_REG_TIM_CLK_COF1 |
690 ABB5ZES3_REG_TIM_CLK_COF2);
691 if (ret < 0) {
692 dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
693 __func__, ret);
694 return ret;
695 }
696
697 /*
698 * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
699 * individually by clearing/setting MSB of each associated register. So,
700 * we set all alarm enable bits to disable current alarm setting.
701 */
702 mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
703 ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
704 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
705 if (ret < 0) {
706 dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
707 __func__, ret);
708 return ret;
709 }
710
711 /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
712 mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
713 ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
714 ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
715 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
716 if (ret < 0) {
717 dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
718 __func__, ret);
719 return ret;
720 }
721
722 /*
723 * Set Control 2 register (timer int. disabled, alarm status cleared).
724 * WTAF is read-only and cleared automatically by reading the register.
725 */
726 mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
727 ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
728 ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
729 ABB5ZES3_REG_CTRL2_CTAF);
730 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
731 if (ret < 0) {
732 dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
733 __func__, ret);
734 return ret;
735 }
736
737 /*
738 * Enable battery low detection function and battery switchover function
739 * (standard mode). Disable associated interrupts. Clear battery
740 * switchover flag but not battery low flag. The latter is checked
741 * later below.
742 */
743 mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
744 ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
745 ABB5ZES3_REG_CTRL3_BSIE| ABB5ZES3_REG_CTRL3_BSF);
746 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
747 if (ret < 0) {
748 dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
749 __func__, ret);
750 return ret;
751 }
752
753 /* Check oscillator integrity flag */
754 ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, &reg);
755 if (ret < 0) {
756 dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
757 __func__, ret);
758 return ret;
759 }
760
761 if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
762 dev_err(dev, "clock integrity not guaranteed. Osc. has stopped "
763 "or has been interrupted.\n");
764 dev_err(dev, "change battery (if not already done) and "
765 "then set time to reset osc. failure flag.\n");
766 }
767
768 /*
769 * Check battery low flag at startup: this allows reporting battery
770 * is low at startup when IRQ line is not connected. Note: we record
771 * current status to avoid reenabling this interrupt later in probe
772 * function if battery is low.
773 */
774 ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, &reg);
775 if (ret < 0) {
776 dev_err(dev, "%s: unable to read battery low flag (%d)\n",
777 __func__, ret);
778 return ret;
779 }
780
781 data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
782 if (data->battery_low) {
783 dev_err(dev, "RTC battery is low; please, consider "
784 "changing it!\n");
785
786 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
787 if (ret)
788 dev_err(dev, "%s: disabling battery low interrupt "
789 "generation failed (%d)\n", __func__, ret);
790 }
791
792 return ret;
793}
794
795static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
796 unsigned int enable)
797{
798 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
799 int ret = 0;
800
801 if (rtc_data->irq) {
802 mutex_lock(&rtc_data->lock);
803 if (rtc_data->timer_alarm)
804 ret = _abb5zes3_rtc_update_timer(dev, enable);
805 else
806 ret = _abb5zes3_rtc_update_alarm(dev, enable);
807 mutex_unlock(&rtc_data->lock);
808 }
809
810 return ret;
811}
812
813static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
814{
815 struct i2c_client *client = data;
816 struct device *dev = &client->dev;
817 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
818 struct rtc_device *rtc = rtc_data->rtc;
819 u8 regs[ABB5ZES3_CTRL_SEC_LEN];
820 int ret, handled = IRQ_NONE;
821
822 ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
823 ABB5ZES3_CTRL_SEC_LEN);
824 if (ret) {
825 dev_err(dev, "%s: unable to read control section (%d)!\n",
826 __func__, ret);
827 return handled;
828 }
829
830 /*
831 * Check battery low detection flag and disable battery low interrupt
832 * generation if flag is set (interrupt can only be cleared when
833 * battery is replaced).
834 */
835 if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
836 dev_err(dev, "RTC battery is low; please change it!\n");
837
838 _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
839
840 handled = IRQ_HANDLED;
841 }
842
843 /* Check alarm flag */
844 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
845 dev_dbg(dev, "RTC alarm!\n");
846
847 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
848
849 /* Acknowledge and disable the alarm */
850 _abb5zes3_rtc_clear_alarm(dev);
851 _abb5zes3_rtc_update_alarm(dev, 0);
852
853 handled = IRQ_HANDLED;
854 }
855
856 /* Check watchdog Timer A flag */
857 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
858 dev_dbg(dev, "RTC timer!\n");
859
860 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
861
862 /*
863 * Acknowledge and disable the alarm. Note: WTAF
864 * flag had been cleared when reading CTRL2
865 */
866 _abb5zes3_rtc_update_timer(dev, 0);
867
868 rtc_data->timer_alarm = 0;
869
870 handled = IRQ_HANDLED;
871 }
872
873 return handled;
874}
875
876static const struct rtc_class_ops rtc_ops = {
877 .read_time = _abb5zes3_rtc_read_time,
878 .set_time = abb5zes3_rtc_set_time,
879 .read_alarm = abb5zes3_rtc_read_alarm,
880 .set_alarm = abb5zes3_rtc_set_alarm,
881 .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
882};
883
884static struct regmap_config abb5zes3_rtc_regmap_config = {
885 .reg_bits = 8,
886 .val_bits = 8,
887};
888
889static int abb5zes3_probe(struct i2c_client *client,
890 const struct i2c_device_id *id)
891{
892 struct abb5zes3_rtc_data *data = NULL;
893 struct device *dev = &client->dev;
894 struct regmap *regmap;
895 int ret;
896
897 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
898 I2C_FUNC_SMBUS_BYTE_DATA |
899 I2C_FUNC_SMBUS_I2C_BLOCK)) {
900 ret = -ENODEV;
901 goto err;
902 }
903
904 regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
905 if (IS_ERR(regmap)) {
906 ret = PTR_ERR(regmap);
907 dev_err(dev, "%s: regmap allocation failed: %d\n",
908 __func__, ret);
909 goto err;
910 }
911
912 ret = abb5zes3_i2c_validate_chip(regmap);
913 if (ret)
914 goto err;
915
916 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
917 if (!data) {
918 ret = -ENOMEM;
919 goto err;
920 }
921
922 mutex_init(&data->lock);
923 data->regmap = regmap;
924 dev_set_drvdata(dev, data);
925
926 ret = abb5zes3_rtc_check_setup(dev);
927 if (ret)
928 goto err;
929
930 if (client->irq > 0) {
931 ret = devm_request_threaded_irq(dev, client->irq, NULL,
932 _abb5zes3_rtc_interrupt,
933 IRQF_SHARED|IRQF_ONESHOT,
934 DRV_NAME, client);
935 if (!ret) {
936 device_init_wakeup(dev, true);
937 data->irq = client->irq;
938 dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
939 client->irq);
940 } else {
941 dev_err(dev, "%s: irq %d unavailable (%d)\n",
942 __func__, client->irq, ret);
943 goto err;
944 }
945 }
946
947 data->rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops,
948 THIS_MODULE);
949 ret = PTR_ERR_OR_ZERO(data->rtc);
950 if (ret) {
951 dev_err(dev, "%s: unable to register RTC device (%d)\n",
952 __func__, ret);
953 goto err;
954 }
955
956 /* Enable battery low detection interrupt if battery not already low */
957 if (!data->battery_low && data->irq) {
958 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
959 if (ret) {
960 dev_err(dev, "%s: enabling battery low interrupt "
961 "generation failed (%d)\n", __func__, ret);
962 goto err;
963 }
964 }
965
966err:
967 if (ret && data && data->irq)
968 device_init_wakeup(dev, false);
969 return ret;
970}
971
972static int abb5zes3_remove(struct i2c_client *client)
973{
974 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(&client->dev);
975
976 if (rtc_data->irq > 0)
977 device_init_wakeup(&client->dev, false);
978
979 return 0;
980}
981
982#ifdef CONFIG_PM_SLEEP
983static int abb5zes3_rtc_suspend(struct device *dev)
984{
985 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
986
987 if (device_may_wakeup(dev))
988 return enable_irq_wake(rtc_data->irq);
989
990 return 0;
991}
992
993static int abb5zes3_rtc_resume(struct device *dev)
994{
995 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
996
997 if (device_may_wakeup(dev))
998 return disable_irq_wake(rtc_data->irq);
999
1000 return 0;
1001}
1002#endif
1003
1004static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
1005 abb5zes3_rtc_resume);
1006
1007#ifdef CONFIG_OF
1008static const struct of_device_id abb5zes3_dt_match[] = {
1009 { .compatible = "abracon,abb5zes3" },
1010 { },
1011};
1012#endif
1013
1014static const struct i2c_device_id abb5zes3_id[] = {
1015 { "abb5zes3", 0 },
1016 { }
1017};
1018MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
1019
1020static struct i2c_driver abb5zes3_driver = {
1021 .driver = {
1022 .name = DRV_NAME,
1023 .owner = THIS_MODULE,
1024 .pm = &abb5zes3_rtc_pm_ops,
1025 .of_match_table = of_match_ptr(abb5zes3_dt_match),
1026 },
1027 .probe = abb5zes3_probe,
1028 .remove = abb5zes3_remove,
1029 .id_table = abb5zes3_id,
1030};
1031module_i2c_driver(abb5zes3_driver);
1032
1033MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
1034MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
1035MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c
new file mode 100644
index 000000000000..43e04af39e09
--- /dev/null
+++ b/drivers/rtc/rtc-armada38x.c
@@ -0,0 +1,320 @@
1/*
2 * RTC driver for the Armada 38x Marvell SoCs
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Gregory Clement <gregory.clement@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/rtc.h>
21
22#define RTC_STATUS 0x0
23#define RTC_STATUS_ALARM1 BIT(0)
24#define RTC_STATUS_ALARM2 BIT(1)
25#define RTC_IRQ1_CONF 0x4
26#define RTC_IRQ1_AL_EN BIT(0)
27#define RTC_IRQ1_FREQ_EN BIT(1)
28#define RTC_IRQ1_FREQ_1HZ BIT(2)
29#define RTC_TIME 0xC
30#define RTC_ALARM1 0x10
31
32#define SOC_RTC_INTERRUPT 0x8
33#define SOC_RTC_ALARM1 BIT(0)
34#define SOC_RTC_ALARM2 BIT(1)
35#define SOC_RTC_ALARM1_MASK BIT(2)
36#define SOC_RTC_ALARM2_MASK BIT(3)
37
38struct armada38x_rtc {
39 struct rtc_device *rtc_dev;
40 void __iomem *regs;
41 void __iomem *regs_soc;
42 spinlock_t lock;
43 int irq;
44};
45
46/*
47 * According to the datasheet, the OS should wait 5us after every
48 * register write to the RTC hard macro so that the required update
49 * can occur without holding off the system bus
50 */
51static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
52{
53 writel(val, rtc->regs + offset);
54 udelay(5);
55}
56
57static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
58{
59 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
60 unsigned long time, time_check, flags;
61
62 spin_lock_irqsave(&rtc->lock, flags);
63
64 time = readl(rtc->regs + RTC_TIME);
65 /*
66 * WA for failing time set attempts. As stated in HW ERRATA if
67 * more than one second between two time reads is detected
68 * then read once again.
69 */
70 time_check = readl(rtc->regs + RTC_TIME);
71 if ((time_check - time) > 1)
72 time_check = readl(rtc->regs + RTC_TIME);
73
74 spin_unlock_irqrestore(&rtc->lock, flags);
75
76 rtc_time_to_tm(time_check, tm);
77
78 return 0;
79}
80
81static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
82{
83 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
84 int ret = 0;
85 unsigned long time, flags;
86
87 ret = rtc_tm_to_time(tm, &time);
88
89 if (ret)
90 goto out;
91 /*
92 * Setting the RTC time not always succeeds. According to the
93 * errata we need to first write on the status register and
94 * then wait for 100ms before writing to the time register to be
95 * sure that the data will be taken into account.
96 */
97 spin_lock_irqsave(&rtc->lock, flags);
98
99 rtc_delayed_write(0, rtc, RTC_STATUS);
100
101 spin_unlock_irqrestore(&rtc->lock, flags);
102
103 msleep(100);
104
105 spin_lock_irqsave(&rtc->lock, flags);
106
107 rtc_delayed_write(time, rtc, RTC_TIME);
108
109 spin_unlock_irqrestore(&rtc->lock, flags);
110out:
111 return ret;
112}
113
114static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
115{
116 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
117 unsigned long time, flags;
118 u32 val;
119
120 spin_lock_irqsave(&rtc->lock, flags);
121
122 time = readl(rtc->regs + RTC_ALARM1);
123 val = readl(rtc->regs + RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN;
124
125 spin_unlock_irqrestore(&rtc->lock, flags);
126
127 alrm->enabled = val ? 1 : 0;
128 rtc_time_to_tm(time, &alrm->time);
129
130 return 0;
131}
132
133static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
134{
135 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
136 unsigned long time, flags;
137 int ret = 0;
138 u32 val;
139
140 ret = rtc_tm_to_time(&alrm->time, &time);
141
142 if (ret)
143 goto out;
144
145 spin_lock_irqsave(&rtc->lock, flags);
146
147 rtc_delayed_write(time, rtc, RTC_ALARM1);
148
149 if (alrm->enabled) {
150 rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
151 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
152 writel(val | SOC_RTC_ALARM1_MASK,
153 rtc->regs_soc + SOC_RTC_INTERRUPT);
154 }
155
156 spin_unlock_irqrestore(&rtc->lock, flags);
157
158out:
159 return ret;
160}
161
162static int armada38x_rtc_alarm_irq_enable(struct device *dev,
163 unsigned int enabled)
164{
165 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
166 unsigned long flags;
167
168 spin_lock_irqsave(&rtc->lock, flags);
169
170 if (enabled)
171 rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
172 else
173 rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
174
175 spin_unlock_irqrestore(&rtc->lock, flags);
176
177 return 0;
178}
179
180static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
181{
182 struct armada38x_rtc *rtc = data;
183 u32 val;
184 int event = RTC_IRQF | RTC_AF;
185
186 dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
187
188 spin_lock(&rtc->lock);
189
190 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
191
192 writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
193 val = readl(rtc->regs + RTC_IRQ1_CONF);
194 /* disable all the interrupts for alarm 1 */
195 rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
196 /* Ack the event */
197 rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS);
198
199 spin_unlock(&rtc->lock);
200
201 if (val & RTC_IRQ1_FREQ_EN) {
202 if (val & RTC_IRQ1_FREQ_1HZ)
203 event |= RTC_UF;
204 else
205 event |= RTC_PF;
206 }
207
208 rtc_update_irq(rtc->rtc_dev, 1, event);
209
210 return IRQ_HANDLED;
211}
212
213static struct rtc_class_ops armada38x_rtc_ops = {
214 .read_time = armada38x_rtc_read_time,
215 .set_time = armada38x_rtc_set_time,
216 .read_alarm = armada38x_rtc_read_alarm,
217 .set_alarm = armada38x_rtc_set_alarm,
218 .alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
219};
220
221static __init int armada38x_rtc_probe(struct platform_device *pdev)
222{
223 struct resource *res;
224 struct armada38x_rtc *rtc;
225 int ret;
226
227 rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
228 GFP_KERNEL);
229 if (!rtc)
230 return -ENOMEM;
231
232 spin_lock_init(&rtc->lock);
233
234 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
235 rtc->regs = devm_ioremap_resource(&pdev->dev, res);
236 if (IS_ERR(rtc->regs))
237 return PTR_ERR(rtc->regs);
238 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
239 rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
240 if (IS_ERR(rtc->regs_soc))
241 return PTR_ERR(rtc->regs_soc);
242
243 rtc->irq = platform_get_irq(pdev, 0);
244
245 if (rtc->irq < 0) {
246 dev_err(&pdev->dev, "no irq\n");
247 return rtc->irq;
248 }
249 if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
250 0, pdev->name, rtc) < 0) {
251 dev_warn(&pdev->dev, "Interrupt not available.\n");
252 rtc->irq = -1;
253 /*
254 * If there is no interrupt available then we can't
255 * use the alarm
256 */
257 armada38x_rtc_ops.set_alarm = NULL;
258 armada38x_rtc_ops.alarm_irq_enable = NULL;
259 }
260 platform_set_drvdata(pdev, rtc);
261 if (rtc->irq != -1)
262 device_init_wakeup(&pdev->dev, 1);
263
264 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
265 &armada38x_rtc_ops, THIS_MODULE);
266 if (IS_ERR(rtc->rtc_dev)) {
267 ret = PTR_ERR(rtc->rtc_dev);
268 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
269 return ret;
270 }
271 return 0;
272}
273
274#ifdef CONFIG_PM_SLEEP
275static int armada38x_rtc_suspend(struct device *dev)
276{
277 if (device_may_wakeup(dev)) {
278 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
279
280 return enable_irq_wake(rtc->irq);
281 }
282
283 return 0;
284}
285
286static int armada38x_rtc_resume(struct device *dev)
287{
288 if (device_may_wakeup(dev)) {
289 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
290
291 return disable_irq_wake(rtc->irq);
292 }
293
294 return 0;
295}
296#endif
297
298static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
299 armada38x_rtc_suspend, armada38x_rtc_resume);
300
301#ifdef CONFIG_OF
302static const struct of_device_id armada38x_rtc_of_match_table[] = {
303 { .compatible = "marvell,armada-380-rtc", },
304 {}
305};
306#endif
307
308static struct platform_driver armada38x_rtc_driver = {
309 .driver = {
310 .name = "armada38x-rtc",
311 .pm = &armada38x_rtc_pm_ops,
312 .of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
313 },
314};
315
316module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
317
318MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
319MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
320MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index 6b9aaf1afc72..2183fd2750ab 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -313,7 +313,7 @@ static const struct rtc_class_ops at91_rtc_ops = {
313 .alarm_irq_enable = at91_rtc_alarm_irq_enable, 313 .alarm_irq_enable = at91_rtc_alarm_irq_enable,
314}; 314};
315 315
316static struct regmap_config gpbr_regmap_config = { 316static const struct regmap_config gpbr_regmap_config = {
317 .reg_bits = 32, 317 .reg_bits = 32,
318 .val_bits = 32, 318 .val_bits = 32,
319 .reg_stride = 4, 319 .reg_stride = 4,
diff --git a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c
new file mode 100644
index 000000000000..803869c7d7c2
--- /dev/null
+++ b/drivers/rtc/rtc-ds1685.c
@@ -0,0 +1,2250 @@
1/*
2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
3 * chips.
4 *
5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
7 *
8 * References:
9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
12 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/bcd.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/rtc.h>
25#include <linux/workqueue.h>
26
27#include <linux/rtc/ds1685.h>
28
29#ifdef CONFIG_PROC_FS
30#include <linux/proc_fs.h>
31#endif
32
33#define DRV_VERSION "0.42.0"
34
35
36/* ----------------------------------------------------------------------- */
37/* Standard read/write functions if platform does not provide overrides */
38
39/**
40 * ds1685_read - read a value from an rtc register.
41 * @rtc: pointer to the ds1685 rtc structure.
42 * @reg: the register address to read.
43 */
44static u8
45ds1685_read(struct ds1685_priv *rtc, int reg)
46{
47 return readb((u8 __iomem *)rtc->regs +
48 (reg * rtc->regstep));
49}
50
51/**
52 * ds1685_write - write a value to an rtc register.
53 * @rtc: pointer to the ds1685 rtc structure.
54 * @reg: the register address to write.
55 * @value: value to write to the register.
56 */
57static void
58ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
59{
60 writeb(value, ((u8 __iomem *)rtc->regs +
61 (reg * rtc->regstep)));
62}
63/* ----------------------------------------------------------------------- */
64
65
66/* ----------------------------------------------------------------------- */
67/* Inlined functions */
68
69/**
70 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
71 * @rtc: pointer to the ds1685 rtc structure.
72 * @val: u8 time value to consider converting.
73 * @bcd_mask: u8 mask value if BCD mode is used.
74 * @bin_mask: u8 mask value if BIN mode is used.
75 *
76 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
77 */
78static inline u8
79ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
80{
81 if (rtc->bcd_mode)
82 return (bcd2bin(val) & bcd_mask);
83
84 return (val & bin_mask);
85}
86
87/**
88 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
89 * @rtc: pointer to the ds1685 rtc structure.
90 * @val: u8 time value to consider converting.
91 * @bin_mask: u8 mask value if BIN mode is used.
92 * @bcd_mask: u8 mask value if BCD mode is used.
93 *
94 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
95 */
96static inline u8
97ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
98{
99 if (rtc->bcd_mode)
100 return (bin2bcd(val) & bcd_mask);
101
102 return (val & bin_mask);
103}
104
105/**
106 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
107 * @rtc: pointer to the ds1685 rtc structure.
108 */
109static inline void
110ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
111{
112 rtc->write(rtc, RTC_CTRL_A,
113 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
114}
115
116/**
117 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
118 * @rtc: pointer to the ds1685 rtc structure.
119 */
120static inline void
121ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
122{
123 rtc->write(rtc, RTC_CTRL_A,
124 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
125}
126
127/**
128 * ds1685_rtc_begin_data_access - prepare the rtc for data access.
129 * @rtc: pointer to the ds1685 rtc structure.
130 *
131 * This takes several steps to prepare the rtc for access to get/set time
132 * and alarm values from the rtc registers:
133 * - Sets the SET bit in Control Register B.
134 * - Reads Ext Control Register 4A and checks the INCR bit.
135 * - If INCR is active, a short delay is added before Ext Control Register 4A
136 * is read again in a loop until INCR is inactive.
137 * - Switches the rtc to bank 1. This allows access to all relevant
138 * data for normal rtc operation, as bank 0 contains only the nvram.
139 */
140static inline void
141ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
142{
143 /* Set the SET bit in Ctrl B */
144 rtc->write(rtc, RTC_CTRL_B,
145 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
146
147 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
148 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
149 cpu_relax();
150
151 /* Switch to Bank 1 */
152 ds1685_rtc_switch_to_bank1(rtc);
153}
154
155/**
156 * ds1685_rtc_end_data_access - end data access on the rtc.
157 * @rtc: pointer to the ds1685 rtc structure.
158 *
159 * This ends what was started by ds1685_rtc_begin_data_access:
160 * - Switches the rtc back to bank 0.
161 * - Clears the SET bit in Control Register B.
162 */
163static inline void
164ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
165{
166 /* Switch back to Bank 0 */
167 ds1685_rtc_switch_to_bank1(rtc);
168
169 /* Clear the SET bit in Ctrl B */
170 rtc->write(rtc, RTC_CTRL_B,
171 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
172}
173
174/**
175 * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
176 * @rtc: pointer to the ds1685 rtc structure.
177 * @flags: irq flags variable for spin_lock_irqsave.
178 *
179 * This takes several steps to prepare the rtc for access to read just the
180 * control registers:
181 * - Sets a spinlock on the rtc IRQ.
182 * - Switches the rtc to bank 1. This allows access to the two extended
183 * control registers.
184 *
185 * Only use this where you are certain another lock will not be held.
186 */
187static inline void
188ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
189{
190 spin_lock_irqsave(&rtc->lock, flags);
191 ds1685_rtc_switch_to_bank1(rtc);
192}
193
194/**
195 * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
196 * @rtc: pointer to the ds1685 rtc structure.
197 * @flags: irq flags variable for spin_unlock_irqrestore.
198 *
199 * This ends what was started by ds1685_rtc_begin_ctrl_access:
200 * - Switches the rtc back to bank 0.
201 * - Unsets the spinlock on the rtc IRQ.
202 */
203static inline void
204ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
205{
206 ds1685_rtc_switch_to_bank0(rtc);
207 spin_unlock_irqrestore(&rtc->lock, flags);
208}
209
210/**
211 * ds1685_rtc_get_ssn - retrieve the silicon serial number.
212 * @rtc: pointer to the ds1685 rtc structure.
213 * @ssn: u8 array to hold the bits of the silicon serial number.
214 *
215 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
216 * first byte is the model number, the next six bytes are the serial number
217 * digits, and the final byte is a CRC check byte. Together, they form the
218 * silicon serial number.
219 *
220 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
221 * called first before calling this function, else data will be read out of
222 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
223 */
224static inline void
225ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
226{
227 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
228 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
229 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
230 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
231 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
232 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
233 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
234 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
235}
236/* ----------------------------------------------------------------------- */
237
238
239/* ----------------------------------------------------------------------- */
240/* Read/Set Time & Alarm functions */
241
242/**
243 * ds1685_rtc_read_time - reads the time registers.
244 * @dev: pointer to device structure.
245 * @tm: pointer to rtc_time structure.
246 */
247static int
248ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
249{
250 struct platform_device *pdev = to_platform_device(dev);
251 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
252 u8 ctrlb, century;
253 u8 seconds, minutes, hours, wday, mday, month, years;
254
255 /* Fetch the time info from the RTC registers. */
256 ds1685_rtc_begin_data_access(rtc);
257 seconds = rtc->read(rtc, RTC_SECS);
258 minutes = rtc->read(rtc, RTC_MINS);
259 hours = rtc->read(rtc, RTC_HRS);
260 wday = rtc->read(rtc, RTC_WDAY);
261 mday = rtc->read(rtc, RTC_MDAY);
262 month = rtc->read(rtc, RTC_MONTH);
263 years = rtc->read(rtc, RTC_YEAR);
264 century = rtc->read(rtc, RTC_CENTURY);
265 ctrlb = rtc->read(rtc, RTC_CTRL_B);
266 ds1685_rtc_end_data_access(rtc);
267
268 /* bcd2bin if needed, perform fixups, and store to rtc_time. */
269 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
270 RTC_YEAR_BIN_MASK);
271 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
272 RTC_CENTURY_MASK);
273 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
274 RTC_SECS_BIN_MASK);
275 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
276 RTC_MINS_BIN_MASK);
277 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
278 RTC_HRS_24_BIN_MASK);
279 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
280 RTC_WDAY_MASK) - 1);
281 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
282 RTC_MDAY_BIN_MASK);
283 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
284 RTC_MONTH_BIN_MASK) - 1);
285 tm->tm_year = ((years + (century * 100)) - 1900);
286 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
287 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
288
289 return rtc_valid_tm(tm);
290}
291
292/**
293 * ds1685_rtc_set_time - sets the time registers.
294 * @dev: pointer to device structure.
295 * @tm: pointer to rtc_time structure.
296 */
297static int
298ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
299{
300 struct platform_device *pdev = to_platform_device(dev);
301 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
302 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
303
304 /* Fetch the time info from rtc_time. */
305 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
306 RTC_SECS_BCD_MASK);
307 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
308 RTC_MINS_BCD_MASK);
309 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
310 RTC_HRS_24_BCD_MASK);
311 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
312 RTC_WDAY_MASK);
313 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
314 RTC_MDAY_BCD_MASK);
315 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
316 RTC_MONTH_BCD_MASK);
317 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
318 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
319 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
320 RTC_CENTURY_MASK, RTC_CENTURY_MASK);
321
322 /*
323 * Perform Sanity Checks:
324 * - Months: !> 12, Month Day != 0.
325 * - Month Day !> Max days in current month.
326 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
327 */
328 if ((tm->tm_mon > 11) || (mday == 0))
329 return -EDOM;
330
331 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
332 return -EDOM;
333
334 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
335 (tm->tm_sec >= 60) || (wday > 7))
336 return -EDOM;
337
338 /*
339 * Set the data mode to use and store the time values in the
340 * RTC registers.
341 */
342 ds1685_rtc_begin_data_access(rtc);
343 ctrlb = rtc->read(rtc, RTC_CTRL_B);
344 if (rtc->bcd_mode)
345 ctrlb &= ~(RTC_CTRL_B_DM);
346 else
347 ctrlb |= RTC_CTRL_B_DM;
348 rtc->write(rtc, RTC_CTRL_B, ctrlb);
349 rtc->write(rtc, RTC_SECS, seconds);
350 rtc->write(rtc, RTC_MINS, minutes);
351 rtc->write(rtc, RTC_HRS, hours);
352 rtc->write(rtc, RTC_WDAY, wday);
353 rtc->write(rtc, RTC_MDAY, mday);
354 rtc->write(rtc, RTC_MONTH, month);
355 rtc->write(rtc, RTC_YEAR, years);
356 rtc->write(rtc, RTC_CENTURY, century);
357 ds1685_rtc_end_data_access(rtc);
358
359 return 0;
360}
361
362/**
363 * ds1685_rtc_read_alarm - reads the alarm registers.
364 * @dev: pointer to device structure.
365 * @alrm: pointer to rtc_wkalrm structure.
366 *
367 * There are three primary alarm registers: seconds, minutes, and hours.
368 * A fourth alarm register for the month date is also available in bank1 for
369 * kickstart/wakeup features. The DS1685/DS1687 manual states that a
370 * "don't care" value ranging from 0xc0 to 0xff may be written into one or
371 * more of the three alarm bytes to act as a wildcard value. The fourth
372 * byte doesn't support a "don't care" value.
373 */
374static int
375ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
376{
377 struct platform_device *pdev = to_platform_device(dev);
378 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
379 u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
380
381 /* Fetch the alarm info from the RTC alarm registers. */
382 ds1685_rtc_begin_data_access(rtc);
383 seconds = rtc->read(rtc, RTC_SECS_ALARM);
384 minutes = rtc->read(rtc, RTC_MINS_ALARM);
385 hours = rtc->read(rtc, RTC_HRS_ALARM);
386 mday = rtc->read(rtc, RTC_MDAY_ALARM);
387 ctrlb = rtc->read(rtc, RTC_CTRL_B);
388 ctrlc = rtc->read(rtc, RTC_CTRL_C);
389 ds1685_rtc_end_data_access(rtc);
390
391 /* Check month date. */
392 if (!(mday >= 1) && (mday <= 31))
393 return -EDOM;
394
395 /*
396 * Check the three alarm bytes.
397 *
398 * The Linux RTC system doesn't support the "don't care" capability
399 * of this RTC chip. We check for it anyways in case support is
400 * added in the future.
401 */
402 if (unlikely(seconds >= 0xc0))
403 alrm->time.tm_sec = -1;
404 else
405 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
406 RTC_SECS_BCD_MASK,
407 RTC_SECS_BIN_MASK);
408
409 if (unlikely(minutes >= 0xc0))
410 alrm->time.tm_min = -1;
411 else
412 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
413 RTC_MINS_BCD_MASK,
414 RTC_MINS_BIN_MASK);
415
416 if (unlikely(hours >= 0xc0))
417 alrm->time.tm_hour = -1;
418 else
419 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
420 RTC_HRS_24_BCD_MASK,
421 RTC_HRS_24_BIN_MASK);
422
423 /* Write the data to rtc_wkalrm. */
424 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
425 RTC_MDAY_BIN_MASK);
426 alrm->time.tm_mon = -1;
427 alrm->time.tm_year = -1;
428 alrm->time.tm_wday = -1;
429 alrm->time.tm_yday = -1;
430 alrm->time.tm_isdst = -1;
431 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
432 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
433
434 return 0;
435}
436
437/**
438 * ds1685_rtc_set_alarm - sets the alarm in registers.
439 * @dev: pointer to device structure.
440 * @alrm: pointer to rtc_wkalrm structure.
441 */
442static int
443ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
444{
445 struct platform_device *pdev = to_platform_device(dev);
446 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
447 u8 ctrlb, seconds, minutes, hours, mday;
448
449 /* Fetch the alarm info and convert to BCD. */
450 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
451 RTC_SECS_BIN_MASK,
452 RTC_SECS_BCD_MASK);
453 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
454 RTC_MINS_BIN_MASK,
455 RTC_MINS_BCD_MASK);
456 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
457 RTC_HRS_24_BIN_MASK,
458 RTC_HRS_24_BCD_MASK);
459 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
460 RTC_MDAY_BIN_MASK,
461 RTC_MDAY_BCD_MASK);
462
463 /* Check the month date for validity. */
464 if (!(mday >= 1) && (mday <= 31))
465 return -EDOM;
466
467 /*
468 * Check the three alarm bytes.
469 *
470 * The Linux RTC system doesn't support the "don't care" capability
471 * of this RTC chip because rtc_valid_tm tries to validate every
472 * field, and we only support four fields. We put the support
473 * here anyways for the future.
474 */
475 if (unlikely(seconds >= 0xc0))
476 seconds = 0xff;
477
478 if (unlikely(minutes >= 0xc0))
479 minutes = 0xff;
480
481 if (unlikely(hours >= 0xc0))
482 hours = 0xff;
483
484 alrm->time.tm_mon = -1;
485 alrm->time.tm_year = -1;
486 alrm->time.tm_wday = -1;
487 alrm->time.tm_yday = -1;
488 alrm->time.tm_isdst = -1;
489
490 /* Disable the alarm interrupt first. */
491 ds1685_rtc_begin_data_access(rtc);
492 ctrlb = rtc->read(rtc, RTC_CTRL_B);
493 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
494
495 /* Read ctrlc to clear RTC_CTRL_C_AF. */
496 rtc->read(rtc, RTC_CTRL_C);
497
498 /*
499 * Set the data mode to use and store the time values in the
500 * RTC registers.
501 */
502 ctrlb = rtc->read(rtc, RTC_CTRL_B);
503 if (rtc->bcd_mode)
504 ctrlb &= ~(RTC_CTRL_B_DM);
505 else
506 ctrlb |= RTC_CTRL_B_DM;
507 rtc->write(rtc, RTC_CTRL_B, ctrlb);
508 rtc->write(rtc, RTC_SECS_ALARM, seconds);
509 rtc->write(rtc, RTC_MINS_ALARM, minutes);
510 rtc->write(rtc, RTC_HRS_ALARM, hours);
511 rtc->write(rtc, RTC_MDAY_ALARM, mday);
512
513 /* Re-enable the alarm if needed. */
514 if (alrm->enabled) {
515 ctrlb = rtc->read(rtc, RTC_CTRL_B);
516 ctrlb |= RTC_CTRL_B_AIE;
517 rtc->write(rtc, RTC_CTRL_B, ctrlb);
518 }
519
520 /* Done! */
521 ds1685_rtc_end_data_access(rtc);
522
523 return 0;
524}
525/* ----------------------------------------------------------------------- */
526
527
528/* ----------------------------------------------------------------------- */
529/* /dev/rtcX Interface functions */
530
531/**
532 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
533 * @dev: pointer to device structure.
534 * @enabled: flag indicating whether to enable or disable.
535 */
536static int
537ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
538{
539 struct ds1685_priv *rtc = dev_get_drvdata(dev);
540 unsigned long flags = 0;
541
542 /* Enable/disable the Alarm IRQ-Enable flag. */
543 spin_lock_irqsave(&rtc->lock, flags);
544
545 /* Flip the requisite interrupt-enable bit. */
546 if (enabled)
547 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
548 RTC_CTRL_B_AIE));
549 else
550 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
551 ~(RTC_CTRL_B_AIE)));
552
553 /* Read Control C to clear all the flag bits. */
554 rtc->read(rtc, RTC_CTRL_C);
555 spin_unlock_irqrestore(&rtc->lock, flags);
556
557 return 0;
558}
559/* ----------------------------------------------------------------------- */
560
561
562/* ----------------------------------------------------------------------- */
563/* IRQ handler & workqueue. */
564
565/**
566 * ds1685_rtc_irq_handler - IRQ handler.
567 * @irq: IRQ number.
568 * @dev_id: platform device pointer.
569 */
570static irqreturn_t
571ds1685_rtc_irq_handler(int irq, void *dev_id)
572{
573 struct platform_device *pdev = dev_id;
574 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
575 u8 ctrlb, ctrlc;
576 unsigned long events = 0;
577 u8 num_irqs = 0;
578
579 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
580 if (unlikely(!rtc))
581 return IRQ_HANDLED;
582
583 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
584 spin_lock(&rtc->lock);
585 ctrlb = rtc->read(rtc, RTC_CTRL_B);
586 ctrlc = rtc->read(rtc, RTC_CTRL_C);
587
588 /* Is the IRQF bit set? */
589 if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
590 /*
591 * We need to determine if it was one of the standard
592 * events: PF, AF, or UF. If so, we handle them and
593 * update the RTC core.
594 */
595 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
596 events = RTC_IRQF;
597
598 /* Check for a periodic interrupt. */
599 if ((ctrlb & RTC_CTRL_B_PIE) &&
600 (ctrlc & RTC_CTRL_C_PF)) {
601 events |= RTC_PF;
602 num_irqs++;
603 }
604
605 /* Check for an alarm interrupt. */
606 if ((ctrlb & RTC_CTRL_B_AIE) &&
607 (ctrlc & RTC_CTRL_C_AF)) {
608 events |= RTC_AF;
609 num_irqs++;
610 }
611
612 /* Check for an update interrupt. */
613 if ((ctrlb & RTC_CTRL_B_UIE) &&
614 (ctrlc & RTC_CTRL_C_UF)) {
615 events |= RTC_UF;
616 num_irqs++;
617 }
618
619 rtc_update_irq(rtc->dev, num_irqs, events);
620 } else {
621 /*
622 * One of the "extended" interrupts was received that
623 * is not recognized by the RTC core. These need to
624 * be handled in task context as they can call other
625 * functions and the time spent in irq context needs
626 * to be minimized. Schedule them into a workqueue
627 * and inform the RTC core that the IRQs were handled.
628 */
629 spin_unlock(&rtc->lock);
630 schedule_work(&rtc->work);
631 rtc_update_irq(rtc->dev, 0, 0);
632 return IRQ_HANDLED;
633 }
634 }
635 spin_unlock(&rtc->lock);
636
637 return events ? IRQ_HANDLED : IRQ_NONE;
638}
639
640/**
641 * ds1685_rtc_work_queue - work queue handler.
642 * @work: work_struct containing data to work on in task context.
643 */
644static void
645ds1685_rtc_work_queue(struct work_struct *work)
646{
647 struct ds1685_priv *rtc = container_of(work,
648 struct ds1685_priv, work);
649 struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
650 struct mutex *rtc_mutex = &rtc->dev->ops_lock;
651 u8 ctrl4a, ctrl4b;
652
653 mutex_lock(rtc_mutex);
654
655 ds1685_rtc_switch_to_bank1(rtc);
656 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
657 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
658
659 /*
660 * Check for a kickstart interrupt. With Vcc applied, this
661 * typically means that the power button was pressed, so we
662 * begin the shutdown sequence.
663 */
664 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
665 /* Briefly disable kickstarts to debounce button presses. */
666 rtc->write(rtc, RTC_EXT_CTRL_4B,
667 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
668 ~(RTC_CTRL_4B_KSE)));
669
670 /* Clear the kickstart flag. */
671 rtc->write(rtc, RTC_EXT_CTRL_4A,
672 (ctrl4a & ~(RTC_CTRL_4A_KF)));
673
674
675 /*
676 * Sleep 500ms before re-enabling kickstarts. This allows
677 * adequate time to avoid reading signal jitter as additional
678 * button presses.
679 */
680 msleep(500);
681 rtc->write(rtc, RTC_EXT_CTRL_4B,
682 (rtc->read(rtc, RTC_EXT_CTRL_4B) |
683 RTC_CTRL_4B_KSE));
684
685 /* Call the platform pre-poweroff function. Else, shutdown. */
686 if (rtc->prepare_poweroff != NULL)
687 rtc->prepare_poweroff();
688 else
689 ds1685_rtc_poweroff(pdev);
690 }
691
692 /*
693 * Check for a wake-up interrupt. With Vcc applied, this is
694 * essentially a second alarm interrupt, except it takes into
695 * account the 'date' register in bank1 in addition to the
696 * standard three alarm registers.
697 */
698 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
699 rtc->write(rtc, RTC_EXT_CTRL_4A,
700 (ctrl4a & ~(RTC_CTRL_4A_WF)));
701
702 /* Call the platform wake_alarm function if defined. */
703 if (rtc->wake_alarm != NULL)
704 rtc->wake_alarm();
705 else
706 dev_warn(&pdev->dev,
707 "Wake Alarm IRQ just occurred!\n");
708 }
709
710 /*
711 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
712 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
713 * each byte to a logic 1. This has no effect on any extended
714 * NV-SRAM that might be present, nor on the time/calendar/alarm
715 * registers. After a ram-clear is completed, there is a minimum
716 * recovery time of ~150ms in which all reads/writes are locked out.
717 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
718 * catch this scenario.
719 */
720 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
721 rtc->write(rtc, RTC_EXT_CTRL_4A,
722 (ctrl4a & ~(RTC_CTRL_4A_RF)));
723 msleep(150);
724
725 /* Call the platform post_ram_clear function if defined. */
726 if (rtc->post_ram_clear != NULL)
727 rtc->post_ram_clear();
728 else
729 dev_warn(&pdev->dev,
730 "RAM-Clear IRQ just occurred!\n");
731 }
732 ds1685_rtc_switch_to_bank0(rtc);
733
734 mutex_unlock(rtc_mutex);
735}
736/* ----------------------------------------------------------------------- */
737
738
739/* ----------------------------------------------------------------------- */
740/* ProcFS interface */
741
742#ifdef CONFIG_PROC_FS
743#define NUM_REGS 6 /* Num of control registers. */
744#define NUM_BITS 8 /* Num bits per register. */
745#define NUM_SPACES 4 /* Num spaces between each bit. */
746
747/*
748 * Periodic Interrupt Rates.
749 */
750static const char *ds1685_rtc_pirq_rate[16] = {
751 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
752 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
753 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
754};
755
756/*
757 * Square-Wave Output Frequencies.
758 */
759static const char *ds1685_rtc_sqw_freq[16] = {
760 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
761 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
762};
763
764#ifdef CONFIG_RTC_DS1685_PROC_REGS
765/**
766 * ds1685_rtc_print_regs - helper function to print register values.
767 * @hex: hex byte to convert into binary bits.
768 * @dest: destination char array.
769 *
770 * This is basically a hex->binary function, just with extra spacing between
771 * the digits. It only works on 1-byte values (8 bits).
772 */
773static char*
774ds1685_rtc_print_regs(u8 hex, char *dest)
775{
776 u32 i, j;
777 char *tmp = dest;
778
779 for (i = 0; i < NUM_BITS; i++) {
780 *tmp++ = ((hex & 0x80) != 0 ? '1' : '0');
781 for (j = 0; j < NUM_SPACES; j++)
782 *tmp++ = ' ';
783 hex <<= 1;
784 }
785 *tmp++ = '\0';
786
787 return dest;
788}
789#endif
790
791/**
792 * ds1685_rtc_proc - procfs access function.
793 * @dev: pointer to device structure.
794 * @seq: pointer to seq_file structure.
795 */
796static int
797ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
798{
799 struct platform_device *pdev = to_platform_device(dev);
800 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
801 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
802 char *model = '\0';
803#ifdef CONFIG_RTC_DS1685_PROC_REGS
804 char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1];
805#endif
806
807 /* Read all the relevant data from the control registers. */
808 ds1685_rtc_switch_to_bank1(rtc);
809 ds1685_rtc_get_ssn(rtc, ssn);
810 ctrla = rtc->read(rtc, RTC_CTRL_A);
811 ctrlb = rtc->read(rtc, RTC_CTRL_B);
812 ctrlc = rtc->read(rtc, RTC_CTRL_C);
813 ctrld = rtc->read(rtc, RTC_CTRL_D);
814 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
815 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
816 ds1685_rtc_switch_to_bank0(rtc);
817
818 /* Determine the RTC model. */
819 switch (ssn[0]) {
820 case RTC_MODEL_DS1685:
821 model = "DS1685/DS1687\0";
822 break;
823 case RTC_MODEL_DS1689:
824 model = "DS1689/DS1693\0";
825 break;
826 case RTC_MODEL_DS17285:
827 model = "DS17285/DS17287\0";
828 break;
829 case RTC_MODEL_DS17485:
830 model = "DS17485/DS17487\0";
831 break;
832 case RTC_MODEL_DS17885:
833 model = "DS17885/DS17887\0";
834 break;
835 default:
836 model = "Unknown\0";
837 break;
838 }
839
840 /* Print out the information. */
841 seq_printf(seq,
842 "Model\t\t: %s\n"
843 "Oscillator\t: %s\n"
844 "12/24hr\t\t: %s\n"
845 "DST\t\t: %s\n"
846 "Data mode\t: %s\n"
847 "Battery\t\t: %s\n"
848 "Aux batt\t: %s\n"
849 "Update IRQ\t: %s\n"
850 "Periodic IRQ\t: %s\n"
851 "Periodic Rate\t: %s\n"
852 "SQW Freq\t: %s\n"
853#ifdef CONFIG_RTC_DS1685_PROC_REGS
854 "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
855 "Register Status\t:\n"
856 " Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n"
857 "\t\t: %s\n"
858 " Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n"
859 "\t\t: %s\n"
860 " Ctrl C\t: IRQF PF AF UF --- --- --- ---\n"
861 "\t\t: %s\n"
862 " Ctrl D\t: VRT --- --- --- --- --- --- ---\n"
863 "\t\t: %s\n"
864#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
865 " Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n"
866#else
867 " Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n"
868#endif
869 "\t\t: %s\n"
870 " Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n"
871 "\t\t: %s\n",
872#else
873 "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
874#endif
875 model,
876 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
877 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
878 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
879 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
880 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
881 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
882 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
883 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
884 (!(ctrl4b & RTC_CTRL_4B_E32K) ?
885 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
886 (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
887 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
888#ifdef CONFIG_RTC_DS1685_PROC_REGS
889 ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7],
890 ds1685_rtc_print_regs(ctrla, bits[0]),
891 ds1685_rtc_print_regs(ctrlb, bits[1]),
892 ds1685_rtc_print_regs(ctrlc, bits[2]),
893 ds1685_rtc_print_regs(ctrld, bits[3]),
894 ds1685_rtc_print_regs(ctrl4a, bits[4]),
895 ds1685_rtc_print_regs(ctrl4b, bits[5]));
896#else
897 ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7]);
898#endif
899 return 0;
900}
901#else
902#define ds1685_rtc_proc NULL
903#endif /* CONFIG_PROC_FS */
904/* ----------------------------------------------------------------------- */
905
906
907/* ----------------------------------------------------------------------- */
908/* RTC Class operations */
909
910static const struct rtc_class_ops
911ds1685_rtc_ops = {
912 .proc = ds1685_rtc_proc,
913 .read_time = ds1685_rtc_read_time,
914 .set_time = ds1685_rtc_set_time,
915 .read_alarm = ds1685_rtc_read_alarm,
916 .set_alarm = ds1685_rtc_set_alarm,
917 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
918};
919/* ----------------------------------------------------------------------- */
920
921
922/* ----------------------------------------------------------------------- */
923/* SysFS interface */
924
925#ifdef CONFIG_SYSFS
926/**
927 * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs.
928 * @file: pointer to file structure.
929 * @kobj: pointer to kobject structure.
930 * @bin_attr: pointer to bin_attribute structure.
931 * @buf: pointer to char array to hold the output.
932 * @pos: current file position pointer.
933 * @size: size of the data to read.
934 */
935static ssize_t
936ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj,
937 struct bin_attribute *bin_attr, char *buf,
938 loff_t pos, size_t size)
939{
940 struct platform_device *pdev =
941 to_platform_device(container_of(kobj, struct device, kobj));
942 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
943 ssize_t count;
944 unsigned long flags = 0;
945
946 spin_lock_irqsave(&rtc->lock, flags);
947 ds1685_rtc_switch_to_bank0(rtc);
948
949 /* Read NVRAM in time and bank0 registers. */
950 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
951 count++, size--) {
952 if (count < NVRAM_SZ_TIME)
953 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
954 else
955 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
956 }
957
958#ifndef CONFIG_RTC_DRV_DS1689
959 if (size > 0) {
960 ds1685_rtc_switch_to_bank1(rtc);
961
962#ifndef CONFIG_RTC_DRV_DS1685
963 /* Enable burst-mode on DS17x85/DS17x87 */
964 rtc->write(rtc, RTC_EXT_CTRL_4A,
965 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
966 RTC_CTRL_4A_BME));
967
968 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
969 * reading with burst-mode */
970 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
971 (pos - NVRAM_TOTAL_SZ_BANK0));
972#endif
973
974 /* Read NVRAM in bank1 registers. */
975 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
976 count++, size--) {
977#ifdef CONFIG_RTC_DRV_DS1685
978 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
979 * before each read. */
980 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
981 (pos - NVRAM_TOTAL_SZ_BANK0));
982#endif
983 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
984 pos++;
985 }
986
987#ifndef CONFIG_RTC_DRV_DS1685
988 /* Disable burst-mode on DS17x85/DS17x87 */
989 rtc->write(rtc, RTC_EXT_CTRL_4A,
990 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
991 ~(RTC_CTRL_4A_BME)));
992#endif
993 ds1685_rtc_switch_to_bank0(rtc);
994 }
995#endif /* !CONFIG_RTC_DRV_DS1689 */
996 spin_unlock_irqrestore(&rtc->lock, flags);
997
998 /*
999 * XXX: Bug? this appears to cause the function to get executed
1000 * several times in succession. But it's the only way to actually get
1001 * data written out to a file.
1002 */
1003 return count;
1004}
1005
1006/**
1007 * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs.
1008 * @file: pointer to file structure.
1009 * @kobj: pointer to kobject structure.
1010 * @bin_attr: pointer to bin_attribute structure.
1011 * @buf: pointer to char array to hold the input.
1012 * @pos: current file position pointer.
1013 * @size: size of the data to write.
1014 */
1015static ssize_t
1016ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj,
1017 struct bin_attribute *bin_attr, char *buf,
1018 loff_t pos, size_t size)
1019{
1020 struct platform_device *pdev =
1021 to_platform_device(container_of(kobj, struct device, kobj));
1022 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1023 ssize_t count;
1024 unsigned long flags = 0;
1025
1026 spin_lock_irqsave(&rtc->lock, flags);
1027 ds1685_rtc_switch_to_bank0(rtc);
1028
1029 /* Write NVRAM in time and bank0 registers. */
1030 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
1031 count++, size--)
1032 if (count < NVRAM_SZ_TIME)
1033 rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
1034 *buf++);
1035 else
1036 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
1037
1038#ifndef CONFIG_RTC_DRV_DS1689
1039 if (size > 0) {
1040 ds1685_rtc_switch_to_bank1(rtc);
1041
1042#ifndef CONFIG_RTC_DRV_DS1685
1043 /* Enable burst-mode on DS17x85/DS17x87 */
1044 rtc->write(rtc, RTC_EXT_CTRL_4A,
1045 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
1046 RTC_CTRL_4A_BME));
1047
1048 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
1049 * writing with burst-mode */
1050 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
1051 (pos - NVRAM_TOTAL_SZ_BANK0));
1052#endif
1053
1054 /* Write NVRAM in bank1 registers. */
1055 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
1056 count++, size--) {
1057#ifdef CONFIG_RTC_DRV_DS1685
1058 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
1059 * before each read. */
1060 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
1061 (pos - NVRAM_TOTAL_SZ_BANK0));
1062#endif
1063 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
1064 pos++;
1065 }
1066
1067#ifndef CONFIG_RTC_DRV_DS1685
1068 /* Disable burst-mode on DS17x85/DS17x87 */
1069 rtc->write(rtc, RTC_EXT_CTRL_4A,
1070 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1071 ~(RTC_CTRL_4A_BME)));
1072#endif
1073 ds1685_rtc_switch_to_bank0(rtc);
1074 }
1075#endif /* !CONFIG_RTC_DRV_DS1689 */
1076 spin_unlock_irqrestore(&rtc->lock, flags);
1077
1078 return count;
1079}
1080
1081/**
1082 * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram.
1083 * @attr: nvram attributes.
1084 * @read: nvram read function.
1085 * @write: nvram write function.
1086 * @size: nvram total size (bank0 + extended).
1087 */
1088static struct bin_attribute
1089ds1685_rtc_sysfs_nvram_attr = {
1090 .attr = {
1091 .name = "nvram",
1092 .mode = S_IRUGO | S_IWUSR,
1093 },
1094 .read = ds1685_rtc_sysfs_nvram_read,
1095 .write = ds1685_rtc_sysfs_nvram_write,
1096 .size = NVRAM_TOTAL_SZ
1097};
1098
1099/**
1100 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
1101 * @dev: pointer to device structure.
1102 * @attr: pointer to device_attribute structure.
1103 * @buf: pointer to char array to hold the output.
1104 */
1105static ssize_t
1106ds1685_rtc_sysfs_battery_show(struct device *dev,
1107 struct device_attribute *attr, char *buf)
1108{
1109 struct platform_device *pdev = to_platform_device(dev);
1110 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1111 u8 ctrld;
1112
1113 ctrld = rtc->read(rtc, RTC_CTRL_D);
1114
1115 return snprintf(buf, 13, "%s\n",
1116 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
1117}
1118static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
1119
1120/**
1121 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1122 * @dev: pointer to device structure.
1123 * @attr: pointer to device_attribute structure.
1124 * @buf: pointer to char array to hold the output.
1125 */
1126static ssize_t
1127ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1128 struct device_attribute *attr, char *buf)
1129{
1130 struct platform_device *pdev = to_platform_device(dev);
1131 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1132 u8 ctrl4a;
1133
1134 ds1685_rtc_switch_to_bank1(rtc);
1135 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1136 ds1685_rtc_switch_to_bank0(rtc);
1137
1138 return snprintf(buf, 13, "%s\n",
1139 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1140}
1141static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1142
1143/**
1144 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1145 * @dev: pointer to device structure.
1146 * @attr: pointer to device_attribute structure.
1147 * @buf: pointer to char array to hold the output.
1148 */
1149static ssize_t
1150ds1685_rtc_sysfs_serial_show(struct device *dev,
1151 struct device_attribute *attr, char *buf)
1152{
1153 struct platform_device *pdev = to_platform_device(dev);
1154 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1155 u8 ssn[8];
1156
1157 ds1685_rtc_switch_to_bank1(rtc);
1158 ds1685_rtc_get_ssn(rtc, ssn);
1159 ds1685_rtc_switch_to_bank0(rtc);
1160
1161 return snprintf(buf, 24, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
1162 ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5],
1163 ssn[6], ssn[7]);
1164
1165 return 0;
1166}
1167static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1168
1169/**
1170 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1171 */
1172static struct attribute*
1173ds1685_rtc_sysfs_misc_attrs[] = {
1174 &dev_attr_battery.attr,
1175 &dev_attr_auxbatt.attr,
1176 &dev_attr_serial.attr,
1177 NULL,
1178};
1179
1180/**
1181 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1182 */
1183static const struct attribute_group
1184ds1685_rtc_sysfs_misc_grp = {
1185 .name = "misc",
1186 .attrs = ds1685_rtc_sysfs_misc_attrs,
1187};
1188
1189#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1190/**
1191 * struct ds1685_rtc_ctrl_regs.
1192 * @name: char pointer for the bit name.
1193 * @reg: control register the bit is in.
1194 * @bit: the bit's offset in the register.
1195 */
1196struct ds1685_rtc_ctrl_regs {
1197 const char *name;
1198 const u8 reg;
1199 const u8 bit;
1200};
1201
1202/*
1203 * Ctrl register bit lookup table.
1204 */
1205static const struct ds1685_rtc_ctrl_regs
1206ds1685_ctrl_regs_table[] = {
1207 { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP },
1208 { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 },
1209 { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 },
1210 { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 },
1211 { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 },
1212 { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 },
1213 { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 },
1214 { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 },
1215 { "set", RTC_CTRL_B, RTC_CTRL_B_SET },
1216 { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE },
1217 { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE },
1218 { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE },
1219 { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE },
1220 { "dm", RTC_CTRL_B, RTC_CTRL_B_DM },
1221 { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 },
1222 { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE },
1223 { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF },
1224 { "pf", RTC_CTRL_C, RTC_CTRL_C_PF },
1225 { "af", RTC_CTRL_C, RTC_CTRL_C_AF },
1226 { "uf", RTC_CTRL_C, RTC_CTRL_C_UF },
1227 { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT },
1228 { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 },
1229 { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR },
1230 { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB },
1231 { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF },
1232 { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF },
1233 { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF },
1234#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1235 { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME },
1236#endif
1237 { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE },
1238 { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K },
1239 { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS },
1240 { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE },
1241 { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS },
1242 { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE },
1243 { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE },
1244 { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE },
1245 { NULL, 0, 0 },
1246};
1247
1248/**
1249 * ds1685_rtc_sysfs_ctrl_regs_lookup - ctrl register bit lookup function.
1250 * @name: ctrl register bit to look up in ds1685_ctrl_regs_table.
1251 */
1252static const struct ds1685_rtc_ctrl_regs*
1253ds1685_rtc_sysfs_ctrl_regs_lookup(const char *name)
1254{
1255 const struct ds1685_rtc_ctrl_regs *p = ds1685_ctrl_regs_table;
1256
1257 for (; p->name != NULL; ++p)
1258 if (strcmp(p->name, name) == 0)
1259 return p;
1260
1261 return NULL;
1262}
1263
1264/**
1265 * ds1685_rtc_sysfs_ctrl_regs_show - reads a ctrl register bit via sysfs.
1266 * @dev: pointer to device structure.
1267 * @attr: pointer to device_attribute structure.
1268 * @buf: pointer to char array to hold the output.
1269 */
1270static ssize_t
1271ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev,
1272 struct device_attribute *attr, char *buf)
1273{
1274 u8 tmp;
1275 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1276 const struct ds1685_rtc_ctrl_regs *reg_info =
1277 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name);
1278
1279 /* Make sure we actually matched something. */
1280 if (!reg_info)
1281 return -EINVAL;
1282
1283 /* No spinlock during a read -- mutex is already held. */
1284 ds1685_rtc_switch_to_bank1(rtc);
1285 tmp = rtc->read(rtc, reg_info->reg) & reg_info->bit;
1286 ds1685_rtc_switch_to_bank0(rtc);
1287
1288 return snprintf(buf, 2, "%d\n", (tmp ? 1 : 0));
1289}
1290
1291/**
1292 * ds1685_rtc_sysfs_ctrl_regs_store - writes a ctrl register bit via sysfs.
1293 * @dev: pointer to device structure.
1294 * @attr: pointer to device_attribute structure.
1295 * @buf: pointer to char array to hold the output.
1296 * @count: number of bytes written.
1297 */
1298static ssize_t
1299ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev,
1300 struct device_attribute *attr,
1301 const char *buf, size_t count)
1302{
1303 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1304 u8 reg = 0, bit = 0, tmp;
1305 unsigned long flags = 0;
1306 long int val = 0;
1307 const struct ds1685_rtc_ctrl_regs *reg_info =
1308 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name);
1309
1310 /* We only accept numbers. */
1311 if (kstrtol(buf, 10, &val) < 0)
1312 return -EINVAL;
1313
1314 /* bits are binary, 0 or 1 only. */
1315 if ((val != 0) && (val != 1))
1316 return -ERANGE;
1317
1318 /* Make sure we actually matched something. */
1319 if (!reg_info)
1320 return -EINVAL;
1321
1322 reg = reg_info->reg;
1323 bit = reg_info->bit;
1324
1325 /* Safe to spinlock during a write. */
1326 ds1685_rtc_begin_ctrl_access(rtc, flags);
1327 tmp = rtc->read(rtc, reg);
1328 rtc->write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit))));
1329 ds1685_rtc_end_ctrl_access(rtc, flags);
1330
1331 return count;
1332}
1333
1334/**
1335 * DS1685_RTC_SYSFS_CTRL_REG_RO - device_attribute for read-only register bit.
1336 * @bit: bit to read.
1337 */
1338#define DS1685_RTC_SYSFS_CTRL_REG_RO(bit) \
1339 static DEVICE_ATTR(bit, S_IRUGO, \
1340 ds1685_rtc_sysfs_ctrl_regs_show, NULL)
1341
1342/**
1343 * DS1685_RTC_SYSFS_CTRL_REG_RW - device_attribute for read-write register bit.
1344 * @bit: bit to read or write.
1345 */
1346#define DS1685_RTC_SYSFS_CTRL_REG_RW(bit) \
1347 static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \
1348 ds1685_rtc_sysfs_ctrl_regs_show, \
1349 ds1685_rtc_sysfs_ctrl_regs_store)
1350
1351/*
1352 * Control Register A bits.
1353 */
1354DS1685_RTC_SYSFS_CTRL_REG_RO(uip);
1355DS1685_RTC_SYSFS_CTRL_REG_RW(dv2);
1356DS1685_RTC_SYSFS_CTRL_REG_RW(dv1);
1357DS1685_RTC_SYSFS_CTRL_REG_RO(dv0);
1358DS1685_RTC_SYSFS_CTRL_REG_RW(rs3);
1359DS1685_RTC_SYSFS_CTRL_REG_RW(rs2);
1360DS1685_RTC_SYSFS_CTRL_REG_RW(rs1);
1361DS1685_RTC_SYSFS_CTRL_REG_RW(rs0);
1362
1363static struct attribute*
1364ds1685_rtc_sysfs_ctrla_attrs[] = {
1365 &dev_attr_uip.attr,
1366 &dev_attr_dv2.attr,
1367 &dev_attr_dv1.attr,
1368 &dev_attr_dv0.attr,
1369 &dev_attr_rs3.attr,
1370 &dev_attr_rs2.attr,
1371 &dev_attr_rs1.attr,
1372 &dev_attr_rs0.attr,
1373 NULL,
1374};
1375
1376static const struct attribute_group
1377ds1685_rtc_sysfs_ctrla_grp = {
1378 .name = "ctrla",
1379 .attrs = ds1685_rtc_sysfs_ctrla_attrs,
1380};
1381
1382
1383/*
1384 * Control Register B bits.
1385 */
1386DS1685_RTC_SYSFS_CTRL_REG_RO(set);
1387DS1685_RTC_SYSFS_CTRL_REG_RW(pie);
1388DS1685_RTC_SYSFS_CTRL_REG_RW(aie);
1389DS1685_RTC_SYSFS_CTRL_REG_RW(uie);
1390DS1685_RTC_SYSFS_CTRL_REG_RW(sqwe);
1391DS1685_RTC_SYSFS_CTRL_REG_RO(dm);
1392DS1685_RTC_SYSFS_CTRL_REG_RO(2412);
1393DS1685_RTC_SYSFS_CTRL_REG_RO(dse);
1394
1395static struct attribute*
1396ds1685_rtc_sysfs_ctrlb_attrs[] = {
1397 &dev_attr_set.attr,
1398 &dev_attr_pie.attr,
1399 &dev_attr_aie.attr,
1400 &dev_attr_uie.attr,
1401 &dev_attr_sqwe.attr,
1402 &dev_attr_dm.attr,
1403 &dev_attr_2412.attr,
1404 &dev_attr_dse.attr,
1405 NULL,
1406};
1407
1408static const struct attribute_group
1409ds1685_rtc_sysfs_ctrlb_grp = {
1410 .name = "ctrlb",
1411 .attrs = ds1685_rtc_sysfs_ctrlb_attrs,
1412};
1413
1414/*
1415 * Control Register C bits.
1416 *
1417 * Reading Control C clears these bits! Reading them individually can
1418 * possibly cause an interrupt to be missed. Use the /proc interface
1419 * to see all the bits in this register simultaneously.
1420 */
1421DS1685_RTC_SYSFS_CTRL_REG_RO(irqf);
1422DS1685_RTC_SYSFS_CTRL_REG_RO(pf);
1423DS1685_RTC_SYSFS_CTRL_REG_RO(af);
1424DS1685_RTC_SYSFS_CTRL_REG_RO(uf);
1425
1426static struct attribute*
1427ds1685_rtc_sysfs_ctrlc_attrs[] = {
1428 &dev_attr_irqf.attr,
1429 &dev_attr_pf.attr,
1430 &dev_attr_af.attr,
1431 &dev_attr_uf.attr,
1432 NULL,
1433};
1434
1435static const struct attribute_group
1436ds1685_rtc_sysfs_ctrlc_grp = {
1437 .name = "ctrlc",
1438 .attrs = ds1685_rtc_sysfs_ctrlc_attrs,
1439};
1440
1441/*
1442 * Control Register D bits.
1443 */
1444DS1685_RTC_SYSFS_CTRL_REG_RO(vrt);
1445
1446static struct attribute*
1447ds1685_rtc_sysfs_ctrld_attrs[] = {
1448 &dev_attr_vrt.attr,
1449 NULL,
1450};
1451
1452static const struct attribute_group
1453ds1685_rtc_sysfs_ctrld_grp = {
1454 .name = "ctrld",
1455 .attrs = ds1685_rtc_sysfs_ctrld_attrs,
1456};
1457
1458/*
1459 * Control Register 4A bits.
1460 */
1461DS1685_RTC_SYSFS_CTRL_REG_RO(vrt2);
1462DS1685_RTC_SYSFS_CTRL_REG_RO(incr);
1463DS1685_RTC_SYSFS_CTRL_REG_RW(pab);
1464DS1685_RTC_SYSFS_CTRL_REG_RW(rf);
1465DS1685_RTC_SYSFS_CTRL_REG_RW(wf);
1466DS1685_RTC_SYSFS_CTRL_REG_RW(kf);
1467#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1468DS1685_RTC_SYSFS_CTRL_REG_RO(bme);
1469#endif
1470
1471static struct attribute*
1472ds1685_rtc_sysfs_ctrl4a_attrs[] = {
1473 &dev_attr_vrt2.attr,
1474 &dev_attr_incr.attr,
1475 &dev_attr_pab.attr,
1476 &dev_attr_rf.attr,
1477 &dev_attr_wf.attr,
1478 &dev_attr_kf.attr,
1479#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1480 &dev_attr_bme.attr,
1481#endif
1482 NULL,
1483};
1484
1485static const struct attribute_group
1486ds1685_rtc_sysfs_ctrl4a_grp = {
1487 .name = "ctrl4a",
1488 .attrs = ds1685_rtc_sysfs_ctrl4a_attrs,
1489};
1490
1491/*
1492 * Control Register 4B bits.
1493 */
1494DS1685_RTC_SYSFS_CTRL_REG_RW(abe);
1495DS1685_RTC_SYSFS_CTRL_REG_RW(e32k);
1496DS1685_RTC_SYSFS_CTRL_REG_RO(cs);
1497DS1685_RTC_SYSFS_CTRL_REG_RW(rce);
1498DS1685_RTC_SYSFS_CTRL_REG_RW(prs);
1499DS1685_RTC_SYSFS_CTRL_REG_RW(rie);
1500DS1685_RTC_SYSFS_CTRL_REG_RW(wie);
1501DS1685_RTC_SYSFS_CTRL_REG_RW(kse);
1502
1503static struct attribute*
1504ds1685_rtc_sysfs_ctrl4b_attrs[] = {
1505 &dev_attr_abe.attr,
1506 &dev_attr_e32k.attr,
1507 &dev_attr_cs.attr,
1508 &dev_attr_rce.attr,
1509 &dev_attr_prs.attr,
1510 &dev_attr_rie.attr,
1511 &dev_attr_wie.attr,
1512 &dev_attr_kse.attr,
1513 NULL,
1514};
1515
1516static const struct attribute_group
1517ds1685_rtc_sysfs_ctrl4b_grp = {
1518 .name = "ctrl4b",
1519 .attrs = ds1685_rtc_sysfs_ctrl4b_attrs,
1520};
1521
1522
1523/**
1524 * struct ds1685_rtc_ctrl_regs.
1525 * @name: char pointer for the bit name.
1526 * @reg: control register the bit is in.
1527 * @bit: the bit's offset in the register.
1528 */
1529struct ds1685_rtc_time_regs {
1530 const char *name;
1531 const u8 reg;
1532 const u8 mask;
1533 const u8 min;
1534 const u8 max;
1535};
1536
1537/*
1538 * Time/Date register lookup tables.
1539 */
1540static const struct ds1685_rtc_time_regs
1541ds1685_time_regs_bcd_table[] = {
1542 { "seconds", RTC_SECS, RTC_SECS_BCD_MASK, 0, 59 },
1543 { "minutes", RTC_MINS, RTC_MINS_BCD_MASK, 0, 59 },
1544 { "hours", RTC_HRS, RTC_HRS_24_BCD_MASK, 0, 23 },
1545 { "wday", RTC_WDAY, RTC_WDAY_MASK, 1, 7 },
1546 { "mday", RTC_MDAY, RTC_MDAY_BCD_MASK, 1, 31 },
1547 { "month", RTC_MONTH, RTC_MONTH_BCD_MASK, 1, 12 },
1548 { "year", RTC_YEAR, RTC_YEAR_BCD_MASK, 0, 99 },
1549 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0, 99 },
1550 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BCD_MASK, 0, 59 },
1551 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BCD_MASK, 0, 59 },
1552 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BCD_MASK, 0, 23 },
1553 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 1, 31 },
1554 { NULL, 0, 0, 0, 0 },
1555};
1556
1557static const struct ds1685_rtc_time_regs
1558ds1685_time_regs_bin_table[] = {
1559 { "seconds", RTC_SECS, RTC_SECS_BIN_MASK, 0x00, 0x3b },
1560 { "minutes", RTC_MINS, RTC_MINS_BIN_MASK, 0x00, 0x3b },
1561 { "hours", RTC_HRS, RTC_HRS_24_BIN_MASK, 0x00, 0x17 },
1562 { "wday", RTC_WDAY, RTC_WDAY_MASK, 0x01, 0x07 },
1563 { "mday", RTC_MDAY, RTC_MDAY_BIN_MASK, 0x01, 0x1f },
1564 { "month", RTC_MONTH, RTC_MONTH_BIN_MASK, 0x01, 0x0c },
1565 { "year", RTC_YEAR, RTC_YEAR_BIN_MASK, 0x00, 0x63 },
1566 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0x00, 0x63 },
1567 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BIN_MASK, 0x00, 0x3b },
1568 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BIN_MASK, 0x00, 0x3b },
1569 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BIN_MASK, 0x00, 0x17 },
1570 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 0x01, 0x1f },
1571 { NULL, 0, 0, 0x00, 0x00 },
1572};
1573
1574/**
1575 * ds1685_rtc_sysfs_time_regs_bcd_lookup - time/date reg bit lookup function.
1576 * @name: register bit to look up in ds1685_time_regs_bcd_table.
1577 */
1578static const struct ds1685_rtc_time_regs*
1579ds1685_rtc_sysfs_time_regs_lookup(const char *name, bool bcd_mode)
1580{
1581 const struct ds1685_rtc_time_regs *p;
1582
1583 if (bcd_mode)
1584 p = ds1685_time_regs_bcd_table;
1585 else
1586 p = ds1685_time_regs_bin_table;
1587
1588 for (; p->name != NULL; ++p)
1589 if (strcmp(p->name, name) == 0)
1590 return p;
1591
1592 return NULL;
1593}
1594
1595/**
1596 * ds1685_rtc_sysfs_time_regs_show - reads a time/date register via sysfs.
1597 * @dev: pointer to device structure.
1598 * @attr: pointer to device_attribute structure.
1599 * @buf: pointer to char array to hold the output.
1600 */
1601static ssize_t
1602ds1685_rtc_sysfs_time_regs_show(struct device *dev,
1603 struct device_attribute *attr, char *buf)
1604{
1605 u8 tmp;
1606 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1607 const struct ds1685_rtc_time_regs *bcd_reg_info =
1608 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true);
1609 const struct ds1685_rtc_time_regs *bin_reg_info =
1610 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1611
1612 /* Make sure we actually matched something. */
1613 if (!bcd_reg_info || !bin_reg_info)
1614 return -EINVAL;
1615
1616 /* bcd_reg_info->reg == bin_reg_info->reg. */
1617 ds1685_rtc_begin_data_access(rtc);
1618 tmp = rtc->read(rtc, bcd_reg_info->reg);
1619 ds1685_rtc_end_data_access(rtc);
1620
1621 tmp = ds1685_rtc_bcd2bin(rtc, tmp, bcd_reg_info->mask,
1622 bin_reg_info->mask);
1623
1624 return snprintf(buf, 4, "%d\n", tmp);
1625}
1626
1627/**
1628 * ds1685_rtc_sysfs_time_regs_store - writes a time/date register via sysfs.
1629 * @dev: pointer to device structure.
1630 * @attr: pointer to device_attribute structure.
1631 * @buf: pointer to char array to hold the output.
1632 * @count: number of bytes written.
1633 */
1634static ssize_t
1635ds1685_rtc_sysfs_time_regs_store(struct device *dev,
1636 struct device_attribute *attr,
1637 const char *buf, size_t count)
1638{
1639 long int val = 0;
1640 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1641 const struct ds1685_rtc_time_regs *bcd_reg_info =
1642 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true);
1643 const struct ds1685_rtc_time_regs *bin_reg_info =
1644 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1645
1646 /* We only accept numbers. */
1647 if (kstrtol(buf, 10, &val) < 0)
1648 return -EINVAL;
1649
1650 /* Make sure we actually matched something. */
1651 if (!bcd_reg_info || !bin_reg_info)
1652 return -EINVAL;
1653
1654 /* Check for a valid range. */
1655 if (rtc->bcd_mode) {
1656 if ((val < bcd_reg_info->min) || (val > bcd_reg_info->max))
1657 return -ERANGE;
1658 } else {
1659 if ((val < bin_reg_info->min) || (val > bin_reg_info->max))
1660 return -ERANGE;
1661 }
1662
1663 val = ds1685_rtc_bin2bcd(rtc, val, bin_reg_info->mask,
1664 bcd_reg_info->mask);
1665
1666 /* bcd_reg_info->reg == bin_reg_info->reg. */
1667 ds1685_rtc_begin_data_access(rtc);
1668 rtc->write(rtc, bcd_reg_info->reg, val);
1669 ds1685_rtc_end_data_access(rtc);
1670
1671 return count;
1672}
1673
1674/**
1675 * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write time register.
1676 * @reg: time/date register to read or write.
1677 */
1678#define DS1685_RTC_SYSFS_TIME_REG_RW(reg) \
1679 static DEVICE_ATTR(reg, S_IRUGO | S_IWUSR, \
1680 ds1685_rtc_sysfs_time_regs_show, \
1681 ds1685_rtc_sysfs_time_regs_store)
1682
1683/*
1684 * Time/Date Register bits.
1685 */
1686DS1685_RTC_SYSFS_TIME_REG_RW(seconds);
1687DS1685_RTC_SYSFS_TIME_REG_RW(minutes);
1688DS1685_RTC_SYSFS_TIME_REG_RW(hours);
1689DS1685_RTC_SYSFS_TIME_REG_RW(wday);
1690DS1685_RTC_SYSFS_TIME_REG_RW(mday);
1691DS1685_RTC_SYSFS_TIME_REG_RW(month);
1692DS1685_RTC_SYSFS_TIME_REG_RW(year);
1693DS1685_RTC_SYSFS_TIME_REG_RW(century);
1694DS1685_RTC_SYSFS_TIME_REG_RW(alarm_seconds);
1695DS1685_RTC_SYSFS_TIME_REG_RW(alarm_minutes);
1696DS1685_RTC_SYSFS_TIME_REG_RW(alarm_hours);
1697DS1685_RTC_SYSFS_TIME_REG_RW(alarm_mday);
1698
1699static struct attribute*
1700ds1685_rtc_sysfs_time_attrs[] = {
1701 &dev_attr_seconds.attr,
1702 &dev_attr_minutes.attr,
1703 &dev_attr_hours.attr,
1704 &dev_attr_wday.attr,
1705 &dev_attr_mday.attr,
1706 &dev_attr_month.attr,
1707 &dev_attr_year.attr,
1708 &dev_attr_century.attr,
1709 NULL,
1710};
1711
1712static const struct attribute_group
1713ds1685_rtc_sysfs_time_grp = {
1714 .name = "datetime",
1715 .attrs = ds1685_rtc_sysfs_time_attrs,
1716};
1717
1718static struct attribute*
1719ds1685_rtc_sysfs_alarm_attrs[] = {
1720 &dev_attr_alarm_seconds.attr,
1721 &dev_attr_alarm_minutes.attr,
1722 &dev_attr_alarm_hours.attr,
1723 &dev_attr_alarm_mday.attr,
1724 NULL,
1725};
1726
1727static const struct attribute_group
1728ds1685_rtc_sysfs_alarm_grp = {
1729 .name = "alarm",
1730 .attrs = ds1685_rtc_sysfs_alarm_attrs,
1731};
1732#endif /* CONFIG_RTC_DS1685_SYSFS_REGS */
1733
1734
1735/**
1736 * ds1685_rtc_sysfs_register - register sysfs files.
1737 * @dev: pointer to device structure.
1738 */
1739static int
1740ds1685_rtc_sysfs_register(struct device *dev)
1741{
1742 int ret = 0;
1743
1744 sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr);
1745 ret = sysfs_create_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1746 if (ret)
1747 return ret;
1748
1749 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1750 if (ret)
1751 return ret;
1752
1753#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1754 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp);
1755 if (ret)
1756 return ret;
1757
1758 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp);
1759 if (ret)
1760 return ret;
1761
1762 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp);
1763 if (ret)
1764 return ret;
1765
1766 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp);
1767 if (ret)
1768 return ret;
1769
1770 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp);
1771 if (ret)
1772 return ret;
1773
1774 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp);
1775 if (ret)
1776 return ret;
1777
1778 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp);
1779 if (ret)
1780 return ret;
1781
1782 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp);
1783 if (ret)
1784 return ret;
1785#endif
1786 return 0;
1787}
1788
1789/**
1790 * ds1685_rtc_sysfs_unregister - unregister sysfs files.
1791 * @dev: pointer to device structure.
1792 */
1793static int
1794ds1685_rtc_sysfs_unregister(struct device *dev)
1795{
1796 sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1797 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1798
1799#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1800 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp);
1801 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp);
1802 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp);
1803 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp);
1804 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp);
1805 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp);
1806 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp);
1807 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp);
1808#endif
1809
1810 return 0;
1811}
1812#endif /* CONFIG_SYSFS */
1813
1814
1815
1816/* ----------------------------------------------------------------------- */
1817/* Driver Probe/Removal */
1818
1819/**
1820 * ds1685_rtc_probe - initializes rtc driver.
1821 * @pdev: pointer to platform_device structure.
1822 */
1823static int
1824ds1685_rtc_probe(struct platform_device *pdev)
1825{
1826 struct rtc_device *rtc_dev;
1827 struct resource *res;
1828 struct ds1685_priv *rtc;
1829 struct ds1685_rtc_platform_data *pdata;
1830 u8 ctrla, ctrlb, hours;
1831 unsigned char am_pm;
1832 int ret = 0;
1833
1834 /* Get the platform data. */
1835 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1836 if (!pdata)
1837 return -ENODEV;
1838
1839 /* Allocate memory for the rtc device. */
1840 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1841 if (!rtc)
1842 return -ENOMEM;
1843
1844 /*
1845 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all
1846 * platforms put the RTC in an easy-access place. Like the SGI Octane,
1847 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip
1848 * that sits behind the IOC3 PCI metadevice.
1849 */
1850 if (pdata->alloc_io_resources) {
1851 /* Get the platform resources. */
1852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1853 if (!res)
1854 return -ENXIO;
1855 rtc->size = resource_size(res);
1856
1857 /* Request a memory region. */
1858 /* XXX: mmio-only for now. */
1859 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size,
1860 pdev->name))
1861 return -EBUSY;
1862
1863 /*
1864 * Set the base address for the rtc, and ioremap its
1865 * registers.
1866 */
1867 rtc->baseaddr = res->start;
1868 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size);
1869 if (!rtc->regs)
1870 return -ENOMEM;
1871 }
1872 rtc->alloc_io_resources = pdata->alloc_io_resources;
1873
1874 /* Get the register step size. */
1875 if (pdata->regstep > 0)
1876 rtc->regstep = pdata->regstep;
1877 else
1878 rtc->regstep = 1;
1879
1880 /* Platform read function, else default if mmio setup */
1881 if (pdata->plat_read)
1882 rtc->read = pdata->plat_read;
1883 else
1884 if (pdata->alloc_io_resources)
1885 rtc->read = ds1685_read;
1886 else
1887 return -ENXIO;
1888
1889 /* Platform write function, else default if mmio setup */
1890 if (pdata->plat_write)
1891 rtc->write = pdata->plat_write;
1892 else
1893 if (pdata->alloc_io_resources)
1894 rtc->write = ds1685_write;
1895 else
1896 return -ENXIO;
1897
1898 /* Platform pre-shutdown function, if defined. */
1899 if (pdata->plat_prepare_poweroff)
1900 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1901
1902 /* Platform wake_alarm function, if defined. */
1903 if (pdata->plat_wake_alarm)
1904 rtc->wake_alarm = pdata->plat_wake_alarm;
1905
1906 /* Platform post_ram_clear function, if defined. */
1907 if (pdata->plat_post_ram_clear)
1908 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1909
1910 /* Init the spinlock, workqueue, & set the driver data. */
1911 spin_lock_init(&rtc->lock);
1912 INIT_WORK(&rtc->work, ds1685_rtc_work_queue);
1913 platform_set_drvdata(pdev, rtc);
1914
1915 /* Turn the oscillator on if is not already on (DV1 = 1). */
1916 ctrla = rtc->read(rtc, RTC_CTRL_A);
1917 if (!(ctrla & RTC_CTRL_A_DV1))
1918 ctrla |= RTC_CTRL_A_DV1;
1919
1920 /* Enable the countdown chain (DV2 = 0) */
1921 ctrla &= ~(RTC_CTRL_A_DV2);
1922
1923 /* Clear RS3-RS0 in Control A. */
1924 ctrla &= ~(RTC_CTRL_A_RS_MASK);
1925
1926 /*
1927 * All done with Control A. Switch to Bank 1 for the remainder of
1928 * the RTC setup so we have access to the extended functions.
1929 */
1930 ctrla |= RTC_CTRL_A_DV0;
1931 rtc->write(rtc, RTC_CTRL_A, ctrla);
1932
1933 /* Default to 32768kHz output. */
1934 rtc->write(rtc, RTC_EXT_CTRL_4B,
1935 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1936
1937 /* Set the SET bit in Control B so we can do some housekeeping. */
1938 rtc->write(rtc, RTC_CTRL_B,
1939 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1940
1941 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1942 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1943 cpu_relax();
1944
1945 /*
1946 * If the platform supports BCD mode, then set DM=0 in Control B.
1947 * Otherwise, set DM=1 for BIN mode.
1948 */
1949 ctrlb = rtc->read(rtc, RTC_CTRL_B);
1950 if (pdata->bcd_mode)
1951 ctrlb &= ~(RTC_CTRL_B_DM);
1952 else
1953 ctrlb |= RTC_CTRL_B_DM;
1954 rtc->bcd_mode = pdata->bcd_mode;
1955
1956 /*
1957 * Disable Daylight Savings Time (DSE = 0).
1958 * The RTC has hardcoded timezone information that is rendered
1959 * obselete. We'll let the OS deal with DST settings instead.
1960 */
1961 if (ctrlb & RTC_CTRL_B_DSE)
1962 ctrlb &= ~(RTC_CTRL_B_DSE);
1963
1964 /* Force 24-hour mode (2412 = 1). */
1965 if (!(ctrlb & RTC_CTRL_B_2412)) {
1966 /* Reinitialize the time hours. */
1967 hours = rtc->read(rtc, RTC_HRS);
1968 am_pm = hours & RTC_HRS_AMPM_MASK;
1969 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1970 RTC_HRS_12_BIN_MASK);
1971 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1972
1973 /* Enable 24-hour mode. */
1974 ctrlb |= RTC_CTRL_B_2412;
1975
1976 /* Write back to Control B, including DM & DSE bits. */
1977 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1978
1979 /* Write the time hours back. */
1980 rtc->write(rtc, RTC_HRS,
1981 ds1685_rtc_bin2bcd(rtc, hours,
1982 RTC_HRS_24_BIN_MASK,
1983 RTC_HRS_24_BCD_MASK));
1984
1985 /* Reinitialize the alarm hours. */
1986 hours = rtc->read(rtc, RTC_HRS_ALARM);
1987 am_pm = hours & RTC_HRS_AMPM_MASK;
1988 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1989 RTC_HRS_12_BIN_MASK);
1990 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1991
1992 /* Write the alarm hours back. */
1993 rtc->write(rtc, RTC_HRS_ALARM,
1994 ds1685_rtc_bin2bcd(rtc, hours,
1995 RTC_HRS_24_BIN_MASK,
1996 RTC_HRS_24_BCD_MASK));
1997 } else {
1998 /* 24-hour mode is already set, so write Control B back. */
1999 rtc->write(rtc, RTC_CTRL_B, ctrlb);
2000 }
2001
2002 /* Unset the SET bit in Control B so the RTC can update. */
2003 rtc->write(rtc, RTC_CTRL_B,
2004 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
2005
2006 /* Check the main battery. */
2007 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
2008 dev_warn(&pdev->dev,
2009 "Main battery is exhausted! RTC may be invalid!\n");
2010
2011 /* Check the auxillary battery. It is optional. */
2012 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
2013 dev_warn(&pdev->dev,
2014 "Aux battery is exhausted or not available.\n");
2015
2016 /* Read Ctrl B and clear PIE/AIE/UIE. */
2017 rtc->write(rtc, RTC_CTRL_B,
2018 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
2019
2020 /* Reading Ctrl C auto-clears PF/AF/UF. */
2021 rtc->read(rtc, RTC_CTRL_C);
2022
2023 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
2024 rtc->write(rtc, RTC_EXT_CTRL_4B,
2025 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
2026
2027 /* Clear RF/WF/KF in Ctrl 4A. */
2028 rtc->write(rtc, RTC_EXT_CTRL_4A,
2029 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
2030
2031 /*
2032 * Re-enable KSE to handle power button events. We do not enable
2033 * WIE or RIE by default.
2034 */
2035 rtc->write(rtc, RTC_EXT_CTRL_4B,
2036 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
2037
2038 /*
2039 * Fetch the IRQ and setup the interrupt handler.
2040 *
2041 * Not all platforms have the IRQF pin tied to something. If not, the
2042 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
2043 * there won't be an automatic way of notifying the kernel about it,
2044 * unless ctrlc is explicitly polled.
2045 */
2046 if (!pdata->no_irq) {
2047 ret = platform_get_irq(pdev, 0);
2048 if (ret > 0) {
2049 rtc->irq_num = ret;
2050
2051 /* Request an IRQ. */
2052 ret = devm_request_irq(&pdev->dev, rtc->irq_num,
2053 ds1685_rtc_irq_handler,
2054 IRQF_SHARED, pdev->name, pdev);
2055
2056 /* Check to see if something came back. */
2057 if (unlikely(ret)) {
2058 dev_warn(&pdev->dev,
2059 "RTC interrupt not available\n");
2060 rtc->irq_num = 0;
2061 }
2062 } else
2063 return ret;
2064 }
2065 rtc->no_irq = pdata->no_irq;
2066
2067 /* Setup complete. */
2068 ds1685_rtc_switch_to_bank0(rtc);
2069
2070 /* Register the device as an RTC. */
2071 rtc_dev = rtc_device_register(pdev->name, &pdev->dev,
2072 &ds1685_rtc_ops, THIS_MODULE);
2073
2074 /* Success? */
2075 if (IS_ERR(rtc_dev))
2076 return PTR_ERR(rtc_dev);
2077
2078 /* Maximum periodic rate is 8192Hz (0.122070ms). */
2079 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
2080
2081 /* See if the platform doesn't support UIE. */
2082 if (pdata->uie_unsupported)
2083 rtc_dev->uie_unsupported = 1;
2084 rtc->uie_unsupported = pdata->uie_unsupported;
2085
2086 rtc->dev = rtc_dev;
2087
2088#ifdef CONFIG_SYSFS
2089 ret = ds1685_rtc_sysfs_register(&pdev->dev);
2090 if (ret)
2091 rtc_device_unregister(rtc->dev);
2092#endif
2093
2094 /* Done! */
2095 return ret;
2096}
2097
2098/**
2099 * ds1685_rtc_remove - removes rtc driver.
2100 * @pdev: pointer to platform_device structure.
2101 */
2102static int
2103ds1685_rtc_remove(struct platform_device *pdev)
2104{
2105 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
2106
2107#ifdef CONFIG_SYSFS
2108 ds1685_rtc_sysfs_unregister(&pdev->dev);
2109#endif
2110
2111 rtc_device_unregister(rtc->dev);
2112
2113 /* Read Ctrl B and clear PIE/AIE/UIE. */
2114 rtc->write(rtc, RTC_CTRL_B,
2115 (rtc->read(rtc, RTC_CTRL_B) &
2116 ~(RTC_CTRL_B_PAU_MASK)));
2117
2118 /* Reading Ctrl C auto-clears PF/AF/UF. */
2119 rtc->read(rtc, RTC_CTRL_C);
2120
2121 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
2122 rtc->write(rtc, RTC_EXT_CTRL_4B,
2123 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
2124 ~(RTC_CTRL_4B_RWK_MASK)));
2125
2126 /* Manually clear RF/WF/KF in Ctrl 4A. */
2127 rtc->write(rtc, RTC_EXT_CTRL_4A,
2128 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
2129 ~(RTC_CTRL_4A_RWK_MASK)));
2130
2131 cancel_work_sync(&rtc->work);
2132
2133 return 0;
2134}
2135
2136/**
2137 * ds1685_rtc_driver - rtc driver properties.
2138 */
2139static struct platform_driver ds1685_rtc_driver = {
2140 .driver = {
2141 .name = "rtc-ds1685",
2142 .owner = THIS_MODULE,
2143 },
2144 .probe = ds1685_rtc_probe,
2145 .remove = ds1685_rtc_remove,
2146};
2147
2148/**
2149 * ds1685_rtc_init - rtc module init.
2150 */
2151static int __init
2152ds1685_rtc_init(void)
2153{
2154 return platform_driver_register(&ds1685_rtc_driver);
2155}
2156
2157/**
2158 * ds1685_rtc_exit - rtc module exit.
2159 */
2160static void __exit
2161ds1685_rtc_exit(void)
2162{
2163 platform_driver_unregister(&ds1685_rtc_driver);
2164}
2165
2166module_init(ds1685_rtc_init);
2167module_exit(ds1685_rtc_exit);
2168/* ----------------------------------------------------------------------- */
2169
2170
2171/* ----------------------------------------------------------------------- */
2172/* Poweroff function */
2173
2174/**
2175 * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
2176 * @pdev: pointer to platform_device structure.
2177 */
2178extern void __noreturn
2179ds1685_rtc_poweroff(struct platform_device *pdev)
2180{
2181 u8 ctrla, ctrl4a, ctrl4b;
2182 struct ds1685_priv *rtc;
2183
2184 /* Check for valid RTC data, else, spin forever. */
2185 if (unlikely(!pdev)) {
2186 pr_emerg("rtc-ds1685: platform device data not available, spinning forever ...\n");
2187 unreachable();
2188 } else {
2189 /* Get the rtc data. */
2190 rtc = platform_get_drvdata(pdev);
2191
2192 /*
2193 * Disable our IRQ. We're powering down, so we're not
2194 * going to worry about cleaning up. Most of that should
2195 * have been taken care of by the shutdown scripts and this
2196 * is the final function call.
2197 */
2198 if (!rtc->no_irq)
2199 disable_irq_nosync(rtc->irq_num);
2200
2201 /* Oscillator must be on and the countdown chain enabled. */
2202 ctrla = rtc->read(rtc, RTC_CTRL_A);
2203 ctrla |= RTC_CTRL_A_DV1;
2204 ctrla &= ~(RTC_CTRL_A_DV2);
2205 rtc->write(rtc, RTC_CTRL_A, ctrla);
2206
2207 /*
2208 * Read Control 4A and check the status of the auxillary
2209 * battery. This must be present and working (VRT2 = 1)
2210 * for wakeup and kickstart functionality to be useful.
2211 */
2212 ds1685_rtc_switch_to_bank1(rtc);
2213 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
2214 if (ctrl4a & RTC_CTRL_4A_VRT2) {
2215 /* Clear all of the interrupt flags on Control 4A. */
2216 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
2217 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
2218
2219 /*
2220 * The auxillary battery is present and working.
2221 * Enable extended functions (ABE=1), enable
2222 * wake-up (WIE=1), and enable kickstart (KSE=1)
2223 * in Control 4B.
2224 */
2225 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
2226 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
2227 RTC_CTRL_4B_KSE);
2228 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
2229 }
2230
2231 /* Set PAB to 1 in Control 4A to power the system down. */
2232 dev_warn(&pdev->dev, "Powerdown.\n");
2233 msleep(20);
2234 rtc->write(rtc, RTC_EXT_CTRL_4A,
2235 (ctrl4a | RTC_CTRL_4A_PAB));
2236
2237 /* Spin ... we do not switch back to bank0. */
2238 unreachable();
2239 }
2240}
2241EXPORT_SYMBOL(ds1685_rtc_poweroff);
2242/* ----------------------------------------------------------------------- */
2243
2244
2245MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
2246MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
2247MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
2248MODULE_LICENSE("GPL");
2249MODULE_VERSION(DRV_VERSION);
2250MODULE_ALIAS("platform:rtc-ds1685");
diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
index 42f5570f42f8..c666eab98273 100644
--- a/drivers/rtc/rtc-imxdi.c
+++ b/drivers/rtc/rtc-imxdi.c
@@ -50,22 +50,58 @@
50#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ 50#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
51 51
52#define DCR 0x10 /* Control Reg */ 52#define DCR 0x10 /* Control Reg */
53#define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
54#define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
55#define DCR_KSSL (1 << 27) /* Key-select soft lock */
56#define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */
57#define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */
58#define DCR_TCHL (1 << 18) /* Timer-counter hard lock */
59#define DCR_TCSL (1 << 17) /* Timer-counter soft lock */
60#define DCR_FSHL (1 << 16) /* Failure state hard lock */
53#define DCR_TCE (1 << 3) /* Time Counter Enable */ 61#define DCR_TCE (1 << 3) /* Time Counter Enable */
62#define DCR_MCE (1 << 2) /* Monotonic Counter Enable */
54 63
55#define DSR 0x14 /* Status Reg */ 64#define DSR 0x14 /* Status Reg */
56#define DSR_WBF (1 << 10) /* Write Busy Flag */ 65#define DSR_WTD (1 << 23) /* Wire-mesh tamper detected */
57#define DSR_WNF (1 << 9) /* Write Next Flag */ 66#define DSR_ETBD (1 << 22) /* External tamper B detected */
58#define DSR_WCF (1 << 8) /* Write Complete Flag */ 67#define DSR_ETAD (1 << 21) /* External tamper A detected */
68#define DSR_EBD (1 << 20) /* External boot detected */
69#define DSR_SAD (1 << 19) /* SCC alarm detected */
70#define DSR_TTD (1 << 18) /* Temperatur tamper detected */
71#define DSR_CTD (1 << 17) /* Clock tamper detected */
72#define DSR_VTD (1 << 16) /* Voltage tamper detected */
73#define DSR_WBF (1 << 10) /* Write Busy Flag (synchronous) */
74#define DSR_WNF (1 << 9) /* Write Next Flag (synchronous) */
75#define DSR_WCF (1 << 8) /* Write Complete Flag (synchronous)*/
59#define DSR_WEF (1 << 7) /* Write Error Flag */ 76#define DSR_WEF (1 << 7) /* Write Error Flag */
60#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ 77#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
78#define DSR_MCO (1 << 3) /* monotonic counter overflow */
79#define DSR_TCO (1 << 2) /* time counter overflow */
61#define DSR_NVF (1 << 1) /* Non-Valid Flag */ 80#define DSR_NVF (1 << 1) /* Non-Valid Flag */
62#define DSR_SVF (1 << 0) /* Security Violation Flag */ 81#define DSR_SVF (1 << 0) /* Security Violation Flag */
63 82
64#define DIER 0x18 /* Interrupt Enable Reg */ 83#define DIER 0x18 /* Interrupt Enable Reg (synchronous) */
65#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ 84#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
66#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ 85#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
67#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ 86#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
68#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ 87#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
88#define DIER_SVIE (1 << 0) /* Security-violation Interrupt Enable */
89
90#define DMCR 0x1c /* DryIce Monotonic Counter Reg */
91
92#define DTCR 0x28 /* DryIce Tamper Configuration Reg */
93#define DTCR_MOE (1 << 9) /* monotonic overflow enabled */
94#define DTCR_TOE (1 << 8) /* time overflow enabled */
95#define DTCR_WTE (1 << 7) /* wire-mesh tamper enabled */
96#define DTCR_ETBE (1 << 6) /* external B tamper enabled */
97#define DTCR_ETAE (1 << 5) /* external A tamper enabled */
98#define DTCR_EBE (1 << 4) /* external boot tamper enabled */
99#define DTCR_SAIE (1 << 3) /* SCC enabled */
100#define DTCR_TTE (1 << 2) /* temperature tamper enabled */
101#define DTCR_CTE (1 << 1) /* clock tamper enabled */
102#define DTCR_VTE (1 << 0) /* voltage tamper enabled */
103
104#define DGPR 0x3c /* DryIce General Purpose Reg */
69 105
70/** 106/**
71 * struct imxdi_dev - private imxdi rtc data 107 * struct imxdi_dev - private imxdi rtc data
@@ -313,7 +349,7 @@ static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
313 dier = __raw_readl(imxdi->ioaddr + DIER); 349 dier = __raw_readl(imxdi->ioaddr + DIER);
314 350
315 /* handle write complete and write error cases */ 351 /* handle write complete and write error cases */
316 if ((dier & DIER_WCIE)) { 352 if (dier & DIER_WCIE) {
317 /*If the write wait queue is empty then there is no pending 353 /*If the write wait queue is empty then there is no pending
318 operations. It means the interrupt is for DryIce -Security. 354 operations. It means the interrupt is for DryIce -Security.
319 IRQ must be returned as none.*/ 355 IRQ must be returned as none.*/
@@ -322,7 +358,7 @@ static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
322 358
323 /* DSR_WCF clears itself on DSR read */ 359 /* DSR_WCF clears itself on DSR read */
324 dsr = __raw_readl(imxdi->ioaddr + DSR); 360 dsr = __raw_readl(imxdi->ioaddr + DSR);
325 if ((dsr & (DSR_WCF | DSR_WEF))) { 361 if (dsr & (DSR_WCF | DSR_WEF)) {
326 /* mask the interrupt */ 362 /* mask the interrupt */
327 di_int_disable(imxdi, DIER_WCIE); 363 di_int_disable(imxdi, DIER_WCIE);
328 364
@@ -335,7 +371,7 @@ static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
335 } 371 }
336 372
337 /* handle the alarm case */ 373 /* handle the alarm case */
338 if ((dier & DIER_CAIE)) { 374 if (dier & DIER_CAIE) {
339 /* DSR_WCF clears itself on DSR read */ 375 /* DSR_WCF clears itself on DSR read */
340 dsr = __raw_readl(imxdi->ioaddr + DSR); 376 dsr = __raw_readl(imxdi->ioaddr + DSR);
341 if (dsr & DSR_CAF) { 377 if (dsr & DSR_CAF) {
diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c
index ee3ba7e6b45e..f9b082784b90 100644
--- a/drivers/rtc/rtc-isl12022.c
+++ b/drivers/rtc/rtc-isl12022.c
@@ -275,7 +275,8 @@ static int isl12022_probe(struct i2c_client *client,
275 275
276#ifdef CONFIG_OF 276#ifdef CONFIG_OF
277static const struct of_device_id isl12022_dt_match[] = { 277static const struct of_device_id isl12022_dt_match[] = {
278 { .compatible = "isl,isl12022" }, 278 { .compatible = "isl,isl12022" }, /* for backward compat., don't use */
279 { .compatible = "isil,isl12022" },
279 { }, 280 { },
280}; 281};
281#endif 282#endif
diff --git a/drivers/rtc/rtc-isl12057.c b/drivers/rtc/rtc-isl12057.c
index 6e1fcfb5d7e6..da818d3337ce 100644
--- a/drivers/rtc/rtc-isl12057.c
+++ b/drivers/rtc/rtc-isl12057.c
@@ -79,8 +79,10 @@
79#define ISL12057_MEM_MAP_LEN 0x10 79#define ISL12057_MEM_MAP_LEN 0x10
80 80
81struct isl12057_rtc_data { 81struct isl12057_rtc_data {
82 struct rtc_device *rtc;
82 struct regmap *regmap; 83 struct regmap *regmap;
83 struct mutex lock; 84 struct mutex lock;
85 int irq;
84}; 86};
85 87
86static void isl12057_rtc_regs_to_tm(struct rtc_time *tm, u8 *regs) 88static void isl12057_rtc_regs_to_tm(struct rtc_time *tm, u8 *regs)
@@ -160,14 +162,47 @@ static int isl12057_i2c_validate_chip(struct regmap *regmap)
160 return 0; 162 return 0;
161} 163}
162 164
163static int isl12057_rtc_read_time(struct device *dev, struct rtc_time *tm) 165static int _isl12057_rtc_clear_alarm(struct device *dev)
166{
167 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
168 int ret;
169
170 ret = regmap_update_bits(data->regmap, ISL12057_REG_SR,
171 ISL12057_REG_SR_A1F, 0);
172 if (ret)
173 dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
174
175 return ret;
176}
177
178static int _isl12057_rtc_update_alarm(struct device *dev, int enable)
179{
180 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
181 int ret;
182
183 ret = regmap_update_bits(data->regmap, ISL12057_REG_INT,
184 ISL12057_REG_INT_A1IE,
185 enable ? ISL12057_REG_INT_A1IE : 0);
186 if (ret)
187 dev_err(dev, "%s: changing alarm interrupt flag failed (%d)\n",
188 __func__, ret);
189
190 return ret;
191}
192
193/*
194 * Note: as we only read from device and do not perform any update, there is
195 * no need for an equivalent function which would try and get driver's main
196 * lock. Here, it is safe for everyone if we just use regmap internal lock
197 * on the device when reading.
198 */
199static int _isl12057_rtc_read_time(struct device *dev, struct rtc_time *tm)
164{ 200{
165 struct isl12057_rtc_data *data = dev_get_drvdata(dev); 201 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
166 u8 regs[ISL12057_RTC_SEC_LEN]; 202 u8 regs[ISL12057_RTC_SEC_LEN];
167 unsigned int sr; 203 unsigned int sr;
168 int ret; 204 int ret;
169 205
170 mutex_lock(&data->lock);
171 ret = regmap_read(data->regmap, ISL12057_REG_SR, &sr); 206 ret = regmap_read(data->regmap, ISL12057_REG_SR, &sr);
172 if (ret) { 207 if (ret) {
173 dev_err(dev, "%s: unable to read oscillator status flag (%d)\n", 208 dev_err(dev, "%s: unable to read oscillator status flag (%d)\n",
@@ -187,8 +222,6 @@ static int isl12057_rtc_read_time(struct device *dev, struct rtc_time *tm)
187 __func__, ret); 222 __func__, ret);
188 223
189out: 224out:
190 mutex_unlock(&data->lock);
191
192 if (ret) 225 if (ret)
193 return ret; 226 return ret;
194 227
@@ -197,6 +230,168 @@ out:
197 return rtc_valid_tm(tm); 230 return rtc_valid_tm(tm);
198} 231}
199 232
233static int isl12057_rtc_update_alarm(struct device *dev, int enable)
234{
235 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
236 int ret;
237
238 mutex_lock(&data->lock);
239 ret = _isl12057_rtc_update_alarm(dev, enable);
240 mutex_unlock(&data->lock);
241
242 return ret;
243}
244
245static int isl12057_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
246{
247 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
248 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
249 unsigned long rtc_secs, alarm_secs;
250 u8 regs[ISL12057_A1_SEC_LEN];
251 unsigned int ir;
252 int ret;
253
254 mutex_lock(&data->lock);
255 ret = regmap_bulk_read(data->regmap, ISL12057_REG_A1_SC, regs,
256 ISL12057_A1_SEC_LEN);
257 if (ret) {
258 dev_err(dev, "%s: reading alarm section failed (%d)\n",
259 __func__, ret);
260 goto err_unlock;
261 }
262
263 alarm_tm->tm_sec = bcd2bin(regs[0] & 0x7f);
264 alarm_tm->tm_min = bcd2bin(regs[1] & 0x7f);
265 alarm_tm->tm_hour = bcd2bin(regs[2] & 0x3f);
266 alarm_tm->tm_mday = bcd2bin(regs[3] & 0x3f);
267 alarm_tm->tm_wday = -1;
268
269 /*
270 * The alarm section does not store year/month. We use the ones in rtc
271 * section as a basis and increment month and then year if needed to get
272 * alarm after current time.
273 */
274 ret = _isl12057_rtc_read_time(dev, &rtc_tm);
275 if (ret)
276 goto err_unlock;
277
278 alarm_tm->tm_year = rtc_tm.tm_year;
279 alarm_tm->tm_mon = rtc_tm.tm_mon;
280
281 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
282 if (ret)
283 goto err_unlock;
284
285 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
286 if (ret)
287 goto err_unlock;
288
289 if (alarm_secs < rtc_secs) {
290 if (alarm_tm->tm_mon == 11) {
291 alarm_tm->tm_mon = 0;
292 alarm_tm->tm_year += 1;
293 } else {
294 alarm_tm->tm_mon += 1;
295 }
296 }
297
298 ret = regmap_read(data->regmap, ISL12057_REG_INT, &ir);
299 if (ret) {
300 dev_err(dev, "%s: reading alarm interrupt flag failed (%d)\n",
301 __func__, ret);
302 goto err_unlock;
303 }
304
305 alarm->enabled = !!(ir & ISL12057_REG_INT_A1IE);
306
307err_unlock:
308 mutex_unlock(&data->lock);
309
310 return ret;
311}
312
313static int isl12057_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
314{
315 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
316 struct rtc_time *alarm_tm = &alarm->time;
317 unsigned long rtc_secs, alarm_secs;
318 u8 regs[ISL12057_A1_SEC_LEN];
319 struct rtc_time rtc_tm;
320 int ret, enable = 1;
321
322 mutex_lock(&data->lock);
323 ret = _isl12057_rtc_read_time(dev, &rtc_tm);
324 if (ret)
325 goto err_unlock;
326
327 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
328 if (ret)
329 goto err_unlock;
330
331 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
332 if (ret)
333 goto err_unlock;
334
335 /* If alarm time is before current time, disable the alarm */
336 if (!alarm->enabled || alarm_secs <= rtc_secs) {
337 enable = 0;
338 } else {
339 /*
340 * Chip only support alarms up to one month in the future. Let's
341 * return an error if we get something after that limit.
342 * Comparison is done by incrementing rtc_tm month field by one
343 * and checking alarm value is still below.
344 */
345 if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
346 rtc_tm.tm_mon = 0;
347 rtc_tm.tm_year += 1;
348 } else {
349 rtc_tm.tm_mon += 1;
350 }
351
352 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
353 if (ret)
354 goto err_unlock;
355
356 if (alarm_secs > rtc_secs) {
357 dev_err(dev, "%s: max for alarm is one month (%d)\n",
358 __func__, ret);
359 ret = -EINVAL;
360 goto err_unlock;
361 }
362 }
363
364 /* Disable the alarm before modifying it */
365 ret = _isl12057_rtc_update_alarm(dev, 0);
366 if (ret < 0) {
367 dev_err(dev, "%s: unable to disable the alarm (%d)\n",
368 __func__, ret);
369 goto err_unlock;
370 }
371
372 /* Program alarm registers */
373 regs[0] = bin2bcd(alarm_tm->tm_sec) & 0x7f;
374 regs[1] = bin2bcd(alarm_tm->tm_min) & 0x7f;
375 regs[2] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
376 regs[3] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
377
378 ret = regmap_bulk_write(data->regmap, ISL12057_REG_A1_SC, regs,
379 ISL12057_A1_SEC_LEN);
380 if (ret < 0) {
381 dev_err(dev, "%s: writing alarm section failed (%d)\n",
382 __func__, ret);
383 goto err_unlock;
384 }
385
386 /* Enable or disable alarm */
387 ret = _isl12057_rtc_update_alarm(dev, enable);
388
389err_unlock:
390 mutex_unlock(&data->lock);
391
392 return ret;
393}
394
200static int isl12057_rtc_set_time(struct device *dev, struct rtc_time *tm) 395static int isl12057_rtc_set_time(struct device *dev, struct rtc_time *tm)
201{ 396{
202 struct isl12057_rtc_data *data = dev_get_drvdata(dev); 397 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
@@ -262,12 +457,85 @@ static int isl12057_check_rtc_status(struct device *dev, struct regmap *regmap)
262 return 0; 457 return 0;
263} 458}
264 459
460#ifdef CONFIG_OF
461/*
462 * One would expect the device to be marked as a wakeup source only
463 * when an IRQ pin of the RTC is routed to an interrupt line of the
464 * CPU. In practice, such an IRQ pin can be connected to a PMIC and
465 * this allows the device to be powered up when RTC alarm rings. This
466 * is for instance the case on ReadyNAS 102, 104 and 2120. On those
467 * devices with no IRQ driectly connected to the SoC, the RTC chip
468 * can be forced as a wakeup source by stating that explicitly in
469 * the device's .dts file using the "isil,irq2-can-wakeup-machine"
470 * boolean property. This will guarantee 'wakealarm' sysfs entry is
471 * available on the device.
472 *
473 * The function below returns 1, i.e. the capability of the chip to
474 * wakeup the device, based on IRQ availability or if the boolean
475 * property has been set in the .dts file. Otherwise, it returns 0.
476 */
477
478static bool isl12057_can_wakeup_machine(struct device *dev)
479{
480 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
481
482 return (data->irq || of_property_read_bool(dev->of_node,
483 "isil,irq2-can-wakeup-machine"));
484}
485#else
486static bool isl12057_can_wakeup_machine(struct device *dev)
487{
488 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
489
490 return !!data->irq;
491}
492#endif
493
494static int isl12057_rtc_alarm_irq_enable(struct device *dev,
495 unsigned int enable)
496{
497 struct isl12057_rtc_data *rtc_data = dev_get_drvdata(dev);
498 int ret = -ENOTTY;
499
500 if (rtc_data->irq)
501 ret = isl12057_rtc_update_alarm(dev, enable);
502
503 return ret;
504}
505
506static irqreturn_t isl12057_rtc_interrupt(int irq, void *data)
507{
508 struct i2c_client *client = data;
509 struct isl12057_rtc_data *rtc_data = dev_get_drvdata(&client->dev);
510 struct rtc_device *rtc = rtc_data->rtc;
511 int ret, handled = IRQ_NONE;
512 unsigned int sr;
513
514 ret = regmap_read(rtc_data->regmap, ISL12057_REG_SR, &sr);
515 if (!ret && (sr & ISL12057_REG_SR_A1F)) {
516 dev_dbg(&client->dev, "RTC alarm!\n");
517
518 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
519
520 /* Acknowledge and disable the alarm */
521 _isl12057_rtc_clear_alarm(&client->dev);
522 _isl12057_rtc_update_alarm(&client->dev, 0);
523
524 handled = IRQ_HANDLED;
525 }
526
527 return handled;
528}
529
265static const struct rtc_class_ops rtc_ops = { 530static const struct rtc_class_ops rtc_ops = {
266 .read_time = isl12057_rtc_read_time, 531 .read_time = _isl12057_rtc_read_time,
267 .set_time = isl12057_rtc_set_time, 532 .set_time = isl12057_rtc_set_time,
533 .read_alarm = isl12057_rtc_read_alarm,
534 .set_alarm = isl12057_rtc_set_alarm,
535 .alarm_irq_enable = isl12057_rtc_alarm_irq_enable,
268}; 536};
269 537
270static struct regmap_config isl12057_rtc_regmap_config = { 538static const struct regmap_config isl12057_rtc_regmap_config = {
271 .reg_bits = 8, 539 .reg_bits = 8,
272 .val_bits = 8, 540 .val_bits = 8,
273}; 541};
@@ -277,7 +545,6 @@ static int isl12057_probe(struct i2c_client *client,
277{ 545{
278 struct device *dev = &client->dev; 546 struct device *dev = &client->dev;
279 struct isl12057_rtc_data *data; 547 struct isl12057_rtc_data *data;
280 struct rtc_device *rtc;
281 struct regmap *regmap; 548 struct regmap *regmap;
282 int ret; 549 int ret;
283 550
@@ -310,13 +577,75 @@ static int isl12057_probe(struct i2c_client *client,
310 data->regmap = regmap; 577 data->regmap = regmap;
311 dev_set_drvdata(dev, data); 578 dev_set_drvdata(dev, data);
312 579
313 rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops, THIS_MODULE); 580 if (client->irq > 0) {
314 return PTR_ERR_OR_ZERO(rtc); 581 ret = devm_request_threaded_irq(dev, client->irq, NULL,
582 isl12057_rtc_interrupt,
583 IRQF_SHARED|IRQF_ONESHOT,
584 DRV_NAME, client);
585 if (!ret)
586 data->irq = client->irq;
587 else
588 dev_err(dev, "%s: irq %d unavailable (%d)\n", __func__,
589 client->irq, ret);
590 }
591
592 if (isl12057_can_wakeup_machine(dev))
593 device_init_wakeup(dev, true);
594
595 data->rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops,
596 THIS_MODULE);
597 ret = PTR_ERR_OR_ZERO(data->rtc);
598 if (ret) {
599 dev_err(dev, "%s: unable to register RTC device (%d)\n",
600 __func__, ret);
601 goto err;
602 }
603
604 /* We cannot support UIE mode if we do not have an IRQ line */
605 if (!data->irq)
606 data->rtc->uie_unsupported = 1;
607
608err:
609 return ret;
610}
611
612static int isl12057_remove(struct i2c_client *client)
613{
614 if (isl12057_can_wakeup_machine(&client->dev))
615 device_init_wakeup(&client->dev, false);
616
617 return 0;
618}
619
620#ifdef CONFIG_PM_SLEEP
621static int isl12057_rtc_suspend(struct device *dev)
622{
623 struct isl12057_rtc_data *rtc_data = dev_get_drvdata(dev);
624
625 if (rtc_data->irq && device_may_wakeup(dev))
626 return enable_irq_wake(rtc_data->irq);
627
628 return 0;
629}
630
631static int isl12057_rtc_resume(struct device *dev)
632{
633 struct isl12057_rtc_data *rtc_data = dev_get_drvdata(dev);
634
635 if (rtc_data->irq && device_may_wakeup(dev))
636 return disable_irq_wake(rtc_data->irq);
637
638 return 0;
315} 639}
640#endif
641
642static SIMPLE_DEV_PM_OPS(isl12057_rtc_pm_ops, isl12057_rtc_suspend,
643 isl12057_rtc_resume);
316 644
317#ifdef CONFIG_OF 645#ifdef CONFIG_OF
318static const struct of_device_id isl12057_dt_match[] = { 646static const struct of_device_id isl12057_dt_match[] = {
319 { .compatible = "isl,isl12057" }, 647 { .compatible = "isl,isl12057" }, /* for backward compat., don't use */
648 { .compatible = "isil,isl12057" },
320 { }, 649 { },
321}; 650};
322#endif 651#endif
@@ -331,9 +660,11 @@ static struct i2c_driver isl12057_driver = {
331 .driver = { 660 .driver = {
332 .name = DRV_NAME, 661 .name = DRV_NAME,
333 .owner = THIS_MODULE, 662 .owner = THIS_MODULE,
663 .pm = &isl12057_rtc_pm_ops,
334 .of_match_table = of_match_ptr(isl12057_dt_match), 664 .of_match_table = of_match_ptr(isl12057_dt_match),
335 }, 665 },
336 .probe = isl12057_probe, 666 .probe = isl12057_probe,
667 .remove = isl12057_remove,
337 .id_table = isl12057_id, 668 .id_table = isl12057_id,
338}; 669};
339module_i2c_driver(isl12057_driver); 670module_i2c_driver(isl12057_driver);
diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c
index d1953bb244c5..8a7556cbcb7f 100644
--- a/drivers/rtc/rtc-pcf2123.c
+++ b/drivers/rtc/rtc-pcf2123.c
@@ -38,6 +38,7 @@
38#include <linux/errno.h> 38#include <linux/errno.h>
39#include <linux/init.h> 39#include <linux/init.h>
40#include <linux/kernel.h> 40#include <linux/kernel.h>
41#include <linux/of.h>
41#include <linux/string.h> 42#include <linux/string.h>
42#include <linux/slab.h> 43#include <linux/slab.h>
43#include <linux/rtc.h> 44#include <linux/rtc.h>
@@ -340,10 +341,19 @@ static int pcf2123_remove(struct spi_device *spi)
340 return 0; 341 return 0;
341} 342}
342 343
344#ifdef CONFIG_OF
345static const struct of_device_id pcf2123_dt_ids[] = {
346 { .compatible = "nxp,rtc-pcf2123", },
347 { /* sentinel */ }
348};
349MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
350#endif
351
343static struct spi_driver pcf2123_driver = { 352static struct spi_driver pcf2123_driver = {
344 .driver = { 353 .driver = {
345 .name = "rtc-pcf2123", 354 .name = "rtc-pcf2123",
346 .owner = THIS_MODULE, 355 .owner = THIS_MODULE,
356 .of_match_table = of_match_ptr(pcf2123_dt_ids),
347 }, 357 },
348 .probe = pcf2123_probe, 358 .probe = pcf2123_probe,
349 .remove = pcf2123_remove, 359 .remove = pcf2123_remove,
diff --git a/drivers/rtc/rtc-rk808.c b/drivers/rtc/rtc-rk808.c
index df42257668ac..91ca0bc1b484 100644
--- a/drivers/rtc/rtc-rk808.c
+++ b/drivers/rtc/rtc-rk808.c
@@ -67,15 +67,21 @@ static int rk808_rtc_readtime(struct device *dev, struct rtc_time *tm)
67 /* Force an update of the shadowed registers right now */ 67 /* Force an update of the shadowed registers right now */
68 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 68 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
69 BIT_RTC_CTRL_REG_RTC_GET_TIME, 69 BIT_RTC_CTRL_REG_RTC_GET_TIME,
70 0); 70 BIT_RTC_CTRL_REG_RTC_GET_TIME);
71 if (ret) { 71 if (ret) {
72 dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret); 72 dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret);
73 return ret; 73 return ret;
74 } 74 }
75 75
76 /*
77 * After we set the GET_TIME bit, the rtc time can't be read
78 * immediately. So we should wait up to 31.25 us, about one cycle of
79 * 32khz. If we clear the GET_TIME bit here, the time of i2c transfer
80 * certainly more than 31.25us: 16 * 2.5us at 400kHz bus frequency.
81 */
76 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 82 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
77 BIT_RTC_CTRL_REG_RTC_GET_TIME, 83 BIT_RTC_CTRL_REG_RTC_GET_TIME,
78 BIT_RTC_CTRL_REG_RTC_GET_TIME); 84 0);
79 if (ret) { 85 if (ret) {
80 dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret); 86 dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret);
81 return ret; 87 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-27 14:59:42 -0400