1 files changed, 134 insertions, 77 deletions

diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c
index 30d2072f480b..722246cf20ab 100644
--- a/drivers/rapidio/devices/tsi721.c
+++ b/drivers/rapidio/devices/tsi721.c
@@ -108,6 +108,7 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
                         u16 destid, u8 hopcount, u32 offset, int len,
                         u32 *data, int do_wr)
 {
+        void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id);
         struct tsi721_dma_desc *bd_ptr;
         u32 rd_count, swr_ptr, ch_stat;
         int i, err = 0;
@@ -116,10 +117,9 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
         if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
                 return -EINVAL;
 
-        bd_ptr = priv->bdma[TSI721_DMACH_MAINT].bd_base;
+        bd_ptr = priv->mdma.bd_base;
 
-        rd_count = ioread32(
-                        priv->regs + TSI721_DMAC_DRDCNT(TSI721_DMACH_MAINT));
+        rd_count = ioread32(regs + TSI721_DMAC_DRDCNT);
 
         /* Initialize DMA descriptor */
         bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
@@ -134,19 +134,18 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
         mb();
 
         /* Start DMA operation */
-        iowrite32(rd_count + 2,
-                priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
-        ioread32(priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
+        iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
+        ioread32(regs + TSI721_DMAC_DWRCNT);
         i = 0;
 
         /* Wait until DMA transfer is finished */
-        while ((ch_stat = ioread32(priv->regs +
-                TSI721_DMAC_STS(TSI721_DMACH_MAINT))) & TSI721_DMAC_STS_RUN) {
+        while ((ch_stat = ioread32(regs + TSI721_DMAC_STS))
+                                                        & TSI721_DMAC_STS_RUN) {
                 udelay(1);
                 if (++i >= 5000000) {
                         dev_dbg(&priv->pdev->dev,
                                 "%s : DMA[%d] read timeout ch_status=%x\n",
-                                __func__, TSI721_DMACH_MAINT, ch_stat);
+                                __func__, priv->mdma.ch_id, ch_stat);
                         if (!do_wr)
                                 *data = 0xffffffff;
                         err = -EIO;
@@ -162,13 +161,10 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
                         __func__, ch_stat);
                 dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
                         do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
-                iowrite32(TSI721_DMAC_INT_ALL,
-                        priv->regs + TSI721_DMAC_INT(TSI721_DMACH_MAINT));
-                iowrite32(TSI721_DMAC_CTL_INIT,
-                        priv->regs + TSI721_DMAC_CTL(TSI721_DMACH_MAINT));
+                iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
+                iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
                 udelay(10);
-                iowrite32(0, priv->regs +
-                                TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
+                iowrite32(0, regs + TSI721_DMAC_DWRCNT);
                 udelay(1);
                 if (!do_wr)
                         *data = 0xffffffff;
@@ -184,8 +180,8 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
          * NOTE: Skipping check and clear FIFO entries because we are waiting
          * for transfer to be completed.
          */
-        swr_ptr = ioread32(priv->regs + TSI721_DMAC_DSWP(TSI721_DMACH_MAINT));
-        iowrite32(swr_ptr, priv->regs + TSI721_DMAC_DSRP(TSI721_DMACH_MAINT));
+        swr_ptr = ioread32(regs + TSI721_DMAC_DSWP);
+        iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
 err_out:
 
         return err;
@@ -541,6 +537,22 @@ static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
                         tsi721_pw_handler(mport);
         }
 
+#ifdef CONFIG_RAPIDIO_DMA_ENGINE
+        if (dev_int & TSI721_DEV_INT_BDMA_CH) {
+                int ch;
+
+                if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) {
+                        dev_dbg(&priv->pdev->dev,
+                                "IRQ from DMA channel 0x%08x\n", dev_ch_int);
+
+                        for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {
+                                if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))
+                                        continue;
+                                tsi721_bdma_handler(&priv->bdma[ch]);
+                        }
+                }
+        }
+#endif
         return IRQ_HANDLED;
 }
 
@@ -553,18 +565,26 @@ static void tsi721_interrupts_init(struct tsi721_device *priv)
                 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
         iowrite32(TSI721_SR_CHINT_IDBQRCV,
                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
-        iowrite32(TSI721_INT_SR2PC_CHAN(IDB_QUEUE),
-                priv->regs + TSI721_DEV_CHAN_INTE);
 
         /* Enable SRIO MAC interrupts */
         iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
                 priv->regs + TSI721_RIO_EM_DEV_INT_EN);
 
+        /* Enable interrupts from channels in use */
+#ifdef CONFIG_RAPIDIO_DMA_ENGINE
+        intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
+                (TSI721_INT_BDMA_CHAN_M &
+                 ~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT));
+#else
+        intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
+#endif
+        iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
+
         if (priv->flags & TSI721_USING_MSIX)
                 intr = TSI721_DEV_INT_SRIO;
         else
                 intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
-                        TSI721_DEV_INT_SMSG_CH;
+                        TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
 
         iowrite32(intr, priv->regs + TSI721_DEV_INTE);
         ioread32(priv->regs + TSI721_DEV_INTE);
@@ -715,12 +735,29 @@ static int tsi721_enable_msix(struct tsi721_device *priv)
                                         TSI721_MSIX_OMSG_INT(i);
         }
 
+#ifdef CONFIG_RAPIDIO_DMA_ENGINE
+        /*
+         * Initialize MSI-X entries for Block DMA Engine:
+         * this driver supports XXX DMA channels
+         * (one is reserved for SRIO maintenance transactions)
+         */
+        for (i = 0; i < TSI721_DMA_CHNUM; i++) {
+                entries[TSI721_VECT_DMA0_DONE + i].entry =
+                                        TSI721_MSIX_DMACH_DONE(i);
+                entries[TSI721_VECT_DMA0_INT + i].entry =
+                                        TSI721_MSIX_DMACH_INT(i);
+        }
+#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
+
         err = pci_enable_msix(priv->pdev, entries, ARRAY_SIZE(entries));
         if (err) {
                 if (err > 0)
                         dev_info(&priv->pdev->dev,
                                  "Only %d MSI-X vectors available, "
                                  "not using MSI-X\n", err);
+                else
+                        dev_err(&priv->pdev->dev,
+                                "Failed to enable MSI-X (err=%d)\n", err);
                 return err;
         }
 
@@ -760,6 +797,22 @@ static int tsi721_enable_msix(struct tsi721_device *priv)
                          i, pci_name(priv->pdev));
         }
 
+#ifdef CONFIG_RAPIDIO_DMA_ENGINE
+        for (i = 0; i < TSI721_DMA_CHNUM; i++) {
+                priv->msix[TSI721_VECT_DMA0_DONE + i].vector =
+                                entries[TSI721_VECT_DMA0_DONE + i].vector;
+                snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,
+                         IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s",
+                         i, pci_name(priv->pdev));
+
+                priv->msix[TSI721_VECT_DMA0_INT + i].vector =
+                                entries[TSI721_VECT_DMA0_INT + i].vector;
+                snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,
+                         IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s",
+                         i, pci_name(priv->pdev));
+        }
+#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
+
         return 0;
 }
 #endif /* CONFIG_PCI_MSI */
@@ -888,20 +941,34 @@ static void tsi721_doorbell_free(struct tsi721_device *priv)
         priv->idb_base = NULL;
 }
 
-static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
+/**
+ * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
+ * @priv: pointer to tsi721 private data
+ *
+ * Initialize BDMA channel allocated for RapidIO maintenance read/write
+ * request generation
+ * Returns %0 on success or %-ENOMEM on failure.
+ */
+static int tsi721_bdma_maint_init(struct tsi721_device *priv)
 {
         struct tsi721_dma_desc *bd_ptr;
         u64             *sts_ptr;
         dma_addr_t      bd_phys, sts_phys;
         int             sts_size;
-        int             bd_num = priv->bdma[chnum].bd_num;
+        int             bd_num = 2;
+        void __iomem    *regs;
 
-        dev_dbg(&priv->pdev->dev, "Init Block DMA Engine, CH%d\n", chnum);
+        dev_dbg(&priv->pdev->dev,
+                "Init Block DMA Engine for Maintenance requests, CH%d\n",
+                TSI721_DMACH_MAINT);
 
         /*
          * Initialize DMA channel for maintenance requests
          */
 
+        priv->mdma.ch_id = TSI721_DMACH_MAINT;
+        regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT);
+
         /* Allocate space for DMA descriptors */
         bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
                                         bd_num * sizeof(struct tsi721_dma_desc),
@@ -909,8 +976,9 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
         if (!bd_ptr)
                 return -ENOMEM;
 
-        priv->bdma[chnum].bd_phys = bd_phys;
-        priv->bdma[chnum].bd_base = bd_ptr;
+        priv->mdma.bd_num = bd_num;
+        priv->mdma.bd_phys = bd_phys;
+        priv->mdma.bd_base = bd_ptr;
 
         dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
                 bd_ptr, (unsigned long long)bd_phys);
@@ -927,13 +995,13 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
                 dma_free_coherent(&priv->pdev->dev,
                                   bd_num * sizeof(struct tsi721_dma_desc),
                                   bd_ptr, bd_phys);
-                priv->bdma[chnum].bd_base = NULL;
+                priv->mdma.bd_base = NULL;
                 return -ENOMEM;
         }
 
-        priv->bdma[chnum].sts_phys = sts_phys;
-        priv->bdma[chnum].sts_base = sts_ptr;
-        priv->bdma[chnum].sts_size = sts_size;
+        priv->mdma.sts_phys = sts_phys;
+        priv->mdma.sts_base = sts_ptr;
+        priv->mdma.sts_size = sts_size;
 
         dev_dbg(&priv->pdev->dev,
                 "desc status FIFO @ %p (phys = %llx) size=0x%x\n",
@@ -946,83 +1014,61 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
         bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
 
         /* Setup DMA descriptor pointers */
-        iowrite32(((u64)bd_phys >> 32),
-                priv->regs + TSI721_DMAC_DPTRH(chnum));
+        iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
         iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
-                priv->regs + TSI721_DMAC_DPTRL(chnum));
+                regs + TSI721_DMAC_DPTRL);
 
         /* Setup descriptor status FIFO */
-        iowrite32(((u64)sts_phys >> 32),
-                priv->regs + TSI721_DMAC_DSBH(chnum));
+        iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
         iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
-                priv->regs + TSI721_DMAC_DSBL(chnum));
+                regs + TSI721_DMAC_DSBL);
         iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
-                priv->regs + TSI721_DMAC_DSSZ(chnum));
+                regs + TSI721_DMAC_DSSZ);
 
         /* Clear interrupt bits */
-        iowrite32(TSI721_DMAC_INT_ALL,
-                priv->regs + TSI721_DMAC_INT(chnum));
+        iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
 
-        ioread32(priv->regs + TSI721_DMAC_INT(chnum));
+        ioread32(regs + TSI721_DMAC_INT);
 
         /* Toggle DMA channel initialization */
-        iowrite32(TSI721_DMAC_CTL_INIT, priv->regs + TSI721_DMAC_CTL(chnum));
-        ioread32(priv->regs + TSI721_DMAC_CTL(chnum));
+        iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
+        ioread32(regs + TSI721_DMAC_CTL);
         udelay(10);
 
         return 0;
 }
 
-static int tsi721_bdma_ch_free(struct tsi721_device *priv, int chnum)
+static int tsi721_bdma_maint_free(struct tsi721_device *priv)
 {
         u32 ch_stat;
+        struct tsi721_bdma_maint *mdma = &priv->mdma;
+        void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id);
 
-        if (priv->bdma[chnum].bd_base == NULL)
+        if (mdma->bd_base == NULL)
                 return 0;
 
         /* Check if DMA channel still running */
-        ch_stat = ioread32(priv->regs + TSI721_DMAC_STS(chnum));
+        ch_stat = ioread32(regs + TSI721_DMAC_STS);
         if (ch_stat & TSI721_DMAC_STS_RUN)
                 return -EFAULT;
 
         /* Put DMA channel into init state */
-        iowrite32(TSI721_DMAC_CTL_INIT,
-                priv->regs + TSI721_DMAC_CTL(chnum));
+        iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
 
         /* Free space allocated for DMA descriptors */
         dma_free_coherent(&priv->pdev->dev,
-                priv->bdma[chnum].bd_num * sizeof(struct tsi721_dma_desc),
-                priv->bdma[chnum].bd_base, priv->bdma[chnum].bd_phys);
-        priv->bdma[chnum].bd_base = NULL;
+                mdma->bd_num * sizeof(struct tsi721_dma_desc),
+                mdma->bd_base, mdma->bd_phys);
+        mdma->bd_base = NULL;
 
         /* Free space allocated for status FIFO */
         dma_free_coherent(&priv->pdev->dev,
-                priv->bdma[chnum].sts_size * sizeof(struct tsi721_dma_sts),
-                priv->bdma[chnum].sts_base, priv->bdma[chnum].sts_phys);
-        priv->bdma[chnum].sts_base = NULL;
-        return 0;
-}
-
-static int tsi721_bdma_init(struct tsi721_device *priv)
-{
-        /* Initialize BDMA channel allocated for RapidIO maintenance read/write
-         * request generation
-         */
-        priv->bdma[TSI721_DMACH_MAINT].bd_num = 2;
-        if (tsi721_bdma_ch_init(priv, TSI721_DMACH_MAINT)) {
-                dev_err(&priv->pdev->dev, "Unable to initialize maintenance DMA"
-                        " channel %d, aborting\n", TSI721_DMACH_MAINT);
-                return -ENOMEM;
-        }
-
+                mdma->sts_size * sizeof(struct tsi721_dma_sts),
+                mdma->sts_base, mdma->sts_phys);
+        mdma->sts_base = NULL;
         return 0;
 }
 
-static void tsi721_bdma_free(struct tsi721_device *priv)
-{
-        tsi721_bdma_ch_free(priv, TSI721_DMACH_MAINT);
-}
-
 /* Enable Inbound Messaging Interrupts */
 static void
 tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
@@ -2035,7 +2081,8 @@ static void tsi721_disable_ints(struct tsi721_device *priv)
 
         /* Disable all BDMA Channel interrupts */
         for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
-                iowrite32(0, priv->regs + TSI721_DMAC_INTE(ch));
+                iowrite32(0,
+                        priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);
 
         /* Disable all general BDMA interrupts */
         iowrite32(0, priv->regs + TSI721_BDMA_INTE);
@@ -2104,6 +2151,7 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
         mport->phy_type = RIO_PHY_SERIAL;
         mport->priv = (void *)priv;
         mport->phys_efptr = 0x100;
+        priv->mport = mport;
 
         INIT_LIST_HEAD(&mport->dbells);
 
@@ -2129,17 +2177,21 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
         if (!err) {
                 tsi721_interrupts_init(priv);
                 ops->pwenable = tsi721_pw_enable;
-        } else
+        } else {
                 dev_err(&pdev->dev, "Unable to get assigned PCI IRQ "
                         "vector %02X err=0x%x\n", pdev->irq, err);
+                goto err_exit;
+        }
 
+#ifdef CONFIG_RAPIDIO_DMA_ENGINE
+        tsi721_register_dma(priv);
+#endif
         /* Enable SRIO link */
         iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
                   TSI721_DEVCTL_SRBOOT_CMPL,
                   priv->regs + TSI721_DEVCTL);
 
         rio_register_mport(mport);
-        priv->mport = mport;
 
         if (mport->host_deviceid >= 0)
                 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
@@ -2149,6 +2201,11 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
                 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
 
         return 0;
+
+err_exit:
+        kfree(mport);
+        kfree(ops);
+        return err;
 }
 
 static int __devinit tsi721_probe(struct pci_dev *pdev,
@@ -2294,7 +2351,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
         tsi721_init_pc2sr_mapping(priv);
         tsi721_init_sr2pc_mapping(priv);
 
-        if (tsi721_bdma_init(priv)) {
+        if (tsi721_bdma_maint_init(priv)) {
                 dev_err(&pdev->dev, "BDMA initialization failed, aborting\n");
                 err = -ENOMEM;
                 goto err_unmap_bars;
@@ -2319,7 +2376,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
 err_free_consistent:
         tsi721_doorbell_free(priv);
 err_free_bdma:
-        tsi721_bdma_free(priv);
+        tsi721_bdma_maint_free(priv);
 err_unmap_bars:
         if (priv->regs)
                 iounmap(priv->regs);