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path: root/drivers/platform/x86/intel_mid_thermal.c
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Diffstat (limited to 'drivers/platform/x86/intel_mid_thermal.c')
-rw-r--r--drivers/platform/x86/intel_mid_thermal.c47
1 files changed, 23 insertions, 24 deletions
diff --git a/drivers/platform/x86/intel_mid_thermal.c b/drivers/platform/x86/intel_mid_thermal.c
index ccd7b1f83519..2ee9766737ea 100644
--- a/drivers/platform/x86/intel_mid_thermal.c
+++ b/drivers/platform/x86/intel_mid_thermal.c
@@ -33,18 +33,15 @@
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <linux/pm.h> 34#include <linux/pm.h>
35#include <linux/thermal.h> 35#include <linux/thermal.h>
36 36#include <linux/mfd/intel_msic.h>
37#include <asm/intel_scu_ipc.h>
38 37
39/* Number of thermal sensors */ 38/* Number of thermal sensors */
40#define MSIC_THERMAL_SENSORS 4 39#define MSIC_THERMAL_SENSORS 4
41 40
42/* ADC1 - thermal registers */ 41/* ADC1 - thermal registers */
43#define MSIC_THERM_ADC1CNTL1 0x1C0
44#define MSIC_ADC_ENBL 0x10 42#define MSIC_ADC_ENBL 0x10
45#define MSIC_ADC_START 0x08 43#define MSIC_ADC_START 0x08
46 44
47#define MSIC_THERM_ADC1CNTL3 0x1C2
48#define MSIC_ADCTHERM_ENBL 0x04 45#define MSIC_ADCTHERM_ENBL 0x04
49#define MSIC_ADCRRDATA_ENBL 0x05 46#define MSIC_ADCRRDATA_ENBL 0x05
50#define MSIC_CHANL_MASK_VAL 0x0F 47#define MSIC_CHANL_MASK_VAL 0x0F
@@ -75,8 +72,8 @@
75#define ADC_VAL60C 315 72#define ADC_VAL60C 315
76 73
77/* ADC base addresses */ 74/* ADC base addresses */
78#define ADC_CHNL_START_ADDR 0x1C5 /* increments by 1 */ 75#define ADC_CHNL_START_ADDR INTEL_MSIC_ADC1ADDR0 /* increments by 1 */
79#define ADC_DATA_START_ADDR 0x1D4 /* increments by 2 */ 76#define ADC_DATA_START_ADDR INTEL_MSIC_ADC1SNS0H /* increments by 2 */
80 77
81/* MSIC die attributes */ 78/* MSIC die attributes */
82#define MSIC_DIE_ADC_MIN 488 79#define MSIC_DIE_ADC_MIN 488
@@ -189,17 +186,17 @@ static int mid_read_temp(struct thermal_zone_device *tzd, unsigned long *temp)
189 addr = td_info->chnl_addr; 186 addr = td_info->chnl_addr;
190 187
191 /* Enable the msic for conversion before reading */ 188 /* Enable the msic for conversion before reading */
192 ret = intel_scu_ipc_iowrite8(MSIC_THERM_ADC1CNTL3, MSIC_ADCRRDATA_ENBL); 189 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCRRDATA_ENBL);
193 if (ret) 190 if (ret)
194 return ret; 191 return ret;
195 192
196 /* Re-toggle the RRDATARD bit (temporary workaround) */ 193 /* Re-toggle the RRDATARD bit (temporary workaround) */
197 ret = intel_scu_ipc_iowrite8(MSIC_THERM_ADC1CNTL3, MSIC_ADCTHERM_ENBL); 194 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCTHERM_ENBL);
198 if (ret) 195 if (ret)
199 return ret; 196 return ret;
200 197
201 /* Read the higher bits of data */ 198 /* Read the higher bits of data */
202 ret = intel_scu_ipc_ioread8(addr, &data); 199 ret = intel_msic_reg_read(addr, &data);
203 if (ret) 200 if (ret)
204 return ret; 201 return ret;
205 202
@@ -207,7 +204,7 @@ static int mid_read_temp(struct thermal_zone_device *tzd, unsigned long *temp)
207 adc_val = (data << 2); 204 adc_val = (data << 2);
208 addr++; 205 addr++;
209 206
210 ret = intel_scu_ipc_ioread8(addr, &data);/* Read lower bits */ 207 ret = intel_msic_reg_read(addr, &data);/* Read lower bits */
211 if (ret) 208 if (ret)
212 return ret; 209 return ret;
213 210
@@ -235,7 +232,7 @@ static int configure_adc(int val)
235 int ret; 232 int ret;
236 uint8_t data; 233 uint8_t data;
237 234
238 ret = intel_scu_ipc_ioread8(MSIC_THERM_ADC1CNTL1, &data); 235 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
239 if (ret) 236 if (ret)
240 return ret; 237 return ret;
241 238
@@ -246,7 +243,7 @@ static int configure_adc(int val)
246 /* Just stop the ADC */ 243 /* Just stop the ADC */
247 data &= (~MSIC_ADC_START); 244 data &= (~MSIC_ADC_START);
248 } 245 }
249 return intel_scu_ipc_iowrite8(MSIC_THERM_ADC1CNTL1, data); 246 return intel_msic_reg_write(INTEL_MSIC_ADC1CNTL1, data);
250} 247}
251 248
252/** 249/**
@@ -262,21 +259,21 @@ static int set_up_therm_channel(u16 base_addr)
262 int ret; 259 int ret;
263 260
264 /* Enable all the sensor channels */ 261 /* Enable all the sensor channels */
265 ret = intel_scu_ipc_iowrite8(base_addr, SKIN_SENSOR0_CODE); 262 ret = intel_msic_reg_write(base_addr, SKIN_SENSOR0_CODE);
266 if (ret) 263 if (ret)
267 return ret; 264 return ret;
268 265
269 ret = intel_scu_ipc_iowrite8(base_addr + 1, SKIN_SENSOR1_CODE); 266 ret = intel_msic_reg_write(base_addr + 1, SKIN_SENSOR1_CODE);
270 if (ret) 267 if (ret)
271 return ret; 268 return ret;
272 269
273 ret = intel_scu_ipc_iowrite8(base_addr + 2, SYS_SENSOR_CODE); 270 ret = intel_msic_reg_write(base_addr + 2, SYS_SENSOR_CODE);
274 if (ret) 271 if (ret)
275 return ret; 272 return ret;
276 273
277 /* Since this is the last channel, set the stop bit 274 /* Since this is the last channel, set the stop bit
278 * to 1 by ORing the DIE_SENSOR_CODE with 0x10 */ 275 * to 1 by ORing the DIE_SENSOR_CODE with 0x10 */
279 ret = intel_scu_ipc_iowrite8(base_addr + 3, 276 ret = intel_msic_reg_write(base_addr + 3,
280 (MSIC_DIE_SENSOR_CODE | 0x10)); 277 (MSIC_DIE_SENSOR_CODE | 0x10));
281 if (ret) 278 if (ret)
282 return ret; 279 return ret;
@@ -295,11 +292,11 @@ static int reset_stopbit(uint16_t addr)
295{ 292{
296 int ret; 293 int ret;
297 uint8_t data; 294 uint8_t data;
298 ret = intel_scu_ipc_ioread8(addr, &data); 295 ret = intel_msic_reg_read(addr, &data);
299 if (ret) 296 if (ret)
300 return ret; 297 return ret;
301 /* Set the stop bit to zero */ 298 /* Set the stop bit to zero */
302 return intel_scu_ipc_iowrite8(addr, (data & 0xEF)); 299 return intel_msic_reg_write(addr, (data & 0xEF));
303} 300}
304 301
305/** 302/**
@@ -322,7 +319,7 @@ static int find_free_channel(void)
322 uint8_t data; 319 uint8_t data;
323 320
324 /* check whether ADC is enabled */ 321 /* check whether ADC is enabled */
325 ret = intel_scu_ipc_ioread8(MSIC_THERM_ADC1CNTL1, &data); 322 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
326 if (ret) 323 if (ret)
327 return ret; 324 return ret;
328 325
@@ -331,7 +328,7 @@ static int find_free_channel(void)
331 328
332 /* ADC is already enabled; Looking for an empty channel */ 329 /* ADC is already enabled; Looking for an empty channel */
333 for (i = 0; i < ADC_CHANLS_MAX; i++) { 330 for (i = 0; i < ADC_CHANLS_MAX; i++) {
334 ret = intel_scu_ipc_ioread8(ADC_CHNL_START_ADDR + i, &data); 331 ret = intel_msic_reg_read(ADC_CHNL_START_ADDR + i, &data);
335 if (ret) 332 if (ret)
336 return ret; 333 return ret;
337 334
@@ -359,12 +356,14 @@ static int mid_initialize_adc(struct device *dev)
359 * Ensure that adctherm is disabled before we 356 * Ensure that adctherm is disabled before we
360 * initialize the ADC 357 * initialize the ADC
361 */ 358 */
362 ret = intel_scu_ipc_ioread8(MSIC_THERM_ADC1CNTL3, &data); 359 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL3, &data);
363 if (ret) 360 if (ret)
364 return ret; 361 return ret;
365 362
366 if (data & MSIC_ADCTHERM_MASK) 363 data &= ~MSIC_ADCTHERM_MASK;
367 dev_warn(dev, "ADCTHERM already set"); 364 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, data);
365 if (ret)
366 return ret;
368 367
369 /* Index of the first channel in which the stop bit is set */ 368 /* Index of the first channel in which the stop bit is set */
370 channel_index = find_free_channel(); 369 channel_index = find_free_channel();
@@ -546,7 +545,7 @@ static int mid_thermal_remove(struct platform_device *pdev)
546 return configure_adc(0); 545 return configure_adc(0);
547} 546}
548 547
549#define DRIVER_NAME "msic_sensor" 548#define DRIVER_NAME "msic_thermal"
550 549
551static const struct platform_device_id therm_id_table[] = { 550static const struct platform_device_id therm_id_table[] = {
552 { DRIVER_NAME, 1 }, 551 { DRIVER_NAME, 1 },