diff options
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-dove.c | 124 |
1 files changed, 58 insertions, 66 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index b1a2e5b828c1..9e7ff651c018 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c | |||
@@ -30,21 +30,6 @@ | |||
30 | #define PMU_REGS_OFFS 0xd802c | 30 | #define PMU_REGS_OFFS 0xd802c |
31 | #define GC_REGS_OFFS 0xe802c | 31 | #define GC_REGS_OFFS 0xe802c |
32 | 32 | ||
33 | #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) | ||
34 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) | ||
35 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) | ||
36 | #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) | ||
37 | #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) | ||
38 | #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) | ||
39 | #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) | ||
40 | #define DOVE_TWSI_OPTION3_GPIO BIT(22) | ||
41 | #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) | ||
42 | #define DOVE_SSP_ON_AU1 BIT(0) | ||
43 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) | ||
44 | #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) | ||
45 | #define DOVE_NAND_GPIO_EN BIT(0) | ||
46 | #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) | ||
47 | |||
48 | /* MPP Base registers */ | 33 | /* MPP Base registers */ |
49 | #define PMU_MPP_GENERAL_CTRL 0x10 | 34 | #define PMU_MPP_GENERAL_CTRL 0x10 |
50 | #define AU0_AC97_SEL BIT(16) | 35 | #define AU0_AC97_SEL BIT(16) |
@@ -61,6 +46,19 @@ | |||
61 | #define PMU_SIGNAL_SELECT_0 0x00 | 46 | #define PMU_SIGNAL_SELECT_0 0x00 |
62 | #define PMU_SIGNAL_SELECT_1 0x04 | 47 | #define PMU_SIGNAL_SELECT_1 0x04 |
63 | 48 | ||
49 | /* Global Config regmap registers */ | ||
50 | #define GLOBAL_CONFIG_1 0x00 | ||
51 | #define TWSI_ENABLE_OPTION1 BIT(7) | ||
52 | #define GLOBAL_CONFIG_2 0x04 | ||
53 | #define TWSI_ENABLE_OPTION2 BIT(20) | ||
54 | #define TWSI_ENABLE_OPTION3 BIT(21) | ||
55 | #define TWSI_OPTION3_GPIO BIT(22) | ||
56 | #define SSP_CTRL_STATUS_1 0x08 | ||
57 | #define SSP_ON_AU1 BIT(0) | ||
58 | #define MPP_GENERAL_CONFIG 0x10 | ||
59 | #define AU1_SPDIFO_GPIO_EN BIT(1) | ||
60 | #define NAND_GPIO_EN BIT(0) | ||
61 | |||
64 | #define CONFIG_PMU BIT(4) | 62 | #define CONFIG_PMU BIT(4) |
65 | 63 | ||
66 | static void __iomem *mpp_base; | 64 | static void __iomem *mpp_base; |
@@ -182,23 +180,19 @@ static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) | |||
182 | 180 | ||
183 | static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) | 181 | static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) |
184 | { | 182 | { |
185 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); | 183 | unsigned int gmpp; |
186 | 184 | ||
187 | *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); | 185 | regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp); |
186 | *config = ((gmpp & NAND_GPIO_EN) != 0); | ||
188 | 187 | ||
189 | return 0; | 188 | return 0; |
190 | } | 189 | } |
191 | 190 | ||
192 | static int dove_nand_ctrl_set(unsigned pid, unsigned long config) | 191 | static int dove_nand_ctrl_set(unsigned pid, unsigned long config) |
193 | { | 192 | { |
194 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); | 193 | regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, |
195 | 194 | NAND_GPIO_EN, | |
196 | gmpp &= ~DOVE_NAND_GPIO_EN; | 195 | (config) ? NAND_GPIO_EN : 0); |
197 | if (config) | ||
198 | gmpp |= DOVE_NAND_GPIO_EN; | ||
199 | |||
200 | writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); | ||
201 | |||
202 | return 0; | 196 | return 0; |
203 | } | 197 | } |
204 | 198 | ||
@@ -226,18 +220,22 @@ static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) | |||
226 | static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) | 220 | static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) |
227 | { | 221 | { |
228 | unsigned int mpp4 = readl(mpp4_base); | 222 | unsigned int mpp4 = readl(mpp4_base); |
229 | unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); | 223 | unsigned int sspc1; |
230 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); | 224 | unsigned int gmpp; |
231 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); | 225 | unsigned int gcfg2; |
226 | |||
227 | regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1); | ||
228 | regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp); | ||
229 | regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2); | ||
232 | 230 | ||
233 | *config = 0; | 231 | *config = 0; |
234 | if (mpp4 & AU1_GPIO_SEL) | 232 | if (mpp4 & AU1_GPIO_SEL) |
235 | *config |= BIT(3); | 233 | *config |= BIT(3); |
236 | if (sspc1 & DOVE_SSP_ON_AU1) | 234 | if (sspc1 & SSP_ON_AU1) |
237 | *config |= BIT(2); | 235 | *config |= BIT(2); |
238 | if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) | 236 | if (gmpp & AU1_SPDIFO_GPIO_EN) |
239 | *config |= BIT(1); | 237 | *config |= BIT(1); |
240 | if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) | 238 | if (gcfg2 & TWSI_OPTION3_GPIO) |
241 | *config |= BIT(0); | 239 | *config |= BIT(0); |
242 | 240 | ||
243 | /* SSP/TWSI only if I2S1 not set*/ | 241 | /* SSP/TWSI only if I2S1 not set*/ |
@@ -252,31 +250,21 @@ static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) | |||
252 | static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) | 250 | static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) |
253 | { | 251 | { |
254 | unsigned int mpp4 = readl(mpp4_base); | 252 | unsigned int mpp4 = readl(mpp4_base); |
255 | unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); | ||
256 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); | ||
257 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); | ||
258 | 253 | ||
259 | /* | ||
260 | * clear all audio1 related bits before configure | ||
261 | */ | ||
262 | gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; | ||
263 | gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; | ||
264 | sspc1 &= ~DOVE_SSP_ON_AU1; | ||
265 | mpp4 &= ~AU1_GPIO_SEL; | 254 | mpp4 &= ~AU1_GPIO_SEL; |
266 | |||
267 | if (config & BIT(0)) | ||
268 | gcfg2 |= DOVE_TWSI_OPTION3_GPIO; | ||
269 | if (config & BIT(1)) | ||
270 | gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; | ||
271 | if (config & BIT(2)) | ||
272 | sspc1 |= DOVE_SSP_ON_AU1; | ||
273 | if (config & BIT(3)) | 255 | if (config & BIT(3)) |
274 | mpp4 |= AU1_GPIO_SEL; | 256 | mpp4 |= AU1_GPIO_SEL; |
275 | |||
276 | writel(mpp4, mpp4_base); | 257 | writel(mpp4, mpp4_base); |
277 | writel(sspc1, DOVE_SSP_CTRL_STATUS_1); | 258 | |
278 | writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); | 259 | regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1, |
279 | writel(gcfg2, DOVE_GLOBAL_CONFIG_2); | 260 | SSP_ON_AU1, |
261 | (config & BIT(2)) ? SSP_ON_AU1 : 0); | ||
262 | regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, | ||
263 | AU1_SPDIFO_GPIO_EN, | ||
264 | (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0); | ||
265 | regmap_update_bits(gconfmap, GLOBAL_CONFIG_2, | ||
266 | TWSI_OPTION3_GPIO, | ||
267 | (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0); | ||
280 | 268 | ||
281 | return 0; | 269 | return 0; |
282 | } | 270 | } |
@@ -322,15 +310,18 @@ static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) | |||
322 | 310 | ||
323 | static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) | 311 | static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) |
324 | { | 312 | { |
325 | unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); | 313 | unsigned int gcfg1; |
326 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); | 314 | unsigned int gcfg2; |
315 | |||
316 | regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1); | ||
317 | regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2); | ||
327 | 318 | ||
328 | *config = 0; | 319 | *config = 0; |
329 | if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) | 320 | if (gcfg1 & TWSI_ENABLE_OPTION1) |
330 | *config = 1; | 321 | *config = 1; |
331 | else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) | 322 | else if (gcfg2 & TWSI_ENABLE_OPTION2) |
332 | *config = 2; | 323 | *config = 2; |
333 | else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) | 324 | else if (gcfg2 & TWSI_ENABLE_OPTION3) |
334 | *config = 3; | 325 | *config = 3; |
335 | 326 | ||
336 | return 0; | 327 | return 0; |
@@ -338,26 +329,27 @@ static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) | |||
338 | 329 | ||
339 | static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) | 330 | static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) |
340 | { | 331 | { |
341 | unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); | 332 | unsigned int gcfg1 = 0; |
342 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); | 333 | unsigned int gcfg2 = 0; |
343 | |||
344 | gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; | ||
345 | gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); | ||
346 | 334 | ||
347 | switch (config) { | 335 | switch (config) { |
348 | case 1: | 336 | case 1: |
349 | gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; | 337 | gcfg1 = TWSI_ENABLE_OPTION1; |
350 | break; | 338 | break; |
351 | case 2: | 339 | case 2: |
352 | gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; | 340 | gcfg2 = TWSI_ENABLE_OPTION2; |
353 | break; | 341 | break; |
354 | case 3: | 342 | case 3: |
355 | gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; | 343 | gcfg2 = TWSI_ENABLE_OPTION3; |
356 | break; | 344 | break; |
357 | } | 345 | } |
358 | 346 | ||
359 | writel(gcfg1, DOVE_GLOBAL_CONFIG_1); | 347 | regmap_update_bits(gconfmap, GLOBAL_CONFIG_1, |
360 | writel(gcfg2, DOVE_GLOBAL_CONFIG_2); | 348 | TWSI_ENABLE_OPTION1, |
349 | gcfg1); | ||
350 | regmap_update_bits(gconfmap, GLOBAL_CONFIG_2, | ||
351 | TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3, | ||
352 | gcfg2); | ||
361 | 353 | ||
362 | return 0; | 354 | return 0; |
363 | } | 355 | } |