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-rw-r--r--drivers/pinctrl/Kconfig5
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c35
-rw-r--r--drivers/pinctrl/pinctrl-u300.c7
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig13
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile2
-rw-r--r--drivers/pinctrl/sh-pfc/core.c22
-rw-r--r--drivers/pinctrl/sh-pfc/core.h4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c1923
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c2783
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c493
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c3835
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c1652
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c742
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h4
14 files changed, 9973 insertions, 1547 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f6692438149..a1c6dd32e14b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,12 +207,13 @@ config PINCTRL_SAMSUNG
207 select PINCONF 207 select PINCONF
208 208
209config PINCTRL_EXYNOS 209config PINCTRL_EXYNOS
210 bool "Pinctrl driver data for Samsung EXYNOS SoCs" 210 bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
211 depends on OF && GPIOLIB 211 depends on OF && GPIOLIB && ARCH_EXYNOS
212 select PINCTRL_SAMSUNG 212 select PINCTRL_SAMSUNG
213 213
214config PINCTRL_EXYNOS5440 214config PINCTRL_EXYNOS5440
215 bool "Samsung EXYNOS5440 SoC pinctrl driver" 215 bool "Samsung EXYNOS5440 SoC pinctrl driver"
216 depends on SOC_EXYNOS5440
216 select PINMUX 217 select PINMUX
217 select PINCONF 218 select PINCONF
218 219
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index d6b41747d687..eeff7f7fc920 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -22,7 +22,6 @@
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/pinctrl/consumer.h> 23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/pinconf-generic.h> 24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/platform_data/pinctrl-coh901.h>
26#include "pinctrl-coh901.h" 25#include "pinctrl-coh901.h"
27 26
28#define U300_GPIO_PORT_STRIDE (0x30) 27#define U300_GPIO_PORT_STRIDE (0x30)
@@ -58,8 +57,9 @@
58#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) 57#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
59 58
60/* 8 bits per port, no version has more than 7 ports */ 59/* 8 bits per port, no version has more than 7 ports */
60#define U300_GPIO_NUM_PORTS 7
61#define U300_GPIO_PINS_PER_PORT 8 61#define U300_GPIO_PINS_PER_PORT 8
62#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) 62#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
63 63
64struct u300_gpio { 64struct u300_gpio {
65 struct gpio_chip chip; 65 struct gpio_chip chip;
@@ -111,9 +111,6 @@ struct u300_gpio_confdata {
111 int outval; 111 int outval;
112}; 112};
113 113
114/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
115#define BS335_GPIO_NUM_PORTS 7
116
117#define U300_FLOATING_INPUT { \ 114#define U300_FLOATING_INPUT { \
118 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ 115 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
119 .output = false, \ 116 .output = false, \
@@ -136,7 +133,7 @@ struct u300_gpio_confdata {
136 133
137/* Initial configuration */ 134/* Initial configuration */
138static const struct __initconst u300_gpio_confdata 135static const struct __initconst u300_gpio_confdata
139bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 136bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
140 /* Port 0, pins 0-7 */ 137 /* Port 0, pins 0-7 */
141 { 138 {
142 U300_FLOATING_INPUT, 139 U300_FLOATING_INPUT,
@@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
630 } 627 }
631} 628}
632 629
633static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, 630static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
634 struct u300_gpio_platform *plat)
635{ 631{
636 int i, j; 632 int i, j;
637 633
638 /* Write default config and values to all pins */ 634 /* Write default config and values to all pins */
639 for (i = 0; i < plat->ports; i++) { 635 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
640 for (j = 0; j < 8; j++) { 636 for (j = 0; j < 8; j++) {
641 const struct u300_gpio_confdata *conf; 637 const struct u300_gpio_confdata *conf;
642 int offset = (i*8) + j; 638 int offset = (i*8) + j;
@@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = {
693 689
694static int __init u300_gpio_probe(struct platform_device *pdev) 690static int __init u300_gpio_probe(struct platform_device *pdev)
695{ 691{
696 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
697 struct u300_gpio *gpio; 692 struct u300_gpio *gpio;
698 struct resource *memres; 693 struct resource *memres;
699 int err = 0; 694 int err = 0;
@@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
707 return -ENOMEM; 702 return -ENOMEM;
708 703
709 gpio->chip = u300_gpio_chip; 704 gpio->chip = u300_gpio_chip;
710 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; 705 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
711 gpio->chip.dev = &pdev->dev; 706 gpio->chip.dev = &pdev->dev;
712 gpio->chip.base = plat->gpio_base; 707 gpio->chip.base = 0;
713 gpio->dev = &pdev->dev; 708 gpio->dev = &pdev->dev;
714 709
715 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -750,11 +745,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
750 ((val & 0x0000FE00) >> 9) * 8); 745 ((val & 0x0000FE00) >> 9) * 8);
751 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, 746 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
752 gpio->base + U300_GPIO_CR); 747 gpio->base + U300_GPIO_CR);
753 u300_gpio_init_coh901571(gpio, plat); 748 u300_gpio_init_coh901571(gpio);
754 749
755 /* Add each port with its IRQ separately */ 750 /* Add each port with its IRQ separately */
756 INIT_LIST_HEAD(&gpio->port_list); 751 INIT_LIST_HEAD(&gpio->port_list);
757 for (portno = 0 ; portno < plat->ports; portno++) { 752 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
758 struct u300_gpio_port *port = 753 struct u300_gpio_port *port =
759 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); 754 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
760 755
@@ -768,8 +763,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
768 port->number = portno; 763 port->number = portno;
769 port->gpio = gpio; 764 port->gpio = gpio;
770 765
771 port->irq = platform_get_irq_byname(pdev, 766 port->irq = platform_get_irq(pdev, portno);
772 port->name);
773 767
774 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, 768 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
775 port->name); 769 port->name);
@@ -806,6 +800,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
806 } 800 }
807 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); 801 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
808 802
803#ifdef CONFIG_OF_GPIO
804 gpio->chip.of_node = pdev->dev.of_node;
805#endif
809 err = gpiochip_add(&gpio->chip); 806 err = gpiochip_add(&gpio->chip);
810 if (err) { 807 if (err) {
811 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); 808 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
@@ -860,9 +857,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
860 return 0; 857 return 0;
861} 858}
862 859
860static const struct of_device_id u300_gpio_match[] = {
861 { .compatible = "stericsson,gpio-coh901" },
862 {},
863};
864
863static struct platform_driver u300_gpio_driver = { 865static struct platform_driver u300_gpio_driver = {
864 .driver = { 866 .driver = {
865 .name = "u300-gpio", 867 .name = "u300-gpio",
868 .of_match_table = u300_gpio_match,
866 }, 869 },
867 .remove = __exit_p(u300_gpio_remove), 870 .remove = __exit_p(u300_gpio_remove),
868}; 871};
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 6a3a7503e6a0..06bfa09bb15c 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -1105,10 +1105,17 @@ static int u300_pmx_remove(struct platform_device *pdev)
1105 return 0; 1105 return 0;
1106} 1106}
1107 1107
1108static const struct of_device_id u300_pinctrl_match[] = {
1109 { .compatible = "stericsson,pinctrl-u300" },
1110 {},
1111};
1112
1113
1108static struct platform_driver u300_pmx_driver = { 1114static struct platform_driver u300_pmx_driver = {
1109 .driver = { 1115 .driver = {
1110 .name = DRIVER_NAME, 1116 .name = DRIVER_NAME,
1111 .owner = THIS_MODULE, 1117 .owner = THIS_MODULE,
1118 .of_match_table = u300_pinctrl_match,
1112 }, 1119 },
1113 .probe = u300_pmx_probe, 1120 .probe = u300_pmx_probe,
1114 .remove = u300_pmx_remove, 1121 .remove = u300_pmx_remove,
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index f8a2ae413c7f..636a882b406e 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -5,8 +5,6 @@
5if ARCH_SHMOBILE || SUPERH 5if ARCH_SHMOBILE || SUPERH
6 6
7config PINCTRL_SH_PFC 7config PINCTRL_SH_PFC
8 # XXX move off the gpio dependency
9 depends on GPIOLIB
10 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB 8 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
11 select PINMUX 9 select PINMUX
12 select PINCONF 10 select PINCONF
@@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740
32 depends on ARCH_R8A7740 30 depends on ARCH_R8A7740
33 select PINCTRL_SH_PFC 31 select PINCTRL_SH_PFC
34 32
33config PINCTRL_PFC_R8A7778
34 def_bool y
35 depends on ARCH_R8A7778
36 select PINCTRL_SH_PFC
37
35config PINCTRL_PFC_R8A7779 38config PINCTRL_PFC_R8A7779
36 def_bool y 39 def_bool y
37 depends on ARCH_R8A7779 40 depends on ARCH_R8A7779
38 select PINCTRL_SH_PFC 41 select PINCTRL_SH_PFC
39 42
43config PINCTRL_PFC_R8A7790
44 def_bool y
45 depends on ARCH_R8A7790
46 select PINCTRL_SH_PFC
47
40config PINCTRL_PFC_SH7203 48config PINCTRL_PFC_SH7203
41 def_bool y 49 def_bool y
42 depends on CPU_SUBTYPE_SH7203 50 depends on CPU_SUBTYPE_SH7203
@@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0
64 def_bool y 72 def_bool y
65 depends on ARCH_SH73A0 73 depends on ARCH_SH73A0
66 select PINCTRL_SH_PFC 74 select PINCTRL_SH_PFC
75 select REGULATOR
67 76
68config PINCTRL_PFC_SH7720 77config PINCTRL_PFC_SH7720
69 def_bool y 78 def_bool y
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 211cd8e98a8a..5e0c222c12d7 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,7 +5,9 @@ endif
5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o 5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o 6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
10obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
9obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 11obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
10obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 12obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
11obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 13obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b551336924a5..3b2fd43ff294 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
372 372
373 spin_lock_init(&pfc->lock); 373 spin_lock_init(&pfc->lock);
374 374
375 if (info->ops && info->ops->init) {
376 ret = info->ops->init(pfc);
377 if (ret < 0)
378 return ret;
379 }
380
375 pinctrl_provide_dummies(); 381 pinctrl_provide_dummies();
376 382
377 /* 383 /*
@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
379 */ 385 */
380 ret = sh_pfc_register_pinctrl(pfc); 386 ret = sh_pfc_register_pinctrl(pfc);
381 if (unlikely(ret != 0)) 387 if (unlikely(ret != 0))
382 return ret; 388 goto error;
383 389
384#ifdef CONFIG_GPIO_SH_PFC 390#ifdef CONFIG_GPIO_SH_PFC
385 /* 391 /*
@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
401 dev_info(pfc->dev, "%s support registered\n", info->name); 407 dev_info(pfc->dev, "%s support registered\n", info->name);
402 408
403 return 0; 409 return 0;
410
411error:
412 if (info->ops && info->ops->exit)
413 info->ops->exit(pfc);
414 return ret;
404} 415}
405 416
406static int sh_pfc_remove(struct platform_device *pdev) 417static int sh_pfc_remove(struct platform_device *pdev)
@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
412#endif 423#endif
413 sh_pfc_unregister_pinctrl(pfc); 424 sh_pfc_unregister_pinctrl(pfc);
414 425
426 if (pfc->info->ops && pfc->info->ops->exit)
427 pfc->info->ops->exit(pfc);
428
415 platform_set_drvdata(pdev, NULL); 429 platform_set_drvdata(pdev, NULL);
416 430
417 return 0; 431 return 0;
@@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = {
424#ifdef CONFIG_PINCTRL_PFC_R8A7740 438#ifdef CONFIG_PINCTRL_PFC_R8A7740
425 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, 439 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
426#endif 440#endif
441#ifdef CONFIG_PINCTRL_PFC_R8A7778
442 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
443#endif
427#ifdef CONFIG_PINCTRL_PFC_R8A7779 444#ifdef CONFIG_PINCTRL_PFC_R8A7779
428 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, 445 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
429#endif 446#endif
447#ifdef CONFIG_PINCTRL_PFC_R8A7790
448 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
449#endif
430#ifdef CONFIG_PINCTRL_PFC_SH7203 450#ifdef CONFIG_PINCTRL_PFC_SH7203
431 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 451 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
432#endif 452#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 89cb4289d761..f02ba1dde3a0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -11,6 +11,7 @@
11#define __SH_PFC_CORE_H__ 11#define __SH_PFC_CORE_H__
12 12
13#include <linux/compiler.h> 13#include <linux/compiler.h>
14#include <linux/spinlock.h>
14#include <linux/types.h> 15#include <linux/types.h>
15 16
16#include "sh_pfc.h" 17#include "sh_pfc.h"
@@ -27,6 +28,7 @@ struct sh_pfc_pinctrl;
27struct sh_pfc { 28struct sh_pfc {
28 struct device *dev; 29 struct device *dev;
29 const struct sh_pfc_soc_info *info; 30 const struct sh_pfc_soc_info *info;
31 void *soc_data;
30 spinlock_t lock; 32 spinlock_t lock;
31 33
32 unsigned int num_windows; 34 unsigned int num_windows;
@@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
56 58
57extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 59extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
58extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 60extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
61extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
59extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 62extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
63extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
60extern const struct sh_pfc_soc_info sh7203_pinmux_info; 64extern const struct sh_pfc_soc_info sh7203_pinmux_info;
61extern const struct sh_pfc_soc_info sh7264_pinmux_info; 65extern const struct sh_pfc_soc_info sh7264_pinmux_info;
62extern const struct sh_pfc_soc_info sh7269_pinmux_info; 66extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d29bfd0..f6ea47c433b3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -18,10 +18,14 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 20 */
21#include <linux/io.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/pinctrl/pinconf-generic.h>
24
22#include <mach/r8a7740.h> 25#include <mach/r8a7740.h>
23#include <mach/irqs.h> 26#include <mach/irqs.h>
24 27
28#include "core.h"
25#include "sh_pfc.h" 29#include "sh_pfc.h"
26 30
27#define CPU_ALL_PORT(fn, pfx, sfx) \ 31#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -30,6 +34,29 @@
30 PORT_10(fn, pfx##20, sfx), \ 34 PORT_10(fn, pfx##20, sfx), \
31 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) 35 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
32 36
37#undef _GPIO_PORT
38#define _GPIO_PORT(gpio, sfx) \
39 [gpio] = { \
40 .name = __stringify(PORT##gpio), \
41 .enum_id = PORT##gpio##_DATA, \
42 }
43
44#define IRQC_PIN_MUX(irq, pin) \
45static const unsigned int intc_irq##irq##_pins[] = { \
46 pin, \
47}; \
48static const unsigned int intc_irq##irq##_mux[] = { \
49 IRQ##irq##_MARK, \
50}
51
52#define IRQC_PINS_MUX(irq, idx, pin) \
53static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
54 pin, \
55}; \
56static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
57 IRQ##irq##_PORT##pin##_MARK, \
58}
59
33enum { 60enum {
34 PINMUX_RESERVED = 0, 61 PINMUX_RESERVED = 0,
35 62
@@ -43,16 +70,6 @@ enum {
43 PORT_ALL(IN), 70 PORT_ALL(IN),
44 PINMUX_INPUT_END, 71 PINMUX_INPUT_END,
45 72
46 /* PORT0_IN_PU -> PORT211_IN_PU */
47 PINMUX_INPUT_PULLUP_BEGIN,
48 PORT_ALL(IN_PU),
49 PINMUX_INPUT_PULLUP_END,
50
51 /* PORT0_IN_PD -> PORT211_IN_PD */
52 PINMUX_INPUT_PULLDOWN_BEGIN,
53 PORT_ALL(IN_PD),
54 PINMUX_INPUT_PULLDOWN_END,
55
56 /* PORT0_OUT -> PORT211_OUT */ 73 /* PORT0_OUT -> PORT211_OUT */
57 PINMUX_OUTPUT_BEGIN, 74 PINMUX_OUTPUT_BEGIN,
58 PORT_ALL(OUT), 75 PORT_ALL(OUT),
@@ -261,8 +278,6 @@ enum {
261 SCIFB_CTS_PORT173_MARK, 278 SCIFB_CTS_PORT173_MARK,
262 279
263 /* LCD0 */ 280 /* LCD0 */
264 LCDC0_SELECT_MARK,
265
266 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, 281 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
267 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, 282 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
268 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, 283 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
@@ -285,8 +300,6 @@ enum {
285 LCD0_LCLK_PORT102_MARK, 300 LCD0_LCLK_PORT102_MARK,
286 301
287 /* LCD1 */ 302 /* LCD1 */
288 LCDC1_SELECT_MARK,
289
290 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, 303 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
291 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, 304 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
292 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, 305 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
@@ -577,137 +590,11 @@ enum {
577 PINMUX_MARK_END, 590 PINMUX_MARK_END,
578}; 591};
579 592
593#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
594#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
595
580static const pinmux_enum_t pinmux_data[] = { 596static const pinmux_enum_t pinmux_data[] = {
581 /* specify valid pin states for each pin in GPIO mode */ 597 PINMUX_DATA_GP_ALL(),
582
583 /* I/O and Pull U/D */
584 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
585 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
586 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
587 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
588 PORT_DATA_IO(8), PORT_DATA_IO(9),
589
590 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
591 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
592 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
593 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
594 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
595
596 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
597 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
598 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
599 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
600 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
601
602 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
603 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
604 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
605 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
606 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
607
608 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
609 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
610 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
611 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
612 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
613
614 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
615 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
616 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
617 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
618 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
619
620 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
621 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
622 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
623 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
624 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
625
626 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
627 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
628 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
629 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
630 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
631
632 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
633 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
634 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
635 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
636 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
637
638 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
639 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
640 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
641 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
642 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
643
644 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
645 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
646 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
647 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
648 PORT_DATA_IO(108), PORT_DATA_IO(109),
649
650 PORT_DATA_IO(110), PORT_DATA_IO(111),
651 PORT_DATA_IO(112), PORT_DATA_IO(113),
652 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
653 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
654 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
655
656 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
657 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
658 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
659 PORT_DATA_IO(126), PORT_DATA_IO(127),
660 PORT_DATA_IO(128), PORT_DATA_IO(129),
661
662 PORT_DATA_IO(130), PORT_DATA_IO(131),
663 PORT_DATA_IO(132), PORT_DATA_IO(133),
664 PORT_DATA_IO(134), PORT_DATA_IO(135),
665 PORT_DATA_IO(136), PORT_DATA_IO(137),
666 PORT_DATA_IO(138), PORT_DATA_IO(139),
667
668 PORT_DATA_IO(140), PORT_DATA_IO(141),
669 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
670 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
671 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
672 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
673
674 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
675 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
676 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
677 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
678 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
679
680 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
681 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
682 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
683 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
684 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
685
686 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
687 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
688 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
689 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
690 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
691
692 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
693 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
694 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
695 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
696 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
697
698 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
699 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
700 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
701 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
702 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
703
704 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
705 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
706 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
707 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
708 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
709
710 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
711 598
712 /* Port0 */ 599 /* Port0 */
713 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), 600 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
@@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = {
986 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), 873 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
987 874
988 /* Port58 */ 875 /* Port58 */
989 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), 876 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
990 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), 877 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
991 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), 878 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
992 PINMUX_DATA(DV_D0_MARK, PORT58_FN6), 879 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
@@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = {
1633 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), 1520 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1634 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), 1521 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1635 1522
1636 /* LCDC select */
1637 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1638 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1639
1640 /* SDENC */ 1523 /* SDENC */
1641 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), 1524 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1642 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), 1525 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
@@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = {
1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), 1537 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1655}; 1538};
1656 1539
1540#define R8A7740_PIN(pin, cfgs) \
1541 { \
1542 .name = __stringify(PORT##pin), \
1543 .enum_id = PORT##pin##_DATA, \
1544 .configs = cfgs, \
1545 }
1546
1547#define __I (SH_PFC_PIN_CFG_INPUT)
1548#define __O (SH_PFC_PIN_CFG_OUTPUT)
1549#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1550#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1551#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1552#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1553
1554#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD)
1555#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU)
1556#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD)
1557#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO)
1558#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD)
1559#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU)
1560#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD)
1561#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O)
1562#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD)
1563
1657static struct sh_pfc_pin pinmux_pins[] = { 1564static struct sh_pfc_pin pinmux_pins[] = {
1658 GPIO_PORT_ALL(), 1565 /* Table 56-1 (I/O and Pull U/D) */
1566 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1567 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1568 R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1569 R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1570 R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1571 R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1572 R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1573 R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1574 R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1575 R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1576 R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1577 R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1578 R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1579 R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1580 R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1581 R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1582 R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1583 R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1584 R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1585 R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1586 R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1587 R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1588 R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1589 R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1590 R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1591 R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1592 R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1593 R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1594 R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1595 R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1596 R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1597 R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1598 R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1599 R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1600 R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1601 R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1602 R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1603 R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1604 R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1605 R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1606 R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1607 R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1608 R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1609 R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1610 R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1611 R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1612 R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1613 R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1614 R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1615 R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1616 R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1617 R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1618 R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1619 R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1620 R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1621 R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1622 R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1623 R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1624 R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1625 R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1626 R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1627 R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1628 R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1629 R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1630 R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1631 R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1632 R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1633 R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1634 R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1635 R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1636 R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1637 R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1638 R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1639 R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1640 R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1641 R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1642 R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1643 R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1644 R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1645 R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1646 R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1647 R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1648 R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1649 R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1650 R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1651 R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1652 R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1653 R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1654 R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1655 R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1656 R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1657 R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1658 R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1659 R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1660 R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1661 R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1662 R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1663 R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1664 R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1665 R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1666 R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1667 R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1668 R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1669 R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1670 R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1671 R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
1672};
1673
1674/* - BSC -------------------------------------------------------------------- */
1675static const unsigned int bsc_data8_pins[] = {
1676 /* D[0:7] */
1677 157, 156, 155, 154, 153, 152, 151, 150,
1678};
1679static const unsigned int bsc_data8_mux[] = {
1680 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1681 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1682};
1683static const unsigned int bsc_data16_pins[] = {
1684 /* D[0:15] */
1685 157, 156, 155, 154, 153, 152, 151, 150,
1686 149, 148, 147, 146, 145, 144, 143, 142,
1687};
1688static const unsigned int bsc_data16_mux[] = {
1689 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1690 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1691 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1692 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1693};
1694static const unsigned int bsc_data32_pins[] = {
1695 /* D[0:31] */
1696 157, 156, 155, 154, 153, 152, 151, 150,
1697 149, 148, 147, 146, 145, 144, 143, 142,
1698 171, 170, 169, 168, 167, 166, 173, 172,
1699 165, 164, 163, 162, 161, 160, 159, 158,
1700};
1701static const unsigned int bsc_data32_mux[] = {
1702 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1703 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1704 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1705 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1706 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1707 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1708 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1709 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1710};
1711static const unsigned int bsc_cs0_pins[] = {
1712 /* CS */
1713 109,
1714};
1715static const unsigned int bsc_cs0_mux[] = {
1716 CS0_MARK,
1717};
1718static const unsigned int bsc_cs2_pins[] = {
1719 /* CS */
1720 110,
1721};
1722static const unsigned int bsc_cs2_mux[] = {
1723 CS2_MARK,
1724};
1725static const unsigned int bsc_cs4_pins[] = {
1726 /* CS */
1727 111,
1728};
1729static const unsigned int bsc_cs4_mux[] = {
1730 CS4_MARK,
1731};
1732static const unsigned int bsc_cs5a_0_pins[] = {
1733 /* CS */
1734 105,
1735};
1736static const unsigned int bsc_cs5a_0_mux[] = {
1737 CS5A_PORT105_MARK,
1738};
1739static const unsigned int bsc_cs5a_1_pins[] = {
1740 /* CS */
1741 19,
1742};
1743static const unsigned int bsc_cs5a_1_mux[] = {
1744 CS5A_PORT19_MARK,
1745};
1746static const unsigned int bsc_cs5b_pins[] = {
1747 /* CS */
1748 103,
1749};
1750static const unsigned int bsc_cs5b_mux[] = {
1751 CS5B_MARK,
1752};
1753static const unsigned int bsc_cs6a_pins[] = {
1754 /* CS */
1755 104,
1756};
1757static const unsigned int bsc_cs6a_mux[] = {
1758 CS6A_MARK,
1759};
1760static const unsigned int bsc_rd_we8_pins[] = {
1761 /* RD, WE[0] */
1762 115, 113,
1763};
1764static const unsigned int bsc_rd_we8_mux[] = {
1765 RD_FSC_MARK, WE0_FWE_MARK,
1766};
1767static const unsigned int bsc_rd_we16_pins[] = {
1768 /* RD, WE[0:1] */
1769 115, 113, 112,
1770};
1771static const unsigned int bsc_rd_we16_mux[] = {
1772 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1773};
1774static const unsigned int bsc_rd_we32_pins[] = {
1775 /* RD, WE[0:3] */
1776 115, 113, 112, 108, 107,
1777};
1778static const unsigned int bsc_rd_we32_mux[] = {
1779 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1780};
1781static const unsigned int bsc_bs_pins[] = {
1782 /* BS */
1783 175,
1784};
1785static const unsigned int bsc_bs_mux[] = {
1786 BS_MARK,
1787};
1788static const unsigned int bsc_rdwr_pins[] = {
1789 /* RDWR */
1790 114,
1791};
1792static const unsigned int bsc_rdwr_mux[] = {
1793 RDWR_MARK,
1794};
1795/* - CEU0 ------------------------------------------------------------------- */
1796static const unsigned int ceu0_data_0_7_pins[] = {
1797 /* D[0:7] */
1798 34, 33, 32, 31, 30, 29, 28, 27,
1799};
1800static const unsigned int ceu0_data_0_7_mux[] = {
1801 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1802 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1803};
1804static const unsigned int ceu0_data_8_15_0_pins[] = {
1805 /* D[8:15] */
1806 182, 181, 180, 179, 178, 26, 25, 24,
1807};
1808static const unsigned int ceu0_data_8_15_0_mux[] = {
1809 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1810 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1811 VIO0_D15_PORT24_MARK,
1812};
1813static const unsigned int ceu0_data_8_15_1_pins[] = {
1814 /* D[8:15] */
1815 182, 181, 180, 179, 178, 22, 95, 96,
1816};
1817static const unsigned int ceu0_data_8_15_1_mux[] = {
1818 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1819 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1820 VIO0_D15_PORT96_MARK,
1821};
1822static const unsigned int ceu0_clk_0_pins[] = {
1823 /* CKO */
1824 36,
1825};
1826static const unsigned int ceu0_clk_0_mux[] = {
1827 VIO_CKO_MARK,
1828};
1829static const unsigned int ceu0_clk_1_pins[] = {
1830 /* CKO */
1831 14,
1832};
1833static const unsigned int ceu0_clk_1_mux[] = {
1834 VIO_CKO1_MARK,
1835};
1836static const unsigned int ceu0_clk_2_pins[] = {
1837 /* CKO */
1838 15,
1839};
1840static const unsigned int ceu0_clk_2_mux[] = {
1841 VIO_CKO2_MARK,
1842};
1843static const unsigned int ceu0_sync_pins[] = {
1844 /* CLK, VD, HD */
1845 35, 39, 37,
1846};
1847static const unsigned int ceu0_sync_mux[] = {
1848 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1849};
1850static const unsigned int ceu0_field_pins[] = {
1851 /* FIELD */
1852 38,
1853};
1854static const unsigned int ceu0_field_mux[] = {
1855 VIO0_FIELD_MARK,
1856};
1857/* - CEU1 ------------------------------------------------------------------- */
1858static const unsigned int ceu1_data_pins[] = {
1859 /* D[0:7] */
1860 182, 181, 180, 179, 178, 26, 25, 24,
1861};
1862static const unsigned int ceu1_data_mux[] = {
1863 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1864 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1865};
1866static const unsigned int ceu1_clk_pins[] = {
1867 /* CKO */
1868 23,
1869};
1870static const unsigned int ceu1_clk_mux[] = {
1871 VIO_CKO_1_MARK,
1872};
1873static const unsigned int ceu1_sync_pins[] = {
1874 /* CLK, VD, HD */
1875 197, 198, 160,
1876};
1877static const unsigned int ceu1_sync_mux[] = {
1878 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1879};
1880static const unsigned int ceu1_field_pins[] = {
1881 /* FIELD */
1882 21,
1883};
1884static const unsigned int ceu1_field_mux[] = {
1885 VIO1_FIELD_MARK,
1886};
1887/* - FSIA ------------------------------------------------------------------- */
1888static const unsigned int fsia_mclk_in_pins[] = {
1889 /* CK */
1890 11,
1891};
1892static const unsigned int fsia_mclk_in_mux[] = {
1893 FSIACK_MARK,
1894};
1895static const unsigned int fsia_mclk_out_pins[] = {
1896 /* OMC */
1897 10,
1898};
1899static const unsigned int fsia_mclk_out_mux[] = {
1900 FSIAOMC_MARK,
1901};
1902static const unsigned int fsia_sclk_in_pins[] = {
1903 /* ILR, IBT */
1904 12, 13,
1905};
1906static const unsigned int fsia_sclk_in_mux[] = {
1907 FSIAILR_MARK, FSIAIBT_MARK,
1908};
1909static const unsigned int fsia_sclk_out_pins[] = {
1910 /* OLR, OBT */
1911 7, 8,
1912};
1913static const unsigned int fsia_sclk_out_mux[] = {
1914 FSIAOLR_MARK, FSIAOBT_MARK,
1915};
1916static const unsigned int fsia_data_in_0_pins[] = {
1917 /* ISLD */
1918 0,
1659}; 1919};
1920static const unsigned int fsia_data_in_0_mux[] = {
1921 FSIAISLD_PORT0_MARK,
1922};
1923static const unsigned int fsia_data_in_1_pins[] = {
1924 /* ISLD */
1925 5,
1926};
1927static const unsigned int fsia_data_in_1_mux[] = {
1928 FSIAISLD_PORT5_MARK,
1929};
1930static const unsigned int fsia_data_out_0_pins[] = {
1931 /* OSLD */
1932 9,
1933};
1934static const unsigned int fsia_data_out_0_mux[] = {
1935 FSIAOSLD_MARK,
1936};
1937static const unsigned int fsia_data_out_1_pins[] = {
1938 /* OSLD */
1939 0,
1940};
1941static const unsigned int fsia_data_out_1_mux[] = {
1942 FSIAOSLD1_MARK,
1943};
1944static const unsigned int fsia_data_out_2_pins[] = {
1945 /* OSLD */
1946 1,
1947};
1948static const unsigned int fsia_data_out_2_mux[] = {
1949 FSIAOSLD2_MARK,
1950};
1951static const unsigned int fsia_spdif_0_pins[] = {
1952 /* SPDIF */
1953 9,
1954};
1955static const unsigned int fsia_spdif_0_mux[] = {
1956 FSIASPDIF_PORT9_MARK,
1957};
1958static const unsigned int fsia_spdif_1_pins[] = {
1959 /* SPDIF */
1960 18,
1961};
1962static const unsigned int fsia_spdif_1_mux[] = {
1963 FSIASPDIF_PORT18_MARK,
1964};
1965/* - FSIB ------------------------------------------------------------------- */
1966static const unsigned int fsib_mclk_in_pins[] = {
1967 /* CK */
1968 11,
1969};
1970static const unsigned int fsib_mclk_in_mux[] = {
1971 FSIBCK_MARK,
1972};
1973/* - GETHER ----------------------------------------------------------------- */
1974static const unsigned int gether_rmii_pins[] = {
1975 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1976 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1977};
1978static const unsigned int gether_rmii_mux[] = {
1979 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1980 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1981 RMII_MDC_MARK, RMII_MDIO_MARK,
1982};
1983static const unsigned int gether_mii_pins[] = {
1984 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1985 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1986 * CRS, COL, MDC, MDIO,
1987 */
1988 185, 186, 187, 188, 174, 161, 204,
1989 171, 170, 169, 168, 184, 183, 203,
1990 205, 163, 206, 207,
1991};
1992static const unsigned int gether_mii_mux[] = {
1993 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1994 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1995 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1996 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1997 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1998};
1999static const unsigned int gether_gmii_pins[] = {
2000 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
2001 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
2002 * CRS, COL, MDC, MDIO, REF125CK_MARK,
2003 */
2004 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
2005 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
2006 205, 163, 206, 207,
2007};
2008static const unsigned int gether_gmii_mux[] = {
2009 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
2010 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
2011 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
2012 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
2013 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
2014 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
2015 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2016 RMII_REF125CK_MARK,
2017};
2018static const unsigned int gether_int_pins[] = {
2019 /* PHY_INT */
2020 164,
2021};
2022static const unsigned int gether_int_mux[] = {
2023 ET_PHY_INT_MARK,
2024};
2025static const unsigned int gether_link_pins[] = {
2026 /* LINK */
2027 177,
2028};
2029static const unsigned int gether_link_mux[] = {
2030 ET_LINK_MARK,
2031};
2032static const unsigned int gether_wol_pins[] = {
2033 /* WOL */
2034 175,
2035};
2036static const unsigned int gether_wol_mux[] = {
2037 ET_WOL_MARK,
2038};
2039/* - HDMI ------------------------------------------------------------------- */
2040static const unsigned int hdmi_pins[] = {
2041 /* HPD, CEC */
2042 210, 211,
2043};
2044static const unsigned int hdmi_mux[] = {
2045 HDMI_HPD_MARK, HDMI_CEC_MARK,
2046};
2047/* - INTC ------------------------------------------------------------------- */
2048IRQC_PINS_MUX(0, 0, 2);
2049IRQC_PINS_MUX(0, 1, 13);
2050IRQC_PIN_MUX(1, 20);
2051IRQC_PINS_MUX(2, 0, 11);
2052IRQC_PINS_MUX(2, 1, 12);
2053IRQC_PINS_MUX(3, 0, 10);
2054IRQC_PINS_MUX(3, 1, 14);
2055IRQC_PINS_MUX(4, 0, 15);
2056IRQC_PINS_MUX(4, 1, 172);
2057IRQC_PINS_MUX(5, 0, 0);
2058IRQC_PINS_MUX(5, 1, 1);
2059IRQC_PINS_MUX(6, 0, 121);
2060IRQC_PINS_MUX(6, 1, 173);
2061IRQC_PINS_MUX(7, 0, 120);
2062IRQC_PINS_MUX(7, 1, 209);
2063IRQC_PIN_MUX(8, 119);
2064IRQC_PINS_MUX(9, 0, 118);
2065IRQC_PINS_MUX(9, 1, 210);
2066IRQC_PIN_MUX(10, 19);
2067IRQC_PIN_MUX(11, 104);
2068IRQC_PINS_MUX(12, 0, 42);
2069IRQC_PINS_MUX(12, 1, 97);
2070IRQC_PINS_MUX(13, 0, 64);
2071IRQC_PINS_MUX(13, 1, 98);
2072IRQC_PINS_MUX(14, 0, 63);
2073IRQC_PINS_MUX(14, 1, 99);
2074IRQC_PINS_MUX(15, 0, 62);
2075IRQC_PINS_MUX(15, 1, 100);
2076IRQC_PINS_MUX(16, 0, 68);
2077IRQC_PINS_MUX(16, 1, 211);
2078IRQC_PIN_MUX(17, 69);
2079IRQC_PIN_MUX(18, 70);
2080IRQC_PIN_MUX(19, 71);
2081IRQC_PIN_MUX(20, 67);
2082IRQC_PIN_MUX(21, 202);
2083IRQC_PIN_MUX(22, 95);
2084IRQC_PIN_MUX(23, 96);
2085IRQC_PIN_MUX(24, 180);
2086IRQC_PIN_MUX(25, 38);
2087IRQC_PINS_MUX(26, 0, 58);
2088IRQC_PINS_MUX(26, 1, 81);
2089IRQC_PINS_MUX(27, 0, 57);
2090IRQC_PINS_MUX(27, 1, 168);
2091IRQC_PINS_MUX(28, 0, 56);
2092IRQC_PINS_MUX(28, 1, 169);
2093IRQC_PINS_MUX(29, 0, 50);
2094IRQC_PINS_MUX(29, 1, 170);
2095IRQC_PINS_MUX(30, 0, 49);
2096IRQC_PINS_MUX(30, 1, 171);
2097IRQC_PINS_MUX(31, 0, 41);
2098IRQC_PINS_MUX(31, 1, 167);
1660 2099
1661/* - LCD0 ------------------------------------------------------------------- */ 2100/* - LCD0 ------------------------------------------------------------------- */
1662static const unsigned int lcd0_data8_pins[] = { 2101static const unsigned int lcd0_data8_pins[] = {
@@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
1930static const unsigned int mmc0_ctrl_1_mux[] = { 2369static const unsigned int mmc0_ctrl_1_mux[] = {
1931 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, 2370 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
1932}; 2371};
2372/* - SCIFA0 ----------------------------------------------------------------- */
2373static const unsigned int scifa0_data_pins[] = {
2374 /* RXD, TXD */
2375 197, 198,
2376};
2377static const unsigned int scifa0_data_mux[] = {
2378 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2379};
2380static const unsigned int scifa0_clk_pins[] = {
2381 /* SCK */
2382 188,
2383};
2384static const unsigned int scifa0_clk_mux[] = {
2385 SCIFA0_SCK_MARK,
2386};
2387static const unsigned int scifa0_ctrl_pins[] = {
2388 /* RTS, CTS */
2389 194, 193,
2390};
2391static const unsigned int scifa0_ctrl_mux[] = {
2392 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2393};
2394/* - SCIFA1 ----------------------------------------------------------------- */
2395static const unsigned int scifa1_data_pins[] = {
2396 /* RXD, TXD */
2397 195, 196,
2398};
2399static const unsigned int scifa1_data_mux[] = {
2400 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2401};
2402static const unsigned int scifa1_clk_pins[] = {
2403 /* SCK */
2404 185,
2405};
2406static const unsigned int scifa1_clk_mux[] = {
2407 SCIFA1_SCK_MARK,
2408};
2409static const unsigned int scifa1_ctrl_pins[] = {
2410 /* RTS, CTS */
2411 23, 21,
2412};
2413static const unsigned int scifa1_ctrl_mux[] = {
2414 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2415};
2416/* - SCIFA2 ----------------------------------------------------------------- */
2417static const unsigned int scifa2_data_pins[] = {
2418 /* RXD, TXD */
2419 200, 201,
2420};
2421static const unsigned int scifa2_data_mux[] = {
2422 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2423};
2424static const unsigned int scifa2_clk_0_pins[] = {
2425 /* SCK */
2426 22,
2427};
2428static const unsigned int scifa2_clk_0_mux[] = {
2429 SCIFA2_SCK_PORT22_MARK,
2430};
2431static const unsigned int scifa2_clk_1_pins[] = {
2432 /* SCK */
2433 199,
2434};
2435static const unsigned int scifa2_clk_1_mux[] = {
2436 SCIFA2_SCK_PORT199_MARK,
2437};
2438static const unsigned int scifa2_ctrl_pins[] = {
2439 /* RTS, CTS */
2440 96, 95,
2441};
2442static const unsigned int scifa2_ctrl_mux[] = {
2443 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2444};
2445/* - SCIFA3 ----------------------------------------------------------------- */
2446static const unsigned int scifa3_data_0_pins[] = {
2447 /* RXD, TXD */
2448 174, 175,
2449};
2450static const unsigned int scifa3_data_0_mux[] = {
2451 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2452};
2453static const unsigned int scifa3_clk_0_pins[] = {
2454 /* SCK */
2455 116,
2456};
2457static const unsigned int scifa3_clk_0_mux[] = {
2458 SCIFA3_SCK_PORT116_MARK,
2459};
2460static const unsigned int scifa3_ctrl_0_pins[] = {
2461 /* RTS, CTS */
2462 105, 117,
2463};
2464static const unsigned int scifa3_ctrl_0_mux[] = {
2465 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2466};
2467static const unsigned int scifa3_data_1_pins[] = {
2468 /* RXD, TXD */
2469 159, 160,
2470};
2471static const unsigned int scifa3_data_1_mux[] = {
2472 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2473};
2474static const unsigned int scifa3_clk_1_pins[] = {
2475 /* SCK */
2476 158,
2477};
2478static const unsigned int scifa3_clk_1_mux[] = {
2479 SCIFA3_SCK_PORT158_MARK,
2480};
2481static const unsigned int scifa3_ctrl_1_pins[] = {
2482 /* RTS, CTS */
2483 161, 162,
2484};
2485static const unsigned int scifa3_ctrl_1_mux[] = {
2486 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2487};
2488/* - SCIFA4 ----------------------------------------------------------------- */
2489static const unsigned int scifa4_data_0_pins[] = {
2490 /* RXD, TXD */
2491 12, 13,
2492};
2493static const unsigned int scifa4_data_0_mux[] = {
2494 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2495};
2496static const unsigned int scifa4_data_1_pins[] = {
2497 /* RXD, TXD */
2498 204, 203,
2499};
2500static const unsigned int scifa4_data_1_mux[] = {
2501 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2502};
2503static const unsigned int scifa4_data_2_pins[] = {
2504 /* RXD, TXD */
2505 94, 93,
2506};
2507static const unsigned int scifa4_data_2_mux[] = {
2508 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2509};
2510static const unsigned int scifa4_clk_0_pins[] = {
2511 /* SCK */
2512 21,
2513};
2514static const unsigned int scifa4_clk_0_mux[] = {
2515 SCIFA4_SCK_PORT21_MARK,
2516};
2517static const unsigned int scifa4_clk_1_pins[] = {
2518 /* SCK */
2519 205,
2520};
2521static const unsigned int scifa4_clk_1_mux[] = {
2522 SCIFA4_SCK_PORT205_MARK,
2523};
2524/* - SCIFA5 ----------------------------------------------------------------- */
2525static const unsigned int scifa5_data_0_pins[] = {
2526 /* RXD, TXD */
2527 10, 20,
2528};
2529static const unsigned int scifa5_data_0_mux[] = {
2530 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2531};
2532static const unsigned int scifa5_data_1_pins[] = {
2533 /* RXD, TXD */
2534 207, 208,
2535};
2536static const unsigned int scifa5_data_1_mux[] = {
2537 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2538};
2539static const unsigned int scifa5_data_2_pins[] = {
2540 /* RXD, TXD */
2541 92, 91,
2542};
2543static const unsigned int scifa5_data_2_mux[] = {
2544 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2545};
2546static const unsigned int scifa5_clk_0_pins[] = {
2547 /* SCK */
2548 23,
2549};
2550static const unsigned int scifa5_clk_0_mux[] = {
2551 SCIFA5_SCK_PORT23_MARK,
2552};
2553static const unsigned int scifa5_clk_1_pins[] = {
2554 /* SCK */
2555 206,
2556};
2557static const unsigned int scifa5_clk_1_mux[] = {
2558 SCIFA5_SCK_PORT206_MARK,
2559};
2560/* - SCIFA6 ----------------------------------------------------------------- */
2561static const unsigned int scifa6_data_pins[] = {
2562 /* RXD, TXD */
2563 25, 26,
2564};
2565static const unsigned int scifa6_data_mux[] = {
2566 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2567};
2568static const unsigned int scifa6_clk_pins[] = {
2569 /* SCK */
2570 24,
2571};
2572static const unsigned int scifa6_clk_mux[] = {
2573 SCIFA6_SCK_MARK,
2574};
2575/* - SCIFA7 ----------------------------------------------------------------- */
2576static const unsigned int scifa7_data_pins[] = {
2577 /* RXD, TXD */
2578 0, 1,
2579};
2580static const unsigned int scifa7_data_mux[] = {
2581 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2582};
2583/* - SCIFB ------------------------------------------------------------------ */
2584static const unsigned int scifb_data_0_pins[] = {
2585 /* RXD, TXD */
2586 191, 192,
2587};
2588static const unsigned int scifb_data_0_mux[] = {
2589 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2590};
2591static const unsigned int scifb_clk_0_pins[] = {
2592 /* SCK */
2593 190,
2594};
2595static const unsigned int scifb_clk_0_mux[] = {
2596 SCIFB_SCK_PORT190_MARK,
2597};
2598static const unsigned int scifb_ctrl_0_pins[] = {
2599 /* RTS, CTS */
2600 186, 187,
2601};
2602static const unsigned int scifb_ctrl_0_mux[] = {
2603 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2604};
2605static const unsigned int scifb_data_1_pins[] = {
2606 /* RXD, TXD */
2607 3, 4,
2608};
2609static const unsigned int scifb_data_1_mux[] = {
2610 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2611};
2612static const unsigned int scifb_clk_1_pins[] = {
2613 /* SCK */
2614 2,
2615};
2616static const unsigned int scifb_clk_1_mux[] = {
2617 SCIFB_SCK_PORT2_MARK,
2618};
2619static const unsigned int scifb_ctrl_1_pins[] = {
2620 /* RTS, CTS */
2621 172, 173,
2622};
2623static const unsigned int scifb_ctrl_1_mux[] = {
2624 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2625};
1933/* - SDHI0 ------------------------------------------------------------------ */ 2626/* - SDHI0 ------------------------------------------------------------------ */
1934static const unsigned int sdhi0_data1_pins[] = { 2627static const unsigned int sdhi0_data1_pins[] = {
1935 /* D0 */ 2628 /* D0 */
@@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = {
2052static const unsigned int sdhi2_wp_1_mux[] = { 2745static const unsigned int sdhi2_wp_1_mux[] = {
2053 SDHI2_WP_PORT25_MARK, 2746 SDHI2_WP_PORT25_MARK,
2054}; 2747};
2748/* - TPU0 ------------------------------------------------------------------- */
2749static const unsigned int tpu0_to0_pins[] = {
2750 /* TO */
2751 23,
2752};
2753static const unsigned int tpu0_to0_mux[] = {
2754 TPU0TO0_MARK,
2755};
2756static const unsigned int tpu0_to1_pins[] = {
2757 /* TO */
2758 21,
2759};
2760static const unsigned int tpu0_to1_mux[] = {
2761 TPU0TO1_MARK,
2762};
2763static const unsigned int tpu0_to2_0_pins[] = {
2764 /* TO */
2765 66,
2766};
2767static const unsigned int tpu0_to2_0_mux[] = {
2768 TPU0TO2_PORT66_MARK,
2769};
2770static const unsigned int tpu0_to2_1_pins[] = {
2771 /* TO */
2772 202,
2773};
2774static const unsigned int tpu0_to2_1_mux[] = {
2775 TPU0TO2_PORT202_MARK,
2776};
2777static const unsigned int tpu0_to3_pins[] = {
2778 /* TO */
2779 180,
2780};
2781static const unsigned int tpu0_to3_mux[] = {
2782 TPU0TO3_MARK,
2783};
2055 2784
2056static const struct sh_pfc_pin_group pinmux_groups[] = { 2785static const struct sh_pfc_pin_group pinmux_groups[] = {
2786 SH_PFC_PIN_GROUP(bsc_data8),
2787 SH_PFC_PIN_GROUP(bsc_data16),
2788 SH_PFC_PIN_GROUP(bsc_data32),
2789 SH_PFC_PIN_GROUP(bsc_cs0),
2790 SH_PFC_PIN_GROUP(bsc_cs2),
2791 SH_PFC_PIN_GROUP(bsc_cs4),
2792 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2793 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2794 SH_PFC_PIN_GROUP(bsc_cs5b),
2795 SH_PFC_PIN_GROUP(bsc_cs6a),
2796 SH_PFC_PIN_GROUP(bsc_rd_we8),
2797 SH_PFC_PIN_GROUP(bsc_rd_we16),
2798 SH_PFC_PIN_GROUP(bsc_rd_we32),
2799 SH_PFC_PIN_GROUP(bsc_bs),
2800 SH_PFC_PIN_GROUP(bsc_rdwr),
2801 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2802 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2803 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2804 SH_PFC_PIN_GROUP(ceu0_clk_0),
2805 SH_PFC_PIN_GROUP(ceu0_clk_1),
2806 SH_PFC_PIN_GROUP(ceu0_clk_2),
2807 SH_PFC_PIN_GROUP(ceu0_sync),
2808 SH_PFC_PIN_GROUP(ceu0_field),
2809 SH_PFC_PIN_GROUP(ceu1_data),
2810 SH_PFC_PIN_GROUP(ceu1_clk),
2811 SH_PFC_PIN_GROUP(ceu1_sync),
2812 SH_PFC_PIN_GROUP(ceu1_field),
2813 SH_PFC_PIN_GROUP(fsia_mclk_in),
2814 SH_PFC_PIN_GROUP(fsia_mclk_out),
2815 SH_PFC_PIN_GROUP(fsia_sclk_in),
2816 SH_PFC_PIN_GROUP(fsia_sclk_out),
2817 SH_PFC_PIN_GROUP(fsia_data_in_0),
2818 SH_PFC_PIN_GROUP(fsia_data_in_1),
2819 SH_PFC_PIN_GROUP(fsia_data_out_0),
2820 SH_PFC_PIN_GROUP(fsia_data_out_1),
2821 SH_PFC_PIN_GROUP(fsia_data_out_2),
2822 SH_PFC_PIN_GROUP(fsia_spdif_0),
2823 SH_PFC_PIN_GROUP(fsia_spdif_1),
2824 SH_PFC_PIN_GROUP(fsib_mclk_in),
2825 SH_PFC_PIN_GROUP(gether_rmii),
2826 SH_PFC_PIN_GROUP(gether_mii),
2827 SH_PFC_PIN_GROUP(gether_gmii),
2828 SH_PFC_PIN_GROUP(gether_int),
2829 SH_PFC_PIN_GROUP(gether_link),
2830 SH_PFC_PIN_GROUP(gether_wol),
2831 SH_PFC_PIN_GROUP(hdmi),
2832 SH_PFC_PIN_GROUP(intc_irq0_0),
2833 SH_PFC_PIN_GROUP(intc_irq0_1),
2834 SH_PFC_PIN_GROUP(intc_irq1),
2835 SH_PFC_PIN_GROUP(intc_irq2_0),
2836 SH_PFC_PIN_GROUP(intc_irq2_1),
2837 SH_PFC_PIN_GROUP(intc_irq3_0),
2838 SH_PFC_PIN_GROUP(intc_irq3_1),
2839 SH_PFC_PIN_GROUP(intc_irq4_0),
2840 SH_PFC_PIN_GROUP(intc_irq4_1),
2841 SH_PFC_PIN_GROUP(intc_irq5_0),
2842 SH_PFC_PIN_GROUP(intc_irq5_1),
2843 SH_PFC_PIN_GROUP(intc_irq6_0),
2844 SH_PFC_PIN_GROUP(intc_irq6_1),
2845 SH_PFC_PIN_GROUP(intc_irq7_0),
2846 SH_PFC_PIN_GROUP(intc_irq7_1),
2847 SH_PFC_PIN_GROUP(intc_irq8),
2848 SH_PFC_PIN_GROUP(intc_irq9_0),
2849 SH_PFC_PIN_GROUP(intc_irq9_1),
2850 SH_PFC_PIN_GROUP(intc_irq10),
2851 SH_PFC_PIN_GROUP(intc_irq11),
2852 SH_PFC_PIN_GROUP(intc_irq12_0),
2853 SH_PFC_PIN_GROUP(intc_irq12_1),
2854 SH_PFC_PIN_GROUP(intc_irq13_0),
2855 SH_PFC_PIN_GROUP(intc_irq13_1),
2856 SH_PFC_PIN_GROUP(intc_irq14_0),
2857 SH_PFC_PIN_GROUP(intc_irq14_1),
2858 SH_PFC_PIN_GROUP(intc_irq15_0),
2859 SH_PFC_PIN_GROUP(intc_irq15_1),
2860 SH_PFC_PIN_GROUP(intc_irq16_0),
2861 SH_PFC_PIN_GROUP(intc_irq16_1),
2862 SH_PFC_PIN_GROUP(intc_irq17),
2863 SH_PFC_PIN_GROUP(intc_irq18),
2864 SH_PFC_PIN_GROUP(intc_irq19),
2865 SH_PFC_PIN_GROUP(intc_irq20),
2866 SH_PFC_PIN_GROUP(intc_irq21),
2867 SH_PFC_PIN_GROUP(intc_irq22),
2868 SH_PFC_PIN_GROUP(intc_irq23),
2869 SH_PFC_PIN_GROUP(intc_irq24),
2870 SH_PFC_PIN_GROUP(intc_irq25),
2871 SH_PFC_PIN_GROUP(intc_irq26_0),
2872 SH_PFC_PIN_GROUP(intc_irq26_1),
2873 SH_PFC_PIN_GROUP(intc_irq27_0),
2874 SH_PFC_PIN_GROUP(intc_irq27_1),
2875 SH_PFC_PIN_GROUP(intc_irq28_0),
2876 SH_PFC_PIN_GROUP(intc_irq28_1),
2877 SH_PFC_PIN_GROUP(intc_irq29_0),
2878 SH_PFC_PIN_GROUP(intc_irq29_1),
2879 SH_PFC_PIN_GROUP(intc_irq30_0),
2880 SH_PFC_PIN_GROUP(intc_irq30_1),
2881 SH_PFC_PIN_GROUP(intc_irq31_0),
2882 SH_PFC_PIN_GROUP(intc_irq31_1),
2057 SH_PFC_PIN_GROUP(lcd0_data8), 2883 SH_PFC_PIN_GROUP(lcd0_data8),
2058 SH_PFC_PIN_GROUP(lcd0_data9), 2884 SH_PFC_PIN_GROUP(lcd0_data9),
2059 SH_PFC_PIN_GROUP(lcd0_data12), 2885 SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2084 SH_PFC_PIN_GROUP(mmc0_data4_1), 2910 SH_PFC_PIN_GROUP(mmc0_data4_1),
2085 SH_PFC_PIN_GROUP(mmc0_data8_1), 2911 SH_PFC_PIN_GROUP(mmc0_data8_1),
2086 SH_PFC_PIN_GROUP(mmc0_ctrl_1), 2912 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2913 SH_PFC_PIN_GROUP(scifa0_data),
2914 SH_PFC_PIN_GROUP(scifa0_clk),
2915 SH_PFC_PIN_GROUP(scifa0_ctrl),
2916 SH_PFC_PIN_GROUP(scifa1_data),
2917 SH_PFC_PIN_GROUP(scifa1_clk),
2918 SH_PFC_PIN_GROUP(scifa1_ctrl),
2919 SH_PFC_PIN_GROUP(scifa2_data),
2920 SH_PFC_PIN_GROUP(scifa2_clk_0),
2921 SH_PFC_PIN_GROUP(scifa2_clk_1),
2922 SH_PFC_PIN_GROUP(scifa2_ctrl),
2923 SH_PFC_PIN_GROUP(scifa3_data_0),
2924 SH_PFC_PIN_GROUP(scifa3_clk_0),
2925 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2926 SH_PFC_PIN_GROUP(scifa3_data_1),
2927 SH_PFC_PIN_GROUP(scifa3_clk_1),
2928 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2929 SH_PFC_PIN_GROUP(scifa4_data_0),
2930 SH_PFC_PIN_GROUP(scifa4_data_1),
2931 SH_PFC_PIN_GROUP(scifa4_data_2),
2932 SH_PFC_PIN_GROUP(scifa4_clk_0),
2933 SH_PFC_PIN_GROUP(scifa4_clk_1),
2934 SH_PFC_PIN_GROUP(scifa5_data_0),
2935 SH_PFC_PIN_GROUP(scifa5_data_1),
2936 SH_PFC_PIN_GROUP(scifa5_data_2),
2937 SH_PFC_PIN_GROUP(scifa5_clk_0),
2938 SH_PFC_PIN_GROUP(scifa5_clk_1),
2939 SH_PFC_PIN_GROUP(scifa6_data),
2940 SH_PFC_PIN_GROUP(scifa6_clk),
2941 SH_PFC_PIN_GROUP(scifa7_data),
2942 SH_PFC_PIN_GROUP(scifb_data_0),
2943 SH_PFC_PIN_GROUP(scifb_clk_0),
2944 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2945 SH_PFC_PIN_GROUP(scifb_data_1),
2946 SH_PFC_PIN_GROUP(scifb_clk_1),
2947 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2087 SH_PFC_PIN_GROUP(sdhi0_data1), 2948 SH_PFC_PIN_GROUP(sdhi0_data1),
2088 SH_PFC_PIN_GROUP(sdhi0_data4), 2949 SH_PFC_PIN_GROUP(sdhi0_data4),
2089 SH_PFC_PIN_GROUP(sdhi0_ctrl), 2950 SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2101 SH_PFC_PIN_GROUP(sdhi2_wp_0), 2962 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2102 SH_PFC_PIN_GROUP(sdhi2_cd_1), 2963 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2103 SH_PFC_PIN_GROUP(sdhi2_wp_1), 2964 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2965 SH_PFC_PIN_GROUP(tpu0_to0),
2966 SH_PFC_PIN_GROUP(tpu0_to1),
2967 SH_PFC_PIN_GROUP(tpu0_to2_0),
2968 SH_PFC_PIN_GROUP(tpu0_to2_1),
2969 SH_PFC_PIN_GROUP(tpu0_to3),
2970};
2971
2972static const char * const bsc_groups[] = {
2973 "bsc_data8",
2974 "bsc_data16",
2975 "bsc_data32",
2976 "bsc_cs0",
2977 "bsc_cs2",
2978 "bsc_cs4",
2979 "bsc_cs5a_0",
2980 "bsc_cs5a_1",
2981 "bsc_cs5b",
2982 "bsc_cs6a",
2983 "bsc_rd_we8",
2984 "bsc_rd_we16",
2985 "bsc_rd_we32",
2986 "bsc_bs",
2987 "bsc_rdwr",
2988};
2989
2990static const char * const ceu0_groups[] = {
2991 "ceu0_data_0_7",
2992 "ceu0_data_8_15_0",
2993 "ceu0_data_8_15_1",
2994 "ceu0_clk_0",
2995 "ceu0_clk_1",
2996 "ceu0_clk_2",
2997 "ceu0_sync",
2998 "ceu0_field",
2999};
3000
3001static const char * const ceu1_groups[] = {
3002 "ceu1_data",
3003 "ceu1_clk",
3004 "ceu1_sync",
3005 "ceu1_field",
3006};
3007
3008static const char * const fsia_groups[] = {
3009 "fsia_mclk_in",
3010 "fsia_mclk_out",
3011 "fsia_sclk_in",
3012 "fsia_sclk_out",
3013 "fsia_data_in_0",
3014 "fsia_data_in_1",
3015 "fsia_data_out_0",
3016 "fsia_data_out_1",
3017 "fsia_data_out_2",
3018 "fsia_spdif_0",
3019 "fsia_spdif_1",
3020};
3021
3022static const char * const fsib_groups[] = {
3023 "fsib_mclk_in",
3024};
3025
3026static const char * const gether_groups[] = {
3027 "gether_rmii",
3028 "gether_mii",
3029 "gether_gmii",
3030 "gether_int",
3031 "gether_link",
3032 "gether_wol",
3033};
3034
3035static const char * const hdmi_groups[] = {
3036 "hdmi",
3037};
3038
3039static const char * const intc_groups[] = {
3040 "intc_irq0_0",
3041 "intc_irq0_1",
3042 "intc_irq1",
3043 "intc_irq2_0",
3044 "intc_irq2_1",
3045 "intc_irq3_0",
3046 "intc_irq3_1",
3047 "intc_irq4_0",
3048 "intc_irq4_1",
3049 "intc_irq5_0",
3050 "intc_irq5_1",
3051 "intc_irq6_0",
3052 "intc_irq6_1",
3053 "intc_irq7_0",
3054 "intc_irq7_1",
3055 "intc_irq8",
3056 "intc_irq9_0",
3057 "intc_irq9_1",
3058 "intc_irq10",
3059 "intc_irq11",
3060 "intc_irq12_0",
3061 "intc_irq12_1",
3062 "intc_irq13_0",
3063 "intc_irq13_1",
3064 "intc_irq14_0",
3065 "intc_irq14_1",
3066 "intc_irq15_0",
3067 "intc_irq15_1",
3068 "intc_irq16_0",
3069 "intc_irq16_1",
3070 "intc_irq17",
3071 "intc_irq18",
3072 "intc_irq19",
3073 "intc_irq20",
3074 "intc_irq21",
3075 "intc_irq22",
3076 "intc_irq23",
3077 "intc_irq24",
3078 "intc_irq25",
3079 "intc_irq26_0",
3080 "intc_irq26_1",
3081 "intc_irq27_0",
3082 "intc_irq27_1",
3083 "intc_irq28_0",
3084 "intc_irq28_1",
3085 "intc_irq29_0",
3086 "intc_irq29_1",
3087 "intc_irq30_0",
3088 "intc_irq30_1",
3089 "intc_irq31_0",
3090 "intc_irq31_1",
2104}; 3091};
2105 3092
2106static const char * const lcd0_groups[] = { 3093static const char * const lcd0_groups[] = {
@@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = {
2142 "mmc0_ctrl_1", 3129 "mmc0_ctrl_1",
2143}; 3130};
2144 3131
3132static const char * const scifa0_groups[] = {
3133 "scifa0_data",
3134 "scifa0_clk",
3135 "scifa0_ctrl",
3136};
3137
3138static const char * const scifa1_groups[] = {
3139 "scifa1_data",
3140 "scifa1_clk",
3141 "scifa1_ctrl",
3142};
3143
3144static const char * const scifa2_groups[] = {
3145 "scifa2_data",
3146 "scifa2_clk_0",
3147 "scifa2_clk_1",
3148 "scifa2_ctrl",
3149};
3150
3151static const char * const scifa3_groups[] = {
3152 "scifa3_data_0",
3153 "scifa3_clk_0",
3154 "scifa3_ctrl_0",
3155 "scifa3_data_1",
3156 "scifa3_clk_1",
3157 "scifa3_ctrl_1",
3158};
3159
3160static const char * const scifa4_groups[] = {
3161 "scifa4_data_0",
3162 "scifa4_data_1",
3163 "scifa4_data_2",
3164 "scifa4_clk_0",
3165 "scifa4_clk_1",
3166};
3167
3168static const char * const scifa5_groups[] = {
3169 "scifa5_data_0",
3170 "scifa5_data_1",
3171 "scifa5_data_2",
3172 "scifa5_clk_0",
3173 "scifa5_clk_1",
3174};
3175
3176static const char * const scifa6_groups[] = {
3177 "scifa6_data",
3178 "scifa6_clk",
3179};
3180
3181static const char * const scifa7_groups[] = {
3182 "scifa7_data",
3183};
3184
3185static const char * const scifb_groups[] = {
3186 "scifb_data_0",
3187 "scifb_clk_0",
3188 "scifb_ctrl_0",
3189 "scifb_data_1",
3190 "scifb_clk_1",
3191 "scifb_ctrl_1",
3192};
3193
2145static const char * const sdhi0_groups[] = { 3194static const char * const sdhi0_groups[] = {
2146 "sdhi0_data1", 3195 "sdhi0_data1",
2147 "sdhi0_data4", 3196 "sdhi0_data4",
@@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = {
2168 "sdhi2_wp_1", 3217 "sdhi2_wp_1",
2169}; 3218};
2170 3219
3220static const char * const tpu0_groups[] = {
3221 "tpu0_to0",
3222 "tpu0_to1",
3223 "tpu0_to2_0",
3224 "tpu0_to2_1",
3225 "tpu0_to3",
3226};
3227
2171static const struct sh_pfc_function pinmux_functions[] = { 3228static const struct sh_pfc_function pinmux_functions[] = {
3229 SH_PFC_FUNCTION(bsc),
3230 SH_PFC_FUNCTION(ceu0),
3231 SH_PFC_FUNCTION(ceu1),
3232 SH_PFC_FUNCTION(fsia),
3233 SH_PFC_FUNCTION(fsib),
3234 SH_PFC_FUNCTION(gether),
3235 SH_PFC_FUNCTION(hdmi),
3236 SH_PFC_FUNCTION(intc),
2172 SH_PFC_FUNCTION(lcd0), 3237 SH_PFC_FUNCTION(lcd0),
2173 SH_PFC_FUNCTION(lcd1), 3238 SH_PFC_FUNCTION(lcd1),
2174 SH_PFC_FUNCTION(mmc0), 3239 SH_PFC_FUNCTION(mmc0),
3240 SH_PFC_FUNCTION(scifa0),
3241 SH_PFC_FUNCTION(scifa1),
3242 SH_PFC_FUNCTION(scifa2),
3243 SH_PFC_FUNCTION(scifa3),
3244 SH_PFC_FUNCTION(scifa4),
3245 SH_PFC_FUNCTION(scifa5),
3246 SH_PFC_FUNCTION(scifa6),
3247 SH_PFC_FUNCTION(scifa7),
3248 SH_PFC_FUNCTION(scifb),
2175 SH_PFC_FUNCTION(sdhi0), 3249 SH_PFC_FUNCTION(sdhi0),
2176 SH_PFC_FUNCTION(sdhi1), 3250 SH_PFC_FUNCTION(sdhi1),
2177 SH_PFC_FUNCTION(sdhi2), 3251 SH_PFC_FUNCTION(sdhi2),
3252 SH_PFC_FUNCTION(tpu0),
2178}; 3253};
2179 3254
2180#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 3255#undef PORTCR
2181 3256#define PORTCR(nr, reg) \
2182static const struct pinmux_func pinmux_func_gpios[] = { 3257 { \
2183 /* IRQ */ 3258 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2184 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), 3259 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2185 GPIO_FN(IRQ1), 3260 PORT##nr##_FN0, PORT##nr##_FN1, \
2186 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), 3261 PORT##nr##_FN2, PORT##nr##_FN3, \
2187 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), 3262 PORT##nr##_FN4, PORT##nr##_FN5, \
2188 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), 3263 PORT##nr##_FN6, PORT##nr##_FN7 } \
2189 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), 3264 }
2190 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
2191 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
2192 GPIO_FN(IRQ8),
2193 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
2194 GPIO_FN(IRQ10),
2195 GPIO_FN(IRQ11),
2196 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
2197 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
2198 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
2199 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
2200 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
2201 GPIO_FN(IRQ17),
2202 GPIO_FN(IRQ18),
2203 GPIO_FN(IRQ19),
2204 GPIO_FN(IRQ20),
2205 GPIO_FN(IRQ21),
2206 GPIO_FN(IRQ22),
2207 GPIO_FN(IRQ23),
2208 GPIO_FN(IRQ24),
2209 GPIO_FN(IRQ25),
2210 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
2211 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
2212 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
2213 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
2214 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
2215 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
2216
2217 /* Function */
2218
2219 /* DBGT */
2220 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
2221 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
2222 GPIO_FN(DBGMD21),
2223
2224 /* FSI-A */
2225 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
2226 GPIO_FN(FSIAISLD_PORT5),
2227 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
2228 GPIO_FN(FSIASPDIF_PORT18),
2229 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
2230 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
2231 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
2232
2233 /* FSI-B */
2234 GPIO_FN(FSIBCK),
2235
2236 /* FMSI */
2237 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
2238 GPIO_FN(FMSISLD_PORT6),
2239 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
2240 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
2241 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
2242 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
2243
2244 /* SCIFA0 */
2245 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
2246 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
2247
2248 /* SCIFA1 */
2249 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
2250 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
2251
2252 /* SCIFA2 */
2253 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
2254 GPIO_FN(SCIFA2_SCK_PORT199),
2255 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
2256 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
2257
2258 /* SCIFA3 */
2259 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
2260 GPIO_FN(SCIFA3_SCK_PORT116),
2261 GPIO_FN(SCIFA3_CTS_PORT117),
2262 GPIO_FN(SCIFA3_RXD_PORT174),
2263 GPIO_FN(SCIFA3_TXD_PORT175),
2264
2265 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
2266 GPIO_FN(SCIFA3_SCK_PORT158),
2267 GPIO_FN(SCIFA3_CTS_PORT162),
2268 GPIO_FN(SCIFA3_RXD_PORT159),
2269 GPIO_FN(SCIFA3_TXD_PORT160),
2270
2271 /* SCIFA4 */
2272 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
2273 GPIO_FN(SCIFA4_TXD_PORT13),
2274
2275 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
2276 GPIO_FN(SCIFA4_TXD_PORT203),
2277
2278 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
2279 GPIO_FN(SCIFA4_TXD_PORT93),
2280
2281 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
2282 GPIO_FN(SCIFA4_SCK_PORT205),
2283
2284 /* SCIFA5 */
2285 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
2286 GPIO_FN(SCIFA5_RXD_PORT10),
2287
2288 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
2289 GPIO_FN(SCIFA5_TXD_PORT208),
2290
2291 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
2292 GPIO_FN(SCIFA5_RXD_PORT92),
2293
2294 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
2295 GPIO_FN(SCIFA5_SCK_PORT206),
2296
2297 /* SCIFA6 */
2298 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
2299
2300 /* SCIFA7 */
2301 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
2302
2303 /* SCIFAB */
2304 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
2305 GPIO_FN(SCIFB_RXD_PORT191),
2306 GPIO_FN(SCIFB_TXD_PORT192),
2307 GPIO_FN(SCIFB_RTS_PORT186),
2308 GPIO_FN(SCIFB_CTS_PORT187),
2309
2310 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
2311 GPIO_FN(SCIFB_RXD_PORT3),
2312 GPIO_FN(SCIFB_TXD_PORT4),
2313 GPIO_FN(SCIFB_RTS_PORT172),
2314 GPIO_FN(SCIFB_CTS_PORT173),
2315
2316 /* RSPI */
2317 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
2318 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
2319 GPIO_FN(RSPI_MISO_A),
2320
2321 /* VIO CKO */
2322 GPIO_FN(VIO_CKO1),
2323 GPIO_FN(VIO_CKO2),
2324 GPIO_FN(VIO_CKO_1),
2325 GPIO_FN(VIO_CKO),
2326
2327 /* VIO0 */
2328 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
2329 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
2330 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
2331 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
2332 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
2333 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
2334
2335 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
2336 GPIO_FN(VIO0_D14_PORT25),
2337 GPIO_FN(VIO0_D15_PORT24),
2338
2339 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
2340 GPIO_FN(VIO0_D14_PORT95),
2341 GPIO_FN(VIO0_D15_PORT96),
2342
2343 /* VIO1 */
2344 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
2345 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
2346 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
2347 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
2348
2349 /* TPU0 */
2350 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
2351 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
2352 GPIO_FN(TPU0TO2_PORT202),
2353
2354 /* SSP1 0 */
2355 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
2356 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
2357 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
2358 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
2359
2360 /* SSP1 1 */
2361 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
2362 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
2363 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
2364
2365 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
2366 GPIO_FN(STP1_IPEN_PORT187),
2367
2368 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
2369 GPIO_FN(STP1_IPEN_PORT193),
2370
2371 /* SIM */
2372 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
2373 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
2374 GPIO_FN(SIM_D_PORT199),
2375
2376 /* MSIOF2 */
2377 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
2378 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
2379 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
2380 GPIO_FN(MSIOF2_RSCK),
2381
2382 /* KEYSC */
2383 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
2384 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
2385 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
2386 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
2387 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
2388
2389 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
2390 GPIO_FN(KEYIN1_PORT44),
2391 GPIO_FN(KEYIN2_PORT45),
2392 GPIO_FN(KEYIN3_PORT46),
2393
2394 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
2395 GPIO_FN(KEYIN1_PORT57),
2396 GPIO_FN(KEYIN2_PORT56),
2397 GPIO_FN(KEYIN3_PORT55),
2398
2399 /* VOU */
2400 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
2401 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
2402 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
2403 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
2404 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
2405 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
2406 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
2407
2408 /* MEMC */
2409 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
2410 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
2411 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
2412 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
2413 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
2414 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
2415 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
2416 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
2417 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
2418 GPIO_FN(MEMC_A0),
2419
2420 /* MSIOF0 */
2421 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
2422 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
2423 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
2424 GPIO_FN(MSIOF0_TSYNC),
2425
2426 /* MSIOF1 */
2427 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
2428 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
2429
2430 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
2431 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
2432 GPIO_FN(MSIOF1_TSYNC_PORT120),
2433 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
2434
2435 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
2436 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
2437 GPIO_FN(MSIOF1_RXD_PORT75),
2438 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
2439
2440 /* GPIO */
2441 GPIO_FN(GPO0), GPIO_FN(GPI0),
2442 GPIO_FN(GPO1), GPIO_FN(GPI1),
2443
2444 /* USB0 */
2445 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
2446
2447 /* USB1 */
2448 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
2449
2450 /* BBIF1 */
2451 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
2452 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
2453 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
2454
2455 /* BBIF2 */
2456 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
2457 GPIO_FN(BBIF2_RXD2_PORT60),
2458 GPIO_FN(BBIF2_TSYNC2_PORT6),
2459 GPIO_FN(BBIF2_TSCK2_PORT59),
2460
2461 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
2462 GPIO_FN(BBIF2_TXD2_PORT183),
2463 GPIO_FN(BBIF2_TSCK2_PORT89),
2464 GPIO_FN(BBIF2_TSYNC2_PORT184),
2465
2466 /* BSC / FLCTL / PCMCIA */
2467 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
2468 GPIO_FN(CS5B), GPIO_FN(CS6A),
2469 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
2470 GPIO_FN(CS5A_PORT19),
2471 GPIO_FN(IOIS16), /* ? */
2472
2473 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
2474 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
2475 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
2476 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
2477 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
2478 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
2479 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
2480 GPIO_FN(A26),
2481
2482 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
2483 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
2484 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
2485 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
2486 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
2487 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
2488 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
2489 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
2490 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
2491 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
2492 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
2493 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
2494
2495 GPIO_FN(WE0_FWE), /* share with FLCTL */
2496 GPIO_FN(WE1),
2497 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
2498 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
2499 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
2500 GPIO_FN(RD_FSC), /* share with FLCTL */
2501 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
2502 GPIO_FN(WAIT_PORT90),
2503
2504 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
2505
2506 /* IRDA */
2507 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
2508
2509 /* ATAPI */
2510 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
2511 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
2512 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
2513 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
2514 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
2515 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
2516 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
2517 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
2518 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
2519 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
2520
2521 /* RMII */
2522 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
2523 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
2524 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
2525 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
2526
2527 /* GEther */
2528 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
2529 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
2530 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
2531 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
2532 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
2533 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
2534 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
2535 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
2536 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
2537 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
2538 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
2539 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
2540
2541 /* DMA0 */
2542 GPIO_FN(DREQ0), GPIO_FN(DACK0),
2543
2544 /* DMA1 */
2545 GPIO_FN(DREQ1), GPIO_FN(DACK1),
2546
2547 /* SYSC */
2548 GPIO_FN(RESETOUTS),
2549
2550 /* IRREM */
2551 GPIO_FN(IROUT),
2552
2553 /* LCDC */
2554 GPIO_FN(LCDC0_SELECT),
2555 GPIO_FN(LCDC1_SELECT),
2556
2557 /* SDENC */
2558 GPIO_FN(SDENC_CPG),
2559 GPIO_FN(SDENC_DV_CLKI),
2560
2561 /* HDMI */
2562 GPIO_FN(HDMI_HPD),
2563 GPIO_FN(HDMI_CEC),
2564
2565 /* SYSC */
2566 GPIO_FN(RESETP_PULLUP),
2567 GPIO_FN(RESETP_PLAIN),
2568
2569 /* DEBUG */
2570 GPIO_FN(EDEBGREQ_PULLDOWN),
2571 GPIO_FN(EDEBGREQ_PULLUP),
2572
2573 GPIO_FN(TRACEAUD_FROM_VIO),
2574 GPIO_FN(TRACEAUD_FROM_LCDC0),
2575 GPIO_FN(TRACEAUD_FROM_MEMC),
2576};
2577 3265
2578static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3266static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2579 PORTCR(0, 0xe6050000), /* PORT0CR */ 3267 PORTCR(0, 0xe6050000), /* PORT0CR */
@@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2994}; 3682};
2995 3683
2996static const struct pinmux_irq pinmux_irqs[] = { 3684static const struct pinmux_irq pinmux_irqs[] = {
2997 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ 3685 PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */
2998 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ 3686 PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */
2999 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ 3687 PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */
3000 PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ 3688 PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */
3001 PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ 3689 PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */
3002 PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ 3690 PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */
3003 PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ 3691 PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */
3004 PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ 3692 PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */
3005 PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ 3693 PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */
3006 PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ 3694 PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */
3007 PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ 3695 PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */
3008 PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ 3696 PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */
3009 PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ 3697 PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */
3010 PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ 3698 PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */
3011 PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ 3699 PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */
3012 PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ 3700 PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */
3013 PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ 3701 PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */
3014 PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ 3702 PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */
3015 PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ 3703 PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */
3016 PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ 3704 PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */
3017 PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ 3705 PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */
3018 PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ 3706 PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */
3019 PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ 3707 PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */
3020 PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ 3708 PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */
3021 PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ 3709 PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */
3022 PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ 3710 PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */
3023 PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ 3711 PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */
3024 PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ 3712 PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */
3025 PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ 3713 PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */
3026 PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ 3714 PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */
3027 PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ 3715 PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */
3028 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ 3716 PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
3717};
3718
3719#define PORTnCR_PULMD_OFF (0 << 6)
3720#define PORTnCR_PULMD_DOWN (2 << 6)
3721#define PORTnCR_PULMD_UP (3 << 6)
3722#define PORTnCR_PULMD_MASK (3 << 6)
3723
3724struct r8a7740_portcr_group {
3725 unsigned int end_pin;
3726 unsigned int offset;
3727};
3728
3729static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3730 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3731};
3732
3733static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3734{
3735 unsigned int i;
3736
3737 for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3738 const struct r8a7740_portcr_group *group =
3739 &r8a7740_portcr_offsets[i];
3740
3741 if (i <= group->end_pin)
3742 return pfc->window->virt + group->offset + pin;
3743 }
3744
3745 return NULL;
3746}
3747
3748static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3749{
3750 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3751 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3752
3753 switch (value) {
3754 case PORTnCR_PULMD_UP:
3755 return PIN_CONFIG_BIAS_PULL_UP;
3756 case PORTnCR_PULMD_DOWN:
3757 return PIN_CONFIG_BIAS_PULL_DOWN;
3758 case PORTnCR_PULMD_OFF:
3759 default:
3760 return PIN_CONFIG_BIAS_DISABLE;
3761 }
3762}
3763
3764static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3765 unsigned int bias)
3766{
3767 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3768 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3769
3770 switch (bias) {
3771 case PIN_CONFIG_BIAS_PULL_UP:
3772 value |= PORTnCR_PULMD_UP;
3773 break;
3774 case PIN_CONFIG_BIAS_PULL_DOWN:
3775 value |= PORTnCR_PULMD_DOWN;
3776 break;
3777 }
3778
3779 iowrite8(value, addr);
3780}
3781
3782static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
3783 .get_bias = r8a7740_pinmux_get_bias,
3784 .set_bias = r8a7740_pinmux_set_bias,
3029}; 3785};
3030 3786
3031const struct sh_pfc_soc_info r8a7740_pinmux_info = { 3787const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3032 .name = "r8a7740_pfc", 3788 .name = "r8a7740_pfc",
3789 .ops = &r8a7740_pinmux_ops,
3790
3033 .input = { PINMUX_INPUT_BEGIN, 3791 .input = { PINMUX_INPUT_BEGIN,
3034 PINMUX_INPUT_END }, 3792 PINMUX_INPUT_END },
3035 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
3036 PINMUX_INPUT_PULLUP_END },
3037 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
3038 PINMUX_INPUT_PULLDOWN_END },
3039 .output = { PINMUX_OUTPUT_BEGIN, 3793 .output = { PINMUX_OUTPUT_BEGIN,
3040 PINMUX_OUTPUT_END }, 3794 PINMUX_OUTPUT_END },
3041 .function = { PINMUX_FUNCTION_BEGIN, 3795 .function = { PINMUX_FUNCTION_BEGIN,
@@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3048 .functions = pinmux_functions, 3802 .functions = pinmux_functions,
3049 .nr_functions = ARRAY_SIZE(pinmux_functions), 3803 .nr_functions = ARRAY_SIZE(pinmux_functions),
3050 3804
3051 .func_gpios = pinmux_func_gpios,
3052 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3053
3054 .cfg_regs = pinmux_config_regs, 3805 .cfg_regs = pinmux_config_regs,
3055 .data_regs = pinmux_data_regs, 3806 .data_regs = pinmux_data_regs,
3056 3807
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 000000000000..1dcbabcd7b3c
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2783 @@
1/*
2 * r8a7778 processor support - PFC hardware block
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * based on
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/platform_data/gpio-rcar.h>
23#include <linux/kernel.h>
24#include "sh_pfc.h"
25
26#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
27
28#define PORT_GP_32(bank, fn, sfx) \
29 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
30 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
31 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
32 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
33 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
34 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
35 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
36 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
37 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
38 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
39 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
40 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
41 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
42 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
43 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
44 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
45
46#define PORT_GP_27(bank, fn, sfx) \
47 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
48 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
49 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
50 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
51 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
52 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
53 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
54 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
55 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
56 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
57 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
58 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
59 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
60 PORT_GP_1(bank, 26, fn, sfx)
61
62#define CPU_ALL_PORT(fn, sfx) \
63 PORT_GP_32(0, fn, sfx), \
64 PORT_GP_32(1, fn, sfx), \
65 PORT_GP_32(2, fn, sfx), \
66 PORT_GP_32(3, fn, sfx), \
67 PORT_GP_27(4, fn, sfx)
68
69#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
70
71#define _GP_GPIO(bank, pin, _name, sfx) \
72 [RCAR_GP_PIN(bank, pin)] = { \
73 .name = __stringify(_name), \
74 .enum_id = _name##_DATA, \
75 }
76
77#define _GP_DATA(bank, pin, name, sfx) \
78 PINMUX_DATA(name##_DATA, name##_FN)
79
80#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
81#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
82#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
83
84#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn)
85#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
86#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
87#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
88
89enum {
90 PINMUX_RESERVED = 0,
91
92 PINMUX_DATA_BEGIN,
93 GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
94 PINMUX_DATA_END,
95
96 PINMUX_FUNCTION_BEGIN,
97 GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
98
99 /* GPSR0 */
100 FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2,
101 FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1,
102 FN_A2, FN_A3, FN_IP0_15, FN_IP0_16,
103 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20,
104 FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24,
105 FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28,
106 FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1,
107 FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11,
108
109 /* GPSR1 */
110 FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25,
111 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6,
112 FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17,
113 FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2,
114 FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13,
115 FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24,
116 FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30,
117 FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4,
118
119 /* GPSR2 */
120 FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11,
121 FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21,
122 FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0,
123 FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7,
124 FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13,
125 FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
126 FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29,
127 FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7,
128
129 /* GPSR3 */
130 FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10,
131 FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16,
132 FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22,
133 FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30,
134 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6,
135 FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
136 FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29,
137 FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9,
138
139 /* GPSR4 */
140 FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19,
141 FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0,
142 FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12,
143 FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24,
144 FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6,
145 FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19,
146 FN_IP10_24_22, FN_AVS1, FN_AVS2,
147
148 /* IPSR0 */
149 FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0,
150 FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B,
151 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C,
152 FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A,
153 FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A,
154 FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0,
155 FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5,
156 FN_A6, FN_A7, FN_A8, FN_A9,
157 FN_A10, FN_A11, FN_A12, FN_A13,
158 FN_A14, FN_A15, FN_A16, FN_A17,
159 FN_A18, FN_A19,
160
161 /* IPSR1 */
162 FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B,
163 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
164 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
165 FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24,
166 FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A,
167 FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A,
168 FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT,
169 FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B,
170 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
171 FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR,
172 FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0,
173 FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1,
174 FN_MMC_D4,
175
176 /* IPSR2 */
177 FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2,
178 FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3,
179 FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4,
180 FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A,
181 FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A,
182 FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0,
183 FN_PWM0_C, FN_D0, FN_D1, FN_D2,
184 FN_D3, FN_D4, FN_D5, FN_D6,
185 FN_D7, FN_D8, FN_D9, FN_D10,
186 FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK,
187 FN_IRQ1_A,
188
189 /* IPSR3 */
190 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
191 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
192 FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B,
193 FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A,
194 FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A,
195 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
196 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B,
197 FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0,
198 FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2,
199 FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4,
200 FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3,
201 FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
202 FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3,
203 FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5,
204 FN_DU0_DR6, FN_LCDOUT6,
205
206 /* IPSR4 */
207 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
208 FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D,
209 FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9,
210 FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D,
211 FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10,
212 FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12,
213 FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B,
214 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7,
215 FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B,
216 FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6,
217 FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B,
218 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
219 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A,
220 FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2,
221 FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19,
222 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20,
223
224 /* IPSR5 */
225 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B,
226 FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B,
227 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN,
228 FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK,
229 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A,
230 FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
231 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
232 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
233 FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP,
234 FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK,
235 FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB,
236 FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D,
237 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
238 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
239 FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B,
240 FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B,
241 FN_RX2_A, FN_CAN0_RX_B,
242
243 /* IPSR6 */
244 FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B,
245 FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B,
246 FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5,
247 FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5,
248 FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8,
249 FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9,
250 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
251 FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
252 FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12,
253 FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13,
254 FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
255 FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0,
256 FN_ARM_TRACEDATA_15,
257 FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST,
258 FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK,
259 FN_SD0_DAT2, FN_SUB_TDI,
260
261 /* IPSR7 */
262 FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A,
263 FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A,
264 FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A,
265 FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A,
266 FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC,
267 FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C,
268 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C,
269 FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A,
270 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
271 FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B,
272 FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A,
273 FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2,
274 FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B,
275
276 /* IPSR8 */
277 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
278 FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0,
279 FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1,
280 FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2,
281 FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3,
282 FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4,
283 FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5,
284 FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B,
285 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A,
286 FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
287 FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4,
288 FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B,
289 FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B,
290
291 /* IPSR9 */
292 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
293 FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7,
294 FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK,
295 FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A,
296 FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2,
297 FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7,
298 FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV,
299 FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN,
300 FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER,
301 FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A,
302 FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C,
303 FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A,
304 FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C,
305 FN_RX2_D, FN_SCL2_C,
306
307 /* IPSR10 */
308 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1,
309 FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A,
310 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1,
311 FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP,
312 FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A,
313 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
314 FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A,
315 FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B,
316 FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B,
317 FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A,
318 FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B,
319 FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B,
320 FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C,
321
322 /* SEL */
323 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
324 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
325 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
326 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
327 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
328 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
329 FN_SEL_SSI2_A, FN_SEL_SSI2_B,
330 FN_SEL_SSI1_A, FN_SEL_SSI1_B,
331 FN_SEL_VI1_A, FN_SEL_VI1_B,
332 FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D,
333 FN_SEL_SD2_A, FN_SEL_SD2_B,
334 FN_SEL_SD1_A, FN_SEL_SD1_B,
335 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
336 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C,
337 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
338 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
339 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
340 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
341 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
342 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
343 FN_SEL_CAN1_A, FN_SEL_CAN1_B,
344 FN_SEL_CAN0_A, FN_SEL_CAN0_B,
345 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
346 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
347 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
348 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
349 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C,
350 FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D,
351 FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C,
352 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
353 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
354 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
355 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
356 FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C,
357 FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C,
358 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
359 PINMUX_FUNCTION_END,
360
361 PINMUX_MARK_BEGIN,
362
363 /* GPSR0 */
364 PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK,
365
366 /* GPSR1 */
367 WE0_MARK,
368
369 /* GPSR2 */
370 AUDIO_CLKA_MARK,
371 AUDIO_CLKB_MARK,
372
373 /* GPSR3 */
374 SSI_SCK34_MARK,
375
376 /* GPSR4 */
377 AVS1_MARK,
378 AVS2_MARK,
379
380 VI0_R0_C_MARK, /* see sel_vi0 */
381 VI0_R1_C_MARK, /* see sel_vi0 */
382 VI0_R2_C_MARK, /* see sel_vi0 */
383 /* VI0_R3_C_MARK, */
384 VI0_R4_C_MARK, /* see sel_vi0 */
385 VI0_R5_C_MARK, /* see sel_vi0 */
386
387 VI0_R0_D_MARK, /* see sel_vi0 */
388 VI0_R1_D_MARK, /* see sel_vi0 */
389 VI0_R2_D_MARK, /* see sel_vi0 */
390 VI0_R3_D_MARK, /* see sel_vi0 */
391 VI0_R4_D_MARK, /* see sel_vi0 */
392 VI0_R5_D_MARK, /* see sel_vi0 */
393
394 /* IPSR0 */
395 PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK,
396 ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK,
397 TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK,
398 GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK,
399 SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK,
400 ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK,
401 MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK,
402 A4_MARK, A5_MARK, A6_MARK, A7_MARK,
403 A8_MARK, A9_MARK, A10_MARK, A11_MARK,
404 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
405 A16_MARK, A17_MARK, A18_MARK, A19_MARK,
406
407 /* IPSR1 */
408 A20_MARK, HSPI_CS1_B_MARK, A21_MARK,
409 HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK,
410 RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK,
411 TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK,
412 SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK,
413 HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK,
414 MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK,
415 RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK,
416 HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK,
417 HSPI_RX1_B_MARK, SSI_SCK1_B_MARK,
418 ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK,
419 MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK,
420 ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK,
421 TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK,
422
423 /* IPSR2 */
424 SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK,
425 SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK,
426 SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK,
427 EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK,
428 MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK,
429 DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK,
430 DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK,
431 D1_MARK, D2_MARK, D3_MARK, D4_MARK,
432 D5_MARK, D6_MARK, D7_MARK, D8_MARK,
433 D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK,
434 IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK,
435
436 /* IPSR3 */
437 MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK,
438 MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK,
439 SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK,
440 CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK,
441 TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK,
442 RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK,
443 SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK,
444 HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK,
445 HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK,
446 DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK,
447 SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK,
448 SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK,
449 ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK,
450 TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
451 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
452 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
453
454 /* IPSR4 */
455 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
456 AUDATA4_MARK, ARM_TRACEDATA_4_MARK,
457 TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK,
458 LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK,
459 RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK,
460 LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK,
461 LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK,
462 TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK,
463 DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK,
464 VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK,
465 ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK,
466 ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK,
467 VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK,
468 ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK,
469 TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
470 VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK,
471 DU0_DB4_MARK, LCDOUT20_MARK,
472
473 /* IPSR5 */
474 VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK,
475 DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK,
476 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK,
477 QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
478 QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK,
479 AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK,
480 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
481 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
482 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
483 QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK,
484 DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK,
485 BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK,
486 AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK,
487 SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK,
488 TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK,
489 RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK,
490 SSI_SCK2_A_MARK, HSPI_CS0_B_MARK,
491 TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK,
492 HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK,
493
494 /* IPSR6 */
495 SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK,
496 CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK,
497 BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK,
498 HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK,
499 RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK,
500 RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK,
501 SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
502 SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK,
503 SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK,
504 TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
505 SSI_SDATA2_MARK, HSPI_CS2_A_MARK,
506 ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK,
507 ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK,
508 SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK,
509 SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK,
510 SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK,
511 SD0_DAT2_MARK, SUB_TDI_MARK,
512
513 /* IPSR7 */
514 SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK,
515 SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK,
516 HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK,
517 HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK,
518 HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK,
519 VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK,
520 TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK,
521 IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK,
522 CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK,
523 VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK,
524 RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK,
525 VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK,
526 TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK,
527 DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK,
528
529 /* IPSR8 */
530 VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK,
531 HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK,
532 DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK,
533 DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK,
534 DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK,
535 DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK,
536 DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK,
537 DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK,
538 VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK,
539 PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK,
540 RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK,
541 DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK,
542 VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK,
543
544 /* IPSR9 */
545 VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK,
546 DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK,
547 VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK,
548 VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK,
549 VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK,
550 PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK,
551 DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK,
552 ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK,
553 VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK,
554 TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK,
555 IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK,
556 DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK,
557 BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK,
558 DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK,
559 RX2_D_MARK, SCL2_C_MARK,
560
561 /* IPSR10 */
562 SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK,
563 ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK,
564 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK,
565 ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK,
566 DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK,
567 CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK,
568 ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK,
569 PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK,
570 DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK,
571 GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK,
572 DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK,
573 GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK,
574 EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK,
575 REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK,
576 EX_WAIT2_B_MARK, DACK0_B_MARK,
577 HSPI_TX2_B_MARK, CAN_CLK_C_MARK,
578
579 PINMUX_MARK_END,
580};
581
582static const pinmux_enum_t pinmux_data[] = {
583 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
584
585 PINMUX_DATA(PENC0_MARK, FN_PENC0),
586 PINMUX_DATA(PENC1_MARK, FN_PENC1),
587 PINMUX_DATA(A1_MARK, FN_A1),
588 PINMUX_DATA(A2_MARK, FN_A2),
589 PINMUX_DATA(A3_MARK, FN_A3),
590 PINMUX_DATA(WE0_MARK, FN_WE0),
591 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
592 PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB),
593 PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34),
594 PINMUX_DATA(AVS1_MARK, FN_AVS1),
595 PINMUX_DATA(AVS2_MARK, FN_AVS2),
596
597 /* IPSR0 */
598 PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT),
599 PINMUX_IPSR_DATA(IP0_1_0, PWM1),
600
601 PINMUX_IPSR_DATA(IP0_4_2, AUDATA0),
602 PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0),
603 PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
604 PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0),
605 PINMUX_IPSR_DATA(IP0_4_2, TX2_E),
606 PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
607
608 PINMUX_IPSR_DATA(IP0_7_5, AUDATA1),
609 PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1),
610 PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
611 PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1),
612 PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
613 PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
614
615 PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
616 PINMUX_IPSR_DATA(IP0_11_8, MMC_D2),
617 PINMUX_IPSR_DATA(IP0_11_8, BS),
618 PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A),
619 PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A),
620 PINMUX_IPSR_DATA(IP0_11_8, PWM4_B),
621
622 PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
623 PINMUX_IPSR_DATA(IP0_14_12, MMC_D3),
624 PINMUX_IPSR_DATA(IP0_14_12, A0),
625 PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A),
626 PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
627
628 PINMUX_IPSR_DATA(IP0_15, A4),
629 PINMUX_IPSR_DATA(IP0_16, A5),
630 PINMUX_IPSR_DATA(IP0_17, A6),
631 PINMUX_IPSR_DATA(IP0_18, A7),
632 PINMUX_IPSR_DATA(IP0_19, A8),
633 PINMUX_IPSR_DATA(IP0_20, A9),
634 PINMUX_IPSR_DATA(IP0_21, A10),
635 PINMUX_IPSR_DATA(IP0_22, A11),
636 PINMUX_IPSR_DATA(IP0_23, A12),
637 PINMUX_IPSR_DATA(IP0_24, A13),
638 PINMUX_IPSR_DATA(IP0_25, A14),
639 PINMUX_IPSR_DATA(IP0_26, A15),
640 PINMUX_IPSR_DATA(IP0_27, A16),
641 PINMUX_IPSR_DATA(IP0_28, A17),
642 PINMUX_IPSR_DATA(IP0_29, A18),
643 PINMUX_IPSR_DATA(IP0_30, A19),
644
645 /* IPSR1 */
646 PINMUX_IPSR_DATA(IP1_0, A20),
647 PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
648
649 PINMUX_IPSR_DATA(IP1_1, A21),
650 PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
651
652 PINMUX_IPSR_DATA(IP1_4_2, A22),
653 PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B),
654 PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B),
655 PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A),
656
657 PINMUX_IPSR_DATA(IP1_7_5, A23),
658 PINMUX_IPSR_DATA(IP1_7_5, HTX0_B),
659 PINMUX_IPSR_DATA(IP1_7_5, TX2_B),
660 PINMUX_IPSR_DATA(IP1_7_5, DACK2_A),
661 PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A),
662
663 PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A),
664 PINMUX_IPSR_DATA(IP1_10_8, MMC_D6),
665 PINMUX_IPSR_DATA(IP1_10_8, A24),
666 PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A),
667 PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B),
668 PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A),
669
670 PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A),
671 PINMUX_IPSR_DATA(IP1_14_11, MMC_D7),
672 PINMUX_IPSR_DATA(IP1_14_11, A25),
673 PINMUX_IPSR_DATA(IP1_14_11, DACK1_A),
674 PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B),
675 PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C),
676 PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A),
677
678 PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT),
679 PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B),
680 PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B),
681
682 PINMUX_IPSR_NOGP(IP1_17, CS0),
683 PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B),
684
685 PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B),
686 PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B),
687 PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26),
688 PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A),
689 PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B),
690
691 PINMUX_IPSR_DATA(IP1_23_21, MMC_D5),
692 PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B),
693 PINMUX_IPSR_DATA(IP1_23_21, RD_WR),
694
695 PINMUX_IPSR_DATA(IP1_24, WE1),
696 PINMUX_IPSR_DATA(IP1_24, ATAWR0_B),
697
698 PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B),
699 PINMUX_IPSR_DATA(IP1_27_25, EX_CS0),
700 PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A),
701 PINMUX_IPSR_DATA(IP1_27_25, TX3_C),
702 PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A),
703
704 PINMUX_IPSR_DATA(IP1_29_28, EX_CS1),
705 PINMUX_IPSR_DATA(IP1_29_28, MMC_D4),
706
707 /* IPSR2 */
708 PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A),
709 PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK),
710 PINMUX_IPSR_DATA(IP2_2_0, ATACS00),
711 PINMUX_IPSR_DATA(IP2_2_0, EX_CS2),
712
713 PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A),
714 PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD),
715 PINMUX_IPSR_DATA(IP2_5_3, ATACS10),
716 PINMUX_IPSR_DATA(IP2_5_3, EX_CS3),
717
718 PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A),
719 PINMUX_IPSR_DATA(IP2_8_6, MMC_D0),
720 PINMUX_IPSR_DATA(IP2_8_6, ATARD0),
721 PINMUX_IPSR_DATA(IP2_8_6, EX_CS4),
722 PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A),
723
724 PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A),
725 PINMUX_IPSR_DATA(IP2_11_9, MMC_D1),
726 PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A),
727 PINMUX_IPSR_DATA(IP2_11_9, EX_CS5),
728 PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A),
729
730 PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A),
731 PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A),
732
733 PINMUX_IPSR_DATA(IP2_16_14, DACK0),
734 PINMUX_IPSR_DATA(IP2_16_14, TX3_A),
735 PINMUX_IPSR_DATA(IP2_16_14, DRACK0),
736
737 PINMUX_IPSR_DATA(IP2_17, EX_WAIT0),
738 PINMUX_IPSR_DATA(IP2_17, PWM0_C),
739
740 PINMUX_IPSR_NOGP(IP2_18, D0),
741 PINMUX_IPSR_NOGP(IP2_19, D1),
742 PINMUX_IPSR_NOGP(IP2_20, D2),
743 PINMUX_IPSR_NOGP(IP2_21, D3),
744 PINMUX_IPSR_NOGP(IP2_22, D4),
745 PINMUX_IPSR_NOGP(IP2_23, D5),
746 PINMUX_IPSR_NOGP(IP2_24, D6),
747 PINMUX_IPSR_NOGP(IP2_25, D7),
748 PINMUX_IPSR_NOGP(IP2_26, D8),
749 PINMUX_IPSR_NOGP(IP2_27, D9),
750 PINMUX_IPSR_NOGP(IP2_28, D10),
751 PINMUX_IPSR_NOGP(IP2_29, D11),
752
753 PINMUX_IPSR_DATA(IP2_30, RD_WR_B),
754 PINMUX_IPSR_DATA(IP2_30, IRQ0),
755
756 PINMUX_IPSR_DATA(IP2_31, MLB_CLK),
757 PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A),
758
759 /* IPSR3 */
760 PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG),
761 PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B),
762 PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A),
763 PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A),
764
765 PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT),
766 PINMUX_IPSR_DATA(IP3_4_2, TX5_B),
767 PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A),
768 PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A),
769 PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B),
770
771 PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B),
772 PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK),
773 PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B),
774 PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B),
775 PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B),
776
777 PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B),
778 PINMUX_IPSR_DATA(IP3_9_8, HTX0_A),
779 PINMUX_IPSR_DATA(IP3_9_8, TX0_A),
780
781 PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B),
782 PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A),
783 PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A),
784
785 PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B),
786 PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A),
787 PINMUX_IPSR_DATA(IP3_15_13, SCK0),
788 PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B),
789
790 PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B),
791 PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A),
792 PINMUX_IPSR_DATA(IP3_18_16, CTS0),
793
794 PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B),
795 PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A),
796 PINMUX_IPSR_DATA(IP3_20_19, RTS0),
797
798 PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4),
799 PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0),
800 PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0),
801 PINMUX_IPSR_DATA(IP3_23_21, AUDATA2),
802 PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2),
803 PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C),
804 PINMUX_IPSR_DATA(IP3_23_21, ADICHS1),
805 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B),
806
807 PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4),
808 PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1),
809 PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1),
810 PINMUX_IPSR_DATA(IP3_26_24, AUDATA3),
811 PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3),
812 PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C),
813 PINMUX_IPSR_DATA(IP3_26_24, ADICHS2),
814 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B),
815
816 PINMUX_IPSR_DATA(IP3_27, DU0_DR2),
817 PINMUX_IPSR_DATA(IP3_27, LCDOUT2),
818
819 PINMUX_IPSR_DATA(IP3_28, DU0_DR3),
820 PINMUX_IPSR_DATA(IP3_28, LCDOUT3),
821
822 PINMUX_IPSR_DATA(IP3_29, DU0_DR4),
823 PINMUX_IPSR_DATA(IP3_29, LCDOUT4),
824
825 PINMUX_IPSR_DATA(IP3_30, DU0_DR5),
826 PINMUX_IPSR_DATA(IP3_30, LCDOUT5),
827
828 PINMUX_IPSR_DATA(IP3_31, DU0_DR6),
829 PINMUX_IPSR_DATA(IP3_31, LCDOUT6),
830
831 /* IPSR4 */
832 PINMUX_IPSR_DATA(IP4_0, DU0_DR7),
833 PINMUX_IPSR_DATA(IP4_0, LCDOUT7),
834
835 PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0),
836 PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8),
837 PINMUX_IPSR_DATA(IP4_3_1, AUDATA4),
838 PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4),
839 PINMUX_IPSR_DATA(IP4_3_1, TX1_D),
840 PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A),
841 PINMUX_IPSR_DATA(IP4_3_1, ADICHS0),
842
843 PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1),
844 PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9),
845 PINMUX_IPSR_DATA(IP4_6_4, AUDATA5),
846 PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5),
847 PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D),
848 PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A),
849 PINMUX_IPSR_DATA(IP4_6_4, ADIDATA),
850
851 PINMUX_IPSR_DATA(IP4_7, DU0_DG2),
852 PINMUX_IPSR_DATA(IP4_7, LCDOUT10),
853
854 PINMUX_IPSR_DATA(IP4_8, DU0_DG3),
855 PINMUX_IPSR_DATA(IP4_8, LCDOUT11),
856
857 PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4),
858 PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12),
859 PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B),
860
861 PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5),
862 PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13),
863 PINMUX_IPSR_DATA(IP4_12_11, TX0_B),
864
865 PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6),
866 PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14),
867 PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A),
868
869 PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7),
870 PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15),
871 PINMUX_IPSR_DATA(IP4_16_15, TX4_A),
872
873 PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B),
874 PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */
875 PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */
876 PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0),
877 PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16),
878 PINMUX_IPSR_DATA(IP4_20_17, AUDATA6),
879 PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6),
880 PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A),
881 PINMUX_IPSR_DATA(IP4_20_17, PWM0_A),
882 PINMUX_IPSR_DATA(IP4_20_17, ADICLK),
883 PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B),
884
885 PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC),
886 PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */
887 PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */
888 PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1),
889 PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17),
890 PINMUX_IPSR_DATA(IP4_24_21, AUDATA7),
891 PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7),
892 PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A),
893 PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP),
894 PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B),
895
896 PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */
897 PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */
898 PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2),
899 PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18),
900
901 PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B),
902 PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3),
903 PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19),
904
905 PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */
906 PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */
907 PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4),
908 PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20),
909
910 /* IPSR5 */
911 PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */
912 PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */
913 PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5),
914 PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21),
915
916 PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B),
917 PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6),
918 PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22),
919
920 PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B),
921 PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7),
922 PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23),
923
924 PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN),
925 PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS),
926
927 PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0),
928 PINMUX_IPSR_DATA(IP5_7, QCLK),
929
930 PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1),
931 PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE),
932 PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A),
933 PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C),
934
935 PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B),
936 PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
937 PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS),
938
939 PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
940 PINMUX_IPSR_DATA(IP5_12, QSTB_QHE),
941
942 PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
943 PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE),
944 PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D),
945
946 PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A),
947 PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP),
948 PINMUX_IPSR_DATA(IP5_17_15, QPOLA),
949 PINMUX_IPSR_DATA(IP5_17_15, AUDCK),
950 PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK),
951 PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D),
952
953 PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A),
954 PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE),
955 PINMUX_IPSR_DATA(IP5_20_18, QPOLB),
956 PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC),
957 PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL),
958 PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D),
959
960 PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B),
961 PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78),
962 PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B),
963 PINMUX_IPSR_DATA(IP5_22_21, TX1_B),
964
965 PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B),
966 PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78),
967 PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B),
968 PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B),
969 PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D),
970
971 PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8),
972 PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A),
973 PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B),
974 PINMUX_IPSR_DATA(IP5_28_26, TX2_A),
975 PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B),
976
977 PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7),
978 PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B),
979 PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A),
980 PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B),
981
982 /* IPSR6 */
983 PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6),
984 PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A),
985 PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B),
986 PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B),
987
988 PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6),
989 PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A),
990 PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B),
991 PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B),
992
993 PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6),
994 PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A),
995 PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B),
996
997 PINMUX_IPSR_DATA(IP6_7, SSI_SCK5),
998 PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C),
999
1000 PINMUX_IPSR_DATA(IP6_8, SSI_WS5),
1001 PINMUX_IPSR_DATA(IP6_8, TX4_C),
1002
1003 PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5),
1004 PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D),
1005
1006 PINMUX_IPSR_DATA(IP6_10, SSI_WS34),
1007 PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8),
1008
1009 PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4),
1010 PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A),
1011 PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9),
1012
1013 PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3),
1014 PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10),
1015
1016 PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012),
1017 PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11),
1018 PINMUX_IPSR_DATA(IP6_15_14, TX0_D),
1019
1020 PINMUX_IPSR_DATA(IP6_16, SSI_WS012),
1021 PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12),
1022
1023 PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2),
1024 PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A),
1025 PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13),
1026 PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A),
1027
1028 PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1),
1029 PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14),
1030 PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A),
1031 PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A),
1032
1033 PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0),
1034 PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15),
1035
1036 PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK),
1037 PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO),
1038
1039 PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD),
1040 PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST),
1041
1042 PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0),
1043 PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS),
1044
1045 PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1),
1046 PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK),
1047
1048 PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2),
1049 PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI),
1050
1051 /* IPSR7 */
1052 PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3),
1053 PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B),
1054
1055 PINMUX_IPSR_DATA(IP7_3_2, SD0_CD),
1056 PINMUX_IPSR_DATA(IP7_3_2, TX5_A),
1057
1058 PINMUX_IPSR_DATA(IP7_5_4, SD0_WP),
1059 PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A),
1060
1061 PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB),
1062 PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A),
1063 PINMUX_IPSR_DATA(IP7_8_6, HTX1_A),
1064 PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C),
1065
1066 PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD),
1067 PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A),
1068 PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A),
1069 PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C),
1070
1071 PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC),
1072 PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A),
1073 PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A),
1074 PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A),
1075 PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C),
1076
1077 PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC),
1078 PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0),
1079 PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A),
1080 PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A),
1081 PINMUX_IPSR_DATA(IP7_17_15, TX1_C),
1082
1083 PINMUX_IPSR_DATA(IP7_20_18, TCLK0),
1084 PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A),
1085 PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A),
1086 PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C),
1087 PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C),
1088 PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN),
1089
1090 PINMUX_IPSR_DATA(IP7_21, VI0_CLK),
1091 PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A),
1092
1093 PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB),
1094 PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B),
1095 PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0),
1096 PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6),
1097 PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A),
1098 PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B),
1099
1100 PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD),
1101 PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B),
1102 PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */
1103 PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */
1104 PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1),
1105 PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7),
1106 PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A),
1107 PINMUX_IPSR_DATA(IP7_28_25, TX4_B),
1108
1109 PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC),
1110 PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B),
1111 PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2),
1112 PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2),
1113 PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A),
1114 PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B),
1115
1116 /* IPSR8 */
1117 PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC),
1118 PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B),
1119 PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3),
1120 PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3),
1121 PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A),
1122 PINMUX_IPSR_DATA(IP8_2_0, TX3_B),
1123
1124 PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0),
1125 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2),
1126 PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B),
1127 PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D),
1128
1129 PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1),
1130 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3),
1131 PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B),
1132 PINMUX_IPSR_DATA(IP8_8_6, TX3_D),
1133
1134 PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2),
1135 PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4),
1136 PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C),
1137
1138 PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3),
1139 PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5),
1140 PINMUX_IPSR_DATA(IP8_13_11, TX1_A),
1141 PINMUX_IPSR_DATA(IP8_13_11, TX0_C),
1142
1143 PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4),
1144 PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2),
1145 PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A),
1146
1147 PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5),
1148 PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3),
1149 PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A),
1150 PINMUX_IPSR_DATA(IP8_18_16, PWM4),
1151 PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B),
1152
1153 PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0),
1154 PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4),
1155 PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A),
1156 PINMUX_IPSR_DATA(IP8_21_19, PWM5),
1157
1158 PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1),
1159 PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5),
1160 PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A),
1161
1162 PINMUX_IPSR_DATA(IP8_26_24, VI0_G2),
1163 PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B),
1164 PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4),
1165 PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4),
1166 PINMUX_IPSR_DATA(IP8_26_24, HTX1_B),
1167
1168 PINMUX_IPSR_DATA(IP8_29_27, VI0_G3),
1169 PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B),
1170 PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5),
1171 PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5),
1172 PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B),
1173
1174 /* IPSR9 */
1175 PINMUX_IPSR_DATA(IP9_2_0, VI0_G4),
1176 PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B),
1177 PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6),
1178 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6),
1179 PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B),
1180
1181 PINMUX_IPSR_DATA(IP9_5_3, VI0_G5),
1182 PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B),
1183 PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7),
1184 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7),
1185 PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B),
1186
1187 PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */
1188 PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */
1189 PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK),
1190 PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK),
1191 PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN),
1192
1193 PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */
1194 PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */
1195 PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8),
1196 PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6),
1197 PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0),
1198 PINMUX_IPSR_DATA(IP9_11_9, PWM2),
1199 PINMUX_IPSR_DATA(IP9_11_9, TCLK1),
1200
1201 PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */
1202 PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */
1203 PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9),
1204 PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7),
1205 PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1),
1206 PINMUX_IPSR_DATA(IP9_14_12, PWM3),
1207
1208 PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A),
1209 PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV),
1210 PINMUX_IPSR_DATA(IP9_17_15, IECLK),
1211 PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C),
1212
1213 PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */
1214 PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */
1215 PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN),
1216 PINMUX_IPSR_DATA(IP9_20_18, IETX),
1217 PINMUX_IPSR_DATA(IP9_20_18, TX2_C),
1218
1219 PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */
1220 PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */
1221 PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER),
1222 PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C),
1223 PINMUX_IPSR_DATA(IP9_23_21, IERX),
1224 PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C),
1225
1226 PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A),
1227 PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT),
1228 PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0),
1229 PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C),
1230 PINMUX_IPSR_DATA(IP9_26_24, TX2_D),
1231 PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C),
1232
1233 PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A),
1234 PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
1235 PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1),
1236 PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C),
1237 PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D),
1238 PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C),
1239
1240 /* IPSR10 */
1241 PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A),
1242 PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
1243 PINMUX_IPSR_DATA(IP10_2_0, ATARD1),
1244 PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC),
1245 PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B),
1246
1247 PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A),
1248 PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1249 PINMUX_IPSR_DATA(IP10_5_3, ATAWR1),
1250 PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO),
1251 PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B),
1252
1253 PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A),
1254 PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP),
1255 PINMUX_IPSR_DATA(IP10_8_6, ATACS01),
1256 PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B),
1257 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1258 PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A),
1259
1260 PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A),
1261 PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE),
1262 PINMUX_IPSR_DATA(IP10_12_9, ATACS11),
1263 PINMUX_IPSR_DATA(IP10_12_9, DACK1_B),
1264 PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC),
1265 PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A),
1266 PINMUX_IPSR_DATA(IP10_12_9, PWM6),
1267
1268 PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A),
1269 PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12),
1270 PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B),
1271 PINMUX_IPSR_DATA(IP10_15_13, ATADIR1),
1272 PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B),
1273 PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B),
1274
1275 PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A),
1276 PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13),
1277 PINMUX_IPSR_DATA(IP10_18_16, DACK2_B),
1278 PINMUX_IPSR_DATA(IP10_18_16, ATAG1),
1279 PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B),
1280 PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B),
1281
1282 PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A),
1283 PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14),
1284 PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B),
1285 PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B),
1286 PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B),
1287 PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A),
1288
1289 PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A),
1290 PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15),
1291 PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B),
1292 PINMUX_IPSR_DATA(IP10_24_22, DACK0_B),
1293 PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B),
1294 PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
1295};
1296
1297static struct sh_pfc_pin pinmux_pins[] = {
1298 PINMUX_GPIO_GP_ALL(),
1299};
1300
1301/* Pin numbers for pins without a corresponding GPIO port number are computed
1302 * from the row and column numbers with a 1000 offset to avoid collisions with
1303 * GPIO port numbers.
1304 */
1305#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
1306
1307/* - macro */
1308#define SH_PFC_PINS(name, args...) \
1309 static const unsigned int name ##_pins[] = { args }
1310#define SH_PFC_MUX1(name, arg1) \
1311 static const unsigned int name ##_mux[] = { arg1##_MARK }
1312#define SH_PFC_MUX2(name, arg1, arg2) \
1313 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, }
1314#define SH_PFC_MUX3(name, arg1, arg2, arg3) \
1315 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
1316 arg3##_MARK }
1317#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \
1318 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
1319 arg3##_MARK, arg4##_MARK }
1320#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
1321 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
1322 arg3##_MARK, arg4##_MARK, \
1323 arg5##_MARK, arg6##_MARK, \
1324 arg7##_MARK, arg8##_MARK, }
1325
1326/* - Ether ------------------------------------------------------------------ */
1327SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1328 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
1329 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1330 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14),
1331 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17));
1332static const unsigned int ether_rmii_mux[] = {
1333 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1334 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1335 ETH_MDIO_MARK, ETH_MDC_MARK,
1336};
1337SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19));
1338SH_PFC_MUX1(ether_link, ETH_LINK);
1339SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20));
1340SH_PFC_MUX1(ether_magic, ETH_MAGIC);
1341
1342/* - SCIF macro ------------------------------------------------------------- */
1343#define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
1344#define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
1345#define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts)
1346#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck)
1347
1348/* - HSCIF0 ----------------------------------------------------------------- */
1349SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
1350SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A);
1351SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30));
1352SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B);
1353SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1354SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A);
1355SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28));
1356SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B);
1357SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19));
1358SCIF_PFC_CLK(hscif0_clk, HSCK0);
1359
1360/* - HSCIF1 ----------------------------------------------------------------- */
1361SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20));
1362SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A);
1363SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
1364SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B);
1365SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
1366SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A);
1367SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7));
1368SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B);
1369SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23));
1370SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A);
1371SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2));
1372SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B);
1373
1374/* - HSPI macro --------------------------------------------------------------*/
1375#define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
1376#define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx)
1377
1378/* - HSPI0 -------------------------------------------------------------------*/
1379HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
1380 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
1381HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A,
1382 HSPI_RX0_A, HSPI_TX0);
1383
1384HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1385 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27));
1386HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B,
1387 HSPI_RX0_B, HSPI_TX0_B);
1388
1389/* - HSPI1 -------------------------------------------------------------------*/
1390HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
1391 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28));
1392HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A,
1393 HSPI_RX1_A, HSPI_TX1_A);
1394
1395HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
1396 PIN_NUMBER(20, 1), PIN_NUMBER(25, 2));
1397HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
1398 HSPI_RX1_B, HSPI_TX1_B);
1399
1400/* - HSPI2 -------------------------------------------------------------------*/
1401HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8),
1402 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30));
1403HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A,
1404 HSPI_RX2_A, HSPI_TX2_A);
1405
1406HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
1407 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24));
1408HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B,
1409 HSPI_RX2_B, HSPI_TX2_B);
1410
1411/* - I2C macro ------------------------------------------------------------- */
1412#define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
1413#define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl)
1414
1415/* - I2C1 ------------------------------------------------------------------ */
1416I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9));
1417I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A);
1418I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
1419I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B);
1420
1421/* - I2C2 ------------------------------------------------------------------ */
1422I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
1423I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A);
1424I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
1425I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B);
1426I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
1427I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C);
1428
1429/* - I2C3 ------------------------------------------------------------------ */
1430I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15));
1431I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A);
1432I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19));
1433I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B);
1434I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
1435I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
1436
1437/* - MMC macro -------------------------------------------------------------- */
1438#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1439#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
1440#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
1441#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
1442#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
1443 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1444
1445/* - MMC -------------------------------------------------------------------- */
1446MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
1447MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
1448MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
1449MMC_PFC_DAT1(mmc_data1, MMC_D0);
1450MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8),
1451 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
1452MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
1453 MMC_D2, MMC_D3);
1454MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8),
1455 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1456 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1457 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
1458MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
1459 MMC_D2, MMC_D3,
1460 MMC_D4, MMC_D5,
1461 MMC_D6, MMC_D7);
1462
1463/* - SCIF CLOCK ------------------------------------------------------------- */
1464SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16));
1465SCIF_PFC_CLK(scif_clk, SCIF_CLK);
1466
1467/* - SCIF0 ------------------------------------------------------------------ */
1468SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
1469SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A);
1470SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2));
1471SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B);
1472SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31));
1473SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C);
1474SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1));
1475SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D);
1476SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1477SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0);
1478SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19));
1479SCIF_PFC_CLK(scif0_clk, SCK0);
1480
1481/* - SCIF1 ------------------------------------------------------------------ */
1482SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1));
1483SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A);
1484SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
1485SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B);
1486SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
1487SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C);
1488SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
1489SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D);
1490SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
1491SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A);
1492SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19));
1493SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C);
1494SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2));
1495SCIF_PFC_CLK(scif1_clk_a, SCK1_A);
1496SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20));
1497SCIF_PFC_CLK(scif1_clk_c, SCK1_C);
1498
1499/* - SCIF2 ------------------------------------------------------------------ */
1500SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
1501SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A);
1502SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28));
1503SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B);
1504SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14));
1505SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C);
1506SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
1507SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D);
1508SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
1509SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
1510SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
1511SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
1512SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20));
1513SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
1514SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
1515SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
1516
1517/* - SCIF3 ------------------------------------------------------------------ */
1518SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9));
1519SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A);
1520SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27));
1521SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B);
1522SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31));
1523SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C);
1524SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29));
1525SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D);
1526
1527/* - SCIF4 ------------------------------------------------------------------ */
1528SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4));
1529SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A);
1530SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25));
1531SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B);
1532SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31));
1533SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C);
1534
1535/* - SCIF5 ------------------------------------------------------------------ */
1536SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18));
1537SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A);
1538SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14));
1539SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
1540
1541/* - SDHI macro ------------------------------------------------------------- */
1542#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1543#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
1544#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
1545#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
1546#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
1547#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp)
1548
1549/* - SDHI0 ------------------------------------------------------------------ */
1550SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
1551SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
1552SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
1553SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
1554SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
1555SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
1556SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1557 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
1558SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
1559 SD0_DAT2, SD0_DAT3);
1560SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
1561SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
1562
1563/* - SDHI1 ------------------------------------------------------------------ */
1564SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30));
1565SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A);
1566SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24));
1567SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B);
1568SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
1569SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
1570SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
1571SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
1572SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
1573SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
1574SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
1575SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
1576SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
1577 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
1578SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
1579 SD1_DAT2_A, SD1_DAT3_A);
1580SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1581 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1582SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
1583 SD1_DAT2_B, SD1_DAT3_B);
1584SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
1585SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
1586SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25));
1587SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B);
1588
1589/* - SDH2 ------------------------------------------------------------------- */
1590SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23));
1591SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A);
1592SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27));
1593SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B);
1594SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
1595SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
1596SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
1597SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
1598SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
1599SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
1600SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
1601SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
1602SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
1603 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
1604SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
1605 SD2_DAT2_A, SD2_DAT3_A);
1606SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
1607 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
1608SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
1609 SD2_DAT2_B, SD2_DAT3_B);
1610SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
1611SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
1612SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
1613SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
1614
1615/* - USB0 ------------------------------------------------------------------- */
1616SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
1617SH_PFC_MUX1(usb0, PENC0);
1618SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3));
1619SH_PFC_MUX1(usb0_ovc, USB_OVC0);
1620
1621/* - USB1 ------------------------------------------------------------------- */
1622SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2));
1623SH_PFC_MUX1(usb1, PENC1);
1624SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4));
1625SH_PFC_MUX1(usb1_ovc, USB_OVC1);
1626
1627/* - VIN macros ------------------------------------------------------------- */
1628#define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1629#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
1630 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1631#define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
1632#define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync)
1633
1634/* - VIN0 ------------------------------------------------------------------- */
1635VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30),
1636 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0),
1637 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
1638 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
1639VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1,
1640 VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3,
1641 VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5,
1642 VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1);
1643VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24));
1644VIN_PFC_CLK(vin0_clk, VI0_CLK);
1645VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28));
1646VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC);
1647/* - VIN1 ------------------------------------------------------------------- */
1648VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1649 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1650 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
1651 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8));
1652VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1,
1653 VI1_DATA2, VI1_DATA3,
1654 VI1_DATA4, VI1_DATA5,
1655 VI1_DATA6, VI1_DATA7);
1656VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9));
1657VIN_PFC_CLK(vin1_clk, VI1_CLK);
1658VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
1659VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
1660
1661static const struct sh_pfc_pin_group pinmux_groups[] = {
1662 SH_PFC_PIN_GROUP(ether_rmii),
1663 SH_PFC_PIN_GROUP(ether_link),
1664 SH_PFC_PIN_GROUP(ether_magic),
1665 SH_PFC_PIN_GROUP(hscif0_data_a),
1666 SH_PFC_PIN_GROUP(hscif0_data_b),
1667 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
1668 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
1669 SH_PFC_PIN_GROUP(hscif0_clk),
1670 SH_PFC_PIN_GROUP(hscif1_data_a),
1671 SH_PFC_PIN_GROUP(hscif1_data_b),
1672 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
1673 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
1674 SH_PFC_PIN_GROUP(hscif1_clk_a),
1675 SH_PFC_PIN_GROUP(hscif1_clk_b),
1676 SH_PFC_PIN_GROUP(hspi0_a),
1677 SH_PFC_PIN_GROUP(hspi0_b),
1678 SH_PFC_PIN_GROUP(hspi1_a),
1679 SH_PFC_PIN_GROUP(hspi1_b),
1680 SH_PFC_PIN_GROUP(hspi2_a),
1681 SH_PFC_PIN_GROUP(hspi2_b),
1682 SH_PFC_PIN_GROUP(i2c1_a),
1683 SH_PFC_PIN_GROUP(i2c1_b),
1684 SH_PFC_PIN_GROUP(i2c2_a),
1685 SH_PFC_PIN_GROUP(i2c2_b),
1686 SH_PFC_PIN_GROUP(i2c2_c),
1687 SH_PFC_PIN_GROUP(i2c3_a),
1688 SH_PFC_PIN_GROUP(i2c3_b),
1689 SH_PFC_PIN_GROUP(i2c3_c),
1690 SH_PFC_PIN_GROUP(mmc_ctrl),
1691 SH_PFC_PIN_GROUP(mmc_data1),
1692 SH_PFC_PIN_GROUP(mmc_data4),
1693 SH_PFC_PIN_GROUP(mmc_data8),
1694 SH_PFC_PIN_GROUP(scif_clk),
1695 SH_PFC_PIN_GROUP(scif0_data_a),
1696 SH_PFC_PIN_GROUP(scif0_data_b),
1697 SH_PFC_PIN_GROUP(scif0_data_c),
1698 SH_PFC_PIN_GROUP(scif0_data_d),
1699 SH_PFC_PIN_GROUP(scif0_ctrl),
1700 SH_PFC_PIN_GROUP(scif0_clk),
1701 SH_PFC_PIN_GROUP(scif1_data_a),
1702 SH_PFC_PIN_GROUP(scif1_data_b),
1703 SH_PFC_PIN_GROUP(scif1_data_c),
1704 SH_PFC_PIN_GROUP(scif1_data_d),
1705 SH_PFC_PIN_GROUP(scif1_ctrl_a),
1706 SH_PFC_PIN_GROUP(scif1_ctrl_c),
1707 SH_PFC_PIN_GROUP(scif1_clk_a),
1708 SH_PFC_PIN_GROUP(scif1_clk_c),
1709 SH_PFC_PIN_GROUP(scif2_data_a),
1710 SH_PFC_PIN_GROUP(scif2_data_b),
1711 SH_PFC_PIN_GROUP(scif2_data_c),
1712 SH_PFC_PIN_GROUP(scif2_data_d),
1713 SH_PFC_PIN_GROUP(scif2_data_e),
1714 SH_PFC_PIN_GROUP(scif2_clk_a),
1715 SH_PFC_PIN_GROUP(scif2_clk_b),
1716 SH_PFC_PIN_GROUP(scif2_clk_c),
1717 SH_PFC_PIN_GROUP(scif3_data_a),
1718 SH_PFC_PIN_GROUP(scif3_data_b),
1719 SH_PFC_PIN_GROUP(scif3_data_c),
1720 SH_PFC_PIN_GROUP(scif3_data_d),
1721 SH_PFC_PIN_GROUP(scif4_data_a),
1722 SH_PFC_PIN_GROUP(scif4_data_b),
1723 SH_PFC_PIN_GROUP(scif4_data_c),
1724 SH_PFC_PIN_GROUP(scif5_data_a),
1725 SH_PFC_PIN_GROUP(scif5_data_b),
1726 SH_PFC_PIN_GROUP(sdhi0_cd),
1727 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1728 SH_PFC_PIN_GROUP(sdhi0_data1),
1729 SH_PFC_PIN_GROUP(sdhi0_data4),
1730 SH_PFC_PIN_GROUP(sdhi0_wp),
1731 SH_PFC_PIN_GROUP(sdhi1_cd_a),
1732 SH_PFC_PIN_GROUP(sdhi1_cd_b),
1733 SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
1734 SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
1735 SH_PFC_PIN_GROUP(sdhi1_data1_a),
1736 SH_PFC_PIN_GROUP(sdhi1_data1_b),
1737 SH_PFC_PIN_GROUP(sdhi1_data4_a),
1738 SH_PFC_PIN_GROUP(sdhi1_data4_b),
1739 SH_PFC_PIN_GROUP(sdhi1_wp_a),
1740 SH_PFC_PIN_GROUP(sdhi1_wp_b),
1741 SH_PFC_PIN_GROUP(sdhi2_cd_a),
1742 SH_PFC_PIN_GROUP(sdhi2_cd_b),
1743 SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
1744 SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
1745 SH_PFC_PIN_GROUP(sdhi2_data1_a),
1746 SH_PFC_PIN_GROUP(sdhi2_data1_b),
1747 SH_PFC_PIN_GROUP(sdhi2_data4_a),
1748 SH_PFC_PIN_GROUP(sdhi2_data4_b),
1749 SH_PFC_PIN_GROUP(sdhi2_wp_a),
1750 SH_PFC_PIN_GROUP(sdhi2_wp_b),
1751 SH_PFC_PIN_GROUP(usb0),
1752 SH_PFC_PIN_GROUP(usb0_ovc),
1753 SH_PFC_PIN_GROUP(usb1),
1754 SH_PFC_PIN_GROUP(usb1_ovc),
1755 SH_PFC_PIN_GROUP(vin0_data8),
1756 SH_PFC_PIN_GROUP(vin0_clk),
1757 SH_PFC_PIN_GROUP(vin0_sync),
1758 SH_PFC_PIN_GROUP(vin1_data8),
1759 SH_PFC_PIN_GROUP(vin1_clk),
1760 SH_PFC_PIN_GROUP(vin1_sync),
1761};
1762
1763static const char * const ether_groups[] = {
1764 "ether_rmii",
1765 "ether_link",
1766 "ether_magic",
1767};
1768
1769static const char * const hscif0_groups[] = {
1770 "hscif0_data_a",
1771 "hscif0_data_b",
1772 "hscif0_ctrl_a",
1773 "hscif0_ctrl_b",
1774 "hscif0_clk",
1775};
1776
1777static const char * const hscif1_groups[] = {
1778 "hscif1_data_a",
1779 "hscif1_data_b",
1780 "hscif1_ctrl_a",
1781 "hscif1_ctrl_b",
1782 "hscif1_clk_a",
1783 "hscif1_clk_b",
1784};
1785
1786static const char * const hspi0_groups[] = {
1787 "hspi0_a",
1788 "hspi0_b",
1789};
1790
1791static const char * const hspi1_groups[] = {
1792 "hspi1_a",
1793 "hspi1_b",
1794};
1795
1796static const char * const hspi2_groups[] = {
1797 "hspi2_a",
1798 "hspi2_b",
1799};
1800
1801static const char * const i2c1_groups[] = {
1802 "i2c1_a",
1803 "i2c1_b",
1804};
1805
1806static const char * const i2c2_groups[] = {
1807 "i2c2_a",
1808 "i2c2_b",
1809 "i2c2_c",
1810};
1811
1812static const char * const i2c3_groups[] = {
1813 "i2c3_a",
1814 "i2c3_b",
1815 "i2c3_c",
1816};
1817
1818static const char * const mmc_groups[] = {
1819 "mmc_ctrl",
1820 "mmc_data1",
1821 "mmc_data4",
1822 "mmc_data8",
1823};
1824
1825static const char * const scif_clk_groups[] = {
1826 "scif_clk",
1827};
1828
1829static const char * const scif0_groups[] = {
1830 "scif0_data_a",
1831 "scif0_data_b",
1832 "scif0_data_c",
1833 "scif0_data_d",
1834 "scif0_ctrl",
1835 "scif0_clk",
1836};
1837
1838static const char * const scif1_groups[] = {
1839 "scif1_data_a",
1840 "scif1_data_b",
1841 "scif1_data_c",
1842 "scif1_data_d",
1843 "scif1_ctrl_a",
1844 "scif1_ctrl_c",
1845 "scif1_clk_a",
1846 "scif1_clk_c",
1847};
1848
1849static const char * const scif2_groups[] = {
1850 "scif2_data_a",
1851 "scif2_data_b",
1852 "scif2_data_c",
1853 "scif2_data_d",
1854 "scif2_data_e",
1855 "scif2_clk_a",
1856 "scif2_clk_b",
1857 "scif2_clk_c",
1858};
1859
1860static const char * const scif3_groups[] = {
1861 "scif3_data_a",
1862 "scif3_data_b",
1863 "scif3_data_c",
1864 "scif3_data_d",
1865};
1866
1867static const char * const scif4_groups[] = {
1868 "scif4_data_a",
1869 "scif4_data_b",
1870 "scif4_data_c",
1871};
1872
1873static const char * const scif5_groups[] = {
1874 "scif5_data_a",
1875 "scif5_data_b",
1876};
1877
1878
1879static const char * const sdhi0_groups[] = {
1880 "sdhi0_cd",
1881 "sdhi0_ctrl",
1882 "sdhi0_data1",
1883 "sdhi0_data4",
1884 "sdhi0_wp",
1885};
1886
1887static const char * const sdhi1_groups[] = {
1888 "sdhi1_cd_a",
1889 "sdhi1_cd_b",
1890 "sdhi1_ctrl_a",
1891 "sdhi1_ctrl_b",
1892 "sdhi1_data1_a",
1893 "sdhi1_data1_b",
1894 "sdhi1_data4_a",
1895 "sdhi1_data4_b",
1896 "sdhi1_wp_a",
1897 "sdhi1_wp_b",
1898};
1899
1900static const char * const sdhi2_groups[] = {
1901 "sdhi2_cd_a",
1902 "sdhi2_cd_b",
1903 "sdhi2_ctrl_a",
1904 "sdhi2_ctrl_b",
1905 "sdhi2_data1_a",
1906 "sdhi2_data1_b",
1907 "sdhi2_data4_a",
1908 "sdhi2_data4_b",
1909 "sdhi2_wp_a",
1910 "sdhi2_wp_b",
1911};
1912
1913static const char * const usb0_groups[] = {
1914 "usb0",
1915 "usb0_ovc",
1916};
1917
1918static const char * const usb1_groups[] = {
1919 "usb1",
1920 "usb1_ovc",
1921};
1922
1923static const char * const vin0_groups[] = {
1924 "vin0_data8",
1925 "vin0_clk",
1926 "vin0_sync",
1927};
1928
1929static const char * const vin1_groups[] = {
1930 "vin1_data8",
1931 "vin1_clk",
1932 "vin1_sync",
1933};
1934
1935static const struct sh_pfc_function pinmux_functions[] = {
1936 SH_PFC_FUNCTION(ether),
1937 SH_PFC_FUNCTION(hscif0),
1938 SH_PFC_FUNCTION(hscif1),
1939 SH_PFC_FUNCTION(hspi0),
1940 SH_PFC_FUNCTION(hspi1),
1941 SH_PFC_FUNCTION(hspi2),
1942 SH_PFC_FUNCTION(i2c1),
1943 SH_PFC_FUNCTION(i2c2),
1944 SH_PFC_FUNCTION(i2c3),
1945 SH_PFC_FUNCTION(mmc),
1946 SH_PFC_FUNCTION(scif_clk),
1947 SH_PFC_FUNCTION(scif0),
1948 SH_PFC_FUNCTION(scif1),
1949 SH_PFC_FUNCTION(scif2),
1950 SH_PFC_FUNCTION(scif3),
1951 SH_PFC_FUNCTION(scif4),
1952 SH_PFC_FUNCTION(scif5),
1953 SH_PFC_FUNCTION(sdhi0),
1954 SH_PFC_FUNCTION(sdhi1),
1955 SH_PFC_FUNCTION(sdhi2),
1956 SH_PFC_FUNCTION(usb0),
1957 SH_PFC_FUNCTION(usb1),
1958 SH_PFC_FUNCTION(vin0),
1959 SH_PFC_FUNCTION(vin1),
1960};
1961
1962static struct pinmux_cfg_reg pinmux_config_regs[] = {
1963 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1964 GP_0_31_FN, FN_IP1_14_11,
1965 GP_0_30_FN, FN_IP1_10_8,
1966 GP_0_29_FN, FN_IP1_7_5,
1967 GP_0_28_FN, FN_IP1_4_2,
1968 GP_0_27_FN, FN_IP1_1,
1969 GP_0_26_FN, FN_IP1_0,
1970 GP_0_25_FN, FN_IP0_30,
1971 GP_0_24_FN, FN_IP0_29,
1972 GP_0_23_FN, FN_IP0_28,
1973 GP_0_22_FN, FN_IP0_27,
1974 GP_0_21_FN, FN_IP0_26,
1975 GP_0_20_FN, FN_IP0_25,
1976 GP_0_19_FN, FN_IP0_24,
1977 GP_0_18_FN, FN_IP0_23,
1978 GP_0_17_FN, FN_IP0_22,
1979 GP_0_16_FN, FN_IP0_21,
1980 GP_0_15_FN, FN_IP0_20,
1981 GP_0_14_FN, FN_IP0_19,
1982 GP_0_13_FN, FN_IP0_18,
1983 GP_0_12_FN, FN_IP0_17,
1984 GP_0_11_FN, FN_IP0_16,
1985 GP_0_10_FN, FN_IP0_15,
1986 GP_0_9_FN, FN_A3,
1987 GP_0_8_FN, FN_A2,
1988 GP_0_7_FN, FN_A1,
1989 GP_0_6_FN, FN_IP0_14_12,
1990 GP_0_5_FN, FN_IP0_11_8,
1991 GP_0_4_FN, FN_IP0_7_5,
1992 GP_0_3_FN, FN_IP0_4_2,
1993 GP_0_2_FN, FN_PENC1,
1994 GP_0_1_FN, FN_PENC0,
1995 GP_0_0_FN, FN_IP0_1_0 }
1996 },
1997 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
1998 GP_1_31_FN, FN_IP4_6_4,
1999 GP_1_30_FN, FN_IP4_3_1,
2000 GP_1_29_FN, FN_IP4_0,
2001 GP_1_28_FN, FN_IP3_31,
2002 GP_1_27_FN, FN_IP3_30,
2003 GP_1_26_FN, FN_IP3_29,
2004 GP_1_25_FN, FN_IP3_28,
2005 GP_1_24_FN, FN_IP3_27,
2006 GP_1_23_FN, FN_IP3_26_24,
2007 GP_1_22_FN, FN_IP3_23_21,
2008 GP_1_21_FN, FN_IP3_20_19,
2009 GP_1_20_FN, FN_IP3_18_16,
2010 GP_1_19_FN, FN_IP3_15_13,
2011 GP_1_18_FN, FN_IP3_12_10,
2012 GP_1_17_FN, FN_IP3_9_8,
2013 GP_1_16_FN, FN_IP3_7_5,
2014 GP_1_15_FN, FN_IP3_4_2,
2015 GP_1_14_FN, FN_IP3_1_0,
2016 GP_1_13_FN, FN_IP2_31,
2017 GP_1_12_FN, FN_IP2_30,
2018 GP_1_11_FN, FN_IP2_17,
2019 GP_1_10_FN, FN_IP2_16_14,
2020 GP_1_9_FN, FN_IP2_13_12,
2021 GP_1_8_FN, FN_IP2_11_9,
2022 GP_1_7_FN, FN_IP2_8_6,
2023 GP_1_6_FN, FN_IP2_5_3,
2024 GP_1_5_FN, FN_IP2_2_0,
2025 GP_1_4_FN, FN_IP1_29_28,
2026 GP_1_3_FN, FN_IP1_27_25,
2027 GP_1_2_FN, FN_IP1_24,
2028 GP_1_1_FN, FN_WE0,
2029 GP_1_0_FN, FN_IP1_23_21 }
2030 },
2031 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
2032 GP_2_31_FN, FN_IP6_7,
2033 GP_2_30_FN, FN_IP6_6_5,
2034 GP_2_29_FN, FN_IP6_4_2,
2035 GP_2_28_FN, FN_IP6_1_0,
2036 GP_2_27_FN, FN_IP5_30_29,
2037 GP_2_26_FN, FN_IP5_28_26,
2038 GP_2_25_FN, FN_IP5_25_23,
2039 GP_2_24_FN, FN_IP5_22_21,
2040 GP_2_23_FN, FN_AUDIO_CLKB,
2041 GP_2_22_FN, FN_AUDIO_CLKA,
2042 GP_2_21_FN, FN_IP5_20_18,
2043 GP_2_20_FN, FN_IP5_17_15,
2044 GP_2_19_FN, FN_IP5_14_13,
2045 GP_2_18_FN, FN_IP5_12,
2046 GP_2_17_FN, FN_IP5_11_10,
2047 GP_2_16_FN, FN_IP5_9_8,
2048 GP_2_15_FN, FN_IP5_7,
2049 GP_2_14_FN, FN_IP5_6,
2050 GP_2_13_FN, FN_IP5_5_4,
2051 GP_2_12_FN, FN_IP5_3_2,
2052 GP_2_11_FN, FN_IP5_1_0,
2053 GP_2_10_FN, FN_IP4_30_29,
2054 GP_2_9_FN, FN_IP4_28_27,
2055 GP_2_8_FN, FN_IP4_26_25,
2056 GP_2_7_FN, FN_IP4_24_21,
2057 GP_2_6_FN, FN_IP4_20_17,
2058 GP_2_5_FN, FN_IP4_16_15,
2059 GP_2_4_FN, FN_IP4_14_13,
2060 GP_2_3_FN, FN_IP4_12_11,
2061 GP_2_2_FN, FN_IP4_10_9,
2062 GP_2_1_FN, FN_IP4_8,
2063 GP_2_0_FN, FN_IP4_7 }
2064 },
2065 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
2066 GP_3_31_FN, FN_IP8_10_9,
2067 GP_3_30_FN, FN_IP8_8_6,
2068 GP_3_29_FN, FN_IP8_5_3,
2069 GP_3_28_FN, FN_IP8_2_0,
2070 GP_3_27_FN, FN_IP7_31_29,
2071 GP_3_26_FN, FN_IP7_28_25,
2072 GP_3_25_FN, FN_IP7_24_22,
2073 GP_3_24_FN, FN_IP7_21,
2074 GP_3_23_FN, FN_IP7_20_18,
2075 GP_3_22_FN, FN_IP7_17_15,
2076 GP_3_21_FN, FN_IP7_14_12,
2077 GP_3_20_FN, FN_IP7_11_9,
2078 GP_3_19_FN, FN_IP7_8_6,
2079 GP_3_18_FN, FN_IP7_5_4,
2080 GP_3_17_FN, FN_IP7_3_2,
2081 GP_3_16_FN, FN_IP7_1_0,
2082 GP_3_15_FN, FN_IP6_31_30,
2083 GP_3_14_FN, FN_IP6_29_28,
2084 GP_3_13_FN, FN_IP6_27_26,
2085 GP_3_12_FN, FN_IP6_25_24,
2086 GP_3_11_FN, FN_IP6_23_22,
2087 GP_3_10_FN, FN_IP6_21,
2088 GP_3_9_FN, FN_IP6_20_19,
2089 GP_3_8_FN, FN_IP6_18_17,
2090 GP_3_7_FN, FN_IP6_16,
2091 GP_3_6_FN, FN_IP6_15_14,
2092 GP_3_5_FN, FN_IP6_13,
2093 GP_3_4_FN, FN_IP6_12_11,
2094 GP_3_3_FN, FN_IP6_10,
2095 GP_3_2_FN, FN_SSI_SCK34,
2096 GP_3_1_FN, FN_IP6_9,
2097 GP_3_0_FN, FN_IP6_8 }
2098 },
2099 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
2100 0, 0,
2101 0, 0,
2102 0, 0,
2103 0, 0,
2104 0, 0,
2105 GP_4_26_FN, FN_AVS2,
2106 GP_4_25_FN, FN_AVS1,
2107 GP_4_24_FN, FN_IP10_24_22,
2108 GP_4_23_FN, FN_IP10_21_19,
2109 GP_4_22_FN, FN_IP10_18_16,
2110 GP_4_21_FN, FN_IP10_15_13,
2111 GP_4_20_FN, FN_IP10_12_9,
2112 GP_4_19_FN, FN_IP10_8_6,
2113 GP_4_18_FN, FN_IP10_5_3,
2114 GP_4_17_FN, FN_IP10_2_0,
2115 GP_4_16_FN, FN_IP9_29_27,
2116 GP_4_15_FN, FN_IP9_26_24,
2117 GP_4_14_FN, FN_IP9_23_21,
2118 GP_4_13_FN, FN_IP9_20_18,
2119 GP_4_12_FN, FN_IP9_17_15,
2120 GP_4_11_FN, FN_IP9_14_12,
2121 GP_4_10_FN, FN_IP9_11_9,
2122 GP_4_9_FN, FN_IP9_8_6,
2123 GP_4_8_FN, FN_IP9_5_3,
2124 GP_4_7_FN, FN_IP9_2_0,
2125 GP_4_6_FN, FN_IP8_29_27,
2126 GP_4_5_FN, FN_IP8_26_24,
2127 GP_4_4_FN, FN_IP8_23_22,
2128 GP_4_3_FN, FN_IP8_21_19,
2129 GP_4_2_FN, FN_IP8_18_16,
2130 GP_4_1_FN, FN_IP8_15_14,
2131 GP_4_0_FN, FN_IP8_13_11 }
2132 },
2133
2134 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2135 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2136 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
2137 /* IP0_31 [1] */
2138 0, 0,
2139 /* IP0_30 [1] */
2140 FN_A19, 0,
2141 /* IP0_29 [1] */
2142 FN_A18, 0,
2143 /* IP0_28 [1] */
2144 FN_A17, 0,
2145 /* IP0_27 [1] */
2146 FN_A16, 0,
2147 /* IP0_26 [1] */
2148 FN_A15, 0,
2149 /* IP0_25 [1] */
2150 FN_A14, 0,
2151 /* IP0_24 [1] */
2152 FN_A13, 0,
2153 /* IP0_23 [1] */
2154 FN_A12, 0,
2155 /* IP0_22 [1] */
2156 FN_A11, 0,
2157 /* IP0_21 [1] */
2158 FN_A10, 0,
2159 /* IP0_20 [1] */
2160 FN_A9, 0,
2161 /* IP0_19 [1] */
2162 FN_A8, 0,
2163 /* IP0_18 [1] */
2164 FN_A7, 0,
2165 /* IP0_17 [1] */
2166 FN_A6, 0,
2167 /* IP0_16 [1] */
2168 FN_A5, 0,
2169 /* IP0_15 [1] */
2170 FN_A4, 0,
2171 /* IP0_14_12 [3] */
2172 FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0,
2173 FN_ATAG0_A, 0, FN_REMOCON_B, 0,
2174 /* IP0_11_8 [4] */
2175 FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
2176 FN_ATADIR0_A, 0, FN_SDSELF_B, 0,
2177 FN_PWM4_B, 0, 0, 0,
2178 0, 0, 0, 0,
2179 /* IP0_7_5 [3] */
2180 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1,
2181 FN_RX2_E, FN_SCL2_B, 0, 0,
2182 /* IP0_4_2 [3] */
2183 FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0,
2184 FN_TX2_E, FN_SDA2_B, 0, 0,
2185 /* IP0_1_0 [2] */
2186 FN_PRESETOUT, 0, FN_PWM1, 0,
2187 }
2188 },
2189 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2190 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
2191 /* IP1_31 [1] */
2192 0, 0,
2193 /* IP1_30 [1] */
2194 0, 0,
2195 /* IP1_29_28 [2] */
2196 FN_EX_CS1, FN_MMC_D4, 0, 0,
2197 /* IP1_27_25 [3] */
2198 FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C,
2199 FN_TS_SCK0_A, 0, 0, 0,
2200 /* IP1_24 [1] */
2201 FN_WE1, FN_ATAWR0_B,
2202 /* IP1_23_21 [3] */
2203 FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR,
2204 0, 0, 0, 0,
2205 /* IP1_20_18 [3] */
2206 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
2207 FN_SCK2_B, 0, 0, 0,
2208 /* IP1_17 [1] */
2209 FN_CS0, FN_HSPI_RX1_B,
2210 /* IP1_16_15 [2] */
2211 FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0,
2212 /* IP1_14_11 [4] */
2213 FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25,
2214 FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C,
2215 FN_TS_SDAT0_A, 0, 0, 0,
2216 0, 0, 0, 0,
2217 /* IP1_10_8 [3] */
2218 FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24,
2219 FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
2220 /* IP1_7_5 [3] */
2221 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
2222 FN_TS_SDEN0_A, 0, 0, 0,
2223 /* IP1_4_2 [3] */
2224 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
2225 0, 0, 0, 0,
2226 /* IP1_1 [1] */
2227 FN_A21, FN_HSPI_CLK1_B,
2228 /* IP1_0 [1] */
2229 FN_A20, FN_HSPI_CS1_B,
2230 }
2231 },
2232 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2234 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
2235 /* IP2_31 [1] */
2236 FN_MLB_CLK, FN_IRQ1_A,
2237 /* IP2_30 [1] */
2238 FN_RD_WR_B, FN_IRQ0,
2239 /* IP2_29 [1] */
2240 FN_D11, 0,
2241 /* IP2_28 [1] */
2242 FN_D10, 0,
2243 /* IP2_27 [1] */
2244 FN_D9, 0,
2245 /* IP2_26 [1] */
2246 FN_D8, 0,
2247 /* IP2_25 [1] */
2248 FN_D7, 0,
2249 /* IP2_24 [1] */
2250 FN_D6, 0,
2251 /* IP2_23 [1] */
2252 FN_D5, 0,
2253 /* IP2_22 [1] */
2254 FN_D4, 0,
2255 /* IP2_21 [1] */
2256 FN_D3, 0,
2257 /* IP2_20 [1] */
2258 FN_D2, 0,
2259 /* IP2_19 [1] */
2260 FN_D1, 0,
2261 /* IP2_18 [1] */
2262 FN_D0, 0,
2263 /* IP2_17 [1] */
2264 FN_EX_WAIT0, FN_PWM0_C,
2265 /* IP2_16_14 [3] */
2266 FN_DACK0, 0, 0, FN_TX3_A,
2267 FN_DRACK0, 0, 0, 0,
2268 /* IP2_13_12 [2] */
2269 FN_DREQ0_A, 0, 0, FN_RX3_A,
2270 /* IP2_11_9 [3] */
2271 FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A,
2272 FN_EX_CS5, FN_EX_WAIT2_A, 0, 0,
2273 /* IP2_8_6 [3] */
2274 FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0,
2275 FN_EX_CS4, FN_EX_WAIT1_A, 0, 0,
2276 /* IP2_5_3 [3] */
2277 FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10,
2278 FN_EX_CS3, 0, 0, 0,
2279 /* IP2_2_0 [3] */
2280 FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
2281 FN_EX_CS2, 0, 0, 0,
2282 }
2283 },
2284 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2285 1, 1, 1, 1, 1, 3, 3, 2,
2286 3, 3, 3, 2, 3, 3, 2) {
2287 /* IP3_31 [1] */
2288 FN_DU0_DR6, FN_LCDOUT6,
2289 /* IP3_30 [1] */
2290 FN_DU0_DR5, FN_LCDOUT5,
2291 /* IP3_29 [1] */
2292 FN_DU0_DR4, FN_LCDOUT4,
2293 /* IP3_28 [1] */
2294 FN_DU0_DR3, FN_LCDOUT3,
2295 /* IP3_27 [1] */
2296 FN_DU0_DR2, FN_LCDOUT2,
2297 /* IP3_26_24 [3] */
2298 FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3,
2299 FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
2300 /* IP3_23_21 [3] */
2301 FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2,
2302 FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B,
2303 /* IP3_20_19 [2] */
2304 FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0,
2305 /* IP3_18_16 [3] */
2306 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0,
2307 0, 0, 0, 0,
2308 /* IP3_15_13 [3] */
2309 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
2310 0, 0, 0, 0,
2311 /* IP3_12_10 [3] */
2312 FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0,
2313 0, 0, 0, 0,
2314 /* IP3_9_8 [2] */
2315 FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0,
2316 /* IP3_7_5 [3] */
2317 FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B,
2318 FN_SDA3_B, 0, 0, 0,
2319 /* IP3_4_2 [3] */
2320 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
2321 FN_SDSELF_B, 0, 0, 0,
2322 /* IP3_1_0 [2] */
2323 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
2324 }
2325 },
2326 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2327 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
2328 /* IP4_31 [1] */
2329 0, 0,
2330 /* IP4_30_29 [2] */
2331 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
2332 /* IP4_28_27 [2] */
2333 FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0,
2334 /* IP4_26_25 [2] */
2335 FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0,
2336 /* IP4_24_21 [4] */
2337 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
2338 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0,
2339 FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0,
2340 0, 0, 0, 0,
2341 /* IP4_20_17 [4] */
2342 FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16,
2343 FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A,
2344 FN_ADICLK, FN_TS_SDAT0_B, 0, 0,
2345 0, 0, 0, 0,
2346 /* IP4_16_15 [2] */
2347 FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0,
2348 /* IP4_14_13 [2] */
2349 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0,
2350 /* IP4_12_11 [2] */
2351 FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0,
2352 /* IP4_10_9 [2] */
2353 FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0,
2354 /* IP4_8 [1] */
2355 FN_DU0_DG3, FN_LCDOUT11,
2356 /* IP4_7 [1] */
2357 FN_DU0_DG2, FN_LCDOUT10,
2358 /* IP4_6_4 [3] */
2359 FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5,
2360 FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0,
2361 /* IP4_3_1 [3] */
2362 FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4,
2363 FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
2364 /* IP4_0 [1] */
2365 FN_DU0_DR7, FN_LCDOUT7,
2366 }
2367 },
2368 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2369 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
2370
2371 /* IP5_31 [1] */
2372 0, 0,
2373 /* IP5_30_29 [2] */
2374 FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
2375 /* IP5_28_26 [3] */
2376 FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A,
2377 FN_CAN0_TX_B, 0, 0, 0,
2378 /* IP5_25_23 [3] */
2379 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
2380 FN_CAN_CLK_D, 0, 0, 0,
2381 /* IP5_22_21 [2] */
2382 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
2383 /* IP5_20_18 [3] */
2384 FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC,
2385 FN_ARM_TRACECTL, FN_FMIN_D, 0, 0,
2386 /* IP5_17_15 [3] */
2387 FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK,
2388 FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0,
2389 /* IP5_14_13 [2] */
2390 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
2391 FN_FMCLK_D, 0,
2392 /* IP5_12 [1] */
2393 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
2394 /* IP5_11_10 [2] */
2395 FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
2396 FN_QSTH_QHS, 0,
2397 /* IP5_9_8 [2] */
2398 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE,
2399 FN_AUDIO_CLKOUT_A, FN_REMOCON_C,
2400 /* IP5_7 [1] */
2401 FN_DU0_DOTCLKO_UT0, FN_QCLK,
2402 /* IP5_6 [1] */
2403 FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
2404 /* IP5_5_4 [2] */
2405 FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0,
2406 /* IP5_3_2 [2] */
2407 FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
2408 /* IP5_1_0 [2] */
2409 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
2410 }
2411 },
2412 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2413 2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
2414 1, 2, 1, 1, 1, 1, 2, 3, 2) {
2415 /* IP6_31_30 [2] */
2416 FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
2417 /* IP6_29_28 [2] */
2418 FN_SD0_DAT1, 0, FN_SUB_TCK, 0,
2419 /* IP6_27_26 [2] */
2420 FN_SD0_DAT0, 0, FN_SUB_TMS, 0,
2421 /* IP6_25_24 [2] */
2422 FN_SD0_CMD, 0, FN_SUB_TRST, 0,
2423 /* IP6_23_22 [2] */
2424 FN_SD0_CLK, 0, FN_SUB_TDO, 0,
2425 /* IP6_21 [1] */
2426 FN_SSI_SDATA0, FN_ARM_TRACEDATA_15,
2427 /* IP6_20_19 [2] */
2428 FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
2429 FN_SCL1_A, FN_SCK2_A,
2430 /* IP6_18_17 [2] */
2431 FN_SSI_SDATA2, FN_HSPI_CS2_A,
2432 FN_ARM_TRACEDATA_13, FN_SDA1_A,
2433 /* IP6_16 [1] */
2434 FN_SSI_WS012, FN_ARM_TRACEDATA_12,
2435 /* IP6_15_14 [2] */
2436 FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
2437 FN_TX0_D, 0,
2438 /* IP6_13 [1] */
2439 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
2440 /* IP6_12_11 [2] */
2441 FN_SSI_SDATA4, FN_SSI_WS2_A,
2442 FN_ARM_TRACEDATA_9, 0,
2443 /* IP6_10 [1] */
2444 FN_SSI_WS34, FN_ARM_TRACEDATA_8,
2445 /* IP6_9 [1] */
2446 FN_SSI_SDATA5, FN_RX0_D,
2447 /* IP6_8 [1] */
2448 FN_SSI_WS5, FN_TX4_C,
2449 /* IP6_7 [1] */
2450 FN_SSI_SCK5, FN_RX4_C,
2451 /* IP6_6_5 [2] */
2452 FN_SSI_SDATA6, FN_HSPI_TX2_A,
2453 FN_FMIN_B, 0,
2454 /* IP6_4_2 [3] */
2455 FN_SSI_WS6, FN_HSPI_CLK2_A,
2456 FN_BPFCLK_B, FN_CAN1_RX_B,
2457 0, 0, 0, 0,
2458 /* IP6_1_0 [2] */
2459 FN_SSI_SCK6, FN_HSPI_RX2_A,
2460 FN_FMCLK_B, FN_CAN1_TX_B,
2461 }
2462 },
2463 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2464 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
2465
2466 /* IP7_31_29 [3] */
2467 FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
2468 0, FN_HSPI_CS1_A, FN_RX3_B, 0,
2469 /* IP7_28_25 [4] */
2470 FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1,
2471 FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B,
2472 0, 0, 0, 0,
2473 0, 0, 0, 0,
2474 /* IP7_24_22 [3] */
2475 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
2476 0, FN_HSPI_RX1_A, FN_RX4_B, 0,
2477 /* IP7_21 [1] */
2478 FN_VI0_CLK, FN_CAN_CLK_A,
2479 /* IP7_20_18 [3] */
2480 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0,
2481 FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0,
2482 /* IP7_17_15 [3] */
2483 FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A,
2484 0, FN_TX1_C, 0, 0,
2485 /* IP7_14_12 [3] */
2486 FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A,
2487 0, FN_RX1_C, 0, 0,
2488 /* IP7_11_9 [3] */
2489 FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0,
2490 FN_SCK1_C, 0, 0, 0,
2491 /* IP7_8_6 [3] */
2492 FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0,
2493 FN_RTS1_C, 0, 0, 0,
2494 /* IP7_5_4 [2] */
2495 FN_SD0_WP, 0, FN_RX5_A, 0,
2496 /* IP7_3_2 [2] */
2497 FN_SD0_CD, 0, FN_TX5_A, 0,
2498 /* IP7_1_0 [2] */
2499 FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
2500 }
2501 },
2502 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2503 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
2504 /* IP8_31 [1] */
2505 0, 0,
2506 /* IP8_30 [1] */
2507 0, 0,
2508 /* IP8_29_27 [3] */
2509 FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
2510 0, FN_HRX1_B, 0, 0,
2511 /* IP8_26_24 [3] */
2512 FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4,
2513 0, FN_HTX1_B, 0, 0,
2514 /* IP8_23_22 [2] */
2515 FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
2516 FN_RTS1_A, 0,
2517 /* IP8_21_19 [3] */
2518 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4,
2519 FN_CTS1_A, FN_PWM5,
2520 0, 0, 0, 0,
2521 /* IP8_18_16 [3] */
2522 FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4,
2523 0, FN_HSCK1_B, 0, 0,
2524 /* IP8_15_14 [2] */
2525 FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0,
2526 /* IP8_13_11 [3] */
2527 FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C,
2528 0, 0, 0, 0,
2529 /* IP8_10_9 [2] */
2530 FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0,
2531 /* IP8_8_6 [3] */
2532 FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D,
2533 0, 0, 0, 0,
2534 /* IP8_5_3 [3] */
2535 FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D,
2536 0, 0, 0, 0,
2537 /* IP8_2_0 [3] */
2538 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
2539 0, FN_HSPI_TX1_A, FN_TX3_B, 0,
2540 }
2541 },
2542 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2543 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2544 /* IP9_31 [1] */
2545 0, 0,
2546 /* IP9_30 [1] */
2547 0, 0,
2548 /* IP9_29_27 [3] */
2549 FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
2550 FN_ETH_RXD1, FN_FMIN_C,
2551 0, FN_RX2_D,
2552 FN_SCL2_C, 0,
2553 /* IP9_26_24 [3] */
2554 FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT,
2555 FN_ETH_RXD0, FN_BPFCLK_C,
2556 0, FN_TX2_D,
2557 FN_SDA2_C, 0,
2558 /* IP9_23_21 [3] */
2559 FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C,
2560 FN_IERX, FN_RX2_C, 0, 0,
2561 /* IP9_20_18 [3] */
2562 FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0,
2563 FN_IETX, FN_TX2_C, 0, 0,
2564 /* IP9_17_15 [3] */
2565 FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK,
2566 FN_SCK2_C, 0, 0, 0,
2567 /* IP9_14_12 [3] */
2568 FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1,
2569 0, FN_PWM3, 0, 0,
2570 /* IP9_11_9 [3] */
2571 FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0,
2572 0, FN_PWM2, FN_TCLK1, 0,
2573 /* IP9_8_6 [3] */
2574 FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
2575 0, 0, 0, 0,
2576 /* IP9_5_3 [3] */
2577 FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7,
2578 0, FN_HCTS1_B, 0, 0,
2579 /* IP9_2_0 [3] */
2580 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
2581 0, FN_HRTS1_B, 0, 0,
2582 }
2583 },
2584 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2585 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
2586
2587 /* IP10_31 [1] */
2588 0, 0,
2589 /* IP10_30 [1] */
2590 0, 0,
2591 /* IP10_29 [1] */
2592 0, 0,
2593 /* IP10_28 [1] */
2594 0, 0,
2595 /* IP10_27 [1] */
2596 0, 0,
2597 /* IP10_26 [1] */
2598 0, 0,
2599 /* IP10_25 [1] */
2600 0, 0,
2601 /* IP10_24_22 [3] */
2602 FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
2603 FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
2604 /* IP10_21_19 [3] */
2605 FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B,
2606 FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0,
2607 /* IP10_18_16 [3] */
2608 FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1,
2609 FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0,
2610 /* IP10_15_13 [3] */
2611 FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1,
2612 FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0,
2613 /* IP10_12_9 [4] */
2614 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
2615 FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6,
2616 0, 0, 0, 0,
2617 0, 0, 0, 0,
2618 /* IP10_8_6 [3] */
2619 FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B,
2620 FN_ETH_LINK, FN_CAN1_RX_A, 0, 0,
2621 /* IP10_5_3 [3] */
2622 FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2623 FN_ATAWR1, FN_ETH_MDIO,
2624 FN_SCL1_B, 0,
2625 0, 0,
2626 /* IP10_2_0 [3] */
2627 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC,
2628 FN_ATARD1, FN_ETH_MDC,
2629 FN_SDA1_B, 0,
2630 0, 0,
2631 }
2632 },
2633 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2634 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2635 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2636
2637 /* SEL 31 [1] */
2638 0, 0,
2639 /* SEL_30 (SCIF5) [1] */
2640 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
2641 /* SEL_29_28 (SCIF4) [2] */
2642 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B,
2643 FN_SEL_SCIF4_C, 0,
2644 /* SEL_27_26 (SCIF3) [2] */
2645 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B,
2646 FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
2647 /* SEL_25_23 (SCIF2) [3] */
2648 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B,
2649 FN_SEL_SCIF2_C, FN_SEL_SCIF2_D,
2650 FN_SEL_SCIF2_E, 0,
2651 0, 0,
2652 /* SEL_22_21 (SCIF1) [2] */
2653 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B,
2654 FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
2655 /* SEL_20_19 (SCIF0) [2] */
2656 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
2657 FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
2658 /* SEL_18 [1] */
2659 0, 0,
2660 /* SEL_17 (SSI2) [1] */
2661 FN_SEL_SSI2_A, FN_SEL_SSI2_B,
2662 /* SEL_16 (SSI1) [1] */
2663 FN_SEL_SSI1_A, FN_SEL_SSI1_B,
2664 /* SEL_15 (VI1) [1] */
2665 FN_SEL_VI1_A, FN_SEL_VI1_B,
2666 /* SEL_14_13 (VI0) [2] */
2667 FN_SEL_VI0_A, FN_SEL_VI0_B,
2668 FN_SEL_VI0_C, FN_SEL_VI0_D,
2669 /* SEL_12 [1] */
2670 0, 0,
2671 /* SEL_11 (SD2) [1] */
2672 FN_SEL_SD2_A, FN_SEL_SD2_B,
2673 /* SEL_10 (SD1) [1] */
2674 FN_SEL_SD1_A, FN_SEL_SD1_B,
2675 /* SEL_9 (IRQ3) [1] */
2676 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
2677 /* SEL_8_7 (IRQ2) [2] */
2678 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B,
2679 FN_SEL_IRQ2_C, 0,
2680 /* SEL_6 (IRQ1) [1] */
2681 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
2682 /* SEL_5 [1] */
2683 0, 0,
2684 /* SEL_4 (DREQ2) [1] */
2685 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
2686 /* SEL_3 (DREQ1) [1] */
2687 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
2688 /* SEL_2 (DREQ0) [1] */
2689 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
2690 /* SEL_1 (WAIT2) [1] */
2691 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
2692 /* SEL_0 (WAIT1) [1] */
2693 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
2694 }
2695 },
2696 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2697 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
2698 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
2699
2700 /* SEL_31 [1] */
2701 0, 0,
2702 /* SEL_30 [1] */
2703 0, 0,
2704 /* SEL_29 [1] */
2705 0, 0,
2706 /* SEL_28 [1] */
2707 0, 0,
2708 /* SEL_27 (CAN1) [1] */
2709 FN_SEL_CAN1_A, FN_SEL_CAN1_B,
2710 /* SEL_26 (CAN0) [1] */
2711 FN_SEL_CAN0_A, FN_SEL_CAN0_B,
2712 /* SEL_25_24 (CANCLK) [2] */
2713 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
2714 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
2715 /* SEL_23 (HSCIF1) [1] */
2716 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
2717 /* SEL_22 (HSCIF0) [1] */
2718 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
2719 /* SEL_21 [1] */
2720 0, 0,
2721 /* SEL_20 [1] */
2722 0, 0,
2723 /* SEL_19 [1] */
2724 0, 0,
2725 /* SEL_18 [1] */
2726 0, 0,
2727 /* SEL_17 [1] */
2728 0, 0,
2729 /* SEL_16 [1] */
2730 0, 0,
2731 /* SEL_15 [1] */
2732 0, 0,
2733 /* SEL_14_13 (REMOCON) [2] */
2734 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
2735 FN_SEL_REMOCON_C, 0,
2736 /* SEL_12_11 (FM) [2] */
2737 FN_SEL_FM_A, FN_SEL_FM_B,
2738 FN_SEL_FM_C, FN_SEL_FM_D,
2739 /* SEL_10_9 (GPS) [2] */
2740 FN_SEL_GPS_A, FN_SEL_GPS_B,
2741 FN_SEL_GPS_C, 0,
2742 /* SEL_8 (TSIF0) [1] */
2743 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
2744 /* SEL_7 (HSPI2) [1] */
2745 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
2746 /* SEL_6 (HSPI1) [1] */
2747 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
2748 /* SEL_5 (HSPI0) [1] */
2749 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
2750 /* SEL_4_3 (I2C3) [2] */
2751 FN_SEL_I2C3_A, FN_SEL_I2C3_B,
2752 FN_SEL_I2C3_C, 0,
2753 /* SEL_2_1 (I2C2) [2] */
2754 FN_SEL_I2C2_A, FN_SEL_I2C2_B,
2755 FN_SEL_I2C2_C, 0,
2756 /* SEL_0 (I2C1) [1] */
2757 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
2758 }
2759 },
2760 { },
2761};
2762
2763const struct sh_pfc_soc_info r8a7778_pinmux_info = {
2764 .name = "r8a7778_pfc",
2765
2766 .unlock_reg = 0xfffc0000, /* PMMR */
2767
2768 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2769
2770 .pins = pinmux_pins,
2771 .nr_pins = ARRAY_SIZE(pinmux_pins),
2772
2773 .groups = pinmux_groups,
2774 .nr_groups = ARRAY_SIZE(pinmux_groups),
2775
2776 .functions = pinmux_functions,
2777 .nr_functions = ARRAY_SIZE(pinmux_functions),
2778
2779 .cfg_regs = pinmux_config_regs,
2780
2781 .gpio_data = pinmux_data,
2782 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2783};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 8cd90e7e945a..8e22ca6c1044 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1,8 +1,9 @@
1/* 1/*
2 * r8a7779 processor support - PFC hardware block 2 * r8a7779 processor support - PFC hardware block
3 * 3 *
4 * Copyright (C) 2011 Renesas Solutions Corp. 4 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm 5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -19,6 +20,7 @@
19 */ 20 */
20 21
21#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/platform_data/gpio-rcar.h>
22 24
23#include "sh_pfc.h" 25#include "sh_pfc.h"
24 26
@@ -79,7 +81,7 @@
79#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx 81#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
80 82
81#define _GP_GPIO(bank, pin, _name, sfx) \ 83#define _GP_GPIO(bank, pin, _name, sfx) \
82 [(bank * 32) + pin] = { \ 84 [RCAR_GP_PIN(bank, pin)] = { \
83 .name = __stringify(_name), \ 85 .name = __stringify(_name), \
84 .enum_id = _name##_DATA, \ 86 .enum_id = _name##_DATA, \
85 } 87 }
@@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = {
1472/* - DU0 -------------------------------------------------------------------- */ 1474/* - DU0 -------------------------------------------------------------------- */
1473static const unsigned int du0_rgb666_pins[] = { 1475static const unsigned int du0_rgb666_pins[] = {
1474 /* R[7:2], G[7:2], B[7:2] */ 1476 /* R[7:2], G[7:2], B[7:2] */
1475 188, 187, 186, 185, 184, 183, 1477 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1476 194, 193, 192, 191, 190, 189, 1478 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1477 200, 199, 198, 197, 196, 195, 1479 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0),
1480 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
1481 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1482 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3),
1478}; 1483};
1479static const unsigned int du0_rgb666_mux[] = { 1484static const unsigned int du0_rgb666_mux[] = {
1480 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1485 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = {
1486}; 1491};
1487static const unsigned int du0_rgb888_pins[] = { 1492static const unsigned int du0_rgb888_pins[] = {
1488 /* R[7:0], G[7:0], B[7:0] */ 1493 /* R[7:0], G[7:0], B[7:0] */
1489 188, 187, 186, 185, 184, 183, 24, 23, 1494 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1490 194, 193, 192, 191, 190, 189, 26, 25, 1495 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1491 200, 199, 198, 197, 196, 195, 28, 27, 1496 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
1497 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31),
1498 RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
1499 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7),
1500 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4),
1501 RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
1492}; 1502};
1493static const unsigned int du0_rgb888_mux[] = { 1503static const unsigned int du0_rgb888_mux[] = {
1494 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1504 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = {
1500}; 1510};
1501static const unsigned int du0_clk_in_pins[] = { 1511static const unsigned int du0_clk_in_pins[] = {
1502 /* CLKIN */ 1512 /* CLKIN */
1503 29, 1513 RCAR_GP_PIN(0, 29),
1504}; 1514};
1505static const unsigned int du0_clk_in_mux[] = { 1515static const unsigned int du0_clk_in_mux[] = {
1506 DU0_DOTCLKIN_MARK, 1516 DU0_DOTCLKIN_MARK,
1507}; 1517};
1508static const unsigned int du0_clk_out_0_pins[] = { 1518static const unsigned int du0_clk_out_0_pins[] = {
1509 /* CLKOUT */ 1519 /* CLKOUT */
1510 180, 1520 RCAR_GP_PIN(5, 20),
1511}; 1521};
1512static const unsigned int du0_clk_out_0_mux[] = { 1522static const unsigned int du0_clk_out_0_mux[] = {
1513 DU0_DOTCLKOUT0_MARK, 1523 DU0_DOTCLKOUT0_MARK,
1514}; 1524};
1515static const unsigned int du0_clk_out_1_pins[] = { 1525static const unsigned int du0_clk_out_1_pins[] = {
1516 /* CLKOUT */ 1526 /* CLKOUT */
1517 30, 1527 RCAR_GP_PIN(0, 30),
1518}; 1528};
1519static const unsigned int du0_clk_out_1_mux[] = { 1529static const unsigned int du0_clk_out_1_mux[] = {
1520 DU0_DOTCLKOUT1_MARK, 1530 DU0_DOTCLKOUT1_MARK,
1521}; 1531};
1522static const unsigned int du0_sync_0_pins[] = { 1532static const unsigned int du0_sync_0_pins[] = {
1523 /* VSYNC, HSYNC, DISP */ 1533 /* VSYNC, HSYNC, DISP */
1524 182, 181, 31, 1534 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
1525}; 1535};
1526static const unsigned int du0_sync_0_mux[] = { 1536static const unsigned int du0_sync_0_mux[] = {
1527 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, 1537 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = {
1529}; 1539};
1530static const unsigned int du0_sync_1_pins[] = { 1540static const unsigned int du0_sync_1_pins[] = {
1531 /* VSYNC, HSYNC, DISP */ 1541 /* VSYNC, HSYNC, DISP */
1532 182, 181, 32, 1542 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
1533}; 1543};
1534static const unsigned int du0_sync_1_mux[] = { 1544static const unsigned int du0_sync_1_mux[] = {
1535 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, 1545 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = {
1537}; 1547};
1538static const unsigned int du0_oddf_pins[] = { 1548static const unsigned int du0_oddf_pins[] = {
1539 /* ODDF */ 1549 /* ODDF */
1540 31, 1550 RCAR_GP_PIN(0, 31),
1541}; 1551};
1542static const unsigned int du0_oddf_mux[] = { 1552static const unsigned int du0_oddf_mux[] = {
1543 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK 1553 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1544}; 1554};
1545static const unsigned int du0_cde_pins[] = { 1555static const unsigned int du0_cde_pins[] = {
1546 /* CDE */ 1556 /* CDE */
1547 33, 1557 RCAR_GP_PIN(1, 1),
1548}; 1558};
1549static const unsigned int du0_cde_mux[] = { 1559static const unsigned int du0_cde_mux[] = {
1550 DU0_CDE_MARK 1560 DU0_CDE_MARK
@@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = {
1552/* - DU1 -------------------------------------------------------------------- */ 1562/* - DU1 -------------------------------------------------------------------- */
1553static const unsigned int du1_rgb666_pins[] = { 1563static const unsigned int du1_rgb666_pins[] = {
1554 /* R[7:2], G[7:2], B[7:2] */ 1564 /* R[7:2], G[7:2], B[7:2] */
1555 41, 40, 39, 38, 37, 36, 1565 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7),
1556 49, 48, 47, 46, 45, 44, 1566 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
1557 57, 56, 55, 54, 53, 52, 1567 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1568 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1569 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1570 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
1558}; 1571};
1559static const unsigned int du1_rgb666_mux[] = { 1572static const unsigned int du1_rgb666_mux[] = {
1560 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1573 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = {
1566}; 1579};
1567static const unsigned int du1_rgb888_pins[] = { 1580static const unsigned int du1_rgb888_pins[] = {
1568 /* R[7:0], G[7:0], B[7:0] */ 1581 /* R[7:0], G[7:0], B[7:0] */
1569 41, 40, 39, 38, 37, 36, 35, 34, 1582 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7),
1570 49, 48, 47, 46, 45, 44, 43, 32, 1583 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
1571 57, 56, 55, 54, 53, 52, 51, 50, 1584 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17),
1585 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1586 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
1587 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
1588 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1589 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1572}; 1590};
1573static const unsigned int du1_rgb888_mux[] = { 1591static const unsigned int du1_rgb888_mux[] = {
1574 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1592 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = {
1580}; 1598};
1581static const unsigned int du1_clk_in_pins[] = { 1599static const unsigned int du1_clk_in_pins[] = {
1582 /* CLKIN */ 1600 /* CLKIN */
1583 58, 1601 RCAR_GP_PIN(1, 26),
1584}; 1602};
1585static const unsigned int du1_clk_in_mux[] = { 1603static const unsigned int du1_clk_in_mux[] = {
1586 DU1_DOTCLKIN_MARK, 1604 DU1_DOTCLKIN_MARK,
1587}; 1605};
1588static const unsigned int du1_clk_out_pins[] = { 1606static const unsigned int du1_clk_out_pins[] = {
1589 /* CLKOUT */ 1607 /* CLKOUT */
1590 59, 1608 RCAR_GP_PIN(1, 27),
1591}; 1609};
1592static const unsigned int du1_clk_out_mux[] = { 1610static const unsigned int du1_clk_out_mux[] = {
1593 DU1_DOTCLKOUT_MARK, 1611 DU1_DOTCLKOUT_MARK,
1594}; 1612};
1595static const unsigned int du1_sync_0_pins[] = { 1613static const unsigned int du1_sync_0_pins[] = {
1596 /* VSYNC, HSYNC, DISP */ 1614 /* VSYNC, HSYNC, DISP */
1597 61, 60, 62, 1615 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
1598}; 1616};
1599static const unsigned int du1_sync_0_mux[] = { 1617static const unsigned int du1_sync_0_mux[] = {
1600 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 1618 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = {
1602}; 1620};
1603static const unsigned int du1_sync_1_pins[] = { 1621static const unsigned int du1_sync_1_pins[] = {
1604 /* VSYNC, HSYNC, DISP */ 1622 /* VSYNC, HSYNC, DISP */
1605 61, 60, 63, 1623 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
1606}; 1624};
1607static const unsigned int du1_sync_1_mux[] = { 1625static const unsigned int du1_sync_1_mux[] = {
1608 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 1626 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = {
1610}; 1628};
1611static const unsigned int du1_oddf_pins[] = { 1629static const unsigned int du1_oddf_pins[] = {
1612 /* ODDF */ 1630 /* ODDF */
1613 62, 1631 RCAR_GP_PIN(1, 30),
1614}; 1632};
1615static const unsigned int du1_oddf_mux[] = { 1633static const unsigned int du1_oddf_mux[] = {
1616 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK 1634 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1617}; 1635};
1618static const unsigned int du1_cde_pins[] = { 1636static const unsigned int du1_cde_pins[] = {
1619 /* CDE */ 1637 /* CDE */
1620 64, 1638 RCAR_GP_PIN(2, 0),
1621}; 1639};
1622static const unsigned int du1_cde_mux[] = { 1640static const unsigned int du1_cde_mux[] = {
1623 DU1_CDE_MARK 1641 DU1_CDE_MARK
1624}; 1642};
1643/* - Ether ------------------------------------------------------------------ */
1644static const unsigned int ether_rmii_pins[] = {
1645 /*
1646 * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK,
1647 * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
1648 * ETH_MDIO, ETH_MDC
1649 */
1650 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
1651 RCAR_GP_PIN(2, 26),
1652 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
1653 RCAR_GP_PIN(2, 19),
1654 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
1655};
1656static const unsigned int ether_rmii_mux[] = {
1657 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1658 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1659 ETH_MDIO_MARK, ETH_MDC_MARK,
1660};
1661static const unsigned int ether_link_pins[] = {
1662 /* ETH_LINK */
1663 RCAR_GP_PIN(2, 24),
1664};
1665static const unsigned int ether_link_mux[] = {
1666 ETH_LINK_MARK,
1667};
1668static const unsigned int ether_magic_pins[] = {
1669 /* ETH_MAGIC */
1670 RCAR_GP_PIN(2, 25),
1671};
1672static const unsigned int ether_magic_mux[] = {
1673 ETH_MAGIC_MARK,
1674};
1625/* - HSPI0 ------------------------------------------------------------------ */ 1675/* - HSPI0 ------------------------------------------------------------------ */
1626static const unsigned int hspi0_pins[] = { 1676static const unsigned int hspi0_pins[] = {
1627 /* CLK, CS, RX, TX */ 1677 /* CLK, CS, RX, TX */
1628 150, 151, 153, 152, 1678 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
1679 RCAR_GP_PIN(4, 24),
1629}; 1680};
1630static const unsigned int hspi0_mux[] = { 1681static const unsigned int hspi0_mux[] = {
1631 HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, 1682 HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
@@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = {
1633/* - HSPI1 ------------------------------------------------------------------ */ 1684/* - HSPI1 ------------------------------------------------------------------ */
1634static const unsigned int hspi1_pins[] = { 1685static const unsigned int hspi1_pins[] = {
1635 /* CLK, CS, RX, TX */ 1686 /* CLK, CS, RX, TX */
1636 63, 58, 64, 62, 1687 RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
1688 RCAR_GP_PIN(1, 30),
1637}; 1689};
1638static const unsigned int hspi1_mux[] = { 1690static const unsigned int hspi1_mux[] = {
1639 HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, 1691 HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1640}; 1692};
1641static const unsigned int hspi1_b_pins[] = { 1693static const unsigned int hspi1_b_pins[] = {
1642 /* CLK, CS, RX, TX */ 1694 /* CLK, CS, RX, TX */
1643 90, 91, 93, 92, 1695 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
1696 RCAR_GP_PIN(2, 28),
1644}; 1697};
1645static const unsigned int hspi1_b_mux[] = { 1698static const unsigned int hspi1_b_mux[] = {
1646 HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, 1699 HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1647}; 1700};
1648static const unsigned int hspi1_c_pins[] = { 1701static const unsigned int hspi1_c_pins[] = {
1649 /* CLK, CS, RX, TX */ 1702 /* CLK, CS, RX, TX */
1650 141, 142, 144, 143, 1703 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
1704 RCAR_GP_PIN(4, 15),
1651}; 1705};
1652static const unsigned int hspi1_c_mux[] = { 1706static const unsigned int hspi1_c_mux[] = {
1653 HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, 1707 HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1654}; 1708};
1655static const unsigned int hspi1_d_pins[] = { 1709static const unsigned int hspi1_d_pins[] = {
1656 /* CLK, CS, RX, TX */ 1710 /* CLK, CS, RX, TX */
1657 101, 102, 104, 103, 1711 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
1712 RCAR_GP_PIN(3, 7),
1658}; 1713};
1659static const unsigned int hspi1_d_mux[] = { 1714static const unsigned int hspi1_d_mux[] = {
1660 HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, 1715 HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
@@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = {
1662/* - HSPI2 ------------------------------------------------------------------ */ 1717/* - HSPI2 ------------------------------------------------------------------ */
1663static const unsigned int hspi2_pins[] = { 1718static const unsigned int hspi2_pins[] = {
1664 /* CLK, CS, RX, TX */ 1719 /* CLK, CS, RX, TX */
1665 9, 10, 11, 14, 1720 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1721 RCAR_GP_PIN(0, 14),
1666}; 1722};
1667static const unsigned int hspi2_mux[] = { 1723static const unsigned int hspi2_mux[] = {
1668 HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, 1724 HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1669}; 1725};
1670static const unsigned int hspi2_b_pins[] = { 1726static const unsigned int hspi2_b_pins[] = {
1671 /* CLK, CS, RX, TX */ 1727 /* CLK, CS, RX, TX */
1672 7, 13, 8, 6, 1728 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
1729 RCAR_GP_PIN(0, 6),
1673}; 1730};
1674static const unsigned int hspi2_b_mux[] = { 1731static const unsigned int hspi2_b_mux[] = {
1675 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, 1732 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
@@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = {
1677/* - INTC ------------------------------------------------------------------- */ 1734/* - INTC ------------------------------------------------------------------- */
1678static const unsigned int intc_irq0_pins[] = { 1735static const unsigned int intc_irq0_pins[] = {
1679 /* IRQ */ 1736 /* IRQ */
1680 78, 1737 RCAR_GP_PIN(2, 14),
1681}; 1738};
1682static const unsigned int intc_irq0_mux[] = { 1739static const unsigned int intc_irq0_mux[] = {
1683 IRQ0_MARK, 1740 IRQ0_MARK,
1684}; 1741};
1685static const unsigned int intc_irq0_b_pins[] = { 1742static const unsigned int intc_irq0_b_pins[] = {
1686 /* IRQ */ 1743 /* IRQ */
1687 141, 1744 RCAR_GP_PIN(4, 13),
1688}; 1745};
1689static const unsigned int intc_irq0_b_mux[] = { 1746static const unsigned int intc_irq0_b_mux[] = {
1690 IRQ0_B_MARK, 1747 IRQ0_B_MARK,
1691}; 1748};
1692static const unsigned int intc_irq1_pins[] = { 1749static const unsigned int intc_irq1_pins[] = {
1693 /* IRQ */ 1750 /* IRQ */
1694 79, 1751 RCAR_GP_PIN(2, 15),
1695}; 1752};
1696static const unsigned int intc_irq1_mux[] = { 1753static const unsigned int intc_irq1_mux[] = {
1697 IRQ1_MARK, 1754 IRQ1_MARK,
1698}; 1755};
1699static const unsigned int intc_irq1_b_pins[] = { 1756static const unsigned int intc_irq1_b_pins[] = {
1700 /* IRQ */ 1757 /* IRQ */
1701 142, 1758 RCAR_GP_PIN(4, 14),
1702}; 1759};
1703static const unsigned int intc_irq1_b_mux[] = { 1760static const unsigned int intc_irq1_b_mux[] = {
1704 IRQ1_B_MARK, 1761 IRQ1_B_MARK,
1705}; 1762};
1706static const unsigned int intc_irq2_pins[] = { 1763static const unsigned int intc_irq2_pins[] = {
1707 /* IRQ */ 1764 /* IRQ */
1708 88, 1765 RCAR_GP_PIN(2, 24),
1709}; 1766};
1710static const unsigned int intc_irq2_mux[] = { 1767static const unsigned int intc_irq2_mux[] = {
1711 IRQ2_MARK, 1768 IRQ2_MARK,
1712}; 1769};
1713static const unsigned int intc_irq2_b_pins[] = { 1770static const unsigned int intc_irq2_b_pins[] = {
1714 /* IRQ */ 1771 /* IRQ */
1715 143, 1772 RCAR_GP_PIN(4, 15),
1716}; 1773};
1717static const unsigned int intc_irq2_b_mux[] = { 1774static const unsigned int intc_irq2_b_mux[] = {
1718 IRQ2_B_MARK, 1775 IRQ2_B_MARK,
1719}; 1776};
1720static const unsigned int intc_irq3_pins[] = { 1777static const unsigned int intc_irq3_pins[] = {
1721 /* IRQ */ 1778 /* IRQ */
1722 89, 1779 RCAR_GP_PIN(2, 25),
1723}; 1780};
1724static const unsigned int intc_irq3_mux[] = { 1781static const unsigned int intc_irq3_mux[] = {
1725 IRQ3_MARK, 1782 IRQ3_MARK,
1726}; 1783};
1727static const unsigned int intc_irq3_b_pins[] = { 1784static const unsigned int intc_irq3_b_pins[] = {
1728 /* IRQ */ 1785 /* IRQ */
1729 144, 1786 RCAR_GP_PIN(4, 16),
1730}; 1787};
1731static const unsigned int intc_irq3_b_mux[] = { 1788static const unsigned int intc_irq3_b_mux[] = {
1732 IRQ3_B_MARK, 1789 IRQ3_B_MARK,
@@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = {
1734/* - LSBC ------------------------------------------------------------------- */ 1791/* - LSBC ------------------------------------------------------------------- */
1735static const unsigned int lbsc_cs0_pins[] = { 1792static const unsigned int lbsc_cs0_pins[] = {
1736 /* CS */ 1793 /* CS */
1737 13, 1794 RCAR_GP_PIN(0, 13),
1738}; 1795};
1739static const unsigned int lbsc_cs0_mux[] = { 1796static const unsigned int lbsc_cs0_mux[] = {
1740 CS0_MARK, 1797 CS0_MARK,
1741}; 1798};
1742static const unsigned int lbsc_cs1_pins[] = { 1799static const unsigned int lbsc_cs1_pins[] = {
1743 /* CS */ 1800 /* CS */
1744 14, 1801 RCAR_GP_PIN(0, 14),
1745}; 1802};
1746static const unsigned int lbsc_cs1_mux[] = { 1803static const unsigned int lbsc_cs1_mux[] = {
1747 CS1_A26_MARK, 1804 CS1_A26_MARK,
1748}; 1805};
1749static const unsigned int lbsc_ex_cs0_pins[] = { 1806static const unsigned int lbsc_ex_cs0_pins[] = {
1750 /* CS */ 1807 /* CS */
1751 15, 1808 RCAR_GP_PIN(0, 15),
1752}; 1809};
1753static const unsigned int lbsc_ex_cs0_mux[] = { 1810static const unsigned int lbsc_ex_cs0_mux[] = {
1754 EX_CS0_MARK, 1811 EX_CS0_MARK,
1755}; 1812};
1756static const unsigned int lbsc_ex_cs1_pins[] = { 1813static const unsigned int lbsc_ex_cs1_pins[] = {
1757 /* CS */ 1814 /* CS */
1758 16, 1815 RCAR_GP_PIN(0, 16),
1759}; 1816};
1760static const unsigned int lbsc_ex_cs1_mux[] = { 1817static const unsigned int lbsc_ex_cs1_mux[] = {
1761 EX_CS1_MARK, 1818 EX_CS1_MARK,
1762}; 1819};
1763static const unsigned int lbsc_ex_cs2_pins[] = { 1820static const unsigned int lbsc_ex_cs2_pins[] = {
1764 /* CS */ 1821 /* CS */
1765 17, 1822 RCAR_GP_PIN(0, 17),
1766}; 1823};
1767static const unsigned int lbsc_ex_cs2_mux[] = { 1824static const unsigned int lbsc_ex_cs2_mux[] = {
1768 EX_CS2_MARK, 1825 EX_CS2_MARK,
1769}; 1826};
1770static const unsigned int lbsc_ex_cs3_pins[] = { 1827static const unsigned int lbsc_ex_cs3_pins[] = {
1771 /* CS */ 1828 /* CS */
1772 18, 1829 RCAR_GP_PIN(0, 18),
1773}; 1830};
1774static const unsigned int lbsc_ex_cs3_mux[] = { 1831static const unsigned int lbsc_ex_cs3_mux[] = {
1775 EX_CS3_MARK, 1832 EX_CS3_MARK,
1776}; 1833};
1777static const unsigned int lbsc_ex_cs4_pins[] = { 1834static const unsigned int lbsc_ex_cs4_pins[] = {
1778 /* CS */ 1835 /* CS */
1779 19, 1836 RCAR_GP_PIN(0, 19),
1780}; 1837};
1781static const unsigned int lbsc_ex_cs4_mux[] = { 1838static const unsigned int lbsc_ex_cs4_mux[] = {
1782 EX_CS4_MARK, 1839 EX_CS4_MARK,
1783}; 1840};
1784static const unsigned int lbsc_ex_cs5_pins[] = { 1841static const unsigned int lbsc_ex_cs5_pins[] = {
1785 /* CS */ 1842 /* CS */
1786 20, 1843 RCAR_GP_PIN(0, 20),
1787}; 1844};
1788static const unsigned int lbsc_ex_cs5_mux[] = { 1845static const unsigned int lbsc_ex_cs5_mux[] = {
1789 EX_CS5_MARK, 1846 EX_CS5_MARK,
@@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
1791/* - MMCIF ------------------------------------------------------------------ */ 1848/* - MMCIF ------------------------------------------------------------------ */
1792static const unsigned int mmc0_data1_pins[] = { 1849static const unsigned int mmc0_data1_pins[] = {
1793 /* D[0] */ 1850 /* D[0] */
1794 19, 1851 RCAR_GP_PIN(0, 19),
1795}; 1852};
1796static const unsigned int mmc0_data1_mux[] = { 1853static const unsigned int mmc0_data1_mux[] = {
1797 MMC0_D0_MARK, 1854 MMC0_D0_MARK,
1798}; 1855};
1799static const unsigned int mmc0_data4_pins[] = { 1856static const unsigned int mmc0_data4_pins[] = {
1800 /* D[0:3] */ 1857 /* D[0:3] */
1801 19, 20, 21, 2, 1858 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1859 RCAR_GP_PIN(0, 2),
1802}; 1860};
1803static const unsigned int mmc0_data4_mux[] = { 1861static const unsigned int mmc0_data4_mux[] = {
1804 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 1862 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1805}; 1863};
1806static const unsigned int mmc0_data8_pins[] = { 1864static const unsigned int mmc0_data8_pins[] = {
1807 /* D[0:7] */ 1865 /* D[0:7] */
1808 19, 20, 21, 2, 10, 11, 15, 16, 1866 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1867 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1868 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1809}; 1869};
1810static const unsigned int mmc0_data8_mux[] = { 1870static const unsigned int mmc0_data8_mux[] = {
1811 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 1871 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
@@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = {
1813}; 1873};
1814static const unsigned int mmc0_ctrl_pins[] = { 1874static const unsigned int mmc0_ctrl_pins[] = {
1815 /* CMD, CLK */ 1875 /* CMD, CLK */
1816 18, 17, 1876 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
1817}; 1877};
1818static const unsigned int mmc0_ctrl_mux[] = { 1878static const unsigned int mmc0_ctrl_mux[] = {
1819 MMC0_CMD_MARK, MMC0_CLK_MARK, 1879 MMC0_CMD_MARK, MMC0_CLK_MARK,
1820}; 1880};
1821static const unsigned int mmc1_data1_pins[] = { 1881static const unsigned int mmc1_data1_pins[] = {
1822 /* D[0] */ 1882 /* D[0] */
1823 72, 1883 RCAR_GP_PIN(2, 8),
1824}; 1884};
1825static const unsigned int mmc1_data1_mux[] = { 1885static const unsigned int mmc1_data1_mux[] = {
1826 MMC1_D0_MARK, 1886 MMC1_D0_MARK,
1827}; 1887};
1828static const unsigned int mmc1_data4_pins[] = { 1888static const unsigned int mmc1_data4_pins[] = {
1829 /* D[0:3] */ 1889 /* D[0:3] */
1830 72, 73, 74, 75, 1890 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1891 RCAR_GP_PIN(2, 11),
1831}; 1892};
1832static const unsigned int mmc1_data4_mux[] = { 1893static const unsigned int mmc1_data4_mux[] = {
1833 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 1894 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1834}; 1895};
1835static const unsigned int mmc1_data8_pins[] = { 1896static const unsigned int mmc1_data8_pins[] = {
1836 /* D[0:7] */ 1897 /* D[0:7] */
1837 72, 73, 74, 75, 76, 77, 80, 81, 1898 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1899 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1900 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1838}; 1901};
1839static const unsigned int mmc1_data8_mux[] = { 1902static const unsigned int mmc1_data8_mux[] = {
1840 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 1903 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = {
1842}; 1905};
1843static const unsigned int mmc1_ctrl_pins[] = { 1906static const unsigned int mmc1_ctrl_pins[] = {
1844 /* CMD, CLK */ 1907 /* CMD, CLK */
1845 68, 65, 1908 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
1846}; 1909};
1847static const unsigned int mmc1_ctrl_mux[] = { 1910static const unsigned int mmc1_ctrl_mux[] = {
1848 MMC1_CMD_MARK, MMC1_CLK_MARK, 1911 MMC1_CMD_MARK, MMC1_CLK_MARK,
@@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = {
1850/* - SCIF0 ------------------------------------------------------------------ */ 1913/* - SCIF0 ------------------------------------------------------------------ */
1851static const unsigned int scif0_data_pins[] = { 1914static const unsigned int scif0_data_pins[] = {
1852 /* RXD, TXD */ 1915 /* RXD, TXD */
1853 153, 152, 1916 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
1854}; 1917};
1855static const unsigned int scif0_data_mux[] = { 1918static const unsigned int scif0_data_mux[] = {
1856 RX0_MARK, TX0_MARK, 1919 RX0_MARK, TX0_MARK,
1857}; 1920};
1858static const unsigned int scif0_clk_pins[] = { 1921static const unsigned int scif0_clk_pins[] = {
1859 /* SCK */ 1922 /* SCK */
1860 156, 1923 RCAR_GP_PIN(4, 28),
1861}; 1924};
1862static const unsigned int scif0_clk_mux[] = { 1925static const unsigned int scif0_clk_mux[] = {
1863 SCK0_MARK, 1926 SCK0_MARK,
1864}; 1927};
1865static const unsigned int scif0_ctrl_pins[] = { 1928static const unsigned int scif0_ctrl_pins[] = {
1866 /* RTS, CTS */ 1929 /* RTS, CTS */
1867 151, 150, 1930 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
1868}; 1931};
1869static const unsigned int scif0_ctrl_mux[] = { 1932static const unsigned int scif0_ctrl_mux[] = {
1870 RTS0_TANS_MARK, CTS0_MARK, 1933 RTS0_TANS_MARK, CTS0_MARK,
1871}; 1934};
1872static const unsigned int scif0_data_b_pins[] = { 1935static const unsigned int scif0_data_b_pins[] = {
1873 /* RXD, TXD */ 1936 /* RXD, TXD */
1874 20, 19, 1937 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1875}; 1938};
1876static const unsigned int scif0_data_b_mux[] = { 1939static const unsigned int scif0_data_b_mux[] = {
1877 RX0_B_MARK, TX0_B_MARK, 1940 RX0_B_MARK, TX0_B_MARK,
1878}; 1941};
1879static const unsigned int scif0_clk_b_pins[] = { 1942static const unsigned int scif0_clk_b_pins[] = {
1880 /* SCK */ 1943 /* SCK */
1881 33, 1944 RCAR_GP_PIN(1, 1),
1882}; 1945};
1883static const unsigned int scif0_clk_b_mux[] = { 1946static const unsigned int scif0_clk_b_mux[] = {
1884 SCK0_B_MARK, 1947 SCK0_B_MARK,
1885}; 1948};
1886static const unsigned int scif0_ctrl_b_pins[] = { 1949static const unsigned int scif0_ctrl_b_pins[] = {
1887 /* RTS, CTS */ 1950 /* RTS, CTS */
1888 18, 11, 1951 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
1889}; 1952};
1890static const unsigned int scif0_ctrl_b_mux[] = { 1953static const unsigned int scif0_ctrl_b_mux[] = {
1891 RTS0_B_TANS_B_MARK, CTS0_B_MARK, 1954 RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1892}; 1955};
1893static const unsigned int scif0_data_c_pins[] = { 1956static const unsigned int scif0_data_c_pins[] = {
1894 /* RXD, TXD */ 1957 /* RXD, TXD */
1895 146, 147, 1958 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1896}; 1959};
1897static const unsigned int scif0_data_c_mux[] = { 1960static const unsigned int scif0_data_c_mux[] = {
1898 RX0_C_MARK, TX0_C_MARK, 1961 RX0_C_MARK, TX0_C_MARK,
1899}; 1962};
1900static const unsigned int scif0_clk_c_pins[] = { 1963static const unsigned int scif0_clk_c_pins[] = {
1901 /* SCK */ 1964 /* SCK */
1902 145, 1965 RCAR_GP_PIN(4, 17),
1903}; 1966};
1904static const unsigned int scif0_clk_c_mux[] = { 1967static const unsigned int scif0_clk_c_mux[] = {
1905 SCK0_C_MARK, 1968 SCK0_C_MARK,
1906}; 1969};
1907static const unsigned int scif0_ctrl_c_pins[] = { 1970static const unsigned int scif0_ctrl_c_pins[] = {
1908 /* RTS, CTS */ 1971 /* RTS, CTS */
1909 149, 148, 1972 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1910}; 1973};
1911static const unsigned int scif0_ctrl_c_mux[] = { 1974static const unsigned int scif0_ctrl_c_mux[] = {
1912 RTS0_C_TANS_C_MARK, CTS0_C_MARK, 1975 RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1913}; 1976};
1914static const unsigned int scif0_data_d_pins[] = { 1977static const unsigned int scif0_data_d_pins[] = {
1915 /* RXD, TXD */ 1978 /* RXD, TXD */
1916 43, 42, 1979 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1917}; 1980};
1918static const unsigned int scif0_data_d_mux[] = { 1981static const unsigned int scif0_data_d_mux[] = {
1919 RX0_D_MARK, TX0_D_MARK, 1982 RX0_D_MARK, TX0_D_MARK,
1920}; 1983};
1921static const unsigned int scif0_clk_d_pins[] = { 1984static const unsigned int scif0_clk_d_pins[] = {
1922 /* SCK */ 1985 /* SCK */
1923 50, 1986 RCAR_GP_PIN(1, 18),
1924}; 1987};
1925static const unsigned int scif0_clk_d_mux[] = { 1988static const unsigned int scif0_clk_d_mux[] = {
1926 SCK0_D_MARK, 1989 SCK0_D_MARK,
1927}; 1990};
1928static const unsigned int scif0_ctrl_d_pins[] = { 1991static const unsigned int scif0_ctrl_d_pins[] = {
1929 /* RTS, CTS */ 1992 /* RTS, CTS */
1930 51, 35, 1993 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
1931}; 1994};
1932static const unsigned int scif0_ctrl_d_mux[] = { 1995static const unsigned int scif0_ctrl_d_mux[] = {
1933 RTS0_D_TANS_D_MARK, CTS0_D_MARK, 1996 RTS0_D_TANS_D_MARK, CTS0_D_MARK,
@@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = {
1935/* - SCIF1 ------------------------------------------------------------------ */ 1998/* - SCIF1 ------------------------------------------------------------------ */
1936static const unsigned int scif1_data_pins[] = { 1999static const unsigned int scif1_data_pins[] = {
1937 /* RXD, TXD */ 2000 /* RXD, TXD */
1938 149, 148, 2001 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1939}; 2002};
1940static const unsigned int scif1_data_mux[] = { 2003static const unsigned int scif1_data_mux[] = {
1941 RX1_MARK, TX1_MARK, 2004 RX1_MARK, TX1_MARK,
1942}; 2005};
1943static const unsigned int scif1_clk_pins[] = { 2006static const unsigned int scif1_clk_pins[] = {
1944 /* SCK */ 2007 /* SCK */
1945 145, 2008 RCAR_GP_PIN(4, 17),
1946}; 2009};
1947static const unsigned int scif1_clk_mux[] = { 2010static const unsigned int scif1_clk_mux[] = {
1948 SCK1_MARK, 2011 SCK1_MARK,
1949}; 2012};
1950static const unsigned int scif1_ctrl_pins[] = { 2013static const unsigned int scif1_ctrl_pins[] = {
1951 /* RTS, CTS */ 2014 /* RTS, CTS */
1952 147, 146, 2015 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1953}; 2016};
1954static const unsigned int scif1_ctrl_mux[] = { 2017static const unsigned int scif1_ctrl_mux[] = {
1955 RTS1_TANS_MARK, CTS1_MARK, 2018 RTS1_TANS_MARK, CTS1_MARK,
1956}; 2019};
1957static const unsigned int scif1_data_b_pins[] = { 2020static const unsigned int scif1_data_b_pins[] = {
1958 /* RXD, TXD */ 2021 /* RXD, TXD */
1959 117, 114, 2022 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
1960}; 2023};
1961static const unsigned int scif1_data_b_mux[] = { 2024static const unsigned int scif1_data_b_mux[] = {
1962 RX1_B_MARK, TX1_B_MARK, 2025 RX1_B_MARK, TX1_B_MARK,
1963}; 2026};
1964static const unsigned int scif1_clk_b_pins[] = { 2027static const unsigned int scif1_clk_b_pins[] = {
1965 /* SCK */ 2028 /* SCK */
1966 113, 2029 RCAR_GP_PIN(3, 17),
1967}; 2030};
1968static const unsigned int scif1_clk_b_mux[] = { 2031static const unsigned int scif1_clk_b_mux[] = {
1969 SCK1_B_MARK, 2032 SCK1_B_MARK,
1970}; 2033};
1971static const unsigned int scif1_ctrl_b_pins[] = { 2034static const unsigned int scif1_ctrl_b_pins[] = {
1972 /* RTS, CTS */ 2035 /* RTS, CTS */
1973 115, 116, 2036 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
1974}; 2037};
1975static const unsigned int scif1_ctrl_b_mux[] = { 2038static const unsigned int scif1_ctrl_b_mux[] = {
1976 RTS1_B_TANS_B_MARK, CTS1_B_MARK, 2039 RTS1_B_TANS_B_MARK, CTS1_B_MARK,
1977}; 2040};
1978static const unsigned int scif1_data_c_pins[] = { 2041static const unsigned int scif1_data_c_pins[] = {
1979 /* RXD, TXD */ 2042 /* RXD, TXD */
1980 67, 66, 2043 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1981}; 2044};
1982static const unsigned int scif1_data_c_mux[] = { 2045static const unsigned int scif1_data_c_mux[] = {
1983 RX1_C_MARK, TX1_C_MARK, 2046 RX1_C_MARK, TX1_C_MARK,
1984}; 2047};
1985static const unsigned int scif1_clk_c_pins[] = { 2048static const unsigned int scif1_clk_c_pins[] = {
1986 /* SCK */ 2049 /* SCK */
1987 86, 2050 RCAR_GP_PIN(2, 22),
1988}; 2051};
1989static const unsigned int scif1_clk_c_mux[] = { 2052static const unsigned int scif1_clk_c_mux[] = {
1990 SCK1_C_MARK, 2053 SCK1_C_MARK,
1991}; 2054};
1992static const unsigned int scif1_ctrl_c_pins[] = { 2055static const unsigned int scif1_ctrl_c_pins[] = {
1993 /* RTS, CTS */ 2056 /* RTS, CTS */
1994 69, 68, 2057 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1995}; 2058};
1996static const unsigned int scif1_ctrl_c_mux[] = { 2059static const unsigned int scif1_ctrl_c_mux[] = {
1997 RTS1_C_TANS_C_MARK, CTS1_C_MARK, 2060 RTS1_C_TANS_C_MARK, CTS1_C_MARK,
@@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = {
1999/* - SCIF2 ------------------------------------------------------------------ */ 2062/* - SCIF2 ------------------------------------------------------------------ */
2000static const unsigned int scif2_data_pins[] = { 2063static const unsigned int scif2_data_pins[] = {
2001 /* RXD, TXD */ 2064 /* RXD, TXD */
2002 106, 105, 2065 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
2003}; 2066};
2004static const unsigned int scif2_data_mux[] = { 2067static const unsigned int scif2_data_mux[] = {
2005 RX2_MARK, TX2_MARK, 2068 RX2_MARK, TX2_MARK,
2006}; 2069};
2007static const unsigned int scif2_clk_pins[] = { 2070static const unsigned int scif2_clk_pins[] = {
2008 /* SCK */ 2071 /* SCK */
2009 107, 2072 RCAR_GP_PIN(3, 11),
2010}; 2073};
2011static const unsigned int scif2_clk_mux[] = { 2074static const unsigned int scif2_clk_mux[] = {
2012 SCK2_MARK, 2075 SCK2_MARK,
2013}; 2076};
2014static const unsigned int scif2_data_b_pins[] = { 2077static const unsigned int scif2_data_b_pins[] = {
2015 /* RXD, TXD */ 2078 /* RXD, TXD */
2016 120, 119, 2079 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
2017}; 2080};
2018static const unsigned int scif2_data_b_mux[] = { 2081static const unsigned int scif2_data_b_mux[] = {
2019 RX2_B_MARK, TX2_B_MARK, 2082 RX2_B_MARK, TX2_B_MARK,
2020}; 2083};
2021static const unsigned int scif2_clk_b_pins[] = { 2084static const unsigned int scif2_clk_b_pins[] = {
2022 /* SCK */ 2085 /* SCK */
2023 118, 2086 RCAR_GP_PIN(3, 22),
2024}; 2087};
2025static const unsigned int scif2_clk_b_mux[] = { 2088static const unsigned int scif2_clk_b_mux[] = {
2026 SCK2_B_MARK, 2089 SCK2_B_MARK,
2027}; 2090};
2028static const unsigned int scif2_data_c_pins[] = { 2091static const unsigned int scif2_data_c_pins[] = {
2029 /* RXD, TXD */ 2092 /* RXD, TXD */
2030 33, 31, 2093 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
2031}; 2094};
2032static const unsigned int scif2_data_c_mux[] = { 2095static const unsigned int scif2_data_c_mux[] = {
2033 RX2_C_MARK, TX2_C_MARK, 2096 RX2_C_MARK, TX2_C_MARK,
2034}; 2097};
2035static const unsigned int scif2_clk_c_pins[] = { 2098static const unsigned int scif2_clk_c_pins[] = {
2036 /* SCK */ 2099 /* SCK */
2037 32, 2100 RCAR_GP_PIN(1, 0),
2038}; 2101};
2039static const unsigned int scif2_clk_c_mux[] = { 2102static const unsigned int scif2_clk_c_mux[] = {
2040 SCK2_C_MARK, 2103 SCK2_C_MARK,
2041}; 2104};
2042static const unsigned int scif2_data_d_pins[] = { 2105static const unsigned int scif2_data_d_pins[] = {
2043 /* RXD, TXD */ 2106 /* RXD, TXD */
2044 64, 62, 2107 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2045}; 2108};
2046static const unsigned int scif2_data_d_mux[] = { 2109static const unsigned int scif2_data_d_mux[] = {
2047 RX2_D_MARK, TX2_D_MARK, 2110 RX2_D_MARK, TX2_D_MARK,
2048}; 2111};
2049static const unsigned int scif2_clk_d_pins[] = { 2112static const unsigned int scif2_clk_d_pins[] = {
2050 /* SCK */ 2113 /* SCK */
2051 63, 2114 RCAR_GP_PIN(1, 31),
2052}; 2115};
2053static const unsigned int scif2_clk_d_mux[] = { 2116static const unsigned int scif2_clk_d_mux[] = {
2054 SCK2_D_MARK, 2117 SCK2_D_MARK,
2055}; 2118};
2056static const unsigned int scif2_data_e_pins[] = { 2119static const unsigned int scif2_data_e_pins[] = {
2057 /* RXD, TXD */ 2120 /* RXD, TXD */
2058 20, 19, 2121 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
2059}; 2122};
2060static const unsigned int scif2_data_e_mux[] = { 2123static const unsigned int scif2_data_e_mux[] = {
2061 RX2_E_MARK, TX2_E_MARK, 2124 RX2_E_MARK, TX2_E_MARK,
@@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = {
2063/* - SCIF3 ------------------------------------------------------------------ */ 2126/* - SCIF3 ------------------------------------------------------------------ */
2064static const unsigned int scif3_data_pins[] = { 2127static const unsigned int scif3_data_pins[] = {
2065 /* RXD, TXD */ 2128 /* RXD, TXD */
2066 137, 136, 2129 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
2067}; 2130};
2068static const unsigned int scif3_data_mux[] = { 2131static const unsigned int scif3_data_mux[] = {
2069 RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, 2132 RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2070}; 2133};
2071static const unsigned int scif3_clk_pins[] = { 2134static const unsigned int scif3_clk_pins[] = {
2072 /* SCK */ 2135 /* SCK */
2073 135, 2136 RCAR_GP_PIN(4, 7),
2074}; 2137};
2075static const unsigned int scif3_clk_mux[] = { 2138static const unsigned int scif3_clk_mux[] = {
2076 SCK3_MARK, 2139 SCK3_MARK,
@@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = {
2078 2141
2079static const unsigned int scif3_data_b_pins[] = { 2142static const unsigned int scif3_data_b_pins[] = {
2080 /* RXD, TXD */ 2143 /* RXD, TXD */
2081 64, 62, 2144 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2082}; 2145};
2083static const unsigned int scif3_data_b_mux[] = { 2146static const unsigned int scif3_data_b_mux[] = {
2084 RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, 2147 RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2085}; 2148};
2086static const unsigned int scif3_data_c_pins[] = { 2149static const unsigned int scif3_data_c_pins[] = {
2087 /* RXD, TXD */ 2150 /* RXD, TXD */
2088 15, 12, 2151 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
2089}; 2152};
2090static const unsigned int scif3_data_c_mux[] = { 2153static const unsigned int scif3_data_c_mux[] = {
2091 RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, 2154 RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2092}; 2155};
2093static const unsigned int scif3_data_d_pins[] = { 2156static const unsigned int scif3_data_d_pins[] = {
2094 /* RXD, TXD */ 2157 /* RXD, TXD */
2095 30, 29, 2158 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
2096}; 2159};
2097static const unsigned int scif3_data_d_mux[] = { 2160static const unsigned int scif3_data_d_mux[] = {
2098 RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, 2161 RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2099}; 2162};
2100static const unsigned int scif3_data_e_pins[] = { 2163static const unsigned int scif3_data_e_pins[] = {
2101 /* RXD, TXD */ 2164 /* RXD, TXD */
2102 35, 34, 2165 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2103}; 2166};
2104static const unsigned int scif3_data_e_mux[] = { 2167static const unsigned int scif3_data_e_mux[] = {
2105 RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, 2168 RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2106}; 2169};
2107static const unsigned int scif3_clk_e_pins[] = { 2170static const unsigned int scif3_clk_e_pins[] = {
2108 /* SCK */ 2171 /* SCK */
2109 42, 2172 RCAR_GP_PIN(1, 10),
2110}; 2173};
2111static const unsigned int scif3_clk_e_mux[] = { 2174static const unsigned int scif3_clk_e_mux[] = {
2112 SCK3_E_MARK, 2175 SCK3_E_MARK,
@@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = {
2114/* - SCIF4 ------------------------------------------------------------------ */ 2177/* - SCIF4 ------------------------------------------------------------------ */
2115static const unsigned int scif4_data_pins[] = { 2178static const unsigned int scif4_data_pins[] = {
2116 /* RXD, TXD */ 2179 /* RXD, TXD */
2117 123, 122, 2180 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
2118}; 2181};
2119static const unsigned int scif4_data_mux[] = { 2182static const unsigned int scif4_data_mux[] = {
2120 RX4_MARK, TX4_MARK, 2183 RX4_MARK, TX4_MARK,
2121}; 2184};
2122static const unsigned int scif4_clk_pins[] = { 2185static const unsigned int scif4_clk_pins[] = {
2123 /* SCK */ 2186 /* SCK */
2124 121, 2187 RCAR_GP_PIN(3, 25),
2125}; 2188};
2126static const unsigned int scif4_clk_mux[] = { 2189static const unsigned int scif4_clk_mux[] = {
2127 SCK4_MARK, 2190 SCK4_MARK,
2128}; 2191};
2129static const unsigned int scif4_data_b_pins[] = { 2192static const unsigned int scif4_data_b_pins[] = {
2130 /* RXD, TXD */ 2193 /* RXD, TXD */
2131 111, 110, 2194 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2132}; 2195};
2133static const unsigned int scif4_data_b_mux[] = { 2196static const unsigned int scif4_data_b_mux[] = {
2134 RX4_B_MARK, TX4_B_MARK, 2197 RX4_B_MARK, TX4_B_MARK,
2135}; 2198};
2136static const unsigned int scif4_clk_b_pins[] = { 2199static const unsigned int scif4_clk_b_pins[] = {
2137 /* SCK */ 2200 /* SCK */
2138 112, 2201 RCAR_GP_PIN(3, 16),
2139}; 2202};
2140static const unsigned int scif4_clk_b_mux[] = { 2203static const unsigned int scif4_clk_b_mux[] = {
2141 SCK4_B_MARK, 2204 SCK4_B_MARK,
2142}; 2205};
2143static const unsigned int scif4_data_c_pins[] = { 2206static const unsigned int scif4_data_c_pins[] = {
2144 /* RXD, TXD */ 2207 /* RXD, TXD */
2145 22, 21, 2208 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
2146}; 2209};
2147static const unsigned int scif4_data_c_mux[] = { 2210static const unsigned int scif4_data_c_mux[] = {
2148 RX4_C_MARK, TX4_C_MARK, 2211 RX4_C_MARK, TX4_C_MARK,
2149}; 2212};
2150static const unsigned int scif4_data_d_pins[] = { 2213static const unsigned int scif4_data_d_pins[] = {
2151 /* RXD, TXD */ 2214 /* RXD, TXD */
2152 69, 68, 2215 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2153}; 2216};
2154static const unsigned int scif4_data_d_mux[] = { 2217static const unsigned int scif4_data_d_mux[] = {
2155 RX4_D_MARK, TX4_D_MARK, 2218 RX4_D_MARK, TX4_D_MARK,
@@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = {
2157/* - SCIF5 ------------------------------------------------------------------ */ 2220/* - SCIF5 ------------------------------------------------------------------ */
2158static const unsigned int scif5_data_pins[] = { 2221static const unsigned int scif5_data_pins[] = {
2159 /* RXD, TXD */ 2222 /* RXD, TXD */
2160 51, 50, 2223 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2161}; 2224};
2162static const unsigned int scif5_data_mux[] = { 2225static const unsigned int scif5_data_mux[] = {
2163 RX5_MARK, TX5_MARK, 2226 RX5_MARK, TX5_MARK,
2164}; 2227};
2165static const unsigned int scif5_clk_pins[] = { 2228static const unsigned int scif5_clk_pins[] = {
2166 /* SCK */ 2229 /* SCK */
2167 43, 2230 RCAR_GP_PIN(1, 11),
2168}; 2231};
2169static const unsigned int scif5_clk_mux[] = { 2232static const unsigned int scif5_clk_mux[] = {
2170 SCK5_MARK, 2233 SCK5_MARK,
2171}; 2234};
2172static const unsigned int scif5_data_b_pins[] = { 2235static const unsigned int scif5_data_b_pins[] = {
2173 /* RXD, TXD */ 2236 /* RXD, TXD */
2174 18, 11, 2237 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2175}; 2238};
2176static const unsigned int scif5_data_b_mux[] = { 2239static const unsigned int scif5_data_b_mux[] = {
2177 RX5_B_MARK, TX5_B_MARK, 2240 RX5_B_MARK, TX5_B_MARK,
2178}; 2241};
2179static const unsigned int scif5_clk_b_pins[] = { 2242static const unsigned int scif5_clk_b_pins[] = {
2180 /* SCK */ 2243 /* SCK */
2181 19, 2244 RCAR_GP_PIN(0, 19),
2182}; 2245};
2183static const unsigned int scif5_clk_b_mux[] = { 2246static const unsigned int scif5_clk_b_mux[] = {
2184 SCK5_B_MARK, 2247 SCK5_B_MARK,
2185}; 2248};
2186static const unsigned int scif5_data_c_pins[] = { 2249static const unsigned int scif5_data_c_pins[] = {
2187 /* RXD, TXD */ 2250 /* RXD, TXD */
2188 24, 23, 2251 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
2189}; 2252};
2190static const unsigned int scif5_data_c_mux[] = { 2253static const unsigned int scif5_data_c_mux[] = {
2191 RX5_C_MARK, TX5_C_MARK, 2254 RX5_C_MARK, TX5_C_MARK,
2192}; 2255};
2193static const unsigned int scif5_clk_c_pins[] = { 2256static const unsigned int scif5_clk_c_pins[] = {
2194 /* SCK */ 2257 /* SCK */
2195 28, 2258 RCAR_GP_PIN(0, 28),
2196}; 2259};
2197static const unsigned int scif5_clk_c_mux[] = { 2260static const unsigned int scif5_clk_c_mux[] = {
2198 SCK5_C_MARK, 2261 SCK5_C_MARK,
2199}; 2262};
2200static const unsigned int scif5_data_d_pins[] = { 2263static const unsigned int scif5_data_d_pins[] = {
2201 /* RXD, TXD */ 2264 /* RXD, TXD */
2202 8, 6, 2265 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
2203}; 2266};
2204static const unsigned int scif5_data_d_mux[] = { 2267static const unsigned int scif5_data_d_mux[] = {
2205 RX5_D_MARK, TX5_D_MARK, 2268 RX5_D_MARK, TX5_D_MARK,
2206}; 2269};
2207static const unsigned int scif5_clk_d_pins[] = { 2270static const unsigned int scif5_clk_d_pins[] = {
2208 /* SCK */ 2271 /* SCK */
2209 7, 2272 RCAR_GP_PIN(0, 7),
2210}; 2273};
2211static const unsigned int scif5_clk_d_mux[] = { 2274static const unsigned int scif5_clk_d_mux[] = {
2212 SCK5_D_MARK, 2275 SCK5_D_MARK,
@@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = {
2214/* - SDHI0 ------------------------------------------------------------------ */ 2277/* - SDHI0 ------------------------------------------------------------------ */
2215static const unsigned int sdhi0_data1_pins[] = { 2278static const unsigned int sdhi0_data1_pins[] = {
2216 /* D0 */ 2279 /* D0 */
2217 117, 2280 RCAR_GP_PIN(3, 21),
2218}; 2281};
2219static const unsigned int sdhi0_data1_mux[] = { 2282static const unsigned int sdhi0_data1_mux[] = {
2220 SD0_DAT0_MARK, 2283 SD0_DAT0_MARK,
2221}; 2284};
2222static const unsigned int sdhi0_data4_pins[] = { 2285static const unsigned int sdhi0_data4_pins[] = {
2223 /* D[0:3] */ 2286 /* D[0:3] */
2224 117, 118, 119, 120, 2287 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2288 RCAR_GP_PIN(3, 24),
2225}; 2289};
2226static const unsigned int sdhi0_data4_mux[] = { 2290static const unsigned int sdhi0_data4_mux[] = {
2227 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 2291 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2228}; 2292};
2229static const unsigned int sdhi0_ctrl_pins[] = { 2293static const unsigned int sdhi0_ctrl_pins[] = {
2230 /* CMD, CLK */ 2294 /* CMD, CLK */
2231 114, 113, 2295 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
2232}; 2296};
2233static const unsigned int sdhi0_ctrl_mux[] = { 2297static const unsigned int sdhi0_ctrl_mux[] = {
2234 SD0_CMD_MARK, SD0_CLK_MARK, 2298 SD0_CMD_MARK, SD0_CLK_MARK,
2235}; 2299};
2236static const unsigned int sdhi0_cd_pins[] = { 2300static const unsigned int sdhi0_cd_pins[] = {
2237 /* CD */ 2301 /* CD */
2238 115, 2302 RCAR_GP_PIN(3, 19),
2239}; 2303};
2240static const unsigned int sdhi0_cd_mux[] = { 2304static const unsigned int sdhi0_cd_mux[] = {
2241 SD0_CD_MARK, 2305 SD0_CD_MARK,
2242}; 2306};
2243static const unsigned int sdhi0_wp_pins[] = { 2307static const unsigned int sdhi0_wp_pins[] = {
2244 /* WP */ 2308 /* WP */
2245 116, 2309 RCAR_GP_PIN(3, 20),
2246}; 2310};
2247static const unsigned int sdhi0_wp_mux[] = { 2311static const unsigned int sdhi0_wp_mux[] = {
2248 SD0_WP_MARK, 2312 SD0_WP_MARK,
@@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = {
2250/* - SDHI1 ------------------------------------------------------------------ */ 2314/* - SDHI1 ------------------------------------------------------------------ */
2251static const unsigned int sdhi1_data1_pins[] = { 2315static const unsigned int sdhi1_data1_pins[] = {
2252 /* D0 */ 2316 /* D0 */
2253 19, 2317 RCAR_GP_PIN(0, 19),
2254}; 2318};
2255static const unsigned int sdhi1_data1_mux[] = { 2319static const unsigned int sdhi1_data1_mux[] = {
2256 SD1_DAT0_MARK, 2320 SD1_DAT0_MARK,
2257}; 2321};
2258static const unsigned int sdhi1_data4_pins[] = { 2322static const unsigned int sdhi1_data4_pins[] = {
2259 /* D[0:3] */ 2323 /* D[0:3] */
2260 19, 20, 21, 2, 2324 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
2325 RCAR_GP_PIN(0, 2),
2261}; 2326};
2262static const unsigned int sdhi1_data4_mux[] = { 2327static const unsigned int sdhi1_data4_mux[] = {
2263 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 2328 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2264}; 2329};
2265static const unsigned int sdhi1_ctrl_pins[] = { 2330static const unsigned int sdhi1_ctrl_pins[] = {
2266 /* CMD, CLK */ 2331 /* CMD, CLK */
2267 18, 17, 2332 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
2268}; 2333};
2269static const unsigned int sdhi1_ctrl_mux[] = { 2334static const unsigned int sdhi1_ctrl_mux[] = {
2270 SD1_CMD_MARK, SD1_CLK_MARK, 2335 SD1_CMD_MARK, SD1_CLK_MARK,
2271}; 2336};
2272static const unsigned int sdhi1_cd_pins[] = { 2337static const unsigned int sdhi1_cd_pins[] = {
2273 /* CD */ 2338 /* CD */
2274 10, 2339 RCAR_GP_PIN(0, 10),
2275}; 2340};
2276static const unsigned int sdhi1_cd_mux[] = { 2341static const unsigned int sdhi1_cd_mux[] = {
2277 SD1_CD_MARK, 2342 SD1_CD_MARK,
2278}; 2343};
2279static const unsigned int sdhi1_wp_pins[] = { 2344static const unsigned int sdhi1_wp_pins[] = {
2280 /* WP */ 2345 /* WP */
2281 11, 2346 RCAR_GP_PIN(0, 11),
2282}; 2347};
2283static const unsigned int sdhi1_wp_mux[] = { 2348static const unsigned int sdhi1_wp_mux[] = {
2284 SD1_WP_MARK, 2349 SD1_WP_MARK,
@@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = {
2286/* - SDHI2 ------------------------------------------------------------------ */ 2351/* - SDHI2 ------------------------------------------------------------------ */
2287static const unsigned int sdhi2_data1_pins[] = { 2352static const unsigned int sdhi2_data1_pins[] = {
2288 /* D0 */ 2353 /* D0 */
2289 97, 2354 RCAR_GP_PIN(3, 1),
2290}; 2355};
2291static const unsigned int sdhi2_data1_mux[] = { 2356static const unsigned int sdhi2_data1_mux[] = {
2292 SD2_DAT0_MARK, 2357 SD2_DAT0_MARK,
2293}; 2358};
2294static const unsigned int sdhi2_data4_pins[] = { 2359static const unsigned int sdhi2_data4_pins[] = {
2295 /* D[0:3] */ 2360 /* D[0:3] */
2296 97, 98, 99, 100, 2361 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2362 RCAR_GP_PIN(3, 4),
2297}; 2363};
2298static const unsigned int sdhi2_data4_mux[] = { 2364static const unsigned int sdhi2_data4_mux[] = {
2299 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 2365 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2300}; 2366};
2301static const unsigned int sdhi2_ctrl_pins[] = { 2367static const unsigned int sdhi2_ctrl_pins[] = {
2302 /* CMD, CLK */ 2368 /* CMD, CLK */
2303 102, 101, 2369 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2304}; 2370};
2305static const unsigned int sdhi2_ctrl_mux[] = { 2371static const unsigned int sdhi2_ctrl_mux[] = {
2306 SD2_CMD_MARK, SD2_CLK_MARK, 2372 SD2_CMD_MARK, SD2_CLK_MARK,
2307}; 2373};
2308static const unsigned int sdhi2_cd_pins[] = { 2374static const unsigned int sdhi2_cd_pins[] = {
2309 /* CD */ 2375 /* CD */
2310 103, 2376 RCAR_GP_PIN(3, 7),
2311}; 2377};
2312static const unsigned int sdhi2_cd_mux[] = { 2378static const unsigned int sdhi2_cd_mux[] = {
2313 SD2_CD_MARK, 2379 SD2_CD_MARK,
2314}; 2380};
2315static const unsigned int sdhi2_wp_pins[] = { 2381static const unsigned int sdhi2_wp_pins[] = {
2316 /* WP */ 2382 /* WP */
2317 104, 2383 RCAR_GP_PIN(3, 8),
2318}; 2384};
2319static const unsigned int sdhi2_wp_mux[] = { 2385static const unsigned int sdhi2_wp_mux[] = {
2320 SD2_WP_MARK, 2386 SD2_WP_MARK,
@@ -2322,35 +2388,36 @@ static const unsigned int sdhi2_wp_mux[] = {
2322/* - SDHI3 ------------------------------------------------------------------ */ 2388/* - SDHI3 ------------------------------------------------------------------ */
2323static const unsigned int sdhi3_data1_pins[] = { 2389static const unsigned int sdhi3_data1_pins[] = {
2324 /* D0 */ 2390 /* D0 */
2325 50, 2391 RCAR_GP_PIN(1, 18),
2326}; 2392};
2327static const unsigned int sdhi3_data1_mux[] = { 2393static const unsigned int sdhi3_data1_mux[] = {
2328 SD3_DAT0_MARK, 2394 SD3_DAT0_MARK,
2329}; 2395};
2330static const unsigned int sdhi3_data4_pins[] = { 2396static const unsigned int sdhi3_data4_pins[] = {
2331 /* D[0:3] */ 2397 /* D[0:3] */
2332 50, 51, 52, 53, 2398 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
2399 RCAR_GP_PIN(1, 21),
2333}; 2400};
2334static const unsigned int sdhi3_data4_mux[] = { 2401static const unsigned int sdhi3_data4_mux[] = {
2335 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 2402 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2336}; 2403};
2337static const unsigned int sdhi3_ctrl_pins[] = { 2404static const unsigned int sdhi3_ctrl_pins[] = {
2338 /* CMD, CLK */ 2405 /* CMD, CLK */
2339 35, 34, 2406 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2340}; 2407};
2341static const unsigned int sdhi3_ctrl_mux[] = { 2408static const unsigned int sdhi3_ctrl_mux[] = {
2342 SD3_CMD_MARK, SD3_CLK_MARK, 2409 SD3_CMD_MARK, SD3_CLK_MARK,
2343}; 2410};
2344static const unsigned int sdhi3_cd_pins[] = { 2411static const unsigned int sdhi3_cd_pins[] = {
2345 /* CD */ 2412 /* CD */
2346 62, 2413 RCAR_GP_PIN(1, 30),
2347}; 2414};
2348static const unsigned int sdhi3_cd_mux[] = { 2415static const unsigned int sdhi3_cd_mux[] = {
2349 SD3_CD_MARK, 2416 SD3_CD_MARK,
2350}; 2417};
2351static const unsigned int sdhi3_wp_pins[] = { 2418static const unsigned int sdhi3_wp_pins[] = {
2352 /* WP */ 2419 /* WP */
2353 64, 2420 RCAR_GP_PIN(2, 0),
2354}; 2421};
2355static const unsigned int sdhi3_wp_mux[] = { 2422static const unsigned int sdhi3_wp_mux[] = {
2356 SD3_WP_MARK, 2423 SD3_WP_MARK,
@@ -2358,14 +2425,14 @@ static const unsigned int sdhi3_wp_mux[] = {
2358/* - USB0 ------------------------------------------------------------------- */ 2425/* - USB0 ------------------------------------------------------------------- */
2359static const unsigned int usb0_pins[] = { 2426static const unsigned int usb0_pins[] = {
2360 /* PENC */ 2427 /* PENC */
2361 154, 2428 RCAR_GP_PIN(4, 26),
2362}; 2429};
2363static const unsigned int usb0_mux[] = { 2430static const unsigned int usb0_mux[] = {
2364 USB_PENC0_MARK, 2431 USB_PENC0_MARK,
2365}; 2432};
2366static const unsigned int usb0_ovc_pins[] = { 2433static const unsigned int usb0_ovc_pins[] = {
2367 /* USB_OVC */ 2434 /* USB_OVC */
2368 150 2435 RCAR_GP_PIN(4, 22),
2369}; 2436};
2370static const unsigned int usb0_ovc_mux[] = { 2437static const unsigned int usb0_ovc_mux[] = {
2371 USB_OVC0_MARK, 2438 USB_OVC0_MARK,
@@ -2373,14 +2440,14 @@ static const unsigned int usb0_ovc_mux[] = {
2373/* - USB1 ------------------------------------------------------------------- */ 2440/* - USB1 ------------------------------------------------------------------- */
2374static const unsigned int usb1_pins[] = { 2441static const unsigned int usb1_pins[] = {
2375 /* PENC */ 2442 /* PENC */
2376 155, 2443 RCAR_GP_PIN(4, 27),
2377}; 2444};
2378static const unsigned int usb1_mux[] = { 2445static const unsigned int usb1_mux[] = {
2379 USB_PENC1_MARK, 2446 USB_PENC1_MARK,
2380}; 2447};
2381static const unsigned int usb1_ovc_pins[] = { 2448static const unsigned int usb1_ovc_pins[] = {
2382 /* USB_OVC */ 2449 /* USB_OVC */
2383 152, 2450 RCAR_GP_PIN(4, 24),
2384}; 2451};
2385static const unsigned int usb1_ovc_mux[] = { 2452static const unsigned int usb1_ovc_mux[] = {
2386 USB_OVC1_MARK, 2453 USB_OVC1_MARK,
@@ -2388,18 +2455,122 @@ static const unsigned int usb1_ovc_mux[] = {
2388/* - USB2 ------------------------------------------------------------------- */ 2455/* - USB2 ------------------------------------------------------------------- */
2389static const unsigned int usb2_pins[] = { 2456static const unsigned int usb2_pins[] = {
2390 /* PENC */ 2457 /* PENC */
2391 156, 2458 RCAR_GP_PIN(4, 28),
2392}; 2459};
2393static const unsigned int usb2_mux[] = { 2460static const unsigned int usb2_mux[] = {
2394 USB_PENC2_MARK, 2461 USB_PENC2_MARK,
2395}; 2462};
2396static const unsigned int usb2_ovc_pins[] = { 2463static const unsigned int usb2_ovc_pins[] = {
2397 /* USB_OVC */ 2464 /* USB_OVC */
2398 125, 2465 RCAR_GP_PIN(3, 29),
2399}; 2466};
2400static const unsigned int usb2_ovc_mux[] = { 2467static const unsigned int usb2_ovc_mux[] = {
2401 USB_OVC2_MARK, 2468 USB_OVC2_MARK,
2402}; 2469};
2470/* - VIN0 ------------------------------------------------------------------- */
2471static const unsigned int vin0_data8_pins[] = {
2472 /* D[0:7] */
2473 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2474 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2475 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2476};
2477static const unsigned int vin0_data8_mux[] = {
2478 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2479 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2480 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2481};
2482static const unsigned int vin0_clk_pins[] = {
2483 /* CLK */
2484 RCAR_GP_PIN(2, 1),
2485};
2486static const unsigned int vin0_clk_mux[] = {
2487 VI0_CLK_MARK,
2488};
2489static const unsigned int vin0_sync_pins[] = {
2490 /* HSYNC, VSYNC */
2491 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2492};
2493static const unsigned int vin0_sync_mux[] = {
2494 VI0_HSYNC_MARK, VI0_VSYNC_MARK,
2495};
2496/* - VIN1 ------------------------------------------------------------------- */
2497static const unsigned int vin1_data8_pins[] = {
2498 /* D[0:7] */
2499 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2500 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2501 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2502};
2503static const unsigned int vin1_data8_mux[] = {
2504 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2505 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2506 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2507};
2508static const unsigned int vin1_clk_pins[] = {
2509 /* CLK */
2510 RCAR_GP_PIN(2, 30),
2511};
2512static const unsigned int vin1_clk_mux[] = {
2513 VI1_CLK_MARK,
2514};
2515static const unsigned int vin1_sync_pins[] = {
2516 /* HSYNC, VSYNC */
2517 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
2518};
2519static const unsigned int vin1_sync_mux[] = {
2520 VI1_HSYNC_MARK, VI1_VSYNC_MARK,
2521};
2522/* - VIN2 ------------------------------------------------------------------- */
2523static const unsigned int vin2_data8_pins[] = {
2524 /* D[0:7] */
2525 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
2526 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2527 RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
2528};
2529static const unsigned int vin2_data8_mux[] = {
2530 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
2531 VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
2532 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
2533};
2534static const unsigned int vin2_clk_pins[] = {
2535 /* CLK */
2536 RCAR_GP_PIN(1, 30),
2537};
2538static const unsigned int vin2_clk_mux[] = {
2539 VI2_CLK_MARK,
2540};
2541static const unsigned int vin2_sync_pins[] = {
2542 /* HSYNC, VSYNC */
2543 RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2544};
2545static const unsigned int vin2_sync_mux[] = {
2546 VI2_HSYNC_MARK, VI2_VSYNC_MARK,
2547};
2548/* - VIN3 ------------------------------------------------------------------- */
2549static const unsigned int vin3_data8_pins[] = {
2550 /* D[0:7] */
2551 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2552 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2553 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2554};
2555static const unsigned int vin3_data8_mux[] = {
2556 VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
2557 VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
2558 VI3_DATA6_MARK, VI3_DATA7_MARK,
2559};
2560static const unsigned int vin3_clk_pins[] = {
2561 /* CLK */
2562 RCAR_GP_PIN(2, 31),
2563};
2564static const unsigned int vin3_clk_mux[] = {
2565 VI3_CLK_MARK,
2566};
2567static const unsigned int vin3_sync_pins[] = {
2568 /* HSYNC, VSYNC */
2569 RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2570};
2571static const unsigned int vin3_sync_mux[] = {
2572 VI3_HSYNC_MARK, VI3_VSYNC_MARK,
2573};
2403 2574
2404static const struct sh_pfc_pin_group pinmux_groups[] = { 2575static const struct sh_pfc_pin_group pinmux_groups[] = {
2405 SH_PFC_PIN_GROUP(du0_rgb666), 2576 SH_PFC_PIN_GROUP(du0_rgb666),
@@ -2419,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2419 SH_PFC_PIN_GROUP(du1_sync_1), 2590 SH_PFC_PIN_GROUP(du1_sync_1),
2420 SH_PFC_PIN_GROUP(du1_oddf), 2591 SH_PFC_PIN_GROUP(du1_oddf),
2421 SH_PFC_PIN_GROUP(du1_cde), 2592 SH_PFC_PIN_GROUP(du1_cde),
2593 SH_PFC_PIN_GROUP(ether_rmii),
2594 SH_PFC_PIN_GROUP(ether_link),
2595 SH_PFC_PIN_GROUP(ether_magic),
2422 SH_PFC_PIN_GROUP(hspi0), 2596 SH_PFC_PIN_GROUP(hspi0),
2423 SH_PFC_PIN_GROUP(hspi1), 2597 SH_PFC_PIN_GROUP(hspi1),
2424 SH_PFC_PIN_GROUP(hspi1_b), 2598 SH_PFC_PIN_GROUP(hspi1_b),
@@ -2527,6 +2701,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2527 SH_PFC_PIN_GROUP(usb1_ovc), 2701 SH_PFC_PIN_GROUP(usb1_ovc),
2528 SH_PFC_PIN_GROUP(usb2), 2702 SH_PFC_PIN_GROUP(usb2),
2529 SH_PFC_PIN_GROUP(usb2_ovc), 2703 SH_PFC_PIN_GROUP(usb2_ovc),
2704 SH_PFC_PIN_GROUP(vin0_data8),
2705 SH_PFC_PIN_GROUP(vin0_clk),
2706 SH_PFC_PIN_GROUP(vin0_sync),
2707 SH_PFC_PIN_GROUP(vin1_data8),
2708 SH_PFC_PIN_GROUP(vin1_clk),
2709 SH_PFC_PIN_GROUP(vin1_sync),
2710 SH_PFC_PIN_GROUP(vin2_data8),
2711 SH_PFC_PIN_GROUP(vin2_clk),
2712 SH_PFC_PIN_GROUP(vin2_sync),
2713 SH_PFC_PIN_GROUP(vin3_data8),
2714 SH_PFC_PIN_GROUP(vin3_clk),
2715 SH_PFC_PIN_GROUP(vin3_sync),
2530}; 2716};
2531 2717
2532static const char * const du0_groups[] = { 2718static const char * const du0_groups[] = {
@@ -2552,6 +2738,12 @@ static const char * const du1_groups[] = {
2552 "du1_cde", 2738 "du1_cde",
2553}; 2739};
2554 2740
2741static const char * const ether_groups[] = {
2742 "ether_rmii",
2743 "ether_link",
2744 "ether_magic",
2745};
2746
2555static const char * const hspi0_groups[] = { 2747static const char * const hspi0_groups[] = {
2556 "hspi0", 2748 "hspi0",
2557}; 2749};
@@ -2720,9 +2912,34 @@ static const char * const usb2_groups[] = {
2720 "usb2_ovc", 2912 "usb2_ovc",
2721}; 2913};
2722 2914
2915static const char * const vin0_groups[] = {
2916 "vin0_data8",
2917 "vin0_clk",
2918 "vin0_sync",
2919};
2920
2921static const char * const vin1_groups[] = {
2922 "vin1_data8",
2923 "vin1_clk",
2924 "vin1_sync",
2925};
2926
2927static const char * const vin2_groups[] = {
2928 "vin2_data8",
2929 "vin2_clk",
2930 "vin2_sync",
2931};
2932
2933static const char * const vin3_groups[] = {
2934 "vin3_data8",
2935 "vin3_clk",
2936 "vin3_sync",
2937};
2938
2723static const struct sh_pfc_function pinmux_functions[] = { 2939static const struct sh_pfc_function pinmux_functions[] = {
2724 SH_PFC_FUNCTION(du0), 2940 SH_PFC_FUNCTION(du0),
2725 SH_PFC_FUNCTION(du1), 2941 SH_PFC_FUNCTION(du1),
2942 SH_PFC_FUNCTION(ether),
2726 SH_PFC_FUNCTION(hspi0), 2943 SH_PFC_FUNCTION(hspi0),
2727 SH_PFC_FUNCTION(hspi1), 2944 SH_PFC_FUNCTION(hspi1),
2728 SH_PFC_FUNCTION(hspi2), 2945 SH_PFC_FUNCTION(hspi2),
@@ -2743,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
2743 SH_PFC_FUNCTION(usb0), 2960 SH_PFC_FUNCTION(usb0),
2744 SH_PFC_FUNCTION(usb1), 2961 SH_PFC_FUNCTION(usb1),
2745 SH_PFC_FUNCTION(usb2), 2962 SH_PFC_FUNCTION(usb2),
2963 SH_PFC_FUNCTION(vin0),
2964 SH_PFC_FUNCTION(vin1),
2965 SH_PFC_FUNCTION(vin2),
2966 SH_PFC_FUNCTION(vin3),
2746}; 2967};
2747 2968
2748static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2969static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3547,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3547 /* SEL_SCIF [2] */ 3768 /* SEL_SCIF [2] */
3548 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, 3769 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3549 /* SEL_CANCLK [2] */ 3770 /* SEL_CANCLK [2] */
3550 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 3771 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
3551 /* SEL_CAN0 [1] */ 3772 /* SEL_CAN0 [1] */
3552 FN_SEL_CAN0_0, FN_SEL_CAN0_1, 3773 FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3553 /* SEL_HSCIF1 [1] */ 3774 /* SEL_HSCIF1 [1] */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
new file mode 100644
index 000000000000..85d77a417c0e
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -0,0 +1,3835 @@
1/*
2 * R8A7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#include <linux/kernel.h>
25#include <linux/platform_data/gpio-rcar.h>
26
27#include "core.h"
28#include "sh_pfc.h"
29
30#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
31
32#define PORT_GP_32(bank, fn, sfx) \
33 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
34 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
35 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
36 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
37 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
38 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
39 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
40 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
41 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
42 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
43 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
44 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
45 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
46 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
47 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
48 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
49
50#define PORT_GP_32_REV(bank, fn, sfx) \
51 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
52 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
53 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
54 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
55 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
56 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
57 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
58 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
59 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
60 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
61 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
62 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
63 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
64 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
65 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
66 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
67
68#define CPU_ALL_PORT(fn, sfx) \
69 PORT_GP_32(0, fn, sfx), \
70 PORT_GP_32(1, fn, sfx), \
71 PORT_GP_32(2, fn, sfx), \
72 PORT_GP_32(3, fn, sfx), \
73 PORT_GP_32(4, fn, sfx), \
74 PORT_GP_32(5, fn, sfx)
75
76#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
77
78#define _GP_GPIO(bank, pin, _name, sfx) \
79 [(bank * 32) + pin] = { \
80 .name = __stringify(_name), \
81 .enum_id = _name##_DATA, \
82 }
83
84#define _GP_DATA(bank, pin, name, sfx) \
85 PINMUX_DATA(name##_DATA, name##_FN)
86
87#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
88#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
89#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
90
91#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
92#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
93 FN_##ipsr, FN_##fn)
94
95enum {
96 PINMUX_RESERVED = 0,
97
98 PINMUX_DATA_BEGIN,
99 GP_ALL(DATA),
100 PINMUX_DATA_END,
101
102 PINMUX_FUNCTION_BEGIN,
103 GP_ALL(FN),
104
105 /* GPSR0 */
106 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
107 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
108 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
109 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
110 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
111 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
112 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
113 FN_IP3_14_12, FN_IP3_17_15,
114
115 /* GPSR1 */
116 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
117 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
118 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
119 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
120 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
121 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
122 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
123
124 /* GPSR2 */
125 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
126 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
127 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
128 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
129 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
130 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
131 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
132
133 /* GPSR3 */
134 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
135 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
136 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
137 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
138 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
139 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
140 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
141
142 /* GPSR4 */
143 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
144 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
145 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
146 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
147 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
148 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
149 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
150 FN_IP14_15_12, FN_IP14_18_16,
151
152 /* GPSR5 */
153 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
154 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
155 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
156 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
157 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
158 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
159 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
160
161 /* IPSR0 */
162 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
163 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
164 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
165 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
166 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
167 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
168 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
169 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
170 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
171 FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
172 FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
173 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
174 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
175 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
176
177 /* IPSR1 */
178 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
179 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
180 FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
181 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
182 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
183 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
184 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
185 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
186 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
187 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
188 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
189 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
190 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
191 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
192 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
193
194 /* IPSR2 */
195 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
196 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
197 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
198 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
199 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
200 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
201 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
202 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
203 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
204 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
205 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
206
207 /* IPSR3 */
208 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
209 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
210 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
211 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
212 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
213 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
214 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
215 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
216 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
217 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
218 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
219 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
220 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
221
222 /* IPSR4 */
223 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
224 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
225 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
226 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
227 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
228 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
229 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
230 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
231 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
232 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
233 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
234 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
235 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
236 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
237 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
238
239 /* IPSR5 */
240 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
241 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
242 FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
243 FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
244 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
245 FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
246 FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
247 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
248 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
249 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
250 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
251 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
252 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
253 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
254 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
255 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
256 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
257 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
258 FN_SSI_WS78_B,
259
260 /* IPSR6 */
261 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
262 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
263 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
264 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
265 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
266 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
267 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
268 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
269 FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
270 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
271 FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
272 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
273 FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
274 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
275 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
276 FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
277 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
278 FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
279 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
280 FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
281 FN_STP_IVCXO27_1_B, FN_HRX0_F,
282
283 /* IPSR7 */
284 FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
285 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
286 FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
287 FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
288 FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
289 FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
290 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
291 FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
292 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
293 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
294 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
295 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
296 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
297 FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
298 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
299 FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
300 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
301 FN_MII_RXD2,
302
303 /* IPSR8 */
304 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
305 FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
306 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
307 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
308 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
309 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
310 FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
311 FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
312 FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
313 FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
314 FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
315 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
316 FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
317 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
318 FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
319 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
320 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
321 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
322
323 /* IPSR9 */
324 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
325 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
326 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
327 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
328 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
329 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
330 FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
331 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
332 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
333 FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
334 FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
335 FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
336 FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
337 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
338 FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
339 FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
340 FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
341 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
342 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
343 FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
344 FN_VI3_CLK_B,
345
346 /* IPSR10 */
347 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
348 FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
349 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
350 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
351 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
352 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
353 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
354 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
355 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
356 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
357 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
358 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
359 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
360 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
361 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
362 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
363 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
364 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
365 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
366 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
367 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
368 FN_GLO_I0_B, FN_VI3_DATA6_B,
369
370 /* IPSR11 */
371 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
372 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
373 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
374 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
375 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
376 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
377 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
378 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
379 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
380 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
381 FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
382 FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
383 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
384 FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
385 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
386 FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
387 FN_MOUT0,
388
389 /* IPSR12 */
390 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
391 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
392 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
393 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
394 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
395 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
396 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
397 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
398 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
399 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
400 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
401 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
402 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
403 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
404 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
405 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
406 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
407 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
408 FN_CAN_DEBUGOUT4,
409
410 /* IPSR13 */
411 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
412 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
413 FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
414 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
415 FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
416 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
417 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
418 FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
419 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
420 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
421 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
422 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
423 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
424 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
425 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
426 FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
427 FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
428 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
429 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
430 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
431 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
432 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
433
434 /* IPSR14 */
435 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
436 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
437 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
438 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
439 FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
440 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
441 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
442 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
443 FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
444 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
445 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
446 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
447 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
448 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
449 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
450 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
451 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
452 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
453 FN_HRTS0_N_C,
454
455 /* IPSR15 */
456 FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
457 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
458 FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
459 FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
460 FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
461 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
462 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
463 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
464 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
465 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
466 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
467 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
468 FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
469 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
470 FN_DU2_DG6, FN_LCDOUT14,
471
472 /* IPSR16 */
473 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
474 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
475 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
476 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
477 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
478 FN_TCLK1_B,
479
480 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
481 FN_SEL_SCIF1_4,
482 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
483 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
484 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
485 FN_SEL_SCIFB1_4,
486 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
487 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
488 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
489 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
490 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
491 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
492 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
493 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
494 FN_SEL_VI3_0, FN_SEL_VI3_1,
495 FN_SEL_VI2_0, FN_SEL_VI2_1,
496 FN_SEL_VI1_0, FN_SEL_VI1_1,
497 FN_SEL_VI0_0, FN_SEL_VI0_1,
498 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
499 FN_SEL_LBS_0, FN_SEL_LBS_1,
500 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
501 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
502 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
503
504 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
505 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
506 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
507 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
508 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
509 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
510 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
511 FN_SEL_ADI_0, FN_SEL_ADI_1,
512 FN_SEL_SSP_0, FN_SEL_SSP_1,
513 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
514 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
515 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
516 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
517 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
518 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
519 FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
520 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
521 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
522
523 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
524 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
525 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
526 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
527 FN_SEL_IIC2_4,
528 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
529 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
530 FN_SEL_I2C2_4,
531 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
532 PINMUX_FUNCTION_END,
533
534 PINMUX_MARK_BEGIN,
535
536 VI1_DATA7_VI1_B7_MARK,
537
538 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
539 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
540 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
541
542 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
543 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
544 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
545 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
546 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
547 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
548 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
549 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
550 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
551 SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
552 SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
553 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
554 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
555 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
556
557 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
558 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
559 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
560 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
561 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
562 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
563 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
564 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
565 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
566 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
567 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
568 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
569 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
570 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
571 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
572
573 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
574 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
575 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
576 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
577 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
578 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
579 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
580 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
581 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
582 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
583 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
584
585 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
586 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
587 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
588 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
589 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
590 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
591 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
592 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
593 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
594 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
595 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
596 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
597 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
598
599 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
600 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
601 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
602 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
603 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
604 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
605 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
606 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
607 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
608 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
609 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
610 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
611 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
612 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
613 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
614
615 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
616 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
617 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
618 VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
619 INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
620 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
621 VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
622 SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
623 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
624 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
625 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
626 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
627 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
628 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
629 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
630 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
631 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
632 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
633 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
634 SSI_WS78_B_MARK,
635
636 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
637 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
638 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
639 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
640 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
641 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
642 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
643 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
644 ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
645 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
646 SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
647 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
648 SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
649 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
650 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
651 RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
652 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
653 RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
654 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
655 ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
656 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
657
658 ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
659 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
660 RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
661 ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
662 HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
663 SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
664 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
665 ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
666 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
667 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
668 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
669 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
670 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
671 PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
672 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
673 ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
674 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
675 MII_RXD2_MARK,
676
677 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
678 MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
679 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
680 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
681 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
682 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
683 MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
684 MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
685 MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
686 AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
687 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
688 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
689 MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
690 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
691 AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
692 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
693 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
694 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
695
696 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
697 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
698 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
699 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
700 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
701 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
702 SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
703 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
704 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
705 SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
706 AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
707 AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
708 SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
709 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
710 MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
711 AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
712 SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
713 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
714 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
715 SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
716 VI3_CLK_B_MARK,
717
718 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
719 GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
720 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
721 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
722 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
723 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
724 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
725 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
726 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
727 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
728 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
729 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
730 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
731 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
732 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
733 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
734 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
735 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
736 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
737 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
738 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
739 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
740
741 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
742 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
743 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
744 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
745 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
746 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
747 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
748 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
749 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
750 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
751 RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
752 RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
753 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
754 SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
755 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
756 RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
757 MOUT0_MARK,
758
759 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
760 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
761 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
762 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
763 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
764 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
765 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
766 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
767 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
768 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
769 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
770 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
771 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
772 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
773 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
774 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
775 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
776 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
777 CAN_DEBUGOUT4_MARK,
778
779 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
780 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
781 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
782 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
783 BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
784 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
785 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
786 FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
787 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
788 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
789 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
790 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
791 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
792 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
793 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
794 BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
795 FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
796 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
797 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
798 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
799 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
800 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
801
802 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
803 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
804 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
805 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
806 SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
807 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
808 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
809 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
810 LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
811 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
812 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
813 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
814 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
815 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
816 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
817 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
818 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
819 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
820 HRTS0_N_C_MARK,
821
822 SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
823 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
824 DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
825 SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
826 SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
827 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
828 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
829 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
830 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
831 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
832 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
833 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
834 SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
835 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
836 DU2_DG6_MARK, LCDOUT14_MARK,
837
838 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
839 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
840 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
841 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
842 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
843 TCLK1_B_MARK,
844 PINMUX_MARK_END,
845};
846
847static const pinmux_enum_t pinmux_data[] = {
848 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
849
850 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
851 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
852 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
853 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
854 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
855 PINMUX_DATA(AVS1_MARK, FN_AVS1),
856 PINMUX_DATA(AVS2_MARK, FN_AVS2),
857 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
858 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
859
860 PINMUX_IPSR_DATA(IP0_2_0, D0),
861 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
862 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
863 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
864 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
865 PINMUX_IPSR_DATA(IP0_5_3, D1),
866 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
867 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
868 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
869 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
870 PINMUX_IPSR_DATA(IP0_8_6, D2),
871 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
872 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
873 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
874 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
875 PINMUX_IPSR_DATA(IP0_11_9, D3),
876 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
877 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
878 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
880 PINMUX_IPSR_DATA(IP0_15_12, D4),
881 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
882 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
883 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
884 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
885 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
886 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
887 PINMUX_IPSR_DATA(IP0_19_16, D5),
888 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
889 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
890 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
891 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
892 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
893 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
894 PINMUX_IPSR_DATA(IP0_22_20, D6),
895 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
896 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
897 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
898 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
899 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
900 PINMUX_IPSR_DATA(IP0_26_23, D7),
901 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
902 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
903 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
904 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
905 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
906 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
907 PINMUX_IPSR_DATA(IP0_30_27, D8),
908 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
909 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
910 PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
911 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
912 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
913 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
914
915 PINMUX_IPSR_DATA(IP1_3_0, D9),
916 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
917 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
918 PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
919 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
920 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
921 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
922 PINMUX_IPSR_DATA(IP1_7_4, D10),
923 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
924 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
925 PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
926 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
927 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
928 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
929 PINMUX_IPSR_DATA(IP1_11_8, D11),
930 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
931 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
932 PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
933 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
934 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
935 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
936 PINMUX_IPSR_DATA(IP1_14_12, D12),
937 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
938 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
939 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
940 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
941 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
942 PINMUX_IPSR_DATA(IP1_17_15, D13),
943 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
944 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
945 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
946 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
947 PINMUX_IPSR_DATA(IP1_21_18, D14),
948 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
949 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
950 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
951 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
952 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
953 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
954 PINMUX_IPSR_DATA(IP1_25_22, D15),
955 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
956 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
957 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
958 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
959 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
960 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
961 PINMUX_IPSR_DATA(IP1_27_26, A0),
962 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
963 PINMUX_IPSR_DATA(IP1_29_28, A1),
964 PINMUX_IPSR_DATA(IP1_29_28, PWM4),
965
966 PINMUX_IPSR_DATA(IP2_2_0, A2),
967 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
968 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
969 PINMUX_IPSR_DATA(IP2_5_3, A3),
970 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
971 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
972 PINMUX_IPSR_DATA(IP2_8_6, A4),
973 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
974 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
975 PINMUX_IPSR_DATA(IP2_11_9, A5),
976 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
977 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
978 PINMUX_IPSR_DATA(IP2_14_12, A6),
979 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
980 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
981 PINMUX_IPSR_DATA(IP2_17_15, A7),
982 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
983 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
984 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
985 PINMUX_IPSR_DATA(IP2_21_18, A8),
986 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
987 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
988 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
989 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
990 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
991 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
992 PINMUX_IPSR_DATA(IP2_25_22, A9),
993 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
994 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
995 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
996 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
997 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
998 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
999 PINMUX_IPSR_DATA(IP2_28_26, A10),
1000 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
1001 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
1002 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
1003 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
1004 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
1005
1006 PINMUX_IPSR_DATA(IP3_3_0, A11),
1007 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1008 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
1009 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
1010 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
1011 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
1012 PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
1013 PINMUX_IPSR_DATA(IP3_7_4, A12),
1014 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
1015 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
1016 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
1017 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
1018 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
1019 PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
1020 PINMUX_IPSR_DATA(IP3_11_8, A13),
1021 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1022 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
1023 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
1024 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
1025 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
1026 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
1027 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
1028 PINMUX_IPSR_DATA(IP3_14_12, A14),
1029 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
1030 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
1031 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
1032 PINMUX_IPSR_DATA(IP3_17_15, A15),
1033 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
1034 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
1035 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
1036 PINMUX_IPSR_DATA(IP3_19_18, A16),
1037 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
1038 PINMUX_IPSR_DATA(IP3_22_20, A17),
1039 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
1040 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
1041 PINMUX_IPSR_DATA(IP3_25_23, A18),
1042 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
1043 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
1044 PINMUX_IPSR_DATA(IP3_28_26, A19),
1045 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
1046 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
1047 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
1048 PINMUX_IPSR_DATA(IP3_31_29, A20),
1049 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
1050 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
1051 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
1052 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
1053
1054 PINMUX_IPSR_DATA(IP4_2_0, A21),
1055 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
1056 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
1057 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1058 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1059 PINMUX_IPSR_DATA(IP4_5_3, A22),
1060 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1061 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1063 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1064 PINMUX_IPSR_DATA(IP4_8_6, A23),
1065 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1066 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1067 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1068 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1069 PINMUX_IPSR_DATA(IP4_11_9, A24),
1070 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1071 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1072 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1073 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1074 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1075 PINMUX_IPSR_DATA(IP4_14_12, A25),
1076 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1077 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1078 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1079 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1081 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1082 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1083 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1084 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1085 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1086 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1087 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1088 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1089 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1090 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1091 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1092 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1093 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1094 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1095 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1096 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1097 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1098 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1099 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1100 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1101 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1102 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1103 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1104 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1105 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1106 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1107 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1108 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1109 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1110 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1111 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1112
1113 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1114 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1115 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1117 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1118 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
1120 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1121 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1122 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1123 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
1124 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1125 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1126 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
1127 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1128 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1129 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1130 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1131 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1132 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1133 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1134 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
1135 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1136 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
1137 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1138 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1139 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1141 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1142 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1143 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1144 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1145 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1146 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1147 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1148 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1149 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1150 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1151 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1152 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1153 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1154 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1155 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1156 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1157 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1158 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1159 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1160 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1161 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1162 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1163 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1164 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1165 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1166 PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
1167 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1168 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1169 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1170 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1171 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1172 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1173 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1174 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1175 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1176 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1177 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1178 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1179
1180 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1181 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1182 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1183 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1184 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1185 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1186 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1187 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1188 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1189 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1190 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1191 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1192 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1193 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1194 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1195 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1196 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1197 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1198 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1200 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1201 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1202 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1203 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1204 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1205 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1207 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1208 PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
1209 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1211 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1212 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
1213 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
1214 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1215 PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
1216 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1218 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1219 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
1220 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
1221 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1222 PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
1223 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1225 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1226 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1227 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1228 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1229 PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
1230 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1231 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1232 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1233 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1234 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1235 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1236 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1237 PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
1238 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1239 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1240 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1241 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1242 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1243 PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
1244 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1245 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1246 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1247
1248 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1249 PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
1250 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1251 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1252 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1253 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1254 PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
1255 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
1256 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
1257 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
1258 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1259 PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
1260 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1261 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1262 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1263 PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
1264 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1265 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1266 PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
1267 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1268 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1269 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1270 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1271 PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
1272 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1273 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1274 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1275 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1276 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1277 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1278 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1279 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1280 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1281 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1282 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1283 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1284 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1285 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1286 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1287 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1288 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1289 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1290 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1291 PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
1292 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1293 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1294 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1295 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1296 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1297 PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
1298 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1299 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1300 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1301 PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
1302
1303 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1304 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1305 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1306 PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
1307 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1308 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1309 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1310 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1311 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1312 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1313 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1314 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1315 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1316 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1317 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1318 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1319 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1320 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1321 PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
1322 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1323 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1324 PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
1325 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1326 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1327 PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
1328 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1329 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1330 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1331 PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
1332 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1333 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1334 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1335 PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
1336 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1337 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1338 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1339 PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
1340 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1341 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1342 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1343 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1344 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1345 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1346 PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
1347 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1348 PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
1349 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1350 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1351 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1352 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1353 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1354 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1355 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1356
1357 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1358 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1359 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1360 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1361 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1362 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1363 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1364 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1365 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1366 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1367 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1368 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1369 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1370 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1371 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1372 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1373 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1374 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
1376 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
1377 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1378 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1379 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1380 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1381 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1382 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1383 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
1385 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
1386 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1387 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1388 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1389 PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
1390 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1391 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1392 PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
1393 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1394 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1395 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1396 PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
1397 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1398 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1399 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1400 PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
1401 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1402 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1403 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1404 PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
1405 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1406 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1407 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1408 PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
1409 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1410 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1411 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1412 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1413 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1414 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1415 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1416 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
1417 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
1418 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1419 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1420
1421 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1422 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1423 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1424 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1425 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1426 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1427 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
1428 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
1429 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1430 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1431 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1432 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1433 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1434 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1435 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1436 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1437 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1438 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1439 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1440 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1441 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1442 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1443 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1444 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1445 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1446 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1447 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1448 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1449 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1450 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1451 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1452 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1453 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1454 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1455 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1456 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1457 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1458 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
1459 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1460 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1461 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1462 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1463 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1464 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1465 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1466 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1467 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1468 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
1469 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1470 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1471 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1472 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1473 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1474 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1475 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1476 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1477 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1478 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1479 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1480 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1481 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1482 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1483 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1484 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1485 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1486 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1487 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1488 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1489 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1490 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1491 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1492
1493 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1494 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1495 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1496 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1497 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1498 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1499 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1500 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1501 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1502 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1503 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1504 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1505 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1506 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1507 PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1508 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1509 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1510 PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1511 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1512 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1513 PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1514 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1515 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1516 PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1517 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1518 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1519 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1520 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1521 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1522 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1523 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1524 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1525 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1526 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1527 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1528 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1529 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1530 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1531 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
1532 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1533 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
1534 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1535 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
1536 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1537 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
1538 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
1539 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1540 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1541 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1542 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
1543 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
1544 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1545 PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
1546 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1547 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1548 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1549 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
1550 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1551 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1552 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1553
1554 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1555 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1556 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1557 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1558 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1559 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1560 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1561 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1562 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1563 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1564 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1565 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
1566 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1567 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1568 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1569 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1570 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1571 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1572 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1573 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1575 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1576 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1577 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1578 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1579 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1580 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1581 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1582 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1583 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1584 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1585 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1586 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1587 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1588 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1589 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1590 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1591 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1592 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1593 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1594 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1595 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1596 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1597 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1598 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1599 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1600 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1601 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1602 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1603 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1604 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1605 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1607 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1608 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1609 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1610
1611 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1612 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1613 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1614 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1615 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1616 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1617 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1618 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1619 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1620 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
1621 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1622 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1623 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1624 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1625 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
1626 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1629 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1630 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1631 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1632 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1633 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1634 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
1635 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1636 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1637 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1638 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1639 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1640 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1641 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1642 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1643 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1644 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1645 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1647 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1648 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1649 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1650 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1651 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1652 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1653 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1654 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1655 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1656 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1657 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1658 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1659 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1660 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
1661 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1662 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1663 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
1664 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1665 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1666 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1667 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1668 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1669 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1670 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1671 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1672 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1673 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1674 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1675 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1676 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1677 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1678 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1679
1680 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1681 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1682 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1683 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1684 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1685 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1686 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1687 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1688 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1689 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1690 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1691 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1692 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1693 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
1694 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
1695 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1696 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1697 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1698 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1699 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1700 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1701 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1702 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1703 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1704 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1705 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1706 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1707 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
1708 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1709 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1710 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
1711 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
1712 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
1713 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
1714 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1715 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1716 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
1717 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1718 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1719 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1720 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1721 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1722 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1723 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1724 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1725 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1726 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1727 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1728 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1729 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1730 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1731 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1732 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1733 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1734 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1735 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1736 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1737 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1738 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1739 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
1740 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1741 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1742 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1743 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1744
1745 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1746 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1747 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1748 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1749 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1750 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
1751 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1752 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1753 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1754 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1755 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
1756 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
1757 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1758 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1759 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1760 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1761 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
1762 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
1763 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1764 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1765 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1766 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1767 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
1768 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
1769 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1770 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1771 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1772 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1773 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1774 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1775 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1776 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1777 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1778 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1779 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1780 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1781 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1782 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1783 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1784 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1785 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1786 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1787 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1788 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1789 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1790 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1791 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1792 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1793 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1794 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
1795 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1796 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1797 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1798 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1799 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1800 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1801 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1802 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1803
1804 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1805 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1806 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1807 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1808 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1809 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1810 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1811 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1812 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1813 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1814 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1815 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1816 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1817 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
1818 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1819 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1820 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1821 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1822};
1823
1824static struct sh_pfc_pin pinmux_pins[] = {
1825 PINMUX_GPIO_GP_ALL(),
1826};
1827
1828/* - ETH -------------------------------------------------------------------- */
1829static const unsigned int eth_link_pins[] = {
1830 /* LINK */
1831 RCAR_GP_PIN(2, 22),
1832};
1833static const unsigned int eth_link_mux[] = {
1834 ETH_LINK_MARK,
1835};
1836static const unsigned int eth_magic_pins[] = {
1837 /* MAGIC */
1838 RCAR_GP_PIN(2, 27),
1839};
1840static const unsigned int eth_magic_mux[] = {
1841 ETH_MAGIC_MARK,
1842};
1843static const unsigned int eth_mdio_pins[] = {
1844 /* MDC, MDIO */
1845 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1846};
1847static const unsigned int eth_mdio_mux[] = {
1848 ETH_MDC_MARK, ETH_MDIO_MARK,
1849};
1850static const unsigned int eth_rmii_pins[] = {
1851 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1852 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1853 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1854 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1855};
1856static const unsigned int eth_rmii_mux[] = {
1857 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1858 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1859};
1860/* - INTC ------------------------------------------------------------------- */
1861static const unsigned int intc_irq0_pins[] = {
1862 /* IRQ */
1863 RCAR_GP_PIN(1, 25),
1864};
1865static const unsigned int intc_irq0_mux[] = {
1866 IRQ0_MARK,
1867};
1868static const unsigned int intc_irq1_pins[] = {
1869 /* IRQ */
1870 RCAR_GP_PIN(1, 27),
1871};
1872static const unsigned int intc_irq1_mux[] = {
1873 IRQ1_MARK,
1874};
1875static const unsigned int intc_irq2_pins[] = {
1876 /* IRQ */
1877 RCAR_GP_PIN(1, 29),
1878};
1879static const unsigned int intc_irq2_mux[] = {
1880 IRQ2_MARK,
1881};
1882static const unsigned int intc_irq3_pins[] = {
1883 /* IRQ */
1884 RCAR_GP_PIN(1, 23),
1885};
1886static const unsigned int intc_irq3_mux[] = {
1887 IRQ3_MARK,
1888};
1889/* - SCIF0 ----------------------------------------------------------------- */
1890static const unsigned int scif0_data_pins[] = {
1891 /* RX, TX */
1892 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1893};
1894static const unsigned int scif0_data_mux[] = {
1895 RX0_MARK, TX0_MARK,
1896};
1897static const unsigned int scif0_clk_pins[] = {
1898 /* SCK */
1899 RCAR_GP_PIN(4, 27),
1900};
1901static const unsigned int scif0_clk_mux[] = {
1902 SCK0_MARK,
1903};
1904static const unsigned int scif0_ctrl_pins[] = {
1905 /* RTS, CTS */
1906 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
1907};
1908static const unsigned int scif0_ctrl_mux[] = {
1909 RTS0_N_TANS_MARK, CTS0_N_MARK,
1910};
1911static const unsigned int scif0_data_b_pins[] = {
1912 /* RX, TX */
1913 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1914};
1915static const unsigned int scif0_data_b_mux[] = {
1916 RX0_B_MARK, TX0_B_MARK,
1917};
1918/* - SCIF1 ----------------------------------------------------------------- */
1919static const unsigned int scif1_data_pins[] = {
1920 /* RX, TX */
1921 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1922};
1923static const unsigned int scif1_data_mux[] = {
1924 RX1_MARK, TX1_MARK,
1925};
1926static const unsigned int scif1_clk_pins[] = {
1927 /* SCK */
1928 RCAR_GP_PIN(4, 20),
1929};
1930static const unsigned int scif1_clk_mux[] = {
1931 SCK1_MARK,
1932};
1933static const unsigned int scif1_ctrl_pins[] = {
1934 /* RTS, CTS */
1935 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
1936};
1937static const unsigned int scif1_ctrl_mux[] = {
1938 RTS1_N_TANS_MARK, CTS1_N_MARK,
1939};
1940static const unsigned int scif1_data_b_pins[] = {
1941 /* RX, TX */
1942 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1943};
1944static const unsigned int scif1_data_b_mux[] = {
1945 RX1_B_MARK, TX1_B_MARK,
1946};
1947static const unsigned int scif1_data_c_pins[] = {
1948 /* RX, TX */
1949 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
1950};
1951static const unsigned int scif1_data_c_mux[] = {
1952 RX1_C_MARK, TX1_C_MARK,
1953};
1954static const unsigned int scif1_data_d_pins[] = {
1955 /* RX, TX */
1956 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1957};
1958static const unsigned int scif1_data_d_mux[] = {
1959 RX1_D_MARK, TX1_D_MARK,
1960};
1961static const unsigned int scif1_clk_d_pins[] = {
1962 /* SCK */
1963 RCAR_GP_PIN(3, 17),
1964};
1965static const unsigned int scif1_clk_d_mux[] = {
1966 SCK1_D_MARK,
1967};
1968static const unsigned int scif1_data_e_pins[] = {
1969 /* RX, TX */
1970 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1971};
1972static const unsigned int scif1_data_e_mux[] = {
1973 RX1_E_MARK, TX1_E_MARK,
1974};
1975static const unsigned int scif1_clk_e_pins[] = {
1976 /* SCK */
1977 RCAR_GP_PIN(2, 20),
1978};
1979static const unsigned int scif1_clk_e_mux[] = {
1980 SCK1_E_MARK,
1981};
1982/* - SCIFA0 ----------------------------------------------------------------- */
1983static const unsigned int scifa0_data_pins[] = {
1984 /* RXD, TXD */
1985 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1986};
1987static const unsigned int scifa0_data_mux[] = {
1988 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1989};
1990static const unsigned int scifa0_clk_pins[] = {
1991 /* SCK */
1992 RCAR_GP_PIN(4, 27),
1993};
1994static const unsigned int scifa0_clk_mux[] = {
1995 SCIFA0_SCK_MARK,
1996};
1997static const unsigned int scifa0_ctrl_pins[] = {
1998 /* RTS, CTS */
1999 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2000};
2001static const unsigned int scifa0_ctrl_mux[] = {
2002 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2003};
2004static const unsigned int scifa0_data_b_pins[] = {
2005 /* RXD, TXD */
2006 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2007};
2008static const unsigned int scifa0_data_b_mux[] = {
2009 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2010};
2011static const unsigned int scifa0_clk_b_pins[] = {
2012 /* SCK */
2013 RCAR_GP_PIN(1, 19),
2014};
2015static const unsigned int scifa0_clk_b_mux[] = {
2016 SCIFA0_SCK_B_MARK,
2017};
2018static const unsigned int scifa0_ctrl_b_pins[] = {
2019 /* RTS, CTS */
2020 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2021};
2022static const unsigned int scifa0_ctrl_b_mux[] = {
2023 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2024};
2025/* - SCIFA1 ----------------------------------------------------------------- */
2026static const unsigned int scifa1_data_pins[] = {
2027 /* RXD, TXD */
2028 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2029};
2030static const unsigned int scifa1_data_mux[] = {
2031 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2032};
2033static const unsigned int scifa1_clk_pins[] = {
2034 /* SCK */
2035 RCAR_GP_PIN(4, 20),
2036};
2037static const unsigned int scifa1_clk_mux[] = {
2038 SCIFA1_SCK_MARK,
2039};
2040static const unsigned int scifa1_ctrl_pins[] = {
2041 /* RTS, CTS */
2042 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2043};
2044static const unsigned int scifa1_ctrl_mux[] = {
2045 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2046};
2047static const unsigned int scifa1_data_b_pins[] = {
2048 /* RXD, TXD */
2049 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2050};
2051static const unsigned int scifa1_data_b_mux[] = {
2052 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2053};
2054static const unsigned int scifa1_clk_b_pins[] = {
2055 /* SCK */
2056 RCAR_GP_PIN(0, 23),
2057};
2058static const unsigned int scifa1_clk_b_mux[] = {
2059 SCIFA1_SCK_B_MARK,
2060};
2061static const unsigned int scifa1_ctrl_b_pins[] = {
2062 /* RTS, CTS */
2063 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2064};
2065static const unsigned int scifa1_ctrl_b_mux[] = {
2066 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2067};
2068static const unsigned int scifa1_data_c_pins[] = {
2069 /* RXD, TXD */
2070 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2071};
2072static const unsigned int scifa1_data_c_mux[] = {
2073 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2074};
2075static const unsigned int scifa1_clk_c_pins[] = {
2076 /* SCK */
2077 RCAR_GP_PIN(0, 8),
2078};
2079static const unsigned int scifa1_clk_c_mux[] = {
2080 SCIFA1_SCK_C_MARK,
2081};
2082static const unsigned int scifa1_ctrl_c_pins[] = {
2083 /* RTS, CTS */
2084 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2085};
2086static const unsigned int scifa1_ctrl_c_mux[] = {
2087 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2088};
2089static const unsigned int scifa1_data_d_pins[] = {
2090 /* RXD, TXD */
2091 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2092};
2093static const unsigned int scifa1_data_d_mux[] = {
2094 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2095};
2096static const unsigned int scifa1_clk_d_pins[] = {
2097 /* SCK */
2098 RCAR_GP_PIN(2, 10),
2099};
2100static const unsigned int scifa1_clk_d_mux[] = {
2101 SCIFA1_SCK_D_MARK,
2102};
2103static const unsigned int scifa1_ctrl_d_pins[] = {
2104 /* RTS, CTS */
2105 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2106};
2107static const unsigned int scifa1_ctrl_d_mux[] = {
2108 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2109};
2110/* - SCIFA2 ----------------------------------------------------------------- */
2111static const unsigned int scifa2_data_pins[] = {
2112 /* RXD, TXD */
2113 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2114};
2115static const unsigned int scifa2_data_mux[] = {
2116 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2117};
2118static const unsigned int scifa2_clk_pins[] = {
2119 /* SCK */
2120 RCAR_GP_PIN(5, 4),
2121};
2122static const unsigned int scifa2_clk_mux[] = {
2123 SCIFA2_SCK_MARK,
2124};
2125static const unsigned int scifa2_ctrl_pins[] = {
2126 /* RTS, CTS */
2127 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2128};
2129static const unsigned int scifa2_ctrl_mux[] = {
2130 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2131};
2132static const unsigned int scifa2_data_b_pins[] = {
2133 /* RXD, TXD */
2134 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2135};
2136static const unsigned int scifa2_data_b_mux[] = {
2137 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2138};
2139static const unsigned int scifa2_data_c_pins[] = {
2140 /* RXD, TXD */
2141 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2142};
2143static const unsigned int scifa2_data_c_mux[] = {
2144 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2145};
2146static const unsigned int scifa2_clk_c_pins[] = {
2147 /* SCK */
2148 RCAR_GP_PIN(5, 29),
2149};
2150static const unsigned int scifa2_clk_c_mux[] = {
2151 SCIFA2_SCK_C_MARK,
2152};
2153/* - SCIFB0 ----------------------------------------------------------------- */
2154static const unsigned int scifb0_data_pins[] = {
2155 /* RXD, TXD */
2156 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2157};
2158static const unsigned int scifb0_data_mux[] = {
2159 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2160};
2161static const unsigned int scifb0_clk_pins[] = {
2162 /* SCK */
2163 RCAR_GP_PIN(4, 8),
2164};
2165static const unsigned int scifb0_clk_mux[] = {
2166 SCIFB0_SCK_MARK,
2167};
2168static const unsigned int scifb0_ctrl_pins[] = {
2169 /* RTS, CTS */
2170 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2171};
2172static const unsigned int scifb0_ctrl_mux[] = {
2173 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2174};
2175static const unsigned int scifb0_data_b_pins[] = {
2176 /* RXD, TXD */
2177 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2178};
2179static const unsigned int scifb0_data_b_mux[] = {
2180 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2181};
2182static const unsigned int scifb0_clk_b_pins[] = {
2183 /* SCK */
2184 RCAR_GP_PIN(3, 9),
2185};
2186static const unsigned int scifb0_clk_b_mux[] = {
2187 SCIFB0_SCK_B_MARK,
2188};
2189static const unsigned int scifb0_ctrl_b_pins[] = {
2190 /* RTS, CTS */
2191 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2192};
2193static const unsigned int scifb0_ctrl_b_mux[] = {
2194 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2195};
2196static const unsigned int scifb0_data_c_pins[] = {
2197 /* RXD, TXD */
2198 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2199};
2200static const unsigned int scifb0_data_c_mux[] = {
2201 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2202};
2203/* - SCIFB1 ----------------------------------------------------------------- */
2204static const unsigned int scifb1_data_pins[] = {
2205 /* RXD, TXD */
2206 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2207};
2208static const unsigned int scifb1_data_mux[] = {
2209 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2210};
2211static const unsigned int scifb1_clk_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(4, 14),
2214};
2215static const unsigned int scifb1_clk_mux[] = {
2216 SCIFB1_SCK_MARK,
2217};
2218static const unsigned int scifb1_ctrl_pins[] = {
2219 /* RTS, CTS */
2220 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2221};
2222static const unsigned int scifb1_ctrl_mux[] = {
2223 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2224};
2225static const unsigned int scifb1_data_b_pins[] = {
2226 /* RXD, TXD */
2227 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2228};
2229static const unsigned int scifb1_data_b_mux[] = {
2230 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2231};
2232static const unsigned int scifb1_clk_b_pins[] = {
2233 /* SCK */
2234 RCAR_GP_PIN(3, 1),
2235};
2236static const unsigned int scifb1_clk_b_mux[] = {
2237 SCIFB1_SCK_B_MARK,
2238};
2239static const unsigned int scifb1_ctrl_b_pins[] = {
2240 /* RTS, CTS */
2241 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2242};
2243static const unsigned int scifb1_ctrl_b_mux[] = {
2244 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2245};
2246static const unsigned int scifb1_data_c_pins[] = {
2247 /* RXD, TXD */
2248 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2249};
2250static const unsigned int scifb1_data_c_mux[] = {
2251 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2252};
2253static const unsigned int scifb1_data_d_pins[] = {
2254 /* RXD, TXD */
2255 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2256};
2257static const unsigned int scifb1_data_d_mux[] = {
2258 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2259};
2260static const unsigned int scifb1_data_e_pins[] = {
2261 /* RXD, TXD */
2262 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2263};
2264static const unsigned int scifb1_data_e_mux[] = {
2265 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2266};
2267static const unsigned int scifb1_clk_e_pins[] = {
2268 /* SCK */
2269 RCAR_GP_PIN(3, 17),
2270};
2271static const unsigned int scifb1_clk_e_mux[] = {
2272 SCIFB1_SCK_E_MARK,
2273};
2274static const unsigned int scifb1_data_f_pins[] = {
2275 /* RXD, TXD */
2276 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2277};
2278static const unsigned int scifb1_data_f_mux[] = {
2279 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2280};
2281static const unsigned int scifb1_data_g_pins[] = {
2282 /* RXD, TXD */
2283 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2284};
2285static const unsigned int scifb1_data_g_mux[] = {
2286 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2287};
2288static const unsigned int scifb1_clk_g_pins[] = {
2289 /* SCK */
2290 RCAR_GP_PIN(2, 20),
2291};
2292static const unsigned int scifb1_clk_g_mux[] = {
2293 SCIFB1_SCK_G_MARK,
2294};
2295/* - SCIFB2 ----------------------------------------------------------------- */
2296static const unsigned int scifb2_data_pins[] = {
2297 /* RXD, TXD */
2298 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2299};
2300static const unsigned int scifb2_data_mux[] = {
2301 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2302};
2303static const unsigned int scifb2_clk_pins[] = {
2304 /* SCK */
2305 RCAR_GP_PIN(4, 21),
2306};
2307static const unsigned int scifb2_clk_mux[] = {
2308 SCIFB2_SCK_MARK,
2309};
2310static const unsigned int scifb2_ctrl_pins[] = {
2311 /* RTS, CTS */
2312 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
2313};
2314static const unsigned int scifb2_ctrl_mux[] = {
2315 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2316};
2317static const unsigned int scifb2_data_b_pins[] = {
2318 /* RXD, TXD */
2319 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
2320};
2321static const unsigned int scifb2_data_b_mux[] = {
2322 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2323};
2324static const unsigned int scifb2_clk_b_pins[] = {
2325 /* SCK */
2326 RCAR_GP_PIN(0, 31),
2327};
2328static const unsigned int scifb2_clk_b_mux[] = {
2329 SCIFB2_SCK_B_MARK,
2330};
2331static const unsigned int scifb2_ctrl_b_pins[] = {
2332 /* RTS, CTS */
2333 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
2334};
2335static const unsigned int scifb2_ctrl_b_mux[] = {
2336 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2337};
2338static const unsigned int scifb2_data_c_pins[] = {
2339 /* RXD, TXD */
2340 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2341};
2342static const unsigned int scifb2_data_c_mux[] = {
2343 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2344};
2345/* - TPU0 ------------------------------------------------------------------- */
2346static const unsigned int tpu0_to0_pins[] = {
2347 /* TO */
2348 RCAR_GP_PIN(0, 20),
2349};
2350static const unsigned int tpu0_to0_mux[] = {
2351 TPU0TO0_MARK,
2352};
2353static const unsigned int tpu0_to1_pins[] = {
2354 /* TO */
2355 RCAR_GP_PIN(0, 21),
2356};
2357static const unsigned int tpu0_to1_mux[] = {
2358 TPU0TO1_MARK,
2359};
2360static const unsigned int tpu0_to2_pins[] = {
2361 /* TO */
2362 RCAR_GP_PIN(0, 22),
2363};
2364static const unsigned int tpu0_to2_mux[] = {
2365 TPU0TO2_MARK,
2366};
2367static const unsigned int tpu0_to3_pins[] = {
2368 /* TO */
2369 RCAR_GP_PIN(0, 23),
2370};
2371static const unsigned int tpu0_to3_mux[] = {
2372 TPU0TO3_MARK,
2373};
2374
2375/* - MMCIF ------------------------------------------------------------------ */
2376static const unsigned int mmc0_data1_pins[] = {
2377 /* D[0] */
2378 RCAR_GP_PIN(3, 18),
2379};
2380static const unsigned int mmc0_data1_mux[] = {
2381 MMC0_D0_MARK,
2382};
2383static const unsigned int mmc0_data4_pins[] = {
2384 /* D[0:3] */
2385 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2386 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2387};
2388static const unsigned int mmc0_data4_mux[] = {
2389 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2390};
2391static const unsigned int mmc0_data8_pins[] = {
2392 /* D[0:7] */
2393 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2394 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2395 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2396 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2397};
2398static const unsigned int mmc0_data8_mux[] = {
2399 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2400 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2401};
2402static const unsigned int mmc0_ctrl_pins[] = {
2403 /* CLK, CMD */
2404 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2405};
2406static const unsigned int mmc0_ctrl_mux[] = {
2407 MMC0_CLK_MARK, MMC0_CMD_MARK,
2408};
2409
2410static const unsigned int mmc1_data1_pins[] = {
2411 /* D[0] */
2412 RCAR_GP_PIN(3, 26),
2413};
2414static const unsigned int mmc1_data1_mux[] = {
2415 MMC1_D0_MARK,
2416};
2417static const unsigned int mmc1_data4_pins[] = {
2418 /* D[0:3] */
2419 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2420 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2421};
2422static const unsigned int mmc1_data4_mux[] = {
2423 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2424};
2425static const unsigned int mmc1_data8_pins[] = {
2426 /* D[0:7] */
2427 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2428 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2429 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2430 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2431};
2432static const unsigned int mmc1_data8_mux[] = {
2433 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2434 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2435};
2436static const unsigned int mmc1_ctrl_pins[] = {
2437 /* CLK, CMD */
2438 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2439};
2440static const unsigned int mmc1_ctrl_mux[] = {
2441 MMC1_CLK_MARK, MMC1_CMD_MARK,
2442};
2443
2444/* - SDHI ------------------------------------------------------------------- */
2445static const unsigned int sdhi0_data1_pins[] = {
2446 /* D0 */
2447 RCAR_GP_PIN(3, 2),
2448};
2449static const unsigned int sdhi0_data1_mux[] = {
2450 SD0_DAT0_MARK,
2451};
2452static const unsigned int sdhi0_data4_pins[] = {
2453 /* D[0:3] */
2454 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2455};
2456static const unsigned int sdhi0_data4_mux[] = {
2457 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2458};
2459static const unsigned int sdhi0_ctrl_pins[] = {
2460 /* CLK, CMD */
2461 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2462};
2463static const unsigned int sdhi0_ctrl_mux[] = {
2464 SD0_CLK_MARK, SD0_CMD_MARK,
2465};
2466static const unsigned int sdhi0_cd_pins[] = {
2467 /* CD */
2468 RCAR_GP_PIN(3, 6),
2469};
2470static const unsigned int sdhi0_cd_mux[] = {
2471 SD0_CD_MARK,
2472};
2473static const unsigned int sdhi0_wp_pins[] = {
2474 /* WP */
2475 RCAR_GP_PIN(3, 7),
2476};
2477static const unsigned int sdhi0_wp_mux[] = {
2478 SD0_WP_MARK,
2479};
2480
2481static const unsigned int sdhi1_data1_pins[] = {
2482 /* D0 */
2483 RCAR_GP_PIN(3, 10),
2484};
2485static const unsigned int sdhi1_data1_mux[] = {
2486 SD1_DAT0_MARK,
2487};
2488static const unsigned int sdhi1_data4_pins[] = {
2489 /* D[0:3] */
2490 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2491};
2492static const unsigned int sdhi1_data4_mux[] = {
2493 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2494};
2495static const unsigned int sdhi1_ctrl_pins[] = {
2496 /* CLK, CMD */
2497 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2498};
2499static const unsigned int sdhi1_ctrl_mux[] = {
2500 SD1_CLK_MARK, SD1_CMD_MARK,
2501};
2502static const unsigned int sdhi1_cd_pins[] = {
2503 /* CD */
2504 RCAR_GP_PIN(3, 14),
2505};
2506static const unsigned int sdhi1_cd_mux[] = {
2507 SD1_CD_MARK,
2508};
2509static const unsigned int sdhi1_wp_pins[] = {
2510 /* WP */
2511 RCAR_GP_PIN(3, 15),
2512};
2513static const unsigned int sdhi1_wp_mux[] = {
2514 SD1_WP_MARK,
2515};
2516
2517static const unsigned int sdhi2_data1_pins[] = {
2518 /* D0 */
2519 RCAR_GP_PIN(3, 18),
2520};
2521static const unsigned int sdhi2_data1_mux[] = {
2522 SD2_DAT0_MARK,
2523};
2524static const unsigned int sdhi2_data4_pins[] = {
2525 /* D[0:3] */
2526 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2527};
2528static const unsigned int sdhi2_data4_mux[] = {
2529 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2530};
2531static const unsigned int sdhi2_ctrl_pins[] = {
2532 /* CLK, CMD */
2533 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2534};
2535static const unsigned int sdhi2_ctrl_mux[] = {
2536 SD2_CLK_MARK, SD2_CMD_MARK,
2537};
2538static const unsigned int sdhi2_cd_pins[] = {
2539 /* CD */
2540 RCAR_GP_PIN(3, 22),
2541};
2542static const unsigned int sdhi2_cd_mux[] = {
2543 SD2_CD_MARK,
2544};
2545static const unsigned int sdhi2_wp_pins[] = {
2546 /* WP */
2547 RCAR_GP_PIN(3, 23),
2548};
2549static const unsigned int sdhi2_wp_mux[] = {
2550 SD2_WP_MARK,
2551};
2552
2553static const unsigned int sdhi3_data1_pins[] = {
2554 /* D0 */
2555 RCAR_GP_PIN(3, 26),
2556};
2557static const unsigned int sdhi3_data1_mux[] = {
2558 SD3_DAT0_MARK,
2559};
2560static const unsigned int sdhi3_data4_pins[] = {
2561 /* D[0:3] */
2562 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2563};
2564static const unsigned int sdhi3_data4_mux[] = {
2565 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2566};
2567static const unsigned int sdhi3_ctrl_pins[] = {
2568 /* CLK, CMD */
2569 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2570};
2571static const unsigned int sdhi3_ctrl_mux[] = {
2572 SD3_CLK_MARK, SD3_CMD_MARK,
2573};
2574static const unsigned int sdhi3_cd_pins[] = {
2575 /* CD */
2576 RCAR_GP_PIN(3, 30),
2577};
2578static const unsigned int sdhi3_cd_mux[] = {
2579 SD3_CD_MARK,
2580};
2581static const unsigned int sdhi3_wp_pins[] = {
2582 /* WP */
2583 RCAR_GP_PIN(3, 31),
2584};
2585static const unsigned int sdhi3_wp_mux[] = {
2586 SD3_WP_MARK,
2587};
2588
2589static const struct sh_pfc_pin_group pinmux_groups[] = {
2590 SH_PFC_PIN_GROUP(eth_link),
2591 SH_PFC_PIN_GROUP(eth_magic),
2592 SH_PFC_PIN_GROUP(eth_mdio),
2593 SH_PFC_PIN_GROUP(eth_rmii),
2594 SH_PFC_PIN_GROUP(intc_irq0),
2595 SH_PFC_PIN_GROUP(intc_irq1),
2596 SH_PFC_PIN_GROUP(intc_irq2),
2597 SH_PFC_PIN_GROUP(intc_irq3),
2598 SH_PFC_PIN_GROUP(scif0_data),
2599 SH_PFC_PIN_GROUP(scif0_clk),
2600 SH_PFC_PIN_GROUP(scif0_ctrl),
2601 SH_PFC_PIN_GROUP(scif0_data_b),
2602 SH_PFC_PIN_GROUP(scif1_data),
2603 SH_PFC_PIN_GROUP(scif1_clk),
2604 SH_PFC_PIN_GROUP(scif1_ctrl),
2605 SH_PFC_PIN_GROUP(scif1_data_b),
2606 SH_PFC_PIN_GROUP(scif1_data_c),
2607 SH_PFC_PIN_GROUP(scif1_data_d),
2608 SH_PFC_PIN_GROUP(scif1_clk_d),
2609 SH_PFC_PIN_GROUP(scif1_data_e),
2610 SH_PFC_PIN_GROUP(scif1_clk_e),
2611 SH_PFC_PIN_GROUP(scifa0_data),
2612 SH_PFC_PIN_GROUP(scifa0_clk),
2613 SH_PFC_PIN_GROUP(scifa0_ctrl),
2614 SH_PFC_PIN_GROUP(scifa0_data_b),
2615 SH_PFC_PIN_GROUP(scifa0_clk_b),
2616 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
2617 SH_PFC_PIN_GROUP(scifa1_data),
2618 SH_PFC_PIN_GROUP(scifa1_clk),
2619 SH_PFC_PIN_GROUP(scifa1_ctrl),
2620 SH_PFC_PIN_GROUP(scifa1_data_b),
2621 SH_PFC_PIN_GROUP(scifa1_clk_b),
2622 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
2623 SH_PFC_PIN_GROUP(scifa1_data_c),
2624 SH_PFC_PIN_GROUP(scifa1_clk_c),
2625 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
2626 SH_PFC_PIN_GROUP(scifa1_data_d),
2627 SH_PFC_PIN_GROUP(scifa1_clk_d),
2628 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
2629 SH_PFC_PIN_GROUP(scifa2_data),
2630 SH_PFC_PIN_GROUP(scifa2_clk),
2631 SH_PFC_PIN_GROUP(scifa2_ctrl),
2632 SH_PFC_PIN_GROUP(scifa2_data_b),
2633 SH_PFC_PIN_GROUP(scifa2_data_c),
2634 SH_PFC_PIN_GROUP(scifa2_clk_c),
2635 SH_PFC_PIN_GROUP(scifb0_data),
2636 SH_PFC_PIN_GROUP(scifb0_clk),
2637 SH_PFC_PIN_GROUP(scifb0_ctrl),
2638 SH_PFC_PIN_GROUP(scifb0_data_b),
2639 SH_PFC_PIN_GROUP(scifb0_clk_b),
2640 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
2641 SH_PFC_PIN_GROUP(scifb0_data_c),
2642 SH_PFC_PIN_GROUP(scifb1_data),
2643 SH_PFC_PIN_GROUP(scifb1_clk),
2644 SH_PFC_PIN_GROUP(scifb1_ctrl),
2645 SH_PFC_PIN_GROUP(scifb1_data_b),
2646 SH_PFC_PIN_GROUP(scifb1_clk_b),
2647 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
2648 SH_PFC_PIN_GROUP(scifb1_data_c),
2649 SH_PFC_PIN_GROUP(scifb1_data_d),
2650 SH_PFC_PIN_GROUP(scifb1_data_e),
2651 SH_PFC_PIN_GROUP(scifb1_clk_e),
2652 SH_PFC_PIN_GROUP(scifb1_data_f),
2653 SH_PFC_PIN_GROUP(scifb1_data_g),
2654 SH_PFC_PIN_GROUP(scifb1_clk_g),
2655 SH_PFC_PIN_GROUP(scifb2_data),
2656 SH_PFC_PIN_GROUP(scifb2_clk),
2657 SH_PFC_PIN_GROUP(scifb2_ctrl),
2658 SH_PFC_PIN_GROUP(scifb2_data_b),
2659 SH_PFC_PIN_GROUP(scifb2_clk_b),
2660 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
2661 SH_PFC_PIN_GROUP(scifb2_data_c),
2662 SH_PFC_PIN_GROUP(tpu0_to0),
2663 SH_PFC_PIN_GROUP(tpu0_to1),
2664 SH_PFC_PIN_GROUP(tpu0_to2),
2665 SH_PFC_PIN_GROUP(tpu0_to3),
2666 SH_PFC_PIN_GROUP(mmc0_data1),
2667 SH_PFC_PIN_GROUP(mmc0_data4),
2668 SH_PFC_PIN_GROUP(mmc0_data8),
2669 SH_PFC_PIN_GROUP(mmc0_ctrl),
2670 SH_PFC_PIN_GROUP(mmc1_data1),
2671 SH_PFC_PIN_GROUP(mmc1_data4),
2672 SH_PFC_PIN_GROUP(mmc1_data8),
2673 SH_PFC_PIN_GROUP(mmc1_ctrl),
2674 SH_PFC_PIN_GROUP(sdhi0_data1),
2675 SH_PFC_PIN_GROUP(sdhi0_data4),
2676 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2677 SH_PFC_PIN_GROUP(sdhi0_cd),
2678 SH_PFC_PIN_GROUP(sdhi0_wp),
2679 SH_PFC_PIN_GROUP(sdhi1_data1),
2680 SH_PFC_PIN_GROUP(sdhi1_data4),
2681 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2682 SH_PFC_PIN_GROUP(sdhi1_cd),
2683 SH_PFC_PIN_GROUP(sdhi1_wp),
2684 SH_PFC_PIN_GROUP(sdhi2_data1),
2685 SH_PFC_PIN_GROUP(sdhi2_data4),
2686 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2687 SH_PFC_PIN_GROUP(sdhi2_cd),
2688 SH_PFC_PIN_GROUP(sdhi2_wp),
2689 SH_PFC_PIN_GROUP(sdhi3_data1),
2690 SH_PFC_PIN_GROUP(sdhi3_data4),
2691 SH_PFC_PIN_GROUP(sdhi3_ctrl),
2692 SH_PFC_PIN_GROUP(sdhi3_cd),
2693 SH_PFC_PIN_GROUP(sdhi3_wp),
2694};
2695
2696static const char * const eth_groups[] = {
2697 "eth_link",
2698 "eth_magic",
2699 "eth_mdio",
2700 "eth_rmii",
2701};
2702
2703static const char * const intc_groups[] = {
2704 "intc_irq0",
2705 "intc_irq1",
2706 "intc_irq2",
2707 "intc_irq3",
2708};
2709
2710static const char * const scif0_groups[] = {
2711 "scif0_data",
2712 "scif0_clk",
2713 "scif0_ctrl",
2714 "scif0_data_b",
2715};
2716
2717static const char * const scif1_groups[] = {
2718 "scif1_data",
2719 "scif1_clk",
2720 "scif1_ctrl",
2721 "scif1_data_b",
2722 "scif1_data_c",
2723 "scif1_data_d",
2724 "scif1_clk_d",
2725 "scif1_data_e",
2726 "scif1_clk_e",
2727};
2728
2729static const char * const scifa0_groups[] = {
2730 "scifa0_data",
2731 "scifa0_clk",
2732 "scifa0_ctrl",
2733 "scifa0_data_b",
2734 "scifa0_clk_b",
2735 "scifa0_ctrl_b",
2736};
2737
2738static const char * const scifa1_groups[] = {
2739 "scifa1_data",
2740 "scifa1_clk",
2741 "scifa1_ctrl",
2742 "scifa1_data_b",
2743 "scifa1_clk_b",
2744 "scifa1_ctrl_b",
2745 "scifa1_data_c",
2746 "scifa1_clk_c",
2747 "scifa1_ctrl_c",
2748 "scifa1_data_d",
2749 "scifa1_clk_d",
2750 "scifa1_ctrl_d",
2751};
2752
2753static const char * const scifa2_groups[] = {
2754 "scifa2_data",
2755 "scifa2_clk",
2756 "scifa2_ctrl",
2757 "scifa2_data_b",
2758 "scifa2_data_c",
2759 "scifa2_clk_c",
2760};
2761
2762static const char * const scifb0_groups[] = {
2763 "scifb0_data",
2764 "scifb0_clk",
2765 "scifb0_ctrl",
2766 "scifb0_data_b",
2767 "scifb0_clk_b",
2768 "scifb0_ctrl_b",
2769 "scifb0_data_c",
2770};
2771
2772static const char * const scifb1_groups[] = {
2773 "scifb1_data",
2774 "scifb1_clk",
2775 "scifb1_ctrl",
2776 "scifb1_data_b",
2777 "scifb1_clk_b",
2778 "scifb1_ctrl_b",
2779 "scifb1_data_c",
2780 "scifb1_data_d",
2781 "scifb1_data_e",
2782 "scifb1_clk_e",
2783 "scifb1_data_f",
2784 "scifb1_data_g",
2785 "scifb1_clk_g",
2786};
2787
2788static const char * const scifb2_groups[] = {
2789 "scifb2_data",
2790 "scifb2_clk",
2791 "scifb2_ctrl",
2792 "scifb2_data_b",
2793 "scifb2_clk_b",
2794 "scifb2_ctrl_b",
2795 "scifb2_data_c",
2796};
2797
2798static const char * const tpu0_groups[] = {
2799 "tpu0_to0",
2800 "tpu0_to1",
2801 "tpu0_to2",
2802 "tpu0_to3",
2803};
2804
2805static const char * const mmc0_groups[] = {
2806 "mmc0_data1",
2807 "mmc0_data4",
2808 "mmc0_data8",
2809 "mmc0_ctrl",
2810};
2811
2812static const char * const mmc1_groups[] = {
2813 "mmc1_data1",
2814 "mmc1_data4",
2815 "mmc1_data8",
2816 "mmc1_ctrl",
2817};
2818
2819static const char * const sdhi0_groups[] = {
2820 "sdhi0_data1",
2821 "sdhi0_data4",
2822 "sdhi0_ctrl",
2823 "sdhi0_cd",
2824 "sdhi0_wp",
2825};
2826
2827static const char * const sdhi1_groups[] = {
2828 "sdhi1_data1",
2829 "sdhi1_data4",
2830 "sdhi1_ctrl",
2831 "sdhi1_cd",
2832 "sdhi1_wp",
2833};
2834
2835static const char * const sdhi2_groups[] = {
2836 "sdhi2_data1",
2837 "sdhi2_data4",
2838 "sdhi2_ctrl",
2839 "sdhi2_cd",
2840 "sdhi2_wp",
2841};
2842
2843static const char * const sdhi3_groups[] = {
2844 "sdhi3_data1",
2845 "sdhi3_data4",
2846 "sdhi3_ctrl",
2847 "sdhi3_cd",
2848 "sdhi3_wp",
2849};
2850
2851static const struct sh_pfc_function pinmux_functions[] = {
2852 SH_PFC_FUNCTION(eth),
2853 SH_PFC_FUNCTION(intc),
2854 SH_PFC_FUNCTION(scif0),
2855 SH_PFC_FUNCTION(scif1),
2856 SH_PFC_FUNCTION(scifa0),
2857 SH_PFC_FUNCTION(scifa1),
2858 SH_PFC_FUNCTION(scifa2),
2859 SH_PFC_FUNCTION(scifb0),
2860 SH_PFC_FUNCTION(scifb1),
2861 SH_PFC_FUNCTION(scifb2),
2862 SH_PFC_FUNCTION(tpu0),
2863 SH_PFC_FUNCTION(mmc0),
2864 SH_PFC_FUNCTION(mmc1),
2865 SH_PFC_FUNCTION(sdhi0),
2866 SH_PFC_FUNCTION(sdhi1),
2867 SH_PFC_FUNCTION(sdhi2),
2868 SH_PFC_FUNCTION(sdhi3),
2869};
2870
2871static struct pinmux_cfg_reg pinmux_config_regs[] = {
2872 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
2873 GP_0_31_FN, FN_IP3_17_15,
2874 GP_0_30_FN, FN_IP3_14_12,
2875 GP_0_29_FN, FN_IP3_11_8,
2876 GP_0_28_FN, FN_IP3_7_4,
2877 GP_0_27_FN, FN_IP3_3_0,
2878 GP_0_26_FN, FN_IP2_28_26,
2879 GP_0_25_FN, FN_IP2_25_22,
2880 GP_0_24_FN, FN_IP2_21_18,
2881 GP_0_23_FN, FN_IP2_17_15,
2882 GP_0_22_FN, FN_IP2_14_12,
2883 GP_0_21_FN, FN_IP2_11_9,
2884 GP_0_20_FN, FN_IP2_8_6,
2885 GP_0_19_FN, FN_IP2_5_3,
2886 GP_0_18_FN, FN_IP2_2_0,
2887 GP_0_17_FN, FN_IP1_29_28,
2888 GP_0_16_FN, FN_IP1_27_26,
2889 GP_0_15_FN, FN_IP1_25_22,
2890 GP_0_14_FN, FN_IP1_21_18,
2891 GP_0_13_FN, FN_IP1_17_15,
2892 GP_0_12_FN, FN_IP1_14_12,
2893 GP_0_11_FN, FN_IP1_11_8,
2894 GP_0_10_FN, FN_IP1_7_4,
2895 GP_0_9_FN, FN_IP1_3_0,
2896 GP_0_8_FN, FN_IP0_30_27,
2897 GP_0_7_FN, FN_IP0_26_23,
2898 GP_0_6_FN, FN_IP0_22_20,
2899 GP_0_5_FN, FN_IP0_19_16,
2900 GP_0_4_FN, FN_IP0_15_12,
2901 GP_0_3_FN, FN_IP0_11_9,
2902 GP_0_2_FN, FN_IP0_8_6,
2903 GP_0_1_FN, FN_IP0_5_3,
2904 GP_0_0_FN, FN_IP0_2_0 }
2905 },
2906 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
2907 0, 0,
2908 0, 0,
2909 GP_1_29_FN, FN_IP6_13_11,
2910 GP_1_28_FN, FN_IP6_10_9,
2911 GP_1_27_FN, FN_IP6_8_6,
2912 GP_1_26_FN, FN_IP6_5_3,
2913 GP_1_25_FN, FN_IP6_2_0,
2914 GP_1_24_FN, FN_IP5_29_27,
2915 GP_1_23_FN, FN_IP5_26_24,
2916 GP_1_22_FN, FN_IP5_23_21,
2917 GP_1_21_FN, FN_IP5_20_18,
2918 GP_1_20_FN, FN_IP5_17_15,
2919 GP_1_19_FN, FN_IP5_14_13,
2920 GP_1_18_FN, FN_IP5_12_10,
2921 GP_1_17_FN, FN_IP5_9_6,
2922 GP_1_16_FN, FN_IP5_5_3,
2923 GP_1_15_FN, FN_IP5_2_0,
2924 GP_1_14_FN, FN_IP4_29_27,
2925 GP_1_13_FN, FN_IP4_26_24,
2926 GP_1_12_FN, FN_IP4_23_21,
2927 GP_1_11_FN, FN_IP4_20_18,
2928 GP_1_10_FN, FN_IP4_17_15,
2929 GP_1_9_FN, FN_IP4_14_12,
2930 GP_1_8_FN, FN_IP4_11_9,
2931 GP_1_7_FN, FN_IP4_8_6,
2932 GP_1_6_FN, FN_IP4_5_3,
2933 GP_1_5_FN, FN_IP4_2_0,
2934 GP_1_4_FN, FN_IP3_31_29,
2935 GP_1_3_FN, FN_IP3_28_26,
2936 GP_1_2_FN, FN_IP3_25_23,
2937 GP_1_1_FN, FN_IP3_22_20,
2938 GP_1_0_FN, FN_IP3_19_18, }
2939 },
2940 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
2941 0, 0,
2942 0, 0,
2943 GP_2_29_FN, FN_IP7_15_13,
2944 GP_2_28_FN, FN_IP7_12_10,
2945 GP_2_27_FN, FN_IP7_9_8,
2946 GP_2_26_FN, FN_IP7_7_6,
2947 GP_2_25_FN, FN_IP7_5_3,
2948 GP_2_24_FN, FN_IP7_2_0,
2949 GP_2_23_FN, FN_IP6_31_29,
2950 GP_2_22_FN, FN_IP6_28_26,
2951 GP_2_21_FN, FN_IP6_25_23,
2952 GP_2_20_FN, FN_IP6_22_20,
2953 GP_2_19_FN, FN_IP6_19_17,
2954 GP_2_18_FN, FN_IP6_16_14,
2955 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
2956 GP_2_16_FN, FN_IP8_27,
2957 GP_2_15_FN, FN_IP8_26,
2958 GP_2_14_FN, FN_IP8_25_24,
2959 GP_2_13_FN, FN_IP8_23_22,
2960 GP_2_12_FN, FN_IP8_21_20,
2961 GP_2_11_FN, FN_IP8_19_18,
2962 GP_2_10_FN, FN_IP8_17_16,
2963 GP_2_9_FN, FN_IP8_15_14,
2964 GP_2_8_FN, FN_IP8_13_12,
2965 GP_2_7_FN, FN_IP8_11_10,
2966 GP_2_6_FN, FN_IP8_9_8,
2967 GP_2_5_FN, FN_IP8_7_6,
2968 GP_2_4_FN, FN_IP8_5_4,
2969 GP_2_3_FN, FN_IP8_3_2,
2970 GP_2_2_FN, FN_IP8_1_0,
2971 GP_2_1_FN, FN_IP7_30_29,
2972 GP_2_0_FN, FN_IP7_28_27 }
2973 },
2974 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
2975 GP_3_31_FN, FN_IP11_21_18,
2976 GP_3_30_FN, FN_IP11_17_15,
2977 GP_3_29_FN, FN_IP11_14_13,
2978 GP_3_28_FN, FN_IP11_12_11,
2979 GP_3_27_FN, FN_IP11_10_9,
2980 GP_3_26_FN, FN_IP11_8_7,
2981 GP_3_25_FN, FN_IP11_6_5,
2982 GP_3_24_FN, FN_IP11_4,
2983 GP_3_23_FN, FN_IP11_3_0,
2984 GP_3_22_FN, FN_IP10_29_26,
2985 GP_3_21_FN, FN_IP10_25_23,
2986 GP_3_20_FN, FN_IP10_22_19,
2987 GP_3_19_FN, FN_IP10_18_15,
2988 GP_3_18_FN, FN_IP10_14_11,
2989 GP_3_17_FN, FN_IP10_10_7,
2990 GP_3_16_FN, FN_IP10_6_4,
2991 GP_3_15_FN, FN_IP10_3_0,
2992 GP_3_14_FN, FN_IP9_31_28,
2993 GP_3_13_FN, FN_IP9_27_26,
2994 GP_3_12_FN, FN_IP9_25_24,
2995 GP_3_11_FN, FN_IP9_23_22,
2996 GP_3_10_FN, FN_IP9_21_20,
2997 GP_3_9_FN, FN_IP9_19_18,
2998 GP_3_8_FN, FN_IP9_17_16,
2999 GP_3_7_FN, FN_IP9_15_12,
3000 GP_3_6_FN, FN_IP9_11_8,
3001 GP_3_5_FN, FN_IP9_7_6,
3002 GP_3_4_FN, FN_IP9_5_4,
3003 GP_3_3_FN, FN_IP9_3_2,
3004 GP_3_2_FN, FN_IP9_1_0,
3005 GP_3_1_FN, FN_IP8_30_29,
3006 GP_3_0_FN, FN_IP8_28 }
3007 },
3008 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3009 GP_4_31_FN, FN_IP14_18_16,
3010 GP_4_30_FN, FN_IP14_15_12,
3011 GP_4_29_FN, FN_IP14_11_9,
3012 GP_4_28_FN, FN_IP14_8_6,
3013 GP_4_27_FN, FN_IP14_5_3,
3014 GP_4_26_FN, FN_IP14_2_0,
3015 GP_4_25_FN, FN_IP13_30_29,
3016 GP_4_24_FN, FN_IP13_28_26,
3017 GP_4_23_FN, FN_IP13_25_23,
3018 GP_4_22_FN, FN_IP13_22_19,
3019 GP_4_21_FN, FN_IP13_18_16,
3020 GP_4_20_FN, FN_IP13_15_13,
3021 GP_4_19_FN, FN_IP13_12_10,
3022 GP_4_18_FN, FN_IP13_9_7,
3023 GP_4_17_FN, FN_IP13_6_3,
3024 GP_4_16_FN, FN_IP13_2_0,
3025 GP_4_15_FN, FN_IP12_30_28,
3026 GP_4_14_FN, FN_IP12_27_25,
3027 GP_4_13_FN, FN_IP12_24_23,
3028 GP_4_12_FN, FN_IP12_22_20,
3029 GP_4_11_FN, FN_IP12_19_17,
3030 GP_4_10_FN, FN_IP12_16_14,
3031 GP_4_9_FN, FN_IP12_13_11,
3032 GP_4_8_FN, FN_IP12_10_8,
3033 GP_4_7_FN, FN_IP12_7_6,
3034 GP_4_6_FN, FN_IP12_5_4,
3035 GP_4_5_FN, FN_IP12_3_2,
3036 GP_4_4_FN, FN_IP12_1_0,
3037 GP_4_3_FN, FN_IP11_31_30,
3038 GP_4_2_FN, FN_IP11_29_27,
3039 GP_4_1_FN, FN_IP11_26_24,
3040 GP_4_0_FN, FN_IP11_23_22 }
3041 },
3042 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3043 GP_5_31_FN, FN_IP7_24_22,
3044 GP_5_30_FN, FN_IP7_21_19,
3045 GP_5_29_FN, FN_IP7_18_16,
3046 GP_5_28_FN, FN_DU_DOTCLKIN2,
3047 GP_5_27_FN, FN_IP7_26_25,
3048 GP_5_26_FN, FN_DU_DOTCLKIN0,
3049 GP_5_25_FN, FN_AVS2,
3050 GP_5_24_FN, FN_AVS1,
3051 GP_5_23_FN, FN_USB2_OVC,
3052 GP_5_22_FN, FN_USB2_PWEN,
3053 GP_5_21_FN, FN_IP16_7,
3054 GP_5_20_FN, FN_IP16_6,
3055 GP_5_19_FN, FN_USB0_OVC_VBUS,
3056 GP_5_18_FN, FN_USB0_PWEN,
3057 GP_5_17_FN, FN_IP16_5_3,
3058 GP_5_16_FN, FN_IP16_2_0,
3059 GP_5_15_FN, FN_IP15_29_28,
3060 GP_5_14_FN, FN_IP15_27_26,
3061 GP_5_13_FN, FN_IP15_25_23,
3062 GP_5_12_FN, FN_IP15_22_20,
3063 GP_5_11_FN, FN_IP15_19_18,
3064 GP_5_10_FN, FN_IP15_17_16,
3065 GP_5_9_FN, FN_IP15_15_14,
3066 GP_5_8_FN, FN_IP15_13_12,
3067 GP_5_7_FN, FN_IP15_11_9,
3068 GP_5_6_FN, FN_IP15_8_6,
3069 GP_5_5_FN, FN_IP15_5_3,
3070 GP_5_4_FN, FN_IP15_2_0,
3071 GP_5_3_FN, FN_IP14_30_28,
3072 GP_5_2_FN, FN_IP14_27_25,
3073 GP_5_1_FN, FN_IP14_24_22,
3074 GP_5_0_FN, FN_IP14_21_19 }
3075 },
3076 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3077 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
3078 /* IP0_31 [1] */
3079 0, 0,
3080 /* IP0_30_27 [4] */
3081 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
3082 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
3083 0, 0, 0, 0, 0, 0, 0, 0, 0,
3084 /* IP0_26_23 [4] */
3085 FN_D7, FN_AD_DI_B, FN_SDA2_C,
3086 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
3087 0, 0, 0, 0, 0, 0, 0, 0, 0,
3088 /* IP0_22_20 [3] */
3089 FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
3090 FN_SCL2_CIS_C, 0, 0,
3091 /* IP0_19_16 [4] */
3092 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
3093 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
3094 0, 0, 0, 0, 0, 0, 0, 0, 0,
3095 /* IP0_15_12 [4] */
3096 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
3097 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
3098 0, 0, 0, 0, 0, 0, 0, 0, 0,
3099 /* IP0_11_9 [3] */
3100 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
3101 0, 0, 0,
3102 /* IP0_8_6 [3] */
3103 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
3104 0, 0, 0,
3105 /* IP0_5_3 [3] */
3106 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
3107 0, 0, 0,
3108 /* IP0_2_0 [3] */
3109 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
3110 0, 0, 0, }
3111 },
3112 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3113 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
3114 /* IP1_31_30 [2] */
3115 0, 0, 0, 0,
3116 /* IP1_29_28 [2] */
3117 FN_A1, FN_PWM4, 0, 0,
3118 /* IP1_27_26 [2] */
3119 FN_A0, FN_PWM3, 0, 0,
3120 /* IP1_25_22 [4] */
3121 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
3122 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
3123 0, 0, 0, 0, 0, 0, 0, 0, 0,
3124 /* IP1_21_18 [4] */
3125 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
3126 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
3127 0, 0, 0, 0, 0, 0, 0, 0, 0,
3128 /* IP1_17_15 [3] */
3129 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
3130 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
3131 0, 0, 0,
3132 /* IP1_14_12 [3] */
3133 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
3134 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
3135 0, 0,
3136 /* IP1_11_8 [4] */
3137 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
3138 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
3139 0, 0, 0, 0, 0, 0, 0, 0, 0,
3140 /* IP1_7_4 [4] */
3141 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
3142 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
3143 0, 0, 0, 0, 0, 0, 0, 0, 0,
3144 /* IP1_3_0 [4] */
3145 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
3146 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
3147 0, 0, 0, 0, 0, 0, 0, 0, 0, }
3148 },
3149 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3150 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
3151 /* IP2_31_29 [3] */
3152 0, 0, 0, 0, 0, 0, 0, 0,
3153 /* IP2_28_26 [3] */
3154 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
3155 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
3156 /* IP2_25_22 [4] */
3157 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
3158 FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
3159 0, 0, 0, 0, 0, 0, 0, 0,
3160 /* IP2_21_18 [4] */
3161 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
3162 FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
3163 0, 0, 0, 0, 0, 0, 0, 0,
3164 /* IP2_17_15 [3] */
3165 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
3166 0, 0, 0, 0,
3167 /* IP2_14_12 [3] */
3168 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
3169 /* IP2_11_9 [3] */
3170 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
3171 /* IP2_8_6 [3] */
3172 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
3173 /* IP2_5_3 [3] */
3174 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
3175 /* IP2_2_0 [3] */
3176 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
3177 },
3178 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3179 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
3180 /* IP3_31_29 [3] */
3181 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
3182 0, 0, 0,
3183 /* IP3_28_26 [3] */
3184 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
3185 0, 0, 0, 0,
3186 /* IP3_25_23 [3] */
3187 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
3188 /* IP3_22_20 [3] */
3189 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
3190 /* IP3_19_18 [2] */
3191 FN_A16, FN_ATAWR1_N, 0, 0,
3192 /* IP3_17_15 [3] */
3193 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
3194 0, 0, 0, 0,
3195 /* IP3_14_12 [3] */
3196 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
3197 0, 0, 0, 0,
3198 /* IP3_11_8 [4] */
3199 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
3200 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
3201 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
3202 /* IP3_7_4 [4] */
3203 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
3204 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
3205 0, 0, 0, 0, 0, 0, 0, 0, 0,
3206 /* IP3_3_0 [4] */
3207 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
3208 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
3209 0, 0, 0, 0, 0, 0, 0, 0, }
3210 },
3211 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3212 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3213 /* IP4_31_30 [2] */
3214 0, 0, 0, 0,
3215 /* IP4_29_27 [3] */
3216 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
3217 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
3218 /* IP4_26_24 [3] */
3219 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
3220 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
3221 /* IP4_23_21 [3] */
3222 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
3223 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
3224 /* IP4_20_18 [3] */
3225 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
3226 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
3227 /* IP4_17_15 [3] */
3228 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
3229 0, 0, 0,
3230 /* IP4_14_12 [3] */
3231 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
3232 FN_VI2_FIELD_B, 0, 0,
3233 /* IP4_11_9 [3] */
3234 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
3235 FN_VI2_CLKENB_B, 0, 0,
3236 /* IP4_8_6 [3] */
3237 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
3238 /* IP4_5_3 [3] */
3239 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
3240 /* IP4_2_0 [3] */
3241 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
3242 }
3243 },
3244 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3245 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
3246 /* IP5_31_30 [2] */
3247 0, 0, 0, 0,
3248 /* IP5_29_27 [3] */
3249 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
3250 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
3251 /* IP5_26_24 [3] */
3252 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
3253 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
3254 FN_MSIOF0_SCK_B, 0,
3255 /* IP5_23_21 [3] */
3256 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
3257 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
3258 FN_IERX_C, 0,
3259 /* IP5_20_18 [3] */
3260 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
3261 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
3262 /* IP5_17_15 [3] */
3263 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
3264 FN_INTC_IRQ4_N, 0, 0,
3265 /* IP5_14_13 [2] */
3266 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
3267 /* IP5_12_10 [3] */
3268 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
3269 0, 0,
3270 /* IP5_9_6 [4] */
3271 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
3272 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
3273 FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
3274 /* IP5_5_3 [3] */
3275 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
3276 FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
3277 FN_INTC_EN0_N, FN_SCL1_CIS,
3278 /* IP5_2_0 [3] */
3279 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
3280 FN_VI2_R3, 0, 0, }
3281 },
3282 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3283 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
3284 /* IP6_31_29 [3] */
3285 FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
3286 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
3287 /* IP6_28_26 [3] */
3288 FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
3289 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
3290 /* IP6_25_23 [3] */
3291 FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
3292 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
3293 /* IP6_22_20 [3] */
3294 FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
3295 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
3296 /* IP6_19_17 [3] */
3297 FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
3298 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
3299 /* IP6_16_14 [3] */
3300 FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
3301 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
3302 FN_SCL2_CIS_E, 0,
3303 /* IP6_13_11 [3] */
3304 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
3305 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
3306 /* IP6_10_9 [2] */
3307 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
3308 /* IP6_8_6 [3] */
3309 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
3310 FN_SSI_SDATA8_C, 0, 0, 0,
3311 /* IP6_5_3 [3] */
3312 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
3313 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
3314 /* IP6_2_0 [3] */
3315 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
3316 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
3317 },
3318 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3319 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
3320 /* IP7_31 [1] */
3321 0, 0,
3322 /* IP7_30_29 [2] */
3323 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
3324 FN_MII_RXD2,
3325 /* IP7_28_27 [2] */
3326 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
3327 /* IP7_26_25 [2] */
3328 FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
3329 /* IP7_24_22 [3] */
3330 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
3331 0, 0, 0,
3332 /* IP7_21_19 [3] */
3333 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
3334 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
3335 /* IP7_18_16 [3] */
3336 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
3337 FN_GLO_SS_C, 0, 0, 0,
3338 /* IP7_15_13 [3] */
3339 FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
3340 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
3341 /* IP7_12_10 [3] */
3342 FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
3343 FN_GLO_SCLK_C, 0, 0, 0,
3344 /* IP7_9_8 [2] */
3345 FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
3346 /* IP7_7_6 [2] */
3347 FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
3348 /* IP7_5_3 [3] */
3349 FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
3350 0, 0, 0,
3351 /* IP7_2_0 [3] */
3352 FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
3353 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
3354 },
3355 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3356 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
3357 2, 2, 2, 2, 2, 2, 2) {
3358 /* IP8_31 [1] */
3359 0, 0,
3360 /* IP8_30_29 [2] */
3361 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
3362 /* IP8_28 [1] */
3363 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
3364 /* IP8_27 [1] */
3365 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
3366 /* IP8_26 [1] */
3367 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
3368 /* IP8_25_24 [2] */
3369 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
3370 FN_AVB_MAGIC, FN_MII_MAGIC,
3371 /* IP8_23_22 [2] */
3372 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
3373 /* IP8_21_20 [2] */
3374 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
3375 FN_MII_MDIO,
3376 /* IP8_19_18 [2] */
3377 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
3378 /* IP8_17_16 [2] */
3379 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
3380 /* IP8_15_14 [2] */
3381 FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
3382 /* IP8_13_12 [2] */
3383 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
3384 /* IP8_11_10 [2] */
3385 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
3386 /* IP8_9_8 [2] */
3387 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
3388 /* IP8_7_6 [2] */
3389 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
3390 /* IP8_5_4 [2] */
3391 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
3392 /* IP8_3_2 [2] */
3393 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
3394 /* IP8_1_0 [2] */
3395 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
3396 },
3397 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3398 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
3399 /* IP9_31_28 [4] */
3400 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
3401 FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
3402 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
3403 /* IP9_27_26 [2] */
3404 FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
3405 /* IP9_25_24 [2] */
3406 FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
3407 /* IP9_23_22 [2] */
3408 FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
3409 /* IP9_21_20 [2] */
3410 FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
3411 /* IP9_19_18 [2] */
3412 FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
3413 /* IP9_17_16 [2] */
3414 FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
3415 /* IP9_15_12 [4] */
3416 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
3417 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
3418 FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
3419 /* IP9_11_8 [4] */
3420 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
3421 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
3422 FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
3423 /* IP9_7_6 [2] */
3424 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
3425 /* IP9_5_4 [2] */
3426 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
3427 /* IP9_3_2 [2] */
3428 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
3429 /* IP9_1_0 [2] */
3430 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
3431 },
3432 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3433 2, 4, 3, 4, 4, 4, 4, 3, 4) {
3434 /* IP10_31_30 [2] */
3435 0, 0, 0, 0,
3436 /* IP10_29_26 [4] */
3437 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
3438 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
3439 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
3440 /* IP10_25_23 [3] */
3441 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
3442 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
3443 /* IP10_22_19 [4] */
3444 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
3445 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
3446 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
3447 /* IP10_18_15 [4] */
3448 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
3449 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
3450 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
3451 0, 0, 0, 0, 0, 0,
3452 /* IP10_14_11 [4] */
3453 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
3454 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
3455 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
3456 0, 0, 0, 0, 0, 0, 0,
3457 /* IP10_10_7 [4] */
3458 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
3459 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
3460 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
3461 0, 0, 0, 0, 0, 0, 0,
3462 /* IP10_6_4 [3] */
3463 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
3464 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
3465 FN_VI3_DATA0_B, 0,
3466 /* IP10_3_0 [4] */
3467 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
3468 FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
3469 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
3470 },
3471 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3472 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
3473 /* IP11_31_30 [2] */
3474 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
3475 /* IP11_29_27 [3] */
3476 FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
3477 FN_RDS_CLK_B, 0, 0,
3478 /* IP11_26_24 [3] */
3479 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
3480 0, 0, 0,
3481 /* IP11_23_22 [2] */
3482 FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
3483 /* IP11_21_18 [4] */
3484 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
3485 FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
3486 FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
3487 /* IP11_17_15 [3] */
3488 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
3489 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
3490 /* IP11_14_13 [2] */
3491 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
3492 /* IP11_12_11 [2] */
3493 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
3494 /* IP11_10_9 [2] */
3495 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
3496 /* IP11_8_7 [2] */
3497 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
3498 /* IP11_6_5 [2] */
3499 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
3500 /* IP11_4 [1] */
3501 FN_SD3_CLK, FN_MMC1_CLK,
3502 /* IP11_3_0 [4] */
3503 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
3504 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
3505 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
3506 },
3507 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3508 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3509 /* IP12_31 [1] */
3510 0, 0,
3511 /* IP12_30_28 [3] */
3512 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
3513 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
3514 FN_CAN_DEBUGOUT4, 0, 0,
3515 /* IP12_27_25 [3] */
3516 FN_SSI_SCK5, FN_SCIFB1_SCK,
3517 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
3518 FN_CAN_DEBUGOUT3, 0, 0,
3519 /* IP12_24_23 [2] */
3520 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
3521 FN_CAN_DEBUGOUT2,
3522 /* IP12_22_20 [3] */
3523 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
3524 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
3525 /* IP12_19_17 [3] */
3526 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
3527 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
3528 /* IP12_16_14 [3] */
3529 FN_SSI_SDATA3, FN_STP_ISCLK_0,
3530 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
3531 /* IP12_13_11 [3] */
3532 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
3533 FN_CAN_STEP0, 0, 0, 0,
3534 /* IP12_10_8 [3] */
3535 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
3536 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
3537 /* IP12_7_6 [2] */
3538 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
3539 /* IP12_5_4 [2] */
3540 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
3541 /* IP12_3_2 [2] */
3542 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
3543 /* IP12_1_0 [2] */
3544 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
3545 },
3546 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3547 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
3548 /* IP13_31 [1] */
3549 0, 0,
3550 /* IP13_30_29 [2] */
3551 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
3552 /* IP13_28_26 [3] */
3553 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
3554 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
3555 /* IP13_25_23 [3] */
3556 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
3557 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
3558 /* IP13_22_19 [4] */
3559 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
3560 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
3561 FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
3562 0, 0, 0, 0,
3563 /* IP13_18_16 [3] */
3564 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
3565 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
3566 /* IP13_15_13 [3] */
3567 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
3568 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
3569 /* IP13_12_10 [3] */
3570 FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
3571 FN_CAN_DEBUGOUT8, 0, 0,
3572 /* IP13_9_7 [3] */
3573 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
3574 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
3575 /* IP13_6_3 [4] */
3576 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
3577 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
3578 FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
3579 /* IP13_2_0 [3] */
3580 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
3581 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
3582 },
3583 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
3584 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
3585 /* IP14_30 [1] */
3586 0, 0,
3587 /* IP14_30_28 [3] */
3588 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
3589 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
3590 FN_HRTS0_N_C, 0,
3591 /* IP14_27_25 [3] */
3592 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
3593 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
3594 /* IP14_24_22 [3] */
3595 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
3596 FN_LCDOUT9, 0, 0, 0,
3597 /* IP14_21_19 [3] */
3598 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
3599 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
3600 /* IP14_18_16 [3] */
3601 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
3602 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
3603 /* IP14_15_12 [4] */
3604 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
3605 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
3606 0, 0, 0, 0, 0, 0, 0,
3607 /* IP14_11_9 [3] */
3608 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
3609 0, 0, 0,
3610 /* IP14_8_6 [3] */
3611 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
3612 0, 0, 0,
3613 /* IP14_5_3 [3] */
3614 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
3615 FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
3616 /* IP14_2_0 [3] */
3617 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
3618 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
3619 FN_REMOCON, 0, }
3620 },
3621 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
3622 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
3623 /* IP15_31_30 [2] */
3624 0, 0, 0, 0,
3625 /* IP15_29_28 [2] */
3626 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
3627 /* IP15_27_26 [2] */
3628 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
3629 /* IP15_25_23 [3] */
3630 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
3631 FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
3632 /* IP15_22_20 [3] */
3633 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
3634 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
3635 /* IP15_19_18 [2] */
3636 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
3637 /* IP15_17_16 [2] */
3638 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
3639 /* IP15_15_14 [2] */
3640 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
3641 /* IP15_13_12 [2] */
3642 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
3643 /* IP15_11_9 [3] */
3644 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
3645 0, 0, 0,
3646 /* IP15_8_6 [3] */
3647 FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
3648 FN_SDA2, FN_SDA2_CIS, 0,
3649 /* IP15_5_3 [3] */
3650 FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
3651 FN_SCL2, FN_SCL2_CIS, 0,
3652 /* IP15_2_0 [3] */
3653 FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
3654 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
3655 },
3656 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
3657 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
3658 /* IP16_31_28 [4] */
3659 0, 0, 0, 0, 0, 0, 0, 0,
3660 0, 0, 0, 0, 0, 0, 0, 0,
3661 /* IP16_27_24 [4] */
3662 0, 0, 0, 0, 0, 0, 0, 0,
3663 0, 0, 0, 0, 0, 0, 0, 0,
3664 /* IP16_23_20 [4] */
3665 0, 0, 0, 0, 0, 0, 0, 0,
3666 0, 0, 0, 0, 0, 0, 0, 0,
3667 /* IP16_19_16 [4] */
3668 0, 0, 0, 0, 0, 0, 0, 0,
3669 0, 0, 0, 0, 0, 0, 0, 0,
3670 /* IP16_15_12 [4] */
3671 0, 0, 0, 0, 0, 0, 0, 0,
3672 0, 0, 0, 0, 0, 0, 0, 0,
3673 /* IP16_11_8 [4] */
3674 0, 0, 0, 0, 0, 0, 0, 0,
3675 0, 0, 0, 0, 0, 0, 0, 0,
3676 /* IP16_7 [1] */
3677 FN_USB1_OVC, FN_TCLK1_B,
3678 /* IP16_6 [1] */
3679 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
3680 /* IP16_5_3 [3] */
3681 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
3682 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
3683 /* IP16_2_0 [3] */
3684 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
3685 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
3686 },
3687 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
3688 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
3689 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
3690 /* SEL_SCIF1 [3] */
3691 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
3692 FN_SEL_SCIF1_4, 0, 0, 0,
3693 /* SEL_SCIFB [2] */
3694 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
3695 /* SEL_SCIFB2 [2] */
3696 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
3697 /* SEL_SCIFB1 [3] */
3698 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
3699 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
3700 FN_SEL_SCIFB1_6, 0,
3701 /* SEL_SCIFA1 [2] */
3702 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
3703 FN_SEL_SCIFA1_3,
3704 /* SEL_SCIF0 [1] */
3705 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
3706 /* SEL_SCIFA [1] */
3707 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
3708 /* SEL_SOF1 [1] */
3709 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
3710 /* SEL_SSI7 [2] */
3711 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3712 /* SEL_SSI6 [1] */
3713 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
3714 /* SEL_SSI5 [2] */
3715 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
3716 /* SEL_VI3 [1] */
3717 FN_SEL_VI3_0, FN_SEL_VI3_1,
3718 /* SEL_VI2 [1] */
3719 FN_SEL_VI2_0, FN_SEL_VI2_1,
3720 /* SEL_VI1 [1] */
3721 FN_SEL_VI1_0, FN_SEL_VI1_1,
3722 /* SEL_VI0 [1] */
3723 FN_SEL_VI0_0, FN_SEL_VI0_1,
3724 /* SEL_TSIF1 [2] */
3725 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
3726 /* RESERVED [1] */
3727 0, 0,
3728 /* SEL_LBS [1] */
3729 FN_SEL_LBS_0, FN_SEL_LBS_1,
3730 /* SEL_TSIF0 [2] */
3731 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
3732 /* SEL_SOF3 [1] */
3733 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
3734 /* SEL_SOF0 [1] */
3735 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
3736 },
3737 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3738 3, 1, 1, 1, 2, 1, 2, 1, 2,
3739 1, 1, 1, 3, 3, 2, 3, 2, 2) {
3740 /* RESERVED [3] */
3741 0, 0, 0, 0, 0, 0, 0, 0,
3742 /* SEL_TMU1 [1] */
3743 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
3744 /* SEL_HSCIF1 [1] */
3745 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3746 /* SEL_SCIFCLK [1] */
3747 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3748 /* SEL_CAN0 [2] */
3749 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3750 /* SEL_CANCLK [1] */
3751 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
3752 /* SEL_SCIFA2 [2] */
3753 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
3754 /* SEL_CAN1 [1] */
3755 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
3756 /* RESERVED [2] */
3757 0, 0, 0, 0,
3758 /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
3759 0, 0,
3760 /* SEL_ADI [1] */
3761 FN_SEL_ADI_0, FN_SEL_ADI_1,
3762 /* SEL_SSP [1] */
3763 FN_SEL_SSP_0, FN_SEL_SSP_1,
3764 /* SEL_FM [3] */
3765 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
3766 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
3767 /* SEL_HSCIF0 [3] */
3768 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
3769 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
3770 /* SEL_GPS [2] */
3771 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
3772 /* SEL_RDS [3] */
3773 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
3774 FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
3775 /* SEL_SIM [2] */
3776 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
3777 /* SEL_SSI8 [2] */
3778 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
3779 },
3780 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
3781 1, 1, 2, 4, 4, 2, 2,
3782 4, 2, 3, 2, 3, 2) {
3783 /* SEL_IICDVFS [1] */
3784 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
3785 /* SEL_IIC0 [1] */
3786 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
3787 /* RESERVED [2] */
3788 0, 0, 0, 0,
3789 /* RESERVED [4] */
3790 0, 0, 0, 0, 0, 0, 0, 0,
3791 0, 0, 0, 0, 0, 0, 0, 0,
3792 /* RESERVED [4] */
3793 0, 0, 0, 0, 0, 0, 0, 0,
3794 0, 0, 0, 0, 0, 0, 0, 0,
3795 /* RESERVED [2] */
3796 0, 0, 0, 0,
3797 /* SEL_IEB [2] */
3798 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
3799 /* RESERVED [4] */
3800 0, 0, 0, 0, 0, 0, 0, 0,
3801 0, 0, 0, 0, 0, 0, 0, 0,
3802 /* RESERVED [2] */
3803 0, 0, 0, 0,
3804 /* SEL_IIC2 [3] */
3805 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
3806 FN_SEL_IIC2_4, 0, 0, 0,
3807 /* SEL_IIC1 [2] */
3808 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
3809 /* SEL_I2C2 [3] */
3810 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3811 FN_SEL_I2C2_4, 0, 0, 0,
3812 /* SEL_I2C1 [2] */
3813 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
3814 },
3815 { },
3816};
3817
3818const struct sh_pfc_soc_info r8a7790_pinmux_info = {
3819 .name = "r8a77900_pfc",
3820 .unlock_reg = 0xe6060000, /* PMMR */
3821
3822 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3823
3824 .pins = pinmux_pins,
3825 .nr_pins = ARRAY_SIZE(pinmux_pins),
3826 .groups = pinmux_groups,
3827 .nr_groups = ARRAY_SIZE(pinmux_groups),
3828 .functions = pinmux_functions,
3829 .nr_functions = ARRAY_SIZE(pinmux_functions),
3830
3831 .cfg_regs = pinmux_config_regs,
3832
3833 .gpio_data = pinmux_data,
3834 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3835};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21a5ac8..6dfb18772574 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */ 22 */
23#include <linux/io.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/pinctrl/pinconf-generic.h>
26
24#include <mach/irqs.h> 27#include <mach/irqs.h>
25#include <mach/sh7372.h> 28#include <mach/sh7372.h>
26 29
30#include "core.h"
27#include "sh_pfc.h" 31#include "sh_pfc.h"
28 32
29#define CPU_ALL_PORT(fn, pfx, sfx) \ 33#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -34,6 +38,35 @@
34 PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ 38 PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
35 PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) 39 PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
36 40
41#undef _GPIO_PORT
42#define _GPIO_PORT(gpio, sfx) \
43 [gpio] = { \
44 .name = __stringify(PORT##gpio), \
45 .enum_id = PORT##gpio##_DATA, \
46 }
47
48#define IRQC_PIN_MUX(irq, pin) \
49static const unsigned int intc_irq##irq##_pins[] = { \
50 pin, \
51}; \
52static const unsigned int intc_irq##irq##_mux[] = { \
53 IRQ##irq##_MARK, \
54}
55
56#define IRQC_PINS_MUX(irq, pin0, pin1) \
57static const unsigned int intc_irq##irq##_0_pins[] = { \
58 pin0, \
59}; \
60static const unsigned int intc_irq##irq##_0_mux[] = { \
61 IRQ##irq##_##pin0##_MARK, \
62}; \
63static const unsigned int intc_irq##irq##_1_pins[] = { \
64 pin1, \
65}; \
66static const unsigned int intc_irq##irq##_1_mux[] = { \
67 IRQ##irq##_##pin1##_MARK, \
68}
69
37enum { 70enum {
38 PINMUX_RESERVED = 0, 71 PINMUX_RESERVED = 0,
39 72
@@ -47,16 +80,6 @@ enum {
47 PORT_ALL(IN), 80 PORT_ALL(IN),
48 PINMUX_INPUT_END, 81 PINMUX_INPUT_END,
49 82
50 /* PORT0_IN_PU -> PORT190_IN_PU */
51 PINMUX_INPUT_PULLUP_BEGIN,
52 PORT_ALL(IN_PU),
53 PINMUX_INPUT_PULLUP_END,
54
55 /* PORT0_IN_PD -> PORT190_IN_PD */
56 PINMUX_INPUT_PULLDOWN_BEGIN,
57 PORT_ALL(IN_PD),
58 PINMUX_INPUT_PULLDOWN_END,
59
60 /* PORT0_OUT -> PORT190_OUT */ 83 /* PORT0_OUT -> PORT190_OUT */
61 PINMUX_OUTPUT_BEGIN, 84 PINMUX_OUTPUT_BEGIN,
62 PORT_ALL(OUT), 85 PORT_ALL(OUT),
@@ -368,124 +391,11 @@ enum {
368 PINMUX_MARK_END, 391 PINMUX_MARK_END,
369}; 392};
370 393
371static const pinmux_enum_t pinmux_data[] = { 394#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
395#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
372 396
373 /* specify valid pin states for each pin in GPIO mode */ 397static const pinmux_enum_t pinmux_data[] = {
374 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), 398 PINMUX_DATA_GP_ALL(),
375 PORT_DATA_O(2), PORT_DATA_I_PD(3),
376 PORT_DATA_I_PD(4), PORT_DATA_I_PD(5),
377 PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7),
378 PORT_DATA_IO_PD(8), PORT_DATA_O(9),
379
380 PORT_DATA_O(10), PORT_DATA_O(11),
381 PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13),
382 PORT_DATA_IO_PD(14), PORT_DATA_O(15),
383 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
384 PORT_DATA_I_PD(18), PORT_DATA_IO(19),
385
386 PORT_DATA_IO(20), PORT_DATA_IO(21),
387 PORT_DATA_IO(22), PORT_DATA_IO(23),
388 PORT_DATA_IO(24), PORT_DATA_IO(25),
389 PORT_DATA_IO(26), PORT_DATA_IO(27),
390 PORT_DATA_IO(28), PORT_DATA_IO(29),
391
392 PORT_DATA_IO(30), PORT_DATA_IO(31),
393 PORT_DATA_IO(32), PORT_DATA_IO(33),
394 PORT_DATA_IO(34), PORT_DATA_IO(35),
395 PORT_DATA_IO(36), PORT_DATA_IO(37),
396 PORT_DATA_IO(38), PORT_DATA_IO(39),
397
398 PORT_DATA_IO(40), PORT_DATA_IO(41),
399 PORT_DATA_IO(42), PORT_DATA_IO(43),
400 PORT_DATA_IO(44), PORT_DATA_IO(45),
401 PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47),
402 PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49),
403
404 PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51),
405 PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53),
406 PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55),
407 PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57),
408 PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59),
409
410 PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61),
411 PORT_DATA_IO(62), PORT_DATA_O(63),
412 PORT_DATA_O(64), PORT_DATA_IO_PU(65),
413 PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/
414 PORT_DATA_O(68), PORT_DATA_IO(69),
415
416 PORT_DATA_IO(70), PORT_DATA_IO(71),
417 PORT_DATA_O(72), PORT_DATA_I_PU(73),
418 PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75),
419 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
420 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
421
422 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
423 PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
424 PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
425 PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87),
426 PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89),
427
428 PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91),
429 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
430 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
431 PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97),
432 PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/
433
434 PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101),
435 PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103),
436 PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105),
437 PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107),
438 PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109),
439
440 PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111),
441 PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
442 PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115),
443 PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
444 PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119),
445
446 PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121),
447 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
448 PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125),
449 PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127),
450 PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129),
451
452 PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
453 PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
454 PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135),
455 PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137),
456 PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139),
457
458 PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141),
459 PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143),
460 PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145),
461 PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147),
462 PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149),
463
464 PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151),
465 PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153),
466 PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155),
467 PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157),
468 PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159),
469
470 PORT_DATA_O(160), PORT_DATA_IO_PD(161),
471 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
472 PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165),
473 PORT_DATA_I_PD(166), PORT_DATA_I_PD(167),
474 PORT_DATA_I_PD(168), PORT_DATA_I_PD(169),
475
476 PORT_DATA_I_PD(170), PORT_DATA_O(171),
477 PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
478 PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
479 PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
480 PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179),
481
482 PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181),
483 PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183),
484 PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185),
485 PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187),
486 PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189),
487
488 PORT_DATA_IO_PU_PD(190),
489 399
490 /* IRQ */ 400 /* IRQ */
491 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), 401 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
@@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = {
929 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), 839 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
930}; 840};
931 841
842#define SH7372_PIN(pin, cfgs) \
843 { \
844 .name = __stringify(PORT##pin), \
845 .enum_id = PORT##pin##_DATA, \
846 .configs = cfgs, \
847 }
848
849#define __I (SH_PFC_PIN_CFG_INPUT)
850#define __O (SH_PFC_PIN_CFG_OUTPUT)
851#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
852#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
853#define __PU (SH_PFC_PIN_CFG_PULL_UP)
854#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
855
856#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD)
857#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU)
858#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD)
859#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO)
860#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD)
861#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU)
862#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD)
863#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O)
864#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD)
865
932static struct sh_pfc_pin pinmux_pins[] = { 866static struct sh_pfc_pin pinmux_pins[] = {
933 GPIO_PORT_ALL(), 867 /* Table 57-1 (I/O and Pull U/D) */
868 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
869 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
870 SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5),
871 SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7),
872 SH7372_PIN_IO_PD(8), SH7372_PIN_O(9),
873 SH7372_PIN_O(10), SH7372_PIN_O(11),
874 SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13),
875 SH7372_PIN_IO_PD(14), SH7372_PIN_O(15),
876 SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17),
877 SH7372_PIN_I_PD(18), SH7372_PIN_IO(19),
878 SH7372_PIN_IO(20), SH7372_PIN_IO(21),
879 SH7372_PIN_IO(22), SH7372_PIN_IO(23),
880 SH7372_PIN_IO(24), SH7372_PIN_IO(25),
881 SH7372_PIN_IO(26), SH7372_PIN_IO(27),
882 SH7372_PIN_IO(28), SH7372_PIN_IO(29),
883 SH7372_PIN_IO(30), SH7372_PIN_IO(31),
884 SH7372_PIN_IO(32), SH7372_PIN_IO(33),
885 SH7372_PIN_IO(34), SH7372_PIN_IO(35),
886 SH7372_PIN_IO(36), SH7372_PIN_IO(37),
887 SH7372_PIN_IO(38), SH7372_PIN_IO(39),
888 SH7372_PIN_IO(40), SH7372_PIN_IO(41),
889 SH7372_PIN_IO(42), SH7372_PIN_IO(43),
890 SH7372_PIN_IO(44), SH7372_PIN_IO(45),
891 SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47),
892 SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49),
893 SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51),
894 SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53),
895 SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55),
896 SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57),
897 SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59),
898 SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61),
899 SH7372_PIN_IO(62), SH7372_PIN_O(63),
900 SH7372_PIN_O(64), SH7372_PIN_IO_PU(65),
901 SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67),
902 SH7372_PIN_O(68), SH7372_PIN_IO(69),
903 SH7372_PIN_IO(70), SH7372_PIN_IO(71),
904 SH7372_PIN_O(72), SH7372_PIN_I_PU(73),
905 SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75),
906 SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77),
907 SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79),
908 SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81),
909 SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83),
910 SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85),
911 SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87),
912 SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89),
913 SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91),
914 SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93),
915 SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95),
916 SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97),
917 SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99),
918 SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101),
919 SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103),
920 SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105),
921 SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107),
922 SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109),
923 SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111),
924 SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113),
925 SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115),
926 SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117),
927 SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119),
928 SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121),
929 SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123),
930 SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125),
931 SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127),
932 SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129),
933 SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131),
934 SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133),
935 SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135),
936 SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137),
937 SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139),
938 SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141),
939 SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143),
940 SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145),
941 SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147),
942 SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149),
943 SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151),
944 SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153),
945 SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155),
946 SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157),
947 SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159),
948 SH7372_PIN_O(160), SH7372_PIN_IO_PD(161),
949 SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163),
950 SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165),
951 SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167),
952 SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169),
953 SH7372_PIN_I_PD(170), SH7372_PIN_O(171),
954 SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173),
955 SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175),
956 SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177),
957 SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179),
958 SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181),
959 SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183),
960 SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185),
961 SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187),
962 SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189),
963 SH7372_PIN_IO_PU_PD(190),
934}; 964};
935 965
966/* - BSC -------------------------------------------------------------------- */
967static const unsigned int bsc_data8_pins[] = {
968 /* D[0:7] */
969 46, 47, 48, 49, 50, 51, 52, 53,
970};
971static const unsigned int bsc_data8_mux[] = {
972 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
973 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
974};
975static const unsigned int bsc_data16_pins[] = {
976 /* D[0:15] */
977 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
978};
979static const unsigned int bsc_data16_mux[] = {
980 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
981 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
982 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
983 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
984};
985static const unsigned int bsc_cs0_pins[] = {
986 /* CS */
987 62,
988};
989static const unsigned int bsc_cs0_mux[] = {
990 CS0_MARK,
991};
992static const unsigned int bsc_cs2_pins[] = {
993 /* CS */
994 63,
995};
996static const unsigned int bsc_cs2_mux[] = {
997 CS2_MARK,
998};
999static const unsigned int bsc_cs4_pins[] = {
1000 /* CS */
1001 64,
1002};
1003static const unsigned int bsc_cs4_mux[] = {
1004 CS4_MARK,
1005};
1006static const unsigned int bsc_cs5a_pins[] = {
1007 /* CS */
1008 65,
1009};
1010static const unsigned int bsc_cs5a_mux[] = {
1011 CS5A_MARK,
1012};
1013static const unsigned int bsc_cs5b_pins[] = {
1014 /* CS */
1015 66,
1016};
1017static const unsigned int bsc_cs5b_mux[] = {
1018 CS5B_MARK,
1019};
1020static const unsigned int bsc_cs6a_pins[] = {
1021 /* CS */
1022 67,
1023};
1024static const unsigned int bsc_cs6a_mux[] = {
1025 CS6A_MARK,
1026};
1027static const unsigned int bsc_rd_we8_pins[] = {
1028 /* RD, WE[0] */
1029 69, 70,
1030};
1031static const unsigned int bsc_rd_we8_mux[] = {
1032 RD_FSC_MARK, WE0_FWE_MARK,
1033};
1034static const unsigned int bsc_rd_we16_pins[] = {
1035 /* RD, WE[0:1] */
1036 69, 70, 71,
1037};
1038static const unsigned int bsc_rd_we16_mux[] = {
1039 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1040};
1041static const unsigned int bsc_bs_pins[] = {
1042 /* BS */
1043 19,
1044};
1045static const unsigned int bsc_bs_mux[] = {
1046 BS_MARK,
1047};
1048static const unsigned int bsc_rdwr_pins[] = {
1049 /* RDWR */
1050 75,
1051};
1052static const unsigned int bsc_rdwr_mux[] = {
1053 RDWR_MARK,
1054};
1055static const unsigned int bsc_wait_pins[] = {
1056 /* WAIT */
1057 74,
1058};
1059static const unsigned int bsc_wait_mux[] = {
1060 WAIT_MARK,
1061};
1062/* - CEU -------------------------------------------------------------------- */
1063static const unsigned int ceu_data_0_7_pins[] = {
1064 /* D[0:7] */
1065 102, 103, 104, 105, 106, 107, 108, 109,
1066};
1067static const unsigned int ceu_data_0_7_mux[] = {
1068 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
1069 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
1070};
1071static const unsigned int ceu_data_8_15_pins[] = {
1072 /* D[8:15] */
1073 110, 111, 112, 113, 114, 115, 116, 117,
1074};
1075static const unsigned int ceu_data_8_15_mux[] = {
1076 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
1077 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
1078};
1079static const unsigned int ceu_clk_0_pins[] = {
1080 /* CKO */
1081 120,
1082};
1083static const unsigned int ceu_clk_0_mux[] = {
1084 VIO_CKO_MARK,
1085};
1086static const unsigned int ceu_clk_1_pins[] = {
1087 /* CKO */
1088 16,
1089};
1090static const unsigned int ceu_clk_1_mux[] = {
1091 VIO_CKO1_MARK,
1092};
1093static const unsigned int ceu_clk_2_pins[] = {
1094 /* CKO */
1095 17,
1096};
1097static const unsigned int ceu_clk_2_mux[] = {
1098 VIO_CKO2_MARK,
1099};
1100static const unsigned int ceu_sync_pins[] = {
1101 /* CLK, VD, HD */
1102 118, 100, 101,
1103};
1104static const unsigned int ceu_sync_mux[] = {
1105 VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
1106};
1107static const unsigned int ceu_field_pins[] = {
1108 /* FIELD */
1109 119,
1110};
1111static const unsigned int ceu_field_mux[] = {
1112 VIO_FIELD_MARK,
1113};
1114/* - FLCTL ------------------------------------------------------------------ */
1115static const unsigned int flctl_data_pins[] = {
1116 /* NAF[0:15] */
1117 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
1118};
1119static const unsigned int flctl_data_mux[] = {
1120 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1121 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1122 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1123 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1124};
1125static const unsigned int flctl_ce0_pins[] = {
1126 /* CE */
1127 68,
1128};
1129static const unsigned int flctl_ce0_mux[] = {
1130 FCE0_MARK,
1131};
1132static const unsigned int flctl_ce1_pins[] = {
1133 /* CE */
1134 66,
1135};
1136static const unsigned int flctl_ce1_mux[] = {
1137 FCE1_MARK,
1138};
1139static const unsigned int flctl_ctrl_pins[] = {
1140 /* FCDE, FOE, FSC, FWE, FRB */
1141 24, 23, 69, 70, 73,
1142};
1143static const unsigned int flctl_ctrl_mux[] = {
1144 A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
1145};
1146/* - FSIA ------------------------------------------------------------------- */
1147static const unsigned int fsia_mclk_in_pins[] = {
1148 /* CK */
1149 4,
1150};
1151static const unsigned int fsia_mclk_in_mux[] = {
1152 FSIACK_MARK,
1153};
1154static const unsigned int fsia_mclk_out_pins[] = {
1155 /* OMC */
1156 8,
1157};
1158static const unsigned int fsia_mclk_out_mux[] = {
1159 FSIAOMC_MARK,
1160};
1161static const unsigned int fsia_sclk_in_pins[] = {
1162 /* ILR, IBT */
1163 5, 6,
1164};
1165static const unsigned int fsia_sclk_in_mux[] = {
1166 FSIAILR_MARK, FSIAIBT_MARK,
1167};
1168static const unsigned int fsia_sclk_out_pins[] = {
1169 /* OLR, OBT */
1170 9, 10,
1171};
1172static const unsigned int fsia_sclk_out_mux[] = {
1173 FSIAOLR_MARK, FSIAOBT_MARK,
1174};
1175static const unsigned int fsia_data_in_pins[] = {
1176 /* ISLD */
1177 7,
1178};
1179static const unsigned int fsia_data_in_mux[] = {
1180 FSIAISLD_MARK,
1181};
1182static const unsigned int fsia_data_out_pins[] = {
1183 /* OSLD */
1184 11,
1185};
1186static const unsigned int fsia_data_out_mux[] = {
1187 FSIAOSLD_MARK,
1188};
1189static const unsigned int fsia_spdif_0_pins[] = {
1190 /* SPDIF */
1191 11,
1192};
1193static const unsigned int fsia_spdif_0_mux[] = {
1194 FSIASPDIF_11_MARK,
1195};
1196static const unsigned int fsia_spdif_1_pins[] = {
1197 /* SPDIF */
1198 15,
1199};
1200static const unsigned int fsia_spdif_1_mux[] = {
1201 FSIASPDIF_15_MARK,
1202};
1203/* - FSIB ------------------------------------------------------------------- */
1204static const unsigned int fsib_mclk_in_pins[] = {
1205 /* CK */
1206 4,
1207};
1208static const unsigned int fsib_mclk_in_mux[] = {
1209 FSIBCK_MARK,
1210};
1211/* - HDMI ------------------------------------------------------------------- */
1212static const unsigned int hdmi_pins[] = {
1213 /* HPD, CEC */
1214 169, 170,
1215};
1216static const unsigned int hdmi_mux[] = {
1217 HDMI_HPD_MARK, HDMI_CEC_MARK,
1218};
1219/* - INTC ------------------------------------------------------------------- */
1220IRQC_PINS_MUX(0, 6, 162);
1221IRQC_PIN_MUX(1, 12);
1222IRQC_PINS_MUX(2, 4, 5);
1223IRQC_PINS_MUX(3, 8, 16);
1224IRQC_PINS_MUX(4, 17, 163);
1225IRQC_PIN_MUX(5, 18);
1226IRQC_PINS_MUX(6, 39, 164);
1227IRQC_PINS_MUX(7, 40, 167);
1228IRQC_PINS_MUX(8, 41, 168);
1229IRQC_PINS_MUX(9, 42, 169);
1230IRQC_PIN_MUX(10, 65);
1231IRQC_PIN_MUX(11, 67);
1232IRQC_PINS_MUX(12, 80, 137);
1233IRQC_PINS_MUX(13, 81, 145);
1234IRQC_PINS_MUX(14, 82, 146);
1235IRQC_PINS_MUX(15, 83, 147);
1236IRQC_PINS_MUX(16, 84, 170);
1237IRQC_PIN_MUX(17, 85);
1238IRQC_PIN_MUX(18, 86);
1239IRQC_PIN_MUX(19, 87);
1240IRQC_PIN_MUX(20, 92);
1241IRQC_PIN_MUX(21, 93);
1242IRQC_PIN_MUX(22, 94);
1243IRQC_PIN_MUX(23, 95);
1244IRQC_PIN_MUX(24, 112);
1245IRQC_PIN_MUX(25, 119);
1246IRQC_PINS_MUX(26, 121, 172);
1247IRQC_PINS_MUX(27, 122, 180);
1248IRQC_PINS_MUX(28, 123, 181);
1249IRQC_PINS_MUX(29, 129, 182);
1250IRQC_PINS_MUX(30, 130, 183);
1251IRQC_PINS_MUX(31, 138, 184);
1252/* - KEYSC ------------------------------------------------------------------ */
1253static const unsigned int keysc_in04_0_pins[] = {
1254 /* KEYIN[0:4] */
1255 136, 135, 134, 133, 132,
1256};
1257static const unsigned int keysc_in04_0_mux[] = {
1258 KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
1259 KEYIN4_MARK,
1260};
1261static const unsigned int keysc_in04_1_pins[] = {
1262 /* KEYIN[0:4] */
1263 121, 122, 123, 124, 132,
1264};
1265static const unsigned int keysc_in04_1_mux[] = {
1266 KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
1267 KEYIN4_MARK,
1268};
1269static const unsigned int keysc_in5_pins[] = {
1270 /* KEYIN5 */
1271 131,
1272};
1273static const unsigned int keysc_in5_mux[] = {
1274 KEYIN5_MARK,
1275};
1276static const unsigned int keysc_in6_pins[] = {
1277 /* KEYIN6 */
1278 130,
1279};
1280static const unsigned int keysc_in6_mux[] = {
1281 KEYIN6_MARK,
1282};
1283static const unsigned int keysc_in7_pins[] = {
1284 /* KEYIN7 */
1285 129,
1286};
1287static const unsigned int keysc_in7_mux[] = {
1288 KEYIN7_MARK,
1289};
1290static const unsigned int keysc_out4_pins[] = {
1291 /* KEYOUT[0:3] */
1292 128, 127, 126, 125,
1293};
1294static const unsigned int keysc_out4_mux[] = {
1295 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1296};
1297static const unsigned int keysc_out5_pins[] = {
1298 /* KEYOUT[0:4] */
1299 128, 127, 126, 125, 124,
1300};
1301static const unsigned int keysc_out5_mux[] = {
1302 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1303 KEYOUT4_MARK,
1304};
1305static const unsigned int keysc_out6_pins[] = {
1306 /* KEYOUT[0:5] */
1307 128, 127, 126, 125, 124, 123,
1308};
1309static const unsigned int keysc_out6_mux[] = {
1310 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1311 KEYOUT4_MARK, KEYOUT5_MARK,
1312};
1313static const unsigned int keysc_out8_pins[] = {
1314 /* KEYOUT[0:7] */
1315 128, 127, 126, 125, 124, 123, 122, 121,
1316};
1317static const unsigned int keysc_out8_mux[] = {
1318 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1319 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
1320};
1321/* - LCD -------------------------------------------------------------------- */
1322static const unsigned int lcd_data8_pins[] = {
1323 /* D[0:7] */
1324 121, 122, 123, 124, 125, 126, 127, 128,
1325};
1326static const unsigned int lcd_data8_mux[] = {
1327 /* LCDC */
1328 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1329 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1330};
1331static const unsigned int lcd_data9_pins[] = {
1332 /* D[0:8] */
1333 121, 122, 123, 124, 125, 126, 127, 128,
1334 129,
1335 137, 138, 139, 140, 141, 142, 143, 144,
1336};
1337static const unsigned int lcd_data9_mux[] = {
1338 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1339 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1340 LCDD8_MARK,
1341};
1342static const unsigned int lcd_data12_pins[] = {
1343 /* D[0:11] */
1344 121, 122, 123, 124, 125, 126, 127, 128,
1345 129, 130, 131, 132,
1346};
1347static const unsigned int lcd_data12_mux[] = {
1348 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1349 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1350 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1351};
1352static const unsigned int lcd_data16_pins[] = {
1353 /* D[0:15] */
1354 121, 122, 123, 124, 125, 126, 127, 128,
1355 129, 130, 131, 132, 133, 134, 135, 136,
1356};
1357static const unsigned int lcd_data16_mux[] = {
1358 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1359 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1360 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1361 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1362};
1363static const unsigned int lcd_data18_pins[] = {
1364 /* D[0:17] */
1365 121, 122, 123, 124, 125, 126, 127, 128,
1366 129, 130, 131, 132, 133, 134, 135, 136,
1367 137, 138,
1368};
1369static const unsigned int lcd_data18_mux[] = {
1370 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1371 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1372 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1373 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1374 LCDD16_MARK, LCDD17_MARK,
1375};
1376static const unsigned int lcd_data24_pins[] = {
1377 /* D[0:23] */
1378 121, 122, 123, 124, 125, 126, 127, 128,
1379 129, 130, 131, 132, 133, 134, 135, 136,
1380 137, 138, 139, 140, 141, 142, 143, 144,
1381};
1382static const unsigned int lcd_data24_mux[] = {
1383 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1384 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1385 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1386 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1387 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1388 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
1389};
1390static const unsigned int lcd_display_pins[] = {
1391 /* DON */
1392 151,
1393};
1394static const unsigned int lcd_display_mux[] = {
1395 LCDDON_MARK,
1396};
1397static const unsigned int lcd_lclk_pins[] = {
1398 /* LCLK */
1399 150,
1400};
1401static const unsigned int lcd_lclk_mux[] = {
1402 LCDLCLK_MARK,
1403};
1404static const unsigned int lcd_sync_pins[] = {
1405 /* VSYN, HSYN, DCK, DISP */
1406 146, 145, 147, 149,
1407};
1408static const unsigned int lcd_sync_mux[] = {
1409 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
1410};
1411static const unsigned int lcd_sys_pins[] = {
1412 /* CS, WR, RD, RS */
1413 145, 147, 148, 149,
1414};
1415static const unsigned int lcd_sys_mux[] = {
1416 LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
1417};
936/* - MMCIF ------------------------------------------------------------------ */ 1418/* - MMCIF ------------------------------------------------------------------ */
937static const unsigned int mmc0_data1_0_pins[] = { 1419static const unsigned int mmc0_data1_0_pins[] = {
938 /* D[0] */ 1420 /* D[0] */
@@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
993static const unsigned int mmc0_ctrl_1_mux[] = { 1475static const unsigned int mmc0_ctrl_1_mux[] = {
994 MMCCMD1_MARK, MMCCLK1_MARK, 1476 MMCCMD1_MARK, MMCCLK1_MARK,
995}; 1477};
1478/* - SCIFA0 ----------------------------------------------------------------- */
1479static const unsigned int scifa0_data_pins[] = {
1480 /* RXD, TXD */
1481 153, 152,
1482};
1483static const unsigned int scifa0_data_mux[] = {
1484 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1485};
1486static const unsigned int scifa0_clk_pins[] = {
1487 /* SCK */
1488 156,
1489};
1490static const unsigned int scifa0_clk_mux[] = {
1491 SCIFA0_SCK_MARK,
1492};
1493static const unsigned int scifa0_ctrl_pins[] = {
1494 /* RTS, CTS */
1495 157, 158,
1496};
1497static const unsigned int scifa0_ctrl_mux[] = {
1498 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1499};
1500/* - SCIFA1 ----------------------------------------------------------------- */
1501static const unsigned int scifa1_data_pins[] = {
1502 /* RXD, TXD */
1503 155, 154,
1504};
1505static const unsigned int scifa1_data_mux[] = {
1506 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1507};
1508static const unsigned int scifa1_clk_pins[] = {
1509 /* SCK */
1510 159,
1511};
1512static const unsigned int scifa1_clk_mux[] = {
1513 SCIFA1_SCK_MARK,
1514};
1515static const unsigned int scifa1_ctrl_pins[] = {
1516 /* RTS, CTS */
1517 160, 161,
1518};
1519static const unsigned int scifa1_ctrl_mux[] = {
1520 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1521};
1522/* - SCIFA2 ----------------------------------------------------------------- */
1523static const unsigned int scifa2_data_pins[] = {
1524 /* RXD, TXD */
1525 97, 96,
1526};
1527static const unsigned int scifa2_data_mux[] = {
1528 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
1529};
1530static const unsigned int scifa2_clk_pins[] = {
1531 /* SCK */
1532 98,
1533};
1534static const unsigned int scifa2_clk_mux[] = {
1535 SCIFA2_SCK1_MARK,
1536};
1537static const unsigned int scifa2_ctrl_pins[] = {
1538 /* RTS, CTS */
1539 95, 94,
1540};
1541static const unsigned int scifa2_ctrl_mux[] = {
1542 SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
1543};
1544/* - SCIFA3 ----------------------------------------------------------------- */
1545static const unsigned int scifa3_data_pins[] = {
1546 /* RXD, TXD */
1547 144, 143,
1548};
1549static const unsigned int scifa3_data_mux[] = {
1550 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
1551};
1552static const unsigned int scifa3_clk_pins[] = {
1553 /* SCK */
1554 142,
1555};
1556static const unsigned int scifa3_clk_mux[] = {
1557 SCIFA3_SCK_MARK,
1558};
1559static const unsigned int scifa3_ctrl_0_pins[] = {
1560 /* RTS, CTS */
1561 44, 43,
1562};
1563static const unsigned int scifa3_ctrl_0_mux[] = {
1564 SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
1565};
1566static const unsigned int scifa3_ctrl_1_pins[] = {
1567 /* RTS, CTS */
1568 141, 140,
1569};
1570static const unsigned int scifa3_ctrl_1_mux[] = {
1571 SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
1572};
1573/* - SCIFA4 ----------------------------------------------------------------- */
1574static const unsigned int scifa4_data_pins[] = {
1575 /* RXD, TXD */
1576 5, 6,
1577};
1578static const unsigned int scifa4_data_mux[] = {
1579 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
1580};
1581/* - SCIFA5 ----------------------------------------------------------------- */
1582static const unsigned int scifa5_data_pins[] = {
1583 /* RXD, TXD */
1584 8, 12,
1585};
1586static const unsigned int scifa5_data_mux[] = {
1587 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
1588};
1589/* - SCIFB ------------------------------------------------------------------ */
1590static const unsigned int scifb_data_pins[] = {
1591 /* RXD, TXD */
1592 166, 165,
1593};
1594static const unsigned int scifb_data_mux[] = {
1595 SCIFB_RXD_MARK, SCIFB_TXD_MARK,
1596};
1597static const unsigned int scifb_clk_pins[] = {
1598 /* SCK */
1599 162,
1600};
1601static const unsigned int scifb_clk_mux[] = {
1602 SCIFB_SCK_MARK,
1603};
1604static const unsigned int scifb_ctrl_pins[] = {
1605 /* RTS, CTS */
1606 163, 164,
1607};
1608static const unsigned int scifb_ctrl_mux[] = {
1609 SCIFB_RTS_MARK, SCIFB_CTS_MARK,
1610};
996/* - SDHI0 ------------------------------------------------------------------ */ 1611/* - SDHI0 ------------------------------------------------------------------ */
997static const unsigned int sdhi0_data1_pins[] = { 1612static const unsigned int sdhi0_data1_pins[] = {
998 /* D0 */ 1613 /* D0 */
@@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = {
1073static const unsigned int sdhi2_ctrl_mux[] = { 1688static const unsigned int sdhi2_ctrl_mux[] = {
1074 SDHICMD2_MARK, SDHICLK2_MARK, 1689 SDHICMD2_MARK, SDHICLK2_MARK,
1075}; 1690};
1691/* - USB0 ------------------------------------------------------------------- */
1692static const unsigned int usb0_vbus_pins[] = {
1693 /* VBUS */
1694 167,
1695};
1696static const unsigned int usb0_vbus_mux[] = {
1697 VBUS0_0_MARK,
1698};
1699static const unsigned int usb0_otg_id_pins[] = {
1700 /* IDIN */
1701 113,
1702};
1703static const unsigned int usb0_otg_id_mux[] = {
1704 IDIN_0_MARK,
1705};
1706static const unsigned int usb0_otg_ctrl_pins[] = {
1707 /* PWEN, EXTLP, OVCN, OVCN2 */
1708 116, 114, 117, 115,
1709};
1710static const unsigned int usb0_otg_ctrl_mux[] = {
1711 PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
1712};
1713/* - USB1 ------------------------------------------------------------------- */
1714static const unsigned int usb1_vbus_pins[] = {
1715 /* VBUS */
1716 168,
1717};
1718static const unsigned int usb1_vbus_mux[] = {
1719 VBUS0_1_MARK,
1720};
1721static const unsigned int usb1_otg_id_0_pins[] = {
1722 /* IDIN */
1723 113,
1724};
1725static const unsigned int usb1_otg_id_0_mux[] = {
1726 IDIN_1_113_MARK,
1727};
1728static const unsigned int usb1_otg_id_1_pins[] = {
1729 /* IDIN */
1730 18,
1731};
1732static const unsigned int usb1_otg_id_1_mux[] = {
1733 IDIN_1_18_MARK,
1734};
1735static const unsigned int usb1_otg_ctrl_0_pins[] = {
1736 /* PWEN, EXTLP, OVCN, OVCN2 */
1737 115, 116, 114, 117, 113,
1738};
1739static const unsigned int usb1_otg_ctrl_0_mux[] = {
1740 PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
1741};
1742static const unsigned int usb1_otg_ctrl_1_pins[] = {
1743 /* PWEN, EXTLP, OVCN, OVCN2 */
1744 138, 116, 162, 117, 18,
1745};
1746static const unsigned int usb1_otg_ctrl_1_mux[] = {
1747 PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
1748};
1076 1749
1077static const struct sh_pfc_pin_group pinmux_groups[] = { 1750static const struct sh_pfc_pin_group pinmux_groups[] = {
1751 SH_PFC_PIN_GROUP(bsc_data8),
1752 SH_PFC_PIN_GROUP(bsc_data16),
1753 SH_PFC_PIN_GROUP(bsc_cs0),
1754 SH_PFC_PIN_GROUP(bsc_cs2),
1755 SH_PFC_PIN_GROUP(bsc_cs4),
1756 SH_PFC_PIN_GROUP(bsc_cs5a),
1757 SH_PFC_PIN_GROUP(bsc_cs5b),
1758 SH_PFC_PIN_GROUP(bsc_cs6a),
1759 SH_PFC_PIN_GROUP(bsc_rd_we8),
1760 SH_PFC_PIN_GROUP(bsc_rd_we16),
1761 SH_PFC_PIN_GROUP(bsc_bs),
1762 SH_PFC_PIN_GROUP(bsc_rdwr),
1763 SH_PFC_PIN_GROUP(ceu_data_0_7),
1764 SH_PFC_PIN_GROUP(ceu_data_8_15),
1765 SH_PFC_PIN_GROUP(ceu_clk_0),
1766 SH_PFC_PIN_GROUP(ceu_clk_1),
1767 SH_PFC_PIN_GROUP(ceu_clk_2),
1768 SH_PFC_PIN_GROUP(ceu_sync),
1769 SH_PFC_PIN_GROUP(ceu_field),
1770 SH_PFC_PIN_GROUP(flctl_data),
1771 SH_PFC_PIN_GROUP(flctl_ce0),
1772 SH_PFC_PIN_GROUP(flctl_ce1),
1773 SH_PFC_PIN_GROUP(flctl_ctrl),
1774 SH_PFC_PIN_GROUP(fsia_mclk_in),
1775 SH_PFC_PIN_GROUP(fsia_mclk_out),
1776 SH_PFC_PIN_GROUP(fsia_sclk_in),
1777 SH_PFC_PIN_GROUP(fsia_sclk_out),
1778 SH_PFC_PIN_GROUP(fsia_data_in),
1779 SH_PFC_PIN_GROUP(fsia_data_out),
1780 SH_PFC_PIN_GROUP(fsia_spdif_0),
1781 SH_PFC_PIN_GROUP(fsia_spdif_1),
1782 SH_PFC_PIN_GROUP(fsib_mclk_in),
1783 SH_PFC_PIN_GROUP(hdmi),
1784 SH_PFC_PIN_GROUP(intc_irq0_0),
1785 SH_PFC_PIN_GROUP(intc_irq0_1),
1786 SH_PFC_PIN_GROUP(intc_irq1),
1787 SH_PFC_PIN_GROUP(intc_irq2_0),
1788 SH_PFC_PIN_GROUP(intc_irq2_1),
1789 SH_PFC_PIN_GROUP(intc_irq3_0),
1790 SH_PFC_PIN_GROUP(intc_irq3_1),
1791 SH_PFC_PIN_GROUP(intc_irq4_0),
1792 SH_PFC_PIN_GROUP(intc_irq4_1),
1793 SH_PFC_PIN_GROUP(intc_irq5),
1794 SH_PFC_PIN_GROUP(intc_irq6_0),
1795 SH_PFC_PIN_GROUP(intc_irq6_1),
1796 SH_PFC_PIN_GROUP(intc_irq7_0),
1797 SH_PFC_PIN_GROUP(intc_irq7_1),
1798 SH_PFC_PIN_GROUP(intc_irq8_0),
1799 SH_PFC_PIN_GROUP(intc_irq8_1),
1800 SH_PFC_PIN_GROUP(intc_irq9_0),
1801 SH_PFC_PIN_GROUP(intc_irq9_1),
1802 SH_PFC_PIN_GROUP(intc_irq10),
1803 SH_PFC_PIN_GROUP(intc_irq11),
1804 SH_PFC_PIN_GROUP(intc_irq12_0),
1805 SH_PFC_PIN_GROUP(intc_irq12_1),
1806 SH_PFC_PIN_GROUP(intc_irq13_0),
1807 SH_PFC_PIN_GROUP(intc_irq13_1),
1808 SH_PFC_PIN_GROUP(intc_irq14_0),
1809 SH_PFC_PIN_GROUP(intc_irq14_1),
1810 SH_PFC_PIN_GROUP(intc_irq15_0),
1811 SH_PFC_PIN_GROUP(intc_irq15_1),
1812 SH_PFC_PIN_GROUP(intc_irq16_0),
1813 SH_PFC_PIN_GROUP(intc_irq16_1),
1814 SH_PFC_PIN_GROUP(intc_irq17),
1815 SH_PFC_PIN_GROUP(intc_irq18),
1816 SH_PFC_PIN_GROUP(intc_irq19),
1817 SH_PFC_PIN_GROUP(intc_irq20),
1818 SH_PFC_PIN_GROUP(intc_irq21),
1819 SH_PFC_PIN_GROUP(intc_irq22),
1820 SH_PFC_PIN_GROUP(intc_irq23),
1821 SH_PFC_PIN_GROUP(intc_irq24),
1822 SH_PFC_PIN_GROUP(intc_irq25),
1823 SH_PFC_PIN_GROUP(intc_irq26_0),
1824 SH_PFC_PIN_GROUP(intc_irq26_1),
1825 SH_PFC_PIN_GROUP(intc_irq27_0),
1826 SH_PFC_PIN_GROUP(intc_irq27_1),
1827 SH_PFC_PIN_GROUP(intc_irq28_0),
1828 SH_PFC_PIN_GROUP(intc_irq28_1),
1829 SH_PFC_PIN_GROUP(intc_irq29_0),
1830 SH_PFC_PIN_GROUP(intc_irq29_1),
1831 SH_PFC_PIN_GROUP(intc_irq30_0),
1832 SH_PFC_PIN_GROUP(intc_irq30_1),
1833 SH_PFC_PIN_GROUP(intc_irq31_0),
1834 SH_PFC_PIN_GROUP(intc_irq31_1),
1835 SH_PFC_PIN_GROUP(keysc_in04_0),
1836 SH_PFC_PIN_GROUP(keysc_in04_1),
1837 SH_PFC_PIN_GROUP(keysc_in5),
1838 SH_PFC_PIN_GROUP(keysc_in6),
1839 SH_PFC_PIN_GROUP(keysc_in7),
1840 SH_PFC_PIN_GROUP(keysc_out4),
1841 SH_PFC_PIN_GROUP(keysc_out5),
1842 SH_PFC_PIN_GROUP(keysc_out6),
1843 SH_PFC_PIN_GROUP(keysc_out8),
1844 SH_PFC_PIN_GROUP(lcd_data8),
1845 SH_PFC_PIN_GROUP(lcd_data9),
1846 SH_PFC_PIN_GROUP(lcd_data12),
1847 SH_PFC_PIN_GROUP(lcd_data16),
1848 SH_PFC_PIN_GROUP(lcd_data18),
1849 SH_PFC_PIN_GROUP(lcd_data24),
1850 SH_PFC_PIN_GROUP(lcd_display),
1851 SH_PFC_PIN_GROUP(lcd_lclk),
1852 SH_PFC_PIN_GROUP(lcd_sync),
1853 SH_PFC_PIN_GROUP(lcd_sys),
1078 SH_PFC_PIN_GROUP(mmc0_data1_0), 1854 SH_PFC_PIN_GROUP(mmc0_data1_0),
1079 SH_PFC_PIN_GROUP(mmc0_data4_0), 1855 SH_PFC_PIN_GROUP(mmc0_data4_0),
1080 SH_PFC_PIN_GROUP(mmc0_data8_0), 1856 SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1083 SH_PFC_PIN_GROUP(mmc0_data4_1), 1859 SH_PFC_PIN_GROUP(mmc0_data4_1),
1084 SH_PFC_PIN_GROUP(mmc0_data8_1), 1860 SH_PFC_PIN_GROUP(mmc0_data8_1),
1085 SH_PFC_PIN_GROUP(mmc0_ctrl_1), 1861 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1862 SH_PFC_PIN_GROUP(scifa0_data),
1863 SH_PFC_PIN_GROUP(scifa0_clk),
1864 SH_PFC_PIN_GROUP(scifa0_ctrl),
1865 SH_PFC_PIN_GROUP(scifa1_data),
1866 SH_PFC_PIN_GROUP(scifa1_clk),
1867 SH_PFC_PIN_GROUP(scifa1_ctrl),
1868 SH_PFC_PIN_GROUP(scifa2_data),
1869 SH_PFC_PIN_GROUP(scifa2_clk),
1870 SH_PFC_PIN_GROUP(scifa2_ctrl),
1871 SH_PFC_PIN_GROUP(scifa3_data),
1872 SH_PFC_PIN_GROUP(scifa3_clk),
1873 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
1874 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
1875 SH_PFC_PIN_GROUP(scifa4_data),
1876 SH_PFC_PIN_GROUP(scifa5_data),
1877 SH_PFC_PIN_GROUP(scifb_data),
1878 SH_PFC_PIN_GROUP(scifb_clk),
1879 SH_PFC_PIN_GROUP(scifb_ctrl),
1086 SH_PFC_PIN_GROUP(sdhi0_data1), 1880 SH_PFC_PIN_GROUP(sdhi0_data1),
1087 SH_PFC_PIN_GROUP(sdhi0_data4), 1881 SH_PFC_PIN_GROUP(sdhi0_data4),
1088 SH_PFC_PIN_GROUP(sdhi0_ctrl), 1882 SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1094 SH_PFC_PIN_GROUP(sdhi2_data1), 1888 SH_PFC_PIN_GROUP(sdhi2_data1),
1095 SH_PFC_PIN_GROUP(sdhi2_data4), 1889 SH_PFC_PIN_GROUP(sdhi2_data4),
1096 SH_PFC_PIN_GROUP(sdhi2_ctrl), 1890 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1891 SH_PFC_PIN_GROUP(usb0_vbus),
1892 SH_PFC_PIN_GROUP(usb0_otg_id),
1893 SH_PFC_PIN_GROUP(usb0_otg_ctrl),
1894 SH_PFC_PIN_GROUP(usb1_vbus),
1895 SH_PFC_PIN_GROUP(usb1_otg_id_0),
1896 SH_PFC_PIN_GROUP(usb1_otg_id_1),
1897 SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
1898 SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
1899};
1900
1901static const char * const bsc_groups[] = {
1902 "bsc_data8",
1903 "bsc_data16",
1904 "bsc_cs0",
1905 "bsc_cs2",
1906 "bsc_cs4",
1907 "bsc_cs5a",
1908 "bsc_cs5b",
1909 "bsc_cs6a",
1910 "bsc_rd_we8",
1911 "bsc_rd_we16",
1912 "bsc_bs",
1913 "bsc_rdwr",
1914};
1915
1916static const char * const ceu_groups[] = {
1917 "ceu_data_0_7",
1918 "ceu_data_8_15",
1919 "ceu_clk_0",
1920 "ceu_clk_1",
1921 "ceu_clk_2",
1922 "ceu_sync",
1923 "ceu_field",
1924};
1925
1926static const char * const flctl_groups[] = {
1927 "flctl_data",
1928 "flctl_ce0",
1929 "flctl_ce1",
1930 "flctl_ctrl",
1931};
1932
1933static const char * const fsia_groups[] = {
1934 "fsia_mclk_in",
1935 "fsia_mclk_out",
1936 "fsia_sclk_in",
1937 "fsia_sclk_out",
1938 "fsia_data_in",
1939 "fsia_data_out",
1940 "fsia_spdif_0",
1941 "fsia_spdif_1",
1942};
1943
1944static const char * const fsib_groups[] = {
1945 "fsib_mclk_in",
1946};
1947
1948static const char * const hdmi_groups[] = {
1949 "hdmi",
1950};
1951
1952static const char * const intc_groups[] = {
1953 "intc_irq0_0",
1954 "intc_irq0_1",
1955 "intc_irq1",
1956 "intc_irq2_0",
1957 "intc_irq2_1",
1958 "intc_irq3_0",
1959 "intc_irq3_1",
1960 "intc_irq4_0",
1961 "intc_irq4_1",
1962 "intc_irq5",
1963 "intc_irq6_0",
1964 "intc_irq6_1",
1965 "intc_irq7_0",
1966 "intc_irq7_1",
1967 "intc_irq8_0",
1968 "intc_irq8_1",
1969 "intc_irq9_0",
1970 "intc_irq9_1",
1971 "intc_irq10",
1972 "intc_irq11",
1973 "intc_irq12_0",
1974 "intc_irq12_1",
1975 "intc_irq13_0",
1976 "intc_irq13_1",
1977 "intc_irq14_0",
1978 "intc_irq14_1",
1979 "intc_irq15_0",
1980 "intc_irq15_1",
1981 "intc_irq16_0",
1982 "intc_irq16_1",
1983 "intc_irq17",
1984 "intc_irq18",
1985 "intc_irq19",
1986 "intc_irq20",
1987 "intc_irq21",
1988 "intc_irq22",
1989 "intc_irq23",
1990 "intc_irq24",
1991 "intc_irq25",
1992 "intc_irq26_0",
1993 "intc_irq26_1",
1994 "intc_irq27_0",
1995 "intc_irq27_1",
1996 "intc_irq28_0",
1997 "intc_irq28_1",
1998 "intc_irq29_0",
1999 "intc_irq29_1",
2000 "intc_irq30_0",
2001 "intc_irq30_1",
2002 "intc_irq31_0",
2003 "intc_irq31_1",
2004};
2005
2006static const char * const keysc_groups[] = {
2007 "keysc_in04_0",
2008 "keysc_in04_1",
2009 "keysc_in5",
2010 "keysc_in6",
2011 "keysc_in7",
2012 "keysc_out4",
2013 "keysc_out5",
2014 "keysc_out6",
2015 "keysc_out8",
2016};
2017
2018static const char * const lcd_groups[] = {
2019 "lcd_data8",
2020 "lcd_data9",
2021 "lcd_data12",
2022 "lcd_data16",
2023 "lcd_data18",
2024 "lcd_data24",
2025 "lcd_display",
2026 "lcd_lclk",
2027 "lcd_sync",
2028 "lcd_sys",
1097}; 2029};
1098 2030
1099static const char * const mmc0_groups[] = { 2031static const char * const mmc0_groups[] = {
@@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = {
1107 "mmc0_ctrl_1", 2039 "mmc0_ctrl_1",
1108}; 2040};
1109 2041
2042static const char * const scifa0_groups[] = {
2043 "scifa0_data",
2044 "scifa0_clk",
2045 "scifa0_ctrl",
2046};
2047
2048static const char * const scifa1_groups[] = {
2049 "scifa1_data",
2050 "scifa1_clk",
2051 "scifa1_ctrl",
2052};
2053
2054static const char * const scifa2_groups[] = {
2055 "scifa2_data",
2056 "scifa2_clk",
2057 "scifa2_ctrl",
2058};
2059
2060static const char * const scifa3_groups[] = {
2061 "scifa3_data",
2062 "scifa3_clk",
2063 "scifa3_ctrl_0",
2064 "scifa3_ctrl_1",
2065};
2066
2067static const char * const scifa4_groups[] = {
2068 "scifa4_data",
2069};
2070
2071static const char * const scifa5_groups[] = {
2072 "scifa5_data",
2073};
2074
2075static const char * const scifb_groups[] = {
2076 "scifb_data",
2077 "scifb_clk",
2078 "scifb_ctrl",
2079};
2080
1110static const char * const sdhi0_groups[] = { 2081static const char * const sdhi0_groups[] = {
1111 "sdhi0_data1", 2082 "sdhi0_data1",
1112 "sdhi0_data4", 2083 "sdhi0_data4",
@@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = {
1127 "sdhi2_ctrl", 2098 "sdhi2_ctrl",
1128}; 2099};
1129 2100
2101static const char * const usb0_groups[] = {
2102 "usb0_vbus",
2103 "usb0_otg_id",
2104 "usb0_otg_ctrl",
2105};
2106
2107static const char * const usb1_groups[] = {
2108 "usb1_vbus",
2109 "usb1_otg_id_0",
2110 "usb1_otg_id_1",
2111 "usb1_otg_ctrl_0",
2112 "usb1_otg_ctrl_1",
2113};
2114
1130static const struct sh_pfc_function pinmux_functions[] = { 2115static const struct sh_pfc_function pinmux_functions[] = {
2116 SH_PFC_FUNCTION(bsc),
2117 SH_PFC_FUNCTION(ceu),
2118 SH_PFC_FUNCTION(flctl),
2119 SH_PFC_FUNCTION(fsia),
2120 SH_PFC_FUNCTION(fsib),
2121 SH_PFC_FUNCTION(hdmi),
2122 SH_PFC_FUNCTION(intc),
2123 SH_PFC_FUNCTION(keysc),
2124 SH_PFC_FUNCTION(lcd),
1131 SH_PFC_FUNCTION(mmc0), 2125 SH_PFC_FUNCTION(mmc0),
2126 SH_PFC_FUNCTION(scifa0),
2127 SH_PFC_FUNCTION(scifa1),
2128 SH_PFC_FUNCTION(scifa2),
2129 SH_PFC_FUNCTION(scifa3),
2130 SH_PFC_FUNCTION(scifa4),
2131 SH_PFC_FUNCTION(scifa5),
2132 SH_PFC_FUNCTION(scifb),
1132 SH_PFC_FUNCTION(sdhi0), 2133 SH_PFC_FUNCTION(sdhi0),
1133 SH_PFC_FUNCTION(sdhi1), 2134 SH_PFC_FUNCTION(sdhi1),
1134 SH_PFC_FUNCTION(sdhi2), 2135 SH_PFC_FUNCTION(sdhi2),
2136 SH_PFC_FUNCTION(usb0),
2137 SH_PFC_FUNCTION(usb1),
1135}; 2138};
1136 2139
1137#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 2140#undef PORTCR
1138 2141#define PORTCR(nr, reg) \
1139static const struct pinmux_func pinmux_func_gpios[] = { 2142 { \
1140 /* IRQ */ 2143 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1141 GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), 2144 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
1142 GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), 2145 PORT##nr##_FN0, PORT##nr##_FN1, \
1143 GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), 2146 PORT##nr##_FN2, PORT##nr##_FN3, \
1144 GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), 2147 PORT##nr##_FN4, PORT##nr##_FN5, \
1145 GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), 2148 PORT##nr##_FN6, PORT##nr##_FN7 } \
1146 GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), 2149 }
1147 GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80),
1148 GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145),
1149 GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83),
1150 GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170),
1151 GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19),
1152 GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22),
1153 GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25),
1154 GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122),
1155 GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181),
1156 GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130),
1157 GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184),
1158
1159 /* MSIOF0 */
1160 GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD),
1161 GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0),
1162 GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2),
1163 GPIO_FN(MSIOF0_TXD),
1164
1165 /* MSIOF1 */
1166 GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88),
1167 GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89),
1168 GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90),
1169 GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91),
1170 GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92),
1171 GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93),
1172 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1173 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1174
1175 /* MSIOF2 */
1176 GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0),
1177 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2),
1178 GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD),
1179 GPIO_FN(MSIOF2_TXD),
1180
1181 /* BBIF1 */
1182 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK),
1183 GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
1184 GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N),
1185
1186 /* BBIF2 */
1187 GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1),
1188 GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD),
1189
1190 /* FSI */
1191 GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR),
1192 GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC),
1193 GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD),
1194 GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15),
1195
1196 /* FMSI */
1197 GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR),
1198 GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD),
1199 GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT),
1200 GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK),
1201
1202 /* SCIFA0 */
1203 GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK),
1204 GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS),
1205
1206 /* SCIFA1 */
1207 GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK),
1208 GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS),
1209
1210 /* SCIFA2 */
1211 GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1),
1212 GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1),
1213
1214 /* SCIFA3 */
1215 GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140),
1216 GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141),
1217 GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD),
1218 GPIO_FN(SCIFA3_RXD),
1219
1220 /* SCIFA4 */
1221 GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD),
1222
1223 /* SCIFA5 */
1224 GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD),
1225
1226 /* SCIFB */
1227 GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS),
1228 GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD),
1229
1230 /* CEU */
1231 GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2),
1232 GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
1233 GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1),
1234 GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4),
1235 GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7),
1236 GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10),
1237 GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13),
1238 GPIO_FN(VIO_D14), GPIO_FN(VIO_D15),
1239
1240 /* USB0 */
1241 GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0),
1242 GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0),
1243
1244 /* USB1 */
1245 GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113),
1246 GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162),
1247 GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138),
1248 GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1),
1249 GPIO_FN(VBUS0_1),
1250
1251 /* GPIO */
1252 GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1),
1253
1254 /* BSC */
1255 GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO),
1256 GPIO_FN(WAIT), GPIO_FN(RDWR),
1257
1258 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2),
1259 GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7),
1260 GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10),
1261 GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
1262 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16),
1263 GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19),
1264 GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22),
1265 GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
1266 GPIO_FN(A26),
1267
1268 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
1269 GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A),
1270
1271 /* BSC/FLCTL */
1272 GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE),
1273 GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1),
1274 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4),
1275 GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7),
1276 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10),
1277 GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
1278 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
1279
1280 /* SPU2 */
1281 GPIO_FN(VINT_I),
1282
1283 /* FLCTL */
1284 GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB),
1285
1286 /* HSI */
1287 GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY),
1288 GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA),
1289 GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE),
1290
1291 /* MFI */
1292 GPIO_FN(MFIv6),
1293 GPIO_FN(MFIv4),
1294
1295 GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0),
1296 GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1),
1297 GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE),
1298 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT),
1299
1300 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1301 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1302 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1303 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1304 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1305 GPIO_FN(MEMC_AD15),
1306
1307 /* SIM */
1308 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D),
1309
1310 /* TPU */
1311 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93),
1312 GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3),
1313
1314 /* I2C2 */
1315 GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2),
1316
1317 /* I2C3(1) */
1318 GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3),
1319
1320 /* I2C3(2) */
1321 GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S),
1322
1323 /* I2C4(2) */
1324 GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4),
1325
1326 /* I2C4(2) */
1327 GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S),
1328
1329 /* KEYSC */
1330 GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136),
1331 GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135),
1332 GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134),
1333 GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133),
1334 GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5),
1335 GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6),
1336 GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7),
1337
1338 /* LCDC */
1339 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
1340 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD),
1341 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
1342 GPIO_FN(LCDDON),
1343
1344 GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2),
1345 GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5),
1346 GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8),
1347 GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11),
1348 GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14),
1349 GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17),
1350 GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20),
1351 GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23),
1352
1353 GPIO_FN(LCDC0_SELECT),
1354 GPIO_FN(LCDC1_SELECT),
1355
1356 /* IRDA */
1357 GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
1358 GPIO_FN(IROUT_139), GPIO_FN(IROUT_140),
1359
1360 /* TSIF1 */
1361 GPIO_FN(TS0_1SELECT),
1362 GPIO_FN(TS0_2SELECT),
1363 GPIO_FN(TS1_1SELECT),
1364 GPIO_FN(TS1_2SELECT),
1365
1366 GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1),
1367 GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1),
1368
1369 /* TSIF2 */
1370 GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2),
1371 GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2),
1372
1373 /* HDMI */
1374 GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
1375
1376 /* SDENC */
1377 GPIO_FN(SDENC_CPG),
1378 GPIO_FN(SDENC_DV_CLKI),
1379};
1380 2150
1381static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2151static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1382 PORTCR(0, 0xE6051000), /* PORT0CR */ 2152 PORTCR(0, 0xE6051000), /* PORT0CR */
@@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
1776#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) 2546#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
1777#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) 2547#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
1778static const struct pinmux_irq pinmux_irqs[] = { 2548static const struct pinmux_irq pinmux_irqs[] = {
1779 PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), 2549 PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
1780 PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), 2550 PINMUX_IRQ(EXT_IRQ16L(1), 12),
1781 PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), 2551 PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
1782 PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), 2552 PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
1783 PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), 2553 PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
1784 PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), 2554 PINMUX_IRQ(EXT_IRQ16L(5), 18),
1785 PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), 2555 PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
1786 PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), 2556 PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
1787 PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), 2557 PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
1788 PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), 2558 PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
1789 PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), 2559 PINMUX_IRQ(EXT_IRQ16L(10), 65),
1790 PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), 2560 PINMUX_IRQ(EXT_IRQ16L(11), 67),
1791 PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), 2561 PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
1792 PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), 2562 PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
1793 PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), 2563 PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
1794 PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), 2564 PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
1795 PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), 2565 PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
1796 PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), 2566 PINMUX_IRQ(EXT_IRQ16H(17), 85),
1797 PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), 2567 PINMUX_IRQ(EXT_IRQ16H(18), 86),
1798 PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), 2568 PINMUX_IRQ(EXT_IRQ16H(19), 87),
1799 PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), 2569 PINMUX_IRQ(EXT_IRQ16H(20), 92),
1800 PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), 2570 PINMUX_IRQ(EXT_IRQ16H(21), 93),
1801 PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), 2571 PINMUX_IRQ(EXT_IRQ16H(22), 94),
1802 PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), 2572 PINMUX_IRQ(EXT_IRQ16H(23), 95),
1803 PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), 2573 PINMUX_IRQ(EXT_IRQ16H(24), 112),
1804 PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), 2574 PINMUX_IRQ(EXT_IRQ16H(25), 119),
1805 PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), 2575 PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
1806 PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), 2576 PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
1807 PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), 2577 PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
1808 PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), 2578 PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
1809 PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), 2579 PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
1810 PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), 2580 PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
2581};
2582
2583#define PORTnCR_PULMD_OFF (0 << 6)
2584#define PORTnCR_PULMD_DOWN (2 << 6)
2585#define PORTnCR_PULMD_UP (3 << 6)
2586#define PORTnCR_PULMD_MASK (3 << 6)
2587
2588struct sh7372_portcr_group {
2589 unsigned int end_pin;
2590 unsigned int offset;
2591};
2592
2593static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
2594 { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 },
2595 { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
2596};
2597
2598static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2599{
2600 unsigned int i;
2601
2602 for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
2603 const struct sh7372_portcr_group *group =
2604 &sh7372_portcr_offsets[i];
2605
2606 if (i <= group->end_pin)
2607 return pfc->window->virt + group->offset + pin;
2608 }
2609
2610 return NULL;
2611}
2612
2613static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
2614{
2615 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2616 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
2617
2618 switch (value) {
2619 case PORTnCR_PULMD_UP:
2620 return PIN_CONFIG_BIAS_PULL_UP;
2621 case PORTnCR_PULMD_DOWN:
2622 return PIN_CONFIG_BIAS_PULL_DOWN;
2623 case PORTnCR_PULMD_OFF:
2624 default:
2625 return PIN_CONFIG_BIAS_DISABLE;
2626 }
2627}
2628
2629static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2630 unsigned int bias)
2631{
2632 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2633 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
2634
2635 switch (bias) {
2636 case PIN_CONFIG_BIAS_PULL_UP:
2637 value |= PORTnCR_PULMD_UP;
2638 break;
2639 case PIN_CONFIG_BIAS_PULL_DOWN:
2640 value |= PORTnCR_PULMD_DOWN;
2641 break;
2642 }
2643
2644 iowrite8(value, addr);
2645}
2646
2647static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
2648 .get_bias = sh7372_pinmux_get_bias,
2649 .set_bias = sh7372_pinmux_set_bias,
1811}; 2650};
1812 2651
1813const struct sh_pfc_soc_info sh7372_pinmux_info = { 2652const struct sh_pfc_soc_info sh7372_pinmux_info = {
1814 .name = "sh7372_pfc", 2653 .name = "sh7372_pfc",
2654 .ops = &sh7372_pinmux_ops,
2655
1815 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2656 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1816 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1817 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1818 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2657 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1819 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2658 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1820 2659
@@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
1825 .functions = pinmux_functions, 2664 .functions = pinmux_functions,
1826 .nr_functions = ARRAY_SIZE(pinmux_functions), 2665 .nr_functions = ARRAY_SIZE(pinmux_functions),
1827 2666
1828 .func_gpios = pinmux_func_gpios,
1829 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1830
1831 .cfg_regs = pinmux_config_regs, 2667 .cfg_regs = pinmux_config_regs,
1832 .data_regs = pinmux_data_regs, 2668 .data_regs = pinmux_data_regs,
1833 2669
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 587f7772abf2..7956df58d751 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -20,9 +20,12 @@
20 */ 20 */
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/module.h>
23#include <linux/pinctrl/pinconf-generic.h> 24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/regulator/driver.h>
26#include <linux/regulator/machine.h>
27#include <linux/slab.h>
24 28
25#include <mach/sh73a0.h>
26#include <mach/irqs.h> 29#include <mach/irqs.h>
27 30
28#include "core.h" 31#include "core.h"
@@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
2538static const unsigned int sdhi2_ctrl_mux[] = { 2541static const unsigned int sdhi2_ctrl_mux[] = {
2539 SDHICMD2_MARK, SDHICLK2_MARK, 2542 SDHICMD2_MARK, SDHICLK2_MARK,
2540}; 2543};
2544/* - TPU0 ------------------------------------------------------------------- */
2545static const unsigned int tpu0_to0_pins[] = {
2546 /* TO */
2547 55,
2548};
2549static const unsigned int tpu0_to0_mux[] = {
2550 TPU0TO0_MARK,
2551};
2552static const unsigned int tpu0_to1_pins[] = {
2553 /* TO */
2554 59,
2555};
2556static const unsigned int tpu0_to1_mux[] = {
2557 TPU0TO1_MARK,
2558};
2559static const unsigned int tpu0_to2_pins[] = {
2560 /* TO */
2561 140,
2562};
2563static const unsigned int tpu0_to2_mux[] = {
2564 TPU0TO2_MARK,
2565};
2566static const unsigned int tpu0_to3_pins[] = {
2567 /* TO */
2568 141,
2569};
2570static const unsigned int tpu0_to3_mux[] = {
2571 TPU0TO3_MARK,
2572};
2573/* - TPU1 ------------------------------------------------------------------- */
2574static const unsigned int tpu1_to0_pins[] = {
2575 /* TO */
2576 246,
2577};
2578static const unsigned int tpu1_to0_mux[] = {
2579 TPU1TO0_MARK,
2580};
2581static const unsigned int tpu1_to1_0_pins[] = {
2582 /* TO */
2583 28,
2584};
2585static const unsigned int tpu1_to1_0_mux[] = {
2586 PORT28_TPU1TO1_MARK,
2587};
2588static const unsigned int tpu1_to1_1_pins[] = {
2589 /* TO */
2590 29,
2591};
2592static const unsigned int tpu1_to1_1_mux[] = {
2593 PORT29_TPU1TO1_MARK,
2594};
2595static const unsigned int tpu1_to2_pins[] = {
2596 /* TO */
2597 153,
2598};
2599static const unsigned int tpu1_to2_mux[] = {
2600 TPU1TO2_MARK,
2601};
2602static const unsigned int tpu1_to3_pins[] = {
2603 /* TO */
2604 145,
2605};
2606static const unsigned int tpu1_to3_mux[] = {
2607 TPU1TO3_MARK,
2608};
2609/* - TPU2 ------------------------------------------------------------------- */
2610static const unsigned int tpu2_to0_pins[] = {
2611 /* TO */
2612 248,
2613};
2614static const unsigned int tpu2_to0_mux[] = {
2615 TPU2TO0_MARK,
2616};
2617static const unsigned int tpu2_to1_pins[] = {
2618 /* TO */
2619 197,
2620};
2621static const unsigned int tpu2_to1_mux[] = {
2622 TPU2TO1_MARK,
2623};
2624static const unsigned int tpu2_to2_pins[] = {
2625 /* TO */
2626 50,
2627};
2628static const unsigned int tpu2_to2_mux[] = {
2629 TPU2TO2_MARK,
2630};
2631static const unsigned int tpu2_to3_pins[] = {
2632 /* TO */
2633 51,
2634};
2635static const unsigned int tpu2_to3_mux[] = {
2636 TPU2TO3_MARK,
2637};
2638/* - TPU3 ------------------------------------------------------------------- */
2639static const unsigned int tpu3_to0_pins[] = {
2640 /* TO */
2641 163,
2642};
2643static const unsigned int tpu3_to0_mux[] = {
2644 TPU3TO0_MARK,
2645};
2646static const unsigned int tpu3_to1_pins[] = {
2647 /* TO */
2648 247,
2649};
2650static const unsigned int tpu3_to1_mux[] = {
2651 TPU3TO1_MARK,
2652};
2653static const unsigned int tpu3_to2_pins[] = {
2654 /* TO */
2655 54,
2656};
2657static const unsigned int tpu3_to2_mux[] = {
2658 TPU3TO2_MARK,
2659};
2660static const unsigned int tpu3_to3_pins[] = {
2661 /* TO */
2662 53,
2663};
2664static const unsigned int tpu3_to3_mux[] = {
2665 TPU3TO3_MARK,
2666};
2667/* - TPU4 ------------------------------------------------------------------- */
2668static const unsigned int tpu4_to0_pins[] = {
2669 /* TO */
2670 241,
2671};
2672static const unsigned int tpu4_to0_mux[] = {
2673 TPU4TO0_MARK,
2674};
2675static const unsigned int tpu4_to1_pins[] = {
2676 /* TO */
2677 199,
2678};
2679static const unsigned int tpu4_to1_mux[] = {
2680 TPU4TO1_MARK,
2681};
2682static const unsigned int tpu4_to2_pins[] = {
2683 /* TO */
2684 58,
2685};
2686static const unsigned int tpu4_to2_mux[] = {
2687 TPU4TO2_MARK,
2688};
2689static const unsigned int tpu4_to3_pins[] = {
2690 /* TO */
2691};
2692static const unsigned int tpu4_to3_mux[] = {
2693 TPU4TO3_MARK,
2694};
2541/* - USB -------------------------------------------------------------------- */ 2695/* - USB -------------------------------------------------------------------- */
2542static const unsigned int usb_vbus_pins[] = { 2696static const unsigned int usb_vbus_pins[] = {
2543 /* VBUS */ 2697 /* VBUS */
@@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2689 SH_PFC_PIN_GROUP(sdhi2_data1), 2843 SH_PFC_PIN_GROUP(sdhi2_data1),
2690 SH_PFC_PIN_GROUP(sdhi2_data4), 2844 SH_PFC_PIN_GROUP(sdhi2_data4),
2691 SH_PFC_PIN_GROUP(sdhi2_ctrl), 2845 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2846 SH_PFC_PIN_GROUP(tpu0_to0),
2847 SH_PFC_PIN_GROUP(tpu0_to1),
2848 SH_PFC_PIN_GROUP(tpu0_to2),
2849 SH_PFC_PIN_GROUP(tpu0_to3),
2850 SH_PFC_PIN_GROUP(tpu1_to0),
2851 SH_PFC_PIN_GROUP(tpu1_to1_0),
2852 SH_PFC_PIN_GROUP(tpu1_to1_1),
2853 SH_PFC_PIN_GROUP(tpu1_to2),
2854 SH_PFC_PIN_GROUP(tpu1_to3),
2855 SH_PFC_PIN_GROUP(tpu2_to0),
2856 SH_PFC_PIN_GROUP(tpu2_to1),
2857 SH_PFC_PIN_GROUP(tpu2_to2),
2858 SH_PFC_PIN_GROUP(tpu2_to3),
2859 SH_PFC_PIN_GROUP(tpu3_to0),
2860 SH_PFC_PIN_GROUP(tpu3_to1),
2861 SH_PFC_PIN_GROUP(tpu3_to2),
2862 SH_PFC_PIN_GROUP(tpu3_to3),
2863 SH_PFC_PIN_GROUP(tpu4_to0),
2864 SH_PFC_PIN_GROUP(tpu4_to1),
2865 SH_PFC_PIN_GROUP(tpu4_to2),
2866 SH_PFC_PIN_GROUP(tpu4_to3),
2692 SH_PFC_PIN_GROUP(usb_vbus), 2867 SH_PFC_PIN_GROUP(usb_vbus),
2693}; 2868};
2694 2869
@@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = {
2908 "usb_vbus", 3083 "usb_vbus",
2909}; 3084};
2910 3085
3086static const char * const tpu0_groups[] = {
3087 "tpu0_to0",
3088 "tpu0_to1",
3089 "tpu0_to2",
3090 "tpu0_to3",
3091};
3092
3093static const char * const tpu1_groups[] = {
3094 "tpu1_to0",
3095 "tpu1_to1_0",
3096 "tpu1_to1_1",
3097 "tpu1_to2",
3098 "tpu1_to3",
3099};
3100
3101static const char * const tpu2_groups[] = {
3102 "tpu2_to0",
3103 "tpu2_to1",
3104 "tpu2_to2",
3105 "tpu2_to3",
3106};
3107
3108static const char * const tpu3_groups[] = {
3109 "tpu3_to0",
3110 "tpu3_to1",
3111 "tpu3_to2",
3112 "tpu3_to3",
3113};
3114
3115static const char * const tpu4_groups[] = {
3116 "tpu4_to0",
3117 "tpu4_to1",
3118 "tpu4_to2",
3119 "tpu4_to3",
3120};
3121
2911static const struct sh_pfc_function pinmux_functions[] = { 3122static const struct sh_pfc_function pinmux_functions[] = {
2912 SH_PFC_FUNCTION(bsc), 3123 SH_PFC_FUNCTION(bsc),
2913 SH_PFC_FUNCTION(fsia), 3124 SH_PFC_FUNCTION(fsia),
@@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
2933 SH_PFC_FUNCTION(sdhi0), 3144 SH_PFC_FUNCTION(sdhi0),
2934 SH_PFC_FUNCTION(sdhi1), 3145 SH_PFC_FUNCTION(sdhi1),
2935 SH_PFC_FUNCTION(sdhi2), 3146 SH_PFC_FUNCTION(sdhi2),
3147 SH_PFC_FUNCTION(tpu0),
3148 SH_PFC_FUNCTION(tpu1),
3149 SH_PFC_FUNCTION(tpu2),
3150 SH_PFC_FUNCTION(tpu3),
3151 SH_PFC_FUNCTION(tpu4),
2936 SH_PFC_FUNCTION(usb), 3152 SH_PFC_FUNCTION(usb),
2937}; 3153};
2938 3154
2939#define PINMUX_FN_BASE GPIO_FN_GPI0
2940
2941static const struct pinmux_func pinmux_func_gpios[] = {
2942 /* Table 25-1 (Functions 0-7) */
2943 GPIO_FN(GPI0),
2944 GPIO_FN(GPI1),
2945 GPIO_FN(GPI2),
2946 GPIO_FN(GPI3),
2947 GPIO_FN(GPI4),
2948 GPIO_FN(GPI5),
2949 GPIO_FN(GPI6),
2950 GPIO_FN(GPI7),
2951 GPIO_FN(GPO7), \
2952 GPIO_FN(MFG0_OUT2),
2953 GPIO_FN(GPO6), \
2954 GPIO_FN(MFG1_OUT2),
2955 GPIO_FN(GPO5), \
2956 GPIO_FN(PORT16_VIO_CKOR),
2957 GPIO_FN(PORT19_VIO_CKO2),
2958 GPIO_FN(GPO0),
2959 GPIO_FN(GPO1),
2960 GPIO_FN(GPO2), \
2961 GPIO_FN(STATUS0),
2962 GPIO_FN(GPO3), \
2963 GPIO_FN(STATUS1),
2964 GPIO_FN(GPO4), \
2965 GPIO_FN(STATUS2),
2966 GPIO_FN(VINT),
2967 GPIO_FN(TCKON),
2968 GPIO_FN(XDVFS1), \
2969 GPIO_FN(MFG0_OUT1), \
2970 GPIO_FN(PORT27_IROUT),
2971 GPIO_FN(XDVFS2), \
2972 GPIO_FN(PORT28_TPU1TO1),
2973 GPIO_FN(SIM_RST), \
2974 GPIO_FN(PORT29_TPU1TO1),
2975 GPIO_FN(SIM_CLK), \
2976 GPIO_FN(PORT30_VIO_CKOR),
2977 GPIO_FN(SIM_D), \
2978 GPIO_FN(PORT31_IROUT),
2979 GPIO_FN(XWUP),
2980 GPIO_FN(VACK),
2981 GPIO_FN(XTAL1L),
2982 GPIO_FN(PORT49_IROUT), \
2983 GPIO_FN(BBIF2_TSYNC2), \
2984 GPIO_FN(TPU2TO2), \
2985
2986 GPIO_FN(BBIF2_TSCK2), \
2987 GPIO_FN(TPU2TO3), \
2988 GPIO_FN(BBIF2_TXD2),
2989 GPIO_FN(TPU3TO3), \
2990 GPIO_FN(TPU3TO2), \
2991 GPIO_FN(TPU0TO0),
2992 GPIO_FN(A0), \
2993 GPIO_FN(BS_),
2994 GPIO_FN(A12), \
2995 GPIO_FN(TPU4TO2),
2996 GPIO_FN(A13), \
2997 GPIO_FN(TPU0TO1),
2998 GPIO_FN(A14), \
2999 GPIO_FN(A15), \
3000 GPIO_FN(A16), \
3001 GPIO_FN(MSIOF0_SS1),
3002 GPIO_FN(A17), \
3003 GPIO_FN(MSIOF0_TSYNC),
3004 GPIO_FN(A18), \
3005 GPIO_FN(MSIOF0_TSCK),
3006 GPIO_FN(A19), \
3007 GPIO_FN(MSIOF0_TXD),
3008 GPIO_FN(A20), \
3009 GPIO_FN(MSIOF0_RSCK),
3010 GPIO_FN(A21), \
3011 GPIO_FN(MSIOF0_RSYNC),
3012 GPIO_FN(A22), \
3013 GPIO_FN(MSIOF0_MCK0),
3014 GPIO_FN(A23), \
3015 GPIO_FN(MSIOF0_MCK1),
3016 GPIO_FN(A24), \
3017 GPIO_FN(MSIOF0_RXD),
3018 GPIO_FN(A25), \
3019 GPIO_FN(MSIOF0_SS2),
3020 GPIO_FN(A26), \
3021 GPIO_FN(FCE1_),
3022 GPIO_FN(DACK0),
3023 GPIO_FN(FCE0_), \
3024 GPIO_FN(WAIT_), \
3025 GPIO_FN(DREQ0),
3026 GPIO_FN(FRB),
3027 GPIO_FN(CKO),
3028 GPIO_FN(NBRSTOUT_),
3029 GPIO_FN(NBRST_),
3030 GPIO_FN(BBIF2_TXD),
3031 GPIO_FN(BBIF2_RXD),
3032 GPIO_FN(BBIF2_SYNC),
3033 GPIO_FN(BBIF2_SCK),
3034 GPIO_FN(MFG3_IN2),
3035 GPIO_FN(MFG3_IN1),
3036 GPIO_FN(BBIF1_SS2), \
3037 GPIO_FN(MFG3_OUT1),
3038 GPIO_FN(HSI_RX_DATA), \
3039 GPIO_FN(BBIF1_RXD),
3040 GPIO_FN(HSI_TX_WAKE), \
3041 GPIO_FN(BBIF1_TSCK),
3042 GPIO_FN(HSI_TX_DATA), \
3043 GPIO_FN(BBIF1_TSYNC),
3044 GPIO_FN(HSI_TX_READY), \
3045 GPIO_FN(BBIF1_TXD),
3046 GPIO_FN(HSI_RX_READY), \
3047 GPIO_FN(BBIF1_RSCK), \
3048 GPIO_FN(HSI_RX_WAKE), \
3049 GPIO_FN(BBIF1_RSYNC), \
3050 GPIO_FN(HSI_RX_FLAG), \
3051 GPIO_FN(BBIF1_SS1), \
3052 GPIO_FN(BBIF1_FLOW),
3053 GPIO_FN(HSI_TX_FLAG),
3054 GPIO_FN(VIO_VD), \
3055 GPIO_FN(VIO2_VD), \
3056
3057 GPIO_FN(VIO_HD), \
3058 GPIO_FN(VIO2_HD), \
3059 GPIO_FN(VIO_D0), \
3060 GPIO_FN(PORT130_MSIOF2_RXD), \
3061 GPIO_FN(VIO_D1), \
3062 GPIO_FN(PORT131_MSIOF2_SS1), \
3063 GPIO_FN(VIO_D2), \
3064 GPIO_FN(PORT132_MSIOF2_SS2), \
3065 GPIO_FN(VIO_D3), \
3066 GPIO_FN(MSIOF2_TSYNC), \
3067 GPIO_FN(VIO_D4), \
3068 GPIO_FN(MSIOF2_TXD), \
3069 GPIO_FN(VIO_D5), \
3070 GPIO_FN(MSIOF2_TSCK), \
3071 GPIO_FN(VIO_D6), \
3072 GPIO_FN(VIO_D7), \
3073 GPIO_FN(VIO_D8), \
3074 GPIO_FN(VIO2_D0), \
3075 GPIO_FN(VIO_D9), \
3076 GPIO_FN(VIO2_D1), \
3077 GPIO_FN(VIO_D10), \
3078 GPIO_FN(TPU0TO2), \
3079 GPIO_FN(VIO2_D2), \
3080 GPIO_FN(VIO_D11), \
3081 GPIO_FN(TPU0TO3), \
3082 GPIO_FN(VIO2_D3), \
3083 GPIO_FN(VIO_D12), \
3084 GPIO_FN(VIO2_D4), \
3085 GPIO_FN(VIO_D13), \
3086 GPIO_FN(VIO2_D5), \
3087 GPIO_FN(VIO_D14), \
3088 GPIO_FN(VIO2_D6), \
3089 GPIO_FN(VIO_D15), \
3090 GPIO_FN(TPU1TO3), \
3091 GPIO_FN(VIO2_D7), \
3092 GPIO_FN(VIO_CLK), \
3093 GPIO_FN(VIO2_CLK), \
3094 GPIO_FN(VIO_FIELD), \
3095 GPIO_FN(VIO2_FIELD), \
3096 GPIO_FN(VIO_CKO),
3097 GPIO_FN(A27), \
3098 GPIO_FN(MFG0_IN1), \
3099 GPIO_FN(MFG0_IN2),
3100 GPIO_FN(TS_SPSYNC3), \
3101 GPIO_FN(MSIOF2_RSCK),
3102 GPIO_FN(TS_SDAT3), \
3103 GPIO_FN(MSIOF2_RSYNC),
3104 GPIO_FN(TPU1TO2), \
3105 GPIO_FN(TS_SDEN3), \
3106 GPIO_FN(PORT153_MSIOF2_SS1),
3107 GPIO_FN(MSIOF2_MCK0),
3108 GPIO_FN(MSIOF2_MCK1),
3109 GPIO_FN(PORT156_MSIOF2_SS2),
3110 GPIO_FN(PORT157_MSIOF2_RXD),
3111 GPIO_FN(DINT_), \
3112 GPIO_FN(TS_SCK3),
3113 GPIO_FN(NMI),
3114 GPIO_FN(TPU3TO0),
3115 GPIO_FN(BBIF2_TSYNC1),
3116 GPIO_FN(BBIF2_TSCK1),
3117 GPIO_FN(BBIF2_TXD1),
3118 GPIO_FN(MFG2_OUT2), \
3119 GPIO_FN(TPU2TO1),
3120 GPIO_FN(TPU4TO1), \
3121 GPIO_FN(MFG4_OUT2),
3122 GPIO_FN(D16),
3123 GPIO_FN(D17),
3124 GPIO_FN(D18),
3125 GPIO_FN(D19),
3126 GPIO_FN(D20),
3127 GPIO_FN(D21),
3128 GPIO_FN(D22),
3129 GPIO_FN(PORT207_MSIOF0L_SS1), \
3130 GPIO_FN(D23),
3131 GPIO_FN(PORT208_MSIOF0L_SS2), \
3132 GPIO_FN(D24),
3133 GPIO_FN(D25),
3134 GPIO_FN(DREQ2), \
3135 GPIO_FN(PORT210_MSIOF0L_SS1), \
3136 GPIO_FN(D26),
3137 GPIO_FN(PORT211_MSIOF0L_SS2), \
3138 GPIO_FN(D27),
3139 GPIO_FN(TS_SPSYNC1), \
3140 GPIO_FN(MSIOF0L_MCK0), \
3141 GPIO_FN(D28),
3142 GPIO_FN(TS_SDAT1), \
3143 GPIO_FN(MSIOF0L_MCK1), \
3144 GPIO_FN(D29),
3145 GPIO_FN(TS_SDEN1), \
3146 GPIO_FN(MSIOF0L_RSCK), \
3147 GPIO_FN(D30),
3148 GPIO_FN(TS_SCK1), \
3149 GPIO_FN(MSIOF0L_RSYNC), \
3150 GPIO_FN(D31),
3151 GPIO_FN(DACK2), \
3152 GPIO_FN(MSIOF0L_TSYNC), \
3153 GPIO_FN(VIO2_FIELD3), \
3154 GPIO_FN(DACK3), \
3155 GPIO_FN(PORT218_VIO_CKOR),
3156 GPIO_FN(DREQ3), \
3157 GPIO_FN(MSIOF0L_TSCK), \
3158 GPIO_FN(VIO2_CLK3), \
3159 GPIO_FN(DREQ1), \
3160 GPIO_FN(PWEN), \
3161 GPIO_FN(MSIOF0L_RXD), \
3162 GPIO_FN(VIO2_HD3), \
3163 GPIO_FN(DACK1), \
3164 GPIO_FN(OVCN), \
3165 GPIO_FN(MSIOF0L_TXD), \
3166 GPIO_FN(VIO2_VD3), \
3167
3168 GPIO_FN(OVCN2),
3169 GPIO_FN(EXTLP), \
3170 GPIO_FN(PORT226_VIO_CKO2),
3171 GPIO_FN(IDIN),
3172 GPIO_FN(MFG1_IN1),
3173 GPIO_FN(MSIOF1_TXD), \
3174 GPIO_FN(MSIOF1_TSYNC), \
3175 GPIO_FN(MSIOF1_TSCK), \
3176 GPIO_FN(MSIOF1_RXD), \
3177 GPIO_FN(MSIOF1_RSCK), \
3178 GPIO_FN(VIO2_CLK2), \
3179 GPIO_FN(MSIOF1_RSYNC), \
3180 GPIO_FN(MFG1_IN2), \
3181 GPIO_FN(VIO2_VD2), \
3182 GPIO_FN(MSIOF1_MCK0), \
3183 GPIO_FN(MSIOF1_MCK1), \
3184 GPIO_FN(MSIOF1_SS1), \
3185 GPIO_FN(VIO2_FIELD2), \
3186 GPIO_FN(MSIOF1_SS2), \
3187 GPIO_FN(VIO2_HD2), \
3188 GPIO_FN(PORT241_IROUT), \
3189 GPIO_FN(MFG4_OUT1), \
3190 GPIO_FN(TPU4TO0),
3191 GPIO_FN(MFG4_IN2),
3192 GPIO_FN(PORT243_VIO_CKO2),
3193 GPIO_FN(MFG2_IN1), \
3194 GPIO_FN(MSIOF2R_RXD),
3195 GPIO_FN(MFG2_IN2), \
3196 GPIO_FN(MSIOF2R_TXD),
3197 GPIO_FN(MFG1_OUT1), \
3198 GPIO_FN(TPU1TO0),
3199 GPIO_FN(MFG3_OUT2), \
3200 GPIO_FN(TPU3TO1),
3201 GPIO_FN(MFG2_OUT1), \
3202 GPIO_FN(TPU2TO0), \
3203 GPIO_FN(MSIOF2R_TSCK),
3204 GPIO_FN(PORT249_IROUT), \
3205 GPIO_FN(MFG4_IN1), \
3206 GPIO_FN(MSIOF2R_TSYNC),
3207 GPIO_FN(SDHICLK0),
3208 GPIO_FN(SDHICD0),
3209 GPIO_FN(SDHID0_0),
3210 GPIO_FN(SDHID0_1),
3211 GPIO_FN(SDHID0_2),
3212 GPIO_FN(SDHID0_3),
3213 GPIO_FN(SDHICMD0),
3214 GPIO_FN(SDHIWP0),
3215 GPIO_FN(SDHICLK1),
3216 GPIO_FN(SDHID1_0), \
3217 GPIO_FN(TS_SPSYNC2),
3218 GPIO_FN(SDHID1_1), \
3219 GPIO_FN(TS_SDAT2),
3220 GPIO_FN(SDHID1_2), \
3221 GPIO_FN(TS_SDEN2),
3222 GPIO_FN(SDHID1_3), \
3223 GPIO_FN(TS_SCK2),
3224 GPIO_FN(SDHICMD1),
3225 GPIO_FN(SDHICLK2),
3226 GPIO_FN(SDHID2_0), \
3227 GPIO_FN(TS_SPSYNC4),
3228 GPIO_FN(SDHID2_1), \
3229 GPIO_FN(TS_SDAT4),
3230 GPIO_FN(SDHID2_2), \
3231 GPIO_FN(TS_SDEN4),
3232 GPIO_FN(SDHID2_3), \
3233 GPIO_FN(TS_SCK4),
3234 GPIO_FN(SDHICMD2),
3235 GPIO_FN(MMCCLK0),
3236 GPIO_FN(MMCD0_0),
3237 GPIO_FN(MMCD0_1),
3238 GPIO_FN(MMCD0_2),
3239 GPIO_FN(MMCD0_3),
3240 GPIO_FN(MMCD0_4), \
3241 GPIO_FN(TS_SPSYNC5),
3242 GPIO_FN(MMCD0_5), \
3243 GPIO_FN(TS_SDAT5),
3244 GPIO_FN(MMCD0_6), \
3245 GPIO_FN(TS_SDEN5),
3246 GPIO_FN(MMCD0_7), \
3247 GPIO_FN(TS_SCK5),
3248 GPIO_FN(MMCCMD0),
3249 GPIO_FN(RESETOUTS_), \
3250 GPIO_FN(EXTAL2OUT),
3251 GPIO_FN(MCP_WAIT__MCP_FRB),
3252 GPIO_FN(MCP_CKO), \
3253 GPIO_FN(MMCCLK1),
3254 GPIO_FN(MCP_D15_MCP_NAF15),
3255 GPIO_FN(MCP_D14_MCP_NAF14),
3256 GPIO_FN(MCP_D13_MCP_NAF13),
3257 GPIO_FN(MCP_D12_MCP_NAF12),
3258 GPIO_FN(MCP_D11_MCP_NAF11),
3259 GPIO_FN(MCP_D10_MCP_NAF10),
3260 GPIO_FN(MCP_D9_MCP_NAF9),
3261 GPIO_FN(MCP_D8_MCP_NAF8), \
3262 GPIO_FN(MMCCMD1),
3263 GPIO_FN(MCP_D7_MCP_NAF7), \
3264 GPIO_FN(MMCD1_7),
3265
3266 GPIO_FN(MCP_D6_MCP_NAF6), \
3267 GPIO_FN(MMCD1_6),
3268 GPIO_FN(MCP_D5_MCP_NAF5), \
3269 GPIO_FN(MMCD1_5),
3270 GPIO_FN(MCP_D4_MCP_NAF4), \
3271 GPIO_FN(MMCD1_4),
3272 GPIO_FN(MCP_D3_MCP_NAF3), \
3273 GPIO_FN(MMCD1_3),
3274 GPIO_FN(MCP_D2_MCP_NAF2), \
3275 GPIO_FN(MMCD1_2),
3276 GPIO_FN(MCP_D1_MCP_NAF1), \
3277 GPIO_FN(MMCD1_1),
3278 GPIO_FN(MCP_D0_MCP_NAF0), \
3279 GPIO_FN(MMCD1_0),
3280 GPIO_FN(MCP_NBRSTOUT_),
3281 GPIO_FN(MCP_WE0__MCP_FWE), \
3282 GPIO_FN(MCP_RDWR_MCP_FWE),
3283
3284 /* MSEL2 special cases */
3285 GPIO_FN(TSIF2_TS_XX1),
3286 GPIO_FN(TSIF2_TS_XX2),
3287 GPIO_FN(TSIF2_TS_XX3),
3288 GPIO_FN(TSIF2_TS_XX4),
3289 GPIO_FN(TSIF2_TS_XX5),
3290 GPIO_FN(TSIF1_TS_XX1),
3291 GPIO_FN(TSIF1_TS_XX2),
3292 GPIO_FN(TSIF1_TS_XX3),
3293 GPIO_FN(TSIF1_TS_XX4),
3294 GPIO_FN(TSIF1_TS_XX5),
3295 GPIO_FN(TSIF0_TS_XX1),
3296 GPIO_FN(TSIF0_TS_XX2),
3297 GPIO_FN(TSIF0_TS_XX3),
3298 GPIO_FN(TSIF0_TS_XX4),
3299 GPIO_FN(TSIF0_TS_XX5),
3300 GPIO_FN(MST1_TS_XX1),
3301 GPIO_FN(MST1_TS_XX2),
3302 GPIO_FN(MST1_TS_XX3),
3303 GPIO_FN(MST1_TS_XX4),
3304 GPIO_FN(MST1_TS_XX5),
3305 GPIO_FN(MST0_TS_XX1),
3306 GPIO_FN(MST0_TS_XX2),
3307 GPIO_FN(MST0_TS_XX3),
3308 GPIO_FN(MST0_TS_XX4),
3309 GPIO_FN(MST0_TS_XX5),
3310
3311 /* MSEL3 special cases */
3312 GPIO_FN(SDHI0_VCCQ_MC0_ON),
3313 GPIO_FN(SDHI0_VCCQ_MC0_OFF),
3314 GPIO_FN(DEBUG_MON_VIO),
3315 GPIO_FN(DEBUG_MON_LCDD),
3316 GPIO_FN(LCDC_LCDC0),
3317 GPIO_FN(LCDC_LCDC1),
3318
3319 /* MSEL4 special cases */
3320 GPIO_FN(IRQ9_MEM_INT),
3321 GPIO_FN(IRQ9_MCP_INT),
3322 GPIO_FN(A11),
3323 GPIO_FN(TPU4TO3),
3324 GPIO_FN(RESETA_N_PU_ON),
3325 GPIO_FN(RESETA_N_PU_OFF),
3326 GPIO_FN(EDBGREQ_PD),
3327 GPIO_FN(EDBGREQ_PU),
3328};
3329
3330#undef PORTCR 3155#undef PORTCR
3331#define PORTCR(nr, reg) \ 3156#define PORTCR(nr, reg) \
3332 { \ 3157 { \
@@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
3888 PINMUX_IRQ(EXT_IRQ16L(9), 308), 3713 PINMUX_IRQ(EXT_IRQ16L(9), 308),
3889}; 3714};
3890 3715
3716/* -----------------------------------------------------------------------------
3717 * VCCQ MC0 regulator
3718 */
3719
3720static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
3721{
3722 struct sh_pfc *pfc = reg->reg_data;
3723 void __iomem *addr = pfc->window[1].virt + 4;
3724 unsigned long flags;
3725 u32 value;
3726
3727 spin_lock_irqsave(&pfc->lock, flags);
3728
3729 value = ioread32(addr);
3730
3731 if (enable)
3732 value |= BIT(28);
3733 else
3734 value &= ~BIT(28);
3735
3736 iowrite32(value, addr);
3737
3738 spin_unlock_irqrestore(&pfc->lock, flags);
3739}
3740
3741static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
3742{
3743 sh73a0_vccq_mc0_endisable(reg, true);
3744 return 0;
3745}
3746
3747static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
3748{
3749 sh73a0_vccq_mc0_endisable(reg, false);
3750 return 0;
3751}
3752
3753static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
3754{
3755 struct sh_pfc *pfc = reg->reg_data;
3756 void __iomem *addr = pfc->window[1].virt + 4;
3757 unsigned long flags;
3758 u32 value;
3759
3760 spin_lock_irqsave(&pfc->lock, flags);
3761 value = ioread32(addr);
3762 spin_unlock_irqrestore(&pfc->lock, flags);
3763
3764 return !!(value & BIT(28));
3765}
3766
3767static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
3768{
3769 return 3300000;
3770}
3771
3772static struct regulator_ops sh73a0_vccq_mc0_ops = {
3773 .enable = sh73a0_vccq_mc0_enable,
3774 .disable = sh73a0_vccq_mc0_disable,
3775 .is_enabled = sh73a0_vccq_mc0_is_enabled,
3776 .get_voltage = sh73a0_vccq_mc0_get_voltage,
3777};
3778
3779static const struct regulator_desc sh73a0_vccq_mc0_desc = {
3780 .owner = THIS_MODULE,
3781 .name = "vccq_mc0",
3782 .type = REGULATOR_VOLTAGE,
3783 .ops = &sh73a0_vccq_mc0_ops,
3784};
3785
3786static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
3787 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
3788};
3789
3790static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
3791 .constraints = {
3792 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3793 },
3794 .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
3795 .consumer_supplies = sh73a0_vccq_mc0_consumers,
3796};
3797
3798/* -----------------------------------------------------------------------------
3799 * Pin bias
3800 */
3801
3891#define PORTnCR_PULMD_OFF (0 << 6) 3802#define PORTnCR_PULMD_OFF (0 << 6)
3892#define PORTnCR_PULMD_DOWN (2 << 6) 3803#define PORTnCR_PULMD_DOWN (2 << 6)
3893#define PORTnCR_PULMD_UP (3 << 6) 3804#define PORTnCR_PULMD_UP (3 << 6)
@@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3934 iowrite8(value, addr); 3845 iowrite8(value, addr);
3935} 3846}
3936 3847
3848/* -----------------------------------------------------------------------------
3849 * SoC information
3850 */
3851
3852struct sh73a0_pinmux_data {
3853 struct regulator_dev *vccq_mc0;
3854};
3855
3856static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3857{
3858 struct sh73a0_pinmux_data *data;
3859 struct regulator_config cfg = { };
3860 int ret;
3861
3862 data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
3863 if (data == NULL)
3864 return -ENOMEM;
3865
3866 cfg.dev = pfc->dev;
3867 cfg.init_data = &sh73a0_vccq_mc0_init_data;
3868 cfg.driver_data = pfc;
3869
3870 data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
3871 if (IS_ERR(data->vccq_mc0)) {
3872 ret = PTR_ERR(data->vccq_mc0);
3873 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
3874 ret);
3875 return ret;
3876 }
3877
3878 pfc->soc_data = data;
3879
3880 return 0;
3881}
3882
3883static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
3884{
3885 struct sh73a0_pinmux_data *data = pfc->soc_data;
3886
3887 regulator_unregister(data->vccq_mc0);
3888}
3889
3937static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { 3890static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3891 .init = sh73a0_pinmux_soc_init,
3892 .exit = sh73a0_pinmux_soc_exit,
3938 .get_bias = sh73a0_pinmux_get_bias, 3893 .get_bias = sh73a0_pinmux_get_bias,
3939 .set_bias = sh73a0_pinmux_set_bias, 3894 .set_bias = sh73a0_pinmux_set_bias,
3940}; 3895};
@@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3956 .functions = pinmux_functions, 3911 .functions = pinmux_functions,
3957 .nr_functions = ARRAY_SIZE(pinmux_functions), 3912 .nr_functions = ARRAY_SIZE(pinmux_functions),
3958 3913
3959 .func_gpios = pinmux_func_gpios,
3960 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3961
3962 .cfg_regs = pinmux_config_regs, 3914 .cfg_regs = pinmux_config_regs,
3963 .data_regs = pinmux_data_regs, 3915 .data_regs = pinmux_data_regs,
3964 3916
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3b785fc428d5..830ae1ffd0b5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -11,8 +11,8 @@
11#ifndef __SH_PFC_H 11#ifndef __SH_PFC_H
12#define __SH_PFC_H 12#define __SH_PFC_H
13 13
14#include <linux/bug.h>
14#include <linux/stringify.h> 15#include <linux/stringify.h>
15#include <asm-generic/gpio.h>
16 16
17typedef unsigned short pinmux_enum_t; 17typedef unsigned short pinmux_enum_t;
18 18
@@ -129,6 +129,8 @@ struct pinmux_range {
129struct sh_pfc; 129struct sh_pfc;
130 130
131struct sh_pfc_soc_operations { 131struct sh_pfc_soc_operations {
132 int (*init)(struct sh_pfc *pfc);
133 void (*exit)(struct sh_pfc *pfc);
132 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 134 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
133 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 135 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
134 unsigned int bias); 136 unsigned int bias);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 04:23:34 -0400