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path: root/drivers/pinctrl/sh-pfc/pfc-sh7372.c
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Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-sh7372.c')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c1652
1 files changed, 1244 insertions, 408 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21a5ac8..6dfb18772574 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */ 22 */
23#include <linux/io.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/pinctrl/pinconf-generic.h>
26
24#include <mach/irqs.h> 27#include <mach/irqs.h>
25#include <mach/sh7372.h> 28#include <mach/sh7372.h>
26 29
30#include "core.h"
27#include "sh_pfc.h" 31#include "sh_pfc.h"
28 32
29#define CPU_ALL_PORT(fn, pfx, sfx) \ 33#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -34,6 +38,35 @@
34 PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ 38 PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
35 PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) 39 PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
36 40
41#undef _GPIO_PORT
42#define _GPIO_PORT(gpio, sfx) \
43 [gpio] = { \
44 .name = __stringify(PORT##gpio), \
45 .enum_id = PORT##gpio##_DATA, \
46 }
47
48#define IRQC_PIN_MUX(irq, pin) \
49static const unsigned int intc_irq##irq##_pins[] = { \
50 pin, \
51}; \
52static const unsigned int intc_irq##irq##_mux[] = { \
53 IRQ##irq##_MARK, \
54}
55
56#define IRQC_PINS_MUX(irq, pin0, pin1) \
57static const unsigned int intc_irq##irq##_0_pins[] = { \
58 pin0, \
59}; \
60static const unsigned int intc_irq##irq##_0_mux[] = { \
61 IRQ##irq##_##pin0##_MARK, \
62}; \
63static const unsigned int intc_irq##irq##_1_pins[] = { \
64 pin1, \
65}; \
66static const unsigned int intc_irq##irq##_1_mux[] = { \
67 IRQ##irq##_##pin1##_MARK, \
68}
69
37enum { 70enum {
38 PINMUX_RESERVED = 0, 71 PINMUX_RESERVED = 0,
39 72
@@ -47,16 +80,6 @@ enum {
47 PORT_ALL(IN), 80 PORT_ALL(IN),
48 PINMUX_INPUT_END, 81 PINMUX_INPUT_END,
49 82
50 /* PORT0_IN_PU -> PORT190_IN_PU */
51 PINMUX_INPUT_PULLUP_BEGIN,
52 PORT_ALL(IN_PU),
53 PINMUX_INPUT_PULLUP_END,
54
55 /* PORT0_IN_PD -> PORT190_IN_PD */
56 PINMUX_INPUT_PULLDOWN_BEGIN,
57 PORT_ALL(IN_PD),
58 PINMUX_INPUT_PULLDOWN_END,
59
60 /* PORT0_OUT -> PORT190_OUT */ 83 /* PORT0_OUT -> PORT190_OUT */
61 PINMUX_OUTPUT_BEGIN, 84 PINMUX_OUTPUT_BEGIN,
62 PORT_ALL(OUT), 85 PORT_ALL(OUT),
@@ -368,124 +391,11 @@ enum {
368 PINMUX_MARK_END, 391 PINMUX_MARK_END,
369}; 392};
370 393
371static const pinmux_enum_t pinmux_data[] = { 394#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
395#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
372 396
373 /* specify valid pin states for each pin in GPIO mode */ 397static const pinmux_enum_t pinmux_data[] = {
374 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), 398 PINMUX_DATA_GP_ALL(),
375 PORT_DATA_O(2), PORT_DATA_I_PD(3),
376 PORT_DATA_I_PD(4), PORT_DATA_I_PD(5),
377 PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7),
378 PORT_DATA_IO_PD(8), PORT_DATA_O(9),
379
380 PORT_DATA_O(10), PORT_DATA_O(11),
381 PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13),
382 PORT_DATA_IO_PD(14), PORT_DATA_O(15),
383 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
384 PORT_DATA_I_PD(18), PORT_DATA_IO(19),
385
386 PORT_DATA_IO(20), PORT_DATA_IO(21),
387 PORT_DATA_IO(22), PORT_DATA_IO(23),
388 PORT_DATA_IO(24), PORT_DATA_IO(25),
389 PORT_DATA_IO(26), PORT_DATA_IO(27),
390 PORT_DATA_IO(28), PORT_DATA_IO(29),
391
392 PORT_DATA_IO(30), PORT_DATA_IO(31),
393 PORT_DATA_IO(32), PORT_DATA_IO(33),
394 PORT_DATA_IO(34), PORT_DATA_IO(35),
395 PORT_DATA_IO(36), PORT_DATA_IO(37),
396 PORT_DATA_IO(38), PORT_DATA_IO(39),
397
398 PORT_DATA_IO(40), PORT_DATA_IO(41),
399 PORT_DATA_IO(42), PORT_DATA_IO(43),
400 PORT_DATA_IO(44), PORT_DATA_IO(45),
401 PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47),
402 PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49),
403
404 PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51),
405 PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53),
406 PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55),
407 PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57),
408 PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59),
409
410 PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61),
411 PORT_DATA_IO(62), PORT_DATA_O(63),
412 PORT_DATA_O(64), PORT_DATA_IO_PU(65),
413 PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/
414 PORT_DATA_O(68), PORT_DATA_IO(69),
415
416 PORT_DATA_IO(70), PORT_DATA_IO(71),
417 PORT_DATA_O(72), PORT_DATA_I_PU(73),
418 PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75),
419 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
420 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
421
422 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
423 PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
424 PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
425 PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87),
426 PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89),
427
428 PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91),
429 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
430 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
431 PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97),
432 PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/
433
434 PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101),
435 PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103),
436 PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105),
437 PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107),
438 PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109),
439
440 PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111),
441 PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
442 PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115),
443 PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
444 PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119),
445
446 PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121),
447 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
448 PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125),
449 PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127),
450 PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129),
451
452 PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
453 PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
454 PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135),
455 PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137),
456 PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139),
457
458 PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141),
459 PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143),
460 PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145),
461 PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147),
462 PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149),
463
464 PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151),
465 PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153),
466 PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155),
467 PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157),
468 PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159),
469
470 PORT_DATA_O(160), PORT_DATA_IO_PD(161),
471 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
472 PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165),
473 PORT_DATA_I_PD(166), PORT_DATA_I_PD(167),
474 PORT_DATA_I_PD(168), PORT_DATA_I_PD(169),
475
476 PORT_DATA_I_PD(170), PORT_DATA_O(171),
477 PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
478 PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
479 PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
480 PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179),
481
482 PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181),
483 PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183),
484 PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185),
485 PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187),
486 PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189),
487
488 PORT_DATA_IO_PU_PD(190),
489 399
490 /* IRQ */ 400 /* IRQ */
491 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), 401 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
@@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = {
929 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), 839 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
930}; 840};
931 841
842#define SH7372_PIN(pin, cfgs) \
843 { \
844 .name = __stringify(PORT##pin), \
845 .enum_id = PORT##pin##_DATA, \
846 .configs = cfgs, \
847 }
848
849#define __I (SH_PFC_PIN_CFG_INPUT)
850#define __O (SH_PFC_PIN_CFG_OUTPUT)
851#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
852#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
853#define __PU (SH_PFC_PIN_CFG_PULL_UP)
854#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
855
856#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD)
857#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU)
858#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD)
859#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO)
860#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD)
861#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU)
862#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD)
863#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O)
864#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD)
865
932static struct sh_pfc_pin pinmux_pins[] = { 866static struct sh_pfc_pin pinmux_pins[] = {
933 GPIO_PORT_ALL(), 867 /* Table 57-1 (I/O and Pull U/D) */
868 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
869 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
870 SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5),
871 SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7),
872 SH7372_PIN_IO_PD(8), SH7372_PIN_O(9),
873 SH7372_PIN_O(10), SH7372_PIN_O(11),
874 SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13),
875 SH7372_PIN_IO_PD(14), SH7372_PIN_O(15),
876 SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17),
877 SH7372_PIN_I_PD(18), SH7372_PIN_IO(19),
878 SH7372_PIN_IO(20), SH7372_PIN_IO(21),
879 SH7372_PIN_IO(22), SH7372_PIN_IO(23),
880 SH7372_PIN_IO(24), SH7372_PIN_IO(25),
881 SH7372_PIN_IO(26), SH7372_PIN_IO(27),
882 SH7372_PIN_IO(28), SH7372_PIN_IO(29),
883 SH7372_PIN_IO(30), SH7372_PIN_IO(31),
884 SH7372_PIN_IO(32), SH7372_PIN_IO(33),
885 SH7372_PIN_IO(34), SH7372_PIN_IO(35),
886 SH7372_PIN_IO(36), SH7372_PIN_IO(37),
887 SH7372_PIN_IO(38), SH7372_PIN_IO(39),
888 SH7372_PIN_IO(40), SH7372_PIN_IO(41),
889 SH7372_PIN_IO(42), SH7372_PIN_IO(43),
890 SH7372_PIN_IO(44), SH7372_PIN_IO(45),
891 SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47),
892 SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49),
893 SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51),
894 SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53),
895 SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55),
896 SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57),
897 SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59),
898 SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61),
899 SH7372_PIN_IO(62), SH7372_PIN_O(63),
900 SH7372_PIN_O(64), SH7372_PIN_IO_PU(65),
901 SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67),
902 SH7372_PIN_O(68), SH7372_PIN_IO(69),
903 SH7372_PIN_IO(70), SH7372_PIN_IO(71),
904 SH7372_PIN_O(72), SH7372_PIN_I_PU(73),
905 SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75),
906 SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77),
907 SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79),
908 SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81),
909 SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83),
910 SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85),
911 SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87),
912 SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89),
913 SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91),
914 SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93),
915 SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95),
916 SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97),
917 SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99),
918 SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101),
919 SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103),
920 SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105),
921 SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107),
922 SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109),
923 SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111),
924 SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113),
925 SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115),
926 SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117),
927 SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119),
928 SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121),
929 SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123),
930 SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125),
931 SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127),
932 SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129),
933 SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131),
934 SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133),
935 SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135),
936 SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137),
937 SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139),
938 SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141),
939 SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143),
940 SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145),
941 SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147),
942 SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149),
943 SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151),
944 SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153),
945 SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155),
946 SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157),
947 SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159),
948 SH7372_PIN_O(160), SH7372_PIN_IO_PD(161),
949 SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163),
950 SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165),
951 SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167),
952 SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169),
953 SH7372_PIN_I_PD(170), SH7372_PIN_O(171),
954 SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173),
955 SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175),
956 SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177),
957 SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179),
958 SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181),
959 SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183),
960 SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185),
961 SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187),
962 SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189),
963 SH7372_PIN_IO_PU_PD(190),
934}; 964};
935 965
966/* - BSC -------------------------------------------------------------------- */
967static const unsigned int bsc_data8_pins[] = {
968 /* D[0:7] */
969 46, 47, 48, 49, 50, 51, 52, 53,
970};
971static const unsigned int bsc_data8_mux[] = {
972 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
973 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
974};
975static const unsigned int bsc_data16_pins[] = {
976 /* D[0:15] */
977 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
978};
979static const unsigned int bsc_data16_mux[] = {
980 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
981 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
982 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
983 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
984};
985static const unsigned int bsc_cs0_pins[] = {
986 /* CS */
987 62,
988};
989static const unsigned int bsc_cs0_mux[] = {
990 CS0_MARK,
991};
992static const unsigned int bsc_cs2_pins[] = {
993 /* CS */
994 63,
995};
996static const unsigned int bsc_cs2_mux[] = {
997 CS2_MARK,
998};
999static const unsigned int bsc_cs4_pins[] = {
1000 /* CS */
1001 64,
1002};
1003static const unsigned int bsc_cs4_mux[] = {
1004 CS4_MARK,
1005};
1006static const unsigned int bsc_cs5a_pins[] = {
1007 /* CS */
1008 65,
1009};
1010static const unsigned int bsc_cs5a_mux[] = {
1011 CS5A_MARK,
1012};
1013static const unsigned int bsc_cs5b_pins[] = {
1014 /* CS */
1015 66,
1016};
1017static const unsigned int bsc_cs5b_mux[] = {
1018 CS5B_MARK,
1019};
1020static const unsigned int bsc_cs6a_pins[] = {
1021 /* CS */
1022 67,
1023};
1024static const unsigned int bsc_cs6a_mux[] = {
1025 CS6A_MARK,
1026};
1027static const unsigned int bsc_rd_we8_pins[] = {
1028 /* RD, WE[0] */
1029 69, 70,
1030};
1031static const unsigned int bsc_rd_we8_mux[] = {
1032 RD_FSC_MARK, WE0_FWE_MARK,
1033};
1034static const unsigned int bsc_rd_we16_pins[] = {
1035 /* RD, WE[0:1] */
1036 69, 70, 71,
1037};
1038static const unsigned int bsc_rd_we16_mux[] = {
1039 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1040};
1041static const unsigned int bsc_bs_pins[] = {
1042 /* BS */
1043 19,
1044};
1045static const unsigned int bsc_bs_mux[] = {
1046 BS_MARK,
1047};
1048static const unsigned int bsc_rdwr_pins[] = {
1049 /* RDWR */
1050 75,
1051};
1052static const unsigned int bsc_rdwr_mux[] = {
1053 RDWR_MARK,
1054};
1055static const unsigned int bsc_wait_pins[] = {
1056 /* WAIT */
1057 74,
1058};
1059static const unsigned int bsc_wait_mux[] = {
1060 WAIT_MARK,
1061};
1062/* - CEU -------------------------------------------------------------------- */
1063static const unsigned int ceu_data_0_7_pins[] = {
1064 /* D[0:7] */
1065 102, 103, 104, 105, 106, 107, 108, 109,
1066};
1067static const unsigned int ceu_data_0_7_mux[] = {
1068 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
1069 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
1070};
1071static const unsigned int ceu_data_8_15_pins[] = {
1072 /* D[8:15] */
1073 110, 111, 112, 113, 114, 115, 116, 117,
1074};
1075static const unsigned int ceu_data_8_15_mux[] = {
1076 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
1077 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
1078};
1079static const unsigned int ceu_clk_0_pins[] = {
1080 /* CKO */
1081 120,
1082};
1083static const unsigned int ceu_clk_0_mux[] = {
1084 VIO_CKO_MARK,
1085};
1086static const unsigned int ceu_clk_1_pins[] = {
1087 /* CKO */
1088 16,
1089};
1090static const unsigned int ceu_clk_1_mux[] = {
1091 VIO_CKO1_MARK,
1092};
1093static const unsigned int ceu_clk_2_pins[] = {
1094 /* CKO */
1095 17,
1096};
1097static const unsigned int ceu_clk_2_mux[] = {
1098 VIO_CKO2_MARK,
1099};
1100static const unsigned int ceu_sync_pins[] = {
1101 /* CLK, VD, HD */
1102 118, 100, 101,
1103};
1104static const unsigned int ceu_sync_mux[] = {
1105 VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
1106};
1107static const unsigned int ceu_field_pins[] = {
1108 /* FIELD */
1109 119,
1110};
1111static const unsigned int ceu_field_mux[] = {
1112 VIO_FIELD_MARK,
1113};
1114/* - FLCTL ------------------------------------------------------------------ */
1115static const unsigned int flctl_data_pins[] = {
1116 /* NAF[0:15] */
1117 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
1118};
1119static const unsigned int flctl_data_mux[] = {
1120 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1121 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1122 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1123 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1124};
1125static const unsigned int flctl_ce0_pins[] = {
1126 /* CE */
1127 68,
1128};
1129static const unsigned int flctl_ce0_mux[] = {
1130 FCE0_MARK,
1131};
1132static const unsigned int flctl_ce1_pins[] = {
1133 /* CE */
1134 66,
1135};
1136static const unsigned int flctl_ce1_mux[] = {
1137 FCE1_MARK,
1138};
1139static const unsigned int flctl_ctrl_pins[] = {
1140 /* FCDE, FOE, FSC, FWE, FRB */
1141 24, 23, 69, 70, 73,
1142};
1143static const unsigned int flctl_ctrl_mux[] = {
1144 A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
1145};
1146/* - FSIA ------------------------------------------------------------------- */
1147static const unsigned int fsia_mclk_in_pins[] = {
1148 /* CK */
1149 4,
1150};
1151static const unsigned int fsia_mclk_in_mux[] = {
1152 FSIACK_MARK,
1153};
1154static const unsigned int fsia_mclk_out_pins[] = {
1155 /* OMC */
1156 8,
1157};
1158static const unsigned int fsia_mclk_out_mux[] = {
1159 FSIAOMC_MARK,
1160};
1161static const unsigned int fsia_sclk_in_pins[] = {
1162 /* ILR, IBT */
1163 5, 6,
1164};
1165static const unsigned int fsia_sclk_in_mux[] = {
1166 FSIAILR_MARK, FSIAIBT_MARK,
1167};
1168static const unsigned int fsia_sclk_out_pins[] = {
1169 /* OLR, OBT */
1170 9, 10,
1171};
1172static const unsigned int fsia_sclk_out_mux[] = {
1173 FSIAOLR_MARK, FSIAOBT_MARK,
1174};
1175static const unsigned int fsia_data_in_pins[] = {
1176 /* ISLD */
1177 7,
1178};
1179static const unsigned int fsia_data_in_mux[] = {
1180 FSIAISLD_MARK,
1181};
1182static const unsigned int fsia_data_out_pins[] = {
1183 /* OSLD */
1184 11,
1185};
1186static const unsigned int fsia_data_out_mux[] = {
1187 FSIAOSLD_MARK,
1188};
1189static const unsigned int fsia_spdif_0_pins[] = {
1190 /* SPDIF */
1191 11,
1192};
1193static const unsigned int fsia_spdif_0_mux[] = {
1194 FSIASPDIF_11_MARK,
1195};
1196static const unsigned int fsia_spdif_1_pins[] = {
1197 /* SPDIF */
1198 15,
1199};
1200static const unsigned int fsia_spdif_1_mux[] = {
1201 FSIASPDIF_15_MARK,
1202};
1203/* - FSIB ------------------------------------------------------------------- */
1204static const unsigned int fsib_mclk_in_pins[] = {
1205 /* CK */
1206 4,
1207};
1208static const unsigned int fsib_mclk_in_mux[] = {
1209 FSIBCK_MARK,
1210};
1211/* - HDMI ------------------------------------------------------------------- */
1212static const unsigned int hdmi_pins[] = {
1213 /* HPD, CEC */
1214 169, 170,
1215};
1216static const unsigned int hdmi_mux[] = {
1217 HDMI_HPD_MARK, HDMI_CEC_MARK,
1218};
1219/* - INTC ------------------------------------------------------------------- */
1220IRQC_PINS_MUX(0, 6, 162);
1221IRQC_PIN_MUX(1, 12);
1222IRQC_PINS_MUX(2, 4, 5);
1223IRQC_PINS_MUX(3, 8, 16);
1224IRQC_PINS_MUX(4, 17, 163);
1225IRQC_PIN_MUX(5, 18);
1226IRQC_PINS_MUX(6, 39, 164);
1227IRQC_PINS_MUX(7, 40, 167);
1228IRQC_PINS_MUX(8, 41, 168);
1229IRQC_PINS_MUX(9, 42, 169);
1230IRQC_PIN_MUX(10, 65);
1231IRQC_PIN_MUX(11, 67);
1232IRQC_PINS_MUX(12, 80, 137);
1233IRQC_PINS_MUX(13, 81, 145);
1234IRQC_PINS_MUX(14, 82, 146);
1235IRQC_PINS_MUX(15, 83, 147);
1236IRQC_PINS_MUX(16, 84, 170);
1237IRQC_PIN_MUX(17, 85);
1238IRQC_PIN_MUX(18, 86);
1239IRQC_PIN_MUX(19, 87);
1240IRQC_PIN_MUX(20, 92);
1241IRQC_PIN_MUX(21, 93);
1242IRQC_PIN_MUX(22, 94);
1243IRQC_PIN_MUX(23, 95);
1244IRQC_PIN_MUX(24, 112);
1245IRQC_PIN_MUX(25, 119);
1246IRQC_PINS_MUX(26, 121, 172);
1247IRQC_PINS_MUX(27, 122, 180);
1248IRQC_PINS_MUX(28, 123, 181);
1249IRQC_PINS_MUX(29, 129, 182);
1250IRQC_PINS_MUX(30, 130, 183);
1251IRQC_PINS_MUX(31, 138, 184);
1252/* - KEYSC ------------------------------------------------------------------ */
1253static const unsigned int keysc_in04_0_pins[] = {
1254 /* KEYIN[0:4] */
1255 136, 135, 134, 133, 132,
1256};
1257static const unsigned int keysc_in04_0_mux[] = {
1258 KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
1259 KEYIN4_MARK,
1260};
1261static const unsigned int keysc_in04_1_pins[] = {
1262 /* KEYIN[0:4] */
1263 121, 122, 123, 124, 132,
1264};
1265static const unsigned int keysc_in04_1_mux[] = {
1266 KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
1267 KEYIN4_MARK,
1268};
1269static const unsigned int keysc_in5_pins[] = {
1270 /* KEYIN5 */
1271 131,
1272};
1273static const unsigned int keysc_in5_mux[] = {
1274 KEYIN5_MARK,
1275};
1276static const unsigned int keysc_in6_pins[] = {
1277 /* KEYIN6 */
1278 130,
1279};
1280static const unsigned int keysc_in6_mux[] = {
1281 KEYIN6_MARK,
1282};
1283static const unsigned int keysc_in7_pins[] = {
1284 /* KEYIN7 */
1285 129,
1286};
1287static const unsigned int keysc_in7_mux[] = {
1288 KEYIN7_MARK,
1289};
1290static const unsigned int keysc_out4_pins[] = {
1291 /* KEYOUT[0:3] */
1292 128, 127, 126, 125,
1293};
1294static const unsigned int keysc_out4_mux[] = {
1295 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1296};
1297static const unsigned int keysc_out5_pins[] = {
1298 /* KEYOUT[0:4] */
1299 128, 127, 126, 125, 124,
1300};
1301static const unsigned int keysc_out5_mux[] = {
1302 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1303 KEYOUT4_MARK,
1304};
1305static const unsigned int keysc_out6_pins[] = {
1306 /* KEYOUT[0:5] */
1307 128, 127, 126, 125, 124, 123,
1308};
1309static const unsigned int keysc_out6_mux[] = {
1310 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1311 KEYOUT4_MARK, KEYOUT5_MARK,
1312};
1313static const unsigned int keysc_out8_pins[] = {
1314 /* KEYOUT[0:7] */
1315 128, 127, 126, 125, 124, 123, 122, 121,
1316};
1317static const unsigned int keysc_out8_mux[] = {
1318 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1319 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
1320};
1321/* - LCD -------------------------------------------------------------------- */
1322static const unsigned int lcd_data8_pins[] = {
1323 /* D[0:7] */
1324 121, 122, 123, 124, 125, 126, 127, 128,
1325};
1326static const unsigned int lcd_data8_mux[] = {
1327 /* LCDC */
1328 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1329 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1330};
1331static const unsigned int lcd_data9_pins[] = {
1332 /* D[0:8] */
1333 121, 122, 123, 124, 125, 126, 127, 128,
1334 129,
1335 137, 138, 139, 140, 141, 142, 143, 144,
1336};
1337static const unsigned int lcd_data9_mux[] = {
1338 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1339 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1340 LCDD8_MARK,
1341};
1342static const unsigned int lcd_data12_pins[] = {
1343 /* D[0:11] */
1344 121, 122, 123, 124, 125, 126, 127, 128,
1345 129, 130, 131, 132,
1346};
1347static const unsigned int lcd_data12_mux[] = {
1348 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1349 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1350 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1351};
1352static const unsigned int lcd_data16_pins[] = {
1353 /* D[0:15] */
1354 121, 122, 123, 124, 125, 126, 127, 128,
1355 129, 130, 131, 132, 133, 134, 135, 136,
1356};
1357static const unsigned int lcd_data16_mux[] = {
1358 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1359 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1360 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1361 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1362};
1363static const unsigned int lcd_data18_pins[] = {
1364 /* D[0:17] */
1365 121, 122, 123, 124, 125, 126, 127, 128,
1366 129, 130, 131, 132, 133, 134, 135, 136,
1367 137, 138,
1368};
1369static const unsigned int lcd_data18_mux[] = {
1370 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1371 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1372 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1373 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1374 LCDD16_MARK, LCDD17_MARK,
1375};
1376static const unsigned int lcd_data24_pins[] = {
1377 /* D[0:23] */
1378 121, 122, 123, 124, 125, 126, 127, 128,
1379 129, 130, 131, 132, 133, 134, 135, 136,
1380 137, 138, 139, 140, 141, 142, 143, 144,
1381};
1382static const unsigned int lcd_data24_mux[] = {
1383 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1384 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1385 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1386 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1387 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1388 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
1389};
1390static const unsigned int lcd_display_pins[] = {
1391 /* DON */
1392 151,
1393};
1394static const unsigned int lcd_display_mux[] = {
1395 LCDDON_MARK,
1396};
1397static const unsigned int lcd_lclk_pins[] = {
1398 /* LCLK */
1399 150,
1400};
1401static const unsigned int lcd_lclk_mux[] = {
1402 LCDLCLK_MARK,
1403};
1404static const unsigned int lcd_sync_pins[] = {
1405 /* VSYN, HSYN, DCK, DISP */
1406 146, 145, 147, 149,
1407};
1408static const unsigned int lcd_sync_mux[] = {
1409 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
1410};
1411static const unsigned int lcd_sys_pins[] = {
1412 /* CS, WR, RD, RS */
1413 145, 147, 148, 149,
1414};
1415static const unsigned int lcd_sys_mux[] = {
1416 LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
1417};
936/* - MMCIF ------------------------------------------------------------------ */ 1418/* - MMCIF ------------------------------------------------------------------ */
937static const unsigned int mmc0_data1_0_pins[] = { 1419static const unsigned int mmc0_data1_0_pins[] = {
938 /* D[0] */ 1420 /* D[0] */
@@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
993static const unsigned int mmc0_ctrl_1_mux[] = { 1475static const unsigned int mmc0_ctrl_1_mux[] = {
994 MMCCMD1_MARK, MMCCLK1_MARK, 1476 MMCCMD1_MARK, MMCCLK1_MARK,
995}; 1477};
1478/* - SCIFA0 ----------------------------------------------------------------- */
1479static const unsigned int scifa0_data_pins[] = {
1480 /* RXD, TXD */
1481 153, 152,
1482};
1483static const unsigned int scifa0_data_mux[] = {
1484 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1485};
1486static const unsigned int scifa0_clk_pins[] = {
1487 /* SCK */
1488 156,
1489};
1490static const unsigned int scifa0_clk_mux[] = {
1491 SCIFA0_SCK_MARK,
1492};
1493static const unsigned int scifa0_ctrl_pins[] = {
1494 /* RTS, CTS */
1495 157, 158,
1496};
1497static const unsigned int scifa0_ctrl_mux[] = {
1498 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1499};
1500/* - SCIFA1 ----------------------------------------------------------------- */
1501static const unsigned int scifa1_data_pins[] = {
1502 /* RXD, TXD */
1503 155, 154,
1504};
1505static const unsigned int scifa1_data_mux[] = {
1506 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1507};
1508static const unsigned int scifa1_clk_pins[] = {
1509 /* SCK */
1510 159,
1511};
1512static const unsigned int scifa1_clk_mux[] = {
1513 SCIFA1_SCK_MARK,
1514};
1515static const unsigned int scifa1_ctrl_pins[] = {
1516 /* RTS, CTS */
1517 160, 161,
1518};
1519static const unsigned int scifa1_ctrl_mux[] = {
1520 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1521};
1522/* - SCIFA2 ----------------------------------------------------------------- */
1523static const unsigned int scifa2_data_pins[] = {
1524 /* RXD, TXD */
1525 97, 96,
1526};
1527static const unsigned int scifa2_data_mux[] = {
1528 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
1529};
1530static const unsigned int scifa2_clk_pins[] = {
1531 /* SCK */
1532 98,
1533};
1534static const unsigned int scifa2_clk_mux[] = {
1535 SCIFA2_SCK1_MARK,
1536};
1537static const unsigned int scifa2_ctrl_pins[] = {
1538 /* RTS, CTS */
1539 95, 94,
1540};
1541static const unsigned int scifa2_ctrl_mux[] = {
1542 SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
1543};
1544/* - SCIFA3 ----------------------------------------------------------------- */
1545static const unsigned int scifa3_data_pins[] = {
1546 /* RXD, TXD */
1547 144, 143,
1548};
1549static const unsigned int scifa3_data_mux[] = {
1550 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
1551};
1552static const unsigned int scifa3_clk_pins[] = {
1553 /* SCK */
1554 142,
1555};
1556static const unsigned int scifa3_clk_mux[] = {
1557 SCIFA3_SCK_MARK,
1558};
1559static const unsigned int scifa3_ctrl_0_pins[] = {
1560 /* RTS, CTS */
1561 44, 43,
1562};
1563static const unsigned int scifa3_ctrl_0_mux[] = {
1564 SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
1565};
1566static const unsigned int scifa3_ctrl_1_pins[] = {
1567 /* RTS, CTS */
1568 141, 140,
1569};
1570static const unsigned int scifa3_ctrl_1_mux[] = {
1571 SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
1572};
1573/* - SCIFA4 ----------------------------------------------------------------- */
1574static const unsigned int scifa4_data_pins[] = {
1575 /* RXD, TXD */
1576 5, 6,
1577};
1578static const unsigned int scifa4_data_mux[] = {
1579 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
1580};
1581/* - SCIFA5 ----------------------------------------------------------------- */
1582static const unsigned int scifa5_data_pins[] = {
1583 /* RXD, TXD */
1584 8, 12,
1585};
1586static const unsigned int scifa5_data_mux[] = {
1587 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
1588};
1589/* - SCIFB ------------------------------------------------------------------ */
1590static const unsigned int scifb_data_pins[] = {
1591 /* RXD, TXD */
1592 166, 165,
1593};
1594static const unsigned int scifb_data_mux[] = {
1595 SCIFB_RXD_MARK, SCIFB_TXD_MARK,
1596};
1597static const unsigned int scifb_clk_pins[] = {
1598 /* SCK */
1599 162,
1600};
1601static const unsigned int scifb_clk_mux[] = {
1602 SCIFB_SCK_MARK,
1603};
1604static const unsigned int scifb_ctrl_pins[] = {
1605 /* RTS, CTS */
1606 163, 164,
1607};
1608static const unsigned int scifb_ctrl_mux[] = {
1609 SCIFB_RTS_MARK, SCIFB_CTS_MARK,
1610};
996/* - SDHI0 ------------------------------------------------------------------ */ 1611/* - SDHI0 ------------------------------------------------------------------ */
997static const unsigned int sdhi0_data1_pins[] = { 1612static const unsigned int sdhi0_data1_pins[] = {
998 /* D0 */ 1613 /* D0 */
@@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = {
1073static const unsigned int sdhi2_ctrl_mux[] = { 1688static const unsigned int sdhi2_ctrl_mux[] = {
1074 SDHICMD2_MARK, SDHICLK2_MARK, 1689 SDHICMD2_MARK, SDHICLK2_MARK,
1075}; 1690};
1691/* - USB0 ------------------------------------------------------------------- */
1692static const unsigned int usb0_vbus_pins[] = {
1693 /* VBUS */
1694 167,
1695};
1696static const unsigned int usb0_vbus_mux[] = {
1697 VBUS0_0_MARK,
1698};
1699static const unsigned int usb0_otg_id_pins[] = {
1700 /* IDIN */
1701 113,
1702};
1703static const unsigned int usb0_otg_id_mux[] = {
1704 IDIN_0_MARK,
1705};
1706static const unsigned int usb0_otg_ctrl_pins[] = {
1707 /* PWEN, EXTLP, OVCN, OVCN2 */
1708 116, 114, 117, 115,
1709};
1710static const unsigned int usb0_otg_ctrl_mux[] = {
1711 PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
1712};
1713/* - USB1 ------------------------------------------------------------------- */
1714static const unsigned int usb1_vbus_pins[] = {
1715 /* VBUS */
1716 168,
1717};
1718static const unsigned int usb1_vbus_mux[] = {
1719 VBUS0_1_MARK,
1720};
1721static const unsigned int usb1_otg_id_0_pins[] = {
1722 /* IDIN */
1723 113,
1724};
1725static const unsigned int usb1_otg_id_0_mux[] = {
1726 IDIN_1_113_MARK,
1727};
1728static const unsigned int usb1_otg_id_1_pins[] = {
1729 /* IDIN */
1730 18,
1731};
1732static const unsigned int usb1_otg_id_1_mux[] = {
1733 IDIN_1_18_MARK,
1734};
1735static const unsigned int usb1_otg_ctrl_0_pins[] = {
1736 /* PWEN, EXTLP, OVCN, OVCN2 */
1737 115, 116, 114, 117, 113,
1738};
1739static const unsigned int usb1_otg_ctrl_0_mux[] = {
1740 PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
1741};
1742static const unsigned int usb1_otg_ctrl_1_pins[] = {
1743 /* PWEN, EXTLP, OVCN, OVCN2 */
1744 138, 116, 162, 117, 18,
1745};
1746static const unsigned int usb1_otg_ctrl_1_mux[] = {
1747 PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
1748};
1076 1749
1077static const struct sh_pfc_pin_group pinmux_groups[] = { 1750static const struct sh_pfc_pin_group pinmux_groups[] = {
1751 SH_PFC_PIN_GROUP(bsc_data8),
1752 SH_PFC_PIN_GROUP(bsc_data16),
1753 SH_PFC_PIN_GROUP(bsc_cs0),
1754 SH_PFC_PIN_GROUP(bsc_cs2),
1755 SH_PFC_PIN_GROUP(bsc_cs4),
1756 SH_PFC_PIN_GROUP(bsc_cs5a),
1757 SH_PFC_PIN_GROUP(bsc_cs5b),
1758 SH_PFC_PIN_GROUP(bsc_cs6a),
1759 SH_PFC_PIN_GROUP(bsc_rd_we8),
1760 SH_PFC_PIN_GROUP(bsc_rd_we16),
1761 SH_PFC_PIN_GROUP(bsc_bs),
1762 SH_PFC_PIN_GROUP(bsc_rdwr),
1763 SH_PFC_PIN_GROUP(ceu_data_0_7),
1764 SH_PFC_PIN_GROUP(ceu_data_8_15),
1765 SH_PFC_PIN_GROUP(ceu_clk_0),
1766 SH_PFC_PIN_GROUP(ceu_clk_1),
1767 SH_PFC_PIN_GROUP(ceu_clk_2),
1768 SH_PFC_PIN_GROUP(ceu_sync),
1769 SH_PFC_PIN_GROUP(ceu_field),
1770 SH_PFC_PIN_GROUP(flctl_data),
1771 SH_PFC_PIN_GROUP(flctl_ce0),
1772 SH_PFC_PIN_GROUP(flctl_ce1),
1773 SH_PFC_PIN_GROUP(flctl_ctrl),
1774 SH_PFC_PIN_GROUP(fsia_mclk_in),
1775 SH_PFC_PIN_GROUP(fsia_mclk_out),
1776 SH_PFC_PIN_GROUP(fsia_sclk_in),
1777 SH_PFC_PIN_GROUP(fsia_sclk_out),
1778 SH_PFC_PIN_GROUP(fsia_data_in),
1779 SH_PFC_PIN_GROUP(fsia_data_out),
1780 SH_PFC_PIN_GROUP(fsia_spdif_0),
1781 SH_PFC_PIN_GROUP(fsia_spdif_1),
1782 SH_PFC_PIN_GROUP(fsib_mclk_in),
1783 SH_PFC_PIN_GROUP(hdmi),
1784 SH_PFC_PIN_GROUP(intc_irq0_0),
1785 SH_PFC_PIN_GROUP(intc_irq0_1),
1786 SH_PFC_PIN_GROUP(intc_irq1),
1787 SH_PFC_PIN_GROUP(intc_irq2_0),
1788 SH_PFC_PIN_GROUP(intc_irq2_1),
1789 SH_PFC_PIN_GROUP(intc_irq3_0),
1790 SH_PFC_PIN_GROUP(intc_irq3_1),
1791 SH_PFC_PIN_GROUP(intc_irq4_0),
1792 SH_PFC_PIN_GROUP(intc_irq4_1),
1793 SH_PFC_PIN_GROUP(intc_irq5),
1794 SH_PFC_PIN_GROUP(intc_irq6_0),
1795 SH_PFC_PIN_GROUP(intc_irq6_1),
1796 SH_PFC_PIN_GROUP(intc_irq7_0),
1797 SH_PFC_PIN_GROUP(intc_irq7_1),
1798 SH_PFC_PIN_GROUP(intc_irq8_0),
1799 SH_PFC_PIN_GROUP(intc_irq8_1),
1800 SH_PFC_PIN_GROUP(intc_irq9_0),
1801 SH_PFC_PIN_GROUP(intc_irq9_1),
1802 SH_PFC_PIN_GROUP(intc_irq10),
1803 SH_PFC_PIN_GROUP(intc_irq11),
1804 SH_PFC_PIN_GROUP(intc_irq12_0),
1805 SH_PFC_PIN_GROUP(intc_irq12_1),
1806 SH_PFC_PIN_GROUP(intc_irq13_0),
1807 SH_PFC_PIN_GROUP(intc_irq13_1),
1808 SH_PFC_PIN_GROUP(intc_irq14_0),
1809 SH_PFC_PIN_GROUP(intc_irq14_1),
1810 SH_PFC_PIN_GROUP(intc_irq15_0),
1811 SH_PFC_PIN_GROUP(intc_irq15_1),
1812 SH_PFC_PIN_GROUP(intc_irq16_0),
1813 SH_PFC_PIN_GROUP(intc_irq16_1),
1814 SH_PFC_PIN_GROUP(intc_irq17),
1815 SH_PFC_PIN_GROUP(intc_irq18),
1816 SH_PFC_PIN_GROUP(intc_irq19),
1817 SH_PFC_PIN_GROUP(intc_irq20),
1818 SH_PFC_PIN_GROUP(intc_irq21),
1819 SH_PFC_PIN_GROUP(intc_irq22),
1820 SH_PFC_PIN_GROUP(intc_irq23),
1821 SH_PFC_PIN_GROUP(intc_irq24),
1822 SH_PFC_PIN_GROUP(intc_irq25),
1823 SH_PFC_PIN_GROUP(intc_irq26_0),
1824 SH_PFC_PIN_GROUP(intc_irq26_1),
1825 SH_PFC_PIN_GROUP(intc_irq27_0),
1826 SH_PFC_PIN_GROUP(intc_irq27_1),
1827 SH_PFC_PIN_GROUP(intc_irq28_0),
1828 SH_PFC_PIN_GROUP(intc_irq28_1),
1829 SH_PFC_PIN_GROUP(intc_irq29_0),
1830 SH_PFC_PIN_GROUP(intc_irq29_1),
1831 SH_PFC_PIN_GROUP(intc_irq30_0),
1832 SH_PFC_PIN_GROUP(intc_irq30_1),
1833 SH_PFC_PIN_GROUP(intc_irq31_0),
1834 SH_PFC_PIN_GROUP(intc_irq31_1),
1835 SH_PFC_PIN_GROUP(keysc_in04_0),
1836 SH_PFC_PIN_GROUP(keysc_in04_1),
1837 SH_PFC_PIN_GROUP(keysc_in5),
1838 SH_PFC_PIN_GROUP(keysc_in6),
1839 SH_PFC_PIN_GROUP(keysc_in7),
1840 SH_PFC_PIN_GROUP(keysc_out4),
1841 SH_PFC_PIN_GROUP(keysc_out5),
1842 SH_PFC_PIN_GROUP(keysc_out6),
1843 SH_PFC_PIN_GROUP(keysc_out8),
1844 SH_PFC_PIN_GROUP(lcd_data8),
1845 SH_PFC_PIN_GROUP(lcd_data9),
1846 SH_PFC_PIN_GROUP(lcd_data12),
1847 SH_PFC_PIN_GROUP(lcd_data16),
1848 SH_PFC_PIN_GROUP(lcd_data18),
1849 SH_PFC_PIN_GROUP(lcd_data24),
1850 SH_PFC_PIN_GROUP(lcd_display),
1851 SH_PFC_PIN_GROUP(lcd_lclk),
1852 SH_PFC_PIN_GROUP(lcd_sync),
1853 SH_PFC_PIN_GROUP(lcd_sys),
1078 SH_PFC_PIN_GROUP(mmc0_data1_0), 1854 SH_PFC_PIN_GROUP(mmc0_data1_0),
1079 SH_PFC_PIN_GROUP(mmc0_data4_0), 1855 SH_PFC_PIN_GROUP(mmc0_data4_0),
1080 SH_PFC_PIN_GROUP(mmc0_data8_0), 1856 SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1083 SH_PFC_PIN_GROUP(mmc0_data4_1), 1859 SH_PFC_PIN_GROUP(mmc0_data4_1),
1084 SH_PFC_PIN_GROUP(mmc0_data8_1), 1860 SH_PFC_PIN_GROUP(mmc0_data8_1),
1085 SH_PFC_PIN_GROUP(mmc0_ctrl_1), 1861 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1862 SH_PFC_PIN_GROUP(scifa0_data),
1863 SH_PFC_PIN_GROUP(scifa0_clk),
1864 SH_PFC_PIN_GROUP(scifa0_ctrl),
1865 SH_PFC_PIN_GROUP(scifa1_data),
1866 SH_PFC_PIN_GROUP(scifa1_clk),
1867 SH_PFC_PIN_GROUP(scifa1_ctrl),
1868 SH_PFC_PIN_GROUP(scifa2_data),
1869 SH_PFC_PIN_GROUP(scifa2_clk),
1870 SH_PFC_PIN_GROUP(scifa2_ctrl),
1871 SH_PFC_PIN_GROUP(scifa3_data),
1872 SH_PFC_PIN_GROUP(scifa3_clk),
1873 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
1874 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
1875 SH_PFC_PIN_GROUP(scifa4_data),
1876 SH_PFC_PIN_GROUP(scifa5_data),
1877 SH_PFC_PIN_GROUP(scifb_data),
1878 SH_PFC_PIN_GROUP(scifb_clk),
1879 SH_PFC_PIN_GROUP(scifb_ctrl),
1086 SH_PFC_PIN_GROUP(sdhi0_data1), 1880 SH_PFC_PIN_GROUP(sdhi0_data1),
1087 SH_PFC_PIN_GROUP(sdhi0_data4), 1881 SH_PFC_PIN_GROUP(sdhi0_data4),
1088 SH_PFC_PIN_GROUP(sdhi0_ctrl), 1882 SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1094 SH_PFC_PIN_GROUP(sdhi2_data1), 1888 SH_PFC_PIN_GROUP(sdhi2_data1),
1095 SH_PFC_PIN_GROUP(sdhi2_data4), 1889 SH_PFC_PIN_GROUP(sdhi2_data4),
1096 SH_PFC_PIN_GROUP(sdhi2_ctrl), 1890 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1891 SH_PFC_PIN_GROUP(usb0_vbus),
1892 SH_PFC_PIN_GROUP(usb0_otg_id),
1893 SH_PFC_PIN_GROUP(usb0_otg_ctrl),
1894 SH_PFC_PIN_GROUP(usb1_vbus),
1895 SH_PFC_PIN_GROUP(usb1_otg_id_0),
1896 SH_PFC_PIN_GROUP(usb1_otg_id_1),
1897 SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
1898 SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
1899};
1900
1901static const char * const bsc_groups[] = {
1902 "bsc_data8",
1903 "bsc_data16",
1904 "bsc_cs0",
1905 "bsc_cs2",
1906 "bsc_cs4",
1907 "bsc_cs5a",
1908 "bsc_cs5b",
1909 "bsc_cs6a",
1910 "bsc_rd_we8",
1911 "bsc_rd_we16",
1912 "bsc_bs",
1913 "bsc_rdwr",
1914};
1915
1916static const char * const ceu_groups[] = {
1917 "ceu_data_0_7",
1918 "ceu_data_8_15",
1919 "ceu_clk_0",
1920 "ceu_clk_1",
1921 "ceu_clk_2",
1922 "ceu_sync",
1923 "ceu_field",
1924};
1925
1926static const char * const flctl_groups[] = {
1927 "flctl_data",
1928 "flctl_ce0",
1929 "flctl_ce1",
1930 "flctl_ctrl",
1931};
1932
1933static const char * const fsia_groups[] = {
1934 "fsia_mclk_in",
1935 "fsia_mclk_out",
1936 "fsia_sclk_in",
1937 "fsia_sclk_out",
1938 "fsia_data_in",
1939 "fsia_data_out",
1940 "fsia_spdif_0",
1941 "fsia_spdif_1",
1942};
1943
1944static const char * const fsib_groups[] = {
1945 "fsib_mclk_in",
1946};
1947
1948static const char * const hdmi_groups[] = {
1949 "hdmi",
1950};
1951
1952static const char * const intc_groups[] = {
1953 "intc_irq0_0",
1954 "intc_irq0_1",
1955 "intc_irq1",
1956 "intc_irq2_0",
1957 "intc_irq2_1",
1958 "intc_irq3_0",
1959 "intc_irq3_1",
1960 "intc_irq4_0",
1961 "intc_irq4_1",
1962 "intc_irq5",
1963 "intc_irq6_0",
1964 "intc_irq6_1",
1965 "intc_irq7_0",
1966 "intc_irq7_1",
1967 "intc_irq8_0",
1968 "intc_irq8_1",
1969 "intc_irq9_0",
1970 "intc_irq9_1",
1971 "intc_irq10",
1972 "intc_irq11",
1973 "intc_irq12_0",
1974 "intc_irq12_1",
1975 "intc_irq13_0",
1976 "intc_irq13_1",
1977 "intc_irq14_0",
1978 "intc_irq14_1",
1979 "intc_irq15_0",
1980 "intc_irq15_1",
1981 "intc_irq16_0",
1982 "intc_irq16_1",
1983 "intc_irq17",
1984 "intc_irq18",
1985 "intc_irq19",
1986 "intc_irq20",
1987 "intc_irq21",
1988 "intc_irq22",
1989 "intc_irq23",
1990 "intc_irq24",
1991 "intc_irq25",
1992 "intc_irq26_0",
1993 "intc_irq26_1",
1994 "intc_irq27_0",
1995 "intc_irq27_1",
1996 "intc_irq28_0",
1997 "intc_irq28_1",
1998 "intc_irq29_0",
1999 "intc_irq29_1",
2000 "intc_irq30_0",
2001 "intc_irq30_1",
2002 "intc_irq31_0",
2003 "intc_irq31_1",
2004};
2005
2006static const char * const keysc_groups[] = {
2007 "keysc_in04_0",
2008 "keysc_in04_1",
2009 "keysc_in5",
2010 "keysc_in6",
2011 "keysc_in7",
2012 "keysc_out4",
2013 "keysc_out5",
2014 "keysc_out6",
2015 "keysc_out8",
2016};
2017
2018static const char * const lcd_groups[] = {
2019 "lcd_data8",
2020 "lcd_data9",
2021 "lcd_data12",
2022 "lcd_data16",
2023 "lcd_data18",
2024 "lcd_data24",
2025 "lcd_display",
2026 "lcd_lclk",
2027 "lcd_sync",
2028 "lcd_sys",
1097}; 2029};
1098 2030
1099static const char * const mmc0_groups[] = { 2031static const char * const mmc0_groups[] = {
@@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = {
1107 "mmc0_ctrl_1", 2039 "mmc0_ctrl_1",
1108}; 2040};
1109 2041
2042static const char * const scifa0_groups[] = {
2043 "scifa0_data",
2044 "scifa0_clk",
2045 "scifa0_ctrl",
2046};
2047
2048static const char * const scifa1_groups[] = {
2049 "scifa1_data",
2050 "scifa1_clk",
2051 "scifa1_ctrl",
2052};
2053
2054static const char * const scifa2_groups[] = {
2055 "scifa2_data",
2056 "scifa2_clk",
2057 "scifa2_ctrl",
2058};
2059
2060static const char * const scifa3_groups[] = {
2061 "scifa3_data",
2062 "scifa3_clk",
2063 "scifa3_ctrl_0",
2064 "scifa3_ctrl_1",
2065};
2066
2067static const char * const scifa4_groups[] = {
2068 "scifa4_data",
2069};
2070
2071static const char * const scifa5_groups[] = {
2072 "scifa5_data",
2073};
2074
2075static const char * const scifb_groups[] = {
2076 "scifb_data",
2077 "scifb_clk",
2078 "scifb_ctrl",
2079};
2080
1110static const char * const sdhi0_groups[] = { 2081static const char * const sdhi0_groups[] = {
1111 "sdhi0_data1", 2082 "sdhi0_data1",
1112 "sdhi0_data4", 2083 "sdhi0_data4",
@@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = {
1127 "sdhi2_ctrl", 2098 "sdhi2_ctrl",
1128}; 2099};
1129 2100
2101static const char * const usb0_groups[] = {
2102 "usb0_vbus",
2103 "usb0_otg_id",
2104 "usb0_otg_ctrl",
2105};
2106
2107static const char * const usb1_groups[] = {
2108 "usb1_vbus",
2109 "usb1_otg_id_0",
2110 "usb1_otg_id_1",
2111 "usb1_otg_ctrl_0",
2112 "usb1_otg_ctrl_1",
2113};
2114
1130static const struct sh_pfc_function pinmux_functions[] = { 2115static const struct sh_pfc_function pinmux_functions[] = {
2116 SH_PFC_FUNCTION(bsc),
2117 SH_PFC_FUNCTION(ceu),
2118 SH_PFC_FUNCTION(flctl),
2119 SH_PFC_FUNCTION(fsia),
2120 SH_PFC_FUNCTION(fsib),
2121 SH_PFC_FUNCTION(hdmi),
2122 SH_PFC_FUNCTION(intc),
2123 SH_PFC_FUNCTION(keysc),
2124 SH_PFC_FUNCTION(lcd),
1131 SH_PFC_FUNCTION(mmc0), 2125 SH_PFC_FUNCTION(mmc0),
2126 SH_PFC_FUNCTION(scifa0),
2127 SH_PFC_FUNCTION(scifa1),
2128 SH_PFC_FUNCTION(scifa2),
2129 SH_PFC_FUNCTION(scifa3),
2130 SH_PFC_FUNCTION(scifa4),
2131 SH_PFC_FUNCTION(scifa5),
2132 SH_PFC_FUNCTION(scifb),
1132 SH_PFC_FUNCTION(sdhi0), 2133 SH_PFC_FUNCTION(sdhi0),
1133 SH_PFC_FUNCTION(sdhi1), 2134 SH_PFC_FUNCTION(sdhi1),
1134 SH_PFC_FUNCTION(sdhi2), 2135 SH_PFC_FUNCTION(sdhi2),
2136 SH_PFC_FUNCTION(usb0),
2137 SH_PFC_FUNCTION(usb1),
1135}; 2138};
1136 2139
1137#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 2140#undef PORTCR
1138 2141#define PORTCR(nr, reg) \
1139static const struct pinmux_func pinmux_func_gpios[] = { 2142 { \
1140 /* IRQ */ 2143 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1141 GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), 2144 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
1142 GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), 2145 PORT##nr##_FN0, PORT##nr##_FN1, \
1143 GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), 2146 PORT##nr##_FN2, PORT##nr##_FN3, \
1144 GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), 2147 PORT##nr##_FN4, PORT##nr##_FN5, \
1145 GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), 2148 PORT##nr##_FN6, PORT##nr##_FN7 } \
1146 GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), 2149 }
1147 GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80),
1148 GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145),
1149 GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83),
1150 GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170),
1151 GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19),
1152 GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22),
1153 GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25),
1154 GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122),
1155 GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181),
1156 GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130),
1157 GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184),
1158
1159 /* MSIOF0 */
1160 GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD),
1161 GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0),
1162 GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2),
1163 GPIO_FN(MSIOF0_TXD),
1164
1165 /* MSIOF1 */
1166 GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88),
1167 GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89),
1168 GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90),
1169 GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91),
1170 GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92),
1171 GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93),
1172 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1173 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1174
1175 /* MSIOF2 */
1176 GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0),
1177 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2),
1178 GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD),
1179 GPIO_FN(MSIOF2_TXD),
1180
1181 /* BBIF1 */
1182 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK),
1183 GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
1184 GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N),
1185
1186 /* BBIF2 */
1187 GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1),
1188 GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD),
1189
1190 /* FSI */
1191 GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR),
1192 GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC),
1193 GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD),
1194 GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15),
1195
1196 /* FMSI */
1197 GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR),
1198 GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD),
1199 GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT),
1200 GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK),
1201
1202 /* SCIFA0 */
1203 GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK),
1204 GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS),
1205
1206 /* SCIFA1 */
1207 GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK),
1208 GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS),
1209
1210 /* SCIFA2 */
1211 GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1),
1212 GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1),
1213
1214 /* SCIFA3 */
1215 GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140),
1216 GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141),
1217 GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD),
1218 GPIO_FN(SCIFA3_RXD),
1219
1220 /* SCIFA4 */
1221 GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD),
1222
1223 /* SCIFA5 */
1224 GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD),
1225
1226 /* SCIFB */
1227 GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS),
1228 GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD),
1229
1230 /* CEU */
1231 GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2),
1232 GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
1233 GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1),
1234 GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4),
1235 GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7),
1236 GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10),
1237 GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13),
1238 GPIO_FN(VIO_D14), GPIO_FN(VIO_D15),
1239
1240 /* USB0 */
1241 GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0),
1242 GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0),
1243
1244 /* USB1 */
1245 GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113),
1246 GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162),
1247 GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138),
1248 GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1),
1249 GPIO_FN(VBUS0_1),
1250
1251 /* GPIO */
1252 GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1),
1253
1254 /* BSC */
1255 GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO),
1256 GPIO_FN(WAIT), GPIO_FN(RDWR),
1257
1258 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2),
1259 GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7),
1260 GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10),
1261 GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
1262 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16),
1263 GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19),
1264 GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22),
1265 GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
1266 GPIO_FN(A26),
1267
1268 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
1269 GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A),
1270
1271 /* BSC/FLCTL */
1272 GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE),
1273 GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1),
1274 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4),
1275 GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7),
1276 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10),
1277 GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
1278 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
1279
1280 /* SPU2 */
1281 GPIO_FN(VINT_I),
1282
1283 /* FLCTL */
1284 GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB),
1285
1286 /* HSI */
1287 GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY),
1288 GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA),
1289 GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE),
1290
1291 /* MFI */
1292 GPIO_FN(MFIv6),
1293 GPIO_FN(MFIv4),
1294
1295 GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0),
1296 GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1),
1297 GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE),
1298 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT),
1299
1300 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1301 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1302 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1303 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1304 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1305 GPIO_FN(MEMC_AD15),
1306
1307 /* SIM */
1308 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D),
1309
1310 /* TPU */
1311 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93),
1312 GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3),
1313
1314 /* I2C2 */
1315 GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2),
1316
1317 /* I2C3(1) */
1318 GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3),
1319
1320 /* I2C3(2) */
1321 GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S),
1322
1323 /* I2C4(2) */
1324 GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4),
1325
1326 /* I2C4(2) */
1327 GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S),
1328
1329 /* KEYSC */
1330 GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136),
1331 GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135),
1332 GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134),
1333 GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133),
1334 GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5),
1335 GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6),
1336 GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7),
1337
1338 /* LCDC */
1339 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
1340 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD),
1341 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
1342 GPIO_FN(LCDDON),
1343
1344 GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2),
1345 GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5),
1346 GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8),
1347 GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11),
1348 GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14),
1349 GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17),
1350 GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20),
1351 GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23),
1352
1353 GPIO_FN(LCDC0_SELECT),
1354 GPIO_FN(LCDC1_SELECT),
1355
1356 /* IRDA */
1357 GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
1358 GPIO_FN(IROUT_139), GPIO_FN(IROUT_140),
1359
1360 /* TSIF1 */
1361 GPIO_FN(TS0_1SELECT),
1362 GPIO_FN(TS0_2SELECT),
1363 GPIO_FN(TS1_1SELECT),
1364 GPIO_FN(TS1_2SELECT),
1365
1366 GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1),
1367 GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1),
1368
1369 /* TSIF2 */
1370 GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2),
1371 GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2),
1372
1373 /* HDMI */
1374 GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
1375
1376 /* SDENC */
1377 GPIO_FN(SDENC_CPG),
1378 GPIO_FN(SDENC_DV_CLKI),
1379};
1380 2150
1381static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2151static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1382 PORTCR(0, 0xE6051000), /* PORT0CR */ 2152 PORTCR(0, 0xE6051000), /* PORT0CR */
@@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
1776#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) 2546#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
1777#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) 2547#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
1778static const struct pinmux_irq pinmux_irqs[] = { 2548static const struct pinmux_irq pinmux_irqs[] = {
1779 PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), 2549 PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
1780 PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), 2550 PINMUX_IRQ(EXT_IRQ16L(1), 12),
1781 PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), 2551 PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
1782 PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), 2552 PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
1783 PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), 2553 PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
1784 PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), 2554 PINMUX_IRQ(EXT_IRQ16L(5), 18),
1785 PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), 2555 PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
1786 PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), 2556 PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
1787 PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), 2557 PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
1788 PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), 2558 PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
1789 PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), 2559 PINMUX_IRQ(EXT_IRQ16L(10), 65),
1790 PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), 2560 PINMUX_IRQ(EXT_IRQ16L(11), 67),
1791 PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), 2561 PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
1792 PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), 2562 PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
1793 PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), 2563 PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
1794 PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), 2564 PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
1795 PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), 2565 PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
1796 PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), 2566 PINMUX_IRQ(EXT_IRQ16H(17), 85),
1797 PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), 2567 PINMUX_IRQ(EXT_IRQ16H(18), 86),
1798 PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), 2568 PINMUX_IRQ(EXT_IRQ16H(19), 87),
1799 PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), 2569 PINMUX_IRQ(EXT_IRQ16H(20), 92),
1800 PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), 2570 PINMUX_IRQ(EXT_IRQ16H(21), 93),
1801 PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), 2571 PINMUX_IRQ(EXT_IRQ16H(22), 94),
1802 PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), 2572 PINMUX_IRQ(EXT_IRQ16H(23), 95),
1803 PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), 2573 PINMUX_IRQ(EXT_IRQ16H(24), 112),
1804 PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), 2574 PINMUX_IRQ(EXT_IRQ16H(25), 119),
1805 PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), 2575 PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
1806 PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), 2576 PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
1807 PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), 2577 PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
1808 PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), 2578 PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
1809 PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), 2579 PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
1810 PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), 2580 PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
2581};
2582
2583#define PORTnCR_PULMD_OFF (0 << 6)
2584#define PORTnCR_PULMD_DOWN (2 << 6)
2585#define PORTnCR_PULMD_UP (3 << 6)
2586#define PORTnCR_PULMD_MASK (3 << 6)
2587
2588struct sh7372_portcr_group {
2589 unsigned int end_pin;
2590 unsigned int offset;
2591};
2592
2593static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
2594 { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 },
2595 { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
2596};
2597
2598static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2599{
2600 unsigned int i;
2601
2602 for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
2603 const struct sh7372_portcr_group *group =
2604 &sh7372_portcr_offsets[i];
2605
2606 if (i <= group->end_pin)
2607 return pfc->window->virt + group->offset + pin;
2608 }
2609
2610 return NULL;
2611}
2612
2613static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
2614{
2615 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2616 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
2617
2618 switch (value) {
2619 case PORTnCR_PULMD_UP:
2620 return PIN_CONFIG_BIAS_PULL_UP;
2621 case PORTnCR_PULMD_DOWN:
2622 return PIN_CONFIG_BIAS_PULL_DOWN;
2623 case PORTnCR_PULMD_OFF:
2624 default:
2625 return PIN_CONFIG_BIAS_DISABLE;
2626 }
2627}
2628
2629static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2630 unsigned int bias)
2631{
2632 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2633 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
2634
2635 switch (bias) {
2636 case PIN_CONFIG_BIAS_PULL_UP:
2637 value |= PORTnCR_PULMD_UP;
2638 break;
2639 case PIN_CONFIG_BIAS_PULL_DOWN:
2640 value |= PORTnCR_PULMD_DOWN;
2641 break;
2642 }
2643
2644 iowrite8(value, addr);
2645}
2646
2647static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
2648 .get_bias = sh7372_pinmux_get_bias,
2649 .set_bias = sh7372_pinmux_set_bias,
1811}; 2650};
1812 2651
1813const struct sh_pfc_soc_info sh7372_pinmux_info = { 2652const struct sh_pfc_soc_info sh7372_pinmux_info = {
1814 .name = "sh7372_pfc", 2653 .name = "sh7372_pfc",
2654 .ops = &sh7372_pinmux_ops,
2655
1815 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2656 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1816 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1817 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1818 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2657 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1819 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2658 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1820 2659
@@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
1825 .functions = pinmux_functions, 2664 .functions = pinmux_functions,
1826 .nr_functions = ARRAY_SIZE(pinmux_functions), 2665 .nr_functions = ARRAY_SIZE(pinmux_functions),
1827 2666
1828 .func_gpios = pinmux_func_gpios,
1829 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1830
1831 .cfg_regs = pinmux_config_regs, 2667 .cfg_regs = pinmux_config_regs,
1832 .data_regs = pinmux_data_regs, 2668 .data_regs = pinmux_data_regs,
1833 2669
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 00:59:02 -0400