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-rw-r--r--drivers/pinctrl/qcom/Kconfig42
-rw-r--r--drivers/pinctrl/qcom/Makefile6
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8064.c630
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq8064.c668
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c919
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h121
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8960.c1282
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8x74.c1067
8 files changed, 4735 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
new file mode 100644
index 000000000000..d160a710d704
--- /dev/null
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -0,0 +1,42 @@
1if (ARCH_QCOM || COMPILE_TEST)
2
3config PINCTRL_MSM
4 bool
5 select PINMUX
6 select PINCONF
7 select GENERIC_PINCONF
8 select GPIOLIB_IRQCHIP
9
10config PINCTRL_APQ8064
11 tristate "Qualcomm APQ8064 pin controller driver"
12 depends on GPIOLIB && OF
13 select PINCTRL_MSM
14 help
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
17
18config PINCTRL_IPQ8064
19 tristate "Qualcomm IPQ8064 pin controller driver"
20 depends on GPIOLIB && OF
21 select PINCTRL_MSM
22 help
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
24 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
25
26config PINCTRL_MSM8960
27 tristate "Qualcomm 8960 pin controller driver"
28 depends on GPIOLIB && OF
29 select PINCTRL_MSM
30 help
31 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
32 Qualcomm TLMM block found in the Qualcomm 8960 platform.
33
34config PINCTRL_MSM8X74
35 tristate "Qualcomm 8x74 pin controller driver"
36 depends on GPIOLIB && OF
37 select PINCTRL_MSM
38 help
39 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
40 Qualcomm TLMM block found in the Qualcomm 8974 platform.
41
42endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
new file mode 100644
index 000000000000..2a02602d715c
--- /dev/null
+++ b/drivers/pinctrl/qcom/Makefile
@@ -0,0 +1,6 @@
1# Qualcomm pin control drivers
2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
4obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
5obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
6obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
new file mode 100644
index 000000000000..feb6f152f9b7
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -0,0 +1,630 @@
1/*
2 * Copyright (c) 2014, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-msm.h"
20
21static const struct pinctrl_pin_desc apq8064_pins[] = {
22 PINCTRL_PIN(0, "GPIO_0"),
23 PINCTRL_PIN(1, "GPIO_1"),
24 PINCTRL_PIN(2, "GPIO_2"),
25 PINCTRL_PIN(3, "GPIO_3"),
26 PINCTRL_PIN(4, "GPIO_4"),
27 PINCTRL_PIN(5, "GPIO_5"),
28 PINCTRL_PIN(6, "GPIO_6"),
29 PINCTRL_PIN(7, "GPIO_7"),
30 PINCTRL_PIN(8, "GPIO_8"),
31 PINCTRL_PIN(9, "GPIO_9"),
32 PINCTRL_PIN(10, "GPIO_10"),
33 PINCTRL_PIN(11, "GPIO_11"),
34 PINCTRL_PIN(12, "GPIO_12"),
35 PINCTRL_PIN(13, "GPIO_13"),
36 PINCTRL_PIN(14, "GPIO_14"),
37 PINCTRL_PIN(15, "GPIO_15"),
38 PINCTRL_PIN(16, "GPIO_16"),
39 PINCTRL_PIN(17, "GPIO_17"),
40 PINCTRL_PIN(18, "GPIO_18"),
41 PINCTRL_PIN(19, "GPIO_19"),
42 PINCTRL_PIN(20, "GPIO_20"),
43 PINCTRL_PIN(21, "GPIO_21"),
44 PINCTRL_PIN(22, "GPIO_22"),
45 PINCTRL_PIN(23, "GPIO_23"),
46 PINCTRL_PIN(24, "GPIO_24"),
47 PINCTRL_PIN(25, "GPIO_25"),
48 PINCTRL_PIN(26, "GPIO_26"),
49 PINCTRL_PIN(27, "GPIO_27"),
50 PINCTRL_PIN(28, "GPIO_28"),
51 PINCTRL_PIN(29, "GPIO_29"),
52 PINCTRL_PIN(30, "GPIO_30"),
53 PINCTRL_PIN(31, "GPIO_31"),
54 PINCTRL_PIN(32, "GPIO_32"),
55 PINCTRL_PIN(33, "GPIO_33"),
56 PINCTRL_PIN(34, "GPIO_34"),
57 PINCTRL_PIN(35, "GPIO_35"),
58 PINCTRL_PIN(36, "GPIO_36"),
59 PINCTRL_PIN(37, "GPIO_37"),
60 PINCTRL_PIN(38, "GPIO_38"),
61 PINCTRL_PIN(39, "GPIO_39"),
62 PINCTRL_PIN(40, "GPIO_40"),
63 PINCTRL_PIN(41, "GPIO_41"),
64 PINCTRL_PIN(42, "GPIO_42"),
65 PINCTRL_PIN(43, "GPIO_43"),
66 PINCTRL_PIN(44, "GPIO_44"),
67 PINCTRL_PIN(45, "GPIO_45"),
68 PINCTRL_PIN(46, "GPIO_46"),
69 PINCTRL_PIN(47, "GPIO_47"),
70 PINCTRL_PIN(48, "GPIO_48"),
71 PINCTRL_PIN(49, "GPIO_49"),
72 PINCTRL_PIN(50, "GPIO_50"),
73 PINCTRL_PIN(51, "GPIO_51"),
74 PINCTRL_PIN(52, "GPIO_52"),
75 PINCTRL_PIN(53, "GPIO_53"),
76 PINCTRL_PIN(54, "GPIO_54"),
77 PINCTRL_PIN(55, "GPIO_55"),
78 PINCTRL_PIN(56, "GPIO_56"),
79 PINCTRL_PIN(57, "GPIO_57"),
80 PINCTRL_PIN(58, "GPIO_58"),
81 PINCTRL_PIN(59, "GPIO_59"),
82 PINCTRL_PIN(60, "GPIO_60"),
83 PINCTRL_PIN(61, "GPIO_61"),
84 PINCTRL_PIN(62, "GPIO_62"),
85 PINCTRL_PIN(63, "GPIO_63"),
86 PINCTRL_PIN(64, "GPIO_64"),
87 PINCTRL_PIN(65, "GPIO_65"),
88 PINCTRL_PIN(66, "GPIO_66"),
89 PINCTRL_PIN(67, "GPIO_67"),
90 PINCTRL_PIN(68, "GPIO_68"),
91 PINCTRL_PIN(69, "GPIO_69"),
92 PINCTRL_PIN(70, "GPIO_70"),
93 PINCTRL_PIN(71, "GPIO_71"),
94 PINCTRL_PIN(72, "GPIO_72"),
95 PINCTRL_PIN(73, "GPIO_73"),
96 PINCTRL_PIN(74, "GPIO_74"),
97 PINCTRL_PIN(75, "GPIO_75"),
98 PINCTRL_PIN(76, "GPIO_76"),
99 PINCTRL_PIN(77, "GPIO_77"),
100 PINCTRL_PIN(78, "GPIO_78"),
101 PINCTRL_PIN(79, "GPIO_79"),
102 PINCTRL_PIN(80, "GPIO_80"),
103 PINCTRL_PIN(81, "GPIO_81"),
104 PINCTRL_PIN(82, "GPIO_82"),
105 PINCTRL_PIN(83, "GPIO_83"),
106 PINCTRL_PIN(84, "GPIO_84"),
107 PINCTRL_PIN(85, "GPIO_85"),
108 PINCTRL_PIN(86, "GPIO_86"),
109 PINCTRL_PIN(87, "GPIO_87"),
110 PINCTRL_PIN(88, "GPIO_88"),
111 PINCTRL_PIN(89, "GPIO_89"),
112
113 PINCTRL_PIN(90, "SDC1_CLK"),
114 PINCTRL_PIN(91, "SDC1_CMD"),
115 PINCTRL_PIN(92, "SDC1_DATA"),
116 PINCTRL_PIN(93, "SDC3_CLK"),
117 PINCTRL_PIN(94, "SDC3_CMD"),
118 PINCTRL_PIN(95, "SDC3_DATA"),
119};
120
121#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
122DECLARE_APQ_GPIO_PINS(0);
123DECLARE_APQ_GPIO_PINS(1);
124DECLARE_APQ_GPIO_PINS(2);
125DECLARE_APQ_GPIO_PINS(3);
126DECLARE_APQ_GPIO_PINS(4);
127DECLARE_APQ_GPIO_PINS(5);
128DECLARE_APQ_GPIO_PINS(6);
129DECLARE_APQ_GPIO_PINS(7);
130DECLARE_APQ_GPIO_PINS(8);
131DECLARE_APQ_GPIO_PINS(9);
132DECLARE_APQ_GPIO_PINS(10);
133DECLARE_APQ_GPIO_PINS(11);
134DECLARE_APQ_GPIO_PINS(12);
135DECLARE_APQ_GPIO_PINS(13);
136DECLARE_APQ_GPIO_PINS(14);
137DECLARE_APQ_GPIO_PINS(15);
138DECLARE_APQ_GPIO_PINS(16);
139DECLARE_APQ_GPIO_PINS(17);
140DECLARE_APQ_GPIO_PINS(18);
141DECLARE_APQ_GPIO_PINS(19);
142DECLARE_APQ_GPIO_PINS(20);
143DECLARE_APQ_GPIO_PINS(21);
144DECLARE_APQ_GPIO_PINS(22);
145DECLARE_APQ_GPIO_PINS(23);
146DECLARE_APQ_GPIO_PINS(24);
147DECLARE_APQ_GPIO_PINS(25);
148DECLARE_APQ_GPIO_PINS(26);
149DECLARE_APQ_GPIO_PINS(27);
150DECLARE_APQ_GPIO_PINS(28);
151DECLARE_APQ_GPIO_PINS(29);
152DECLARE_APQ_GPIO_PINS(30);
153DECLARE_APQ_GPIO_PINS(31);
154DECLARE_APQ_GPIO_PINS(32);
155DECLARE_APQ_GPIO_PINS(33);
156DECLARE_APQ_GPIO_PINS(34);
157DECLARE_APQ_GPIO_PINS(35);
158DECLARE_APQ_GPIO_PINS(36);
159DECLARE_APQ_GPIO_PINS(37);
160DECLARE_APQ_GPIO_PINS(38);
161DECLARE_APQ_GPIO_PINS(39);
162DECLARE_APQ_GPIO_PINS(40);
163DECLARE_APQ_GPIO_PINS(41);
164DECLARE_APQ_GPIO_PINS(42);
165DECLARE_APQ_GPIO_PINS(43);
166DECLARE_APQ_GPIO_PINS(44);
167DECLARE_APQ_GPIO_PINS(45);
168DECLARE_APQ_GPIO_PINS(46);
169DECLARE_APQ_GPIO_PINS(47);
170DECLARE_APQ_GPIO_PINS(48);
171DECLARE_APQ_GPIO_PINS(49);
172DECLARE_APQ_GPIO_PINS(50);
173DECLARE_APQ_GPIO_PINS(51);
174DECLARE_APQ_GPIO_PINS(52);
175DECLARE_APQ_GPIO_PINS(53);
176DECLARE_APQ_GPIO_PINS(54);
177DECLARE_APQ_GPIO_PINS(55);
178DECLARE_APQ_GPIO_PINS(56);
179DECLARE_APQ_GPIO_PINS(57);
180DECLARE_APQ_GPIO_PINS(58);
181DECLARE_APQ_GPIO_PINS(59);
182DECLARE_APQ_GPIO_PINS(60);
183DECLARE_APQ_GPIO_PINS(61);
184DECLARE_APQ_GPIO_PINS(62);
185DECLARE_APQ_GPIO_PINS(63);
186DECLARE_APQ_GPIO_PINS(64);
187DECLARE_APQ_GPIO_PINS(65);
188DECLARE_APQ_GPIO_PINS(66);
189DECLARE_APQ_GPIO_PINS(67);
190DECLARE_APQ_GPIO_PINS(68);
191DECLARE_APQ_GPIO_PINS(69);
192DECLARE_APQ_GPIO_PINS(70);
193DECLARE_APQ_GPIO_PINS(71);
194DECLARE_APQ_GPIO_PINS(72);
195DECLARE_APQ_GPIO_PINS(73);
196DECLARE_APQ_GPIO_PINS(74);
197DECLARE_APQ_GPIO_PINS(75);
198DECLARE_APQ_GPIO_PINS(76);
199DECLARE_APQ_GPIO_PINS(77);
200DECLARE_APQ_GPIO_PINS(78);
201DECLARE_APQ_GPIO_PINS(79);
202DECLARE_APQ_GPIO_PINS(80);
203DECLARE_APQ_GPIO_PINS(81);
204DECLARE_APQ_GPIO_PINS(82);
205DECLARE_APQ_GPIO_PINS(83);
206DECLARE_APQ_GPIO_PINS(84);
207DECLARE_APQ_GPIO_PINS(85);
208DECLARE_APQ_GPIO_PINS(86);
209DECLARE_APQ_GPIO_PINS(87);
210DECLARE_APQ_GPIO_PINS(88);
211DECLARE_APQ_GPIO_PINS(89);
212
213static const unsigned int sdc1_clk_pins[] = { 90 };
214static const unsigned int sdc1_cmd_pins[] = { 91 };
215static const unsigned int sdc1_data_pins[] = { 92 };
216static const unsigned int sdc3_clk_pins[] = { 93 };
217static const unsigned int sdc3_cmd_pins[] = { 94 };
218static const unsigned int sdc3_data_pins[] = { 95 };
219
220#define FUNCTION(fname) \
221 [APQ_MUX_##fname] = { \
222 .name = #fname, \
223 .groups = fname##_groups, \
224 .ngroups = ARRAY_SIZE(fname##_groups), \
225 }
226
227#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
228 { \
229 .name = "gpio" #id, \
230 .pins = gpio##id##_pins, \
231 .npins = ARRAY_SIZE(gpio##id##_pins), \
232 .funcs = (int[]){ \
233 APQ_MUX_gpio, \
234 APQ_MUX_##f1, \
235 APQ_MUX_##f2, \
236 APQ_MUX_##f3, \
237 APQ_MUX_##f4, \
238 APQ_MUX_##f5, \
239 APQ_MUX_##f6, \
240 APQ_MUX_##f7, \
241 APQ_MUX_##f8, \
242 APQ_MUX_##f9, \
243 APQ_MUX_##f10, \
244 }, \
245 .nfuncs = 11, \
246 .ctl_reg = 0x1000 + 0x10 * id, \
247 .io_reg = 0x1004 + 0x10 * id, \
248 .intr_cfg_reg = 0x1008 + 0x10 * id, \
249 .intr_status_reg = 0x100c + 0x10 * id, \
250 .intr_target_reg = 0x400 + 0x4 * id, \
251 .mux_bit = 2, \
252 .pull_bit = 0, \
253 .drv_bit = 6, \
254 .oe_bit = 9, \
255 .in_bit = 0, \
256 .out_bit = 1, \
257 .intr_enable_bit = 0, \
258 .intr_status_bit = 0, \
259 .intr_ack_high = 1, \
260 .intr_target_bit = 0, \
261 .intr_raw_status_bit = 3, \
262 .intr_polarity_bit = 1, \
263 .intr_detection_bit = 2, \
264 .intr_detection_width = 1, \
265 }
266
267#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
268 { \
269 .name = #pg_name, \
270 .pins = pg_name##_pins, \
271 .npins = ARRAY_SIZE(pg_name##_pins), \
272 .ctl_reg = ctl, \
273 .io_reg = 0, \
274 .intr_cfg_reg = 0, \
275 .intr_status_reg = 0, \
276 .intr_target_reg = 0, \
277 .mux_bit = -1, \
278 .pull_bit = pull, \
279 .drv_bit = drv, \
280 .oe_bit = -1, \
281 .in_bit = -1, \
282 .out_bit = -1, \
283 .intr_enable_bit = -1, \
284 .intr_status_bit = -1, \
285 .intr_target_bit = -1, \
286 .intr_raw_status_bit = -1, \
287 .intr_polarity_bit = -1, \
288 .intr_detection_bit = -1, \
289 .intr_detection_width = -1, \
290 }
291
292enum apq8064_functions {
293 APQ_MUX_cam_mclk,
294 APQ_MUX_codec_mic_i2s,
295 APQ_MUX_codec_spkr_i2s,
296 APQ_MUX_gpio,
297 APQ_MUX_gsbi1,
298 APQ_MUX_gsbi2,
299 APQ_MUX_gsbi3,
300 APQ_MUX_gsbi4,
301 APQ_MUX_gsbi4_cam_i2c,
302 APQ_MUX_gsbi5,
303 APQ_MUX_gsbi5_spi_cs1,
304 APQ_MUX_gsbi5_spi_cs2,
305 APQ_MUX_gsbi5_spi_cs3,
306 APQ_MUX_gsbi6,
307 APQ_MUX_gsbi6_spi_cs1,
308 APQ_MUX_gsbi6_spi_cs2,
309 APQ_MUX_gsbi6_spi_cs3,
310 APQ_MUX_gsbi7,
311 APQ_MUX_gsbi7_spi_cs1,
312 APQ_MUX_gsbi7_spi_cs2,
313 APQ_MUX_gsbi7_spi_cs3,
314 APQ_MUX_gsbi_cam_i2c,
315 APQ_MUX_hdmi,
316 APQ_MUX_mi2s,
317 APQ_MUX_riva_bt,
318 APQ_MUX_riva_fm,
319 APQ_MUX_riva_wlan,
320 APQ_MUX_sdc2,
321 APQ_MUX_sdc4,
322 APQ_MUX_slimbus,
323 APQ_MUX_spkr_i2s,
324 APQ_MUX_tsif1,
325 APQ_MUX_tsif2,
326 APQ_MUX_usb2_hsic,
327 APQ_MUX_NA,
328};
329
330static const char * const cam_mclk_groups[] = {
331 "gpio4" "gpio5"
332};
333static const char * const codec_mic_i2s_groups[] = {
334 "gpio34", "gpio35", "gpio36", "gpio37", "gpio38"
335};
336static const char * const codec_spkr_i2s_groups[] = {
337 "gpio39", "gpio40", "gpio41", "gpio42"
338};
339static const char * const gpio_groups[] = {
340 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
341 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
342 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
343 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
344 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
345 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
346 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
347 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
348 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
349 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
350 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
351 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
352 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
353};
354static const char * const gsbi1_groups[] = {
355 "gpio18", "gpio19", "gpio20", "gpio21"
356};
357static const char * const gsbi2_groups[] = {
358 "gpio22", "gpio23", "gpio24", "gpio25"
359};
360static const char * const gsbi3_groups[] = {
361 "gpio6", "gpio7", "gpio8", "gpio9"
362};
363static const char * const gsbi4_groups[] = {
364 "gpio10", "gpio11", "gpio12", "gpio13"
365};
366static const char * const gsbi4_cam_i2c_groups[] = {
367 "gpio10", "gpio11", "gpio12", "gpio13"
368};
369static const char * const gsbi5_groups[] = {
370 "gpio51", "gpio52", "gpio53", "gpio54"
371};
372static const char * const gsbi5_spi_cs1_groups[] = {
373 "gpio47"
374};
375static const char * const gsbi5_spi_cs2_groups[] = {
376 "gpio31"
377};
378static const char * const gsbi5_spi_cs3_groups[] = {
379 "gpio32"
380};
381static const char * const gsbi6_groups[] = {
382 "gpio14", "gpio15", "gpio16", "gpio17"
383};
384static const char * const gsbi6_spi_cs1_groups[] = {
385 "gpio47"
386};
387static const char * const gsbi6_spi_cs2_groups[] = {
388 "gpio31"
389};
390static const char * const gsbi6_spi_cs3_groups[] = {
391 "gpio32"
392};
393static const char * const gsbi7_groups[] = {
394 "gpio82", "gpio83", "gpio84", "gpio85"
395};
396static const char * const gsbi7_spi_cs1_groups[] = {
397 "gpio47"
398};
399static const char * const gsbi7_spi_cs2_groups[] = {
400 "gpio31"
401};
402static const char * const gsbi7_spi_cs3_groups[] = {
403 "gpio32"
404};
405static const char * const gsbi_cam_i2c_groups[] = {
406 "gpio10", "gpio11", "gpio12", "gpio13"
407};
408static const char * const hdmi_groups[] = {
409 "gpio69", "gpio70", "gpio71", "gpio72"
410};
411static const char * const mi2s_groups[] = {
412 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33"
413};
414static const char * const riva_bt_groups[] = {
415 "gpio16", "gpio17"
416};
417static const char * const riva_fm_groups[] = {
418 "gpio14", "gpio15"
419};
420static const char * const riva_wlan_groups[] = {
421 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
422};
423static const char * const sdc2_groups[] = {
424 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62"
425};
426static const char * const sdc4_groups[] = {
427 "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
428};
429static const char * const slimbus_groups[] = {
430 "gpio40", "gpio41"
431};
432static const char * const spkr_i2s_groups[] = {
433 "gpio47", "gpio48", "gpio49", "gpio50"
434};
435static const char * const tsif1_groups[] = {
436 "gpio55", "gpio56", "gpio57"
437};
438static const char * const tsif2_groups[] = {
439 "gpio58", "gpio59", "gpio60"
440};
441static const char * const usb2_hsic_groups[] = {
442 "gpio88", "gpio89"
443};
444
445static const struct msm_function apq8064_functions[] = {
446 FUNCTION(cam_mclk),
447 FUNCTION(codec_mic_i2s),
448 FUNCTION(codec_spkr_i2s),
449 FUNCTION(gpio),
450 FUNCTION(gsbi1),
451 FUNCTION(gsbi2),
452 FUNCTION(gsbi3),
453 FUNCTION(gsbi4),
454 FUNCTION(gsbi4_cam_i2c),
455 FUNCTION(gsbi5),
456 FUNCTION(gsbi5_spi_cs1),
457 FUNCTION(gsbi5_spi_cs2),
458 FUNCTION(gsbi5_spi_cs3),
459 FUNCTION(gsbi6),
460 FUNCTION(gsbi6_spi_cs1),
461 FUNCTION(gsbi6_spi_cs2),
462 FUNCTION(gsbi6_spi_cs3),
463 FUNCTION(gsbi7),
464 FUNCTION(gsbi7_spi_cs1),
465 FUNCTION(gsbi7_spi_cs2),
466 FUNCTION(gsbi7_spi_cs3),
467 FUNCTION(gsbi_cam_i2c),
468 FUNCTION(hdmi),
469 FUNCTION(mi2s),
470 FUNCTION(riva_bt),
471 FUNCTION(riva_fm),
472 FUNCTION(riva_wlan),
473 FUNCTION(sdc2),
474 FUNCTION(sdc4),
475 FUNCTION(slimbus),
476 FUNCTION(spkr_i2s),
477 FUNCTION(tsif1),
478 FUNCTION(tsif2),
479 FUNCTION(usb2_hsic),
480};
481
482static const struct msm_pingroup apq8064_groups[] = {
483 PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
484 PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
485 PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
486 PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
487 PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA),
488 PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA),
489 PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
490 PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
491 PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
492 PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
493 PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA),
494 PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c),
495 PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA),
496 PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA),
497 PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
498 PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
499 PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
500 PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
501 PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
502 PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
503 PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
504 PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
505 PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
506 PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
507 PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
508 PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
509 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
510 PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
511 PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
512 PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
513 PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
514 PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA),
515 PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA),
516 PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
517 PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
518 PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
519 PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
520 PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
521 PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
522 PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
523 PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
524 PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
525 PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
526 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
527 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
528 PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
529 PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
530 PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA),
531 PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
532 PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
533 PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
534 PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
535 PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
536 PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
537 PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
538 PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
539 PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
540 PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
541 PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
543 PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
544 PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
545 PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
546 PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
547 PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
548 PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
549 PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
550 PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
551 PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
552 PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
553 PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
554 PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
555 PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
556 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
557 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
558 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
559 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
560 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
561 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
562 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
563 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
564 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
565 PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA),
566 PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
567 PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA),
568 PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA),
569 PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
570 PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
571 PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
572 PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
573
574 SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6),
575 SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3),
576 SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0),
577
578 SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6),
579 SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3),
580 SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0),
581};
582
583#define NUM_GPIO_PINGROUPS 90
584
585static const struct msm_pinctrl_soc_data apq8064_pinctrl = {
586 .pins = apq8064_pins,
587 .npins = ARRAY_SIZE(apq8064_pins),
588 .functions = apq8064_functions,
589 .nfunctions = ARRAY_SIZE(apq8064_functions),
590 .groups = apq8064_groups,
591 .ngroups = ARRAY_SIZE(apq8064_groups),
592 .ngpios = NUM_GPIO_PINGROUPS,
593};
594
595static int apq8064_pinctrl_probe(struct platform_device *pdev)
596{
597 return msm_pinctrl_probe(pdev, &apq8064_pinctrl);
598}
599
600static const struct of_device_id apq8064_pinctrl_of_match[] = {
601 { .compatible = "qcom,apq8064-pinctrl", },
602 { },
603};
604
605static struct platform_driver apq8064_pinctrl_driver = {
606 .driver = {
607 .name = "apq8064-pinctrl",
608 .owner = THIS_MODULE,
609 .of_match_table = apq8064_pinctrl_of_match,
610 },
611 .probe = apq8064_pinctrl_probe,
612 .remove = msm_pinctrl_remove,
613};
614
615static int __init apq8064_pinctrl_init(void)
616{
617 return platform_driver_register(&apq8064_pinctrl_driver);
618}
619arch_initcall(apq8064_pinctrl_init);
620
621static void __exit apq8064_pinctrl_exit(void)
622{
623 platform_driver_unregister(&apq8064_pinctrl_driver);
624}
625module_exit(apq8064_pinctrl_exit);
626
627MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
628MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver");
629MODULE_LICENSE("GPL v2");
630MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
new file mode 100644
index 000000000000..767cf1120b20
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -0,0 +1,668 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc ipq8064_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92
93 PINCTRL_PIN(69, "SDC3_CLK"),
94 PINCTRL_PIN(70, "SDC3_CMD"),
95 PINCTRL_PIN(71, "SDC3_DATA"),
96};
97
98#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
99DECLARE_IPQ_GPIO_PINS(0);
100DECLARE_IPQ_GPIO_PINS(1);
101DECLARE_IPQ_GPIO_PINS(2);
102DECLARE_IPQ_GPIO_PINS(3);
103DECLARE_IPQ_GPIO_PINS(4);
104DECLARE_IPQ_GPIO_PINS(5);
105DECLARE_IPQ_GPIO_PINS(6);
106DECLARE_IPQ_GPIO_PINS(7);
107DECLARE_IPQ_GPIO_PINS(8);
108DECLARE_IPQ_GPIO_PINS(9);
109DECLARE_IPQ_GPIO_PINS(10);
110DECLARE_IPQ_GPIO_PINS(11);
111DECLARE_IPQ_GPIO_PINS(12);
112DECLARE_IPQ_GPIO_PINS(13);
113DECLARE_IPQ_GPIO_PINS(14);
114DECLARE_IPQ_GPIO_PINS(15);
115DECLARE_IPQ_GPIO_PINS(16);
116DECLARE_IPQ_GPIO_PINS(17);
117DECLARE_IPQ_GPIO_PINS(18);
118DECLARE_IPQ_GPIO_PINS(19);
119DECLARE_IPQ_GPIO_PINS(20);
120DECLARE_IPQ_GPIO_PINS(21);
121DECLARE_IPQ_GPIO_PINS(22);
122DECLARE_IPQ_GPIO_PINS(23);
123DECLARE_IPQ_GPIO_PINS(24);
124DECLARE_IPQ_GPIO_PINS(25);
125DECLARE_IPQ_GPIO_PINS(26);
126DECLARE_IPQ_GPIO_PINS(27);
127DECLARE_IPQ_GPIO_PINS(28);
128DECLARE_IPQ_GPIO_PINS(29);
129DECLARE_IPQ_GPIO_PINS(30);
130DECLARE_IPQ_GPIO_PINS(31);
131DECLARE_IPQ_GPIO_PINS(32);
132DECLARE_IPQ_GPIO_PINS(33);
133DECLARE_IPQ_GPIO_PINS(34);
134DECLARE_IPQ_GPIO_PINS(35);
135DECLARE_IPQ_GPIO_PINS(36);
136DECLARE_IPQ_GPIO_PINS(37);
137DECLARE_IPQ_GPIO_PINS(38);
138DECLARE_IPQ_GPIO_PINS(39);
139DECLARE_IPQ_GPIO_PINS(40);
140DECLARE_IPQ_GPIO_PINS(41);
141DECLARE_IPQ_GPIO_PINS(42);
142DECLARE_IPQ_GPIO_PINS(43);
143DECLARE_IPQ_GPIO_PINS(44);
144DECLARE_IPQ_GPIO_PINS(45);
145DECLARE_IPQ_GPIO_PINS(46);
146DECLARE_IPQ_GPIO_PINS(47);
147DECLARE_IPQ_GPIO_PINS(48);
148DECLARE_IPQ_GPIO_PINS(49);
149DECLARE_IPQ_GPIO_PINS(50);
150DECLARE_IPQ_GPIO_PINS(51);
151DECLARE_IPQ_GPIO_PINS(52);
152DECLARE_IPQ_GPIO_PINS(53);
153DECLARE_IPQ_GPIO_PINS(54);
154DECLARE_IPQ_GPIO_PINS(55);
155DECLARE_IPQ_GPIO_PINS(56);
156DECLARE_IPQ_GPIO_PINS(57);
157DECLARE_IPQ_GPIO_PINS(58);
158DECLARE_IPQ_GPIO_PINS(59);
159DECLARE_IPQ_GPIO_PINS(60);
160DECLARE_IPQ_GPIO_PINS(61);
161DECLARE_IPQ_GPIO_PINS(62);
162DECLARE_IPQ_GPIO_PINS(63);
163DECLARE_IPQ_GPIO_PINS(64);
164DECLARE_IPQ_GPIO_PINS(65);
165DECLARE_IPQ_GPIO_PINS(66);
166DECLARE_IPQ_GPIO_PINS(67);
167DECLARE_IPQ_GPIO_PINS(68);
168
169static const unsigned int sdc3_clk_pins[] = { 69 };
170static const unsigned int sdc3_cmd_pins[] = { 70 };
171static const unsigned int sdc3_data_pins[] = { 71 };
172
173#define FUNCTION(fname) \
174 [IPQ_MUX_##fname] = { \
175 .name = #fname, \
176 .groups = fname##_groups, \
177 .ngroups = ARRAY_SIZE(fname##_groups), \
178 }
179
180#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
181 { \
182 .name = "gpio" #id, \
183 .pins = gpio##id##_pins, \
184 .npins = ARRAY_SIZE(gpio##id##_pins), \
185 .funcs = (int[]){ \
186 IPQ_MUX_gpio, \
187 IPQ_MUX_##f1, \
188 IPQ_MUX_##f2, \
189 IPQ_MUX_##f3, \
190 IPQ_MUX_##f4, \
191 IPQ_MUX_##f5, \
192 IPQ_MUX_##f6, \
193 IPQ_MUX_##f7, \
194 IPQ_MUX_##f8, \
195 IPQ_MUX_##f9, \
196 IPQ_MUX_##f10, \
197 }, \
198 .nfuncs = 11, \
199 .ctl_reg = 0x1000 + 0x10 * id, \
200 .io_reg = 0x1004 + 0x10 * id, \
201 .intr_cfg_reg = 0x1008 + 0x10 * id, \
202 .intr_status_reg = 0x100c + 0x10 * id, \
203 .intr_target_reg = 0x400 + 0x4 * id, \
204 .mux_bit = 2, \
205 .pull_bit = 0, \
206 .drv_bit = 6, \
207 .oe_bit = 9, \
208 .in_bit = 0, \
209 .out_bit = 1, \
210 .intr_enable_bit = 0, \
211 .intr_status_bit = 0, \
212 .intr_ack_high = 1, \
213 .intr_target_bit = 0, \
214 .intr_raw_status_bit = 3, \
215 .intr_polarity_bit = 1, \
216 .intr_detection_bit = 2, \
217 .intr_detection_width = 1, \
218 }
219
220#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
221 { \
222 .name = #pg_name, \
223 .pins = pg_name##_pins, \
224 .npins = ARRAY_SIZE(pg_name##_pins), \
225 .ctl_reg = ctl, \
226 .io_reg = 0, \
227 .intr_cfg_reg = 0, \
228 .intr_status_reg = 0, \
229 .intr_target_reg = 0, \
230 .mux_bit = -1, \
231 .pull_bit = pull, \
232 .drv_bit = drv, \
233 .oe_bit = -1, \
234 .in_bit = -1, \
235 .out_bit = -1, \
236 .intr_enable_bit = -1, \
237 .intr_status_bit = -1, \
238 .intr_target_bit = -1, \
239 .intr_raw_status_bit = -1, \
240 .intr_polarity_bit = -1, \
241 .intr_detection_bit = -1, \
242 .intr_detection_width = -1, \
243 }
244
245enum ipq8064_functions {
246 IPQ_MUX_gpio,
247 IPQ_MUX_mdio,
248 IPQ_MUX_mi2s,
249 IPQ_MUX_pdm,
250 IPQ_MUX_ssbi,
251 IPQ_MUX_spmi,
252 IPQ_MUX_audio_pcm,
253 IPQ_MUX_gsbi1,
254 IPQ_MUX_gsbi2,
255 IPQ_MUX_gsbi4,
256 IPQ_MUX_gsbi5,
257 IPQ_MUX_gsbi5_spi_cs1,
258 IPQ_MUX_gsbi5_spi_cs2,
259 IPQ_MUX_gsbi5_spi_cs3,
260 IPQ_MUX_gsbi6,
261 IPQ_MUX_gsbi7,
262 IPQ_MUX_nss_spi,
263 IPQ_MUX_sdc1,
264 IPQ_MUX_spdif,
265 IPQ_MUX_nand,
266 IPQ_MUX_tsif1,
267 IPQ_MUX_tsif2,
268 IPQ_MUX_usb_fs_n,
269 IPQ_MUX_usb_fs,
270 IPQ_MUX_usb2_hsic,
271 IPQ_MUX_rgmii2,
272 IPQ_MUX_sata,
273 IPQ_MUX_pcie1_rst,
274 IPQ_MUX_pcie1_prsnt,
275 IPQ_MUX_pcie1_pwrflt,
276 IPQ_MUX_pcie1_pwren_n,
277 IPQ_MUX_pcie1_pwren,
278 IPQ_MUX_pcie1_clk_req,
279 IPQ_MUX_pcie2_rst,
280 IPQ_MUX_pcie2_prsnt,
281 IPQ_MUX_pcie2_pwrflt,
282 IPQ_MUX_pcie2_pwren_n,
283 IPQ_MUX_pcie2_pwren,
284 IPQ_MUX_pcie2_clk_req,
285 IPQ_MUX_pcie3_rst,
286 IPQ_MUX_pcie3_prsnt,
287 IPQ_MUX_pcie3_pwrflt,
288 IPQ_MUX_pcie3_pwren_n,
289 IPQ_MUX_pcie3_pwren,
290 IPQ_MUX_pcie3_clk_req,
291 IPQ_MUX_ps_hold,
292 IPQ_MUX_NA,
293};
294
295static const char * const gpio_groups[] = {
296 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
297 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
298 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
299 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
300 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
301 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
302 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
303 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
304 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
305 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
306};
307
308static const char * const mdio_groups[] = {
309 "gpio0", "gpio1", "gpio10", "gpio11",
310};
311
312static const char * const mi2s_groups[] = {
313 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
314 "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
315};
316
317static const char * const pdm_groups[] = {
318 "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
319 "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
320 "gpio59",
321};
322
323static const char * const ssbi_groups[] = {
324 "gpio10", "gpio11",
325};
326
327static const char * const spmi_groups[] = {
328 "gpio10", "gpio11",
329};
330
331static const char * const audio_pcm_groups[] = {
332 "gpio14", "gpio15", "gpio16", "gpio17",
333};
334
335static const char * const gsbi1_groups[] = {
336 "gpio51", "gpio52", "gpio53", "gpio54",
337};
338
339static const char * const gsbi2_groups[] = {
340 "gpio22", "gpio23", "gpio24", "gpio25",
341};
342
343static const char * const gsbi4_groups[] = {
344 "gpio10", "gpio11", "gpio12", "gpio13",
345};
346
347static const char * const gsbi5_groups[] = {
348 "gpio18", "gpio19", "gpio20", "gpio21",
349};
350
351static const char * const gsbi5_spi_cs1_groups[] = {
352 "gpio6", "gpio61",
353};
354
355static const char * const gsbi5_spi_cs2_groups[] = {
356 "gpio7", "gpio62",
357};
358
359static const char * const gsbi5_spi_cs3_groups[] = {
360 "gpio2",
361};
362
363static const char * const gsbi6_groups[] = {
364 "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
365 "gpio57", "gpio58",
366};
367
368static const char * const gsbi7_groups[] = {
369 "gpio6", "gpio7", "gpio8", "gpio9",
370};
371
372static const char * const nss_spi_groups[] = {
373 "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
374 "gpio57", "gpio58",
375};
376
377static const char * const sdc1_groups[] = {
378 "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
379 "gpio44", "gpio45", "gpio46", "gpio47",
380};
381
382static const char * const spdif_groups[] = {
383 "gpio10", "gpio48",
384};
385
386static const char * const nand_groups[] = {
387 "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
388 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
389 "gpio46", "gpio47",
390};
391
392static const char * const tsif1_groups[] = {
393 "gpio55", "gpio56", "gpio57", "gpio58",
394};
395
396static const char * const tsif2_groups[] = {
397 "gpio59", "gpio60", "gpio61", "gpio62",
398};
399
400static const char * const usb_fs_n_groups[] = {
401 "gpio6",
402};
403
404static const char * const usb_fs_groups[] = {
405 "gpio6", "gpio7", "gpio8",
406};
407
408static const char * const usb2_hsic_groups[] = {
409 "gpio67", "gpio68",
410};
411
412static const char * const rgmii2_groups[] = {
413 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
414 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
415};
416
417static const char * const sata_groups[] = {
418 "gpio10",
419};
420
421static const char * const pcie1_rst_groups[] = {
422 "gpio3",
423};
424
425static const char * const pcie1_prsnt_groups[] = {
426 "gpio3", "gpio11",
427};
428
429static const char * const pcie1_pwren_n_groups[] = {
430 "gpio4", "gpio12",
431};
432
433static const char * const pcie1_pwren_groups[] = {
434 "gpio4", "gpio12",
435};
436
437static const char * const pcie1_pwrflt_groups[] = {
438 "gpio5", "gpio13",
439};
440
441static const char * const pcie1_clk_req_groups[] = {
442 "gpio5",
443};
444
445static const char * const pcie2_rst_groups[] = {
446 "gpio48",
447};
448
449static const char * const pcie2_prsnt_groups[] = {
450 "gpio11", "gpio48",
451};
452
453static const char * const pcie2_pwren_n_groups[] = {
454 "gpio12", "gpio49",
455};
456
457static const char * const pcie2_pwren_groups[] = {
458 "gpio12", "gpio49",
459};
460
461static const char * const pcie2_pwrflt_groups[] = {
462 "gpio13", "gpio50",
463};
464
465static const char * const pcie2_clk_req_groups[] = {
466 "gpio50",
467};
468
469static const char * const pcie3_rst_groups[] = {
470 "gpio63",
471};
472
473static const char * const pcie3_prsnt_groups[] = {
474 "gpio11",
475};
476
477static const char * const pcie3_pwren_n_groups[] = {
478 "gpio12",
479};
480
481static const char * const pcie3_pwren_groups[] = {
482 "gpio12",
483};
484
485static const char * const pcie3_pwrflt_groups[] = {
486 "gpio13",
487};
488
489static const char * const pcie3_clk_req_groups[] = {
490 "gpio65",
491};
492
493static const char * const ps_hold_groups[] = {
494 "gpio26",
495};
496
497static const struct msm_function ipq8064_functions[] = {
498 FUNCTION(gpio),
499 FUNCTION(mdio),
500 FUNCTION(ssbi),
501 FUNCTION(spmi),
502 FUNCTION(mi2s),
503 FUNCTION(pdm),
504 FUNCTION(audio_pcm),
505 FUNCTION(gsbi1),
506 FUNCTION(gsbi2),
507 FUNCTION(gsbi4),
508 FUNCTION(gsbi5),
509 FUNCTION(gsbi5_spi_cs1),
510 FUNCTION(gsbi5_spi_cs2),
511 FUNCTION(gsbi5_spi_cs3),
512 FUNCTION(gsbi6),
513 FUNCTION(gsbi7),
514 FUNCTION(nss_spi),
515 FUNCTION(sdc1),
516 FUNCTION(spdif),
517 FUNCTION(nand),
518 FUNCTION(tsif1),
519 FUNCTION(tsif2),
520 FUNCTION(usb_fs_n),
521 FUNCTION(usb_fs),
522 FUNCTION(usb2_hsic),
523 FUNCTION(rgmii2),
524 FUNCTION(sata),
525 FUNCTION(pcie1_rst),
526 FUNCTION(pcie1_prsnt),
527 FUNCTION(pcie1_pwren_n),
528 FUNCTION(pcie1_pwren),
529 FUNCTION(pcie1_pwrflt),
530 FUNCTION(pcie1_clk_req),
531 FUNCTION(pcie2_rst),
532 FUNCTION(pcie2_prsnt),
533 FUNCTION(pcie2_pwren_n),
534 FUNCTION(pcie2_pwren),
535 FUNCTION(pcie2_pwrflt),
536 FUNCTION(pcie2_clk_req),
537 FUNCTION(pcie3_rst),
538 FUNCTION(pcie3_prsnt),
539 FUNCTION(pcie3_pwren_n),
540 FUNCTION(pcie3_pwren),
541 FUNCTION(pcie3_pwrflt),
542 FUNCTION(pcie3_clk_req),
543 FUNCTION(ps_hold),
544};
545
546static const struct msm_pingroup ipq8064_groups[] = {
547 PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
548 PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
549 PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
550 PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
551 PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
552 PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
553 PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
554 PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
555 PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
556 PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
557 PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
558 PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
559 PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
560 PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
561 PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
562 PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
563 PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
564 PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
565 PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
566 PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
567 PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
568 PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
569 PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
570 PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
571 PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
572 PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
573 PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
574 PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
575 PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
576 PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
577 PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
578 PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
579 PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
580 PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
581 PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
582 PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
583 PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
584 PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
585 PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
586 PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
587 PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
588 PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
589 PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
590 PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
591 PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
592 PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
593 PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
594 PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
595 PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
596 PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
597 PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
598 PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
599 PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
600 PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
601 PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
602 PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
603 PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
604 PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
605 PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
606 PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
607 PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
608 PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
609 PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
610 PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
611 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
612 PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
613 PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
614 PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
615 PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
616 SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
617 SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
618 SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
619};
620
621#define NUM_GPIO_PINGROUPS 69
622
623static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
624 .pins = ipq8064_pins,
625 .npins = ARRAY_SIZE(ipq8064_pins),
626 .functions = ipq8064_functions,
627 .nfunctions = ARRAY_SIZE(ipq8064_functions),
628 .groups = ipq8064_groups,
629 .ngroups = ARRAY_SIZE(ipq8064_groups),
630 .ngpios = NUM_GPIO_PINGROUPS,
631};
632
633static int ipq8064_pinctrl_probe(struct platform_device *pdev)
634{
635 return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
636}
637
638static const struct of_device_id ipq8064_pinctrl_of_match[] = {
639 { .compatible = "qcom,ipq8064-pinctrl", },
640 { },
641};
642
643static struct platform_driver ipq8064_pinctrl_driver = {
644 .driver = {
645 .name = "ipq8064-pinctrl",
646 .owner = THIS_MODULE,
647 .of_match_table = ipq8064_pinctrl_of_match,
648 },
649 .probe = ipq8064_pinctrl_probe,
650 .remove = msm_pinctrl_remove,
651};
652
653static int __init ipq8064_pinctrl_init(void)
654{
655 return platform_driver_register(&ipq8064_pinctrl_driver);
656}
657arch_initcall(ipq8064_pinctrl_init);
658
659static void __exit ipq8064_pinctrl_exit(void)
660{
661 platform_driver_unregister(&ipq8064_pinctrl_driver);
662}
663module_exit(ipq8064_pinctrl_exit);
664
665MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
666MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
667MODULE_LICENSE("GPL v2");
668MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
new file mode 100644
index 000000000000..2738108caff2
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -0,0 +1,919 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/slab.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/spinlock.h>
29
30#include "../core.h"
31#include "../pinconf.h"
32#include "pinctrl-msm.h"
33#include "../pinctrl-utils.h"
34
35#define MAX_NR_GPIO 300
36
37/**
38 * struct msm_pinctrl - state for a pinctrl-msm device
39 * @dev: device handle.
40 * @pctrl: pinctrl handle.
41 * @chip: gpiochip handle.
42 * @irq: parent irq for the TLMM irq_chip.
43 * @lock: Spinlock to protect register resources as well
44 * as msm_pinctrl data structures.
45 * @enabled_irqs: Bitmap of currently enabled irqs.
46 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
47 * detection.
48 * @soc; Reference to soc_data of platform specific data.
49 * @regs: Base address for the TLMM register map.
50 */
51struct msm_pinctrl {
52 struct device *dev;
53 struct pinctrl_dev *pctrl;
54 struct gpio_chip chip;
55 int irq;
56
57 spinlock_t lock;
58
59 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
60 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
61
62 const struct msm_pinctrl_soc_data *soc;
63 void __iomem *regs;
64};
65
66static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
67{
68 return container_of(gc, struct msm_pinctrl, chip);
69}
70
71static int msm_get_groups_count(struct pinctrl_dev *pctldev)
72{
73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
74
75 return pctrl->soc->ngroups;
76}
77
78static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
79 unsigned group)
80{
81 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
82
83 return pctrl->soc->groups[group].name;
84}
85
86static int msm_get_group_pins(struct pinctrl_dev *pctldev,
87 unsigned group,
88 const unsigned **pins,
89 unsigned *num_pins)
90{
91 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
92
93 *pins = pctrl->soc->groups[group].pins;
94 *num_pins = pctrl->soc->groups[group].npins;
95 return 0;
96}
97
98static const struct pinctrl_ops msm_pinctrl_ops = {
99 .get_groups_count = msm_get_groups_count,
100 .get_group_name = msm_get_group_name,
101 .get_group_pins = msm_get_group_pins,
102 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
103 .dt_free_map = pinctrl_utils_dt_free_map,
104};
105
106static int msm_get_functions_count(struct pinctrl_dev *pctldev)
107{
108 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
109
110 return pctrl->soc->nfunctions;
111}
112
113static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
114 unsigned function)
115{
116 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
117
118 return pctrl->soc->functions[function].name;
119}
120
121static int msm_get_function_groups(struct pinctrl_dev *pctldev,
122 unsigned function,
123 const char * const **groups,
124 unsigned * const num_groups)
125{
126 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
127
128 *groups = pctrl->soc->functions[function].groups;
129 *num_groups = pctrl->soc->functions[function].ngroups;
130 return 0;
131}
132
133static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
134 unsigned function,
135 unsigned group)
136{
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g;
139 unsigned long flags;
140 u32 val;
141 int i;
142
143 g = &pctrl->soc->groups[group];
144
145 for (i = 0; i < g->nfuncs; i++) {
146 if (g->funcs[i] == function)
147 break;
148 }
149
150 if (WARN_ON(i == g->nfuncs))
151 return -EINVAL;
152
153 spin_lock_irqsave(&pctrl->lock, flags);
154
155 val = readl(pctrl->regs + g->ctl_reg);
156 val &= ~(0x7 << g->mux_bit);
157 val |= i << g->mux_bit;
158 writel(val, pctrl->regs + g->ctl_reg);
159
160 spin_unlock_irqrestore(&pctrl->lock, flags);
161
162 return 0;
163}
164
165static const struct pinmux_ops msm_pinmux_ops = {
166 .get_functions_count = msm_get_functions_count,
167 .get_function_name = msm_get_function_name,
168 .get_function_groups = msm_get_function_groups,
169 .enable = msm_pinmux_enable,
170};
171
172static int msm_config_reg(struct msm_pinctrl *pctrl,
173 const struct msm_pingroup *g,
174 unsigned param,
175 unsigned *mask,
176 unsigned *bit)
177{
178 switch (param) {
179 case PIN_CONFIG_BIAS_DISABLE:
180 case PIN_CONFIG_BIAS_PULL_DOWN:
181 case PIN_CONFIG_BIAS_BUS_HOLD:
182 case PIN_CONFIG_BIAS_PULL_UP:
183 *bit = g->pull_bit;
184 *mask = 3;
185 break;
186 case PIN_CONFIG_DRIVE_STRENGTH:
187 *bit = g->drv_bit;
188 *mask = 7;
189 break;
190 case PIN_CONFIG_OUTPUT:
191 *bit = g->oe_bit;
192 *mask = 1;
193 break;
194 default:
195 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
196 return -ENOTSUPP;
197 }
198
199 return 0;
200}
201
202static int msm_config_get(struct pinctrl_dev *pctldev,
203 unsigned int pin,
204 unsigned long *config)
205{
206 dev_err(pctldev->dev, "pin_config_set op not supported\n");
207 return -ENOTSUPP;
208}
209
210static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
211 unsigned long *configs, unsigned num_configs)
212{
213 dev_err(pctldev->dev, "pin_config_set op not supported\n");
214 return -ENOTSUPP;
215}
216
217#define MSM_NO_PULL 0
218#define MSM_PULL_DOWN 1
219#define MSM_KEEPER 2
220#define MSM_PULL_UP 3
221
222static unsigned msm_regval_to_drive(u32 val)
223{
224 return (val + 1) * 2;
225}
226
227static int msm_config_group_get(struct pinctrl_dev *pctldev,
228 unsigned int group,
229 unsigned long *config)
230{
231 const struct msm_pingroup *g;
232 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
233 unsigned param = pinconf_to_config_param(*config);
234 unsigned mask;
235 unsigned arg;
236 unsigned bit;
237 int ret;
238 u32 val;
239
240 g = &pctrl->soc->groups[group];
241
242 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
243 if (ret < 0)
244 return ret;
245
246 val = readl(pctrl->regs + g->ctl_reg);
247 arg = (val >> bit) & mask;
248
249 /* Convert register value to pinconf value */
250 switch (param) {
251 case PIN_CONFIG_BIAS_DISABLE:
252 arg = arg == MSM_NO_PULL;
253 break;
254 case PIN_CONFIG_BIAS_PULL_DOWN:
255 arg = arg == MSM_PULL_DOWN;
256 break;
257 case PIN_CONFIG_BIAS_BUS_HOLD:
258 arg = arg == MSM_KEEPER;
259 break;
260 case PIN_CONFIG_BIAS_PULL_UP:
261 arg = arg == MSM_PULL_UP;
262 break;
263 case PIN_CONFIG_DRIVE_STRENGTH:
264 arg = msm_regval_to_drive(arg);
265 break;
266 case PIN_CONFIG_OUTPUT:
267 /* Pin is not output */
268 if (!arg)
269 return -EINVAL;
270
271 val = readl(pctrl->regs + g->io_reg);
272 arg = !!(val & BIT(g->in_bit));
273 break;
274 default:
275 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
276 param);
277 return -EINVAL;
278 }
279
280 *config = pinconf_to_config_packed(param, arg);
281
282 return 0;
283}
284
285static int msm_config_group_set(struct pinctrl_dev *pctldev,
286 unsigned group,
287 unsigned long *configs,
288 unsigned num_configs)
289{
290 const struct msm_pingroup *g;
291 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292 unsigned long flags;
293 unsigned param;
294 unsigned mask;
295 unsigned arg;
296 unsigned bit;
297 int ret;
298 u32 val;
299 int i;
300
301 g = &pctrl->soc->groups[group];
302
303 for (i = 0; i < num_configs; i++) {
304 param = pinconf_to_config_param(configs[i]);
305 arg = pinconf_to_config_argument(configs[i]);
306
307 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
308 if (ret < 0)
309 return ret;
310
311 /* Convert pinconf values to register values */
312 switch (param) {
313 case PIN_CONFIG_BIAS_DISABLE:
314 arg = MSM_NO_PULL;
315 break;
316 case PIN_CONFIG_BIAS_PULL_DOWN:
317 arg = MSM_PULL_DOWN;
318 break;
319 case PIN_CONFIG_BIAS_BUS_HOLD:
320 arg = MSM_KEEPER;
321 break;
322 case PIN_CONFIG_BIAS_PULL_UP:
323 arg = MSM_PULL_UP;
324 break;
325 case PIN_CONFIG_DRIVE_STRENGTH:
326 /* Check for invalid values */
327 if (arg > 16 || arg < 2 || (arg % 2) != 0)
328 arg = -1;
329 else
330 arg = (arg / 2) - 1;
331 break;
332 case PIN_CONFIG_OUTPUT:
333 /* set output value */
334 spin_lock_irqsave(&pctrl->lock, flags);
335 val = readl(pctrl->regs + g->io_reg);
336 if (arg)
337 val |= BIT(g->out_bit);
338 else
339 val &= ~BIT(g->out_bit);
340 writel(val, pctrl->regs + g->io_reg);
341 spin_unlock_irqrestore(&pctrl->lock, flags);
342
343 /* enable output */
344 arg = 1;
345 break;
346 default:
347 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
348 param);
349 return -EINVAL;
350 }
351
352 /* Range-check user-supplied value */
353 if (arg & ~mask) {
354 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
355 return -EINVAL;
356 }
357
358 spin_lock_irqsave(&pctrl->lock, flags);
359 val = readl(pctrl->regs + g->ctl_reg);
360 val &= ~(mask << bit);
361 val |= arg << bit;
362 writel(val, pctrl->regs + g->ctl_reg);
363 spin_unlock_irqrestore(&pctrl->lock, flags);
364 }
365
366 return 0;
367}
368
369static const struct pinconf_ops msm_pinconf_ops = {
370 .pin_config_get = msm_config_get,
371 .pin_config_set = msm_config_set,
372 .pin_config_group_get = msm_config_group_get,
373 .pin_config_group_set = msm_config_group_set,
374};
375
376static struct pinctrl_desc msm_pinctrl_desc = {
377 .pctlops = &msm_pinctrl_ops,
378 .pmxops = &msm_pinmux_ops,
379 .confops = &msm_pinconf_ops,
380 .owner = THIS_MODULE,
381};
382
383static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
384{
385 const struct msm_pingroup *g;
386 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
387 unsigned long flags;
388 u32 val;
389
390 g = &pctrl->soc->groups[offset];
391
392 spin_lock_irqsave(&pctrl->lock, flags);
393
394 val = readl(pctrl->regs + g->ctl_reg);
395 val &= ~BIT(g->oe_bit);
396 writel(val, pctrl->regs + g->ctl_reg);
397
398 spin_unlock_irqrestore(&pctrl->lock, flags);
399
400 return 0;
401}
402
403static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
404{
405 const struct msm_pingroup *g;
406 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
407 unsigned long flags;
408 u32 val;
409
410 g = &pctrl->soc->groups[offset];
411
412 spin_lock_irqsave(&pctrl->lock, flags);
413
414 val = readl(pctrl->regs + g->io_reg);
415 if (value)
416 val |= BIT(g->out_bit);
417 else
418 val &= ~BIT(g->out_bit);
419 writel(val, pctrl->regs + g->io_reg);
420
421 val = readl(pctrl->regs + g->ctl_reg);
422 val |= BIT(g->oe_bit);
423 writel(val, pctrl->regs + g->ctl_reg);
424
425 spin_unlock_irqrestore(&pctrl->lock, flags);
426
427 return 0;
428}
429
430static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
431{
432 const struct msm_pingroup *g;
433 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
434 u32 val;
435
436 g = &pctrl->soc->groups[offset];
437
438 val = readl(pctrl->regs + g->io_reg);
439 return !!(val & BIT(g->in_bit));
440}
441
442static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
443{
444 const struct msm_pingroup *g;
445 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
446 unsigned long flags;
447 u32 val;
448
449 g = &pctrl->soc->groups[offset];
450
451 spin_lock_irqsave(&pctrl->lock, flags);
452
453 val = readl(pctrl->regs + g->io_reg);
454 if (value)
455 val |= BIT(g->out_bit);
456 else
457 val &= ~BIT(g->out_bit);
458 writel(val, pctrl->regs + g->io_reg);
459
460 spin_unlock_irqrestore(&pctrl->lock, flags);
461}
462
463static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
464{
465 int gpio = chip->base + offset;
466 return pinctrl_request_gpio(gpio);
467}
468
469static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
470{
471 int gpio = chip->base + offset;
472 return pinctrl_free_gpio(gpio);
473}
474
475#ifdef CONFIG_DEBUG_FS
476#include <linux/seq_file.h>
477
478static void msm_gpio_dbg_show_one(struct seq_file *s,
479 struct pinctrl_dev *pctldev,
480 struct gpio_chip *chip,
481 unsigned offset,
482 unsigned gpio)
483{
484 const struct msm_pingroup *g;
485 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
486 unsigned func;
487 int is_out;
488 int drive;
489 int pull;
490 u32 ctl_reg;
491
492 static const char * const pulls[] = {
493 "no pull",
494 "pull down",
495 "keeper",
496 "pull up"
497 };
498
499 g = &pctrl->soc->groups[offset];
500 ctl_reg = readl(pctrl->regs + g->ctl_reg);
501
502 is_out = !!(ctl_reg & BIT(g->oe_bit));
503 func = (ctl_reg >> g->mux_bit) & 7;
504 drive = (ctl_reg >> g->drv_bit) & 7;
505 pull = (ctl_reg >> g->pull_bit) & 3;
506
507 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
508 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
509 seq_printf(s, " %s", pulls[pull]);
510}
511
512static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
513{
514 unsigned gpio = chip->base;
515 unsigned i;
516
517 for (i = 0; i < chip->ngpio; i++, gpio++) {
518 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
519 seq_puts(s, "\n");
520 }
521}
522
523#else
524#define msm_gpio_dbg_show NULL
525#endif
526
527static struct gpio_chip msm_gpio_template = {
528 .direction_input = msm_gpio_direction_input,
529 .direction_output = msm_gpio_direction_output,
530 .get = msm_gpio_get,
531 .set = msm_gpio_set,
532 .request = msm_gpio_request,
533 .free = msm_gpio_free,
534 .dbg_show = msm_gpio_dbg_show,
535};
536
537/* For dual-edge interrupts in software, since some hardware has no
538 * such support:
539 *
540 * At appropriate moments, this function may be called to flip the polarity
541 * settings of both-edge irq lines to try and catch the next edge.
542 *
543 * The attempt is considered successful if:
544 * - the status bit goes high, indicating that an edge was caught, or
545 * - the input value of the gpio doesn't change during the attempt.
546 * If the value changes twice during the process, that would cause the first
547 * test to fail but would force the second, as two opposite
548 * transitions would cause a detection no matter the polarity setting.
549 *
550 * The do-loop tries to sledge-hammer closed the timing hole between
551 * the initial value-read and the polarity-write - if the line value changes
552 * during that window, an interrupt is lost, the new polarity setting is
553 * incorrect, and the first success test will fail, causing a retry.
554 *
555 * Algorithm comes from Google's msmgpio driver.
556 */
557static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
558 const struct msm_pingroup *g,
559 struct irq_data *d)
560{
561 int loop_limit = 100;
562 unsigned val, val2, intstat;
563 unsigned pol;
564
565 do {
566 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
567
568 pol = readl(pctrl->regs + g->intr_cfg_reg);
569 pol ^= BIT(g->intr_polarity_bit);
570 writel(pol, pctrl->regs + g->intr_cfg_reg);
571
572 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
573 intstat = readl(pctrl->regs + g->intr_status_reg);
574 if (intstat || (val == val2))
575 return;
576 } while (loop_limit-- > 0);
577 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
578 val, val2);
579}
580
581static void msm_gpio_irq_mask(struct irq_data *d)
582{
583 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
584 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
585 const struct msm_pingroup *g;
586 unsigned long flags;
587 u32 val;
588
589 g = &pctrl->soc->groups[d->hwirq];
590
591 spin_lock_irqsave(&pctrl->lock, flags);
592
593 val = readl(pctrl->regs + g->intr_cfg_reg);
594 val &= ~BIT(g->intr_enable_bit);
595 writel(val, pctrl->regs + g->intr_cfg_reg);
596
597 clear_bit(d->hwirq, pctrl->enabled_irqs);
598
599 spin_unlock_irqrestore(&pctrl->lock, flags);
600}
601
602static void msm_gpio_irq_unmask(struct irq_data *d)
603{
604 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
605 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
606 const struct msm_pingroup *g;
607 unsigned long flags;
608 u32 val;
609
610 g = &pctrl->soc->groups[d->hwirq];
611
612 spin_lock_irqsave(&pctrl->lock, flags);
613
614 val = readl(pctrl->regs + g->intr_status_reg);
615 val &= ~BIT(g->intr_status_bit);
616 writel(val, pctrl->regs + g->intr_status_reg);
617
618 val = readl(pctrl->regs + g->intr_cfg_reg);
619 val |= BIT(g->intr_enable_bit);
620 writel(val, pctrl->regs + g->intr_cfg_reg);
621
622 set_bit(d->hwirq, pctrl->enabled_irqs);
623
624 spin_unlock_irqrestore(&pctrl->lock, flags);
625}
626
627static void msm_gpio_irq_ack(struct irq_data *d)
628{
629 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
630 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
631 const struct msm_pingroup *g;
632 unsigned long flags;
633 u32 val;
634
635 g = &pctrl->soc->groups[d->hwirq];
636
637 spin_lock_irqsave(&pctrl->lock, flags);
638
639 val = readl(pctrl->regs + g->intr_status_reg);
640 if (g->intr_ack_high)
641 val |= BIT(g->intr_status_bit);
642 else
643 val &= ~BIT(g->intr_status_bit);
644 writel(val, pctrl->regs + g->intr_status_reg);
645
646 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
647 msm_gpio_update_dual_edge_pos(pctrl, g, d);
648
649 spin_unlock_irqrestore(&pctrl->lock, flags);
650}
651
652#define INTR_TARGET_PROC_APPS 4
653
654static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
655{
656 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
657 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
658 const struct msm_pingroup *g;
659 unsigned long flags;
660 u32 val;
661
662 g = &pctrl->soc->groups[d->hwirq];
663
664 spin_lock_irqsave(&pctrl->lock, flags);
665
666 /*
667 * For hw without possibility of detecting both edges
668 */
669 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
670 set_bit(d->hwirq, pctrl->dual_edge_irqs);
671 else
672 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
673
674 /* Route interrupts to application cpu */
675 val = readl(pctrl->regs + g->intr_target_reg);
676 val &= ~(7 << g->intr_target_bit);
677 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
678 writel(val, pctrl->regs + g->intr_target_reg);
679
680 /* Update configuration for gpio.
681 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
682 * internal circuitry of TLMM, toggling the RAW_STATUS
683 * could cause the INTR_STATUS to be set for EDGE interrupts.
684 */
685 val = readl(pctrl->regs + g->intr_cfg_reg);
686 val |= BIT(g->intr_raw_status_bit);
687 if (g->intr_detection_width == 2) {
688 val &= ~(3 << g->intr_detection_bit);
689 val &= ~(1 << g->intr_polarity_bit);
690 switch (type) {
691 case IRQ_TYPE_EDGE_RISING:
692 val |= 1 << g->intr_detection_bit;
693 val |= BIT(g->intr_polarity_bit);
694 break;
695 case IRQ_TYPE_EDGE_FALLING:
696 val |= 2 << g->intr_detection_bit;
697 val |= BIT(g->intr_polarity_bit);
698 break;
699 case IRQ_TYPE_EDGE_BOTH:
700 val |= 3 << g->intr_detection_bit;
701 val |= BIT(g->intr_polarity_bit);
702 break;
703 case IRQ_TYPE_LEVEL_LOW:
704 break;
705 case IRQ_TYPE_LEVEL_HIGH:
706 val |= BIT(g->intr_polarity_bit);
707 break;
708 }
709 } else if (g->intr_detection_width == 1) {
710 val &= ~(1 << g->intr_detection_bit);
711 val &= ~(1 << g->intr_polarity_bit);
712 switch (type) {
713 case IRQ_TYPE_EDGE_RISING:
714 val |= BIT(g->intr_detection_bit);
715 val |= BIT(g->intr_polarity_bit);
716 break;
717 case IRQ_TYPE_EDGE_FALLING:
718 val |= BIT(g->intr_detection_bit);
719 break;
720 case IRQ_TYPE_EDGE_BOTH:
721 val |= BIT(g->intr_detection_bit);
722 val |= BIT(g->intr_polarity_bit);
723 break;
724 case IRQ_TYPE_LEVEL_LOW:
725 break;
726 case IRQ_TYPE_LEVEL_HIGH:
727 val |= BIT(g->intr_polarity_bit);
728 break;
729 }
730 } else {
731 BUG();
732 }
733 writel(val, pctrl->regs + g->intr_cfg_reg);
734
735 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
736 msm_gpio_update_dual_edge_pos(pctrl, g, d);
737
738 spin_unlock_irqrestore(&pctrl->lock, flags);
739
740 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
741 __irq_set_handler_locked(d->irq, handle_level_irq);
742 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
743 __irq_set_handler_locked(d->irq, handle_edge_irq);
744
745 return 0;
746}
747
748static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
749{
750 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
751 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
752 unsigned long flags;
753
754 spin_lock_irqsave(&pctrl->lock, flags);
755
756 irq_set_irq_wake(pctrl->irq, on);
757
758 spin_unlock_irqrestore(&pctrl->lock, flags);
759
760 return 0;
761}
762
763static struct irq_chip msm_gpio_irq_chip = {
764 .name = "msmgpio",
765 .irq_mask = msm_gpio_irq_mask,
766 .irq_unmask = msm_gpio_irq_unmask,
767 .irq_ack = msm_gpio_irq_ack,
768 .irq_set_type = msm_gpio_irq_set_type,
769 .irq_set_wake = msm_gpio_irq_set_wake,
770};
771
772static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
773{
774 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
775 const struct msm_pingroup *g;
776 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
777 struct irq_chip *chip = irq_get_chip(irq);
778 int irq_pin;
779 int handled = 0;
780 u32 val;
781 int i;
782
783 chained_irq_enter(chip, desc);
784
785 /*
786 * Each pin has it's own IRQ status register, so use
787 * enabled_irq bitmap to limit the number of reads.
788 */
789 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
790 g = &pctrl->soc->groups[i];
791 val = readl(pctrl->regs + g->intr_status_reg);
792 if (val & BIT(g->intr_status_bit)) {
793 irq_pin = irq_find_mapping(gc->irqdomain, i);
794 generic_handle_irq(irq_pin);
795 handled++;
796 }
797 }
798
799 /* No interrupts were flagged */
800 if (handled == 0)
801 handle_bad_irq(irq, desc);
802
803 chained_irq_exit(chip, desc);
804}
805
806static int msm_gpio_init(struct msm_pinctrl *pctrl)
807{
808 struct gpio_chip *chip;
809 int ret;
810 unsigned ngpio = pctrl->soc->ngpios;
811
812 if (WARN_ON(ngpio > MAX_NR_GPIO))
813 return -EINVAL;
814
815 chip = &pctrl->chip;
816 chip->base = 0;
817 chip->ngpio = ngpio;
818 chip->label = dev_name(pctrl->dev);
819 chip->dev = pctrl->dev;
820 chip->owner = THIS_MODULE;
821 chip->of_node = pctrl->dev->of_node;
822
823 ret = gpiochip_add(&pctrl->chip);
824 if (ret) {
825 dev_err(pctrl->dev, "Failed register gpiochip\n");
826 return ret;
827 }
828
829 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
830 if (ret) {
831 dev_err(pctrl->dev, "Failed to add pin range\n");
832 return ret;
833 }
834
835 ret = gpiochip_irqchip_add(chip,
836 &msm_gpio_irq_chip,
837 0,
838 handle_edge_irq,
839 IRQ_TYPE_NONE);
840 if (ret) {
841 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
842 return -ENOSYS;
843 }
844
845 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
846 msm_gpio_irq_handler);
847
848 return 0;
849}
850
851int msm_pinctrl_probe(struct platform_device *pdev,
852 const struct msm_pinctrl_soc_data *soc_data)
853{
854 struct msm_pinctrl *pctrl;
855 struct resource *res;
856 int ret;
857
858 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
859 if (!pctrl) {
860 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
861 return -ENOMEM;
862 }
863 pctrl->dev = &pdev->dev;
864 pctrl->soc = soc_data;
865 pctrl->chip = msm_gpio_template;
866
867 spin_lock_init(&pctrl->lock);
868
869 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
870 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
871 if (IS_ERR(pctrl->regs))
872 return PTR_ERR(pctrl->regs);
873
874 pctrl->irq = platform_get_irq(pdev, 0);
875 if (pctrl->irq < 0) {
876 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
877 return pctrl->irq;
878 }
879
880 msm_pinctrl_desc.name = dev_name(&pdev->dev);
881 msm_pinctrl_desc.pins = pctrl->soc->pins;
882 msm_pinctrl_desc.npins = pctrl->soc->npins;
883 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
884 if (!pctrl->pctrl) {
885 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
886 return -ENODEV;
887 }
888
889 ret = msm_gpio_init(pctrl);
890 if (ret) {
891 pinctrl_unregister(pctrl->pctrl);
892 return ret;
893 }
894
895 platform_set_drvdata(pdev, pctrl);
896
897 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
898
899 return 0;
900}
901EXPORT_SYMBOL(msm_pinctrl_probe);
902
903int msm_pinctrl_remove(struct platform_device *pdev)
904{
905 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
906 int ret;
907
908 ret = gpiochip_remove(&pctrl->chip);
909 if (ret) {
910 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
911 return ret;
912 }
913
914 pinctrl_unregister(pctrl->pctrl);
915
916 return 0;
917}
918EXPORT_SYMBOL(msm_pinctrl_remove);
919
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
new file mode 100644
index 000000000000..7b2a227a590a
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -0,0 +1,121 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __PINCTRL_MSM_H__
14#define __PINCTRL_MSM_H__
15
16struct pinctrl_pin_desc;
17
18/**
19 * struct msm_function - a pinmux function
20 * @name: Name of the pinmux function.
21 * @groups: List of pingroups for this function.
22 * @ngroups: Number of entries in @groups.
23 */
24struct msm_function {
25 const char *name;
26 const char * const *groups;
27 unsigned ngroups;
28};
29
30/**
31 * struct msm_pingroup - Qualcomm pingroup definition
32 * @name: Name of the pingroup.
33 * @pins: A list of pins assigned to this pingroup.
34 * @npins: Number of entries in @pins.
35 * @funcs: A list of pinmux functions that can be selected for
36 * this group. The index of the selected function is used
37 * for programming the function selector.
38 * Entries should be indices into the groups list of the
39 * struct msm_pinctrl_soc_data.
40 * @ctl_reg: Offset of the register holding control bits for this group.
41 * @io_reg: Offset of the register holding input/output bits for this group.
42 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
43 * @intr_status_reg: Offset of the register holding the status bits for this group.
44 * @intr_target_reg: Offset of the register specifying routing of the interrupts
45 * from this group.
46 * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
47 * @pull_bit: Offset in @ctl_reg for the bias configuration.
48 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
49 * @oe_bit: Offset in @ctl_reg for controlling output enable.
50 * @in_bit: Offset in @io_reg for the input bit value.
51 * @out_bit: Offset in @io_reg for the output bit value.
52 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
54 * status.
55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
56 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
57 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
58 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
59 * @intr_detection_width: Number of bits used for specifying interrupt type,
60 * Should be 2 for SoCs that can detect both edges in hardware,
61 * otherwise 1.
62 */
63struct msm_pingroup {
64 const char *name;
65 const unsigned *pins;
66 unsigned npins;
67
68 unsigned *funcs;
69 unsigned nfuncs;
70
71 s16 ctl_reg;
72 s16 io_reg;
73 s16 intr_cfg_reg;
74 s16 intr_status_reg;
75 s16 intr_target_reg;
76
77 unsigned mux_bit:5;
78
79 unsigned pull_bit:5;
80 unsigned drv_bit:5;
81
82 unsigned oe_bit:5;
83 unsigned in_bit:5;
84 unsigned out_bit:5;
85
86 unsigned intr_enable_bit:5;
87 unsigned intr_status_bit:5;
88 unsigned intr_ack_high:1;
89
90 unsigned intr_target_bit:5;
91 unsigned intr_raw_status_bit:5;
92 unsigned intr_polarity_bit:5;
93 unsigned intr_detection_bit:5;
94 unsigned intr_detection_width:5;
95};
96
97/**
98 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
99 * @pins: An array describing all pins the pin controller affects.
100 * @npins: The number of entries in @pins.
101 * @functions: An array describing all mux functions the SoC supports.
102 * @nfunctions: The number of entries in @functions.
103 * @groups: An array describing all pin groups the pin SoC supports.
104 * @ngroups: The numbmer of entries in @groups.
105 * @ngpio: The number of pingroups the driver should expose as GPIOs.
106 */
107struct msm_pinctrl_soc_data {
108 const struct pinctrl_pin_desc *pins;
109 unsigned npins;
110 const struct msm_function *functions;
111 unsigned nfunctions;
112 const struct msm_pingroup *groups;
113 unsigned ngroups;
114 unsigned ngpios;
115};
116
117int msm_pinctrl_probe(struct platform_device *pdev,
118 const struct msm_pinctrl_soc_data *soc_data);
119int msm_pinctrl_remove(struct platform_device *pdev);
120
121#endif
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
new file mode 100644
index 000000000000..35047036a053
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -0,0 +1,1282 @@
1/*
2 * Copyright (c) 2014, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc msm8960_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169 PINCTRL_PIN(146, "GPIO_146"),
170 PINCTRL_PIN(147, "GPIO_147"),
171 PINCTRL_PIN(148, "GPIO_148"),
172 PINCTRL_PIN(149, "GPIO_149"),
173 PINCTRL_PIN(150, "GPIO_150"),
174 PINCTRL_PIN(151, "GPIO_151"),
175
176 PINCTRL_PIN(152, "SDC1_CLK"),
177 PINCTRL_PIN(153, "SDC1_CMD"),
178 PINCTRL_PIN(154, "SDC1_DATA"),
179 PINCTRL_PIN(155, "SDC3_CLK"),
180 PINCTRL_PIN(156, "SDC3_CMD"),
181 PINCTRL_PIN(157, "SDC3_DATA"),
182};
183
184#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
185DECLARE_MSM_GPIO_PINS(0);
186DECLARE_MSM_GPIO_PINS(1);
187DECLARE_MSM_GPIO_PINS(2);
188DECLARE_MSM_GPIO_PINS(3);
189DECLARE_MSM_GPIO_PINS(4);
190DECLARE_MSM_GPIO_PINS(5);
191DECLARE_MSM_GPIO_PINS(6);
192DECLARE_MSM_GPIO_PINS(7);
193DECLARE_MSM_GPIO_PINS(8);
194DECLARE_MSM_GPIO_PINS(9);
195DECLARE_MSM_GPIO_PINS(10);
196DECLARE_MSM_GPIO_PINS(11);
197DECLARE_MSM_GPIO_PINS(12);
198DECLARE_MSM_GPIO_PINS(13);
199DECLARE_MSM_GPIO_PINS(14);
200DECLARE_MSM_GPIO_PINS(15);
201DECLARE_MSM_GPIO_PINS(16);
202DECLARE_MSM_GPIO_PINS(17);
203DECLARE_MSM_GPIO_PINS(18);
204DECLARE_MSM_GPIO_PINS(19);
205DECLARE_MSM_GPIO_PINS(20);
206DECLARE_MSM_GPIO_PINS(21);
207DECLARE_MSM_GPIO_PINS(22);
208DECLARE_MSM_GPIO_PINS(23);
209DECLARE_MSM_GPIO_PINS(24);
210DECLARE_MSM_GPIO_PINS(25);
211DECLARE_MSM_GPIO_PINS(26);
212DECLARE_MSM_GPIO_PINS(27);
213DECLARE_MSM_GPIO_PINS(28);
214DECLARE_MSM_GPIO_PINS(29);
215DECLARE_MSM_GPIO_PINS(30);
216DECLARE_MSM_GPIO_PINS(31);
217DECLARE_MSM_GPIO_PINS(32);
218DECLARE_MSM_GPIO_PINS(33);
219DECLARE_MSM_GPIO_PINS(34);
220DECLARE_MSM_GPIO_PINS(35);
221DECLARE_MSM_GPIO_PINS(36);
222DECLARE_MSM_GPIO_PINS(37);
223DECLARE_MSM_GPIO_PINS(38);
224DECLARE_MSM_GPIO_PINS(39);
225DECLARE_MSM_GPIO_PINS(40);
226DECLARE_MSM_GPIO_PINS(41);
227DECLARE_MSM_GPIO_PINS(42);
228DECLARE_MSM_GPIO_PINS(43);
229DECLARE_MSM_GPIO_PINS(44);
230DECLARE_MSM_GPIO_PINS(45);
231DECLARE_MSM_GPIO_PINS(46);
232DECLARE_MSM_GPIO_PINS(47);
233DECLARE_MSM_GPIO_PINS(48);
234DECLARE_MSM_GPIO_PINS(49);
235DECLARE_MSM_GPIO_PINS(50);
236DECLARE_MSM_GPIO_PINS(51);
237DECLARE_MSM_GPIO_PINS(52);
238DECLARE_MSM_GPIO_PINS(53);
239DECLARE_MSM_GPIO_PINS(54);
240DECLARE_MSM_GPIO_PINS(55);
241DECLARE_MSM_GPIO_PINS(56);
242DECLARE_MSM_GPIO_PINS(57);
243DECLARE_MSM_GPIO_PINS(58);
244DECLARE_MSM_GPIO_PINS(59);
245DECLARE_MSM_GPIO_PINS(60);
246DECLARE_MSM_GPIO_PINS(61);
247DECLARE_MSM_GPIO_PINS(62);
248DECLARE_MSM_GPIO_PINS(63);
249DECLARE_MSM_GPIO_PINS(64);
250DECLARE_MSM_GPIO_PINS(65);
251DECLARE_MSM_GPIO_PINS(66);
252DECLARE_MSM_GPIO_PINS(67);
253DECLARE_MSM_GPIO_PINS(68);
254DECLARE_MSM_GPIO_PINS(69);
255DECLARE_MSM_GPIO_PINS(70);
256DECLARE_MSM_GPIO_PINS(71);
257DECLARE_MSM_GPIO_PINS(72);
258DECLARE_MSM_GPIO_PINS(73);
259DECLARE_MSM_GPIO_PINS(74);
260DECLARE_MSM_GPIO_PINS(75);
261DECLARE_MSM_GPIO_PINS(76);
262DECLARE_MSM_GPIO_PINS(77);
263DECLARE_MSM_GPIO_PINS(78);
264DECLARE_MSM_GPIO_PINS(79);
265DECLARE_MSM_GPIO_PINS(80);
266DECLARE_MSM_GPIO_PINS(81);
267DECLARE_MSM_GPIO_PINS(82);
268DECLARE_MSM_GPIO_PINS(83);
269DECLARE_MSM_GPIO_PINS(84);
270DECLARE_MSM_GPIO_PINS(85);
271DECLARE_MSM_GPIO_PINS(86);
272DECLARE_MSM_GPIO_PINS(87);
273DECLARE_MSM_GPIO_PINS(88);
274DECLARE_MSM_GPIO_PINS(89);
275DECLARE_MSM_GPIO_PINS(90);
276DECLARE_MSM_GPIO_PINS(91);
277DECLARE_MSM_GPIO_PINS(92);
278DECLARE_MSM_GPIO_PINS(93);
279DECLARE_MSM_GPIO_PINS(94);
280DECLARE_MSM_GPIO_PINS(95);
281DECLARE_MSM_GPIO_PINS(96);
282DECLARE_MSM_GPIO_PINS(97);
283DECLARE_MSM_GPIO_PINS(98);
284DECLARE_MSM_GPIO_PINS(99);
285DECLARE_MSM_GPIO_PINS(100);
286DECLARE_MSM_GPIO_PINS(101);
287DECLARE_MSM_GPIO_PINS(102);
288DECLARE_MSM_GPIO_PINS(103);
289DECLARE_MSM_GPIO_PINS(104);
290DECLARE_MSM_GPIO_PINS(105);
291DECLARE_MSM_GPIO_PINS(106);
292DECLARE_MSM_GPIO_PINS(107);
293DECLARE_MSM_GPIO_PINS(108);
294DECLARE_MSM_GPIO_PINS(109);
295DECLARE_MSM_GPIO_PINS(110);
296DECLARE_MSM_GPIO_PINS(111);
297DECLARE_MSM_GPIO_PINS(112);
298DECLARE_MSM_GPIO_PINS(113);
299DECLARE_MSM_GPIO_PINS(114);
300DECLARE_MSM_GPIO_PINS(115);
301DECLARE_MSM_GPIO_PINS(116);
302DECLARE_MSM_GPIO_PINS(117);
303DECLARE_MSM_GPIO_PINS(118);
304DECLARE_MSM_GPIO_PINS(119);
305DECLARE_MSM_GPIO_PINS(120);
306DECLARE_MSM_GPIO_PINS(121);
307DECLARE_MSM_GPIO_PINS(122);
308DECLARE_MSM_GPIO_PINS(123);
309DECLARE_MSM_GPIO_PINS(124);
310DECLARE_MSM_GPIO_PINS(125);
311DECLARE_MSM_GPIO_PINS(126);
312DECLARE_MSM_GPIO_PINS(127);
313DECLARE_MSM_GPIO_PINS(128);
314DECLARE_MSM_GPIO_PINS(129);
315DECLARE_MSM_GPIO_PINS(130);
316DECLARE_MSM_GPIO_PINS(131);
317DECLARE_MSM_GPIO_PINS(132);
318DECLARE_MSM_GPIO_PINS(133);
319DECLARE_MSM_GPIO_PINS(134);
320DECLARE_MSM_GPIO_PINS(135);
321DECLARE_MSM_GPIO_PINS(136);
322DECLARE_MSM_GPIO_PINS(137);
323DECLARE_MSM_GPIO_PINS(138);
324DECLARE_MSM_GPIO_PINS(139);
325DECLARE_MSM_GPIO_PINS(140);
326DECLARE_MSM_GPIO_PINS(141);
327DECLARE_MSM_GPIO_PINS(142);
328DECLARE_MSM_GPIO_PINS(143);
329DECLARE_MSM_GPIO_PINS(144);
330DECLARE_MSM_GPIO_PINS(145);
331DECLARE_MSM_GPIO_PINS(146);
332DECLARE_MSM_GPIO_PINS(147);
333DECLARE_MSM_GPIO_PINS(148);
334DECLARE_MSM_GPIO_PINS(149);
335DECLARE_MSM_GPIO_PINS(150);
336DECLARE_MSM_GPIO_PINS(151);
337
338static const unsigned int sdc1_clk_pins[] = { 152 };
339static const unsigned int sdc1_cmd_pins[] = { 153 };
340static const unsigned int sdc1_data_pins[] = { 154 };
341static const unsigned int sdc3_clk_pins[] = { 155 };
342static const unsigned int sdc3_cmd_pins[] = { 156 };
343static const unsigned int sdc3_data_pins[] = { 157 };
344
345#define FUNCTION(fname) \
346 [MSM_MUX_##fname] = { \
347 .name = #fname, \
348 .groups = fname##_groups, \
349 .ngroups = ARRAY_SIZE(fname##_groups), \
350 }
351
352#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
353 { \
354 .name = "gpio" #id, \
355 .pins = gpio##id##_pins, \
356 .npins = ARRAY_SIZE(gpio##id##_pins), \
357 .funcs = (int[]){ \
358 MSM_MUX_gpio, \
359 MSM_MUX_##f1, \
360 MSM_MUX_##f2, \
361 MSM_MUX_##f3, \
362 MSM_MUX_##f4, \
363 MSM_MUX_##f5, \
364 MSM_MUX_##f6, \
365 MSM_MUX_##f7, \
366 MSM_MUX_##f8, \
367 MSM_MUX_##f9, \
368 MSM_MUX_##f10, \
369 MSM_MUX_##f11 \
370 }, \
371 .nfuncs = 12, \
372 .ctl_reg = 0x1000 + 0x10 * id, \
373 .io_reg = 0x1004 + 0x10 * id, \
374 .intr_cfg_reg = 0x1008 + 0x10 * id, \
375 .intr_status_reg = 0x100c + 0x10 * id, \
376 .intr_target_reg = 0x400 + 0x4 * id, \
377 .mux_bit = 2, \
378 .pull_bit = 0, \
379 .drv_bit = 6, \
380 .oe_bit = 9, \
381 .in_bit = 0, \
382 .out_bit = 1, \
383 .intr_enable_bit = 0, \
384 .intr_status_bit = 0, \
385 .intr_ack_high = 1, \
386 .intr_target_bit = 0, \
387 .intr_raw_status_bit = 3, \
388 .intr_polarity_bit = 1, \
389 .intr_detection_bit = 2, \
390 .intr_detection_width = 1, \
391 }
392
393#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
394 { \
395 .name = #pg_name, \
396 .pins = pg_name##_pins, \
397 .npins = ARRAY_SIZE(pg_name##_pins), \
398 .ctl_reg = ctl, \
399 .io_reg = 0, \
400 .intr_cfg_reg = 0, \
401 .intr_status_reg = 0, \
402 .intr_target_reg = 0, \
403 .mux_bit = -1, \
404 .pull_bit = pull, \
405 .drv_bit = drv, \
406 .oe_bit = -1, \
407 .in_bit = -1, \
408 .out_bit = -1, \
409 .intr_enable_bit = -1, \
410 .intr_status_bit = -1, \
411 .intr_target_bit = -1, \
412 .intr_raw_status_bit = -1, \
413 .intr_polarity_bit = -1, \
414 .intr_detection_bit = -1, \
415 .intr_detection_width = -1, \
416 }
417
418enum msm8960_functions {
419 MSM_MUX_audio_pcm,
420 MSM_MUX_bt,
421 MSM_MUX_cam_mclk0,
422 MSM_MUX_cam_mclk1,
423 MSM_MUX_cam_mclk2,
424 MSM_MUX_codec_mic_i2s,
425 MSM_MUX_codec_spkr_i2s,
426 MSM_MUX_ext_gps,
427 MSM_MUX_fm,
428 MSM_MUX_gps_blanking,
429 MSM_MUX_gps_pps_in,
430 MSM_MUX_gps_pps_out,
431 MSM_MUX_gp_clk_0a,
432 MSM_MUX_gp_clk_0b,
433 MSM_MUX_gp_clk_1a,
434 MSM_MUX_gp_clk_1b,
435 MSM_MUX_gp_clk_2a,
436 MSM_MUX_gp_clk_2b,
437 MSM_MUX_gp_mn,
438 MSM_MUX_gp_pdm_0a,
439 MSM_MUX_gp_pdm_0b,
440 MSM_MUX_gp_pdm_1a,
441 MSM_MUX_gp_pdm_1b,
442 MSM_MUX_gp_pdm_2a,
443 MSM_MUX_gp_pdm_2b,
444 MSM_MUX_gpio,
445 MSM_MUX_gsbi1,
446 MSM_MUX_gsbi1_spi_cs1_n,
447 MSM_MUX_gsbi1_spi_cs2a_n,
448 MSM_MUX_gsbi1_spi_cs2b_n,
449 MSM_MUX_gsbi1_spi_cs3_n,
450 MSM_MUX_gsbi2,
451 MSM_MUX_gsbi2_spi_cs1_n,
452 MSM_MUX_gsbi2_spi_cs2_n,
453 MSM_MUX_gsbi2_spi_cs3_n,
454 MSM_MUX_gsbi3,
455 MSM_MUX_gsbi4,
456 MSM_MUX_gsbi4_3d_cam_i2c_l,
457 MSM_MUX_gsbi4_3d_cam_i2c_r,
458 MSM_MUX_gsbi5,
459 MSM_MUX_gsbi5_3d_cam_i2c_l,
460 MSM_MUX_gsbi5_3d_cam_i2c_r,
461 MSM_MUX_gsbi6,
462 MSM_MUX_gsbi7,
463 MSM_MUX_gsbi8,
464 MSM_MUX_gsbi9,
465 MSM_MUX_gsbi10,
466 MSM_MUX_gsbi11,
467 MSM_MUX_gsbi11_spi_cs1a_n,
468 MSM_MUX_gsbi11_spi_cs1b_n,
469 MSM_MUX_gsbi11_spi_cs2a_n,
470 MSM_MUX_gsbi11_spi_cs2b_n,
471 MSM_MUX_gsbi11_spi_cs3_n,
472 MSM_MUX_gsbi12,
473 MSM_MUX_hdmi_cec,
474 MSM_MUX_hdmi_ddc_clock,
475 MSM_MUX_hdmi_ddc_data,
476 MSM_MUX_hdmi_hot_plug_detect,
477 MSM_MUX_hsic,
478 MSM_MUX_mdp_vsync,
479 MSM_MUX_mi2s,
480 MSM_MUX_mic_i2s,
481 MSM_MUX_pmb_clk,
482 MSM_MUX_pmb_ext_ctrl,
483 MSM_MUX_ps_hold,
484 MSM_MUX_rpm_wdog,
485 MSM_MUX_sdc2,
486 MSM_MUX_sdc4,
487 MSM_MUX_sdc5,
488 MSM_MUX_slimbus1,
489 MSM_MUX_slimbus2,
490 MSM_MUX_spkr_i2s,
491 MSM_MUX_ssbi1,
492 MSM_MUX_ssbi2,
493 MSM_MUX_ssbi_ext_gps,
494 MSM_MUX_ssbi_pmic2,
495 MSM_MUX_ssbi_qpa1,
496 MSM_MUX_ssbi_ts,
497 MSM_MUX_tsif1,
498 MSM_MUX_tsif2,
499 MSM_MUX_ts_eoc,
500 MSM_MUX_usb_fs1,
501 MSM_MUX_usb_fs1_oe,
502 MSM_MUX_usb_fs1_oe_n,
503 MSM_MUX_usb_fs2,
504 MSM_MUX_usb_fs2_oe,
505 MSM_MUX_usb_fs2_oe_n,
506 MSM_MUX_vfe_camif_timer1_a,
507 MSM_MUX_vfe_camif_timer1_b,
508 MSM_MUX_vfe_camif_timer2,
509 MSM_MUX_vfe_camif_timer3_a,
510 MSM_MUX_vfe_camif_timer3_b,
511 MSM_MUX_vfe_camif_timer4_a,
512 MSM_MUX_vfe_camif_timer4_b,
513 MSM_MUX_vfe_camif_timer4_c,
514 MSM_MUX_vfe_camif_timer5_a,
515 MSM_MUX_vfe_camif_timer5_b,
516 MSM_MUX_vfe_camif_timer6_a,
517 MSM_MUX_vfe_camif_timer6_b,
518 MSM_MUX_vfe_camif_timer6_c,
519 MSM_MUX_vfe_camif_timer7_a,
520 MSM_MUX_vfe_camif_timer7_b,
521 MSM_MUX_vfe_camif_timer7_c,
522 MSM_MUX_wlan,
523 MSM_MUX_NA,
524};
525
526static const char * const audio_pcm_groups[] = {
527 "gpio63", "gpio64", "gpio65", "gpio66"
528};
529
530static const char * const bt_groups[] = {
531 "gpio28", "gpio29", "gpio83"
532};
533
534static const char * const cam_mclk0_groups[] = {
535 "gpio5"
536};
537
538static const char * const cam_mclk1_groups[] = {
539 "gpio4"
540};
541
542static const char * const cam_mclk2_groups[] = {
543 "gpio2"
544};
545
546static const char * const codec_mic_i2s_groups[] = {
547 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58"
548};
549
550static const char * const codec_spkr_i2s_groups[] = {
551 "gpio59", "gpio60", "gpio61", "gpio62"
552};
553
554static const char * const ext_gps_groups[] = {
555 "gpio22", "gpio23", "gpio24", "gpio25"
556};
557
558static const char * const fm_groups[] = {
559 "gpio26", "gpio27"
560};
561
562static const char * const gps_blanking_groups[] = {
563 "gpio137"
564};
565
566static const char * const gps_pps_in_groups[] = {
567 "gpio37"
568};
569
570static const char * const gps_pps_out_groups[] = {
571 "gpio37"
572};
573
574static const char * const gp_clk_0a_groups[] = {
575 "gpio3"
576};
577
578static const char * const gp_clk_0b_groups[] = {
579 "gpio54"
580};
581
582static const char * const gp_clk_1a_groups[] = {
583 "gpio4"
584};
585
586static const char * const gp_clk_1b_groups[] = {
587 "gpio70"
588};
589
590static const char * const gp_clk_2a_groups[] = {
591 "gpio52"
592};
593
594static const char * const gp_clk_2b_groups[] = {
595 "gpio37"
596};
597
598static const char * const gp_mn_groups[] = {
599 "gpio2"
600};
601
602static const char * const gp_pdm_0a_groups[] = {
603 "gpio58"
604};
605
606static const char * const gp_pdm_0b_groups[] = {
607 "gpio39"
608};
609
610static const char * const gp_pdm_1a_groups[] = {
611 "gpio94"
612};
613
614static const char * const gp_pdm_1b_groups[] = {
615 "gpio64"
616};
617
618static const char * const gp_pdm_2a_groups[] = {
619 "gpio69"
620};
621
622static const char * const gp_pdm_2b_groups[] = {
623 "gpio53"
624};
625
626static const char * const gpio_groups[] = {
627 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
628 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
629 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
630 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
631 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
632 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
633 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
634 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
635 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
636 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
637 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
638 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
639 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
640 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
641 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
642 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
643 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
644 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
645 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
646 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
647 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
648 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
649 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151"
650};
651
652static const char * const gsbi1_groups[] = {
653 "gpio6", "gpio7", "gpio8", "gpio9"
654};
655
656static const char * const gsbi1_spi_cs1_n_groups[] = {
657 "gpio14"
658};
659
660static const char * const gsbi1_spi_cs2a_n_groups[] = {
661 "gpio15"
662};
663
664static const char * const gsbi1_spi_cs2b_n_groups[] = {
665 "gpio17"
666};
667
668static const char * const gsbi1_spi_cs3_n_groups[] = {
669 "gpio16"
670};
671
672static const char * const gsbi2_groups[] = {
673 "gpio10", "gpio11", "gpio12", "gpio13"
674};
675
676static const char * const gsbi2_spi_cs1_n_groups[] = {
677 "gpio52"
678};
679
680static const char * const gsbi2_spi_cs2_n_groups[] = {
681 "gpio68"
682};
683
684static const char * const gsbi2_spi_cs3_n_groups[] = {
685 "gpio56"
686};
687
688static const char * const gsbi3_groups[] = {
689 "gpio14", "gpio15", "gpio16", "gpio17"
690};
691
692static const char * const gsbi4_groups[] = {
693 "gpio18", "gpio19", "gpio20", "gpio21"
694};
695
696static const char * const gsbi4_3d_cam_i2c_l_groups[] = {
697 "gpio18", "gpio19"
698};
699
700static const char * const gsbi4_3d_cam_i2c_r_groups[] = {
701 "gpio20", "gpio21"
702};
703
704static const char * const gsbi5_groups[] = {
705 "gpio22", "gpio23", "gpio24", "gpio25"
706};
707
708static const char * const gsbi5_3d_cam_i2c_l_groups[] = {
709 "gpio22", "gpio23"
710};
711
712static const char * const gsbi5_3d_cam_i2c_r_groups[] = {
713 "gpio24", "gpio25"
714};
715
716static const char * const gsbi6_groups[] = {
717 "gpio26", "gpio27", "gpio28", "gpio29"
718};
719
720static const char * const gsbi7_groups[] = {
721 "gpio30", "gpio31", "gpio32", "gpio33"
722};
723
724static const char * const gsbi8_groups[] = {
725 "gpio34", "gpio35", "gpio36", "gpio37"
726};
727
728static const char * const gsbi9_groups[] = {
729 "gpio93", "gpio94", "gpio95", "gpio96"
730};
731
732static const char * const gsbi10_groups[] = {
733 "gpio71", "gpio72", "gpio73", "gpio74"
734};
735
736static const char * const gsbi11_groups[] = {
737 "gpio38", "gpio39", "gpio40", "gpio41"
738};
739
740static const char * const gsbi11_spi_cs1a_n_groups[] = {
741 "gpio36"
742};
743
744static const char * const gsbi11_spi_cs1b_n_groups[] = {
745 "gpio18"
746};
747
748static const char * const gsbi11_spi_cs2a_n_groups[] = {
749 "gpio37"
750};
751
752static const char * const gsbi11_spi_cs2b_n_groups[] = {
753 "gpio19"
754};
755
756static const char * const gsbi11_spi_cs3_n_groups[] = {
757 "gpio76"
758};
759
760static const char * const gsbi12_groups[] = {
761 "gpio42", "gpio43", "gpio44", "gpio45"
762};
763
764static const char * const hdmi_cec_groups[] = {
765 "gpio99"
766};
767
768static const char * const hdmi_ddc_clock_groups[] = {
769 "gpio100"
770};
771
772static const char * const hdmi_ddc_data_groups[] = {
773 "gpio101"
774};
775
776static const char * const hdmi_hot_plug_detect_groups[] = {
777 "gpio102"
778};
779
780static const char * const hsic_groups[] = {
781 "gpio150", "gpio151"
782};
783
784static const char * const mdp_vsync_groups[] = {
785 "gpio0", "gpio1", "gpio19"
786};
787
788static const char * const mi2s_groups[] = {
789 "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53"
790};
791
792static const char * const mic_i2s_groups[] = {
793 "gpio71", "gpio72", "gpio73", "gpio74"
794};
795
796static const char * const pmb_clk_groups[] = {
797 "gpio21", "gpio86", "gpio112"
798};
799
800static const char * const pmb_ext_ctrl_groups[] = {
801 "gpio4", "gpio5"
802};
803
804static const char * const ps_hold_groups[] = {
805 "gpio108"
806};
807
808static const char * const rpm_wdog_groups[] = {
809 "gpio12"
810};
811
812static const char * const sdc2_groups[] = {
813 "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
814 "gpio96", "gpio97", "gpio98"
815};
816
817static const char * const sdc4_groups[] = {
818 "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
819};
820
821static const char * const sdc5_groups[] = {
822 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
823};
824
825static const char * const slimbus1_groups[] = {
826 "gpio50", "gpio51", "gpio60", "gpio61"
827};
828
829static const char * const slimbus2_groups[] = {
830 "gpio42", "gpio43"
831};
832
833static const char * const spkr_i2s_groups[] = {
834 "gpio67", "gpio68", "gpio69", "gpio70"
835};
836
837static const char * const ssbi1_groups[] = {
838 "gpio141", "gpio143"
839};
840
841static const char * const ssbi2_groups[] = {
842 "gpio140", "gpio142"
843};
844
845static const char * const ssbi_ext_gps_groups[] = {
846 "gpio23"
847};
848
849static const char * const ssbi_pmic2_groups[] = {
850 "gpio149"
851};
852
853static const char * const ssbi_qpa1_groups[] = {
854 "gpio131"
855};
856
857static const char * const ssbi_ts_groups[] = {
858 "gpio10"
859};
860
861static const char * const tsif1_groups[] = {
862 "gpio75", "gpio76", "gpio77", "gpio82"
863};
864
865static const char * const tsif2_groups[] = {
866 "gpio78", "gpio79", "gpio80", "gpio81"
867};
868
869static const char * const ts_eoc_groups[] = {
870 "gpio11"
871};
872
873static const char * const usb_fs1_groups[] = {
874 "gpio32", "gpio33"
875};
876
877static const char * const usb_fs1_oe_groups[] = {
878 "gpio31"
879};
880
881static const char * const usb_fs1_oe_n_groups[] = {
882 "gpio31"
883};
884
885static const char * const usb_fs2_groups[] = {
886 "gpio34", "gpio35"
887};
888
889static const char * const usb_fs2_oe_groups[] = {
890 "gpio36"
891};
892
893static const char * const usb_fs2_oe_n_groups[] = {
894 "gpio36"
895};
896
897static const char * const vfe_camif_timer1_a_groups[] = {
898 "gpio2"
899};
900
901static const char * const vfe_camif_timer1_b_groups[] = {
902 "gpio38"
903};
904
905static const char * const vfe_camif_timer2_groups[] = {
906 "gpio3"
907};
908
909static const char * const vfe_camif_timer3_a_groups[] = {
910 "gpio4"
911};
912
913static const char * const vfe_camif_timer3_b_groups[] = {
914 "gpio151"
915};
916
917static const char * const vfe_camif_timer4_a_groups[] = {
918 "gpio65"
919};
920
921static const char * const vfe_camif_timer4_b_groups[] = {
922 "gpio150"
923};
924
925static const char * const vfe_camif_timer4_c_groups[] = {
926 "gpio10"
927};
928
929static const char * const vfe_camif_timer5_a_groups[] = {
930 "gpio66"
931};
932
933static const char * const vfe_camif_timer5_b_groups[] = {
934 "gpio39"
935};
936
937static const char * const vfe_camif_timer6_a_groups[] = {
938 "gpio71"
939};
940
941static const char * const vfe_camif_timer6_b_groups[] = {
942 "gpio0"
943};
944
945static const char * const vfe_camif_timer6_c_groups[] = {
946 "gpio18"
947};
948
949static const char * const vfe_camif_timer7_a_groups[] = {
950 "gpio67"
951};
952
953static const char * const vfe_camif_timer7_b_groups[] = {
954 "gpio1"
955};
956
957static const char * const vfe_camif_timer7_c_groups[] = {
958 "gpio19"
959};
960
961static const char * const wlan_groups[] = {
962 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
963};
964
965static const struct msm_function msm8960_functions[] = {
966 FUNCTION(audio_pcm),
967 FUNCTION(bt),
968 FUNCTION(cam_mclk0),
969 FUNCTION(cam_mclk1),
970 FUNCTION(cam_mclk2),
971 FUNCTION(codec_mic_i2s),
972 FUNCTION(codec_spkr_i2s),
973 FUNCTION(ext_gps),
974 FUNCTION(fm),
975 FUNCTION(gps_blanking),
976 FUNCTION(gps_pps_in),
977 FUNCTION(gps_pps_out),
978 FUNCTION(gp_clk_0a),
979 FUNCTION(gp_clk_0b),
980 FUNCTION(gp_clk_1a),
981 FUNCTION(gp_clk_1b),
982 FUNCTION(gp_clk_2a),
983 FUNCTION(gp_clk_2b),
984 FUNCTION(gp_mn),
985 FUNCTION(gp_pdm_0a),
986 FUNCTION(gp_pdm_0b),
987 FUNCTION(gp_pdm_1a),
988 FUNCTION(gp_pdm_1b),
989 FUNCTION(gp_pdm_2a),
990 FUNCTION(gp_pdm_2b),
991 FUNCTION(gpio),
992 FUNCTION(gsbi1),
993 FUNCTION(gsbi1_spi_cs1_n),
994 FUNCTION(gsbi1_spi_cs2a_n),
995 FUNCTION(gsbi1_spi_cs2b_n),
996 FUNCTION(gsbi1_spi_cs3_n),
997 FUNCTION(gsbi2),
998 FUNCTION(gsbi2_spi_cs1_n),
999 FUNCTION(gsbi2_spi_cs2_n),
1000 FUNCTION(gsbi2_spi_cs3_n),
1001 FUNCTION(gsbi3),
1002 FUNCTION(gsbi4),
1003 FUNCTION(gsbi4_3d_cam_i2c_l),
1004 FUNCTION(gsbi4_3d_cam_i2c_r),
1005 FUNCTION(gsbi5),
1006 FUNCTION(gsbi5_3d_cam_i2c_l),
1007 FUNCTION(gsbi5_3d_cam_i2c_r),
1008 FUNCTION(gsbi6),
1009 FUNCTION(gsbi7),
1010 FUNCTION(gsbi8),
1011 FUNCTION(gsbi9),
1012 FUNCTION(gsbi10),
1013 FUNCTION(gsbi11),
1014 FUNCTION(gsbi11_spi_cs1a_n),
1015 FUNCTION(gsbi11_spi_cs1b_n),
1016 FUNCTION(gsbi11_spi_cs2a_n),
1017 FUNCTION(gsbi11_spi_cs2b_n),
1018 FUNCTION(gsbi11_spi_cs3_n),
1019 FUNCTION(gsbi12),
1020 FUNCTION(hdmi_cec),
1021 FUNCTION(hdmi_ddc_clock),
1022 FUNCTION(hdmi_ddc_data),
1023 FUNCTION(hdmi_hot_plug_detect),
1024 FUNCTION(hsic),
1025 FUNCTION(mdp_vsync),
1026 FUNCTION(mi2s),
1027 FUNCTION(mic_i2s),
1028 FUNCTION(pmb_clk),
1029 FUNCTION(pmb_ext_ctrl),
1030 FUNCTION(ps_hold),
1031 FUNCTION(rpm_wdog),
1032 FUNCTION(sdc2),
1033 FUNCTION(sdc4),
1034 FUNCTION(sdc5),
1035 FUNCTION(slimbus1),
1036 FUNCTION(slimbus2),
1037 FUNCTION(spkr_i2s),
1038 FUNCTION(ssbi1),
1039 FUNCTION(ssbi2),
1040 FUNCTION(ssbi_ext_gps),
1041 FUNCTION(ssbi_pmic2),
1042 FUNCTION(ssbi_qpa1),
1043 FUNCTION(ssbi_ts),
1044 FUNCTION(tsif1),
1045 FUNCTION(tsif2),
1046 FUNCTION(ts_eoc),
1047 FUNCTION(usb_fs1),
1048 FUNCTION(usb_fs1_oe),
1049 FUNCTION(usb_fs1_oe_n),
1050 FUNCTION(usb_fs2),
1051 FUNCTION(usb_fs2_oe),
1052 FUNCTION(usb_fs2_oe_n),
1053 FUNCTION(vfe_camif_timer1_a),
1054 FUNCTION(vfe_camif_timer1_b),
1055 FUNCTION(vfe_camif_timer2),
1056 FUNCTION(vfe_camif_timer3_a),
1057 FUNCTION(vfe_camif_timer3_b),
1058 FUNCTION(vfe_camif_timer4_a),
1059 FUNCTION(vfe_camif_timer4_b),
1060 FUNCTION(vfe_camif_timer4_c),
1061 FUNCTION(vfe_camif_timer5_a),
1062 FUNCTION(vfe_camif_timer5_b),
1063 FUNCTION(vfe_camif_timer6_a),
1064 FUNCTION(vfe_camif_timer6_b),
1065 FUNCTION(vfe_camif_timer6_c),
1066 FUNCTION(vfe_camif_timer7_a),
1067 FUNCTION(vfe_camif_timer7_b),
1068 FUNCTION(vfe_camif_timer7_c),
1069 FUNCTION(wlan),
1070};
1071
1072static const struct msm_pingroup msm8960_groups[] = {
1073 PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1074 PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1075 PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA),
1076 PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1077 PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA),
1078 PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1079 PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1080 PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1081 PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1082 PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1083 PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA),
1084 PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1085 PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1086 PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1087 PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1088 PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1089 PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1090 PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1091 PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA),
1092 PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA),
1093 PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1094 PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA),
1095 PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA),
1096 PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA),
1097 PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA),
1098 PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA),
1099 PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1100 PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1101 PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1102 PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1103 PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1104 PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA),
1105 PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1106 PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1107 PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1108 PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1109 PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA),
1110 PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA),
1111 PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA),
1112 PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b),
1113 PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1114 PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1115 PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1116 PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1117 PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1118 PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1119 PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1120 PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1121 PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1122 PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1123 PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1124 PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1125 PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA),
1126 PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1127 PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1128 PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1129 PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1130 PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1131 PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1132 PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1133 PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1134 PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1135 PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1136 PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1137 PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1138 PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1139 PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1140 PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1141 PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1142 PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1143 PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1144 PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA),
1145 PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1146 PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1147 PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1148 PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1149 PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1150 PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1151 PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1152 PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1153 PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1154 PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1155 PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1156 PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1157 PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1158 PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1159 PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA),
1160 PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1161 PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1162 PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1163 PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1164 PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1165 PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1166 PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1167 PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA),
1168 PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1169 PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1170 PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1171 PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1172 PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1173 PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1174 PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1175 PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1176 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1177 PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1178 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1179 PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1180 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1181 PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1182 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1183 PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1184 PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1185 PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1186 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1187 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1188 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1189 PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1190 PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1191 PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1192 PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1193 PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1194 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1195 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1196 PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1197 PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1198 PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1199 PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1200 PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1201 PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1202 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1203 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1204 PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1205 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1206 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1207 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1208 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1209 PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1210 PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1211 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1212 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1213 PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1214 PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1215 PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1216 PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1217 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1218 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1219 PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1220 PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1221 PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1222 PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1223 PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA),
1224 PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA),
1225
1226 SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6),
1227 SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3),
1228 SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0),
1229
1230 SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6),
1231 SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3),
1232 SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0),
1233};
1234
1235#define NUM_GPIO_PINGROUPS 152
1236
1237static const struct msm_pinctrl_soc_data msm8960_pinctrl = {
1238 .pins = msm8960_pins,
1239 .npins = ARRAY_SIZE(msm8960_pins),
1240 .functions = msm8960_functions,
1241 .nfunctions = ARRAY_SIZE(msm8960_functions),
1242 .groups = msm8960_groups,
1243 .ngroups = ARRAY_SIZE(msm8960_groups),
1244 .ngpios = NUM_GPIO_PINGROUPS,
1245};
1246
1247static int msm8960_pinctrl_probe(struct platform_device *pdev)
1248{
1249 return msm_pinctrl_probe(pdev, &msm8960_pinctrl);
1250}
1251
1252static const struct of_device_id msm8960_pinctrl_of_match[] = {
1253 { .compatible = "qcom,msm8960-pinctrl", },
1254 { },
1255};
1256
1257static struct platform_driver msm8960_pinctrl_driver = {
1258 .driver = {
1259 .name = "msm8960-pinctrl",
1260 .owner = THIS_MODULE,
1261 .of_match_table = msm8960_pinctrl_of_match,
1262 },
1263 .probe = msm8960_pinctrl_probe,
1264 .remove = msm_pinctrl_remove,
1265};
1266
1267static int __init msm8960_pinctrl_init(void)
1268{
1269 return platform_driver_register(&msm8960_pinctrl_driver);
1270}
1271arch_initcall(msm8960_pinctrl_init);
1272
1273static void __exit msm8960_pinctrl_exit(void)
1274{
1275 platform_driver_unregister(&msm8960_pinctrl_driver);
1276}
1277module_exit(msm8960_pinctrl_exit);
1278
1279MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1280MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver");
1281MODULE_LICENSE("GPL v2");
1282MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
new file mode 100644
index 000000000000..8c9720154d1e
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -0,0 +1,1067 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-msm.h"
20
21static const struct pinctrl_pin_desc msm8x74_pins[] = {
22 PINCTRL_PIN(0, "GPIO_0"),
23 PINCTRL_PIN(1, "GPIO_1"),
24 PINCTRL_PIN(2, "GPIO_2"),
25 PINCTRL_PIN(3, "GPIO_3"),
26 PINCTRL_PIN(4, "GPIO_4"),
27 PINCTRL_PIN(5, "GPIO_5"),
28 PINCTRL_PIN(6, "GPIO_6"),
29 PINCTRL_PIN(7, "GPIO_7"),
30 PINCTRL_PIN(8, "GPIO_8"),
31 PINCTRL_PIN(9, "GPIO_9"),
32 PINCTRL_PIN(10, "GPIO_10"),
33 PINCTRL_PIN(11, "GPIO_11"),
34 PINCTRL_PIN(12, "GPIO_12"),
35 PINCTRL_PIN(13, "GPIO_13"),
36 PINCTRL_PIN(14, "GPIO_14"),
37 PINCTRL_PIN(15, "GPIO_15"),
38 PINCTRL_PIN(16, "GPIO_16"),
39 PINCTRL_PIN(17, "GPIO_17"),
40 PINCTRL_PIN(18, "GPIO_18"),
41 PINCTRL_PIN(19, "GPIO_19"),
42 PINCTRL_PIN(20, "GPIO_20"),
43 PINCTRL_PIN(21, "GPIO_21"),
44 PINCTRL_PIN(22, "GPIO_22"),
45 PINCTRL_PIN(23, "GPIO_23"),
46 PINCTRL_PIN(24, "GPIO_24"),
47 PINCTRL_PIN(25, "GPIO_25"),
48 PINCTRL_PIN(26, "GPIO_26"),
49 PINCTRL_PIN(27, "GPIO_27"),
50 PINCTRL_PIN(28, "GPIO_28"),
51 PINCTRL_PIN(29, "GPIO_29"),
52 PINCTRL_PIN(30, "GPIO_30"),
53 PINCTRL_PIN(31, "GPIO_31"),
54 PINCTRL_PIN(32, "GPIO_32"),
55 PINCTRL_PIN(33, "GPIO_33"),
56 PINCTRL_PIN(34, "GPIO_34"),
57 PINCTRL_PIN(35, "GPIO_35"),
58 PINCTRL_PIN(36, "GPIO_36"),
59 PINCTRL_PIN(37, "GPIO_37"),
60 PINCTRL_PIN(38, "GPIO_38"),
61 PINCTRL_PIN(39, "GPIO_39"),
62 PINCTRL_PIN(40, "GPIO_40"),
63 PINCTRL_PIN(41, "GPIO_41"),
64 PINCTRL_PIN(42, "GPIO_42"),
65 PINCTRL_PIN(43, "GPIO_43"),
66 PINCTRL_PIN(44, "GPIO_44"),
67 PINCTRL_PIN(45, "GPIO_45"),
68 PINCTRL_PIN(46, "GPIO_46"),
69 PINCTRL_PIN(47, "GPIO_47"),
70 PINCTRL_PIN(48, "GPIO_48"),
71 PINCTRL_PIN(49, "GPIO_49"),
72 PINCTRL_PIN(50, "GPIO_50"),
73 PINCTRL_PIN(51, "GPIO_51"),
74 PINCTRL_PIN(52, "GPIO_52"),
75 PINCTRL_PIN(53, "GPIO_53"),
76 PINCTRL_PIN(54, "GPIO_54"),
77 PINCTRL_PIN(55, "GPIO_55"),
78 PINCTRL_PIN(56, "GPIO_56"),
79 PINCTRL_PIN(57, "GPIO_57"),
80 PINCTRL_PIN(58, "GPIO_58"),
81 PINCTRL_PIN(59, "GPIO_59"),
82 PINCTRL_PIN(60, "GPIO_60"),
83 PINCTRL_PIN(61, "GPIO_61"),
84 PINCTRL_PIN(62, "GPIO_62"),
85 PINCTRL_PIN(63, "GPIO_63"),
86 PINCTRL_PIN(64, "GPIO_64"),
87 PINCTRL_PIN(65, "GPIO_65"),
88 PINCTRL_PIN(66, "GPIO_66"),
89 PINCTRL_PIN(67, "GPIO_67"),
90 PINCTRL_PIN(68, "GPIO_68"),
91 PINCTRL_PIN(69, "GPIO_69"),
92 PINCTRL_PIN(70, "GPIO_70"),
93 PINCTRL_PIN(71, "GPIO_71"),
94 PINCTRL_PIN(72, "GPIO_72"),
95 PINCTRL_PIN(73, "GPIO_73"),
96 PINCTRL_PIN(74, "GPIO_74"),
97 PINCTRL_PIN(75, "GPIO_75"),
98 PINCTRL_PIN(76, "GPIO_76"),
99 PINCTRL_PIN(77, "GPIO_77"),
100 PINCTRL_PIN(78, "GPIO_78"),
101 PINCTRL_PIN(79, "GPIO_79"),
102 PINCTRL_PIN(80, "GPIO_80"),
103 PINCTRL_PIN(81, "GPIO_81"),
104 PINCTRL_PIN(82, "GPIO_82"),
105 PINCTRL_PIN(83, "GPIO_83"),
106 PINCTRL_PIN(84, "GPIO_84"),
107 PINCTRL_PIN(85, "GPIO_85"),
108 PINCTRL_PIN(86, "GPIO_86"),
109 PINCTRL_PIN(87, "GPIO_87"),
110 PINCTRL_PIN(88, "GPIO_88"),
111 PINCTRL_PIN(89, "GPIO_89"),
112 PINCTRL_PIN(90, "GPIO_90"),
113 PINCTRL_PIN(91, "GPIO_91"),
114 PINCTRL_PIN(92, "GPIO_92"),
115 PINCTRL_PIN(93, "GPIO_93"),
116 PINCTRL_PIN(94, "GPIO_94"),
117 PINCTRL_PIN(95, "GPIO_95"),
118 PINCTRL_PIN(96, "GPIO_96"),
119 PINCTRL_PIN(97, "GPIO_97"),
120 PINCTRL_PIN(98, "GPIO_98"),
121 PINCTRL_PIN(99, "GPIO_99"),
122 PINCTRL_PIN(100, "GPIO_100"),
123 PINCTRL_PIN(101, "GPIO_101"),
124 PINCTRL_PIN(102, "GPIO_102"),
125 PINCTRL_PIN(103, "GPIO_103"),
126 PINCTRL_PIN(104, "GPIO_104"),
127 PINCTRL_PIN(105, "GPIO_105"),
128 PINCTRL_PIN(106, "GPIO_106"),
129 PINCTRL_PIN(107, "GPIO_107"),
130 PINCTRL_PIN(108, "GPIO_108"),
131 PINCTRL_PIN(109, "GPIO_109"),
132 PINCTRL_PIN(110, "GPIO_110"),
133 PINCTRL_PIN(111, "GPIO_111"),
134 PINCTRL_PIN(112, "GPIO_112"),
135 PINCTRL_PIN(113, "GPIO_113"),
136 PINCTRL_PIN(114, "GPIO_114"),
137 PINCTRL_PIN(115, "GPIO_115"),
138 PINCTRL_PIN(116, "GPIO_116"),
139 PINCTRL_PIN(117, "GPIO_117"),
140 PINCTRL_PIN(118, "GPIO_118"),
141 PINCTRL_PIN(119, "GPIO_119"),
142 PINCTRL_PIN(120, "GPIO_120"),
143 PINCTRL_PIN(121, "GPIO_121"),
144 PINCTRL_PIN(122, "GPIO_122"),
145 PINCTRL_PIN(123, "GPIO_123"),
146 PINCTRL_PIN(124, "GPIO_124"),
147 PINCTRL_PIN(125, "GPIO_125"),
148 PINCTRL_PIN(126, "GPIO_126"),
149 PINCTRL_PIN(127, "GPIO_127"),
150 PINCTRL_PIN(128, "GPIO_128"),
151 PINCTRL_PIN(129, "GPIO_129"),
152 PINCTRL_PIN(130, "GPIO_130"),
153 PINCTRL_PIN(131, "GPIO_131"),
154 PINCTRL_PIN(132, "GPIO_132"),
155 PINCTRL_PIN(133, "GPIO_133"),
156 PINCTRL_PIN(134, "GPIO_134"),
157 PINCTRL_PIN(135, "GPIO_135"),
158 PINCTRL_PIN(136, "GPIO_136"),
159 PINCTRL_PIN(137, "GPIO_137"),
160 PINCTRL_PIN(138, "GPIO_138"),
161 PINCTRL_PIN(139, "GPIO_139"),
162 PINCTRL_PIN(140, "GPIO_140"),
163 PINCTRL_PIN(141, "GPIO_141"),
164 PINCTRL_PIN(142, "GPIO_142"),
165 PINCTRL_PIN(143, "GPIO_143"),
166 PINCTRL_PIN(144, "GPIO_144"),
167 PINCTRL_PIN(145, "GPIO_145"),
168
169 PINCTRL_PIN(146, "SDC1_CLK"),
170 PINCTRL_PIN(147, "SDC1_CMD"),
171 PINCTRL_PIN(148, "SDC1_DATA"),
172 PINCTRL_PIN(149, "SDC2_CLK"),
173 PINCTRL_PIN(150, "SDC2_CMD"),
174 PINCTRL_PIN(151, "SDC2_DATA"),
175};
176
177#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
178DECLARE_MSM_GPIO_PINS(0);
179DECLARE_MSM_GPIO_PINS(1);
180DECLARE_MSM_GPIO_PINS(2);
181DECLARE_MSM_GPIO_PINS(3);
182DECLARE_MSM_GPIO_PINS(4);
183DECLARE_MSM_GPIO_PINS(5);
184DECLARE_MSM_GPIO_PINS(6);
185DECLARE_MSM_GPIO_PINS(7);
186DECLARE_MSM_GPIO_PINS(8);
187DECLARE_MSM_GPIO_PINS(9);
188DECLARE_MSM_GPIO_PINS(10);
189DECLARE_MSM_GPIO_PINS(11);
190DECLARE_MSM_GPIO_PINS(12);
191DECLARE_MSM_GPIO_PINS(13);
192DECLARE_MSM_GPIO_PINS(14);
193DECLARE_MSM_GPIO_PINS(15);
194DECLARE_MSM_GPIO_PINS(16);
195DECLARE_MSM_GPIO_PINS(17);
196DECLARE_MSM_GPIO_PINS(18);
197DECLARE_MSM_GPIO_PINS(19);
198DECLARE_MSM_GPIO_PINS(20);
199DECLARE_MSM_GPIO_PINS(21);
200DECLARE_MSM_GPIO_PINS(22);
201DECLARE_MSM_GPIO_PINS(23);
202DECLARE_MSM_GPIO_PINS(24);
203DECLARE_MSM_GPIO_PINS(25);
204DECLARE_MSM_GPIO_PINS(26);
205DECLARE_MSM_GPIO_PINS(27);
206DECLARE_MSM_GPIO_PINS(28);
207DECLARE_MSM_GPIO_PINS(29);
208DECLARE_MSM_GPIO_PINS(30);
209DECLARE_MSM_GPIO_PINS(31);
210DECLARE_MSM_GPIO_PINS(32);
211DECLARE_MSM_GPIO_PINS(33);
212DECLARE_MSM_GPIO_PINS(34);
213DECLARE_MSM_GPIO_PINS(35);
214DECLARE_MSM_GPIO_PINS(36);
215DECLARE_MSM_GPIO_PINS(37);
216DECLARE_MSM_GPIO_PINS(38);
217DECLARE_MSM_GPIO_PINS(39);
218DECLARE_MSM_GPIO_PINS(40);
219DECLARE_MSM_GPIO_PINS(41);
220DECLARE_MSM_GPIO_PINS(42);
221DECLARE_MSM_GPIO_PINS(43);
222DECLARE_MSM_GPIO_PINS(44);
223DECLARE_MSM_GPIO_PINS(45);
224DECLARE_MSM_GPIO_PINS(46);
225DECLARE_MSM_GPIO_PINS(47);
226DECLARE_MSM_GPIO_PINS(48);
227DECLARE_MSM_GPIO_PINS(49);
228DECLARE_MSM_GPIO_PINS(50);
229DECLARE_MSM_GPIO_PINS(51);
230DECLARE_MSM_GPIO_PINS(52);
231DECLARE_MSM_GPIO_PINS(53);
232DECLARE_MSM_GPIO_PINS(54);
233DECLARE_MSM_GPIO_PINS(55);
234DECLARE_MSM_GPIO_PINS(56);
235DECLARE_MSM_GPIO_PINS(57);
236DECLARE_MSM_GPIO_PINS(58);
237DECLARE_MSM_GPIO_PINS(59);
238DECLARE_MSM_GPIO_PINS(60);
239DECLARE_MSM_GPIO_PINS(61);
240DECLARE_MSM_GPIO_PINS(62);
241DECLARE_MSM_GPIO_PINS(63);
242DECLARE_MSM_GPIO_PINS(64);
243DECLARE_MSM_GPIO_PINS(65);
244DECLARE_MSM_GPIO_PINS(66);
245DECLARE_MSM_GPIO_PINS(67);
246DECLARE_MSM_GPIO_PINS(68);
247DECLARE_MSM_GPIO_PINS(69);
248DECLARE_MSM_GPIO_PINS(70);
249DECLARE_MSM_GPIO_PINS(71);
250DECLARE_MSM_GPIO_PINS(72);
251DECLARE_MSM_GPIO_PINS(73);
252DECLARE_MSM_GPIO_PINS(74);
253DECLARE_MSM_GPIO_PINS(75);
254DECLARE_MSM_GPIO_PINS(76);
255DECLARE_MSM_GPIO_PINS(77);
256DECLARE_MSM_GPIO_PINS(78);
257DECLARE_MSM_GPIO_PINS(79);
258DECLARE_MSM_GPIO_PINS(80);
259DECLARE_MSM_GPIO_PINS(81);
260DECLARE_MSM_GPIO_PINS(82);
261DECLARE_MSM_GPIO_PINS(83);
262DECLARE_MSM_GPIO_PINS(84);
263DECLARE_MSM_GPIO_PINS(85);
264DECLARE_MSM_GPIO_PINS(86);
265DECLARE_MSM_GPIO_PINS(87);
266DECLARE_MSM_GPIO_PINS(88);
267DECLARE_MSM_GPIO_PINS(89);
268DECLARE_MSM_GPIO_PINS(90);
269DECLARE_MSM_GPIO_PINS(91);
270DECLARE_MSM_GPIO_PINS(92);
271DECLARE_MSM_GPIO_PINS(93);
272DECLARE_MSM_GPIO_PINS(94);
273DECLARE_MSM_GPIO_PINS(95);
274DECLARE_MSM_GPIO_PINS(96);
275DECLARE_MSM_GPIO_PINS(97);
276DECLARE_MSM_GPIO_PINS(98);
277DECLARE_MSM_GPIO_PINS(99);
278DECLARE_MSM_GPIO_PINS(100);
279DECLARE_MSM_GPIO_PINS(101);
280DECLARE_MSM_GPIO_PINS(102);
281DECLARE_MSM_GPIO_PINS(103);
282DECLARE_MSM_GPIO_PINS(104);
283DECLARE_MSM_GPIO_PINS(105);
284DECLARE_MSM_GPIO_PINS(106);
285DECLARE_MSM_GPIO_PINS(107);
286DECLARE_MSM_GPIO_PINS(108);
287DECLARE_MSM_GPIO_PINS(109);
288DECLARE_MSM_GPIO_PINS(110);
289DECLARE_MSM_GPIO_PINS(111);
290DECLARE_MSM_GPIO_PINS(112);
291DECLARE_MSM_GPIO_PINS(113);
292DECLARE_MSM_GPIO_PINS(114);
293DECLARE_MSM_GPIO_PINS(115);
294DECLARE_MSM_GPIO_PINS(116);
295DECLARE_MSM_GPIO_PINS(117);
296DECLARE_MSM_GPIO_PINS(118);
297DECLARE_MSM_GPIO_PINS(119);
298DECLARE_MSM_GPIO_PINS(120);
299DECLARE_MSM_GPIO_PINS(121);
300DECLARE_MSM_GPIO_PINS(122);
301DECLARE_MSM_GPIO_PINS(123);
302DECLARE_MSM_GPIO_PINS(124);
303DECLARE_MSM_GPIO_PINS(125);
304DECLARE_MSM_GPIO_PINS(126);
305DECLARE_MSM_GPIO_PINS(127);
306DECLARE_MSM_GPIO_PINS(128);
307DECLARE_MSM_GPIO_PINS(129);
308DECLARE_MSM_GPIO_PINS(130);
309DECLARE_MSM_GPIO_PINS(131);
310DECLARE_MSM_GPIO_PINS(132);
311DECLARE_MSM_GPIO_PINS(133);
312DECLARE_MSM_GPIO_PINS(134);
313DECLARE_MSM_GPIO_PINS(135);
314DECLARE_MSM_GPIO_PINS(136);
315DECLARE_MSM_GPIO_PINS(137);
316DECLARE_MSM_GPIO_PINS(138);
317DECLARE_MSM_GPIO_PINS(139);
318DECLARE_MSM_GPIO_PINS(140);
319DECLARE_MSM_GPIO_PINS(141);
320DECLARE_MSM_GPIO_PINS(142);
321DECLARE_MSM_GPIO_PINS(143);
322DECLARE_MSM_GPIO_PINS(144);
323DECLARE_MSM_GPIO_PINS(145);
324
325static const unsigned int sdc1_clk_pins[] = { 146 };
326static const unsigned int sdc1_cmd_pins[] = { 147 };
327static const unsigned int sdc1_data_pins[] = { 148 };
328static const unsigned int sdc2_clk_pins[] = { 149 };
329static const unsigned int sdc2_cmd_pins[] = { 150 };
330static const unsigned int sdc2_data_pins[] = { 151 };
331
332#define FUNCTION(fname) \
333 [MSM_MUX_##fname] = { \
334 .name = #fname, \
335 .groups = fname##_groups, \
336 .ngroups = ARRAY_SIZE(fname##_groups), \
337 }
338
339#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
340 { \
341 .name = "gpio" #id, \
342 .pins = gpio##id##_pins, \
343 .npins = ARRAY_SIZE(gpio##id##_pins), \
344 .funcs = (int[]){ \
345 MSM_MUX_gpio, \
346 MSM_MUX_##f1, \
347 MSM_MUX_##f2, \
348 MSM_MUX_##f3, \
349 MSM_MUX_##f4, \
350 MSM_MUX_##f5, \
351 MSM_MUX_##f6, \
352 MSM_MUX_##f7 \
353 }, \
354 .nfuncs = 8, \
355 .ctl_reg = 0x1000 + 0x10 * id, \
356 .io_reg = 0x1004 + 0x10 * id, \
357 .intr_cfg_reg = 0x1008 + 0x10 * id, \
358 .intr_status_reg = 0x100c + 0x10 * id, \
359 .intr_target_reg = 0x1008 + 0x10 * id, \
360 .mux_bit = 2, \
361 .pull_bit = 0, \
362 .drv_bit = 6, \
363 .oe_bit = 9, \
364 .in_bit = 0, \
365 .out_bit = 1, \
366 .intr_enable_bit = 0, \
367 .intr_status_bit = 0, \
368 .intr_target_bit = 5, \
369 .intr_raw_status_bit = 4, \
370 .intr_polarity_bit = 1, \
371 .intr_detection_bit = 2, \
372 .intr_detection_width = 2, \
373 }
374
375#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
376 { \
377 .name = #pg_name, \
378 .pins = pg_name##_pins, \
379 .npins = ARRAY_SIZE(pg_name##_pins), \
380 .ctl_reg = ctl, \
381 .io_reg = 0, \
382 .intr_cfg_reg = 0, \
383 .intr_status_reg = 0, \
384 .intr_target_reg = 0, \
385 .mux_bit = -1, \
386 .pull_bit = pull, \
387 .drv_bit = drv, \
388 .oe_bit = -1, \
389 .in_bit = -1, \
390 .out_bit = -1, \
391 .intr_enable_bit = -1, \
392 .intr_status_bit = -1, \
393 .intr_target_bit = -1, \
394 .intr_raw_status_bit = -1, \
395 .intr_polarity_bit = -1, \
396 .intr_detection_bit = -1, \
397 .intr_detection_width = -1, \
398 }
399
400/*
401 * TODO: Add the rest of the possible functions and fill out
402 * the pingroup table below.
403 */
404enum msm8x74_functions {
405 MSM_MUX_gpio,
406 MSM_MUX_cci_i2c0,
407 MSM_MUX_cci_i2c1,
408 MSM_MUX_blsp_i2c1,
409 MSM_MUX_blsp_i2c2,
410 MSM_MUX_blsp_i2c3,
411 MSM_MUX_blsp_i2c4,
412 MSM_MUX_blsp_i2c5,
413 MSM_MUX_blsp_i2c6,
414 MSM_MUX_blsp_i2c7,
415 MSM_MUX_blsp_i2c8,
416 MSM_MUX_blsp_i2c9,
417 MSM_MUX_blsp_i2c10,
418 MSM_MUX_blsp_i2c11,
419 MSM_MUX_blsp_i2c12,
420 MSM_MUX_blsp_spi1,
421 MSM_MUX_blsp_spi1_cs1,
422 MSM_MUX_blsp_spi1_cs2,
423 MSM_MUX_blsp_spi1_cs3,
424 MSM_MUX_blsp_spi2,
425 MSM_MUX_blsp_spi2_cs1,
426 MSM_MUX_blsp_spi2_cs2,
427 MSM_MUX_blsp_spi2_cs3,
428 MSM_MUX_blsp_spi3,
429 MSM_MUX_blsp_spi4,
430 MSM_MUX_blsp_spi5,
431 MSM_MUX_blsp_spi6,
432 MSM_MUX_blsp_spi7,
433 MSM_MUX_blsp_spi8,
434 MSM_MUX_blsp_spi9,
435 MSM_MUX_blsp_spi10,
436 MSM_MUX_blsp_spi10_cs1,
437 MSM_MUX_blsp_spi10_cs2,
438 MSM_MUX_blsp_spi10_cs3,
439 MSM_MUX_blsp_spi11,
440 MSM_MUX_blsp_spi12,
441 MSM_MUX_blsp_uart1,
442 MSM_MUX_blsp_uart2,
443 MSM_MUX_blsp_uart3,
444 MSM_MUX_blsp_uart4,
445 MSM_MUX_blsp_uart5,
446 MSM_MUX_blsp_uart6,
447 MSM_MUX_blsp_uart7,
448 MSM_MUX_blsp_uart8,
449 MSM_MUX_blsp_uart9,
450 MSM_MUX_blsp_uart10,
451 MSM_MUX_blsp_uart11,
452 MSM_MUX_blsp_uart12,
453 MSM_MUX_blsp_uim1,
454 MSM_MUX_blsp_uim2,
455 MSM_MUX_blsp_uim3,
456 MSM_MUX_blsp_uim4,
457 MSM_MUX_blsp_uim5,
458 MSM_MUX_blsp_uim6,
459 MSM_MUX_blsp_uim7,
460 MSM_MUX_blsp_uim8,
461 MSM_MUX_blsp_uim9,
462 MSM_MUX_blsp_uim10,
463 MSM_MUX_blsp_uim11,
464 MSM_MUX_blsp_uim12,
465 MSM_MUX_uim1,
466 MSM_MUX_uim2,
467 MSM_MUX_uim_batt_alarm,
468 MSM_MUX_sdc3,
469 MSM_MUX_sdc4,
470 MSM_MUX_gcc_gp_clk1,
471 MSM_MUX_gcc_gp_clk2,
472 MSM_MUX_gcc_gp_clk3,
473 MSM_MUX_qua_mi2s,
474 MSM_MUX_pri_mi2s,
475 MSM_MUX_spkr_mi2s,
476 MSM_MUX_ter_mi2s,
477 MSM_MUX_sec_mi2s,
478 MSM_MUX_hdmi_cec,
479 MSM_MUX_hdmi_ddc,
480 MSM_MUX_hdmi_hpd,
481 MSM_MUX_edp_hpd,
482 MSM_MUX_mdp_vsync,
483 MSM_MUX_cam_mclk0,
484 MSM_MUX_cam_mclk1,
485 MSM_MUX_cam_mclk2,
486 MSM_MUX_cam_mclk3,
487 MSM_MUX_cci_timer0,
488 MSM_MUX_cci_timer1,
489 MSM_MUX_cci_timer2,
490 MSM_MUX_cci_timer3,
491 MSM_MUX_cci_timer4,
492 MSM_MUX_cci_async_in0,
493 MSM_MUX_cci_async_in1,
494 MSM_MUX_cci_async_in2,
495 MSM_MUX_gp_pdm0,
496 MSM_MUX_gp_pdm1,
497 MSM_MUX_gp_pdm2,
498 MSM_MUX_gp0_clk,
499 MSM_MUX_gp1_clk,
500 MSM_MUX_gp_mn,
501 MSM_MUX_tsif1,
502 MSM_MUX_tsif2,
503 MSM_MUX_hsic,
504 MSM_MUX_grfc,
505 MSM_MUX_audio_ref_clk,
506 MSM_MUX_bt,
507 MSM_MUX_fm,
508 MSM_MUX_wlan,
509 MSM_MUX_slimbus,
510 MSM_MUX_NA,
511};
512
513static const char * const gpio_groups[] = {
514 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
515 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
516 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
517 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
518 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
519 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
520 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
521 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
522 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
523 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
524 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
525 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
526 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
527 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
528 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
529 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
530 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
531 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
532 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
533 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
534 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
535 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145"
536};
537
538static const char * const blsp_uart1_groups[] = {
539 "gpio0", "gpio1", "gpio2", "gpio3"
540};
541static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
542static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
543static const char * const blsp_spi1_groups[] = {
544 "gpio0", "gpio1", "gpio2", "gpio3"
545};
546static const char * const blsp_spi1_cs1_groups[] = { "gpio8" };
547static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" };
548static const char * const blsp_spi1_cs3_groups[] = { "gpio10" };
549
550static const char * const blsp_uart2_groups[] = {
551 "gpio4", "gpio5", "gpio6", "gpio7"
552};
553static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
554static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
555static const char * const blsp_spi2_groups[] = {
556 "gpio4", "gpio5", "gpio6", "gpio7"
557};
558static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" };
559static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" };
560static const char * const blsp_spi2_cs3_groups[] = { "gpio66" };
561
562static const char * const blsp_uart3_groups[] = {
563 "gpio8", "gpio9", "gpio10", "gpio11"
564};
565static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
566static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
567static const char * const blsp_spi3_groups[] = {
568 "gpio8", "gpio9", "gpio10", "gpio11"
569};
570
571static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" };
572static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" };
573
574static const char * const blsp_uart4_groups[] = {
575 "gpio19", "gpio20", "gpio21", "gpio22"
576};
577static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" };
578static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" };
579static const char * const blsp_spi4_groups[] = {
580 "gpio19", "gpio20", "gpio21", "gpio22"
581};
582
583static const char * const blsp_uart5_groups[] = {
584 "gpio23", "gpio24", "gpio25", "gpio26"
585};
586static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" };
587static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" };
588static const char * const blsp_spi5_groups[] = {
589 "gpio23", "gpio24", "gpio25", "gpio26"
590};
591
592static const char * const blsp_uart6_groups[] = {
593 "gpio27", "gpio28", "gpio29", "gpio30"
594};
595static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" };
596static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
597static const char * const blsp_spi6_groups[] = {
598 "gpio27", "gpio28", "gpio29", "gpio30"
599};
600
601static const char * const blsp_uart7_groups[] = {
602 "gpio41", "gpio42", "gpio43", "gpio44"
603};
604static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" };
605static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" };
606static const char * const blsp_spi7_groups[] = {
607 "gpio41", "gpio42", "gpio43", "gpio44"
608};
609
610static const char * const blsp_uart8_groups[] = {
611 "gpio45", "gpio46", "gpio47", "gpio48"
612};
613static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" };
614static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" };
615static const char * const blsp_spi8_groups[] = {
616 "gpio45", "gpio46", "gpio47", "gpio48"
617};
618
619static const char * const blsp_uart9_groups[] = {
620 "gpio49", "gpio50", "gpio51", "gpio52"
621};
622static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" };
623static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" };
624static const char * const blsp_spi9_groups[] = {
625 "gpio49", "gpio50", "gpio51", "gpio52"
626};
627
628static const char * const blsp_uart10_groups[] = {
629 "gpio53", "gpio54", "gpio55", "gpio56"
630};
631static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" };
632static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" };
633static const char * const blsp_spi10_groups[] = {
634 "gpio53", "gpio54", "gpio55", "gpio56"
635};
636static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" };
637static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" };
638static const char * const blsp_spi10_cs3_groups[] = { "gpio90" };
639
640static const char * const blsp_uart11_groups[] = {
641 "gpio81", "gpio82", "gpio83", "gpio84"
642};
643static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" };
644static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
645static const char * const blsp_spi11_groups[] = {
646 "gpio81", "gpio82", "gpio83", "gpio84"
647};
648
649static const char * const blsp_uart12_groups[] = {
650 "gpio85", "gpio86", "gpio87", "gpio88"
651};
652static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" };
653static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" };
654static const char * const blsp_spi12_groups[] = {
655 "gpio85", "gpio86", "gpio87", "gpio88"
656};
657
658static const char * const uim1_groups[] = {
659 "gpio97", "gpio98", "gpio99", "gpio100"
660};
661
662static const char * const uim2_groups[] = {
663 "gpio49", "gpio50", "gpio51", "gpio52"
664};
665
666static const char * const uim_batt_alarm_groups[] = { "gpio101" };
667
668static const char * const sdc3_groups[] = {
669 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
670};
671
672static const char * const sdc4_groups[] = {
673 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96"
674};
675
676static const char * const gp0_clk_groups[] = { "gpio26" };
677static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" };
678static const char * const gp_mn_groups[] = { "gpio29" };
679static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" };
680static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" };
681static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" };
682
683static const char * const qua_mi2s_groups[] = {
684 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
685};
686
687static const char * const pri_mi2s_groups[] = {
688 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
689};
690
691static const char * const spkr_mi2s_groups[] = {
692 "gpio69", "gpio70", "gpio71", "gpio72"
693};
694
695static const char * const ter_mi2s_groups[] = {
696 "gpio73", "gpio74", "gpio75", "gpio76", "gpio77"
697};
698
699static const char * const sec_mi2s_groups[] = {
700 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
701};
702
703static const char * const hdmi_cec_groups[] = { "gpio31" };
704static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" };
705static const char * const hdmi_hpd_groups[] = { "gpio34" };
706static const char * const edp_hpd_groups[] = { "gpio102" };
707
708static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" };
709static const char * const cam_mclk0_groups[] = { "gpio15" };
710static const char * const cam_mclk1_groups[] = { "gpio16" };
711static const char * const cam_mclk2_groups[] = { "gpio17" };
712static const char * const cam_mclk3_groups[] = { "gpio18" };
713
714static const char * const cci_timer0_groups[] = { "gpio23" };
715static const char * const cci_timer1_groups[] = { "gpio24" };
716static const char * const cci_timer2_groups[] = { "gpio25" };
717static const char * const cci_timer3_groups[] = { "gpio26" };
718static const char * const cci_timer4_groups[] = { "gpio27" };
719static const char * const cci_async_in0_groups[] = { "gpio28" };
720static const char * const cci_async_in1_groups[] = { "gpio26" };
721static const char * const cci_async_in2_groups[] = { "gpio27" };
722
723static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" };
724static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" };
725static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" };
726
727static const char * const tsif1_groups[] = {
728 "gpio89", "gpio90", "gpio91", "gpio92"
729};
730
731static const char * const tsif2_groups[] = {
732 "gpio93", "gpio94", "gpio95", "gpio96"
733};
734
735static const char * const hsic_groups[] = { "gpio144", "gpio145" };
736static const char * const grfc_groups[] = {
737 "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
738 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
739 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
740 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
741 "gpio128", "gpio136", "gpio137", "gpio141", "gpio143"
742};
743
744static const char * const audio_ref_clk_groups[] = { "gpio69" };
745
746static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" };
747
748static const char * const fm_groups[] = { "gpio41", "gpio42" };
749
750static const char * const wlan_groups[] = {
751 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
752};
753
754static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
755
756static const struct msm_function msm8x74_functions[] = {
757 FUNCTION(gpio),
758 FUNCTION(cci_i2c0),
759 FUNCTION(cci_i2c1),
760 FUNCTION(uim1),
761 FUNCTION(uim2),
762 FUNCTION(uim_batt_alarm),
763 FUNCTION(blsp_uim1),
764 FUNCTION(blsp_uim2),
765 FUNCTION(blsp_uim3),
766 FUNCTION(blsp_uim4),
767 FUNCTION(blsp_uim5),
768 FUNCTION(blsp_uim6),
769 FUNCTION(blsp_uim7),
770 FUNCTION(blsp_uim8),
771 FUNCTION(blsp_uim9),
772 FUNCTION(blsp_uim10),
773 FUNCTION(blsp_uim11),
774 FUNCTION(blsp_uim12),
775 FUNCTION(blsp_i2c1),
776 FUNCTION(blsp_i2c2),
777 FUNCTION(blsp_i2c3),
778 FUNCTION(blsp_i2c4),
779 FUNCTION(blsp_i2c5),
780 FUNCTION(blsp_i2c6),
781 FUNCTION(blsp_i2c7),
782 FUNCTION(blsp_i2c8),
783 FUNCTION(blsp_i2c9),
784 FUNCTION(blsp_i2c10),
785 FUNCTION(blsp_i2c11),
786 FUNCTION(blsp_i2c12),
787 FUNCTION(blsp_spi1),
788 FUNCTION(blsp_spi1_cs1),
789 FUNCTION(blsp_spi1_cs2),
790 FUNCTION(blsp_spi1_cs3),
791 FUNCTION(blsp_spi2),
792 FUNCTION(blsp_spi2_cs1),
793 FUNCTION(blsp_spi2_cs2),
794 FUNCTION(blsp_spi2_cs3),
795 FUNCTION(blsp_spi3),
796 FUNCTION(blsp_spi4),
797 FUNCTION(blsp_spi5),
798 FUNCTION(blsp_spi6),
799 FUNCTION(blsp_spi7),
800 FUNCTION(blsp_spi8),
801 FUNCTION(blsp_spi9),
802 FUNCTION(blsp_spi10),
803 FUNCTION(blsp_spi10_cs1),
804 FUNCTION(blsp_spi10_cs2),
805 FUNCTION(blsp_spi10_cs3),
806 FUNCTION(blsp_spi11),
807 FUNCTION(blsp_spi12),
808 FUNCTION(blsp_uart1),
809 FUNCTION(blsp_uart2),
810 FUNCTION(blsp_uart3),
811 FUNCTION(blsp_uart4),
812 FUNCTION(blsp_uart5),
813 FUNCTION(blsp_uart6),
814 FUNCTION(blsp_uart7),
815 FUNCTION(blsp_uart8),
816 FUNCTION(blsp_uart9),
817 FUNCTION(blsp_uart10),
818 FUNCTION(blsp_uart11),
819 FUNCTION(blsp_uart12),
820 FUNCTION(sdc3),
821 FUNCTION(sdc4),
822 FUNCTION(gcc_gp_clk1),
823 FUNCTION(gcc_gp_clk2),
824 FUNCTION(gcc_gp_clk3),
825 FUNCTION(qua_mi2s),
826 FUNCTION(pri_mi2s),
827 FUNCTION(spkr_mi2s),
828 FUNCTION(ter_mi2s),
829 FUNCTION(sec_mi2s),
830 FUNCTION(mdp_vsync),
831 FUNCTION(cam_mclk0),
832 FUNCTION(cam_mclk1),
833 FUNCTION(cam_mclk2),
834 FUNCTION(cam_mclk3),
835 FUNCTION(cci_timer0),
836 FUNCTION(cci_timer1),
837 FUNCTION(cci_timer2),
838 FUNCTION(cci_timer3),
839 FUNCTION(cci_timer4),
840 FUNCTION(cci_async_in0),
841 FUNCTION(cci_async_in1),
842 FUNCTION(cci_async_in2),
843 FUNCTION(hdmi_cec),
844 FUNCTION(hdmi_ddc),
845 FUNCTION(hdmi_hpd),
846 FUNCTION(edp_hpd),
847 FUNCTION(gp_pdm0),
848 FUNCTION(gp_pdm1),
849 FUNCTION(gp_pdm2),
850 FUNCTION(gp0_clk),
851 FUNCTION(gp1_clk),
852 FUNCTION(gp_mn),
853 FUNCTION(tsif1),
854 FUNCTION(tsif2),
855 FUNCTION(hsic),
856 FUNCTION(grfc),
857 FUNCTION(audio_ref_clk),
858 FUNCTION(bt),
859 FUNCTION(fm),
860 FUNCTION(wlan),
861 FUNCTION(slimbus),
862};
863
864static const struct msm_pingroup msm8x74_groups[] = {
865 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
866 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
867 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
868 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
869 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
870 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
871 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
872 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
873 PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA),
874 PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA),
875 PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA),
876 PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA),
877 PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
878 PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
879 PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
880 PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
881 PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
882 PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
883 PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
884 PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
885 PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
886 PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
887 PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
888 PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
889 PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
890 PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA),
891 PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA),
892 PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA),
893 PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA),
894 PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA),
895 PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
896 PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
897 PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
898 PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
899 PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA),
900 PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA),
901 PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA),
902 PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA),
903 PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA),
904 PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA),
905 PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA),
906 PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
907 PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
908 PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
909 PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
910 PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
911 PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
912 PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA),
913 PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA),
914 PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
915 PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
916 PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
917 PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
918 PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA),
919 PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA),
920 PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
921 PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
922 PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
923 PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA),
924 PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA),
925 PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA),
926 PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA),
927 PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA),
928 PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA),
929 PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA),
930 PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA),
931 PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA),
932 PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA),
933 PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA),
934 PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA),
935 PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
936 PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
937 PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA),
938 PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA),
939 PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA),
940 PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA),
941 PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA),
942 PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA),
943 PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
944 PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA),
945 PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA),
946 PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA),
947 PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA),
948 PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
949 PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
950 PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
951 PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA),
952 PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
953 PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
954 PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA),
955 PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA),
956 PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA),
957 PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA),
958 PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA),
959 PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA),
960 PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA),
961 PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA),
962 PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA),
963 PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA),
964 PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA),
965 PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA),
966 PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
967 PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA),
968 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
969 PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA),
970 PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA),
971 PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA),
972 PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA),
973 PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA),
974 PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA),
975 PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA),
976 PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA),
977 PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA),
978 PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA),
979 PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA),
980 PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA),
981 PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA),
982 PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA),
983 PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA),
984 PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA),
985 PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA),
986 PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA),
987 PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA),
988 PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA),
989 PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA),
990 PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA),
991 PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA),
992 PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA),
993 PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA),
994 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA),
995 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA),
996 PINGROUP(131, NA, NA, NA, NA, NA, NA, NA),
997 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA),
998 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA),
999 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA),
1000 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA),
1001 PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA),
1002 PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA),
1003 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
1004 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
1005 PINGROUP(140, NA, NA, NA, NA, NA, NA, NA),
1006 PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA),
1007 PINGROUP(142, NA, NA, NA, NA, NA, NA, NA),
1008 PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA),
1009 PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA),
1010 PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA),
1011 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
1012 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
1013 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
1014 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
1015 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
1016 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
1017};
1018
1019#define NUM_GPIO_PINGROUPS 146
1020
1021static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
1022 .pins = msm8x74_pins,
1023 .npins = ARRAY_SIZE(msm8x74_pins),
1024 .functions = msm8x74_functions,
1025 .nfunctions = ARRAY_SIZE(msm8x74_functions),
1026 .groups = msm8x74_groups,
1027 .ngroups = ARRAY_SIZE(msm8x74_groups),
1028 .ngpios = NUM_GPIO_PINGROUPS,
1029};
1030
1031static int msm8x74_pinctrl_probe(struct platform_device *pdev)
1032{
1033 return msm_pinctrl_probe(pdev, &msm8x74_pinctrl);
1034}
1035
1036static const struct of_device_id msm8x74_pinctrl_of_match[] = {
1037 { .compatible = "qcom,msm8974-pinctrl", },
1038 { },
1039};
1040
1041static struct platform_driver msm8x74_pinctrl_driver = {
1042 .driver = {
1043 .name = "msm8x74-pinctrl",
1044 .owner = THIS_MODULE,
1045 .of_match_table = msm8x74_pinctrl_of_match,
1046 },
1047 .probe = msm8x74_pinctrl_probe,
1048 .remove = msm_pinctrl_remove,
1049};
1050
1051static int __init msm8x74_pinctrl_init(void)
1052{
1053 return platform_driver_register(&msm8x74_pinctrl_driver);
1054}
1055arch_initcall(msm8x74_pinctrl_init);
1056
1057static void __exit msm8x74_pinctrl_exit(void)
1058{
1059 platform_driver_unregister(&msm8x74_pinctrl_driver);
1060}
1061module_exit(msm8x74_pinctrl_exit);
1062
1063MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1064MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");
1065MODULE_LICENSE("GPL v2");
1066MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
1067
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 19:55:43 -0500