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-rw-r--r--drivers/pci/pci.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index deb7fa9cc638..ea5e70486174 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3230,11 +3230,23 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3230 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 3230 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3231 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3231 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3232 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3232 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3233 msleep(100); 3233 /*
3234 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3235 * this to 2ms to ensure that we meet the minium requirement.
3236 */
3237 msleep(2);
3234 3238
3235 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 3239 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3236 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3240 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3237 msleep(100); 3241
3242 /*
3243 * Trhfa for conventional PCI is 2^25 clock cycles.
3244 * Assuming a minimum 33MHz clock this results in a 1s
3245 * delay before we can consider subordinate devices to
3246 * be re-initialized. PCIe has some ways to shorten this,
3247 * but we don't make use of them yet.
3248 */
3249 ssleep(1);
3238} 3250}
3239EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 3251EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3240 3252